1 /*
2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 */
30
31 #ifndef _SYS_EFX_REGS_PCI_H
32 #define _SYS_EFX_REGS_PCI_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 /*
39 * PC_VEND_ID_REG(16bit):
40 * Vendor ID register
41 */
42
43 #define PCR_AZ_VEND_ID_REG 0x00000000
44 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
45
46 #define PCRF_AZ_VEND_ID_LBN 0
47 #define PCRF_AZ_VEND_ID_WIDTH 16
48
49
50 /*
51 * PC_DEV_ID_REG(16bit):
52 * Device ID register
53 */
54
55 #define PCR_AZ_DEV_ID_REG 0x00000002
56 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
57
58 #define PCRF_AZ_DEV_ID_LBN 0
59 #define PCRF_AZ_DEV_ID_WIDTH 16
60
61
62 /*
63 * PC_CMD_REG(16bit):
64 * Command register
65 */
66
67 #define PCR_AZ_CMD_REG 0x00000004
68 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
69
70 #define PCRF_AZ_INTX_DIS_LBN 10
71 #define PCRF_AZ_INTX_DIS_WIDTH 1
72 #define PCRF_AZ_FB2B_EN_LBN 9
73 #define PCRF_AZ_FB2B_EN_WIDTH 1
74 #define PCRF_AZ_SERR_EN_LBN 8
75 #define PCRF_AZ_SERR_EN_WIDTH 1
76 #define PCRF_AZ_IDSEL_CTL_LBN 7
77 #define PCRF_AZ_IDSEL_CTL_WIDTH 1
78 #define PCRF_AZ_PERR_EN_LBN 6
79 #define PCRF_AZ_PERR_EN_WIDTH 1
80 #define PCRF_AZ_VGA_PAL_SNP_LBN 5
81 #define PCRF_AZ_VGA_PAL_SNP_WIDTH 1
82 #define PCRF_AZ_MWI_EN_LBN 4
83 #define PCRF_AZ_MWI_EN_WIDTH 1
84 #define PCRF_AZ_SPEC_CYC_LBN 3
85 #define PCRF_AZ_SPEC_CYC_WIDTH 1
86 #define PCRF_AZ_MST_EN_LBN 2
87 #define PCRF_AZ_MST_EN_WIDTH 1
88 #define PCRF_AZ_MEM_EN_LBN 1
89 #define PCRF_AZ_MEM_EN_WIDTH 1
90 #define PCRF_AZ_IO_EN_LBN 0
91 #define PCRF_AZ_IO_EN_WIDTH 1
92
93
94 /*
95 * PC_STAT_REG(16bit):
96 * Status register
97 */
98
99 #define PCR_AZ_STAT_REG 0x00000006
100 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
101
102 #define PCRF_AZ_DET_PERR_LBN 15
103 #define PCRF_AZ_DET_PERR_WIDTH 1
104 #define PCRF_AZ_SIG_SERR_LBN 14
105 #define PCRF_AZ_SIG_SERR_WIDTH 1
106 #define PCRF_AZ_GOT_MABRT_LBN 13
107 #define PCRF_AZ_GOT_MABRT_WIDTH 1
108 #define PCRF_AZ_GOT_TABRT_LBN 12
109 #define PCRF_AZ_GOT_TABRT_WIDTH 1
110 #define PCRF_AZ_SIG_TABRT_LBN 11
111 #define PCRF_AZ_SIG_TABRT_WIDTH 1
112 #define PCRF_AZ_DEVSEL_TIM_LBN 9
113 #define PCRF_AZ_DEVSEL_TIM_WIDTH 2
114 #define PCRF_AZ_MDAT_PERR_LBN 8
115 #define PCRF_AZ_MDAT_PERR_WIDTH 1
116 #define PCRF_AZ_FB2B_CAP_LBN 7
117 #define PCRF_AZ_FB2B_CAP_WIDTH 1
118 #define PCRF_AZ_66MHZ_CAP_LBN 5
119 #define PCRF_AZ_66MHZ_CAP_WIDTH 1
120 #define PCRF_AZ_CAP_LIST_LBN 4
121 #define PCRF_AZ_CAP_LIST_WIDTH 1
122 #define PCRF_AZ_INTX_STAT_LBN 3
123 #define PCRF_AZ_INTX_STAT_WIDTH 1
124
125
126 /*
127 * PC_REV_ID_REG(8bit):
128 * Class code & revision ID register
129 */
130
131 #define PCR_AZ_REV_ID_REG 0x00000008
132 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
133
134 #define PCRF_AZ_REV_ID_LBN 0
135 #define PCRF_AZ_REV_ID_WIDTH 8
136
137
138 /*
139 * PC_CC_REG(24bit):
140 * Class code register
141 */
142
143 #define PCR_AZ_CC_REG 0x00000009
144 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
145
146 #define PCRF_AZ_BASE_CC_LBN 16
147 #define PCRF_AZ_BASE_CC_WIDTH 8
148 #define PCRF_AZ_SUB_CC_LBN 8
149 #define PCRF_AZ_SUB_CC_WIDTH 8
150 #define PCRF_AZ_PROG_IF_LBN 0
151 #define PCRF_AZ_PROG_IF_WIDTH 8
152
153
154 /*
155 * PC_CACHE_LSIZE_REG(8bit):
156 * Cache line size
157 */
158
159 #define PCR_AZ_CACHE_LSIZE_REG 0x0000000c
160 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
161
162 #define PCRF_AZ_CACHE_LSIZE_LBN 0
163 #define PCRF_AZ_CACHE_LSIZE_WIDTH 8
164
165
166 /*
167 * PC_MST_LAT_REG(8bit):
168 * Master latency timer register
169 */
170
171 #define PCR_AZ_MST_LAT_REG 0x0000000d
172 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
173
174 #define PCRF_AZ_MST_LAT_LBN 0
175 #define PCRF_AZ_MST_LAT_WIDTH 8
176
177
178 /*
179 * PC_HDR_TYPE_REG(8bit):
180 * Header type register
181 */
182
183 #define PCR_AZ_HDR_TYPE_REG 0x0000000e
184 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
185
186 #define PCRF_AZ_MULT_FUNC_LBN 7
187 #define PCRF_AZ_MULT_FUNC_WIDTH 1
188 #define PCRF_AZ_TYPE_LBN 0
189 #define PCRF_AZ_TYPE_WIDTH 7
190
191
192 /*
193 * PC_BIST_REG(8bit):
194 * BIST register
195 */
196
197 #define PCR_AZ_BIST_REG 0x0000000f
198 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
199
200 #define PCRF_AZ_BIST_LBN 0
201 #define PCRF_AZ_BIST_WIDTH 8
202
203
204 /*
205 * PC_BAR0_REG(32bit):
206 * Primary function base address register 0
207 */
208
209 #define PCR_AZ_BAR0_REG 0x00000010
210 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
211
212 #define PCRF_AZ_BAR0_LBN 4
213 #define PCRF_AZ_BAR0_WIDTH 28
214 #define PCRF_AZ_BAR0_PREF_LBN 3
215 #define PCRF_AZ_BAR0_PREF_WIDTH 1
216 #define PCRF_AZ_BAR0_TYPE_LBN 1
217 #define PCRF_AZ_BAR0_TYPE_WIDTH 2
218 #define PCRF_AZ_BAR0_IOM_LBN 0
219 #define PCRF_AZ_BAR0_IOM_WIDTH 1
220
221
222 /*
223 * PC_BAR1_REG(32bit):
224 * Primary function base address register 1, BAR1 is not implemented so read only.
225 */
226
227 #define PCR_DZ_BAR1_REG 0x00000014
228 /* hunta0=pci_f0_config */
229
230 #define PCRF_DZ_BAR1_LBN 0
231 #define PCRF_DZ_BAR1_WIDTH 32
232
233
234 /*
235 * PC_BAR2_LO_REG(32bit):
236 * Primary function base address register 2 low bits
237 */
238
239 #define PCR_AZ_BAR2_LO_REG 0x00000018
240 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
241
242 #define PCRF_AZ_BAR2_LO_LBN 4
243 #define PCRF_AZ_BAR2_LO_WIDTH 28
244 #define PCRF_AZ_BAR2_PREF_LBN 3
245 #define PCRF_AZ_BAR2_PREF_WIDTH 1
246 #define PCRF_AZ_BAR2_TYPE_LBN 1
247 #define PCRF_AZ_BAR2_TYPE_WIDTH 2
248 #define PCRF_AZ_BAR2_IOM_LBN 0
249 #define PCRF_AZ_BAR2_IOM_WIDTH 1
250
251
252 /*
253 * PC_BAR2_HI_REG(32bit):
254 * Primary function base address register 2 high bits
255 */
256
257 #define PCR_AZ_BAR2_HI_REG 0x0000001c
258 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
259
260 #define PCRF_AZ_BAR2_HI_LBN 0
261 #define PCRF_AZ_BAR2_HI_WIDTH 32
262
263
264 /*
265 * PC_BAR4_LO_REG(32bit):
266 * Primary function base address register 2 low bits
267 */
268
269 #define PCR_CZ_BAR4_LO_REG 0x00000020
270 /* sienaa0,hunta0=pci_f0_config */
271
272 #define PCRF_CZ_BAR4_LO_LBN 4
273 #define PCRF_CZ_BAR4_LO_WIDTH 28
274 #define PCRF_CZ_BAR4_PREF_LBN 3
275 #define PCRF_CZ_BAR4_PREF_WIDTH 1
276 #define PCRF_CZ_BAR4_TYPE_LBN 1
277 #define PCRF_CZ_BAR4_TYPE_WIDTH 2
278 #define PCRF_CZ_BAR4_IOM_LBN 0
279 #define PCRF_CZ_BAR4_IOM_WIDTH 1
280
281
282 /*
283 * PC_BAR4_HI_REG(32bit):
284 * Primary function base address register 2 high bits
285 */
286
287 #define PCR_CZ_BAR4_HI_REG 0x00000024
288 /* sienaa0,hunta0=pci_f0_config */
289
290 #define PCRF_CZ_BAR4_HI_LBN 0
291 #define PCRF_CZ_BAR4_HI_WIDTH 32
292
293
294 /*
295 * PC_SS_VEND_ID_REG(16bit):
296 * Sub-system vendor ID register
297 */
298
299 #define PCR_AZ_SS_VEND_ID_REG 0x0000002c
300 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
301
302 #define PCRF_AZ_SS_VEND_ID_LBN 0
303 #define PCRF_AZ_SS_VEND_ID_WIDTH 16
304
305
306 /*
307 * PC_SS_ID_REG(16bit):
308 * Sub-system ID register
309 */
310
311 #define PCR_AZ_SS_ID_REG 0x0000002e
312 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
313
314 #define PCRF_AZ_SS_ID_LBN 0
315 #define PCRF_AZ_SS_ID_WIDTH 16
316
317
318 /*
319 * PC_EXPROM_BAR_REG(32bit):
320 * Expansion ROM base address register
321 */
322
323 #define PCR_AZ_EXPROM_BAR_REG 0x00000030
324 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
325
326 #define PCRF_AZ_EXPROM_BAR_LBN 11
327 #define PCRF_AZ_EXPROM_BAR_WIDTH 21
328 #define PCRF_AB_EXPROM_MIN_SIZE_LBN 2
329 #define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9
330 #define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1
331 #define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10
332 #define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1
333 #define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1
334 #define PCRF_AZ_EXPROM_EN_LBN 0
335 #define PCRF_AZ_EXPROM_EN_WIDTH 1
336
337
338 /*
339 * PC_CAP_PTR_REG(8bit):
340 * Capability pointer register
341 */
342
343 #define PCR_AZ_CAP_PTR_REG 0x00000034
344 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
345
346 #define PCRF_AZ_CAP_PTR_LBN 0
347 #define PCRF_AZ_CAP_PTR_WIDTH 8
348
349
350 /*
351 * PC_INT_LINE_REG(8bit):
352 * Interrupt line register
353 */
354
355 #define PCR_AZ_INT_LINE_REG 0x0000003c
356 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
357
358 #define PCRF_AZ_INT_LINE_LBN 0
359 #define PCRF_AZ_INT_LINE_WIDTH 8
360
361
362 /*
363 * PC_INT_PIN_REG(8bit):
364 * Interrupt pin register
365 */
366
367 #define PCR_AZ_INT_PIN_REG 0x0000003d
368 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
369
370 #define PCRF_AZ_INT_PIN_LBN 0
371 #define PCRF_AZ_INT_PIN_WIDTH 8
372 #define PCFE_DZ_INTPIN_INTD 4
373 #define PCFE_DZ_INTPIN_INTC 3
374 #define PCFE_DZ_INTPIN_INTB 2
375 #define PCFE_DZ_INTPIN_INTA 1
376
377
378 /*
379 * PC_PM_CAP_ID_REG(8bit):
380 * Power management capability ID
381 */
382
383 #define PCR_AZ_PM_CAP_ID_REG 0x00000040
384 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
385
386 #define PCRF_AZ_PM_CAP_ID_LBN 0
387 #define PCRF_AZ_PM_CAP_ID_WIDTH 8
388
389
390 /*
391 * PC_PM_NXT_PTR_REG(8bit):
392 * Power management next item pointer
393 */
394
395 #define PCR_AZ_PM_NXT_PTR_REG 0x00000041
396 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
397
398 #define PCRF_AZ_PM_NXT_PTR_LBN 0
399 #define PCRF_AZ_PM_NXT_PTR_WIDTH 8
400
401
402 /*
403 * PC_PM_CAP_REG(16bit):
404 * Power management capabilities register
405 */
406
407 #define PCR_AZ_PM_CAP_REG 0x00000042
408 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
409
410 #define PCRF_AZ_PM_PME_SUPT_LBN 11
411 #define PCRF_AZ_PM_PME_SUPT_WIDTH 5
412 #define PCRF_AZ_PM_D2_SUPT_LBN 10
413 #define PCRF_AZ_PM_D2_SUPT_WIDTH 1
414 #define PCRF_AZ_PM_D1_SUPT_LBN 9
415 #define PCRF_AZ_PM_D1_SUPT_WIDTH 1
416 #define PCRF_AZ_PM_AUX_CURR_LBN 6
417 #define PCRF_AZ_PM_AUX_CURR_WIDTH 3
418 #define PCRF_AZ_PM_DSI_LBN 5
419 #define PCRF_AZ_PM_DSI_WIDTH 1
420 #define PCRF_AZ_PM_PME_CLK_LBN 3
421 #define PCRF_AZ_PM_PME_CLK_WIDTH 1
422 #define PCRF_AZ_PM_PME_VER_LBN 0
423 #define PCRF_AZ_PM_PME_VER_WIDTH 3
424
425
426 /*
427 * PC_PM_CS_REG(16bit):
428 * Power management control & status register
429 */
430
431 #define PCR_AZ_PM_CS_REG 0x00000044
432 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
433
434 #define PCRF_AZ_PM_PME_STAT_LBN 15
435 #define PCRF_AZ_PM_PME_STAT_WIDTH 1
436 #define PCRF_AZ_PM_DAT_SCALE_LBN 13
437 #define PCRF_AZ_PM_DAT_SCALE_WIDTH 2
438 #define PCRF_AZ_PM_DAT_SEL_LBN 9
439 #define PCRF_AZ_PM_DAT_SEL_WIDTH 4
440 #define PCRF_AZ_PM_PME_EN_LBN 8
441 #define PCRF_AZ_PM_PME_EN_WIDTH 1
442 #define PCRF_CZ_NO_SOFT_RESET_LBN 3
443 #define PCRF_CZ_NO_SOFT_RESET_WIDTH 1
444 #define PCRF_AZ_PM_PWR_ST_LBN 0
445 #define PCRF_AZ_PM_PWR_ST_WIDTH 2
446
447
448 /*
449 * PC_MSI_CAP_ID_REG(8bit):
450 * MSI capability ID
451 */
452
453 #define PCR_AZ_MSI_CAP_ID_REG 0x00000050
454 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
455
456 #define PCRF_AZ_MSI_CAP_ID_LBN 0
457 #define PCRF_AZ_MSI_CAP_ID_WIDTH 8
458
459
460 /*
461 * PC_MSI_NXT_PTR_REG(8bit):
462 * MSI next item pointer
463 */
464
465 #define PCR_AZ_MSI_NXT_PTR_REG 0x00000051
466 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
467
468 #define PCRF_AZ_MSI_NXT_PTR_LBN 0
469 #define PCRF_AZ_MSI_NXT_PTR_WIDTH 8
470
471
472 /*
473 * PC_MSI_CTL_REG(16bit):
474 * MSI control register
475 */
476
477 #define PCR_AZ_MSI_CTL_REG 0x00000052
478 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
479
480 #define PCRF_AZ_MSI_64_EN_LBN 7
481 #define PCRF_AZ_MSI_64_EN_WIDTH 1
482 #define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4
483 #define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3
484 #define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1
485 #define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3
486 #define PCRF_AZ_MSI_EN_LBN 0
487 #define PCRF_AZ_MSI_EN_WIDTH 1
488
489
490 /*
491 * PC_MSI_ADR_LO_REG(32bit):
492 * MSI low 32 bits address register
493 */
494
495 #define PCR_AZ_MSI_ADR_LO_REG 0x00000054
496 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
497
498 #define PCRF_AZ_MSI_ADR_LO_LBN 2
499 #define PCRF_AZ_MSI_ADR_LO_WIDTH 30
500
501
502 /*
503 * PC_MSI_ADR_HI_REG(32bit):
504 * MSI high 32 bits address register
505 */
506
507 #define PCR_AZ_MSI_ADR_HI_REG 0x00000058
508 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
509
510 #define PCRF_AZ_MSI_ADR_HI_LBN 0
511 #define PCRF_AZ_MSI_ADR_HI_WIDTH 32
512
513
514 /*
515 * PC_MSI_DAT_REG(16bit):
516 * MSI data register
517 */
518
519 #define PCR_AZ_MSI_DAT_REG 0x0000005c
520 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
521
522 #define PCRF_AZ_MSI_DAT_LBN 0
523 #define PCRF_AZ_MSI_DAT_WIDTH 16
524
525
526 /*
527 * PC_PCIE_CAP_LIST_REG(16bit):
528 * PCIe capability list register
529 */
530
531 #define PCR_AB_PCIE_CAP_LIST_REG 0x00000060
532 /* falcona0,falconb0=pci_f0_config */
533
534 #define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070
535 /* sienaa0,hunta0=pci_f0_config */
536
537 #define PCRF_AZ_PCIE_NXT_PTR_LBN 8
538 #define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8
539 #define PCRF_AZ_PCIE_CAP_ID_LBN 0
540 #define PCRF_AZ_PCIE_CAP_ID_WIDTH 8
541
542
543 /*
544 * PC_PCIE_CAP_REG(16bit):
545 * PCIe capability register
546 */
547
548 #define PCR_AB_PCIE_CAP_REG 0x00000062
549 /* falcona0,falconb0=pci_f0_config */
550
551 #define PCR_CZ_PCIE_CAP_REG 0x00000072
552 /* sienaa0,hunta0=pci_f0_config */
553
554 #define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9
555 #define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5
556 #define PCRF_AZ_PCIE_SLOT_IMP_LBN 8
557 #define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1
558 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4
559 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4
560 #define PCRF_AZ_PCIE_CAP_VER_LBN 0
561 #define PCRF_AZ_PCIE_CAP_VER_WIDTH 4
562
563
564 /*
565 * PC_DEV_CAP_REG(32bit):
566 * PCIe device capabilities register
567 */
568
569 #define PCR_AB_DEV_CAP_REG 0x00000064
570 /* falcona0,falconb0=pci_f0_config */
571
572 #define PCR_CZ_DEV_CAP_REG 0x00000074
573 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
574
575 #define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28
576 #define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1
577 #define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26
578 #define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2
579 #define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18
580 #define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8
581 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15
582 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1
583 #define PCRF_AB_PWR_IND_LBN 14
584 #define PCRF_AB_PWR_IND_WIDTH 1
585 #define PCRF_AB_ATTN_IND_LBN 13
586 #define PCRF_AB_ATTN_IND_WIDTH 1
587 #define PCRF_AB_ATTN_BUTTON_LBN 12
588 #define PCRF_AB_ATTN_BUTTON_WIDTH 1
589 #define PCRF_AZ_ENDPT_L1_LAT_LBN 9
590 #define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3
591 #define PCRF_AZ_ENDPT_L0_LAT_LBN 6
592 #define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3
593 #define PCRF_AZ_TAG_FIELD_LBN 5
594 #define PCRF_AZ_TAG_FIELD_WIDTH 1
595 #define PCRF_AZ_PHAN_FUNC_LBN 3
596 #define PCRF_AZ_PHAN_FUNC_WIDTH 2
597 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0
598 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3
599
600
601 /*
602 * PC_DEV_CTL_REG(16bit):
603 * PCIe device control register
604 */
605
606 #define PCR_AB_DEV_CTL_REG 0x00000068
607 /* falcona0,falconb0=pci_f0_config */
608
609 #define PCR_CZ_DEV_CTL_REG 0x00000078
610 /* sienaa0,hunta0=pci_f0_config */
611
612 #define PCRF_CZ_FN_LEVEL_RESET_LBN 15
613 #define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1
614 #define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12
615 #define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3
616 #define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5
617 #define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4
618 #define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3
619 #define PCFE_AZ_MAX_RD_REQ_SIZE_512 2
620 #define PCFE_AZ_MAX_RD_REQ_SIZE_256 1
621 #define PCFE_AZ_MAX_RD_REQ_SIZE_128 0
622 #define PCRF_AZ_EN_NO_SNOOP_LBN 11
623 #define PCRF_AZ_EN_NO_SNOOP_WIDTH 1
624 #define PCRF_AZ_AUX_PWR_PM_EN_LBN 10
625 #define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1
626 #define PCRF_AZ_PHAN_FUNC_EN_LBN 9
627 #define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1
628 #define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8
629 #define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1
630 #define PCRF_CZ_EXTENDED_TAG_EN_LBN 8
631 #define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1
632 #define PCRF_AZ_MAX_PAYL_SIZE_LBN 5
633 #define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3
634 #define PCFE_AZ_MAX_PAYL_SIZE_4096 5
635 #define PCFE_AZ_MAX_PAYL_SIZE_2048 4
636 #define PCFE_AZ_MAX_PAYL_SIZE_1024 3
637 #define PCFE_AZ_MAX_PAYL_SIZE_512 2
638 #define PCFE_AZ_MAX_PAYL_SIZE_256 1
639 #define PCFE_AZ_MAX_PAYL_SIZE_128 0
640 #define PCRF_AZ_EN_RELAX_ORDER_LBN 4
641 #define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1
642 #define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3
643 #define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1
644 #define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2
645 #define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1
646 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1
647 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1
648 #define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0
649 #define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1
650
651
652 /*
653 * PC_DEV_STAT_REG(16bit):
654 * PCIe device status register
655 */
656
657 #define PCR_AB_DEV_STAT_REG 0x0000006a
658 /* falcona0,falconb0=pci_f0_config */
659
660 #define PCR_CZ_DEV_STAT_REG 0x0000007a
661 /* sienaa0,hunta0=pci_f0_config */
662
663 #define PCRF_AZ_TRNS_PEND_LBN 5
664 #define PCRF_AZ_TRNS_PEND_WIDTH 1
665 #define PCRF_AZ_AUX_PWR_DET_LBN 4
666 #define PCRF_AZ_AUX_PWR_DET_WIDTH 1
667 #define PCRF_AZ_UNSUP_REQ_DET_LBN 3
668 #define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1
669 #define PCRF_AZ_FATAL_ERR_DET_LBN 2
670 #define PCRF_AZ_FATAL_ERR_DET_WIDTH 1
671 #define PCRF_AZ_NONFATAL_ERR_DET_LBN 1
672 #define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1
673 #define PCRF_AZ_CORR_ERR_DET_LBN 0
674 #define PCRF_AZ_CORR_ERR_DET_WIDTH 1
675
676
677 /*
678 * PC_LNK_CAP_REG(32bit):
679 * PCIe link capabilities register
680 */
681
682 #define PCR_AB_LNK_CAP_REG 0x0000006c
683 /* falcona0,falconb0=pci_f0_config */
684
685 #define PCR_CZ_LNK_CAP_REG 0x0000007c
686 /* sienaa0,hunta0=pci_f0_config */
687
688 #define PCRF_AZ_PORT_NUM_LBN 24
689 #define PCRF_AZ_PORT_NUM_WIDTH 8
690 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22
691 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1
692 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21
693 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1
694 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20
695 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1
696 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19
697 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1
698 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18
699 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1
700 #define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15
701 #define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3
702 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12
703 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3
704 #define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10
705 #define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2
706 #define PCRF_AZ_MAX_LNK_WIDTH_LBN 4
707 #define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6
708 #define PCRF_AZ_MAX_LNK_SP_LBN 0
709 #define PCRF_AZ_MAX_LNK_SP_WIDTH 4
710
711
712 /*
713 * PC_LNK_CTL_REG(16bit):
714 * PCIe link control register
715 */
716
717 #define PCR_AB_LNK_CTL_REG 0x00000070
718 /* falcona0,falconb0=pci_f0_config */
719
720 #define PCR_CZ_LNK_CTL_REG 0x00000080
721 /* sienaa0,hunta0=pci_f0_config */
722
723 #define PCRF_AZ_EXT_SYNC_LBN 7
724 #define PCRF_AZ_EXT_SYNC_WIDTH 1
725 #define PCRF_AZ_COMM_CLK_CFG_LBN 6
726 #define PCRF_AZ_COMM_CLK_CFG_WIDTH 1
727 #define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5
728 #define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1
729 #define PCRF_CZ_LNK_RETRAIN_LBN 5
730 #define PCRF_CZ_LNK_RETRAIN_WIDTH 1
731 #define PCRF_AZ_LNK_DIS_LBN 4
732 #define PCRF_AZ_LNK_DIS_WIDTH 1
733 #define PCRF_AZ_RD_COM_BDRY_LBN 3
734 #define PCRF_AZ_RD_COM_BDRY_WIDTH 1
735 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0
736 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2
737
738
739 /*
740 * PC_LNK_STAT_REG(16bit):
741 * PCIe link status register
742 */
743
744 #define PCR_AB_LNK_STAT_REG 0x00000072
745 /* falcona0,falconb0=pci_f0_config */
746
747 #define PCR_CZ_LNK_STAT_REG 0x00000082
748 /* sienaa0,hunta0=pci_f0_config */
749
750 #define PCRF_AZ_SLOT_CLK_CFG_LBN 12
751 #define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1
752 #define PCRF_AZ_LNK_TRAIN_LBN 11
753 #define PCRF_AZ_LNK_TRAIN_WIDTH 1
754 #define PCRF_AB_TRAIN_ERR_LBN 10
755 #define PCRF_AB_TRAIN_ERR_WIDTH 1
756 #define PCRF_AZ_LNK_WIDTH_LBN 4
757 #define PCRF_AZ_LNK_WIDTH_WIDTH 6
758 #define PCRF_AZ_LNK_SP_LBN 0
759 #define PCRF_AZ_LNK_SP_WIDTH 4
760
761
762 /*
763 * PC_SLOT_CAP_REG(32bit):
764 * PCIe slot capabilities register
765 */
766
767 #define PCR_AB_SLOT_CAP_REG 0x00000074
768 /* falcona0,falconb0=pci_f0_config */
769
770 #define PCRF_AB_SLOT_NUM_LBN 19
771 #define PCRF_AB_SLOT_NUM_WIDTH 13
772 #define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15
773 #define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2
774 #define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7
775 #define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8
776 #define PCRF_AB_SLOT_HP_CAP_LBN 6
777 #define PCRF_AB_SLOT_HP_CAP_WIDTH 1
778 #define PCRF_AB_SLOT_HP_SURP_LBN 5
779 #define PCRF_AB_SLOT_HP_SURP_WIDTH 1
780 #define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4
781 #define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1
782 #define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3
783 #define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1
784 #define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2
785 #define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1
786 #define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1
787 #define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1
788 #define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0
789 #define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1
790
791
792 /*
793 * PC_SLOT_CTL_REG(16bit):
794 * PCIe slot control register
795 */
796
797 #define PCR_AB_SLOT_CTL_REG 0x00000078
798 /* falcona0,falconb0=pci_f0_config */
799
800 #define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10
801 #define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1
802 #define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8
803 #define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2
804 #define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6
805 #define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2
806 #define PCRF_AB_SLOT_HP_INT_EN_LBN 5
807 #define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1
808 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4
809 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1
810 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3
811 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1
812 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2
813 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1
814 #define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1
815 #define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1
816 #define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0
817 #define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1
818
819
820 /*
821 * PC_SLOT_STAT_REG(16bit):
822 * PCIe slot status register
823 */
824
825 #define PCR_AB_SLOT_STAT_REG 0x0000007a
826 /* falcona0,falconb0=pci_f0_config */
827
828 #define PCRF_AB_PRES_DET_ST_LBN 6
829 #define PCRF_AB_PRES_DET_ST_WIDTH 1
830 #define PCRF_AB_MRL_SENS_ST_LBN 5
831 #define PCRF_AB_MRL_SENS_ST_WIDTH 1
832 #define PCRF_AB_SLOT_PWR_IND_LBN 4
833 #define PCRF_AB_SLOT_PWR_IND_WIDTH 1
834 #define PCRF_AB_SLOT_ATTN_IND_LBN 3
835 #define PCRF_AB_SLOT_ATTN_IND_WIDTH 1
836 #define PCRF_AB_SLOT_MRL_SENS_LBN 2
837 #define PCRF_AB_SLOT_MRL_SENS_WIDTH 1
838 #define PCRF_AB_PWR_FLTDET_LBN 1
839 #define PCRF_AB_PWR_FLTDET_WIDTH 1
840 #define PCRF_AB_ATTN_BUTDET_LBN 0
841 #define PCRF_AB_ATTN_BUTDET_WIDTH 1
842
843
844 /*
845 * PC_MSIX_CAP_ID_REG(8bit):
846 * MSIX Capability ID
847 */
848
849 #define PCR_BB_MSIX_CAP_ID_REG 0x00000090
850 /* falconb0=pci_f0_config */
851
852 #define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0
853 /* sienaa0,hunta0=pci_f0_config */
854
855 #define PCRF_BZ_MSIX_CAP_ID_LBN 0
856 #define PCRF_BZ_MSIX_CAP_ID_WIDTH 8
857
858
859 /*
860 * PC_MSIX_NXT_PTR_REG(8bit):
861 * MSIX Capability Next Capability Ptr
862 */
863
864 #define PCR_BB_MSIX_NXT_PTR_REG 0x00000091
865 /* falconb0=pci_f0_config */
866
867 #define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1
868 /* sienaa0,hunta0=pci_f0_config */
869
870 #define PCRF_BZ_MSIX_NXT_PTR_LBN 0
871 #define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8
872
873
874 /*
875 * PC_MSIX_CTL_REG(16bit):
876 * MSIX control register
877 */
878
879 #define PCR_BB_MSIX_CTL_REG 0x00000092
880 /* falconb0=pci_f0_config */
881
882 #define PCR_CZ_MSIX_CTL_REG 0x000000b2
883 /* sienaa0,hunta0=pci_f0_config */
884
885 #define PCRF_BZ_MSIX_EN_LBN 15
886 #define PCRF_BZ_MSIX_EN_WIDTH 1
887 #define PCRF_BZ_MSIX_FUNC_MASK_LBN 14
888 #define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1
889 #define PCRF_BZ_MSIX_TBL_SIZE_LBN 0
890 #define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11
891
892
893 /*
894 * PC_MSIX_TBL_BASE_REG(32bit):
895 * MSIX Capability Vector Table Base
896 */
897
898 #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094
899 /* falconb0=pci_f0_config */
900
901 #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
902 /* sienaa0,hunta0=pci_f0_config */
903
904 #define PCRF_BZ_MSIX_TBL_OFF_LBN 3
905 #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
906 #define PCRF_BZ_MSIX_TBL_BIR_LBN 0
907 #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
908
909
910 /*
911 * PC_DEV_CAP2_REG(32bit):
912 * PCIe Device Capabilities 2
913 */
914
915 #define PCR_CZ_DEV_CAP2_REG 0x00000094
916 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
917
918 #define PCRF_DZ_OBFF_SUPPORTED_LBN 18
919 #define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2
920 #define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12
921 #define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2
922 #define PCRF_DZ_LTR_M_SUPPORTED_LBN 11
923 #define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1
924 #define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4
925 #define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1
926 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4
927 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1
928 #define PCRF_CZ_CMPL_TIMEOUT_LBN 0
929 #define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4
930 #define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14
931 #define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13
932 #define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10
933 #define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9
934 #define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6
935 #define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5
936 #define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2
937 #define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1
938 #define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0
939
940
941 /*
942 * PC_DEV_CTL2_REG(16bit):
943 * PCIe Device Control 2
944 */
945
946 #define PCR_CZ_DEV_CTL2_REG 0x00000098
947 /* sienaa0,hunta0=pci_f0_config */
948
949 #define PCRF_DZ_OBFF_ENABLE_LBN 13
950 #define PCRF_DZ_OBFF_ENABLE_WIDTH 2
951 #define PCRF_DZ_LTR_ENABLE_LBN 10
952 #define PCRF_DZ_LTR_ENABLE_WIDTH 1
953 #define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9
954 #define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1
955 #define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8
956 #define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1
957 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4
958 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1
959 #define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0
960 #define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4
961
962
963 /*
964 * PC_MSIX_PBA_BASE_REG(32bit):
965 * MSIX Capability PBA Base
966 */
967
968 #define PCR_BB_MSIX_PBA_BASE_REG 0x00000098
969 /* falconb0=pci_f0_config */
970
971 #define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8
972 /* sienaa0,hunta0=pci_f0_config */
973
974 #define PCRF_BZ_MSIX_PBA_OFF_LBN 3
975 #define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29
976 #define PCRF_BZ_MSIX_PBA_BIR_LBN 0
977 #define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3
978
979
980 /*
981 * PC_LNK_CAP2_REG(32bit):
982 * PCIe Link Capability 2
983 */
984
985 #define PCR_DZ_LNK_CAP2_REG 0x0000009c
986 /* hunta0=pci_f0_config */
987
988 #define PCRF_DZ_LNK_SPEED_SUP_LBN 1
989 #define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7
990
991
992 /*
993 * PC_LNK_CTL2_REG(16bit):
994 * PCIe Link Control 2
995 */
996
997 #define PCR_CZ_LNK_CTL2_REG 0x000000a0
998 /* sienaa0,hunta0=pci_f0_config */
999
1000 #define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12
1001 #define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1
1002 #define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11
1003 #define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1
1004 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10
1005 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1
1006 #define PCRF_CZ_TRANSMIT_MARGIN_LBN 7
1007 #define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3
1008 #define PCRF_CZ_SELECT_DEEMPH_LBN 6
1009 #define PCRF_CZ_SELECT_DEEMPH_WIDTH 1
1010 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5
1011 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1
1012 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4
1013 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1
1014 #define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0
1015 #define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4
1016 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3
1017 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2
1018 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1
1019
1020
1021 /*
1022 * PC_LNK_STAT2_REG(16bit):
1023 * PCIe Link Status 2
1024 */
1025
1026 #define PCR_CZ_LNK_STAT2_REG 0x000000a2
1027 /* sienaa0,hunta0=pci_f0_config */
1028
1029 #define PCRF_CZ_CURRENT_DEEMPH_LBN 0
1030 #define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1
1031
1032
1033 /*
1034 * PC_VPD_CAP_ID_REG(8bit):
1035 * VPD data register
1036 */
1037
1038 #define PCR_AB_VPD_CAP_ID_REG 0x000000b0
1039 /* falcona0,falconb0=pci_f0_config */
1040
1041 #define PCRF_AB_VPD_CAP_ID_LBN 0
1042 #define PCRF_AB_VPD_CAP_ID_WIDTH 8
1043
1044
1045 /*
1046 * PC_VPD_NXT_PTR_REG(8bit):
1047 * VPD next item pointer
1048 */
1049
1050 #define PCR_AB_VPD_NXT_PTR_REG 0x000000b1
1051 /* falcona0,falconb0=pci_f0_config */
1052
1053 #define PCRF_AB_VPD_NXT_PTR_LBN 0
1054 #define PCRF_AB_VPD_NXT_PTR_WIDTH 8
1055
1056
1057 /*
1058 * PC_VPD_ADDR_REG(16bit):
1059 * VPD address register
1060 */
1061
1062 #define PCR_AB_VPD_ADDR_REG 0x000000b2
1063 /* falcona0,falconb0=pci_f0_config */
1064
1065 #define PCRF_AB_VPD_FLAG_LBN 15
1066 #define PCRF_AB_VPD_FLAG_WIDTH 1
1067 #define PCRF_AB_VPD_ADDR_LBN 0
1068 #define PCRF_AB_VPD_ADDR_WIDTH 15
1069
1070
1071 /*
1072 * PC_VPD_CAP_DATA_REG(32bit):
1073 * documentation to be written for sum_PC_VPD_CAP_DATA_REG
1074 */
1075
1076 #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4
1077 /* falcona0,falconb0=pci_f0_config */
1078
1079 #define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4
1080 /* sienaa0,hunta0=pci_f0_config */
1081
1082 #define PCRF_AZ_VPD_DATA_LBN 0
1083 #define PCRF_AZ_VPD_DATA_WIDTH 32
1084
1085
1086 /*
1087 * PC_VPD_CAP_CTL_REG(8bit):
1088 * VPD control and capabilities register
1089 */
1090
1091 #define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0
1092 /* sienaa0,hunta0=pci_f0_config */
1093
1094 #define PCRF_CZ_VPD_FLAG_LBN 31
1095 #define PCRF_CZ_VPD_FLAG_WIDTH 1
1096 #define PCRF_CZ_VPD_ADDR_LBN 16
1097 #define PCRF_CZ_VPD_ADDR_WIDTH 15
1098 #define PCRF_CZ_VPD_NXT_PTR_LBN 8
1099 #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8
1100 #define PCRF_CZ_VPD_CAP_ID_LBN 0
1101 #define PCRF_CZ_VPD_CAP_ID_WIDTH 8
1102
1103
1104 /*
1105 * PC_AER_CAP_HDR_REG(32bit):
1106 * AER capability header register
1107 */
1108
1109 #define PCR_AZ_AER_CAP_HDR_REG 0x00000100
1110 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1111
1112 #define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20
1113 #define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12
1114 #define PCRF_AZ_AERCAPHDR_VER_LBN 16
1115 #define PCRF_AZ_AERCAPHDR_VER_WIDTH 4
1116 #define PCRF_AZ_AERCAPHDR_ID_LBN 0
1117 #define PCRF_AZ_AERCAPHDR_ID_WIDTH 16
1118
1119
1120 /*
1121 * PC_AER_UNCORR_ERR_STAT_REG(32bit):
1122 * AER Uncorrectable error status register
1123 */
1124
1125 #define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104
1126 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1127
1128 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20
1129 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1
1130 #define PCRF_AZ_ECRC_ERR_STAT_LBN 19
1131 #define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1
1132 #define PCRF_AZ_MALF_TLP_STAT_LBN 18
1133 #define PCRF_AZ_MALF_TLP_STAT_WIDTH 1
1134 #define PCRF_AZ_RX_OVF_STAT_LBN 17
1135 #define PCRF_AZ_RX_OVF_STAT_WIDTH 1
1136 #define PCRF_AZ_UNEXP_COMP_STAT_LBN 16
1137 #define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1
1138 #define PCRF_AZ_COMP_ABRT_STAT_LBN 15
1139 #define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1
1140 #define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14
1141 #define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1
1142 #define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13
1143 #define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1
1144 #define PCRF_AZ_PSON_TLP_STAT_LBN 12
1145 #define PCRF_AZ_PSON_TLP_STAT_WIDTH 1
1146 #define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4
1147 #define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1
1148 #define PCRF_AB_TRAIN_ERR_STAT_LBN 0
1149 #define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1
1150
1151
1152 /*
1153 * PC_AER_UNCORR_ERR_MASK_REG(32bit):
1154 * AER Uncorrectable error mask register
1155 */
1156
1157 #define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108
1158 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1159
1160 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24
1161 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1
1162 #define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22
1163 #define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1
1164 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20
1165 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1
1166 #define PCRF_AZ_ECRC_ERR_MASK_LBN 19
1167 #define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1
1168 #define PCRF_AZ_MALF_TLP_MASK_LBN 18
1169 #define PCRF_AZ_MALF_TLP_MASK_WIDTH 1
1170 #define PCRF_AZ_RX_OVF_MASK_LBN 17
1171 #define PCRF_AZ_RX_OVF_MASK_WIDTH 1
1172 #define PCRF_AZ_UNEXP_COMP_MASK_LBN 16
1173 #define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1
1174 #define PCRF_AZ_COMP_ABRT_MASK_LBN 15
1175 #define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1
1176 #define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14
1177 #define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1
1178 #define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13
1179 #define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1
1180 #define PCRF_AZ_PSON_TLP_MASK_LBN 12
1181 #define PCRF_AZ_PSON_TLP_MASK_WIDTH 1
1182 #define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4
1183 #define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1
1184 #define PCRF_AB_TRAIN_ERR_MASK_LBN 0
1185 #define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1
1186
1187
1188 /*
1189 * PC_AER_UNCORR_ERR_SEV_REG(32bit):
1190 * AER Uncorrectable error severity register
1191 */
1192
1193 #define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c
1194 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1195
1196 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20
1197 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1
1198 #define PCRF_AZ_ECRC_ERR_SEV_LBN 19
1199 #define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1
1200 #define PCRF_AZ_MALF_TLP_SEV_LBN 18
1201 #define PCRF_AZ_MALF_TLP_SEV_WIDTH 1
1202 #define PCRF_AZ_RX_OVF_SEV_LBN 17
1203 #define PCRF_AZ_RX_OVF_SEV_WIDTH 1
1204 #define PCRF_AZ_UNEXP_COMP_SEV_LBN 16
1205 #define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1
1206 #define PCRF_AZ_COMP_ABRT_SEV_LBN 15
1207 #define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1
1208 #define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14
1209 #define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1
1210 #define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13
1211 #define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1
1212 #define PCRF_AZ_PSON_TLP_SEV_LBN 12
1213 #define PCRF_AZ_PSON_TLP_SEV_WIDTH 1
1214 #define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4
1215 #define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1
1216 #define PCRF_AB_TRAIN_ERR_SEV_LBN 0
1217 #define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1
1218
1219
1220 /*
1221 * PC_AER_CORR_ERR_STAT_REG(32bit):
1222 * AER Correctable error status register
1223 */
1224
1225 #define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110
1226 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1227
1228 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13
1229 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1
1230 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12
1231 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1
1232 #define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8
1233 #define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1
1234 #define PCRF_AZ_BAD_DLLP_STAT_LBN 7
1235 #define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1
1236 #define PCRF_AZ_BAD_TLP_STAT_LBN 6
1237 #define PCRF_AZ_BAD_TLP_STAT_WIDTH 1
1238 #define PCRF_AZ_RX_ERR_STAT_LBN 0
1239 #define PCRF_AZ_RX_ERR_STAT_WIDTH 1
1240
1241
1242 /*
1243 * PC_AER_CORR_ERR_MASK_REG(32bit):
1244 * AER Correctable error status register
1245 */
1246
1247 #define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114
1248 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1249
1250 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13
1251 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1
1252 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12
1253 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1
1254 #define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8
1255 #define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1
1256 #define PCRF_AZ_BAD_DLLP_MASK_LBN 7
1257 #define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1
1258 #define PCRF_AZ_BAD_TLP_MASK_LBN 6
1259 #define PCRF_AZ_BAD_TLP_MASK_WIDTH 1
1260 #define PCRF_AZ_RX_ERR_MASK_LBN 0
1261 #define PCRF_AZ_RX_ERR_MASK_WIDTH 1
1262
1263
1264 /*
1265 * PC_AER_CAP_CTL_REG(32bit):
1266 * AER capability and control register
1267 */
1268
1269 #define PCR_AZ_AER_CAP_CTL_REG 0x00000118
1270 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1271
1272 #define PCRF_AZ_ECRC_CHK_EN_LBN 8
1273 #define PCRF_AZ_ECRC_CHK_EN_WIDTH 1
1274 #define PCRF_AZ_ECRC_CHK_CAP_LBN 7
1275 #define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1
1276 #define PCRF_AZ_ECRC_GEN_EN_LBN 6
1277 #define PCRF_AZ_ECRC_GEN_EN_WIDTH 1
1278 #define PCRF_AZ_ECRC_GEN_CAP_LBN 5
1279 #define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1
1280 #define PCRF_AZ_1ST_ERR_PTR_LBN 0
1281 #define PCRF_AZ_1ST_ERR_PTR_WIDTH 5
1282
1283
1284 /*
1285 * PC_AER_HDR_LOG_REG(128bit):
1286 * AER Header log register
1287 */
1288
1289 #define PCR_AZ_AER_HDR_LOG_REG 0x0000011c
1290 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1291
1292 #define PCRF_AZ_HDR_LOG_LBN 0
1293 #define PCRF_AZ_HDR_LOG_WIDTH 128
1294
1295
1296 /*
1297 * PC_DEVSN_CAP_HDR_REG(32bit):
1298 * Device serial number capability header register
1299 */
1300
1301 #define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140
1302 /* sienaa0,hunta0=pci_f0_config */
1303
1304 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20
1305 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12
1306 #define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16
1307 #define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4
1308 #define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0
1309 #define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16
1310
1311
1312 /*
1313 * PC_DEVSN_DWORD0_REG(32bit):
1314 * Device serial number DWORD0
1315 */
1316
1317 #define PCR_CZ_DEVSN_DWORD0_REG 0x00000144
1318 /* sienaa0,hunta0=pci_f0_config */
1319
1320 #define PCRF_CZ_DEVSN_DWORD0_LBN 0
1321 #define PCRF_CZ_DEVSN_DWORD0_WIDTH 32
1322
1323
1324 /*
1325 * PC_DEVSN_DWORD1_REG(32bit):
1326 * Device serial number DWORD0
1327 */
1328
1329 #define PCR_CZ_DEVSN_DWORD1_REG 0x00000148
1330 /* sienaa0,hunta0=pci_f0_config */
1331
1332 #define PCRF_CZ_DEVSN_DWORD1_LBN 0
1333 #define PCRF_CZ_DEVSN_DWORD1_WIDTH 32
1334
1335
1336 /*
1337 * PC_ARI_CAP_HDR_REG(32bit):
1338 * ARI capability header register
1339 */
1340
1341 #define PCR_CZ_ARI_CAP_HDR_REG 0x00000150
1342 /* sienaa0,hunta0=pci_f0_config */
1343
1344 #define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20
1345 #define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12
1346 #define PCRF_CZ_ARICAPHDR_VER_LBN 16
1347 #define PCRF_CZ_ARICAPHDR_VER_WIDTH 4
1348 #define PCRF_CZ_ARICAPHDR_ID_LBN 0
1349 #define PCRF_CZ_ARICAPHDR_ID_WIDTH 16
1350
1351
1352 /*
1353 * PC_ARI_CAP_REG(16bit):
1354 * ARI Capabilities
1355 */
1356
1357 #define PCR_CZ_ARI_CAP_REG 0x00000154
1358 /* sienaa0,hunta0=pci_f0_config */
1359
1360 #define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8
1361 #define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8
1362 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1
1363 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1
1364 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0
1365 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1
1366
1367
1368 /*
1369 * PC_ARI_CTL_REG(16bit):
1370 * ARI Control
1371 */
1372
1373 #define PCR_CZ_ARI_CTL_REG 0x00000156
1374 /* sienaa0,hunta0=pci_f0_config */
1375
1376 #define PCRF_CZ_ARI_FN_GRP_LBN 4
1377 #define PCRF_CZ_ARI_FN_GRP_WIDTH 3
1378 #define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1
1379 #define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1
1380 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0
1381 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1
1382
1383
1384 /*
1385 * PC_SEC_PCIE_CAP_REG(32bit):
1386 * Secondary PCIE Capability Register
1387 */
1388
1389 #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160
1390 /* hunta0=pci_f0_config */
1391
1392 #define PCRF_DZ_SEC_NXT_PTR_LBN 20
1393 #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12
1394 #define PCRF_DZ_SEC_VERSION_LBN 16
1395 #define PCRF_DZ_SEC_VERSION_WIDTH 4
1396 #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0
1397 #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16
1398
1399
1400 /*
1401 * PC_SRIOV_CAP_HDR_REG(32bit):
1402 * SRIOV capability header register
1403 */
1404
1405 #define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160
1406 /* sienaa0=pci_f0_config */
1407
1408 #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180
1409 /* hunta0=pci_f0_config */
1410
1411 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20
1412 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12
1413 #define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16
1414 #define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4
1415 #define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0
1416 #define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16
1417
1418
1419 /*
1420 * PC_SRIOV_CAP_REG(32bit):
1421 * SRIOV Capabilities
1422 */
1423
1424 #define PCR_CC_SRIOV_CAP_REG 0x00000164
1425 /* sienaa0=pci_f0_config */
1426
1427 #define PCR_DZ_SRIOV_CAP_REG 0x00000184
1428 /* hunta0=pci_f0_config */
1429
1430 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21
1431 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11
1432 #define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1
1433 #define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1
1434 #define PCRF_CZ_VF_MIGR_CAP_LBN 0
1435 #define PCRF_CZ_VF_MIGR_CAP_WIDTH 1
1436
1437
1438 /*
1439 * PC_LINK_CONTROL3_REG(32bit):
1440 * Link Control 3.
1441 */
1442
1443 #define PCR_DZ_LINK_CONTROL3_REG 0x00000164
1444 /* hunta0=pci_f0_config */
1445
1446 #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1
1447 #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1
1448 #define PCRF_DZ_PERFORM_EQL_LBN 0
1449 #define PCRF_DZ_PERFORM_EQL_WIDTH 1
1450
1451
1452 /*
1453 * PC_LANE_ERROR_STAT_REG(32bit):
1454 * Lane Error Status Register.
1455 */
1456
1457 #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168
1458 /* hunta0=pci_f0_config */
1459
1460 #define PCRF_DZ_LANE_STATUS_LBN 0
1461 #define PCRF_DZ_LANE_STATUS_WIDTH 8
1462
1463
1464 /*
1465 * PC_SRIOV_CTL_REG(16bit):
1466 * SRIOV Control
1467 */
1468
1469 #define PCR_CC_SRIOV_CTL_REG 0x00000168
1470 /* sienaa0=pci_f0_config */
1471
1472 #define PCR_DZ_SRIOV_CTL_REG 0x00000188
1473 /* hunta0=pci_f0_config */
1474
1475 #define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4
1476 #define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1
1477 #define PCRF_CZ_VF_MSE_LBN 3
1478 #define PCRF_CZ_VF_MSE_WIDTH 1
1479 #define PCRF_CZ_VF_MIGR_INT_EN_LBN 2
1480 #define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1
1481 #define PCRF_CZ_VF_MIGR_EN_LBN 1
1482 #define PCRF_CZ_VF_MIGR_EN_WIDTH 1
1483 #define PCRF_CZ_VF_EN_LBN 0
1484 #define PCRF_CZ_VF_EN_WIDTH 1
1485
1486
1487 /*
1488 * PC_SRIOV_STAT_REG(16bit):
1489 * SRIOV Status
1490 */
1491
1492 #define PCR_CC_SRIOV_STAT_REG 0x0000016a
1493 /* sienaa0=pci_f0_config */
1494
1495 #define PCR_DZ_SRIOV_STAT_REG 0x0000018a
1496 /* hunta0=pci_f0_config */
1497
1498 #define PCRF_CZ_VF_MIGR_STAT_LBN 0
1499 #define PCRF_CZ_VF_MIGR_STAT_WIDTH 1
1500
1501
1502 /*
1503 * PC_LANE01_EQU_CONTROL_REG(32bit):
1504 * Lanes 0,1 Equalization Control Register.
1505 */
1506
1507 #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c
1508 /* hunta0=pci_f0_config */
1509
1510 #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16
1511 #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16
1512 #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0
1513 #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16
1514
1515
1516 /*
1517 * PC_SRIOV_INITIALVFS_REG(16bit):
1518 * SRIOV Initial VFs
1519 */
1520
1521 #define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c
1522 /* sienaa0=pci_f0_config */
1523
1524 #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c
1525 /* hunta0=pci_f0_config */
1526
1527 #define PCRF_CZ_VF_INITIALVFS_LBN 0
1528 #define PCRF_CZ_VF_INITIALVFS_WIDTH 16
1529
1530
1531 /*
1532 * PC_SRIOV_TOTALVFS_REG(10bit):
1533 * SRIOV Total VFs
1534 */
1535
1536 #define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e
1537 /* sienaa0=pci_f0_config */
1538
1539 #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e
1540 /* hunta0=pci_f0_config */
1541
1542 #define PCRF_CZ_VF_TOTALVFS_LBN 0
1543 #define PCRF_CZ_VF_TOTALVFS_WIDTH 16
1544
1545
1546 /*
1547 * PC_SRIOV_NUMVFS_REG(16bit):
1548 * SRIOV Number of VFs
1549 */
1550
1551 #define PCR_CC_SRIOV_NUMVFS_REG 0x00000170
1552 /* sienaa0=pci_f0_config */
1553
1554 #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190
1555 /* hunta0=pci_f0_config */
1556
1557 #define PCRF_CZ_VF_NUMVFS_LBN 0
1558 #define PCRF_CZ_VF_NUMVFS_WIDTH 16
1559
1560
1561 /*
1562 * PC_LANE23_EQU_CONTROL_REG(32bit):
1563 * Lanes 2,3 Equalization Control Register.
1564 */
1565
1566 #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170
1567 /* hunta0=pci_f0_config */
1568
1569 #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16
1570 #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16
1571 #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0
1572 #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16
1573
1574
1575 /*
1576 * PC_SRIOV_FN_DPND_LNK_REG(16bit):
1577 * SRIOV Function dependency link
1578 */
1579
1580 #define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172
1581 /* sienaa0=pci_f0_config */
1582
1583 #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192
1584 /* hunta0=pci_f0_config */
1585
1586 #define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0
1587 #define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8
1588
1589
1590 /*
1591 * PC_SRIOV_1STVF_OFFSET_REG(16bit):
1592 * SRIOV First VF Offset
1593 */
1594
1595 #define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174
1596 /* sienaa0=pci_f0_config */
1597
1598 #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194
1599 /* hunta0=pci_f0_config */
1600
1601 #define PCRF_CZ_VF_1STVF_OFFSET_LBN 0
1602 #define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16
1603
1604
1605 /*
1606 * PC_LANE45_EQU_CONTROL_REG(32bit):
1607 * Lanes 4,5 Equalization Control Register.
1608 */
1609
1610 #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174
1611 /* hunta0=pci_f0_config */
1612
1613 #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16
1614 #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16
1615 #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0
1616 #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16
1617
1618
1619 /*
1620 * PC_SRIOV_VFSTRIDE_REG(16bit):
1621 * SRIOV VF Stride
1622 */
1623
1624 #define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176
1625 /* sienaa0=pci_f0_config */
1626
1627 #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196
1628 /* hunta0=pci_f0_config */
1629
1630 #define PCRF_CZ_VF_VFSTRIDE_LBN 0
1631 #define PCRF_CZ_VF_VFSTRIDE_WIDTH 16
1632
1633
1634 /*
1635 * PC_LANE67_EQU_CONTROL_REG(32bit):
1636 * Lanes 6,7 Equalization Control Register.
1637 */
1638
1639 #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178
1640 /* hunta0=pci_f0_config */
1641
1642 #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16
1643 #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16
1644 #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0
1645 #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16
1646
1647
1648 /*
1649 * PC_SRIOV_DEVID_REG(16bit):
1650 * SRIOV VF Device ID
1651 */
1652
1653 #define PCR_CC_SRIOV_DEVID_REG 0x0000017a
1654 /* sienaa0=pci_f0_config */
1655
1656 #define PCR_DZ_SRIOV_DEVID_REG 0x0000019a
1657 /* hunta0=pci_f0_config */
1658
1659 #define PCRF_CZ_VF_DEVID_LBN 0
1660 #define PCRF_CZ_VF_DEVID_WIDTH 16
1661
1662
1663 /*
1664 * PC_SRIOV_SUP_PAGESZ_REG(16bit):
1665 * SRIOV Supported Page Sizes
1666 */
1667
1668 #define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c
1669 /* sienaa0=pci_f0_config */
1670
1671 #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c
1672 /* hunta0=pci_f0_config */
1673
1674 #define PCRF_CZ_VF_SUP_PAGESZ_LBN 0
1675 #define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16
1676
1677
1678 /*
1679 * PC_SRIOV_SYS_PAGESZ_REG(32bit):
1680 * SRIOV System Page Size
1681 */
1682
1683 #define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180
1684 /* sienaa0=pci_f0_config */
1685
1686 #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0
1687 /* hunta0=pci_f0_config */
1688
1689 #define PCRF_CZ_VF_SYS_PAGESZ_LBN 0
1690 #define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16
1691
1692
1693 /*
1694 * PC_SRIOV_BAR0_REG(32bit):
1695 * SRIOV VF Bar0
1696 */
1697
1698 #define PCR_CC_SRIOV_BAR0_REG 0x00000184
1699 /* sienaa0=pci_f0_config */
1700
1701 #define PCR_DZ_SRIOV_BAR0_REG 0x000001a4
1702 /* hunta0=pci_f0_config */
1703
1704 #define PCRF_CC_VF_BAR_ADDRESS_LBN 0
1705 #define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32
1706 #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4
1707 #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28
1708 #define PCRF_DZ_VF_BAR0_PREF_LBN 3
1709 #define PCRF_DZ_VF_BAR0_PREF_WIDTH 1
1710 #define PCRF_DZ_VF_BAR0_TYPE_LBN 1
1711 #define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2
1712 #define PCRF_DZ_VF_BAR0_IOM_LBN 0
1713 #define PCRF_DZ_VF_BAR0_IOM_WIDTH 1
1714
1715
1716 /*
1717 * PC_SRIOV_BAR1_REG(32bit):
1718 * SRIOV Bar1
1719 */
1720
1721 #define PCR_CC_SRIOV_BAR1_REG 0x00000188
1722 /* sienaa0=pci_f0_config */
1723
1724 #define PCR_DZ_SRIOV_BAR1_REG 0x000001a8
1725 /* hunta0=pci_f0_config */
1726
1727 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1728 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1729 #define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0
1730 #define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32
1731
1732
1733 /*
1734 * PC_SRIOV_BAR2_REG(32bit):
1735 * SRIOV Bar2
1736 */
1737
1738 #define PCR_CC_SRIOV_BAR2_REG 0x0000018c
1739 /* sienaa0=pci_f0_config */
1740
1741 #define PCR_DZ_SRIOV_BAR2_REG 0x000001ac
1742 /* hunta0=pci_f0_config */
1743
1744 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1745 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1746 #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4
1747 #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28
1748 #define PCRF_DZ_VF_BAR2_PREF_LBN 3
1749 #define PCRF_DZ_VF_BAR2_PREF_WIDTH 1
1750 #define PCRF_DZ_VF_BAR2_TYPE_LBN 1
1751 #define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2
1752 #define PCRF_DZ_VF_BAR2_IOM_LBN 0
1753 #define PCRF_DZ_VF_BAR2_IOM_WIDTH 1
1754
1755
1756 /*
1757 * PC_SRIOV_BAR3_REG(32bit):
1758 * SRIOV Bar3
1759 */
1760
1761 #define PCR_CC_SRIOV_BAR3_REG 0x00000190
1762 /* sienaa0=pci_f0_config */
1763
1764 #define PCR_DZ_SRIOV_BAR3_REG 0x000001b0
1765 /* hunta0=pci_f0_config */
1766
1767 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1768 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1769 #define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0
1770 #define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32
1771
1772
1773 /*
1774 * PC_SRIOV_BAR4_REG(32bit):
1775 * SRIOV Bar4
1776 */
1777
1778 #define PCR_CC_SRIOV_BAR4_REG 0x00000194
1779 /* sienaa0=pci_f0_config */
1780
1781 #define PCR_DZ_SRIOV_BAR4_REG 0x000001b4
1782 /* hunta0=pci_f0_config */
1783
1784 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1785 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1786 #define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0
1787 #define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32
1788
1789
1790 /*
1791 * PC_SRIOV_BAR5_REG(32bit):
1792 * SRIOV Bar5
1793 */
1794
1795 #define PCR_CC_SRIOV_BAR5_REG 0x00000198
1796 /* sienaa0=pci_f0_config */
1797
1798 #define PCR_DZ_SRIOV_BAR5_REG 0x000001b8
1799 /* hunta0=pci_f0_config */
1800
1801 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1802 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1803 #define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0
1804 #define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32
1805
1806
1807 /*
1808 * PC_SRIOV_RSVD_REG(16bit):
1809 * Reserved register
1810 */
1811
1812 #define PCR_DZ_SRIOV_RSVD_REG 0x00000198
1813 /* hunta0=pci_f0_config */
1814
1815 #define PCRF_DZ_VF_RSVD_LBN 0
1816 #define PCRF_DZ_VF_RSVD_WIDTH 16
1817
1818
1819 /*
1820 * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit):
1821 * SRIOV VF Migration State Array Offset
1822 */
1823
1824 #define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c
1825 /* sienaa0=pci_f0_config */
1826
1827 #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc
1828 /* hunta0=pci_f0_config */
1829
1830 #define PCRF_CZ_VF_MIGR_OFFSET_LBN 3
1831 #define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29
1832 #define PCRF_CZ_VF_MIGR_BIR_LBN 0
1833 #define PCRF_CZ_VF_MIGR_BIR_WIDTH 3
1834
1835
1836 /*
1837 * PC_TPH_CAP_HDR_REG(32bit):
1838 * TPH Capability Header Register
1839 */
1840
1841 #define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0
1842 /* hunta0=pci_f0_config */
1843
1844 #define PCRF_DZ_TPH_NXT_PTR_LBN 20
1845 #define PCRF_DZ_TPH_NXT_PTR_WIDTH 12
1846 #define PCRF_DZ_TPH_VERSION_LBN 16
1847 #define PCRF_DZ_TPH_VERSION_WIDTH 4
1848 #define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0
1849 #define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16
1850
1851
1852 /*
1853 * PC_TPH_REQ_CAP_REG(32bit):
1854 * TPH Requester Capability Register
1855 */
1856
1857 #define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4
1858 /* hunta0=pci_f0_config */
1859
1860 #define PCRF_DZ_ST_TBLE_SIZE_LBN 16
1861 #define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11
1862 #define PCRF_DZ_ST_TBLE_LOC_LBN 9
1863 #define PCRF_DZ_ST_TBLE_LOC_WIDTH 2
1864 #define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8
1865 #define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1
1866 #define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2
1867 #define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1
1868 #define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1
1869 #define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1
1870 #define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0
1871 #define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1
1872
1873
1874 /*
1875 * PC_TPH_REQ_CTL_REG(32bit):
1876 * TPH Requester Control Register
1877 */
1878
1879 #define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8
1880 /* hunta0=pci_f0_config */
1881
1882 #define PCRF_DZ_TPH_REQ_ENABLE_LBN 8
1883 #define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2
1884 #define PCRF_DZ_TPH_ST_MODE_LBN 0
1885 #define PCRF_DZ_TPH_ST_MODE_WIDTH 3
1886
1887
1888 /*
1889 * PC_LTR_CAP_HDR_REG(32bit):
1890 * Latency Tolerance Reporting Cap Header Reg
1891 */
1892
1893 #define PCR_DZ_LTR_CAP_HDR_REG 0x00000290
1894 /* hunta0=pci_f0_config */
1895
1896 #define PCRF_DZ_LTR_NXT_PTR_LBN 20
1897 #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12
1898 #define PCRF_DZ_LTR_VERSION_LBN 16
1899 #define PCRF_DZ_LTR_VERSION_WIDTH 4
1900 #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0
1901 #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16
1902
1903
1904 /*
1905 * PC_LTR_MAX_SNOOP_REG(32bit):
1906 * LTR Maximum Snoop/No Snoop Register
1907 */
1908
1909 #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294
1910 /* hunta0=pci_f0_config */
1911
1912 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26
1913 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3
1914 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16
1915 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10
1916 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10
1917 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3
1918 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0
1919 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10
1920
1921
1922 /*
1923 * PC_ACK_LAT_TMR_REG(32bit):
1924 * ACK latency timer & replay timer register
1925 */
1926
1927 #define PCR_AC_ACK_LAT_TMR_REG 0x00000700
1928 /* falcona0,falconb0,sienaa0=pci_f0_config */
1929
1930 #define PCRF_AC_RT_LBN 16
1931 #define PCRF_AC_RT_WIDTH 16
1932 #define PCRF_AC_ALT_LBN 0
1933 #define PCRF_AC_ALT_WIDTH 16
1934
1935
1936 /*
1937 * PC_OTHER_MSG_REG(32bit):
1938 * Other message register
1939 */
1940
1941 #define PCR_AC_OTHER_MSG_REG 0x00000704
1942 /* falcona0,falconb0,sienaa0=pci_f0_config */
1943
1944 #define PCRF_AC_OM_CRPT3_LBN 24
1945 #define PCRF_AC_OM_CRPT3_WIDTH 8
1946 #define PCRF_AC_OM_CRPT2_LBN 16
1947 #define PCRF_AC_OM_CRPT2_WIDTH 8
1948 #define PCRF_AC_OM_CRPT1_LBN 8
1949 #define PCRF_AC_OM_CRPT1_WIDTH 8
1950 #define PCRF_AC_OM_CRPT0_LBN 0
1951 #define PCRF_AC_OM_CRPT0_WIDTH 8
1952
1953
1954 /*
1955 * PC_FORCE_LNK_REG(24bit):
1956 * Port force link register
1957 */
1958
1959 #define PCR_AC_FORCE_LNK_REG 0x00000708
1960 /* falcona0,falconb0,sienaa0=pci_f0_config */
1961
1962 #define PCRF_AC_LFS_LBN 16
1963 #define PCRF_AC_LFS_WIDTH 6
1964 #define PCRF_AC_FL_LBN 15
1965 #define PCRF_AC_FL_WIDTH 1
1966 #define PCRF_AC_LN_LBN 0
1967 #define PCRF_AC_LN_WIDTH 8
1968
1969
1970 /*
1971 * PC_ACK_FREQ_REG(32bit):
1972 * ACK frequency register
1973 */
1974
1975 #define PCR_AC_ACK_FREQ_REG 0x0000070c
1976 /* falcona0,falconb0,sienaa0=pci_f0_config */
1977
1978 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30
1979 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1
1980 #define PCRF_AC_L1_ENTR_LAT_LBN 27
1981 #define PCRF_AC_L1_ENTR_LAT_WIDTH 3
1982 #define PCRF_AC_L0_ENTR_LAT_LBN 24
1983 #define PCRF_AC_L0_ENTR_LAT_WIDTH 3
1984 #define PCRF_CC_COMM_NFTS_LBN 16
1985 #define PCRF_CC_COMM_NFTS_WIDTH 8
1986 #define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16
1987 #define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3
1988 #define PCRF_AC_MAX_FTS_LBN 8
1989 #define PCRF_AC_MAX_FTS_WIDTH 8
1990 #define PCRF_AC_ACK_FREQ_LBN 0
1991 #define PCRF_AC_ACK_FREQ_WIDTH 8
1992
1993
1994 /*
1995 * PC_PORT_LNK_CTL_REG(32bit):
1996 * Port link control register
1997 */
1998
1999 #define PCR_AC_PORT_LNK_CTL_REG 0x00000710
2000 /* falcona0,falconb0,sienaa0=pci_f0_config */
2001
2002 #define PCRF_AB_LRE_LBN 27
2003 #define PCRF_AB_LRE_WIDTH 1
2004 #define PCRF_AB_ESYNC_LBN 26
2005 #define PCRF_AB_ESYNC_WIDTH 1
2006 #define PCRF_AB_CRPT_LBN 25
2007 #define PCRF_AB_CRPT_WIDTH 1
2008 #define PCRF_AB_XB_LBN 24
2009 #define PCRF_AB_XB_WIDTH 1
2010 #define PCRF_AC_LC_LBN 16
2011 #define PCRF_AC_LC_WIDTH 6
2012 #define PCRF_AC_LDR_LBN 8
2013 #define PCRF_AC_LDR_WIDTH 4
2014 #define PCRF_AC_FLM_LBN 7
2015 #define PCRF_AC_FLM_WIDTH 1
2016 #define PCRF_AC_LKD_LBN 6
2017 #define PCRF_AC_LKD_WIDTH 1
2018 #define PCRF_AC_DLE_LBN 5
2019 #define PCRF_AC_DLE_WIDTH 1
2020 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4
2021 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1
2022 #define PCRF_AC_RA_LBN 3
2023 #define PCRF_AC_RA_WIDTH 1
2024 #define PCRF_AC_LE_LBN 2
2025 #define PCRF_AC_LE_WIDTH 1
2026 #define PCRF_AC_SD_LBN 1
2027 #define PCRF_AC_SD_WIDTH 1
2028 #define PCRF_AC_OMR_LBN 0
2029 #define PCRF_AC_OMR_WIDTH 1
2030
2031
2032 /*
2033 * PC_LN_SKEW_REG(32bit):
2034 * Lane skew register
2035 */
2036
2037 #define PCR_AC_LN_SKEW_REG 0x00000714
2038 /* falcona0,falconb0,sienaa0=pci_f0_config */
2039
2040 #define PCRF_AC_DIS_LBN 31
2041 #define PCRF_AC_DIS_WIDTH 1
2042 #define PCRF_AB_RST_LBN 30
2043 #define PCRF_AB_RST_WIDTH 1
2044 #define PCRF_AC_AD_LBN 25
2045 #define PCRF_AC_AD_WIDTH 1
2046 #define PCRF_AC_FCD_LBN 24
2047 #define PCRF_AC_FCD_WIDTH 1
2048 #define PCRF_AC_LS2_LBN 16
2049 #define PCRF_AC_LS2_WIDTH 8
2050 #define PCRF_AC_LS1_LBN 8
2051 #define PCRF_AC_LS1_WIDTH 8
2052 #define PCRF_AC_LS0_LBN 0
2053 #define PCRF_AC_LS0_WIDTH 8
2054
2055
2056 /*
2057 * PC_SYM_NUM_REG(16bit):
2058 * Symbol number register
2059 */
2060
2061 #define PCR_AC_SYM_NUM_REG 0x00000718
2062 /* falcona0,falconb0,sienaa0=pci_f0_config */
2063
2064 #define PCRF_CC_MAX_FUNCTIONS_LBN 29
2065 #define PCRF_CC_MAX_FUNCTIONS_WIDTH 3
2066 #define PCRF_CC_FC_WATCHDOG_TMR_LBN 24
2067 #define PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5
2068 #define PCRF_CC_ACK_NAK_TMR_MOD_LBN 19
2069 #define PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5
2070 #define PCRF_CC_REPLAY_TMR_MOD_LBN 14
2071 #define PCRF_CC_REPLAY_TMR_MOD_WIDTH 5
2072 #define PCRF_AB_ES_LBN 12
2073 #define PCRF_AB_ES_WIDTH 3
2074 #define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11
2075 #define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1
2076 #define PCRF_CC_NUM_SKP_SYMS_LBN 8
2077 #define PCRF_CC_NUM_SKP_SYMS_WIDTH 3
2078 #define PCRF_AB_TS2_LBN 4
2079 #define PCRF_AB_TS2_WIDTH 4
2080 #define PCRF_AC_TS1_LBN 0
2081 #define PCRF_AC_TS1_WIDTH 4
2082
2083
2084 /*
2085 * PC_SYM_TMR_FLT_MSK_REG(16bit):
2086 * Symbol timer and Filter Mask Register
2087 */
2088
2089 #define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c
2090 /* sienaa0=pci_f0_config */
2091
2092 #define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16
2093 #define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16
2094 #define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15
2095 #define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1
2096 #define PCRF_CC_SI1_LBN 8
2097 #define PCRF_CC_SI1_WIDTH 3
2098 #define PCRF_CC_SKIP_INT_VAL_LBN 0
2099 #define PCRF_CC_SKIP_INT_VAL_WIDTH 11
2100 #define PCRF_CC_SI0_LBN 0
2101 #define PCRF_CC_SI0_WIDTH 8
2102
2103
2104 /*
2105 * PC_SYM_TMR_REG(16bit):
2106 * Symbol timer register
2107 */
2108
2109 #define PCR_AB_SYM_TMR_REG 0x0000071c
2110 /* falcona0,falconb0=pci_f0_config */
2111
2112 #define PCRF_AB_ET_LBN 11
2113 #define PCRF_AB_ET_WIDTH 4
2114 #define PCRF_AB_SI1_LBN 8
2115 #define PCRF_AB_SI1_WIDTH 3
2116 #define PCRF_AB_SI0_LBN 0
2117 #define PCRF_AB_SI0_WIDTH 8
2118
2119
2120 /*
2121 * PC_FLT_MSK_REG(32bit):
2122 * Filter Mask Register 2
2123 */
2124
2125 #define PCR_CC_FLT_MSK_REG 0x00000720
2126 /* sienaa0=pci_f0_config */
2127
2128 #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0
2129 #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32
2130
2131
2132 /*
2133 * PC_PHY_STAT_REG(32bit):
2134 * PHY status register
2135 */
2136
2137 #define PCR_AB_PHY_STAT_REG 0x00000720
2138 /* falcona0,falconb0=pci_f0_config */
2139
2140 #define PCR_CC_PHY_STAT_REG 0x00000810
2141 /* sienaa0=pci_f0_config */
2142
2143 #define PCRF_AC_SSL_LBN 3
2144 #define PCRF_AC_SSL_WIDTH 1
2145 #define PCRF_AC_SSR_LBN 2
2146 #define PCRF_AC_SSR_WIDTH 1
2147 #define PCRF_AC_SSCL_LBN 1
2148 #define PCRF_AC_SSCL_WIDTH 1
2149 #define PCRF_AC_SSCD_LBN 0
2150 #define PCRF_AC_SSCD_WIDTH 1
2151
2152
2153 /*
2154 * PC_PHY_CTL_REG(32bit):
2155 * PHY control register
2156 */
2157
2158 #define PCR_AB_PHY_CTL_REG 0x00000724
2159 /* falcona0,falconb0=pci_f0_config */
2160
2161 #define PCR_CC_PHY_CTL_REG 0x00000814
2162 /* sienaa0=pci_f0_config */
2163
2164 #define PCRF_AC_BD_LBN 31
2165 #define PCRF_AC_BD_WIDTH 1
2166 #define PCRF_AC_CDS_LBN 30
2167 #define PCRF_AC_CDS_WIDTH 1
2168 #define PCRF_AC_DWRAP_LB_LBN 29
2169 #define PCRF_AC_DWRAP_LB_WIDTH 1
2170 #define PCRF_AC_EBD_LBN 28
2171 #define PCRF_AC_EBD_WIDTH 1
2172 #define PCRF_AC_SNR_LBN 27
2173 #define PCRF_AC_SNR_WIDTH 1
2174 #define PCRF_AC_RX_NOT_DET_LBN 2
2175 #define PCRF_AC_RX_NOT_DET_WIDTH 1
2176 #define PCRF_AC_FORCE_LOS_VAL_LBN 1
2177 #define PCRF_AC_FORCE_LOS_VAL_WIDTH 1
2178 #define PCRF_AC_FORCE_LOS_EN_LBN 0
2179 #define PCRF_AC_FORCE_LOS_EN_WIDTH 1
2180
2181
2182 /*
2183 * PC_DEBUG0_REG(32bit):
2184 * Debug register 0
2185 */
2186
2187 #define PCR_AC_DEBUG0_REG 0x00000728
2188 /* falcona0,falconb0,sienaa0=pci_f0_config */
2189
2190 #define PCRF_AC_CDI03_LBN 24
2191 #define PCRF_AC_CDI03_WIDTH 8
2192 #define PCRF_AC_CDI0_LBN 0
2193 #define PCRF_AC_CDI0_WIDTH 32
2194 #define PCRF_AC_CDI02_LBN 16
2195 #define PCRF_AC_CDI02_WIDTH 8
2196 #define PCRF_AC_CDI01_LBN 8
2197 #define PCRF_AC_CDI01_WIDTH 8
2198 #define PCRF_AC_CDI00_LBN 0
2199 #define PCRF_AC_CDI00_WIDTH 8
2200
2201
2202 /*
2203 * PC_DEBUG1_REG(32bit):
2204 * Debug register 1
2205 */
2206
2207 #define PCR_AC_DEBUG1_REG 0x0000072c
2208 /* falcona0,falconb0,sienaa0=pci_f0_config */
2209
2210 #define PCRF_AC_CDI13_LBN 24
2211 #define PCRF_AC_CDI13_WIDTH 8
2212 #define PCRF_AC_CDI1_LBN 0
2213 #define PCRF_AC_CDI1_WIDTH 32
2214 #define PCRF_AC_CDI12_LBN 16
2215 #define PCRF_AC_CDI12_WIDTH 8
2216 #define PCRF_AC_CDI11_LBN 8
2217 #define PCRF_AC_CDI11_WIDTH 8
2218 #define PCRF_AC_CDI10_LBN 0
2219 #define PCRF_AC_CDI10_WIDTH 8
2220
2221
2222 /*
2223 * PC_XPFCC_STAT_REG(24bit):
2224 * documentation to be written for sum_PC_XPFCC_STAT_REG
2225 */
2226
2227 #define PCR_AC_XPFCC_STAT_REG 0x00000730
2228 /* falcona0,falconb0,sienaa0=pci_f0_config */
2229
2230 #define PCRF_AC_XPDC_LBN 12
2231 #define PCRF_AC_XPDC_WIDTH 8
2232 #define PCRF_AC_XPHC_LBN 0
2233 #define PCRF_AC_XPHC_WIDTH 12
2234
2235
2236 /*
2237 * PC_XNPFCC_STAT_REG(24bit):
2238 * documentation to be written for sum_PC_XNPFCC_STAT_REG
2239 */
2240
2241 #define PCR_AC_XNPFCC_STAT_REG 0x00000734
2242 /* falcona0,falconb0,sienaa0=pci_f0_config */
2243
2244 #define PCRF_AC_XNPDC_LBN 12
2245 #define PCRF_AC_XNPDC_WIDTH 8
2246 #define PCRF_AC_XNPHC_LBN 0
2247 #define PCRF_AC_XNPHC_WIDTH 12
2248
2249
2250 /*
2251 * PC_XCFCC_STAT_REG(24bit):
2252 * documentation to be written for sum_PC_XCFCC_STAT_REG
2253 */
2254
2255 #define PCR_AC_XCFCC_STAT_REG 0x00000738
2256 /* falcona0,falconb0,sienaa0=pci_f0_config */
2257
2258 #define PCRF_AC_XCDC_LBN 12
2259 #define PCRF_AC_XCDC_WIDTH 8
2260 #define PCRF_AC_XCHC_LBN 0
2261 #define PCRF_AC_XCHC_WIDTH 12
2262
2263
2264 /*
2265 * PC_Q_STAT_REG(8bit):
2266 * documentation to be written for sum_PC_Q_STAT_REG
2267 */
2268
2269 #define PCR_AC_Q_STAT_REG 0x0000073c
2270 /* falcona0,falconb0,sienaa0=pci_f0_config */
2271
2272 #define PCRF_AC_RQNE_LBN 2
2273 #define PCRF_AC_RQNE_WIDTH 1
2274 #define PCRF_AC_XRNE_LBN 1
2275 #define PCRF_AC_XRNE_WIDTH 1
2276 #define PCRF_AC_RCNR_LBN 0
2277 #define PCRF_AC_RCNR_WIDTH 1
2278
2279
2280 /*
2281 * PC_VC_XMIT_ARB1_REG(32bit):
2282 * VC Transmit Arbitration Register 1
2283 */
2284
2285 #define PCR_CC_VC_XMIT_ARB1_REG 0x00000740
2286 /* sienaa0=pci_f0_config */
2287
2288
2289
2290 /*
2291 * PC_VC_XMIT_ARB2_REG(32bit):
2292 * VC Transmit Arbitration Register 2
2293 */
2294
2295 #define PCR_CC_VC_XMIT_ARB2_REG 0x00000744
2296 /* sienaa0=pci_f0_config */
2297
2298
2299
2300 /*
2301 * PC_VC0_P_RQ_CTL_REG(32bit):
2302 * VC0 Posted Receive Queue Control
2303 */
2304
2305 #define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748
2306 /* sienaa0=pci_f0_config */
2307
2308
2309
2310 /*
2311 * PC_VC0_NP_RQ_CTL_REG(32bit):
2312 * VC0 Non-Posted Receive Queue Control
2313 */
2314
2315 #define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c
2316 /* sienaa0=pci_f0_config */
2317
2318
2319
2320 /*
2321 * PC_VC0_C_RQ_CTL_REG(32bit):
2322 * VC0 Completion Receive Queue Control
2323 */
2324
2325 #define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750
2326 /* sienaa0=pci_f0_config */
2327
2328
2329
2330 /*
2331 * PC_GEN2_REG(32bit):
2332 * Gen2 Register
2333 */
2334
2335 #define PCR_CC_GEN2_REG 0x0000080c
2336 /* sienaa0=pci_f0_config */
2337
2338 #define PCRF_CC_SET_DE_EMPHASIS_LBN 20
2339 #define PCRF_CC_SET_DE_EMPHASIS_WIDTH 1
2340 #define PCRF_CC_CFG_TX_COMPLIANCE_LBN 19
2341 #define PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1
2342 #define PCRF_CC_CFG_TX_SWING_LBN 18
2343 #define PCRF_CC_CFG_TX_SWING_WIDTH 1
2344 #define PCRF_CC_DIR_SPEED_CHANGE_LBN 17
2345 #define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1
2346 #define PCRF_CC_LANE_ENABLE_LBN 8
2347 #define PCRF_CC_LANE_ENABLE_WIDTH 9
2348 #define PCRF_CC_NUM_FTS_LBN 0
2349 #define PCRF_CC_NUM_FTS_WIDTH 8
2350
2351
2352 #ifdef __cplusplus
2353 }
2354 #endif
2355
2356 #endif /* _SYS_EFX_REGS_PCI_H */