1 /*
2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 */
30
31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
33
34 #include "efx.h"
35 #include "efx_regs.h"
36 #include "efx_regs_ef10.h"
37
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
41 #endif
42
43
44 #if EFSYS_OPT_SIENA
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
47
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
51
52 #if EFSYS_OPT_MEDFORD
53 #include "medford_impl.h"
54 #endif /* EFSYS_OPT_MEDFORD */
55
56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
57 #include "ef10_impl.h"
58 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
59
60 #ifdef __cplusplus
61 extern "C" {
62 #endif
63
64 #define EFX_MOD_MCDI 0x00000001
65 #define EFX_MOD_PROBE 0x00000002
66 #define EFX_MOD_NVRAM 0x00000004
67 #define EFX_MOD_VPD 0x00000008
68 #define EFX_MOD_NIC 0x00000010
69 #define EFX_MOD_INTR 0x00000020
70 #define EFX_MOD_EV 0x00000040
71 #define EFX_MOD_RX 0x00000080
72 #define EFX_MOD_TX 0x00000100
73 #define EFX_MOD_PORT 0x00000200
74 #define EFX_MOD_MON 0x00000400
75 #define EFX_MOD_WOL 0x00000800
76 #define EFX_MOD_FILTER 0x00001000
77 #define EFX_MOD_LIC 0x00002000
78
79 #define EFX_RESET_PHY 0x00000001
80 #define EFX_RESET_RXQ_ERR 0x00000002
81 #define EFX_RESET_TXQ_ERR 0x00000004
82
83 typedef enum efx_mac_type_e {
84 EFX_MAC_INVALID = 0,
85 EFX_MAC_SIENA,
86 EFX_MAC_HUNTINGTON,
87 EFX_MAC_MEDFORD,
88 EFX_MAC_NTYPES
89 } efx_mac_type_t;
90
91 typedef struct efx_ev_ops_s {
92 efx_rc_t (*eevo_init)(efx_nic_t *);
93 void (*eevo_fini)(efx_nic_t *);
94 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
95 efsys_mem_t *, size_t, uint32_t,
96 efx_evq_t *);
97 void (*eevo_qdestroy)(efx_evq_t *);
98 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
99 void (*eevo_qpost)(efx_evq_t *, uint16_t);
100 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
101 #if EFSYS_OPT_QSTATS
102 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
103 #endif
104 } efx_ev_ops_t;
105
106 typedef struct efx_tx_ops_s {
107 efx_rc_t (*etxo_init)(efx_nic_t *);
108 void (*etxo_fini)(efx_nic_t *);
109 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
110 unsigned int, unsigned int,
111 efsys_mem_t *, size_t,
112 uint32_t, uint16_t,
113 efx_evq_t *, efx_txq_t *,
114 unsigned int *);
115 void (*etxo_qdestroy)(efx_txq_t *);
116 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
117 unsigned int, unsigned int,
118 unsigned int *);
119 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
120 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
121 efx_rc_t (*etxo_qflush)(efx_txq_t *);
122 void (*etxo_qenable)(efx_txq_t *);
123 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
124 void (*etxo_qpio_disable)(efx_txq_t *);
125 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
126 size_t);
127 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
128 unsigned int *);
129 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
130 unsigned int, unsigned int,
131 unsigned int *);
132 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
133 size_t, boolean_t,
134 efx_desc_t *);
135 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
136 uint32_t, uint8_t,
137 efx_desc_t *);
138 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
139 uint32_t, uint16_t,
140 efx_desc_t *, int);
141 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
142 efx_desc_t *);
143 #if EFSYS_OPT_QSTATS
144 void (*etxo_qstats_update)(efx_txq_t *,
145 efsys_stat_t *);
146 #endif
147 } efx_tx_ops_t;
148
149 typedef struct efx_rx_ops_s {
150 efx_rc_t (*erxo_init)(efx_nic_t *);
151 void (*erxo_fini)(efx_nic_t *);
152 #if EFSYS_OPT_RX_SCATTER
153 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
154 #endif
155 #if EFSYS_OPT_RX_SCALE
156 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
157 efx_rx_hash_type_t, boolean_t);
158 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
159 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
160 size_t);
161 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
162 uint8_t *);
163 #endif /* EFSYS_OPT_RX_SCALE */
164 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
165 uint16_t *);
166 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
167 unsigned int, unsigned int,
168 unsigned int);
169 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
170 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
171 void (*erxo_qenable)(efx_rxq_t *);
172 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
173 unsigned int, efx_rxq_type_t,
174 efsys_mem_t *, size_t, uint32_t,
175 efx_evq_t *, efx_rxq_t *);
176 void (*erxo_qdestroy)(efx_rxq_t *);
177 } efx_rx_ops_t;
178
179 typedef struct efx_mac_ops_s {
180 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
181 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
182 efx_rc_t (*emo_addr_set)(efx_nic_t *);
183 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
184 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
185 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
186 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
187 efx_rxq_t *, boolean_t);
188 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
189 #if EFSYS_OPT_LOOPBACK
190 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
191 efx_loopback_type_t);
192 #endif /* EFSYS_OPT_LOOPBACK */
193 #if EFSYS_OPT_MAC_STATS
194 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
195 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
196 uint16_t, boolean_t);
197 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
198 efsys_stat_t *, uint32_t *);
199 #endif /* EFSYS_OPT_MAC_STATS */
200 } efx_mac_ops_t;
201
202 typedef struct efx_phy_ops_s {
203 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
204 efx_rc_t (*epo_reset)(efx_nic_t *);
205 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
206 efx_rc_t (*epo_verify)(efx_nic_t *);
207 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
208 #if EFSYS_OPT_PHY_STATS
209 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
210 uint32_t *);
211 #endif /* EFSYS_OPT_PHY_STATS */
212 #if EFSYS_OPT_BIST
213 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
214 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
215 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
216 efx_bist_result_t *, uint32_t *,
217 unsigned long *, size_t);
218 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
219 #endif /* EFSYS_OPT_BIST */
220 } efx_phy_ops_t;
221
222 #if EFSYS_OPT_FILTER
223 typedef struct efx_filter_ops_s {
224 efx_rc_t (*efo_init)(efx_nic_t *);
225 void (*efo_fini)(efx_nic_t *);
226 efx_rc_t (*efo_restore)(efx_nic_t *);
227 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
228 boolean_t may_replace);
229 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
230 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
231 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
232 boolean_t, boolean_t, boolean_t,
233 uint8_t const *, uint32_t);
234 } efx_filter_ops_t;
235
236 extern __checkReturn efx_rc_t
237 efx_filter_reconfigure(
238 __in efx_nic_t *enp,
239 __in_ecount(6) uint8_t const *mac_addr,
240 __in boolean_t all_unicst,
241 __in boolean_t mulcst,
242 __in boolean_t all_mulcst,
243 __in boolean_t brdcst,
244 __in_ecount(6*count) uint8_t const *addrs,
245 __in uint32_t count);
246
247 #endif /* EFSYS_OPT_FILTER */
248
249
250 typedef struct efx_port_s {
251 efx_mac_type_t ep_mac_type;
252 uint32_t ep_phy_type;
253 uint8_t ep_port;
254 uint32_t ep_mac_pdu;
255 uint8_t ep_mac_addr[6];
256 efx_link_mode_t ep_link_mode;
257 boolean_t ep_all_unicst;
258 boolean_t ep_mulcst;
259 boolean_t ep_all_mulcst;
260 boolean_t ep_brdcst;
261 unsigned int ep_fcntl;
262 boolean_t ep_fcntl_autoneg;
263 efx_oword_t ep_multicst_hash[2];
264 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
265 EFX_MAC_MULTICAST_LIST_MAX];
266 uint32_t ep_mulcst_addr_count;
267 #if EFSYS_OPT_LOOPBACK
268 efx_loopback_type_t ep_loopback_type;
269 efx_link_mode_t ep_loopback_link_mode;
270 #endif /* EFSYS_OPT_LOOPBACK */
271 #if EFSYS_OPT_PHY_FLAGS
272 uint32_t ep_phy_flags;
273 #endif /* EFSYS_OPT_PHY_FLAGS */
274 #if EFSYS_OPT_PHY_LED_CONTROL
275 efx_phy_led_mode_t ep_phy_led_mode;
276 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
277 efx_phy_media_type_t ep_fixed_port_type;
278 efx_phy_media_type_t ep_module_type;
279 uint32_t ep_adv_cap_mask;
280 uint32_t ep_lp_cap_mask;
281 uint32_t ep_default_adv_cap_mask;
282 uint32_t ep_phy_cap_mask;
283 boolean_t ep_mac_drain;
284 boolean_t ep_mac_stats_pending;
285 #if EFSYS_OPT_BIST
286 efx_bist_type_t ep_current_bist;
287 #endif
288 const efx_mac_ops_t *ep_emop;
289 const efx_phy_ops_t *ep_epop;
290 } efx_port_t;
291
292 typedef struct efx_mon_ops_s {
293 #if EFSYS_OPT_MON_STATS
294 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
295 efx_mon_stat_value_t *);
296 #endif /* EFSYS_OPT_MON_STATS */
297 } efx_mon_ops_t;
298
299 typedef struct efx_mon_s {
300 efx_mon_type_t em_type;
301 const efx_mon_ops_t *em_emop;
302 } efx_mon_t;
303
304 typedef struct efx_intr_ops_s {
305 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
306 void (*eio_enable)(efx_nic_t *);
307 void (*eio_disable)(efx_nic_t *);
308 void (*eio_disable_unlocked)(efx_nic_t *);
309 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
310 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
311 void (*eio_status_message)(efx_nic_t *, unsigned int,
312 boolean_t *);
313 void (*eio_fatal)(efx_nic_t *);
314 void (*eio_fini)(efx_nic_t *);
315 } efx_intr_ops_t;
316
317 typedef struct efx_intr_s {
318 const efx_intr_ops_t *ei_eiop;
319 efsys_mem_t *ei_esmp;
320 efx_intr_type_t ei_type;
321 unsigned int ei_level;
322 } efx_intr_t;
323
324 typedef struct efx_nic_ops_s {
325 efx_rc_t (*eno_probe)(efx_nic_t *);
326 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
327 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
328 efx_rc_t (*eno_reset)(efx_nic_t *);
329 efx_rc_t (*eno_init)(efx_nic_t *);
330 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
331 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
332 uint32_t *, size_t *);
333 #if EFSYS_OPT_DIAG
334 efx_rc_t (*eno_register_test)(efx_nic_t *);
335 #endif /* EFSYS_OPT_DIAG */
336 void (*eno_fini)(efx_nic_t *);
337 void (*eno_unprobe)(efx_nic_t *);
338 } efx_nic_ops_t;
339
340 #ifndef EFX_TXQ_LIMIT_TARGET
341 #define EFX_TXQ_LIMIT_TARGET 259
342 #endif
343 #ifndef EFX_RXQ_LIMIT_TARGET
344 #define EFX_RXQ_LIMIT_TARGET 512
345 #endif
346 #ifndef EFX_TXQ_DC_SIZE
347 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
348 #endif
349 #ifndef EFX_RXQ_DC_SIZE
350 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
351 #endif
352
353 #if EFSYS_OPT_FILTER
354
355 typedef struct siena_filter_spec_s {
356 uint8_t sfs_type;
357 uint32_t sfs_flags;
358 uint32_t sfs_dmaq_id;
359 uint32_t sfs_dword[3];
360 } siena_filter_spec_t;
361
362 typedef enum siena_filter_type_e {
363 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
364 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
365 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
366 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
367 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
368 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
369
370 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
371 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
372 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
373 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
374 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
375 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
376
377 EFX_SIENA_FILTER_NTYPES
378 } siena_filter_type_t;
379
380 typedef enum siena_filter_tbl_id_e {
381 EFX_SIENA_FILTER_TBL_RX_IP = 0,
382 EFX_SIENA_FILTER_TBL_RX_MAC,
383 EFX_SIENA_FILTER_TBL_TX_IP,
384 EFX_SIENA_FILTER_TBL_TX_MAC,
385 EFX_SIENA_FILTER_NTBLS
386 } siena_filter_tbl_id_t;
387
388 typedef struct siena_filter_tbl_s {
389 int sft_size; /* number of entries */
390 int sft_used; /* active count */
391 uint32_t *sft_bitmap; /* active bitmap */
392 siena_filter_spec_t *sft_spec; /* array of saved specs */
393 } siena_filter_tbl_t;
394
395 typedef struct siena_filter_s {
396 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
397 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
398 } siena_filter_t;
399
400 typedef struct efx_filter_s {
401 #if EFSYS_OPT_SIENA
402 siena_filter_t *ef_siena_filter;
403 #endif /* EFSYS_OPT_SIENA */
404 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
405 ef10_filter_table_t *ef_ef10_filter_table;
406 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
407 } efx_filter_t;
408
409 extern void
410 siena_filter_tbl_clear(
411 __in efx_nic_t *enp,
412 __in siena_filter_tbl_id_t tbl);
413
414 #endif /* EFSYS_OPT_FILTER */
415
416 #if EFSYS_OPT_MCDI
417
418 typedef struct efx_mcdi_ops_s {
419 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
420 void (*emco_send_request)(efx_nic_t *, void *, size_t,
421 void *, size_t);
422 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
423 boolean_t (*emco_poll_response)(efx_nic_t *);
424 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
425 void (*emco_fini)(efx_nic_t *);
426 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
427 } efx_mcdi_ops_t;
428
429 typedef struct efx_mcdi_s {
430 const efx_mcdi_ops_t *em_emcop;
431 const efx_mcdi_transport_t *em_emtp;
432 efx_mcdi_iface_t em_emip;
433 } efx_mcdi_t;
434
435 #endif /* EFSYS_OPT_MCDI */
436
437 #if EFSYS_OPT_NVRAM
438 typedef struct efx_nvram_ops_s {
439 #if EFSYS_OPT_DIAG
440 efx_rc_t (*envo_test)(efx_nic_t *);
441 #endif /* EFSYS_OPT_DIAG */
442 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
443 uint32_t *);
444 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
445 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
446 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
447 unsigned int, caddr_t, size_t);
448 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
449 unsigned int, size_t);
450 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
451 unsigned int, caddr_t, size_t);
452 void (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
453 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
454 uint32_t *, uint16_t *);
455 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
456 uint16_t *);
457 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
458 caddr_t, size_t);
459 } efx_nvram_ops_t;
460 #endif /* EFSYS_OPT_NVRAM */
461
462 extern __checkReturn efx_rc_t
463 efx_nvram_tlv_validate(
464 __in efx_nic_t *enp,
465 __in uint32_t partn,
466 __in_bcount(partn_size) caddr_t partn_data,
467 __in size_t partn_size);
468
469
470 #if EFSYS_OPT_VPD
471 typedef struct efx_vpd_ops_s {
472 efx_rc_t (*evpdo_init)(efx_nic_t *);
473 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
474 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
475 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
476 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
477 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
478 efx_vpd_value_t *);
479 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
480 efx_vpd_value_t *);
481 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
482 efx_vpd_value_t *, unsigned int *);
483 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
484 void (*evpdo_fini)(efx_nic_t *);
485 } efx_vpd_ops_t;
486 #endif /* EFSYS_OPT_VPD */
487
488 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
489
490 __checkReturn efx_rc_t
491 efx_mcdi_nvram_partitions(
492 __in efx_nic_t *enp,
493 __out_bcount(size) caddr_t data,
494 __in size_t size,
495 __out unsigned int *npartnp);
496
497 __checkReturn efx_rc_t
498 efx_mcdi_nvram_metadata(
499 __in efx_nic_t *enp,
500 __in uint32_t partn,
501 __out uint32_t *subtypep,
502 __out_ecount(4) uint16_t version[4],
503 __out_bcount_opt(size) char *descp,
504 __in size_t size);
505
506 __checkReturn efx_rc_t
507 efx_mcdi_nvram_info(
508 __in efx_nic_t *enp,
509 __in uint32_t partn,
510 __out_opt size_t *sizep,
511 __out_opt uint32_t *addressp,
512 __out_opt uint32_t *erase_sizep,
513 __out_opt uint32_t *write_sizep);
514
515 __checkReturn efx_rc_t
516 efx_mcdi_nvram_update_start(
517 __in efx_nic_t *enp,
518 __in uint32_t partn);
519
520 __checkReturn efx_rc_t
521 efx_mcdi_nvram_read(
522 __in efx_nic_t *enp,
523 __in uint32_t partn,
524 __in uint32_t offset,
525 __out_bcount(size) caddr_t data,
526 __in size_t size,
527 __in uint32_t mode);
528
529 __checkReturn efx_rc_t
530 efx_mcdi_nvram_erase(
531 __in efx_nic_t *enp,
532 __in uint32_t partn,
533 __in uint32_t offset,
534 __in size_t size);
535
536 __checkReturn efx_rc_t
537 efx_mcdi_nvram_write(
538 __in efx_nic_t *enp,
539 __in uint32_t partn,
540 __in uint32_t offset,
541 __out_bcount(size) caddr_t data,
542 __in size_t size);
543
544 __checkReturn efx_rc_t
545 efx_mcdi_nvram_update_finish(
546 __in efx_nic_t *enp,
547 __in uint32_t partn,
548 __in boolean_t reboot);
549
550 #if EFSYS_OPT_DIAG
551
552 __checkReturn efx_rc_t
553 efx_mcdi_nvram_test(
554 __in efx_nic_t *enp,
555 __in uint32_t partn);
556
557 #endif /* EFSYS_OPT_DIAG */
558
559 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
560
561 #if EFSYS_OPT_LICENSING
562
563 typedef struct efx_lic_ops_s {
564 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
565 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
566 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
567 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
568 size_t *, uint8_t *);
569 efx_rc_t (*elo_find_start)
570 (efx_nic_t *, caddr_t, size_t, uint32_t *);
571 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
572 uint32_t , uint32_t *);
573 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
574 uint32_t, uint32_t *, uint32_t *);
575 boolean_t (*elo_validate_key)(efx_nic_t *,
576 caddr_t, uint32_t);
577 efx_rc_t (*elo_read_key)(efx_nic_t *,
578 caddr_t, size_t, uint32_t, uint32_t,
579 caddr_t, size_t, uint32_t *);
580 efx_rc_t (*elo_write_key)(efx_nic_t *,
581 caddr_t, size_t, uint32_t,
582 caddr_t, uint32_t, uint32_t *);
583 efx_rc_t (*elo_delete_key)(efx_nic_t *,
584 caddr_t, size_t, uint32_t,
585 uint32_t, uint32_t, uint32_t *);
586 efx_rc_t (*elo_create_partition)(efx_nic_t *,
587 caddr_t, size_t);
588 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
589 caddr_t, size_t);
590 } efx_lic_ops_t;
591
592 #endif
593
594 typedef struct efx_drv_cfg_s {
595 uint32_t edc_min_vi_count;
596 uint32_t edc_max_vi_count;
597
598 uint32_t edc_max_piobuf_count;
599 uint32_t edc_pio_alloc_size;
600 } efx_drv_cfg_t;
601
602 struct efx_nic_s {
603 uint32_t en_magic;
604 efx_family_t en_family;
605 uint32_t en_features;
606 efsys_identifier_t *en_esip;
607 efsys_lock_t *en_eslp;
608 efsys_bar_t *en_esbp;
609 unsigned int en_mod_flags;
610 unsigned int en_reset_flags;
611 efx_nic_cfg_t en_nic_cfg;
612 efx_drv_cfg_t en_drv_cfg;
613 efx_port_t en_port;
614 efx_mon_t en_mon;
615 efx_intr_t en_intr;
616 uint32_t en_ev_qcount;
617 uint32_t en_rx_qcount;
618 uint32_t en_tx_qcount;
619 const efx_nic_ops_t *en_enop;
620 const efx_ev_ops_t *en_eevop;
621 const efx_tx_ops_t *en_etxop;
622 const efx_rx_ops_t *en_erxop;
623 #if EFSYS_OPT_FILTER
624 efx_filter_t en_filter;
625 const efx_filter_ops_t *en_efop;
626 #endif /* EFSYS_OPT_FILTER */
627 #if EFSYS_OPT_MCDI
628 efx_mcdi_t en_mcdi;
629 #endif /* EFSYS_OPT_MCDI */
630 #if EFSYS_OPT_NVRAM
631 efx_nvram_type_t en_nvram_locked;
632 const efx_nvram_ops_t *en_envop;
633 #endif /* EFSYS_OPT_NVRAM */
634 #if EFSYS_OPT_VPD
635 const efx_vpd_ops_t *en_evpdop;
636 #endif /* EFSYS_OPT_VPD */
637 #if EFSYS_OPT_RX_SCALE
638 efx_rx_hash_support_t en_hash_support;
639 efx_rx_scale_support_t en_rss_support;
640 uint32_t en_rss_context;
641 #endif /* EFSYS_OPT_RX_SCALE */
642 uint32_t en_vport_id;
643 #if EFSYS_OPT_LICENSING
644 const efx_lic_ops_t *en_elop;
645 #endif
646 union {
647 #if EFSYS_OPT_SIENA
648 struct {
649 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
650 unsigned int enu_partn_mask;
651 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
652 #if EFSYS_OPT_VPD
653 caddr_t enu_svpd;
654 size_t enu_svpd_length;
655 #endif /* EFSYS_OPT_VPD */
656 int enu_unused;
657 } siena;
658 #endif /* EFSYS_OPT_SIENA */
659 int enu_unused;
660 } en_u;
661 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
662 union en_arch {
663 struct {
664 int ena_vi_base;
665 int ena_vi_count;
666 int ena_vi_shift;
667 #if EFSYS_OPT_VPD
668 caddr_t ena_svpd;
669 size_t ena_svpd_length;
670 #endif /* EFSYS_OPT_VPD */
671 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
672 uint32_t ena_piobuf_count;
673 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
674 uint32_t ena_pio_write_vi_base;
675 /* Memory BAR mapping regions */
676 uint32_t ena_uc_mem_map_offset;
677 size_t ena_uc_mem_map_size;
678 uint32_t ena_wc_mem_map_offset;
679 size_t ena_wc_mem_map_size;
680 } ef10;
681 } en_arch;
682 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
683 };
684
685
686 #define EFX_NIC_MAGIC 0x02121996
687
688 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
689 const efx_ev_callbacks_t *, void *);
690
691 typedef struct efx_evq_rxq_state_s {
692 unsigned int eers_rx_read_ptr;
693 unsigned int eers_rx_mask;
694 } efx_evq_rxq_state_t;
695
696 struct efx_evq_s {
697 uint32_t ee_magic;
698 efx_nic_t *ee_enp;
699 unsigned int ee_index;
700 unsigned int ee_mask;
701 efsys_mem_t *ee_esmp;
702 #if EFSYS_OPT_QSTATS
703 uint32_t ee_stat[EV_NQSTATS];
704 #endif /* EFSYS_OPT_QSTATS */
705
706 efx_ev_handler_t ee_rx;
707 efx_ev_handler_t ee_tx;
708 efx_ev_handler_t ee_driver;
709 efx_ev_handler_t ee_global;
710 efx_ev_handler_t ee_drv_gen;
711 #if EFSYS_OPT_MCDI
712 efx_ev_handler_t ee_mcdi;
713 #endif /* EFSYS_OPT_MCDI */
714
715 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
716 };
717
718 #define EFX_EVQ_MAGIC 0x08081997
719
720 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
721
722 struct efx_rxq_s {
723 uint32_t er_magic;
724 efx_nic_t *er_enp;
725 efx_evq_t *er_eep;
726 unsigned int er_index;
727 unsigned int er_label;
728 unsigned int er_mask;
729 efsys_mem_t *er_esmp;
730 };
731
732 #define EFX_RXQ_MAGIC 0x15022005
733
734 struct efx_txq_s {
735 uint32_t et_magic;
736 efx_nic_t *et_enp;
737 unsigned int et_index;
738 unsigned int et_mask;
739 efsys_mem_t *et_esmp;
740 #if EFSYS_OPT_HUNTINGTON
741 uint32_t et_pio_bufnum;
742 uint32_t et_pio_blknum;
743 uint32_t et_pio_write_offset;
744 uint32_t et_pio_offset;
745 size_t et_pio_size;
746 #endif
747 #if EFSYS_OPT_QSTATS
748 uint32_t et_stat[TX_NQSTATS];
749 #endif /* EFSYS_OPT_QSTATS */
750 };
751
752 #define EFX_TXQ_MAGIC 0x05092005
753
754 #define EFX_MAC_ADDR_COPY(_dst, _src) \
755 do { \
756 (_dst)[0] = (_src)[0]; \
757 (_dst)[1] = (_src)[1]; \
758 (_dst)[2] = (_src)[2]; \
759 (_dst)[3] = (_src)[3]; \
760 (_dst)[4] = (_src)[4]; \
761 (_dst)[5] = (_src)[5]; \
762 _NOTE(CONSTANTCONDITION) \
763 } while (B_FALSE)
764
765 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
766 do { \
767 uint16_t *_d = (void *)(_dst); \
768 _d[0] = 0xffff; \
769 _d[1] = 0xffff; \
770 _d[2] = 0xffff; \
771 _NOTE(CONSTANTCONDITION) \
772 } while (B_FALSE)
773
774 #if EFSYS_OPT_CHECK_REG
775 #define EFX_CHECK_REG(_enp, _reg) \
776 do { \
777 const char *name = #_reg; \
778 char min = name[4]; \
779 char max = name[5]; \
780 char rev; \
781 \
782 switch ((_enp)->en_family) { \
783 case EFX_FAMILY_SIENA: \
784 rev = 'C'; \
785 break; \
786 \
787 case EFX_FAMILY_HUNTINGTON: \
788 rev = 'D'; \
789 break; \
790 \
791 case EFX_FAMILY_MEDFORD: \
792 rev = 'E'; \
793 break; \
794 \
795 default: \
796 rev = '?'; \
797 break; \
798 } \
799 \
800 EFSYS_ASSERT3S(rev, >=, min); \
801 EFSYS_ASSERT3S(rev, <=, max); \
802 \
803 _NOTE(CONSTANTCONDITION) \
804 } while (B_FALSE)
805 #else
806 #define EFX_CHECK_REG(_enp, _reg) do { \
807 _NOTE(CONSTANTCONDITION) \
808 } while(B_FALSE)
809 #endif
810
811 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
812 do { \
813 EFX_CHECK_REG((_enp), (_reg)); \
814 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
815 (_edp), (_lock)); \
816 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
817 uint32_t, _reg ## _OFST, \
818 uint32_t, (_edp)->ed_u32[0]); \
819 _NOTE(CONSTANTCONDITION) \
820 } while (B_FALSE)
821
822 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
823 do { \
824 EFX_CHECK_REG((_enp), (_reg)); \
825 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
826 uint32_t, _reg ## _OFST, \
827 uint32_t, (_edp)->ed_u32[0]); \
828 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
829 (_edp), (_lock)); \
830 _NOTE(CONSTANTCONDITION) \
831 } while (B_FALSE)
832
833 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
834 do { \
835 EFX_CHECK_REG((_enp), (_reg)); \
836 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
837 (_eqp)); \
838 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
839 uint32_t, _reg ## _OFST, \
840 uint32_t, (_eqp)->eq_u32[1], \
841 uint32_t, (_eqp)->eq_u32[0]); \
842 _NOTE(CONSTANTCONDITION) \
843 } while (B_FALSE)
844
845 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
846 do { \
847 EFX_CHECK_REG((_enp), (_reg)); \
848 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
849 uint32_t, _reg ## _OFST, \
850 uint32_t, (_eqp)->eq_u32[1], \
851 uint32_t, (_eqp)->eq_u32[0]); \
852 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
853 (_eqp)); \
854 _NOTE(CONSTANTCONDITION) \
855 } while (B_FALSE)
856
857 #define EFX_BAR_READO(_enp, _reg, _eop) \
858 do { \
859 EFX_CHECK_REG((_enp), (_reg)); \
860 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
861 (_eop), B_TRUE); \
862 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
863 uint32_t, _reg ## _OFST, \
864 uint32_t, (_eop)->eo_u32[3], \
865 uint32_t, (_eop)->eo_u32[2], \
866 uint32_t, (_eop)->eo_u32[1], \
867 uint32_t, (_eop)->eo_u32[0]); \
868 _NOTE(CONSTANTCONDITION) \
869 } while (B_FALSE)
870
871 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
872 do { \
873 EFX_CHECK_REG((_enp), (_reg)); \
874 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
875 uint32_t, _reg ## _OFST, \
876 uint32_t, (_eop)->eo_u32[3], \
877 uint32_t, (_eop)->eo_u32[2], \
878 uint32_t, (_eop)->eo_u32[1], \
879 uint32_t, (_eop)->eo_u32[0]); \
880 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
881 (_eop), B_TRUE); \
882 _NOTE(CONSTANTCONDITION) \
883 } while (B_FALSE)
884
885 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
886 do { \
887 EFX_CHECK_REG((_enp), (_reg)); \
888 EFSYS_BAR_READD((_enp)->en_esbp, \
889 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
890 (_edp), (_lock)); \
891 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
892 uint32_t, (_index), \
893 uint32_t, _reg ## _OFST, \
894 uint32_t, (_edp)->ed_u32[0]); \
895 _NOTE(CONSTANTCONDITION) \
896 } while (B_FALSE)
897
898 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
899 do { \
900 EFX_CHECK_REG((_enp), (_reg)); \
901 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
902 uint32_t, (_index), \
903 uint32_t, _reg ## _OFST, \
904 uint32_t, (_edp)->ed_u32[0]); \
905 EFSYS_BAR_WRITED((_enp)->en_esbp, \
906 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
907 (_edp), (_lock)); \
908 _NOTE(CONSTANTCONDITION) \
909 } while (B_FALSE)
910
911 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
912 do { \
913 EFX_CHECK_REG((_enp), (_reg)); \
914 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
915 uint32_t, (_index), \
916 uint32_t, _reg ## _OFST, \
917 uint32_t, (_edp)->ed_u32[0]); \
918 EFSYS_BAR_WRITED((_enp)->en_esbp, \
919 (_reg ## _OFST + \
920 (2 * sizeof (efx_dword_t)) + \
921 ((_index) * _reg ## _STEP)), \
922 (_edp), (_lock)); \
923 _NOTE(CONSTANTCONDITION) \
924 } while (B_FALSE)
925
926 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
927 do { \
928 EFX_CHECK_REG((_enp), (_reg)); \
929 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
930 uint32_t, (_index), \
931 uint32_t, _reg ## _OFST, \
932 uint32_t, (_edp)->ed_u32[0]); \
933 EFSYS_BAR_WRITED((_enp)->en_esbp, \
934 (_reg ## _OFST + \
935 (3 * sizeof (efx_dword_t)) + \
936 ((_index) * _reg ## _STEP)), \
937 (_edp), (_lock)); \
938 _NOTE(CONSTANTCONDITION) \
939 } while (B_FALSE)
940
941 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
942 do { \
943 EFX_CHECK_REG((_enp), (_reg)); \
944 EFSYS_BAR_READQ((_enp)->en_esbp, \
945 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
946 (_eqp)); \
947 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
948 uint32_t, (_index), \
949 uint32_t, _reg ## _OFST, \
950 uint32_t, (_eqp)->eq_u32[1], \
951 uint32_t, (_eqp)->eq_u32[0]); \
952 _NOTE(CONSTANTCONDITION) \
953 } while (B_FALSE)
954
955 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
956 do { \
957 EFX_CHECK_REG((_enp), (_reg)); \
958 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
959 uint32_t, (_index), \
960 uint32_t, _reg ## _OFST, \
961 uint32_t, (_eqp)->eq_u32[1], \
962 uint32_t, (_eqp)->eq_u32[0]); \
963 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
964 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
965 (_eqp)); \
966 _NOTE(CONSTANTCONDITION) \
967 } while (B_FALSE)
968
969 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
970 do { \
971 EFX_CHECK_REG((_enp), (_reg)); \
972 EFSYS_BAR_READO((_enp)->en_esbp, \
973 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
974 (_eop), (_lock)); \
975 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
976 uint32_t, (_index), \
977 uint32_t, _reg ## _OFST, \
978 uint32_t, (_eop)->eo_u32[3], \
979 uint32_t, (_eop)->eo_u32[2], \
980 uint32_t, (_eop)->eo_u32[1], \
981 uint32_t, (_eop)->eo_u32[0]); \
982 _NOTE(CONSTANTCONDITION) \
983 } while (B_FALSE)
984
985 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
986 do { \
987 EFX_CHECK_REG((_enp), (_reg)); \
988 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
989 uint32_t, (_index), \
990 uint32_t, _reg ## _OFST, \
991 uint32_t, (_eop)->eo_u32[3], \
992 uint32_t, (_eop)->eo_u32[2], \
993 uint32_t, (_eop)->eo_u32[1], \
994 uint32_t, (_eop)->eo_u32[0]); \
995 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
996 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
997 (_eop), (_lock)); \
998 _NOTE(CONSTANTCONDITION) \
999 } while (B_FALSE)
1000
1001 /*
1002 * Allow drivers to perform optimised 128-bit doorbell writes.
1003 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1004 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1005 * the need for locking in the host, and are the only ones known to be safe to
1006 * use 128-bites write with.
1007 */
1008 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1009 do { \
1010 EFX_CHECK_REG((_enp), (_reg)); \
1011 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1012 const char *, \
1013 #_reg, \
1014 uint32_t, (_index), \
1015 uint32_t, _reg ## _OFST, \
1016 uint32_t, (_eop)->eo_u32[3], \
1017 uint32_t, (_eop)->eo_u32[2], \
1018 uint32_t, (_eop)->eo_u32[1], \
1019 uint32_t, (_eop)->eo_u32[0]); \
1020 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1021 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1022 (_eop)); \
1023 _NOTE(CONSTANTCONDITION) \
1024 } while (B_FALSE)
1025
1026 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1027 do { \
1028 unsigned int _new = (_wptr); \
1029 unsigned int _old = (_owptr); \
1030 \
1031 if ((_new) >= (_old)) \
1032 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1033 (_old) * sizeof (efx_desc_t), \
1034 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1035 else \
1036 /* \
1037 * It is cheaper to sync entire map than sync \
1038 * two parts especially when offset/size are \
1039 * ignored and entire map is synced in any case.\
1040 */ \
1041 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1042 0, \
1043 (_entries) * sizeof (efx_desc_t)); \
1044 _NOTE(CONSTANTCONDITION) \
1045 } while (B_FALSE)
1046
1047 extern __checkReturn efx_rc_t
1048 efx_nic_biu_test(
1049 __in efx_nic_t *enp);
1050
1051 extern __checkReturn efx_rc_t
1052 efx_mac_select(
1053 __in efx_nic_t *enp);
1054
1055 extern void
1056 efx_mac_multicast_hash_compute(
1057 __in_ecount(6*count) uint8_t const *addrs,
1058 __in int count,
1059 __out efx_oword_t *hash_low,
1060 __out efx_oword_t *hash_high);
1061
1062 extern __checkReturn efx_rc_t
1063 efx_phy_probe(
1064 __in efx_nic_t *enp);
1065
1066 extern void
1067 efx_phy_unprobe(
1068 __in efx_nic_t *enp);
1069
1070 #if EFSYS_OPT_VPD
1071
1072 /* VPD utility functions */
1073
1074 extern __checkReturn efx_rc_t
1075 efx_vpd_hunk_length(
1076 __in_bcount(size) caddr_t data,
1077 __in size_t size,
1078 __out size_t *lengthp);
1079
1080 extern __checkReturn efx_rc_t
1081 efx_vpd_hunk_verify(
1082 __in_bcount(size) caddr_t data,
1083 __in size_t size,
1084 __out_opt boolean_t *cksummedp);
1085
1086 extern __checkReturn efx_rc_t
1087 efx_vpd_hunk_reinit(
1088 __in_bcount(size) caddr_t data,
1089 __in size_t size,
1090 __in boolean_t wantpid);
1091
1092 extern __checkReturn efx_rc_t
1093 efx_vpd_hunk_get(
1094 __in_bcount(size) caddr_t data,
1095 __in size_t size,
1096 __in efx_vpd_tag_t tag,
1097 __in efx_vpd_keyword_t keyword,
1098 __out unsigned int *payloadp,
1099 __out uint8_t *paylenp);
1100
1101 extern __checkReturn efx_rc_t
1102 efx_vpd_hunk_next(
1103 __in_bcount(size) caddr_t data,
1104 __in size_t size,
1105 __out efx_vpd_tag_t *tagp,
1106 __out efx_vpd_keyword_t *keyword,
1107 __out_opt unsigned int *payloadp,
1108 __out_opt uint8_t *paylenp,
1109 __inout unsigned int *contp);
1110
1111 extern __checkReturn efx_rc_t
1112 efx_vpd_hunk_set(
1113 __in_bcount(size) caddr_t data,
1114 __in size_t size,
1115 __in efx_vpd_value_t *evvp);
1116
1117 #endif /* EFSYS_OPT_VPD */
1118
1119 #if EFSYS_OPT_DIAG
1120
1121 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1122
1123 typedef struct efx_register_set_s {
1124 unsigned int address;
1125 unsigned int step;
1126 unsigned int rows;
1127 efx_oword_t mask;
1128 } efx_register_set_t;
1129
1130 extern __checkReturn efx_rc_t
1131 efx_nic_test_registers(
1132 __in efx_nic_t *enp,
1133 __in efx_register_set_t *rsp,
1134 __in size_t count);
1135
1136 extern __checkReturn efx_rc_t
1137 efx_nic_test_tables(
1138 __in efx_nic_t *enp,
1139 __in efx_register_set_t *rsp,
1140 __in efx_pattern_type_t pattern,
1141 __in size_t count);
1142
1143 #endif /* EFSYS_OPT_DIAG */
1144
1145 #if EFSYS_OPT_MCDI
1146
1147 extern __checkReturn efx_rc_t
1148 efx_mcdi_set_workaround(
1149 __in efx_nic_t *enp,
1150 __in uint32_t type,
1151 __in boolean_t enabled,
1152 __out_opt uint32_t *flagsp);
1153
1154 extern __checkReturn efx_rc_t
1155 efx_mcdi_get_workarounds(
1156 __in efx_nic_t *enp,
1157 __out_opt uint32_t *implementedp,
1158 __out_opt uint32_t *enabledp);
1159
1160 #endif /* EFSYS_OPT_MCDI */
1161
1162 #ifdef __cplusplus
1163 }
1164 #endif
1165
1166 #endif /* _SYS_EFX_IMPL_H */