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--- old/usr/src/uts/common/sys/ddidmareq.h
+++ new/usr/src/uts/common/sys/ddidmareq.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 + * Copyright 2014 Garrett D'Amore <garrett@damore.org>
23 + *
22 24 * Copyright (c) 1990, 2010, Oracle and/or its affiliates. All rights reserved.
23 25 */
24 -/*
25 - * Copyright 2014 Garrett D'Amore <garrett@damore.org>
26 - */
27 26
28 27 #ifndef _SYS_DDIDMAREQ_H
29 28 #define _SYS_DDIDMAREQ_H
30 29
31 30 #ifdef __cplusplus
32 31 extern "C" {
33 32 #endif
34 33
35 34 /*
36 35 * Memory Objects
37 36 *
38 37 * Definitions of structures that can describe
39 38 * an object that can be mapped for DMA.
40 39 */
41 40
42 41 /*
43 42 * Structure describing a virtual address
44 43 */
45 44 struct v_address {
46 45 caddr_t v_addr; /* base virtual address */
47 46 struct as *v_as; /* pointer to address space */
48 47 void *v_priv; /* priv data for shadow I/O */
49 48 };
50 49
51 50 /*
52 51 * Structure describing a page-based address
53 52 */
54 53 struct pp_address {
55 54 /*
56 55 * A pointer to a circularly linked list of page structures.
57 56 */
58 57 struct page *pp_pp;
59 58 uint_t pp_offset; /* offset within first page */
60 59 };
61 60
62 61 /*
63 62 * Structure to describe a physical memory address.
64 63 */
65 64 struct phy_address {
66 65 ulong_t p_addr; /* base physical address */
67 66 ulong_t p_memtype; /* memory type */
68 67 };
69 68
70 69 /*
71 70 * Structure to describe an array DVMA addresses.
72 71 * Under normal circumstances, dv_nseg will be 1.
73 72 * dvs_start is always page aligned.
74 73 */
75 74 struct dvma_address {
76 75 size_t dv_off;
77 76 size_t dv_nseg;
78 77 struct dvmaseg {
79 78 uint64_t dvs_start;
80 79 size_t dvs_len;
81 80 } *dv_seg;
82 81 };
83 82
84 83 /*
85 84 * A union of all of the above structures.
86 85 *
87 86 * This union describes the relationship between
88 87 * the kind of an address description and an object.
89 88 */
90 89 typedef union {
91 90 struct v_address virt_obj; /* Some virtual address */
92 91 struct pp_address pp_obj; /* Some page-based address */
93 92 struct phy_address phys_obj; /* Some physical address */
94 93 struct dvma_address dvma_obj;
95 94 } ddi_dma_aobj_t;
96 95
97 96 /*
98 97 * DMA object types - used to select how the object
99 98 * being mapped is being addressed by the IU.
100 99 */
101 100 typedef enum {
102 101 DMA_OTYP_VADDR = 0, /* enforce starting value of zero */
103 102 DMA_OTYP_PAGES,
104 103 DMA_OTYP_PADDR,
105 104 DMA_OTYP_BUFVADDR,
106 105 DMA_OTYP_DVADDR
107 106 } ddi_dma_atyp_t;
108 107
109 108 /*
110 109 * A compact package to describe an object that is to be mapped for DMA.
111 110 */
112 111 typedef struct {
113 112 uint_t dmao_size; /* size, in bytes, of the object */
114 113 ddi_dma_atyp_t dmao_type; /* type of object */
115 114 ddi_dma_aobj_t dmao_obj; /* the object described */
116 115 } ddi_dma_obj_t;
117 116
118 117 /*
119 118 * DMA addressing limits.
120 119 *
121 120 * This structure describes the constraints that a particular device's
122 121 * DMA engine has to its parent so that the parent may correctly set
123 122 * things up for a DMA mapping. Each parent may in turn modify the
124 123 * constraints listed in a DMA request structure in order to describe
125 124 * to its parent any changed or additional constraints. The rules
126 125 * are that each parent may modify a constraint in order to further
127 126 * constrain things (e.g., picking a more limited address range than
128 127 * that permitted by the child), but that the parent may not ignore
129 128 * a child's constraints.
130 129 *
131 130 * A particular constraint that we do *not* address is whether or not
132 131 * a requested mapping is too large for a DMA engine's counter to
133 132 * correctly track. It is still up to each driver to explicitly handle
134 133 * transfers that are too large for its own hardware to deal with directly.
135 134 *
136 135 * The mapping routines that are cognizant of this structure will
137 136 * copy any user defined limits structure if they need to modify
138 137 * the fields (as alluded to above).
139 138 *
140 139 * A note as to how to define constraints:
141 140 *
142 141 * How you define the constraints for your device depends on how you
143 142 * define your device. For example, you may have an SBus card with a
144 143 * device on it that address only the bottom 16mb of virtual DMA space.
145 144 * However, if the card also has ancillary circuitry that pulls the high 8
146 145 * bits of address lines high, the more correct expression for your device
147 146 * is that it address [0xff000000..0xffffffff] rather than [0..0x00ffffff].
148 147 */
149 148 #if defined(__sparc)
150 149 typedef struct ddi_dma_lim {
151 150
152 151 /*
153 152 * Low range of 32 bit addressing capability.
154 153 */
155 154 uint_t dlim_addr_lo;
156 155
157 156 /*
158 157 * Upper inclusive bound of addressing capability. It is an
159 158 * inclusive boundary limit to allow for the addressing range
160 159 * [0..0xffffffff] to be specified in preference to [0..0].
161 160 */
162 161 uint_t dlim_addr_hi;
163 162
164 163 /*
165 164 * Inclusive upper bound with which The DMA engine's counter acts as
166 165 * a register.
167 166 *
168 167 * This handles the case where an upper portion of a DMA address
169 168 * register is a latch instead of being a full 32 bit register
170 169 * (e.g., the upper 8 bits may remain constant while the lower
171 170 * 24 bits are the real address register).
172 171 *
173 172 * This essentially gives a hint about segment limitations
174 173 * to the mapping routines.
175 174 */
176 175 uint_t dlim_cntr_max;
177 176
178 177 /*
179 178 * DMA burst sizes.
180 179 *
181 180 * At the time of a mapping request, this tag defines the possible
182 181 * DMA burst cycle sizes that the requestor's DMA engine can
183 182 * emit. The format of the data is binary encoding of burst sizes
184 183 * assumed to be powers of two. That is, if a DMA engine is capable
185 184 * of doing 1, 2, 4 and 16 byte transfers, the encoding would be 0x17.
186 185 *
187 186 * As the mapping request is handled by intervening nexi, the
188 187 * burstsizes value may be modified. Prior to enabling DMA for
189 188 * the specific device, the driver that owns the DMA engine should
190 189 * check (via ddi_dma_burstsizes(9F)) what the allowed burstsizes
191 190 * have become and program their DMA engine appropriately.
192 191 */
193 192 uint_t dlim_burstsizes;
194 193
195 194 /*
196 195 * Minimum effective DMA transfer size, in units of bytes.
197 196 *
198 197 * This value specifies the minimum effective granularity of the
199 198 * DMA engine. It is distinct from dlim_burtsizes in that it
200 199 * describes the minimum amount of access a DMA transfer will
201 200 * effect. dlim_burtsizes describes in what electrical fashion
202 201 * the DMA engine might perform its accesses, while dlim_minxfer
203 202 * describes the minimum amount of memory that can be touched by
204 203 * the DMA transfer.
205 204 *
206 205 * As the mapping request is handled by intervening nexi, the
207 206 * dlim_minxfer value may be modifed contingent upon the presence
208 207 * (and use) of I/O caches and DMA write buffers in between the
209 208 * DMA engine and the object that DMA is being performed on.
210 209 *
211 210 */
212 211 uint_t dlim_minxfer;
213 212
214 213 /*
215 214 * Expected average data rate for this DMA engine
216 215 * while transferring data.
217 216 *
218 217 * This is used as a hint for a number of operations that might
219 218 * want to know the possible optimal latency requirements of this
220 219 * device. A value of zero will be interpreted as a 'do not care'.
221 220 */
222 221 uint_t dlim_dmaspeed;
223 222
224 223 } ddi_dma_lim_t;
225 224
226 225 #elif defined(__x86)
227 226
228 227 /*
229 228 * values for dlim_minxfer
230 229 */
231 230 #define DMA_UNIT_8 1
232 231 #define DMA_UNIT_16 2
233 232 #define DMA_UNIT_32 4
234 233
235 234 /*
236 235 * Version number
237 236 */
238 237 #define DMALIM_VER0 ((0x86000000) + 0)
239 238
240 239 typedef struct ddi_dma_lim {
241 240
242 241 /*
243 242 * Low range of 32 bit addressing capability.
244 243 */
245 244 uint_t dlim_addr_lo;
246 245
247 246 /*
248 247 * Upper Inclusive bound of 32 bit addressing capability.
249 248 *
250 249 * The ISA nexus restricts this to 0x00ffffff, since this bus has
251 250 * only 24 address lines. This enforces the 16 Mb address limitation.
252 251 * The EISA nexus restricts this to 0xffffffff.
253 252 */
254 253 uint_t dlim_addr_hi;
255 254
256 255 /*
257 256 * DMA engine counter not used; set to 0
258 257 */
259 258 uint_t dlim_cntr_max;
260 259
261 260 /*
262 261 * DMA burst sizes not used; set to 1
263 262 */
264 263 uint_t dlim_burstsizes;
265 264
266 265 /*
267 266 * Minimum effective DMA transfer size.
268 267 *
269 268 * This value specifies the minimum effective granularity of the
270 269 * DMA engine. It is distinct from dlim_burstsizes in that it
271 270 * describes the minimum amount of access a DMA transfer will
272 271 * effect. dlim_burstsizes describes in what electrical fashion
273 272 * the DMA engine might perform its accesses, while dlim_minxfer
274 273 * describes the minimum amount of memory that can be touched by
275 274 * the DMA transfer.
276 275 *
277 276 * This value also implies the required address alignment.
278 277 * The number of bytes transferred is assumed to be
279 278 * dlim_minxfer * (DMA engine count)
280 279 *
281 280 * It should be set to DMA_UNIT_8, DMA_UNIT_16, or DMA_UNIT_32.
282 281 */
283 282 uint_t dlim_minxfer;
284 283
285 284 /*
286 285 * Expected average data rate for this DMA engine
287 286 * while transferring data.
288 287 *
289 288 * This is used as a hint for a number of operations that might
290 289 * want to know the possible optimal latency requirements of this
291 290 * device. A value of zero will be interpreted as a 'do not care'.
292 291 */
293 292 uint_t dlim_dmaspeed;
294 293
295 294
296 295 /*
297 296 * Version number of this structure
298 297 */
299 298 uint_t dlim_version; /* = 0x86 << 24 + 0 */
300 299
301 300 /*
302 301 * Inclusive upper bound with which the DMA engine's Address acts as
303 302 * a register.
304 303 * This handles the case where an upper portion of a DMA address
305 304 * register is a latch instead of being a full 32 bit register
306 305 * (e.g., the upper 16 bits remain constant while the lower 16 bits
307 306 * are incremented for each DMA transfer).
308 307 *
309 308 * The ISA nexus restricts only 3rd-party DMA requests to 0x0000ffff,
310 309 * since the ISA DMA engine has a 16-bit register for low address and
311 310 * an 8-bit latch for high address. This enforces the first 64 Kb
312 311 * limitation (address boundary).
313 312 * The EISA nexus restricts only 3rd-party DMA requests to 0xffffffff.
314 313 */
315 314 uint_t dlim_adreg_max;
316 315
317 316 /*
318 317 * Maximum transfer count that the DMA engine can handle.
319 318 *
320 319 * The ISA nexus restricts only 3rd-party DMA requests to 0x0000ffff,
321 320 * since the ISA DMA engine has a 16-bit register for counting.
322 321 * This enforces the other 64 Kb limitation (count size).
323 322 * The EISA nexus restricts only 3rd-party DMA requests to 0x00ffffff,
324 323 * since the EISA DMA engine has a 24-bit register for counting.
325 324 *
326 325 * This transfer count limitation is a per segment limitation.
327 326 * It can also be used to restrict the size of segments.
328 327 *
329 328 * This is used as a bit mask, so it must be a power of 2, minus 1.
330 329 */
331 330 uint_t dlim_ctreg_max;
332 331
333 332 /*
334 333 * Granularity of DMA transfer, in units of bytes.
335 334 *
336 335 * Breakup sizes must be multiples of this value.
337 336 * If no scatter/gather capabilty is specified, then the size of
338 337 * each DMA transfer must be a multiple of this value.
339 338 *
340 339 * If there is scatter/gather capability, then a single cookie cannot
341 340 * be smaller in size than the minimum xfer value, and may be less
342 341 * than the granularity value. The total transfer length of the
343 342 * scatter/gather list should be a multiple of the granularity value;
344 343 * use dlim_sgllen to specify the length of the scatter/gather list.
345 344 *
346 345 * This value should be equal to the sector size of the device.
347 346 */
348 347 uint_t dlim_granular;
349 348
350 349 /*
351 350 * Length of scatter/gather list
352 351 *
353 352 * This value specifies the number of segments or cookies that a DMA
354 353 * engine can consume in one i/o request to the device. For 3rd-party
355 354 * DMA that uses the bus nexus this should be set to 1. Devices with
356 355 * 1st-party DMA capability should specify the number of entries in
357 356 * its scatter/gather list. The breakup routine will ensure that each
358 357 * group of dlim_sgllen cookies (within a DMA window) will have a
359 358 * total transfer length that is a multiple of dlim_granular.
360 359 *
361 360 * < 0 : tbd
362 361 * = 0 : breakup is for PIO.
363 362 * = 1 : breakup is for DMA engine with no scatter/gather
364 363 * capability.
365 364 * >= 2 : breakup is for DMA engine with scatter/gather
366 365 * capability; value is max number of entries in list.
367 366 *
368 367 * Note that this list length is not dependent on the DMA window
369 368 * size. The size of the DMA window is based on resources consumed,
370 369 * such as intermediate buffers. Several s/g lists may exist within
371 370 * a window. But the end of a window does imply the end of the s/g
372 371 * list.
373 372 */
374 373 short dlim_sgllen;
375 374
376 375 /*
377 376 * Size of device i/o request
378 377 *
379 378 * This value indicates the maximum number of bytes the device
380 379 * can transmit/receive for one i/o command. This limitation is
381 380 * significant ony if it is less than (dlim_ctreg_max * dlim_sgllen).
382 381 */
383 382 uint_t dlim_reqsize;
384 383
385 384 } ddi_dma_lim_t;
386 385
387 386 #else
388 387 #error "struct ddi_dma_lim not defined for this architecture"
389 388 #endif /* defined(__sparc) */
390 389
391 390 /*
392 391 * Flags definition for dma_attr_flags
393 392 */
394 393
395 394 /*
396 395 * return physical DMA address on platforms
397 396 * which support DVMA
398 397 */
399 398 #define DDI_DMA_FORCE_PHYSICAL 0x0100
400 399
401 400 /*
402 401 * An error will be flagged for DMA data path errors
403 402 */
404 403 #define DDI_DMA_FLAGERR 0x200
405 404
406 405 /*
407 406 * Enable relaxed ordering
408 407 */
409 408 #define DDI_DMA_RELAXED_ORDERING 0x400
410 409
411 410
412 411 /*
413 412 * Consolidation private x86 only flag which will cause a bounce buffer
414 413 * (paddr < dma_attr_seg) to be used if the buffer passed to the bind
415 414 * operation contains pages both above and below dma_attr_seg. If this flag
416 415 * is set, dma_attr_seg must be <= dma_attr_addr_hi.
417 416 */
418 417 #define _DDI_DMA_BOUNCE_ON_SEG 0x8000
419 418
420 419 #define DMA_ATTR_V0 0
421 420 #define DMA_ATTR_VERSION DMA_ATTR_V0
422 421
423 422 typedef struct ddi_dma_attr {
424 423 uint_t dma_attr_version; /* version number */
425 424 uint64_t dma_attr_addr_lo; /* low DMA address range */
426 425 uint64_t dma_attr_addr_hi; /* high DMA address range */
427 426 uint64_t dma_attr_count_max; /* DMA counter register */
428 427 uint64_t dma_attr_align; /* DMA address alignment */
429 428 uint_t dma_attr_burstsizes; /* DMA burstsizes */
430 429 uint32_t dma_attr_minxfer; /* min effective DMA size */
431 430 uint64_t dma_attr_maxxfer; /* max DMA xfer size */
432 431 uint64_t dma_attr_seg; /* segment boundary */
433 432 int dma_attr_sgllen; /* s/g length */
434 433 uint32_t dma_attr_granular; /* granularity of device */
435 434 uint_t dma_attr_flags; /* Bus specific DMA flags */
436 435 } ddi_dma_attr_t;
437 436
438 437 /*
439 438 * Handy macro to set a maximum bit value (should be elsewhere)
440 439 *
441 440 * Clear off all bits lower then 'mybit' in val; if there are no
442 441 * bits higher than or equal to mybit in val then set mybit. Assumes
443 442 * mybit equals some power of 2 and is not zero.
444 443 */
445 444 #define maxbit(val, mybit) \
446 445 ((val) & ~((mybit)-1)) | ((((val) & ~((mybit)-1)) == 0) ? (mybit) : 0)
447 446
448 447 /*
449 448 * Handy macro to set a minimum bit value (should be elsewhere)
450 449 *
451 450 * Clear off all bits higher then 'mybit' in val; if there are no
452 451 * bits lower than or equal to mybit in val then set mybit. Assumes
453 452 * mybit equals some pow2 and is not zero.
454 453 */
455 454 #define minbit(val, mybit) \
456 455 (((val)&((mybit)|((mybit)-1))) | \
457 456 ((((val) & ((mybit)-1)) == 0) ? (mybit) : 0))
458 457
459 458 /*
460 459 * Structure of a request to map an object for DMA.
461 460 */
462 461 typedef struct ddi_dma_req {
463 462 /*
464 463 * Caller's DMA engine constraints.
465 464 *
466 465 * If there are no particular constraints to the caller's DMA
467 466 * engine, this field may be set to NULL. The implementation DMA
468 467 * setup functions will then select a set of standard beginning
469 468 * constraints.
470 469 *
471 470 * In either case, as the mapping proceeds, the initial DMA
472 471 * constraints may become more restrictive as each intervening
473 472 * nexus might add further restrictions.
474 473 */
475 474 ddi_dma_lim_t *dmar_limits;
476 475
477 476 /*
478 477 * Contains the information passed to the DMA mapping allocation
479 478 * routine(s).
480 479 */
481 480 uint_t dmar_flags;
482 481
483 482 /*
484 483 * Callback function. A caller of the DMA mapping functions must
485 484 * specify by filling in this field whether the allocation routines
486 485 * can sleep awaiting mapping resources, must *not* sleep awaiting
487 486 * resources, or may *not* sleep awaiting any resources and must
488 487 * call the function specified by dmar_fp with the the argument
489 488 * dmar_arg when resources might have become available at a future
490 489 * time.
491 490 */
492 491 int (*dmar_fp)();
493 492
494 493 caddr_t dmar_arg; /* Callback function argument */
495 494
496 495 /*
497 496 * Description of the object to be mapped for DMA.
498 497 * Must be last in this structure in case that the
499 498 * union ddi_dma_obj_t changes in the future.
500 499 */
501 500 ddi_dma_obj_t dmar_object;
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502 501
503 502 } ddi_dma_req_t;
504 503
505 504 /*
506 505 * Defines for the DMA mapping allocation functions
507 506 *
508 507 * If a DMA callback funtion is set to anything other than the following
509 508 * defines then it is assumed that one wishes a callback and is providing
510 509 * a function address.
511 510 */
512 -#ifdef __STDC__
513 511 #define DDI_DMA_DONTWAIT ((int (*)(caddr_t))0)
514 512 #define DDI_DMA_SLEEP ((int (*)(caddr_t))1)
515 -#else
516 -#define DDI_DMA_DONTWAIT ((int (*)())0)
517 -#define DDI_DMA_SLEEP ((int (*)())1)
518 -#endif
519 513
520 514 /*
521 515 * Return values from callback functions.
522 516 */
523 517 #define DDI_DMA_CALLBACK_RUNOUT 0
524 518 #define DDI_DMA_CALLBACK_DONE 1
525 519
526 520 /*
527 521 * Flag definitions for the allocation functions.
528 522 */
529 523 #define DDI_DMA_WRITE 0x0001 /* Direction memory --> IO */
530 524 #define DDI_DMA_READ 0x0002 /* Direction IO --> memory */
531 525 #define DDI_DMA_RDWR (DDI_DMA_READ | DDI_DMA_WRITE)
532 526
533 527 /*
534 528 * If possible, establish a MMU redzone after the mapping (to protect
535 529 * against cheap DMA hardware that might get out of control).
536 530 */
537 531 #define DDI_DMA_REDZONE 0x0004
538 532
539 533 /*
540 534 * A partial allocation is allowed. That is, if the size of the object
541 535 * exceeds the mapping resources available, only map a portion of the
542 536 * object and return status indicating that this took place. The caller
543 537 * can use the functions ddi_dma_numwin(9F) and ddi_dma_getwin(9F) to
544 538 * change, at a later point, the actual mapped portion of the object.
545 539 *
546 540 * The mapped portion begins at offset 0 of the object.
547 541 *
548 542 */
549 543 #define DDI_DMA_PARTIAL 0x0008
550 544
551 545 /*
552 546 * Map the object for byte consistent access. Note that explicit
553 547 * synchronization (via ddi_dma_sync(9F)) will still be required.
554 548 * Consider this flag to be a hint to the mapping routines as to
555 549 * the intended use of the mapping.
556 550 *
557 551 * Normal data transfers can be usually consider to use 'streaming'
558 552 * modes of operations. They start at a specific point, transfer a
559 553 * fairly large amount of data sequentially, and then stop (usually
560 554 * on a well aligned boundary).
561 555 *
562 556 * Control mode data transfers (for memory resident device control blocks,
563 557 * e.g., ethernet message descriptors) do not access memory in such
564 558 * a streaming sequential fashion. Instead, they tend to modify a few
565 559 * words or bytes, move around and maybe modify a few more.
566 560 *
567 561 * There are many machine implementations that make this difficult to
568 562 * control in a generic and seamless fashion. Therefore, explicit synch-
569 563 * ronization steps (via ddi_dma_sync(9F)) are still required (even if you
570 564 * ask for a byte-consistent mapping) in order to make the view of the
571 565 * memory object shared between a CPU and a DMA master in consistent.
572 566 * However, judicious use of this flag can give sufficient hints to
573 567 * the mapping routines to attempt to pick the most efficacious mapping
574 568 * such that the synchronization steps are as efficient as possible.
575 569 *
576 570 */
577 571 #define DDI_DMA_CONSISTENT 0x0010
578 572
579 573 /*
580 574 * Some DMA mappings have to be 'exclusive' access.
581 575 */
582 576 #define DDI_DMA_EXCLUSIVE 0x0020
583 577
584 578 /*
585 579 * Sequential, unidirectional, block-sized and block aligned transfers
586 580 */
587 581 #define DDI_DMA_STREAMING 0x0040
588 582
589 583 /*
590 584 * Support for 64-bit SBus devices
591 585 */
592 586 #define DDI_DMA_SBUS_64BIT 0x2000
593 587
594 588 /*
595 589 * Return values from the mapping allocation functions.
596 590 */
597 591
598 592 /*
599 593 * succeeded in satisfying request
600 594 */
601 595 #define DDI_DMA_MAPPED 0
602 596
603 597 /*
604 598 * Mapping is legitimate (for advisory calls).
605 599 */
606 600 #define DDI_DMA_MAPOK 0
607 601
608 602 /*
609 603 * Succeeded in mapping a portion of the request.
610 604 */
611 605 #define DDI_DMA_PARTIAL_MAP 1
612 606
613 607 /*
614 608 * indicates end of window/segment list
615 609 */
616 610 #define DDI_DMA_DONE 2
617 611
618 612 /*
619 613 * No resources to map request.
620 614 */
621 615 #define DDI_DMA_NORESOURCES -1
622 616
623 617 /*
624 618 * Can't establish a mapping to the specified object
625 619 * (no specific reason).
626 620 */
627 621 #define DDI_DMA_NOMAPPING -2
628 622
629 623 /*
630 624 * The request is too big to be mapped.
631 625 */
632 626 #define DDI_DMA_TOOBIG -3
633 627
634 628 /*
635 629 * The request is too small to be mapped.
636 630 */
637 631 #define DDI_DMA_TOOSMALL -4
638 632
639 633 /*
640 634 * The request cannot be mapped because the object
641 635 * is locked against mapping by another DMA master.
642 636 */
643 637 #define DDI_DMA_LOCKED -5
644 638
645 639 /*
646 640 * The request cannot be mapped because the limits
647 641 * structure has bogus values.
648 642 */
649 643 #define DDI_DMA_BADLIMITS -6
650 644
651 645 /*
652 646 * the segment/window pointer is stale
653 647 */
654 648 #define DDI_DMA_STALE -7
655 649
656 650 /*
657 651 * The system can't allocate DMA resources using
658 652 * the given DMA attributes
659 653 */
660 654 #define DDI_DMA_BADATTR -8
661 655
662 656 /*
663 657 * A DMA handle is already used for a DMA
664 658 */
665 659 #define DDI_DMA_INUSE -9
666 660
667 661
668 662 /*
669 663 * DVMA disabled or not supported. use physical DMA
670 664 */
671 665 #define DDI_DMA_USE_PHYSICAL -10
672 666
673 667
674 668 /*
675 669 * In order for the access to a memory object to be consistent
676 670 * between a device and a CPU, the function ddi_dma_sync(9F)
677 671 * must be called upon the DMA handle. The following flags
678 672 * define whose view of the object should be made consistent.
679 673 * There are different flags here because on different machines
680 674 * there are definite performance implications of how long
681 675 * such synchronization takes.
682 676 *
683 677 * DDI_DMA_SYNC_FORDEV makes all device references to the object
684 678 * mapped by the DMA handle up to date. It should be used by a
685 679 * driver after a cpu modifies the memory object (over the range
686 680 * specified by the other arguments to the ddi_dma_sync(9F) call).
687 681 *
688 682 * DDI_DMA_SYNC_FORCPU makes all cpu references to the object
689 683 * mapped by the DMA handle up to date. It should be used
690 684 * by a driver after the receipt of data from the device to
691 685 * the memory object is done (over the range specified by
692 686 * the other arguments to the ddi_dma_sync(9F) call).
693 687 *
694 688 * If the only mapping that concerns the driver is one for the
695 689 * kernel (such as memory allocated by ddi_iopb_alloc(9F)), the
696 690 * flag DDI_DMA_SYNC_FORKERNEL can be used. This is a hint to the
697 691 * system that if it can synchronize the kernel's view faster
698 692 * that the CPU's view, it can do so, otherwise it acts the
699 693 * same as DDI_DMA_SYNC_FORCPU. DDI_DMA_SYNC_FORKERNEL might
700 694 * speed up the synchronization of kernel mappings in case of
701 695 * non IO-coherent CPU caches.
702 696 */
703 697 #define DDI_DMA_SYNC_FORDEV 0x0
704 698 #define DDI_DMA_SYNC_FORCPU 0x1
705 699 #define DDI_DMA_SYNC_FORKERNEL 0x2
706 700
707 701 /*
708 702 * Bus nexus control functions for DMA
709 703 */
710 704
711 705 /*
712 706 * Control operations, defined here so that devops.h can be included
713 707 * by drivers without having to include a specific SYSDDI implementation
714 708 * header file.
715 709 */
716 710
717 711 enum ddi_dma_ctlops {
718 712 DDI_DMA_FREE, /* obsolete - do not use */
719 713 DDI_DMA_SYNC, /* obsolete - do not use */
720 714 DDI_DMA_HTOC, /* obsolete - do not use */
721 715 DDI_DMA_KVADDR, /* obsolete - do not use */
722 716 DDI_DMA_MOVWIN, /* obsolete - do not use */
723 717 DDI_DMA_REPWIN, /* obsolete - do not use */
724 718 DDI_DMA_GETERR, /* obsolete - do not use */
725 719 DDI_DMA_COFF, /* obsolete - do not use */
726 720 DDI_DMA_NEXTWIN, /* obsolete - do not use */
727 721 DDI_DMA_NEXTSEG, /* obsolete - do not use */
728 722 DDI_DMA_SEGTOC, /* obsolete - do not use */
729 723 DDI_DMA_RESERVE, /* reserve some DVMA range */
730 724 DDI_DMA_RELEASE, /* free preallocated DVMA range */
731 725 DDI_DMA_RESETH, /* obsolete - do not use */
732 726 DDI_DMA_CKSYNC, /* obsolete - do not use */
733 727 DDI_DMA_IOPB_ALLOC, /* obsolete - do not use */
734 728 DDI_DMA_IOPB_FREE, /* obsolete - do not use */
735 729 DDI_DMA_SMEM_ALLOC, /* obsolete - do not use */
736 730 DDI_DMA_SMEM_FREE, /* obsolete - do not use */
737 731 DDI_DMA_SET_SBUS64, /* 64 bit SBus support */
738 732 DDI_DMA_REMAP, /* remap DVMA buffers after relocation */
739 733
740 734 /*
741 735 * control ops for DMA engine on motherboard
742 736 */
743 737 DDI_DMA_E_ACQUIRE, /* get channel for exclusive use */
744 738 DDI_DMA_E_FREE, /* release channel */
745 739 DDI_DMA_E_1STPTY, /* setup channel for 1st party DMA */
746 740 DDI_DMA_E_GETCB, /* get control block for DMA engine */
747 741 DDI_DMA_E_FREECB, /* free control blk for DMA engine */
748 742 DDI_DMA_E_PROG, /* program channel of DMA engine */
749 743 DDI_DMA_E_SWSETUP, /* setup channel for software control */
750 744 DDI_DMA_E_SWSTART, /* software operation of DMA channel */
751 745 DDI_DMA_E_ENABLE, /* enable channel of DMA engine */
752 746 DDI_DMA_E_STOP, /* stop a channel of DMA engine */
753 747 DDI_DMA_E_DISABLE, /* disable channel of DMA engine */
754 748 DDI_DMA_E_GETCNT, /* get remaining xfer count */
755 749 DDI_DMA_E_GETLIM, /* obsolete - do not use */
756 750 DDI_DMA_E_GETATTR /* get DMA engine attributes */
757 751 };
758 752
759 753 /*
760 754 * Cache attribute flags:
761 755 *
762 756 * IOMEM_DATA_CACHED
763 757 * The CPU can cache the data it fetches and push it to memory at a later
764 758 * time. This is the default attribute and used if no cache attributes is
765 759 * specified.
766 760 *
767 761 * IOMEM_DATA_UC_WR_COMBINE
768 762 * The CPU never caches the data but writes may occur out of order or be
769 763 * combined. It implies re-ordering.
770 764 *
771 765 * IOMEM_DATA_UNCACHED
772 766 * The CPU never caches the data and has uncacheable access to memory.
773 767 * It also implies strict ordering.
774 768 *
775 769 * The cache attributes are mutually exclusive, and any combination of the
776 770 * values leads to a failure. On the sparc architecture, only IOMEM_DATA_CACHED
777 771 * is meaningful, but others lead to a failure.
778 772 */
779 773 #define IOMEM_DATA_CACHED 0x10000 /* data is cached */
780 774 #define IOMEM_DATA_UC_WR_COMBINE 0x20000 /* data is not cached, but */
781 775 /* writes might be combined */
782 776 #define IOMEM_DATA_UNCACHED 0x40000 /* data is not cached. */
783 777 #define IOMEM_DATA_MASK 0xF0000 /* cache attrs mask */
784 778
785 779 /*
786 780 * Check if either uncacheable or write-combining specified. (those flags are
787 781 * mutually exclusive) This macro is used to override hat attributes if either
788 782 * one is set.
789 783 */
790 784 #define OVERRIDE_CACHE_ATTR(attr) \
791 785 (attr & (IOMEM_DATA_UNCACHED | IOMEM_DATA_UC_WR_COMBINE))
792 786
793 787 /*
794 788 * Get the cache attribute from flags. If there is no attributes,
795 789 * return IOMEM_DATA_CACHED (default attribute).
796 790 */
797 791 #define IOMEM_CACHE_ATTR(flags) \
798 792 ((flags & IOMEM_DATA_MASK) ? (flags & IOMEM_DATA_MASK) : \
799 793 IOMEM_DATA_CACHED)
800 794
801 795 #ifdef __cplusplus
802 796 }
803 797 #endif
804 798
805 799 #endif /* _SYS_DDIDMAREQ_H */
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