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4888 Undocument dma_req(9s)
4884 EOF scsi_hba_attach
4886 EOF ddi_dmae_getlim
4887 EOF ddi_iomin
4634 undocument scsi_hba_attach() and ddi_dma_lim(9s)
4630 clean stale references to ddi_iopb_alloc and ddi_iopb_free
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--- old/usr/src/uts/intel/ia32/os/ddi_i86.c
+++ new/usr/src/uts/intel/ia32/os/ddi_i86.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
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16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 +/*
27 + * Copyright 2014 Garrett D'Amore <garrett@damore.org>
28 + */
26 29
27 30 #include <sys/conf.h>
28 31 #include <sys/kmem.h>
29 32 #include <sys/ddi_impldefs.h>
30 33 #include <sys/ddi.h>
31 34 #include <sys/sunddi.h>
32 35 #include <sys/ddifm.h>
33 36 #include <sys/fm/io/ddi.h>
34 37 #include <sys/fm/protocol.h>
35 38 #include <sys/ontrap.h>
36 39
37 40
38 41 /*
39 42 * DDI DMA Engine functions for x86.
40 43 * These functions are more naturally generic, but do not apply to SPARC.
41 44 */
42 45
43 46 int
44 47 ddi_dmae_alloc(dev_info_t *dip, int chnl, int (*dmae_waitfp)(), caddr_t arg)
45 48 {
46 49 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_ACQUIRE,
47 50 (off_t *)dmae_waitfp, (size_t *)arg,
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48 51 (caddr_t *)(uintptr_t)chnl, 0));
49 52 }
50 53
51 54 int
52 55 ddi_dmae_release(dev_info_t *dip, int chnl)
53 56 {
54 57 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_FREE, 0, 0,
55 58 (caddr_t *)(uintptr_t)chnl, 0));
56 59 }
57 60
58 -int
59 -ddi_dmae_getlim(dev_info_t *dip, ddi_dma_lim_t *limitsp)
60 -{
61 - return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_GETLIM, 0, 0,
62 - (caddr_t *)limitsp, 0));
63 -}
64 -
65 61 int
66 62 ddi_dmae_getattr(dev_info_t *dip, ddi_dma_attr_t *attrp)
67 63 {
68 64 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_GETATTR, 0, 0,
69 65 (caddr_t *)attrp, 0));
70 66 }
71 67
72 68 int
73 69 ddi_dmae_1stparty(dev_info_t *dip, int chnl)
74 70 {
75 71 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_1STPTY, 0, 0,
76 72 (caddr_t *)(uintptr_t)chnl, 0));
77 73 }
78 74
79 75 int
80 76 ddi_dmae_prog(dev_info_t *dip, struct ddi_dmae_req *dmaereqp,
81 77 ddi_dma_cookie_t *cookiep, int chnl)
82 78 {
83 79 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_PROG, (off_t *)dmaereqp,
84 80 (size_t *)cookiep, (caddr_t *)(uintptr_t)chnl, 0));
85 81 }
86 82
87 83 int
88 84 ddi_dmae_swsetup(dev_info_t *dip, struct ddi_dmae_req *dmaereqp,
89 85 ddi_dma_cookie_t *cookiep, int chnl)
90 86 {
91 87 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_SWSETUP, (off_t *)dmaereqp,
92 88 (size_t *)cookiep, (caddr_t *)(uintptr_t)chnl, 0));
93 89 }
94 90
95 91 int
96 92 ddi_dmae_swstart(dev_info_t *dip, int chnl)
97 93 {
98 94 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_SWSTART, 0, 0,
99 95 (caddr_t *)(uintptr_t)chnl, 0));
100 96 }
101 97
102 98 int
103 99 ddi_dmae_stop(dev_info_t *dip, int chnl)
104 100 {
105 101 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_STOP, 0, 0,
106 102 (caddr_t *)(uintptr_t)chnl, 0));
107 103 }
108 104
109 105 int
110 106 ddi_dmae_enable(dev_info_t *dip, int chnl)
111 107 {
112 108 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_ENABLE, 0, 0,
113 109 (caddr_t *)(uintptr_t)chnl, 0));
114 110 }
115 111
116 112 int
117 113 ddi_dmae_disable(dev_info_t *dip, int chnl)
118 114 {
119 115 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_DISABLE, 0, 0,
120 116 (caddr_t *)(uintptr_t)chnl, 0));
121 117 }
122 118
123 119 int
124 120 ddi_dmae_getcnt(dev_info_t *dip, int chnl, int *countp)
125 121 {
126 122 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_GETCNT, 0, (size_t *)countp,
127 123 (caddr_t *)(uintptr_t)chnl, 0));
128 124 }
129 125
130 126 /*
131 127 * implementation specific access handle and routines:
132 128 */
133 129
134 130 static uintptr_t impl_acc_hdl_id = 0;
135 131
136 132 /*
137 133 * access handle allocator
138 134 */
139 135 ddi_acc_hdl_t *
140 136 impl_acc_hdl_get(ddi_acc_handle_t hdl)
141 137 {
142 138 /*
143 139 * recast to ddi_acc_hdl_t instead of
144 140 * casting to ddi_acc_impl_t and then return the ah_platform_private
145 141 *
146 142 * this optimization based on the ddi_acc_hdl_t is the
147 143 * first member of the ddi_acc_impl_t.
148 144 */
149 145 return ((ddi_acc_hdl_t *)hdl);
150 146 }
151 147
152 148 ddi_acc_handle_t
153 149 impl_acc_hdl_alloc(int (*waitfp)(caddr_t), caddr_t arg)
154 150 {
155 151 ddi_acc_impl_t *hp;
156 152 on_trap_data_t *otp;
157 153 int sleepflag;
158 154
159 155 sleepflag = ((waitfp == (int (*)())KM_SLEEP) ? KM_SLEEP : KM_NOSLEEP);
160 156 /*
161 157 * Allocate and initialize the data access handle and error status.
162 158 */
163 159 if ((hp = kmem_zalloc(sizeof (ddi_acc_impl_t), sleepflag)) == NULL)
164 160 goto fail;
165 161 if ((hp->ahi_err = (ndi_err_t *)kmem_zalloc(
166 162 sizeof (ndi_err_t), sleepflag)) == NULL) {
167 163 kmem_free(hp, sizeof (ddi_acc_impl_t));
168 164 goto fail;
169 165 }
170 166 if ((otp = (on_trap_data_t *)kmem_zalloc(
171 167 sizeof (on_trap_data_t), sleepflag)) == NULL) {
172 168 kmem_free(hp->ahi_err, sizeof (ndi_err_t));
173 169 kmem_free(hp, sizeof (ddi_acc_impl_t));
174 170 goto fail;
175 171 }
176 172 hp->ahi_err->err_ontrap = otp;
177 173 hp->ahi_common.ah_platform_private = (void *)hp;
178 174
179 175 return ((ddi_acc_handle_t)hp);
180 176 fail:
181 177 if ((waitfp != (int (*)())KM_SLEEP) &&
182 178 (waitfp != (int (*)())KM_NOSLEEP))
183 179 ddi_set_callback(waitfp, arg, &impl_acc_hdl_id);
184 180 return (NULL);
185 181 }
186 182
187 183 void
188 184 impl_acc_hdl_free(ddi_acc_handle_t handle)
189 185 {
190 186 ddi_acc_impl_t *hp;
191 187
192 188 /*
193 189 * The supplied (ddi_acc_handle_t) is actually a (ddi_acc_impl_t *),
194 190 * because that's what we allocated in impl_acc_hdl_alloc() above.
195 191 */
196 192 hp = (ddi_acc_impl_t *)handle;
197 193 if (hp) {
198 194 kmem_free(hp->ahi_err->err_ontrap, sizeof (on_trap_data_t));
199 195 kmem_free(hp->ahi_err, sizeof (ndi_err_t));
200 196 kmem_free(hp, sizeof (ddi_acc_impl_t));
201 197 if (impl_acc_hdl_id)
202 198 ddi_run_callback(&impl_acc_hdl_id);
203 199 }
204 200 }
205 201
206 202 /*
207 203 * Function used to check if a given access handle owns the failing address.
208 204 * Called by ndi_fmc_error, when we detect a PIO error.
209 205 */
210 206 /* ARGSUSED */
211 207 static int
212 208 impl_acc_check(dev_info_t *dip, const void *handle, const void *addr,
213 209 const void *not_used)
214 210 {
215 211 pfn_t pfn, fault_pfn;
216 212 ddi_acc_hdl_t *hp;
217 213
218 214 hp = impl_acc_hdl_get((ddi_acc_handle_t)handle);
219 215
220 216 ASSERT(hp);
221 217
222 218 if (addr != NULL) {
223 219 pfn = hp->ah_pfn;
224 220 fault_pfn = mmu_btop(*(uint64_t *)addr);
225 221 if (fault_pfn >= pfn && fault_pfn < (pfn + hp->ah_pnum))
226 222 return (DDI_FM_NONFATAL);
227 223 }
228 224 return (DDI_FM_UNKNOWN);
229 225 }
230 226
231 227 void
232 228 impl_acc_err_init(ddi_acc_hdl_t *handlep)
233 229 {
234 230 int fmcap;
235 231 ndi_err_t *errp;
236 232 on_trap_data_t *otp;
237 233 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handlep;
238 234
239 235 fmcap = ddi_fm_capable(handlep->ah_dip);
240 236
241 237 if (handlep->ah_acc.devacc_attr_version < DDI_DEVICE_ATTR_V1 ||
242 238 !DDI_FM_ACC_ERR_CAP(fmcap)) {
243 239 handlep->ah_acc.devacc_attr_access = DDI_DEFAULT_ACC;
244 240 } else if (handlep->ah_acc.devacc_attr_access == DDI_FLAGERR_ACC &&
245 241 hp->ahi_scan == NULL) {
246 242 handlep->ah_acc.devacc_attr_access = DDI_DEFAULT_ACC;
247 243 } else if (DDI_FM_ACC_ERR_CAP(fmcap)) {
248 244 if (handlep->ah_acc.devacc_attr_access == DDI_DEFAULT_ACC) {
249 245 if (handlep->ah_xfermodes)
250 246 return;
251 247 i_ddi_drv_ereport_post(handlep->ah_dip, DVR_EFMCAP,
252 248 NULL, DDI_NOSLEEP);
253 249 } else {
254 250 errp = hp->ahi_err;
255 251 otp = (on_trap_data_t *)errp->err_ontrap;
256 252 otp->ot_handle = (void *)(hp);
257 253 otp->ot_prot = OT_DATA_ACCESS;
258 254 errp->err_status = DDI_FM_OK;
259 255 errp->err_expected = DDI_FM_ERR_UNEXPECTED;
260 256 errp->err_cf = impl_acc_check;
261 257 }
262 258 }
263 259 }
264 260
265 261 /* ARGSUSED */
266 262 int
267 263 impl_dma_check(dev_info_t *dip, const void *handle, const void *pci_hdl,
268 264 const void *not_used)
269 265 {
270 266 return (DDI_FM_UNKNOWN);
271 267 }
272 268
273 269 void
274 270 impl_acc_hdl_init(ddi_acc_hdl_t *handlep)
275 271 {
276 272 ddi_acc_impl_t *hp;
277 273 int fmcap;
278 274 int devacc_attr_access;
279 275
280 276 if (!handlep)
281 277 return;
282 278 fmcap = ddi_fm_capable(handlep->ah_dip);
283 279 if (handlep->ah_acc.devacc_attr_version < DDI_DEVICE_ATTR_V1 ||
284 280 !DDI_FM_ACC_ERR_CAP(fmcap))
285 281 devacc_attr_access = DDI_DEFAULT_ACC;
286 282 else
287 283 devacc_attr_access = handlep->ah_acc.devacc_attr_access;
288 284
289 285 hp = (ddi_acc_impl_t *)handlep->ah_platform_private;
290 286
291 287 /*
292 288 * Can only do FLAGERR if scan callback is set up. This should
293 289 * also guarantee that the peekpoke_mutex and err_mutex are defined.
294 290 */
295 291 if (devacc_attr_access == DDI_FLAGERR_ACC && hp->ahi_scan == NULL)
296 292 devacc_attr_access = DDI_DEFAULT_ACC;
297 293
298 294 switch (devacc_attr_access) {
299 295 case DDI_CAUTIOUS_ACC:
300 296 hp->ahi_get8 = i_ddi_caut_get8;
301 297 hp->ahi_put8 = i_ddi_caut_put8;
302 298 hp->ahi_rep_get8 = i_ddi_caut_rep_get8;
303 299 hp->ahi_rep_put8 = i_ddi_caut_rep_put8;
304 300 hp->ahi_get16 = i_ddi_caut_get16;
305 301 hp->ahi_get32 = i_ddi_caut_get32;
306 302 hp->ahi_put16 = i_ddi_caut_put16;
307 303 hp->ahi_put32 = i_ddi_caut_put32;
308 304 hp->ahi_rep_get16 = i_ddi_caut_rep_get16;
309 305 hp->ahi_rep_get32 = i_ddi_caut_rep_get32;
310 306 hp->ahi_rep_put16 = i_ddi_caut_rep_put16;
311 307 hp->ahi_rep_put32 = i_ddi_caut_rep_put32;
312 308 hp->ahi_get64 = i_ddi_caut_get64;
313 309 hp->ahi_put64 = i_ddi_caut_put64;
314 310 hp->ahi_rep_get64 = i_ddi_caut_rep_get64;
315 311 hp->ahi_rep_put64 = i_ddi_caut_rep_put64;
316 312 break;
317 313 case DDI_FLAGERR_ACC:
318 314 if (hp->ahi_acc_attr & DDI_ACCATTR_IO_SPACE) {
319 315 hp->ahi_get8 = i_ddi_prot_io_get8;
320 316 hp->ahi_put8 = i_ddi_prot_io_put8;
321 317 hp->ahi_rep_get8 = i_ddi_prot_io_rep_get8;
322 318 hp->ahi_rep_put8 = i_ddi_prot_io_rep_put8;
323 319
324 320 /* temporary set these 64 functions to no-ops */
325 321 hp->ahi_get64 = i_ddi_io_get64;
326 322 hp->ahi_put64 = i_ddi_io_put64;
327 323 hp->ahi_rep_get64 = i_ddi_io_rep_get64;
328 324 hp->ahi_rep_put64 = i_ddi_io_rep_put64;
329 325
330 326 /*
331 327 * check for BIG endian access
332 328 */
333 329 if (handlep->ah_acc.devacc_attr_endian_flags ==
334 330 DDI_STRUCTURE_BE_ACC) {
335 331 hp->ahi_get16 = i_ddi_prot_io_swap_get16;
336 332 hp->ahi_get32 = i_ddi_prot_io_swap_get32;
337 333 hp->ahi_put16 = i_ddi_prot_io_swap_put16;
338 334 hp->ahi_put32 = i_ddi_prot_io_swap_put32;
339 335 hp->ahi_rep_get16 =
340 336 i_ddi_prot_io_swap_rep_get16;
341 337 hp->ahi_rep_get32 =
342 338 i_ddi_prot_io_swap_rep_get32;
343 339 hp->ahi_rep_put16 =
344 340 i_ddi_prot_io_swap_rep_put16;
345 341 hp->ahi_rep_put32 =
346 342 i_ddi_prot_io_swap_rep_put32;
347 343 } else {
348 344 hp->ahi_acc_attr |= DDI_ACCATTR_DIRECT;
349 345 hp->ahi_get16 = i_ddi_prot_io_get16;
350 346 hp->ahi_get32 = i_ddi_prot_io_get32;
351 347 hp->ahi_put16 = i_ddi_prot_io_put16;
352 348 hp->ahi_put32 = i_ddi_prot_io_put32;
353 349 hp->ahi_rep_get16 = i_ddi_prot_io_rep_get16;
354 350 hp->ahi_rep_get32 = i_ddi_prot_io_rep_get32;
355 351 hp->ahi_rep_put16 = i_ddi_prot_io_rep_put16;
356 352 hp->ahi_rep_put32 = i_ddi_prot_io_rep_put32;
357 353 }
358 354
359 355 } else if (hp->ahi_acc_attr & DDI_ACCATTR_CPU_VADDR) {
360 356
361 357 hp->ahi_get8 = i_ddi_prot_vaddr_get8;
362 358 hp->ahi_put8 = i_ddi_prot_vaddr_put8;
363 359 hp->ahi_rep_get8 = i_ddi_prot_vaddr_rep_get8;
364 360 hp->ahi_rep_put8 = i_ddi_prot_vaddr_rep_put8;
365 361
366 362 /*
367 363 * check for BIG endian access
368 364 */
369 365 if (handlep->ah_acc.devacc_attr_endian_flags ==
370 366 DDI_STRUCTURE_BE_ACC) {
371 367
372 368 hp->ahi_get16 = i_ddi_prot_vaddr_swap_get16;
373 369 hp->ahi_get32 = i_ddi_prot_vaddr_swap_get32;
374 370 hp->ahi_get64 = i_ddi_prot_vaddr_swap_get64;
375 371 hp->ahi_put16 = i_ddi_prot_vaddr_swap_put16;
376 372 hp->ahi_put32 = i_ddi_prot_vaddr_swap_put32;
377 373 hp->ahi_put64 = i_ddi_prot_vaddr_swap_put64;
378 374 hp->ahi_rep_get16 =
379 375 i_ddi_prot_vaddr_swap_rep_get16;
380 376 hp->ahi_rep_get32 =
381 377 i_ddi_prot_vaddr_swap_rep_get32;
382 378 hp->ahi_rep_get64 =
383 379 i_ddi_prot_vaddr_swap_rep_get64;
384 380 hp->ahi_rep_put16 =
385 381 i_ddi_prot_vaddr_swap_rep_put16;
386 382 hp->ahi_rep_put32 =
387 383 i_ddi_prot_vaddr_swap_rep_put32;
388 384 hp->ahi_rep_put64 =
389 385 i_ddi_prot_vaddr_swap_rep_put64;
390 386 } else {
391 387 hp->ahi_acc_attr |= DDI_ACCATTR_DIRECT;
392 388 hp->ahi_get16 = i_ddi_prot_vaddr_get16;
393 389 hp->ahi_get32 = i_ddi_prot_vaddr_get32;
394 390 hp->ahi_get64 = i_ddi_prot_vaddr_get64;
395 391 hp->ahi_put16 = i_ddi_prot_vaddr_put16;
396 392 hp->ahi_put32 = i_ddi_prot_vaddr_put32;
397 393 hp->ahi_put64 = i_ddi_prot_vaddr_put64;
398 394 hp->ahi_rep_get16 = i_ddi_prot_vaddr_rep_get16;
399 395 hp->ahi_rep_get32 = i_ddi_prot_vaddr_rep_get32;
400 396 hp->ahi_rep_get64 = i_ddi_prot_vaddr_rep_get64;
401 397 hp->ahi_rep_put16 = i_ddi_prot_vaddr_rep_put16;
402 398 hp->ahi_rep_put32 = i_ddi_prot_vaddr_rep_put32;
403 399 hp->ahi_rep_put64 = i_ddi_prot_vaddr_rep_put64;
404 400 }
405 401 }
406 402 break;
407 403 case DDI_DEFAULT_ACC:
408 404 if (hp->ahi_acc_attr & DDI_ACCATTR_IO_SPACE) {
409 405 hp->ahi_get8 = i_ddi_io_get8;
410 406 hp->ahi_put8 = i_ddi_io_put8;
411 407 hp->ahi_rep_get8 = i_ddi_io_rep_get8;
412 408 hp->ahi_rep_put8 = i_ddi_io_rep_put8;
413 409
414 410 /* temporary set these 64 functions to no-ops */
415 411 hp->ahi_get64 = i_ddi_io_get64;
416 412 hp->ahi_put64 = i_ddi_io_put64;
417 413 hp->ahi_rep_get64 = i_ddi_io_rep_get64;
418 414 hp->ahi_rep_put64 = i_ddi_io_rep_put64;
419 415
420 416 /*
421 417 * check for BIG endian access
422 418 */
423 419 if (handlep->ah_acc.devacc_attr_endian_flags ==
424 420 DDI_STRUCTURE_BE_ACC) {
425 421 hp->ahi_get16 = i_ddi_io_swap_get16;
426 422 hp->ahi_get32 = i_ddi_io_swap_get32;
427 423 hp->ahi_put16 = i_ddi_io_swap_put16;
428 424 hp->ahi_put32 = i_ddi_io_swap_put32;
429 425 hp->ahi_rep_get16 = i_ddi_io_swap_rep_get16;
430 426 hp->ahi_rep_get32 = i_ddi_io_swap_rep_get32;
431 427 hp->ahi_rep_put16 = i_ddi_io_swap_rep_put16;
432 428 hp->ahi_rep_put32 = i_ddi_io_swap_rep_put32;
433 429 } else {
434 430 hp->ahi_acc_attr |= DDI_ACCATTR_DIRECT;
435 431 hp->ahi_get16 = i_ddi_io_get16;
436 432 hp->ahi_get32 = i_ddi_io_get32;
437 433 hp->ahi_put16 = i_ddi_io_put16;
438 434 hp->ahi_put32 = i_ddi_io_put32;
439 435 hp->ahi_rep_get16 = i_ddi_io_rep_get16;
440 436 hp->ahi_rep_get32 = i_ddi_io_rep_get32;
441 437 hp->ahi_rep_put16 = i_ddi_io_rep_put16;
442 438 hp->ahi_rep_put32 = i_ddi_io_rep_put32;
443 439 }
444 440
445 441 } else if (hp->ahi_acc_attr & DDI_ACCATTR_CPU_VADDR) {
446 442
447 443 hp->ahi_get8 = i_ddi_vaddr_get8;
448 444 hp->ahi_put8 = i_ddi_vaddr_put8;
449 445 hp->ahi_rep_get8 = i_ddi_vaddr_rep_get8;
450 446 hp->ahi_rep_put8 = i_ddi_vaddr_rep_put8;
451 447
452 448 /*
453 449 * check for BIG endian access
454 450 */
455 451 if (handlep->ah_acc.devacc_attr_endian_flags ==
456 452 DDI_STRUCTURE_BE_ACC) {
457 453
458 454 hp->ahi_get16 = i_ddi_vaddr_swap_get16;
459 455 hp->ahi_get32 = i_ddi_vaddr_swap_get32;
460 456 hp->ahi_get64 = i_ddi_vaddr_swap_get64;
461 457 hp->ahi_put16 = i_ddi_vaddr_swap_put16;
462 458 hp->ahi_put32 = i_ddi_vaddr_swap_put32;
463 459 hp->ahi_put64 = i_ddi_vaddr_swap_put64;
464 460 hp->ahi_rep_get16 = i_ddi_vaddr_swap_rep_get16;
465 461 hp->ahi_rep_get32 = i_ddi_vaddr_swap_rep_get32;
466 462 hp->ahi_rep_get64 = i_ddi_vaddr_swap_rep_get64;
467 463 hp->ahi_rep_put16 = i_ddi_vaddr_swap_rep_put16;
468 464 hp->ahi_rep_put32 = i_ddi_vaddr_swap_rep_put32;
469 465 hp->ahi_rep_put64 = i_ddi_vaddr_swap_rep_put64;
470 466 } else {
471 467 hp->ahi_acc_attr |= DDI_ACCATTR_DIRECT;
472 468 hp->ahi_get16 = i_ddi_vaddr_get16;
473 469 hp->ahi_get32 = i_ddi_vaddr_get32;
474 470 hp->ahi_get64 = i_ddi_vaddr_get64;
475 471 hp->ahi_put16 = i_ddi_vaddr_put16;
476 472 hp->ahi_put32 = i_ddi_vaddr_put32;
477 473 hp->ahi_put64 = i_ddi_vaddr_put64;
478 474 hp->ahi_rep_get16 = i_ddi_vaddr_rep_get16;
479 475 hp->ahi_rep_get32 = i_ddi_vaddr_rep_get32;
480 476 hp->ahi_rep_get64 = i_ddi_vaddr_rep_get64;
481 477 hp->ahi_rep_put16 = i_ddi_vaddr_rep_put16;
482 478 hp->ahi_rep_put32 = i_ddi_vaddr_rep_put32;
483 479 hp->ahi_rep_put64 = i_ddi_vaddr_rep_put64;
484 480 }
485 481 }
486 482 break;
487 483 }
488 484 hp->ahi_fault_check = i_ddi_acc_fault_check;
489 485 hp->ahi_fault_notify = i_ddi_acc_fault_notify;
490 486 hp->ahi_fault = 0;
491 487 impl_acc_err_init(handlep);
492 488 }
493 489
494 490 /*
495 491 * The followings are low-level routines for data access.
496 492 *
497 493 * All of these routines should be implemented in assembly. Those
498 494 * that have been rewritten be found in ~ml/ddi_i86_asm.s
499 495 */
500 496
501 497 /*ARGSUSED*/
502 498 uint16_t
503 499 i_ddi_vaddr_swap_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
504 500 {
505 501 return (ddi_swap16(*addr));
506 502 }
507 503
508 504 /*ARGSUSED*/
509 505 uint16_t
510 506 i_ddi_io_swap_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
511 507 {
512 508 return (ddi_swap16(inw((uintptr_t)addr)));
513 509 }
514 510
515 511 /*ARGSUSED*/
516 512 uint32_t
517 513 i_ddi_vaddr_swap_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
518 514 {
519 515 return (ddi_swap32(*addr));
520 516 }
521 517
522 518 /*ARGSUSED*/
523 519 uint32_t
524 520 i_ddi_io_swap_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
525 521 {
526 522 return (ddi_swap32(inl((uintptr_t)addr)));
527 523 }
528 524
529 525 /*ARGSUSED*/
530 526 uint64_t
531 527 i_ddi_vaddr_swap_get64(ddi_acc_impl_t *hdlp, uint64_t *addr)
532 528 {
533 529 return (ddi_swap64(*addr));
534 530 }
535 531
536 532 /*ARGSUSED*/
537 533 void
538 534 i_ddi_vaddr_swap_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value)
539 535 {
540 536 *addr = ddi_swap16(value);
541 537 }
542 538
543 539 /*ARGSUSED*/
544 540 void
545 541 i_ddi_io_swap_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value)
546 542 {
547 543 outw((uintptr_t)addr, ddi_swap16(value));
548 544 }
549 545
550 546 /*ARGSUSED*/
551 547 void
552 548 i_ddi_vaddr_swap_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value)
553 549 {
554 550 *addr = ddi_swap32(value);
555 551 }
556 552
557 553 /*ARGSUSED*/
558 554 void
559 555 i_ddi_io_swap_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value)
560 556 {
561 557 outl((uintptr_t)addr, ddi_swap32(value));
562 558 }
563 559
564 560 /*ARGSUSED*/
565 561 void
566 562 i_ddi_vaddr_swap_put64(ddi_acc_impl_t *hdlp, uint64_t *addr, uint64_t value)
567 563 {
568 564 *addr = ddi_swap64(value);
569 565 }
570 566
571 567 /*ARGSUSED*/
572 568 void
573 569 i_ddi_vaddr_rep_get8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
574 570 uint8_t *dev_addr, size_t repcount, uint_t flags)
575 571 {
576 572 uint8_t *h, *d;
577 573
578 574 h = host_addr;
579 575 d = dev_addr;
580 576
581 577 if (flags == DDI_DEV_AUTOINCR)
582 578 for (; repcount; repcount--)
583 579 *h++ = *d++;
584 580 else
585 581 for (; repcount; repcount--)
586 582 *h++ = *d;
587 583 }
588 584
589 585 /*ARGSUSED*/
590 586 void
591 587 i_ddi_vaddr_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
592 588 uint16_t *dev_addr, size_t repcount, uint_t flags)
593 589 {
594 590 uint16_t *h, *d;
595 591
596 592 h = host_addr;
597 593 d = dev_addr;
598 594
599 595 if (flags == DDI_DEV_AUTOINCR)
600 596 for (; repcount; repcount--)
601 597 *h++ = *d++;
602 598 else
603 599 for (; repcount; repcount--)
604 600 *h++ = *d;
605 601 }
606 602
607 603 /*ARGSUSED*/
608 604 void
609 605 i_ddi_vaddr_swap_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
610 606 uint16_t *dev_addr, size_t repcount, uint_t flags)
611 607 {
612 608 uint16_t *h, *d;
613 609
614 610 h = host_addr;
615 611 d = dev_addr;
616 612
617 613 if (flags == DDI_DEV_AUTOINCR)
618 614 for (; repcount; repcount--)
619 615 *h++ = ddi_swap16(*d++);
620 616 else
621 617 for (; repcount; repcount--)
622 618 *h++ = ddi_swap16(*d);
623 619 }
624 620
625 621 /*ARGSUSED*/
626 622 void
627 623 i_ddi_io_swap_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
628 624 uint16_t *dev_addr, size_t repcount, uint_t flags)
629 625 {
630 626 uint16_t *h;
631 627 uintptr_t port;
632 628
633 629 h = host_addr;
634 630 port = (uintptr_t)dev_addr;
635 631
636 632 if (flags == DDI_DEV_AUTOINCR)
637 633 for (; repcount; repcount--, port += 2)
638 634 *h++ = ddi_swap16(inw(port));
639 635 else
640 636 for (; repcount; repcount--)
641 637 *h++ = ddi_swap16(inw(port));
642 638 }
643 639
644 640 /*ARGSUSED*/
645 641 void
646 642 i_ddi_vaddr_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
647 643 uint32_t *dev_addr, size_t repcount, uint_t flags)
648 644 {
649 645 uint32_t *h, *d;
650 646
651 647 h = host_addr;
652 648 d = dev_addr;
653 649
654 650 if (flags == DDI_DEV_AUTOINCR)
655 651 for (; repcount; repcount--)
656 652 *h++ = *d++;
657 653 else
658 654 for (; repcount; repcount--)
659 655 *h++ = *d;
660 656 }
661 657
662 658 /*ARGSUSED*/
663 659 void
664 660 i_ddi_vaddr_swap_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
665 661 uint32_t *dev_addr, size_t repcount, uint_t flags)
666 662 {
667 663 uint32_t *h, *d;
668 664
669 665 h = host_addr;
670 666 d = dev_addr;
671 667
672 668 if (flags == DDI_DEV_AUTOINCR)
673 669 for (; repcount; repcount--)
674 670 *h++ = ddi_swap32(*d++);
675 671 else
676 672 for (; repcount; repcount--)
677 673 *h++ = ddi_swap32(*d);
678 674 }
679 675
680 676 /*ARGSUSED*/
681 677 void
682 678 i_ddi_io_swap_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
683 679 uint32_t *dev_addr, size_t repcount, uint_t flags)
684 680 {
685 681 uint32_t *h;
686 682 uintptr_t port;
687 683
688 684 h = host_addr;
689 685 port = (uintptr_t)dev_addr;
690 686
691 687 if (flags == DDI_DEV_AUTOINCR)
692 688 for (; repcount; repcount--, port += 4)
693 689 *h++ = ddi_swap32(inl(port));
694 690 else
695 691 for (; repcount; repcount--)
696 692 *h++ = ddi_swap32(inl(port));
697 693 }
698 694
699 695 /*ARGSUSED*/
700 696 void
701 697 i_ddi_vaddr_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
702 698 uint64_t *dev_addr, size_t repcount, uint_t flags)
703 699 {
704 700 uint64_t *h, *d;
705 701
706 702 h = host_addr;
707 703 d = dev_addr;
708 704
709 705 if (flags == DDI_DEV_AUTOINCR)
710 706 for (; repcount; repcount--)
711 707 *h++ = *d++;
712 708 else
713 709 for (; repcount; repcount--)
714 710 *h++ = *d;
715 711 }
716 712
717 713 /*ARGSUSED*/
718 714 void
719 715 i_ddi_vaddr_swap_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
720 716 uint64_t *dev_addr, size_t repcount, uint_t flags)
721 717 {
722 718 uint64_t *h, *d;
723 719
724 720 h = host_addr;
725 721 d = dev_addr;
726 722
727 723 if (flags == DDI_DEV_AUTOINCR)
728 724 for (; repcount; repcount--)
729 725 *h++ = ddi_swap64(*d++);
730 726 else
731 727 for (; repcount; repcount--)
732 728 *h++ = ddi_swap64(*d);
733 729 }
734 730
735 731 /*ARGSUSED*/
736 732 void
737 733 i_ddi_vaddr_rep_put8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
738 734 uint8_t *dev_addr, size_t repcount, uint_t flags)
739 735 {
740 736 uint8_t *h, *d;
741 737
742 738 h = host_addr;
743 739 d = dev_addr;
744 740
745 741 if (flags == DDI_DEV_AUTOINCR)
746 742 for (; repcount; repcount--)
747 743 *d++ = *h++;
748 744 else
749 745 for (; repcount; repcount--)
750 746 *d = *h++;
751 747 }
752 748
753 749 /*ARGSUSED*/
754 750 void
755 751 i_ddi_vaddr_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
756 752 uint16_t *dev_addr, size_t repcount, uint_t flags)
757 753 {
758 754 uint16_t *h, *d;
759 755
760 756 h = host_addr;
761 757 d = dev_addr;
762 758
763 759 if (flags == DDI_DEV_AUTOINCR)
764 760 for (; repcount; repcount--)
765 761 *d++ = *h++;
766 762 else
767 763 for (; repcount; repcount--)
768 764 *d = *h++;
769 765 }
770 766
771 767 /*ARGSUSED*/
772 768 void
773 769 i_ddi_vaddr_swap_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
774 770 uint16_t *dev_addr, size_t repcount, uint_t flags)
775 771 {
776 772 uint16_t *h, *d;
777 773
778 774 h = host_addr;
779 775 d = dev_addr;
780 776
781 777 if (flags == DDI_DEV_AUTOINCR)
782 778 for (; repcount; repcount--)
783 779 *d++ = ddi_swap16(*h++);
784 780 else
785 781 for (; repcount; repcount--)
786 782 *d = ddi_swap16(*h++);
787 783 }
788 784
789 785 /*ARGSUSED*/
790 786 void
791 787 i_ddi_io_swap_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
792 788 uint16_t *dev_addr, size_t repcount, uint_t flags)
793 789 {
794 790 uint16_t *h;
795 791 uintptr_t port;
796 792
797 793 h = host_addr;
798 794 port = (uintptr_t)dev_addr;
799 795
800 796 if (flags == DDI_DEV_AUTOINCR)
801 797 for (; repcount; repcount--, port += 2)
802 798 outw(port, ddi_swap16(*h++));
803 799 else
804 800 for (; repcount; repcount--)
805 801 outw(port, ddi_swap16(*h++));
806 802 }
807 803
808 804 /*ARGSUSED*/
809 805 void
810 806 i_ddi_vaddr_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
811 807 uint32_t *dev_addr, size_t repcount, uint_t flags)
812 808 {
813 809 uint32_t *h, *d;
814 810
815 811 h = host_addr;
816 812 d = dev_addr;
817 813
818 814 if (flags == DDI_DEV_AUTOINCR)
819 815 for (; repcount; repcount--)
820 816 *d++ = *h++;
821 817 else
822 818 for (; repcount; repcount--)
823 819 *d = *h++;
824 820 }
825 821
826 822 /*ARGSUSED*/
827 823 void
828 824 i_ddi_vaddr_swap_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
829 825 uint32_t *dev_addr, size_t repcount, uint_t flags)
830 826 {
831 827 uint32_t *h, *d;
832 828
833 829 h = host_addr;
834 830 d = dev_addr;
835 831
836 832 if (flags == DDI_DEV_AUTOINCR)
837 833 for (; repcount; repcount--)
838 834 *d++ = ddi_swap32(*h++);
839 835 else
840 836 for (; repcount; repcount--)
841 837 *d = ddi_swap32(*h++);
842 838 }
843 839
844 840 /*ARGSUSED*/
845 841 void
846 842 i_ddi_io_swap_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
847 843 uint32_t *dev_addr, size_t repcount, uint_t flags)
848 844 {
849 845 uint32_t *h;
850 846 uintptr_t port;
851 847
852 848 h = host_addr;
853 849 port = (uintptr_t)dev_addr;
854 850
855 851 if (flags == DDI_DEV_AUTOINCR)
856 852 for (; repcount; repcount--, port += 4)
857 853 outl(port, ddi_swap32(*h++));
858 854 else
859 855 for (; repcount; repcount--)
860 856 outl(port, ddi_swap32(*h++));
861 857 }
862 858
863 859 /*ARGSUSED*/
864 860 void
865 861 i_ddi_vaddr_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
866 862 uint64_t *dev_addr, size_t repcount, uint_t flags)
867 863 {
868 864 uint64_t *h, *d;
869 865
870 866 h = host_addr;
871 867 d = dev_addr;
872 868
873 869 if (flags == DDI_DEV_AUTOINCR)
874 870 for (; repcount; repcount--)
875 871 *d++ = *h++;
876 872 else
877 873 for (; repcount; repcount--)
878 874 *d = *h++;
879 875 }
880 876
881 877 /*ARGSUSED*/
882 878 void
883 879 i_ddi_vaddr_swap_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
884 880 uint64_t *dev_addr, size_t repcount, uint_t flags)
885 881 {
886 882 uint64_t *h, *d;
887 883
888 884 h = host_addr;
889 885 d = dev_addr;
890 886
891 887 if (flags == DDI_DEV_AUTOINCR)
892 888 for (; repcount; repcount--)
893 889 *d++ = ddi_swap64(*h++);
894 890 else
895 891 for (; repcount; repcount--)
896 892 *d = ddi_swap64(*h++);
897 893 }
898 894
899 895 /*ARGSUSED*/
900 896 uint64_t
901 897 i_ddi_io_get64(ddi_acc_impl_t *hdlp, uint64_t *addr)
902 898 {
903 899 panic("ddi_get64 from i/o space");
904 900 /*NOTREACHED*/
905 901 return (0);
906 902 }
907 903
908 904 /*ARGSUSED*/
909 905 void
910 906 i_ddi_io_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, uint64_t value)
911 907 {
912 908 panic("ddi_put64 to i/o space");
913 909 /*NOTREACHED*/
914 910 }
915 911
916 912 void
917 913 do_scan(ddi_acc_impl_t *hdlp)
918 914 {
919 915 ddi_fm_error_t de;
920 916 ndi_err_t *errp = (ndi_err_t *)hdlp->ahi_err;
921 917
922 918 bzero(&de, sizeof (ddi_fm_error_t));
923 919 de.fme_version = DDI_FME_VERSION;
924 920 de.fme_ena = fm_ena_generate(0, FM_ENA_FMT1);
925 921 de.fme_flag = DDI_FM_ERR_UNEXPECTED;
926 922
927 923 mutex_enter(hdlp->ahi_err_mutexp);
928 924 hdlp->ahi_scan(hdlp->ahi_scan_dip, &de);
929 925 if (de.fme_status != DDI_FM_OK) {
930 926 errp->err_ena = de.fme_ena;
931 927 errp->err_expected = de.fme_flag;
932 928 errp->err_status = DDI_FM_NONFATAL;
933 929 }
934 930 mutex_exit(hdlp->ahi_err_mutexp);
935 931 }
936 932
937 933 /*ARGSUSED*/
938 934 uint8_t
939 935 i_ddi_prot_vaddr_get8(ddi_acc_impl_t *hdlp, uint8_t *addr)
940 936 {
941 937 uint8_t val;
942 938
943 939 mutex_enter(hdlp->ahi_peekpoke_mutexp);
944 940 val = *addr;
945 941 if (val == 0xff)
946 942 do_scan(hdlp);
947 943 mutex_exit(hdlp->ahi_peekpoke_mutexp);
948 944
949 945 return (val);
950 946 }
951 947
952 948 /*ARGSUSED*/
953 949 uint16_t
954 950 i_ddi_prot_vaddr_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
955 951 {
956 952 uint16_t val;
957 953
958 954 mutex_enter(hdlp->ahi_peekpoke_mutexp);
959 955 val = *addr;
960 956 if (val == 0xffff)
961 957 do_scan(hdlp);
962 958 mutex_exit(hdlp->ahi_peekpoke_mutexp);
963 959
964 960 return (val);
965 961 }
966 962
967 963 /*ARGSUSED*/
968 964 uint32_t
969 965 i_ddi_prot_vaddr_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
970 966 {
971 967 uint32_t val;
972 968
973 969 mutex_enter(hdlp->ahi_peekpoke_mutexp);
974 970 val = *addr;
975 971 if (val == 0xffffffff)
976 972 do_scan(hdlp);
977 973 mutex_exit(hdlp->ahi_peekpoke_mutexp);
978 974
979 975 return (val);
980 976 }
981 977
982 978 /*ARGSUSED*/
983 979 uint64_t
984 980 i_ddi_prot_vaddr_get64(ddi_acc_impl_t *hdlp, uint64_t *addr)
985 981 {
986 982 uint64_t val;
987 983
988 984 mutex_enter(hdlp->ahi_peekpoke_mutexp);
989 985 val = *addr;
990 986 if (val == 0xffffffffffffffff)
991 987 do_scan(hdlp);
992 988 mutex_exit(hdlp->ahi_peekpoke_mutexp);
993 989
994 990 return (val);
995 991 }
996 992
997 993 /*ARGSUSED*/
998 994 uint8_t
999 995 i_ddi_prot_io_get8(ddi_acc_impl_t *hdlp, uint8_t *addr)
1000 996 {
1001 997 uint8_t val;
1002 998
1003 999 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1004 1000 val = inb((uintptr_t)addr);
1005 1001 if (val == 0xff)
1006 1002 do_scan(hdlp);
1007 1003 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1008 1004
1009 1005 return (val);
1010 1006 }
1011 1007
1012 1008 /*ARGSUSED*/
1013 1009 uint16_t
1014 1010 i_ddi_prot_io_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
1015 1011 {
1016 1012 uint16_t val;
1017 1013
1018 1014 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1019 1015 val = inw((uintptr_t)addr);
1020 1016 if (val == 0xffff)
1021 1017 do_scan(hdlp);
1022 1018 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1023 1019
1024 1020 return (val);
1025 1021 }
1026 1022
1027 1023 /*ARGSUSED*/
1028 1024 uint32_t
1029 1025 i_ddi_prot_io_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
1030 1026 {
1031 1027 uint32_t val;
1032 1028
1033 1029 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1034 1030 val = inl((uintptr_t)addr);
1035 1031 if (val == 0xffffffff)
1036 1032 do_scan(hdlp);
1037 1033 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1038 1034
1039 1035 return (val);
1040 1036 }
1041 1037
1042 1038 /*ARGSUSED*/
1043 1039 uint16_t
1044 1040 i_ddi_prot_vaddr_swap_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
1045 1041 {
1046 1042 uint16_t val;
1047 1043
1048 1044 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1049 1045 val = ddi_swap16(*addr);
1050 1046 if (val == 0xffff)
1051 1047 do_scan(hdlp);
1052 1048 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1053 1049
1054 1050 return (val);
1055 1051 }
1056 1052
1057 1053 /*ARGSUSED*/
1058 1054 uint16_t
1059 1055 i_ddi_prot_io_swap_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
1060 1056 {
1061 1057 uint16_t val;
1062 1058
1063 1059 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1064 1060 val = ddi_swap16(inw((uintptr_t)addr));
1065 1061 if (val == 0xffff)
1066 1062 do_scan(hdlp);
1067 1063 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1068 1064
1069 1065 return (val);
1070 1066 }
1071 1067
1072 1068 /*ARGSUSED*/
1073 1069 uint32_t
1074 1070 i_ddi_prot_vaddr_swap_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
1075 1071 {
1076 1072 uint32_t val;
1077 1073
1078 1074 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1079 1075 val = ddi_swap32(*addr);
1080 1076 if (val == 0xffffffff)
1081 1077 do_scan(hdlp);
1082 1078 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1083 1079
1084 1080 return (val);
1085 1081 }
1086 1082
1087 1083 /*ARGSUSED*/
1088 1084 uint32_t
1089 1085 i_ddi_prot_io_swap_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
1090 1086 {
1091 1087 uint32_t val;
1092 1088
1093 1089 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1094 1090 val = ddi_swap32(inl((uintptr_t)addr));
1095 1091 if (val == 0xffffffff)
1096 1092 do_scan(hdlp);
1097 1093 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1098 1094
1099 1095 return (val);
1100 1096 }
1101 1097
1102 1098 /*ARGSUSED*/
1103 1099 uint64_t
1104 1100 i_ddi_prot_vaddr_swap_get64(ddi_acc_impl_t *hdlp, uint64_t *addr)
1105 1101 {
1106 1102 uint64_t val;
1107 1103
1108 1104 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1109 1105 val = ddi_swap64(*addr);
1110 1106 if (val == 0xffffffffffffffff)
1111 1107 do_scan(hdlp);
1112 1108 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1113 1109
1114 1110 return (val);
1115 1111 }
1116 1112
1117 1113 /*ARGSUSED*/
1118 1114 void
1119 1115 i_ddi_prot_vaddr_put8(ddi_acc_impl_t *hdlp, uint8_t *addr, uint8_t value)
1120 1116 {
1121 1117 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1122 1118 *addr = value;
1123 1119 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1124 1120 }
1125 1121
1126 1122 /*ARGSUSED*/
1127 1123 void
1128 1124 i_ddi_prot_io_put8(ddi_acc_impl_t *hdlp, uint8_t *addr, uint8_t value)
1129 1125 {
1130 1126 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1131 1127 outb((uintptr_t)addr, value);
1132 1128 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1133 1129 }
1134 1130
1135 1131 /*ARGSUSED*/
1136 1132 void
1137 1133 i_ddi_prot_vaddr_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value)
1138 1134 {
1139 1135 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1140 1136 *addr = value;
1141 1137 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1142 1138 }
1143 1139
1144 1140 /*ARGSUSED*/
1145 1141 void
1146 1142 i_ddi_prot_io_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value)
1147 1143 {
1148 1144 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1149 1145 outw((uintptr_t)addr, value);
1150 1146 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1151 1147 }
1152 1148
1153 1149 /*ARGSUSED*/
1154 1150 void
1155 1151 i_ddi_prot_vaddr_put32(ddi_acc_impl_t *hdlp, uint32_t *addr,
1156 1152 uint32_t value)
1157 1153 {
1158 1154 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1159 1155 *addr = value;
1160 1156 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1161 1157 }
1162 1158
1163 1159 /*ARGSUSED*/
1164 1160 void
1165 1161 i_ddi_prot_io_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value)
1166 1162 {
1167 1163 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1168 1164 outl((uintptr_t)addr, value);
1169 1165 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1170 1166 }
1171 1167
1172 1168 /*ARGSUSED*/
1173 1169 void
1174 1170 i_ddi_prot_vaddr_put64(ddi_acc_impl_t *hdlp, uint64_t *addr,
1175 1171 uint64_t value)
1176 1172 {
1177 1173 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1178 1174 *addr = value;
1179 1175 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1180 1176 }
1181 1177
1182 1178 /*ARGSUSED*/
1183 1179 void
1184 1180 i_ddi_prot_vaddr_swap_put16(ddi_acc_impl_t *hdlp, uint16_t *addr,
1185 1181 uint16_t value)
1186 1182 {
1187 1183 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1188 1184 *addr = ddi_swap16(value);
1189 1185 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1190 1186 }
1191 1187
1192 1188 /*ARGSUSED*/
1193 1189 void
1194 1190 i_ddi_prot_io_swap_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value)
1195 1191 {
1196 1192 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1197 1193 outw((uintptr_t)addr, ddi_swap16(value));
1198 1194 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1199 1195 }
1200 1196
1201 1197 /*ARGSUSED*/
1202 1198 void
1203 1199 i_ddi_prot_vaddr_swap_put32(ddi_acc_impl_t *hdlp, uint32_t *addr,
1204 1200 uint32_t value)
1205 1201 {
1206 1202 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1207 1203 *addr = ddi_swap32(value);
1208 1204 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1209 1205 }
1210 1206
1211 1207 /*ARGSUSED*/
1212 1208 void
1213 1209 i_ddi_prot_io_swap_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value)
1214 1210 {
1215 1211 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1216 1212 outl((uintptr_t)addr, ddi_swap32(value));
1217 1213 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1218 1214 }
1219 1215
1220 1216 /*ARGSUSED*/
1221 1217 void
1222 1218 i_ddi_prot_vaddr_swap_put64(ddi_acc_impl_t *hdlp, uint64_t *addr,
1223 1219 uint64_t value)
1224 1220 {
1225 1221 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1226 1222 *addr = ddi_swap64(value);
1227 1223 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1228 1224 }
1229 1225
1230 1226 /*ARGSUSED*/
1231 1227 void
1232 1228 i_ddi_prot_io_rep_get8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
1233 1229 uint8_t *dev_addr, size_t repcount, uint_t flags)
1234 1230 {
1235 1231 int fail = 0;
1236 1232 uint8_t *h;
1237 1233 uintptr_t port;
1238 1234
1239 1235 h = host_addr;
1240 1236 port = (uintptr_t)dev_addr;
1241 1237
1242 1238 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1243 1239 if (flags == DDI_DEV_AUTOINCR) {
1244 1240 for (; repcount; repcount--, port++)
1245 1241 if ((*h++ = inb(port)) == 0xff)
1246 1242 fail = 1;
1247 1243 } else {
1248 1244 for (; repcount; repcount--)
1249 1245 if ((*h++ = inb(port)) == 0xff)
1250 1246 fail = 1;
1251 1247 }
1252 1248 if (fail == 1)
1253 1249 do_scan(hdlp);
1254 1250 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1255 1251 }
1256 1252
1257 1253 /*ARGSUSED*/
1258 1254 void
1259 1255 i_ddi_prot_io_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1260 1256 uint16_t *dev_addr, size_t repcount, uint_t flags)
1261 1257 {
1262 1258 int fail = 0;
1263 1259 uint16_t *h;
1264 1260 uintptr_t port;
1265 1261
1266 1262 h = host_addr;
1267 1263 port = (uintptr_t)dev_addr;
1268 1264
1269 1265 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1270 1266 if (flags == DDI_DEV_AUTOINCR) {
1271 1267 for (; repcount; repcount--, port += 2)
1272 1268 if ((*h++ = inw(port)) == 0xffff)
1273 1269 fail = 1;
1274 1270 } else {
1275 1271 for (; repcount; repcount--)
1276 1272 if ((*h++ = inw(port)) == 0xffff)
1277 1273 fail = 1;
1278 1274 }
1279 1275 if (fail == 1)
1280 1276 do_scan(hdlp);
1281 1277 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1282 1278 }
1283 1279
1284 1280 /*ARGSUSED*/
1285 1281 void
1286 1282 i_ddi_prot_io_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1287 1283 uint32_t *dev_addr, size_t repcount, uint_t flags)
1288 1284 {
1289 1285 int fail = 0;
1290 1286 uint32_t *h;
1291 1287 uintptr_t port;
1292 1288
1293 1289 h = host_addr;
1294 1290 port = (uintptr_t)dev_addr;
1295 1291
1296 1292 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1297 1293 if (flags == DDI_DEV_AUTOINCR) {
1298 1294 for (; repcount; repcount--, port += 4)
1299 1295 if ((*h++ = inl(port)) == 0xffffffff)
1300 1296 fail = 1;
1301 1297 } else {
1302 1298 for (; repcount; repcount--)
1303 1299 if ((*h++ = inl(port)) == 0xffffffff)
1304 1300 fail = 1;
1305 1301 }
1306 1302 if (fail == 1)
1307 1303 do_scan(hdlp);
1308 1304 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1309 1305 }
1310 1306
1311 1307 /*ARGSUSED*/
1312 1308 void
1313 1309 i_ddi_prot_vaddr_rep_get8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
1314 1310 uint8_t *dev_addr, size_t repcount, uint_t flags)
1315 1311 {
1316 1312 int fail = 0;
1317 1313 uint8_t *h, *d;
1318 1314
1319 1315 h = host_addr;
1320 1316 d = dev_addr;
1321 1317
1322 1318 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1323 1319 if (flags == DDI_DEV_AUTOINCR) {
1324 1320 for (; repcount; repcount--)
1325 1321 if ((*h++ = *d++) == 0xff)
1326 1322 fail = 1;
1327 1323 } else {
1328 1324 for (; repcount; repcount--)
1329 1325 if ((*h++ = *d) == 0xff)
1330 1326 fail = 1;
1331 1327 }
1332 1328 if (fail == 1)
1333 1329 do_scan(hdlp);
1334 1330 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1335 1331 }
1336 1332
1337 1333 /*ARGSUSED*/
1338 1334 void
1339 1335 i_ddi_prot_vaddr_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1340 1336 uint16_t *dev_addr, size_t repcount, uint_t flags)
1341 1337 {
1342 1338 int fail = 0;
1343 1339 uint16_t *h, *d;
1344 1340
1345 1341 h = host_addr;
1346 1342 d = dev_addr;
1347 1343
1348 1344 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1349 1345 if (flags == DDI_DEV_AUTOINCR) {
1350 1346 for (; repcount; repcount--)
1351 1347 if ((*h++ = *d++) == 0xffff)
1352 1348 fail = 1;
1353 1349 } else {
1354 1350 for (; repcount; repcount--)
1355 1351 if ((*h++ = *d) == 0xffff)
1356 1352 fail = 1;
1357 1353 }
1358 1354 if (fail == 1)
1359 1355 do_scan(hdlp);
1360 1356 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1361 1357 }
1362 1358
1363 1359 /*ARGSUSED*/
1364 1360 void
1365 1361 i_ddi_prot_vaddr_swap_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1366 1362 uint16_t *dev_addr, size_t repcount, uint_t flags)
1367 1363 {
1368 1364 int fail = 0;
1369 1365 uint16_t *h, *d;
1370 1366
1371 1367 h = host_addr;
1372 1368 d = dev_addr;
1373 1369
1374 1370 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1375 1371 if (flags == DDI_DEV_AUTOINCR) {
1376 1372 for (; repcount; repcount--)
1377 1373 if ((*h++ = ddi_swap16(*d++)) == 0xffff)
1378 1374 fail = 1;
1379 1375 } else {
1380 1376 for (; repcount; repcount--)
1381 1377 if ((*h++ = ddi_swap16(*d)) == 0xffff)
1382 1378 fail = 1;
1383 1379 }
1384 1380 if (fail == 1)
1385 1381 do_scan(hdlp);
1386 1382 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1387 1383 }
1388 1384
1389 1385 /*ARGSUSED*/
1390 1386 void
1391 1387 i_ddi_prot_io_swap_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1392 1388 uint16_t *dev_addr, size_t repcount, uint_t flags)
1393 1389 {
1394 1390 int fail = 0;
1395 1391 uint16_t *h;
1396 1392 uintptr_t port;
1397 1393
1398 1394 h = host_addr;
1399 1395 port = (uintptr_t)dev_addr;
1400 1396
1401 1397 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1402 1398 if (flags == DDI_DEV_AUTOINCR) {
1403 1399 for (; repcount; repcount--, port += 2)
1404 1400 if ((*h++ = ddi_swap16(inw(port))) == 0xffff)
1405 1401 fail = 1;
1406 1402 } else {
1407 1403 for (; repcount; repcount--)
1408 1404 if ((*h++ = ddi_swap16(inw(port))) == 0xffff)
1409 1405 fail = 1;
1410 1406 }
1411 1407 if (fail == 1)
1412 1408 do_scan(hdlp);
1413 1409 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1414 1410 }
1415 1411
1416 1412 /*ARGSUSED*/
1417 1413 void
1418 1414 i_ddi_prot_vaddr_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1419 1415 uint32_t *dev_addr, size_t repcount, uint_t flags)
1420 1416 {
1421 1417 int fail = 0;
1422 1418 uint32_t *h, *d;
1423 1419
1424 1420 h = host_addr;
1425 1421 d = dev_addr;
1426 1422
1427 1423 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1428 1424 if (flags == DDI_DEV_AUTOINCR) {
1429 1425 for (; repcount; repcount--)
1430 1426 if ((*h++ = *d++) == 0xffffffff)
1431 1427 fail = 1;
1432 1428 } else {
1433 1429 for (; repcount; repcount--)
1434 1430 if ((*h++ = *d) == 0xffffffff)
1435 1431 fail = 1;
1436 1432 }
1437 1433 if (fail == 1)
1438 1434 do_scan(hdlp);
1439 1435 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1440 1436 }
1441 1437
1442 1438 /*ARGSUSED*/
1443 1439 void
1444 1440 i_ddi_prot_vaddr_swap_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1445 1441 uint32_t *dev_addr, size_t repcount, uint_t flags)
1446 1442 {
1447 1443 int fail = 0;
1448 1444 uint32_t *h, *d;
1449 1445
1450 1446 h = host_addr;
1451 1447 d = dev_addr;
1452 1448
1453 1449 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1454 1450 if (flags == DDI_DEV_AUTOINCR) {
1455 1451 for (; repcount; repcount--)
1456 1452 if ((*h++ = ddi_swap32(*d++)) == 0xffffffff)
1457 1453 fail = 1;
1458 1454 } else {
1459 1455 for (; repcount; repcount--)
1460 1456 if ((*h++ = ddi_swap32(*d)) == 0xffffffff)
1461 1457 fail = 1;
1462 1458 }
1463 1459 if (fail == 1)
1464 1460 do_scan(hdlp);
1465 1461 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1466 1462 }
1467 1463
1468 1464 /*ARGSUSED*/
1469 1465 void
1470 1466 i_ddi_prot_io_swap_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1471 1467 uint32_t *dev_addr, size_t repcount, uint_t flags)
1472 1468 {
1473 1469 int fail = 0;
1474 1470 uint32_t *h;
1475 1471 uintptr_t port;
1476 1472
1477 1473 h = host_addr;
1478 1474 port = (uintptr_t)dev_addr;
1479 1475
1480 1476 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1481 1477 if (flags == DDI_DEV_AUTOINCR) {
1482 1478 for (; repcount; repcount--, port += 4)
1483 1479 if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff)
1484 1480 fail = 1;
1485 1481 } else {
1486 1482 for (; repcount; repcount--)
1487 1483 if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff)
1488 1484 fail = 1;
1489 1485 }
1490 1486 if (fail == 1)
1491 1487 do_scan(hdlp);
1492 1488 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1493 1489 }
1494 1490
1495 1491 /*ARGSUSED*/
1496 1492 void
1497 1493 i_ddi_prot_vaddr_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
1498 1494 uint64_t *dev_addr, size_t repcount, uint_t flags)
1499 1495 {
1500 1496 int fail = 0;
1501 1497 uint64_t *h, *d;
1502 1498
1503 1499 h = host_addr;
1504 1500 d = dev_addr;
1505 1501
1506 1502 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1507 1503 if (flags == DDI_DEV_AUTOINCR) {
1508 1504 for (; repcount; repcount--)
1509 1505 if ((*h++ = *d++) == 0xffffffffffffffff)
1510 1506 fail = 1;
1511 1507 } else {
1512 1508 for (; repcount; repcount--)
1513 1509 if ((*h++ = *d) == 0xffffffffffffffff)
1514 1510 fail = 1;
1515 1511 }
1516 1512 if (fail == 1)
1517 1513 do_scan(hdlp);
1518 1514 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1519 1515 }
1520 1516
1521 1517 /*ARGSUSED*/
1522 1518 void
1523 1519 i_ddi_prot_vaddr_swap_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
1524 1520 uint64_t *dev_addr, size_t repcount, uint_t flags)
1525 1521 {
1526 1522 int fail = 0;
1527 1523 uint64_t *h, *d;
1528 1524
1529 1525 h = host_addr;
1530 1526 d = dev_addr;
1531 1527
1532 1528 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1533 1529 if (flags == DDI_DEV_AUTOINCR) {
1534 1530 for (; repcount; repcount--)
1535 1531 if ((*h++ = ddi_swap64(*d++)) == 0xffffffffffffffff)
1536 1532 fail = 1;
1537 1533 } else {
1538 1534 for (; repcount; repcount--)
1539 1535 if ((*h++ = ddi_swap64(*d)) == 0xffffffffffffffff)
1540 1536 fail = 1;
1541 1537 }
1542 1538 if (fail == 1)
1543 1539 do_scan(hdlp);
1544 1540 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1545 1541 }
1546 1542
1547 1543 /*ARGSUSED*/
1548 1544 void
1549 1545 i_ddi_prot_vaddr_rep_put8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
1550 1546 uint8_t *dev_addr, size_t repcount, uint_t flags)
1551 1547 {
1552 1548 uint8_t *h, *d;
1553 1549
1554 1550 h = host_addr;
1555 1551 d = dev_addr;
1556 1552
1557 1553 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1558 1554 if (flags == DDI_DEV_AUTOINCR)
1559 1555 for (; repcount; repcount--)
1560 1556 *d++ = *h++;
1561 1557 else
1562 1558 for (; repcount; repcount--)
1563 1559 *d = *h++;
1564 1560 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1565 1561 }
1566 1562
1567 1563 /*ARGSUSED*/
1568 1564 void
1569 1565 i_ddi_prot_io_rep_put8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
1570 1566 uint8_t *dev_addr, size_t repcount, uint_t flags)
1571 1567 {
1572 1568 uint8_t *h;
1573 1569 uintptr_t port;
1574 1570
1575 1571 h = host_addr;
1576 1572 port = (uintptr_t)dev_addr;
1577 1573
1578 1574 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1579 1575 if (flags == DDI_DEV_AUTOINCR)
1580 1576 for (; repcount; repcount--, port++)
1581 1577 outb(port, *h++);
1582 1578 else
1583 1579 for (; repcount; repcount--)
1584 1580 outb(port, *h++);
1585 1581 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1586 1582 }
1587 1583
1588 1584 /*ARGSUSED*/
1589 1585 void
1590 1586 i_ddi_prot_vaddr_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1591 1587 uint16_t *dev_addr, size_t repcount, uint_t flags)
1592 1588 {
1593 1589 uint16_t *h, *d;
1594 1590
1595 1591 h = host_addr;
1596 1592 d = dev_addr;
1597 1593
1598 1594 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1599 1595 if (flags == DDI_DEV_AUTOINCR)
1600 1596 for (; repcount; repcount--)
1601 1597 *d++ = *h++;
1602 1598 else
1603 1599 for (; repcount; repcount--)
1604 1600 *d = *h++;
1605 1601 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1606 1602 }
1607 1603
1608 1604 /*ARGSUSED*/
1609 1605 void
1610 1606 i_ddi_prot_io_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1611 1607 uint16_t *dev_addr, size_t repcount, uint_t flags)
1612 1608 {
1613 1609 uint16_t *h;
1614 1610 uintptr_t port;
1615 1611
1616 1612 h = host_addr;
1617 1613 port = (uintptr_t)dev_addr;
1618 1614
1619 1615 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1620 1616 if (flags == DDI_DEV_AUTOINCR)
1621 1617 for (; repcount; repcount--, port += 2)
1622 1618 outw(port, *h++);
1623 1619 else
1624 1620 for (; repcount; repcount--)
1625 1621 outw(port, *h++);
1626 1622 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1627 1623 }
1628 1624
1629 1625 /*ARGSUSED*/
1630 1626 void
1631 1627 i_ddi_prot_vaddr_swap_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1632 1628 uint16_t *dev_addr, size_t repcount, uint_t flags)
1633 1629 {
1634 1630 uint16_t *h, *d;
1635 1631
1636 1632 h = host_addr;
1637 1633 d = dev_addr;
1638 1634
1639 1635 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1640 1636 if (flags == DDI_DEV_AUTOINCR)
1641 1637 for (; repcount; repcount--)
1642 1638 *d++ = ddi_swap16(*h++);
1643 1639 else
1644 1640 for (; repcount; repcount--)
1645 1641 *d = ddi_swap16(*h++);
1646 1642 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1647 1643 }
1648 1644
1649 1645 /*ARGSUSED*/
1650 1646 void
1651 1647 i_ddi_prot_io_swap_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1652 1648 uint16_t *dev_addr, size_t repcount, uint_t flags)
1653 1649 {
1654 1650 uint16_t *h;
1655 1651 uintptr_t port;
1656 1652
1657 1653 h = host_addr;
1658 1654 port = (uintptr_t)dev_addr;
1659 1655
1660 1656 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1661 1657 if (flags == DDI_DEV_AUTOINCR)
1662 1658 for (; repcount; repcount--, port += 2)
1663 1659 outw(port, ddi_swap16(*h++));
1664 1660 else
1665 1661 for (; repcount; repcount--)
1666 1662 outw(port, ddi_swap16(*h++));
1667 1663 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1668 1664 }
1669 1665
1670 1666 /*ARGSUSED*/
1671 1667 void
1672 1668 i_ddi_prot_vaddr_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1673 1669 uint32_t *dev_addr, size_t repcount, uint_t flags)
1674 1670 {
1675 1671 uint32_t *h, *d;
1676 1672
1677 1673 h = host_addr;
1678 1674 d = dev_addr;
1679 1675
1680 1676 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1681 1677 if (flags == DDI_DEV_AUTOINCR)
1682 1678 for (; repcount; repcount--)
1683 1679 *d++ = *h++;
1684 1680 else
1685 1681 for (; repcount; repcount--)
1686 1682 *d = *h++;
1687 1683 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1688 1684 }
1689 1685
1690 1686 /*ARGSUSED*/
1691 1687 void
1692 1688 i_ddi_prot_io_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1693 1689 uint32_t *dev_addr, size_t repcount, uint_t flags)
1694 1690 {
1695 1691 uint32_t *h;
1696 1692 uintptr_t port;
1697 1693
1698 1694 h = host_addr;
1699 1695 port = (uintptr_t)dev_addr;
1700 1696
1701 1697 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1702 1698 if (flags == DDI_DEV_AUTOINCR)
1703 1699 for (; repcount; repcount--, port += 4)
1704 1700 outl(port, *h++);
1705 1701 else
1706 1702 for (; repcount; repcount--)
1707 1703 outl(port, *h++);
1708 1704 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1709 1705 }
1710 1706
1711 1707 /*ARGSUSED*/
1712 1708 void
1713 1709 i_ddi_prot_vaddr_swap_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1714 1710 uint32_t *dev_addr, size_t repcount, uint_t flags)
1715 1711 {
1716 1712 uint32_t *h, *d;
1717 1713
1718 1714 h = host_addr;
1719 1715 d = dev_addr;
1720 1716
1721 1717 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1722 1718 if (flags == DDI_DEV_AUTOINCR)
1723 1719 for (; repcount; repcount--)
1724 1720 *d++ = ddi_swap32(*h++);
1725 1721 else
1726 1722 for (; repcount; repcount--)
1727 1723 *d = ddi_swap32(*h++);
1728 1724 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1729 1725 }
1730 1726
1731 1727 /*ARGSUSED*/
1732 1728 void
1733 1729 i_ddi_prot_io_swap_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1734 1730 uint32_t *dev_addr, size_t repcount, uint_t flags)
1735 1731 {
1736 1732 uint32_t *h;
1737 1733 uintptr_t port;
1738 1734
1739 1735 h = host_addr;
1740 1736 port = (uintptr_t)dev_addr;
1741 1737
1742 1738 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1743 1739 if (flags == DDI_DEV_AUTOINCR)
1744 1740 for (; repcount; repcount--, port += 4)
1745 1741 outl(port, ddi_swap32(*h++));
1746 1742 else
1747 1743 for (; repcount; repcount--)
1748 1744 outl(port, ddi_swap32(*h++));
1749 1745 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1750 1746 }
1751 1747
1752 1748 /*ARGSUSED*/
1753 1749 void
1754 1750 i_ddi_prot_vaddr_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
1755 1751 uint64_t *dev_addr, size_t repcount, uint_t flags)
1756 1752 {
1757 1753 uint64_t *h, *d;
1758 1754
1759 1755 h = host_addr;
1760 1756 d = dev_addr;
1761 1757
1762 1758 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1763 1759 if (flags == DDI_DEV_AUTOINCR)
1764 1760 for (; repcount; repcount--)
1765 1761 *d++ = *h++;
1766 1762 else
1767 1763 for (; repcount; repcount--)
1768 1764 *d = *h++;
1769 1765 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1770 1766 }
1771 1767
1772 1768 /*ARGSUSED*/
1773 1769 void
1774 1770 i_ddi_prot_vaddr_swap_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
1775 1771 uint64_t *dev_addr, size_t repcount, uint_t flags)
1776 1772 {
1777 1773 uint64_t *h, *d;
1778 1774
1779 1775 h = host_addr;
1780 1776 d = dev_addr;
1781 1777
1782 1778 mutex_enter(hdlp->ahi_peekpoke_mutexp);
1783 1779 if (flags == DDI_DEV_AUTOINCR)
1784 1780 for (; repcount; repcount--)
1785 1781 *d++ = ddi_swap64(*h++);
1786 1782 else
1787 1783 for (; repcount; repcount--)
1788 1784 *d = ddi_swap64(*h++);
1789 1785 mutex_exit(hdlp->ahi_peekpoke_mutexp);
1790 1786 }
1791 1787
1792 1788 void
1793 1789 ddi_io_rep_get8(ddi_acc_handle_t handle,
1794 1790 uint8_t *host_addr, uint8_t *dev_addr, size_t repcount)
1795 1791 {
1796 1792 (((ddi_acc_impl_t *)handle)->ahi_rep_get8)
1797 1793 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1798 1794 repcount, DDI_DEV_NO_AUTOINCR);
1799 1795 }
1800 1796
1801 1797 void
1802 1798 ddi_io_rep_get16(ddi_acc_handle_t handle,
1803 1799 uint16_t *host_addr, uint16_t *dev_addr, size_t repcount)
1804 1800 {
1805 1801 (((ddi_acc_impl_t *)handle)->ahi_rep_get16)
1806 1802 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1807 1803 repcount, DDI_DEV_NO_AUTOINCR);
1808 1804 }
1809 1805
1810 1806 void
1811 1807 ddi_io_rep_get32(ddi_acc_handle_t handle,
1812 1808 uint32_t *host_addr, uint32_t *dev_addr, size_t repcount)
1813 1809 {
1814 1810 (((ddi_acc_impl_t *)handle)->ahi_rep_get32)
1815 1811 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1816 1812 repcount, DDI_DEV_NO_AUTOINCR);
1817 1813 }
1818 1814
1819 1815 /*ARGSUSED*/
1820 1816 void
1821 1817 i_ddi_io_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
1822 1818 uint64_t *dev_addr, size_t repcount, uint_t flags)
1823 1819 {
1824 1820 cmn_err(CE_PANIC, "ddi_rep_get64 from i/o space");
1825 1821 }
1826 1822
1827 1823 void
1828 1824 ddi_io_rep_put8(ddi_acc_handle_t handle,
1829 1825 uint8_t *host_addr, uint8_t *dev_addr, size_t repcount)
1830 1826 {
1831 1827 (((ddi_acc_impl_t *)handle)->ahi_rep_put8)
1832 1828 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1833 1829 repcount, DDI_DEV_NO_AUTOINCR);
1834 1830 }
1835 1831
1836 1832 void
1837 1833 ddi_io_rep_put16(ddi_acc_handle_t handle,
1838 1834 uint16_t *host_addr, uint16_t *dev_addr, size_t repcount)
1839 1835 {
1840 1836 (((ddi_acc_impl_t *)handle)->ahi_rep_put16)
1841 1837 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1842 1838 repcount, DDI_DEV_NO_AUTOINCR);
1843 1839 }
1844 1840
1845 1841 void
1846 1842 ddi_io_rep_put32(ddi_acc_handle_t handle,
1847 1843 uint32_t *host_addr, uint32_t *dev_addr, size_t repcount)
1848 1844 {
1849 1845 (((ddi_acc_impl_t *)handle)->ahi_rep_put32)
1850 1846 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1851 1847 repcount, DDI_DEV_NO_AUTOINCR);
1852 1848 }
1853 1849
1854 1850 /*ARGSUSED*/
1855 1851 void
1856 1852 i_ddi_io_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
1857 1853 uint64_t *dev_addr, size_t repcount, uint_t flags)
1858 1854 {
1859 1855 cmn_err(CE_PANIC, "ddi_rep_put64 to i/o space");
1860 1856 }
1861 1857
1862 1858 /*
1863 1859 * We need to separate the old interfaces from the new ones and leave them
1864 1860 * in here for a while. Previous versions of the OS defined the new interfaces
1865 1861 * to the old interfaces. This way we can fix things up so that we can
1866 1862 * eventually remove these interfaces.
1867 1863 * e.g. A 3rd party module/driver using ddi_io_rep_get8 and built against S10
1868 1864 * or earlier will actually have a reference to ddi_io_rep_getb in the binary.
1869 1865 */
1870 1866 #ifdef _ILP32
1871 1867 void
1872 1868 ddi_io_rep_getb(ddi_acc_handle_t handle,
1873 1869 uint8_t *host_addr, uint8_t *dev_addr, size_t repcount)
1874 1870 {
1875 1871 (((ddi_acc_impl_t *)handle)->ahi_rep_get8)
1876 1872 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1877 1873 repcount, DDI_DEV_NO_AUTOINCR);
1878 1874 }
1879 1875
1880 1876 void
1881 1877 ddi_io_rep_getw(ddi_acc_handle_t handle,
1882 1878 uint16_t *host_addr, uint16_t *dev_addr, size_t repcount)
1883 1879 {
1884 1880 (((ddi_acc_impl_t *)handle)->ahi_rep_get16)
1885 1881 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1886 1882 repcount, DDI_DEV_NO_AUTOINCR);
1887 1883 }
1888 1884
1889 1885 void
1890 1886 ddi_io_rep_getl(ddi_acc_handle_t handle,
1891 1887 uint32_t *host_addr, uint32_t *dev_addr, size_t repcount)
1892 1888 {
1893 1889 (((ddi_acc_impl_t *)handle)->ahi_rep_get32)
1894 1890 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1895 1891 repcount, DDI_DEV_NO_AUTOINCR);
1896 1892 }
1897 1893
1898 1894 void
1899 1895 ddi_io_rep_putb(ddi_acc_handle_t handle,
1900 1896 uint8_t *host_addr, uint8_t *dev_addr, size_t repcount)
1901 1897 {
1902 1898 (((ddi_acc_impl_t *)handle)->ahi_rep_put8)
1903 1899 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1904 1900 repcount, DDI_DEV_NO_AUTOINCR);
1905 1901 }
1906 1902
1907 1903 void
1908 1904 ddi_io_rep_putw(ddi_acc_handle_t handle,
1909 1905 uint16_t *host_addr, uint16_t *dev_addr, size_t repcount)
1910 1906 {
1911 1907 (((ddi_acc_impl_t *)handle)->ahi_rep_put16)
1912 1908 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1913 1909 repcount, DDI_DEV_NO_AUTOINCR);
1914 1910 }
1915 1911
1916 1912 void
1917 1913 ddi_io_rep_putl(ddi_acc_handle_t handle,
1918 1914 uint32_t *host_addr, uint32_t *dev_addr, size_t repcount)
1919 1915 {
1920 1916 (((ddi_acc_impl_t *)handle)->ahi_rep_put32)
1921 1917 ((ddi_acc_impl_t *)handle, host_addr, dev_addr,
1922 1918 repcount, DDI_DEV_NO_AUTOINCR);
1923 1919 }
1924 1920 #endif /* _ILP32 */
1925 1921
1926 1922 /*
1927 1923 * These next two functions could be translated into assembler someday
1928 1924 */
1929 1925 int
1930 1926 ddi_check_acc_handle(ddi_acc_handle_t handle)
1931 1927 {
1932 1928 ddi_acc_impl_t *hdlp = (ddi_acc_impl_t *)handle;
1933 1929 return (((*hdlp->ahi_fault_check)(hdlp) == DDI_SUCCESS) ? DDI_SUCCESS :
1934 1930 DDI_FAILURE);
1935 1931 }
1936 1932
1937 1933 int
1938 1934 i_ddi_acc_fault_check(ddi_acc_impl_t *hdlp)
1939 1935 {
1940 1936 /* Default version, just returns flag value */
1941 1937 return (hdlp->ahi_fault);
1942 1938 }
1943 1939
1944 1940 /*ARGSUSED*/
1945 1941 void
1946 1942 i_ddi_acc_fault_notify(ddi_acc_impl_t *hdlp)
1947 1943 {
1948 1944 /* Default version, does nothing for now */
1949 1945 }
1950 1946
1951 1947 void
1952 1948 i_ddi_acc_set_fault(ddi_acc_handle_t handle)
1953 1949 {
1954 1950 ddi_acc_impl_t *hdlp = (ddi_acc_impl_t *)handle;
1955 1951
1956 1952 if (!hdlp->ahi_fault) {
1957 1953 hdlp->ahi_fault = 1;
1958 1954 (*hdlp->ahi_fault_notify)(hdlp);
1959 1955 }
1960 1956 }
1961 1957
1962 1958 void
1963 1959 i_ddi_acc_clr_fault(ddi_acc_handle_t handle)
1964 1960 {
1965 1961 ddi_acc_impl_t *hdlp = (ddi_acc_impl_t *)handle;
1966 1962
1967 1963 if (hdlp->ahi_fault) {
1968 1964 hdlp->ahi_fault = 0;
1969 1965 (*hdlp->ahi_fault_notify)(hdlp);
1970 1966 }
1971 1967 }
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