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4888 Undocument dma_req(9s)
4884 EOF scsi_hba_attach
4886 EOF ddi_dmae_getlim
4887 EOF ddi_iomin
4634 undocument scsi_hba_attach() and ddi_dma_lim(9s)
4630 clean stale references to ddi_iopb_alloc and ddi_iopb_free
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--- old/usr/src/uts/common/sys/dma_engine.h
+++ new/usr/src/uts/common/sys/dma_engine.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License, Version 1.0 only
6 6 * (the "License"). You may not use this file except in compliance
7 7 * with the License.
8 8 *
9 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 10 * or http://www.opensolaris.org/os/licensing.
11 11 * See the License for the specific language governing permissions
12 12 * and limitations under the License.
13 13 *
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14 14 * When distributing Covered Code, include this CDDL HEADER in each
15 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 16 * If applicable, add the following below this CDDL HEADER, with the
17 17 * fields enclosed by brackets "[]" replaced with your own identifying
18 18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 19 *
20 20 * CDDL HEADER END
21 21 */
22 22
23 23 /*
24 - * Copyright 2012 Garrett D'Amore <garrett@damore.org>. All rights reserved.
24 + * Copyright 2014 Garrett D'Amore <garrett@damore.org>
25 25 */
26 26
27 27 /*
28 28 * Copyright 1998 Sun Microsystems, Inc. All rights reserved.
29 29 * Use is subject to license terms.
30 30 */
31 31
32 32 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
33 33 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
34 34 /* All Rights Reserved */
35 35
36 36 /* Copyright (c) 1988, 1989 Intel Corp. */
37 37 /* All Rights Reserved */
38 38
39 39 #ifndef _SYS_DMAENGINE_H
40 40 #define _SYS_DMAENGINE_H
41 41
42 42 #include <sys/types.h>
43 43 #include <sys/dditypes.h>
44 44
45 45 #ifdef __cplusplus
46 46 extern "C" {
47 47 #endif
48 48
49 49 #define NCHANS 8
50 50
51 51 /*
52 52 * the DMA Engine Request structure
53 53 */
54 54 struct ddi_dmae_req {
55 55 dev_info_t *der_rdip; /* original requester's dev_info_t */
56 56 uchar_t der_command; /* Read/Write/Translate/Verify */
57 57 uchar_t der_bufprocess; /* NoAuto_init/Chain/Auto_init */
58 58 uchar_t der_step; /* Inc / Dec / Hold */
59 59 uchar_t der_trans; /* Single/Demand/Block/Cascade */
60 60 uchar_t der_path; /* 8/16/32 */
61 61 uchar_t der_cycles; /* 1 or 2 */
62 62 uchar_t der_dest; /* Memory / IO */
63 63 uchar_t der_arbus; /* MicroChannel arbitration reg */
64 64 ushort_t der_ioadr; /* MicroChannel i/o address reg */
65 65 ddi_dma_cookie_t *(*proc)(); /* address of application call routine */
66 66 void *procparms; /* parameter buffer for appl call */
67 67 };
68 68
69 69 #define DMAE_CMD_VRFY 0
70 70 #define DMAE_CMD_WRITE 1 /* from memory to device */
71 71 #define DMAE_CMD_READ 2 /* from device to memory */
72 72 #define DMAE_CMD_TRAN 3
73 73
74 74 #define DMAE_BUF_NOAUTO 0 /* default */
75 75 #define DMAE_BUF_CHAIN 0x1
76 76 #define DMAE_BUF_AUTO 0x2
77 77
78 78 #define DMAE_STEP_INC 0 /* default */
79 79 #define DMAE_STEP_DEC 1
80 80 #define DMAE_STEP_HOLD 2
81 81
82 82 #define DMAE_TRANS_SNGL 0 /* default */
83 83 #define DMAE_TRANS_BLCK 1
84 84 #define DMAE_TRANS_DMND 2
85 85 #define DMAE_TRANS_CSCD 3
86 86
87 87
88 88 /*
89 89 * For the EISA bus
90 90 */
91 91 #define DMAE_PATH_DEF 0 /* default to ISA xfer width */
92 92 #define DMAE_PATH_8 1 /* ISA default for chnl 0..3 */
93 93 #define DMAE_PATH_16 2 /* ISA default for chnl 5..7 */
94 94 #define DMAE_PATH_32 3
95 95 #define DMAE_PATH_64 4
96 96 #define DMAE_PATH_16B 5 /* 16-bit path but byte count */
97 97
98 98 #define DMAE_CYCLES_1 0 /* Compatible timing */
99 99 #define DMAE_CYCLES_2 1 /* Type "A" timing */
100 100 #define DMAE_CYCLES_3 2 /* Type "B" timing */
101 101 #define DMAE_CYCLES_4 3 /* Burst timing */
102 102
103 103 #define DMAE_DEST_IO 0 /* default */
104 104 #define DMAE_DEST_MEM 1
105 105
106 106
107 107
108 108 /* public function routines */
109 109 extern int i_dmae_init(dev_info_t *);
110 110 extern ddi_dma_cookie_t *_dmae_nxcookie(int);
111 111 extern int i_dmae_acquire(dev_info_t *, int, int (*)(), caddr_t);
112 112 extern int i_dmae_free(dev_info_t *, int);
113 113 extern int i_dmae_prog(dev_info_t *, struct ddi_dmae_req *,
114 114 ddi_dma_cookie_t *, int);
115 115 extern int i_dmae_swsetup(dev_info_t *, struct ddi_dmae_req *,
116 116 ddi_dma_cookie_t *, int);
117 117 extern void i_dmae_swstart(dev_info_t *, int);
118 118 extern void i_dmae_stop(dev_info_t *, int);
119 119 extern void i_dmae_enable(dev_info_t *, int);
120 120 extern void i_dmae_disable(dev_info_t *, int);
121 121 extern void i_dmae_get_chan_stat(dev_info_t *dip, int chnl,
122 122 ulong_t *addressp, int *countp);
123 123
124 124 /*
125 125 * the DMA Channel Block structure
126 126 */
127 127 struct dmae_chnl {
128 128 ksema_t dch_lock; /* semaphore for this channel */
129 129 ddi_dma_cookie_t *dch_cookiep; /* current dma mapping cookie */
130 130 ddi_dma_cookie_t *(*proc)(); /* address of application call */
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131 131 /* routine */
132 132 void *procparms; /* parameter buffer for appl call */
133 133 };
134 134
135 135
136 136 /*
137 137 * DMA Engine DDI functions
138 138 */
139 139
140 140 /*
141 - * Get DMA engine limits
142 - *
143 - * The limits of the DMA engine of the parent bus-nexus are copied into the
144 - * provided structure. This should be called at driver attach time,
145 - * rather than for each dma setup (breakup).
146 - */
147 -
148 -int ddi_dmae_getlim(dev_info_t *dip, ddi_dma_lim_t *limitsp);
149 -
150 -/*
151 141 * Get DMA engine attributes
152 142 *
153 143 * The attributes of the DMA engine of the parent bus-nexus are copied into
154 144 * the provided structure. This should be called at driver attach time,
155 145 * rather than for each DMA bind.
156 146 */
157 147
158 148 int ddi_dmae_getattr(dev_info_t *dip, ddi_dma_attr_t *attrp);
159 149
160 150 /*
161 151 * DMA channel allocation
162 152 *
163 153 * The allocation function must be called prior to any other DMA engine
164 154 * function on a channel. The channel should be freed after completion of the
165 155 * DMA / device operation if the channel is to be shared.
166 156 *
167 157 * Specifics of arguments to ddi_dmae_alloc:
168 158 *
169 159 * dip - dev_info pointer, which identifies the base device that wishes
170 160 * to use the DMA channel.
171 161 *
172 162 * chnl - a DMA channel number.
173 163 *
174 164 * dmae_waitfp - wait/callback_function pointer, which operates in the same
175 165 * manner as in ddi_dma_setup(). The value DDI_DMA_DONTWAIT will cause an
176 166 * immediate return if the channel cannot be acquired. The value
177 167 * DDI_DMA_SLEEP will will cause the thread to sleep and not return until
178 168 * the channel has been acquired. Any other value is assumed to be a
179 169 * callback function address.
180 170 *
181 171 * When resources might be available, the callback function is called
182 172 * (with the argument specified in arg) from interrupt context.
183 173 *
184 174 * When the callback function dmae_waitfp() is called, it should attempt to
185 175 * allocate the DMA channel again. If it succeeds or does not need the
186 176 * channel any more, it must return the value DDI_DMA_CALLBACK_DONE.
187 177 * If it does not want to allocate the channel, but instead wishes to be
188 178 * called back again later, it must return the value DDI_DMA_CALLBACK_LATER.
189 179 * If it tries to allocate the channel, but fails to do so, it must return the
190 180 * value DDI_DMA_CALLBACK_RUNOUT.
191 181 *
192 182 * Failure to observe this protocol will have unpredictable results.
193 183 *
194 184 * The callback function must provide its own data structure integrity
195 185 * when it is invoked.
196 186 */
197 187
198 188 int ddi_dmae_alloc(dev_info_t *dip, int chnl, int (*dmae_waitfp)(),
199 189 caddr_t arg);
200 190
201 191 /*
202 192 * DMA channel deallocation
203 193 *
204 194 * The deallocation function should be called after completion of the
205 195 * DMA / device operation if the channel is to be shared.
206 196 */
207 197
208 198 int ddi_dmae_release(dev_info_t *dip, int chnl);
209 199
210 200 /*
211 201 * DMA channel used in 1st party DMA scheme
212 202 *
213 203 * The specified channel will be configured to operate in a "slave" mode
214 204 * to a first_party DMA engine that also uses the channel.
215 205 */
216 206
217 207 int ddi_dmae_1stparty(dev_info_t *dip, int chnl);
218 208
219 209 /*
220 210 * Program DMA channel
221 211 *
222 212 * The DMA channel is setup for an operation using ddi_dmae_prog().
223 213 * This function is implemented to access all capabilities of the DMA engine
224 214 * hardware. This function disables the channel prior to setup, and enables
225 215 * the channel before returning.
226 216 *
227 217 * Specifics of arguments to ddi_dmae_prog:
228 218 *
229 219 * dmaereqp - pointer to a DMA engine request structure. This structure
230 220 * is implementation specific and contains all the info necessary to
231 221 * setup the channel, except for the memory address and count.
232 222 * This structure is implemented with default values equal to zero,
233 223 * so that normally only der_command has to be set with a read or write
234 224 * command value. Once the channel has been setup, subsequent calls to
235 225 * ddi_dmae_prog() can have dmaereqp set to NULL if only the address and
236 226 * count have to be updated.
237 227 *
238 228 * cookiep - pointer to a ddi_dma_cookie object which contains address,
239 229 * count and intermediate memory mapping information.
240 230 */
241 231
242 232 int ddi_dmae_prog(dev_info_t *dip, struct ddi_dmae_req *dmaereqp,
243 233 ddi_dma_cookie_t *cookiep, int chnl);
244 234
245 235 int ddi_dmae_swsetup(dev_info_t *dip, struct ddi_dmae_req *dmaereqp,
246 236 ddi_dma_cookie_t *cookiep, int chnl);
247 237
248 238 int ddi_dmae_swstart(dev_info_t *dip, int chnl);
249 239
250 240 /*
251 241 * Stop DMA channel
252 242 *
253 243 * The DMA channel is disabled and any active operation is terminated.
254 244 */
255 245
256 246 int ddi_dmae_stop(dev_info_t *dip, int chnl);
257 247
258 248 /*
259 249 * Enable DMA channel
260 250 *
261 251 * The DMA channel is enabled for operation. The channel is also enabled
262 252 * after successful setup in ddi_dmae_prog().
263 253 */
264 254
265 255 int ddi_dmae_enable(dev_info_t *dip, int chnl);
266 256
267 257 /*
268 258 * Disable DMA channel
269 259 *
270 260 * The DMA channel is disabled so that transfers cannot continue.
271 261 */
272 262
273 263 int ddi_dmae_disable(dev_info_t *dip, int chnl);
274 264
275 265 /*
276 266 * Get remaining xfer count
277 267 *
278 268 * The count register of the DMA channel is read. The channel is assumed
279 269 * to be stopped.
280 270 */
281 271
282 272 int ddi_dmae_getcnt(dev_info_t *dip, int chnl, int *count);
283 273
284 274 #ifdef __cplusplus
285 275 }
286 276 #endif
287 277
288 278 #endif /* !_SYS_DMAENGINE_H */
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