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5719 Add support for LSI Fury adapters
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--- old/usr/src/uts/common/io/mr_sas/mr_sas.h
+++ new/usr/src/uts/common/io/mr_sas/mr_sas.h
1 1 /*
2 2 * mr_sas.h: header for mr_sas
3 3 *
4 4 * Solaris MegaRAID driver for SAS2.0 controllers
5 5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 6 * All rights reserved.
7 7 *
8 8 * Version:
9 9 * Author:
10 10 * Swaminathan K S
11 11 * Arun Chandrashekhar
12 12 * Manju R
13 13 * Rasheed
14 14 * Shakeel Bukhari
15 15 *
16 16 * Redistribution and use in source and binary forms, with or without
17 17 * modification, are permitted provided that the following conditions are met:
18 18 *
19 19 * 1. Redistributions of source code must retain the above copyright notice,
20 20 * this list of conditions and the following disclaimer.
21 21 *
22 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 23 * this list of conditions and the following disclaimer in the documentation
24 24 * and/or other materials provided with the distribution.
25 25 *
26 26 * 3. Neither the name of the author nor the names of its contributors may be
27 27 * used to endorse or promote products derived from this software without
28 28 * specific prior written permission.
29 29 *
30 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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37 37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 41 * DAMAGE.
42 42 */
43 43
44 44 /*
45 45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 46 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
47 + * Copyright 2015 Garrett D'Amore <garrett@damore.org>
47 48 */
48 49
49 50 #ifndef _MR_SAS_H_
50 51 #define _MR_SAS_H_
51 52
52 53 #ifdef __cplusplus
53 54 extern "C" {
54 55 #endif
55 56
56 57 #include <sys/scsi/scsi.h>
57 58 #include "mr_sas_list.h"
58 59 #include "ld_pd_map.h"
59 60
60 61 /*
61 62 * MegaRAID SAS2.0 Driver meta data
62 63 */
63 64 #define MRSAS_VERSION "6.503.00.00ILLUMOS"
64 65 #define MRSAS_RELDATE "July 30, 2012"
65 66
66 67 #define MRSAS_TRUE 1
67 68 #define MRSAS_FALSE 0
68 69
69 70 #define ADAPTER_RESET_NOT_REQUIRED 0
70 71 #define ADAPTER_RESET_REQUIRED 1
71 72
72 73 #define PDSUPPORT 1
73 74
74 75 /*
75 76 * MegaRAID SAS2.0 device id conversion definitions.
76 77 */
77 78 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
78 79 #define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
79 80 int rem; \
80 81 rem = (len / boundary_len); \
81 82 if ((rem * boundary_len) != len) { \
82 83 new_len = len + ((rem + 1) * boundary_len - len); \
83 84 } else { \
84 85 new_len = len; \
85 86 } \
86 87 }
87 88
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88 89
89 90 /*
90 91 * MegaRAID SAS2.0 supported controllers
91 92 */
92 93 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
93 94 #define PCI_DEVICE_ID_LSI_2108V 0x0079
94 95 #define PCI_DEVICE_ID_LSI_SKINNY 0x0071
95 96 #define PCI_DEVICE_ID_LSI_SKINNY_NEW 0x0073
96 97 #define PCI_DEVICE_ID_LSI_TBOLT 0x005b
97 98 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
99 +#define PCI_DEVICE_ID_LSI_FURY 0x005f
98 100
99 101 /*
100 102 * Register Index for 2108 Controllers.
101 103 */
102 104 #define REGISTER_SET_IO_2108 (2)
103 105
104 106 #define MRSAS_MAX_SGE_CNT 0x50
105 107 #define MRSAS_APP_RESERVED_CMDS 32
106 108 #define MRSAS_APP_MIN_RESERVED_CMDS 4
107 109
108 110 #define MRSAS_IOCTL_DRIVER 0x12341234
109 111 #define MRSAS_IOCTL_FIRMWARE 0x12345678
110 112 #define MRSAS_IOCTL_AEN 0x87654321
111 113
112 114 #define MRSAS_1_SECOND 1000000
113 115
114 116 #ifdef PDSUPPORT
115 117
116 118 #define UNCONFIGURED_GOOD 0x0
117 119 #define PD_SYSTEM 0x40
118 120 #define MR_EVT_PD_STATE_CHANGE 0x0072
119 121 #define MR_EVT_PD_REMOVED_EXT 0x00f8
120 122 #define MR_EVT_PD_INSERTED_EXT 0x00f7
121 123 #define MR_DCMD_PD_GET_INFO 0x02020000
122 124 #define MRSAS_TBOLT_PD_LUN 1
123 125 #define MRSAS_TBOLT_PD_TGT_MAX 255
124 126 #define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
125 127
126 128 #endif
127 129
128 130 /* Raid Context Flags */
129 131 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
130 132 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
131 133 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
132 134 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
133 135 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
134 136 } MR_RAID_FLAGS_IO_SUB_TYPE;
135 137
136 138 /* Dynamic Enumeration Flags */
137 139 #define MRSAS_LD_LUN 0
138 140 #define WWN_STRLEN 17
139 141 #define LD_SYNC_BIT 1
140 142 #define LD_SYNC_SHIFT 14
141 143 /* ThunderBolt (TB) specific */
142 144 #define MRSAS_THUNDERBOLT_MSG_SIZE 256
143 145 #define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
144 146 #define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
145 147 #define MRSAS_THUNDERBOLT_REPLY_SIZE 8
146 148 #define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
147 149
148 150 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
149 151 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
150 152
151 153 #define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
152 154
153 155 #define MR_INTERNAL_MFI_FRAMES_SMID 1
154 156 #define MR_CTRL_EVENT_WAIT_SMID 2
155 157 #define MR_INTERNAL_DRIVER_RESET_SMID 3
156 158
157 159
158 160 /*
159 161 * =====================================
160 162 * MegaRAID SAS2.0 MFI firmware definitions
161 163 * =====================================
162 164 */
163 165 /*
164 166 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
165 167 * protocol between the software and firmware. Commands are issued using
166 168 * "message frames"
167 169 */
168 170
169 171 /*
170 172 * FW posts its state in upper 4 bits of outbound_msg_0 register
171 173 */
172 174 #define MFI_STATE_MASK 0xF0000000
173 175 #define MFI_STATE_UNDEFINED 0x00000000
174 176 #define MFI_STATE_BB_INIT 0x10000000
175 177 #define MFI_STATE_FW_INIT 0x40000000
176 178 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
177 179 #define MFI_STATE_FW_INIT_2 0x70000000
178 180 #define MFI_STATE_DEVICE_SCAN 0x80000000
179 181 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
180 182 #define MFI_STATE_FLUSH_CACHE 0xA0000000
181 183 #define MFI_STATE_READY 0xB0000000
182 184 #define MFI_STATE_OPERATIONAL 0xC0000000
183 185 #define MFI_STATE_FAULT 0xF0000000
184 186
185 187 #define MRMFI_FRAME_SIZE 64
186 188
187 189 /*
188 190 * During FW init, clear pending cmds & reset state using inbound_msg_0
189 191 *
190 192 * ABORT : Abort all pending cmds
191 193 * READY : Move from OPERATIONAL to READY state; discard queue info
192 194 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
193 195 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
194 196 */
195 197 #define MFI_INIT_ABORT 0x00000001
196 198 #define MFI_INIT_READY 0x00000002
197 199 #define MFI_INIT_MFIMODE 0x00000004
198 200 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
199 201 #define MFI_INIT_HOTPLUG 0x00000010
200 202 #define MFI_STOP_ADP 0x00000020
201 203 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
202 204
203 205 /*
204 206 * MFI frame flags
205 207 */
206 208 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
207 209 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
208 210 #define MFI_FRAME_SGL32 0x0000
209 211 #define MFI_FRAME_SGL64 0x0002
210 212 #define MFI_FRAME_SENSE32 0x0000
211 213 #define MFI_FRAME_SENSE64 0x0004
212 214 #define MFI_FRAME_DIR_NONE 0x0000
213 215 #define MFI_FRAME_DIR_WRITE 0x0008
214 216 #define MFI_FRAME_DIR_READ 0x0010
215 217 #define MFI_FRAME_DIR_BOTH 0x0018
216 218 #define MFI_FRAME_IEEE 0x0020
217 219
218 220 /*
219 221 * Definition for cmd_status
220 222 */
221 223 #define MFI_CMD_STATUS_POLL_MODE 0xFF
222 224 #define MFI_CMD_STATUS_SYNC_MODE 0xFF
223 225
224 226 /*
225 227 * MFI command opcodes
226 228 */
227 229 #define MFI_CMD_OP_INIT 0x00
228 230 #define MFI_CMD_OP_LD_READ 0x01
229 231 #define MFI_CMD_OP_LD_WRITE 0x02
230 232 #define MFI_CMD_OP_LD_SCSI 0x03
231 233 #define MFI_CMD_OP_PD_SCSI 0x04
232 234 #define MFI_CMD_OP_DCMD 0x05
233 235 #define MFI_CMD_OP_ABORT 0x06
234 236 #define MFI_CMD_OP_SMP 0x07
235 237 #define MFI_CMD_OP_STP 0x08
236 238
237 239 #define MR_DCMD_CTRL_GET_INFO 0x01010000
238 240
239 241 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
240 242 #define MR_FLUSH_CTRL_CACHE 0x01
241 243 #define MR_FLUSH_DISK_CACHE 0x02
242 244
243 245 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
244 246 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
245 247
246 248 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
247 249 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
248 250 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
249 251 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
250 252
251 253 /*
252 254 * Solaris Specific MAX values
253 255 */
254 256 #define MAX_SGL 24
255 257
256 258 /*
257 259 * MFI command completion codes
258 260 */
259 261 enum MFI_STAT {
260 262 MFI_STAT_OK = 0x00,
261 263 MFI_STAT_INVALID_CMD = 0x01,
262 264 MFI_STAT_INVALID_DCMD = 0x02,
263 265 MFI_STAT_INVALID_PARAMETER = 0x03,
264 266 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
265 267 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
266 268 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
267 269 MFI_STAT_APP_IN_USE = 0x07,
268 270 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
269 271 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
270 272 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
271 273 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
272 274 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
273 275 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
274 276 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
275 277 MFI_STAT_FLASH_BUSY = 0x0f,
276 278 MFI_STAT_FLASH_ERROR = 0x10,
277 279 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
278 280 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
279 281 MFI_STAT_FLASH_NOT_OPEN = 0x13,
280 282 MFI_STAT_FLASH_NOT_STARTED = 0x14,
281 283 MFI_STAT_FLUSH_FAILED = 0x15,
282 284 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
283 285 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
284 286 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
285 287 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
286 288 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
287 289 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
288 290 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
289 291 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
290 292 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
291 293 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
292 294 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
293 295 MFI_STAT_MFC_HW_ERROR = 0x21,
294 296 MFI_STAT_NO_HW_PRESENT = 0x22,
295 297 MFI_STAT_NOT_FOUND = 0x23,
296 298 MFI_STAT_NOT_IN_ENCL = 0x24,
297 299 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
298 300 MFI_STAT_PD_TYPE_WRONG = 0x26,
299 301 MFI_STAT_PR_DISABLED = 0x27,
300 302 MFI_STAT_ROW_INDEX_INVALID = 0x28,
301 303 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
302 304 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
303 305 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
304 306 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
305 307 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
306 308 MFI_STAT_SCSI_IO_FAILED = 0x2e,
307 309 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
308 310 MFI_STAT_SHUTDOWN_FAILED = 0x30,
309 311 MFI_STAT_TIME_NOT_SET = 0x31,
310 312 MFI_STAT_WRONG_STATE = 0x32,
311 313 MFI_STAT_LD_OFFLINE = 0x33,
312 314 MFI_STAT_INVALID_STATUS = 0xFF
313 315 };
314 316
315 317 enum MR_EVT_CLASS {
316 318 MR_EVT_CLASS_DEBUG = -2,
317 319 MR_EVT_CLASS_PROGRESS = -1,
318 320 MR_EVT_CLASS_INFO = 0,
319 321 MR_EVT_CLASS_WARNING = 1,
320 322 MR_EVT_CLASS_CRITICAL = 2,
321 323 MR_EVT_CLASS_FATAL = 3,
322 324 MR_EVT_CLASS_DEAD = 4
323 325 };
324 326
325 327 enum MR_EVT_LOCALE {
326 328 MR_EVT_LOCALE_LD = 0x0001,
327 329 MR_EVT_LOCALE_PD = 0x0002,
328 330 MR_EVT_LOCALE_ENCL = 0x0004,
329 331 MR_EVT_LOCALE_BBU = 0x0008,
330 332 MR_EVT_LOCALE_SAS = 0x0010,
331 333 MR_EVT_LOCALE_CTRL = 0x0020,
332 334 MR_EVT_LOCALE_CONFIG = 0x0040,
333 335 MR_EVT_LOCALE_CLUSTER = 0x0080,
334 336 MR_EVT_LOCALE_ALL = 0xffff
335 337 };
336 338
337 339 enum MR_EVT_ARGS {
338 340 MR_EVT_ARGS_NONE,
339 341 MR_EVT_ARGS_CDB_SENSE,
340 342 MR_EVT_ARGS_LD,
341 343 MR_EVT_ARGS_LD_COUNT,
342 344 MR_EVT_ARGS_LD_LBA,
343 345 MR_EVT_ARGS_LD_OWNER,
344 346 MR_EVT_ARGS_LD_LBA_PD_LBA,
345 347 MR_EVT_ARGS_LD_PROG,
346 348 MR_EVT_ARGS_LD_STATE,
347 349 MR_EVT_ARGS_LD_STRIP,
348 350 MR_EVT_ARGS_PD,
349 351 MR_EVT_ARGS_PD_ERR,
350 352 MR_EVT_ARGS_PD_LBA,
351 353 MR_EVT_ARGS_PD_LBA_LD,
352 354 MR_EVT_ARGS_PD_PROG,
353 355 MR_EVT_ARGS_PD_STATE,
354 356 MR_EVT_ARGS_PCI,
355 357 MR_EVT_ARGS_RATE,
356 358 MR_EVT_ARGS_STR,
357 359 MR_EVT_ARGS_TIME,
358 360 MR_EVT_ARGS_ECC
359 361 };
360 362
361 363 #define MR_EVT_CFG_CLEARED 0x0004
362 364 #define MR_EVT_LD_CREATED 0x008a
363 365 #define MR_EVT_LD_DELETED 0x008b
364 366 #define MR_EVT_CFG_FP_CHANGE 0x017B
365 367
366 368 enum LD_STATE {
367 369 LD_OFFLINE = 0,
368 370 LD_PARTIALLY_DEGRADED = 1,
369 371 LD_DEGRADED = 2,
370 372 LD_OPTIMAL = 3,
371 373 LD_INVALID = 0xFF
372 374 };
373 375
374 376 enum MRSAS_EVT {
375 377 MRSAS_EVT_CONFIG_TGT = 0,
376 378 MRSAS_EVT_UNCONFIG_TGT = 1,
377 379 MRSAS_EVT_UNCONFIG_SMP = 2
378 380 };
379 381
380 382 #define DMA_OBJ_ALLOCATED 1
381 383 #define DMA_OBJ_REALLOCATED 2
382 384 #define DMA_OBJ_FREED 3
383 385
384 386 /*
385 387 * dma_obj_t - Our DMA object
386 388 * @param buffer : kernel virtual address
387 389 * @param size : size of the data to be allocated
388 390 * @param acc_handle : access handle
389 391 * @param dma_handle : dma handle
390 392 * @param dma_cookie : scatter-gather list
391 393 * @param dma_attr : dma attributes for this buffer
392 394 *
393 395 * Our DMA object. The caller must initialize the size and dma attributes
394 396 * (dma_attr) fields before allocating the resources.
395 397 */
396 398 typedef struct {
397 399 caddr_t buffer;
398 400 uint32_t size;
399 401 ddi_acc_handle_t acc_handle;
400 402 ddi_dma_handle_t dma_handle;
401 403 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
402 404 ddi_dma_attr_t dma_attr;
403 405 uint8_t status;
404 406 uint8_t reserved[3];
405 407 } dma_obj_t;
406 408
407 409 struct mrsas_eventinfo {
408 410 struct mrsas_instance *instance;
409 411 int tgt;
410 412 int lun;
411 413 int event;
412 414 uint64_t wwn;
413 415 };
414 416
415 417 struct mrsas_ld {
416 418 dev_info_t *dip;
417 419 uint8_t lun_type;
418 420 uint8_t flag;
419 421 uint8_t reserved[2];
420 422 };
421 423
422 424
423 425 #ifdef PDSUPPORT
424 426 struct mrsas_tbolt_pd {
425 427 dev_info_t *dip;
426 428 uint8_t lun_type;
427 429 uint8_t dev_id;
428 430 uint8_t flag;
429 431 uint8_t reserved;
430 432 };
431 433 struct mrsas_tbolt_pd_info {
432 434 uint16_t deviceId;
433 435 uint16_t seqNum;
434 436 uint8_t inquiryData[96];
435 437 uint8_t vpdPage83[64];
436 438 uint8_t notSupported;
437 439 uint8_t scsiDevType;
438 440 uint8_t a;
439 441 uint8_t device_speed;
440 442 uint32_t mediaerrcnt;
441 443 uint32_t other;
442 444 uint32_t pred;
443 445 uint32_t lastpred;
444 446 uint16_t fwState;
445 447 uint8_t disabled;
446 448 uint8_t linkspwwd;
447 449 uint32_t ddfType;
448 450 struct {
449 451 uint8_t count;
450 452 uint8_t isPathBroken;
451 453 uint8_t connectorIndex[2];
452 454 uint8_t reserved[4];
453 455 uint64_t sasAddr[2];
454 456 uint8_t reserved2[16];
455 457 } pathInfo;
456 458 };
457 459 #endif
458 460
459 461 typedef struct mrsas_instance {
460 462 uint32_t *producer;
461 463 uint32_t *consumer;
462 464
463 465 uint32_t *reply_queue;
464 466 dma_obj_t mfi_internal_dma_obj;
465 467 uint16_t adapterresetinprogress;
466 468 uint16_t deadadapter;
467 469 /* ThunderBolt (TB) specific */
468 470 dma_obj_t mpi2_frame_pool_dma_obj;
469 471 dma_obj_t request_desc_dma_obj;
470 472 dma_obj_t reply_desc_dma_obj;
471 473 dma_obj_t ld_map_obj[2];
472 474
473 475 uint8_t init_id;
474 476 uint8_t flag_ieee;
475 477 uint8_t disable_online_ctrl_reset;
476 478 uint8_t fw_fault_count_after_ocr;
477 479
478 480 uint16_t max_num_sge;
479 481 uint16_t max_fw_cmds;
480 482 uint32_t max_sectors_per_req;
481 483
482 484 struct mrsas_cmd **cmd_list;
483 485
484 486 mlist_t cmd_pool_list;
485 487 kmutex_t cmd_pool_mtx;
486 488 kmutex_t sync_map_mtx;
487 489
488 490 mlist_t app_cmd_pool_list;
489 491 kmutex_t app_cmd_pool_mtx;
490 492 mlist_t cmd_app_pool_list;
491 493 kmutex_t cmd_app_pool_mtx;
492 494
493 495
494 496 mlist_t cmd_pend_list;
495 497 kmutex_t cmd_pend_mtx;
496 498
497 499 dma_obj_t mfi_evt_detail_obj;
498 500 struct mrsas_cmd *aen_cmd;
499 501
500 502 uint32_t aen_seq_num;
501 503 uint32_t aen_class_locale_word;
502 504
503 505 scsi_hba_tran_t *tran;
504 506
505 507 kcondvar_t int_cmd_cv;
506 508 kmutex_t int_cmd_mtx;
507 509
508 510 kcondvar_t aen_cmd_cv;
509 511 kmutex_t aen_cmd_mtx;
510 512
511 513 kcondvar_t abort_cmd_cv;
512 514 kmutex_t abort_cmd_mtx;
513 515
514 516 kmutex_t reg_write_mtx;
515 517 kmutex_t chip_mtx;
516 518
517 519 dev_info_t *dip;
518 520 ddi_acc_handle_t pci_handle;
519 521
520 522 timeout_id_t timeout_id;
521 523 uint32_t unique_id;
522 524 uint16_t fw_outstanding;
523 525 caddr_t regmap;
524 526 ddi_acc_handle_t regmap_handle;
525 527 uint8_t isr_level;
526 528 ddi_iblock_cookie_t iblock_cookie;
527 529 ddi_iblock_cookie_t soft_iblock_cookie;
528 530 ddi_softintr_t soft_intr_id;
529 531 uint8_t softint_running;
530 532 uint8_t tbolt_softint_running;
531 533 kmutex_t completed_pool_mtx;
532 534 mlist_t completed_pool_list;
533 535
534 536 caddr_t internal_buf;
535 537 uint32_t internal_buf_dmac_add;
536 538 uint32_t internal_buf_size;
537 539
538 540 uint16_t vendor_id;
539 541 uint16_t device_id;
540 542 uint16_t subsysvid;
541 543 uint16_t subsysid;
542 544 int instance;
543 545 int baseaddress;
544 546 char iocnode[16];
545 547
546 548 int fm_capabilities;
547 549 /*
548 550 * Driver resources unroll flags. The flag is set for resources that
549 551 * are needed to be free'd at detach() time.
550 552 */
551 553 struct _unroll {
552 554 uint8_t softs; /* The software state was allocated. */
553 555 uint8_t regs; /* Controller registers mapped. */
554 556 uint8_t intr; /* Interrupt handler added. */
555 557 uint8_t reqs; /* Request structs allocated. */
556 558 uint8_t mutexs; /* Mutex's allocated. */
557 559 uint8_t taskq; /* Task q's created. */
558 560 uint8_t tran; /* Tran struct allocated */
559 561 uint8_t tranSetup; /* Tran attached to the ddi. */
560 562 uint8_t devctl; /* Device nodes for cfgadm created. */
561 563 uint8_t scsictl; /* Device nodes for cfgadm created. */
562 564 uint8_t ioctl; /* Device nodes for ioctl's created. */
563 565 uint8_t timer; /* Timer started. */
564 566 uint8_t aenPend; /* AEN cmd pending f/w. */
565 567 uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */
566 568 uint8_t soft_isr; /* Soft interrupt handler allocated. */
567 569 uint8_t ldlist_buff; /* Logical disk list allocated. */
568 570 uint8_t pdlist_buff; /* Physical disk list allocated. */
569 571 uint8_t syncCmd; /* Sync map command allocated. */
570 572 uint8_t verBuff; /* 2108 MFI buffer allocated. */
571 573 uint8_t alloc_space_mfi; /* Allocated space for 2108 MFI. */
572 574 uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */
573 575 } unroll;
574 576
575 577
576 578 /* function template pointer */
577 579 struct mrsas_function_template *func_ptr;
578 580
579 581
580 582 /* MSI interrupts specific */
581 583 ddi_intr_handle_t *intr_htable; /* Interrupt handle array */
582 584 size_t intr_htable_size; /* Int. handle array size */
583 585 int intr_type;
584 586 int intr_cnt;
585 587 uint_t intr_pri;
586 588 int intr_cap;
587 589
588 590 ddi_taskq_t *taskq;
589 591 struct mrsas_ld *mr_ld_list;
590 592 kmutex_t config_dev_mtx;
591 593 /* ThunderBolt (TB) specific */
592 594 ddi_softintr_t tbolt_soft_intr_id;
593 595
594 596 #ifdef PDSUPPORT
595 597 uint32_t mr_tbolt_pd_max;
596 598 struct mrsas_tbolt_pd *mr_tbolt_pd_list;
597 599 #endif
598 600
599 601 uint8_t fast_path_io;
600 602
601 603 uint8_t skinny;
602 604 uint8_t tbolt;
603 605 uint16_t reply_read_index;
604 606 uint16_t reply_size; /* Single Reply struct size */
605 607 uint16_t raid_io_msg_size; /* Single message size */
606 608 uint32_t io_request_frames_phy;
607 609 uint8_t *io_request_frames;
608 610 /* Virtual address of request desc frame pool */
609 611 MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool;
610 612 /* Physical address of request desc frame pool */
611 613 uint32_t request_message_pool_phy;
612 614 /* Virtual address of reply Frame */
613 615 MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool;
614 616 /* Physical address of reply Frame */
615 617 uint32_t reply_frame_pool_phy;
616 618 uint8_t *reply_pool_limit; /* Last reply frame address */
617 619 /* Physical address of Last reply frame */
618 620 uint32_t reply_pool_limit_phy;
619 621 uint32_t reply_q_depth; /* Reply Queue Depth */
620 622 uint8_t max_sge_in_main_msg;
621 623 uint8_t max_sge_in_chain;
622 624 uint8_t chain_offset_io_req;
623 625 uint8_t chain_offset_mpt_msg;
624 626 MR_FW_RAID_MAP_ALL *ld_map[2];
625 627 uint32_t ld_map_phy[2];
626 628 uint32_t size_map_info;
627 629 uint64_t map_id;
628 630 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
629 631 struct mrsas_cmd *map_update_cmd;
630 632 uint32_t SyncRequired;
631 633 kmutex_t ocr_flags_mtx;
632 634 dma_obj_t drv_ver_dma_obj;
633 635 } mrsas_t;
634 636
635 637
636 638 /*
637 639 * Function templates for various controller specific functions
638 640 */
639 641 struct mrsas_function_template {
640 642 uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
641 643 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
642 644 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
643 645 struct mrsas_cmd *);
644 646 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
645 647 struct mrsas_cmd *);
646 648 void (*enable_intr)(struct mrsas_instance *);
647 649 void (*disable_intr)(struct mrsas_instance *);
648 650 int (*intr_ack)(struct mrsas_instance *);
649 651 int (*init_adapter)(struct mrsas_instance *);
650 652 /* int (*reset_adapter)(struct mrsas_instance *); */
651 653 };
652 654
653 655 /*
654 656 * ### Helper routines ###
655 657 */
656 658
657 659 /*
658 660 * con_log() - console log routine
659 661 * @param level : indicates the severity of the message.
660 662 * @fparam mt : format string
661 663 *
662 664 * con_log displays the error messages on the console based on the current
663 665 * debug level. Also it attaches the appropriate kernel severity level with
664 666 * the message.
665 667 *
666 668 *
667 669 * console messages debug levels
668 670 */
669 671 #define CL_NONE 0 /* No debug information */
670 672 #define CL_ANN 1 /* print unconditionally, announcements */
671 673 #define CL_ANN1 2 /* No-op */
672 674 #define CL_DLEVEL1 3 /* debug level 1, informative */
673 675 #define CL_DLEVEL2 4 /* debug level 2, verbose */
674 676 #define CL_DLEVEL3 5 /* debug level 3, very verbose */
675 677
676 678 #ifdef __SUNPRO_C
677 679 #define __func__ ""
678 680 #endif
679 681
680 682 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
681 683
682 684 /*
683 685 * ### SCSA definitions ###
684 686 */
685 687 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
686 688 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
687 689 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
688 690 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
689 691
690 692 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
691 693 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
692 694
693 695 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
694 696 #define CMD2PKT(sp) ((sp)->cmd_pkt)
695 697 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
696 698
697 699 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address)
698 700 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran)
699 701 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd)))
700 702
701 703 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */
702 704 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */
703 705 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */
704 706
705 707 /*
706 708 * ### Data structures for ioctl inteface and internal commands ###
707 709 */
708 710
709 711 /*
710 712 * Data direction flags
711 713 */
712 714 #define UIOC_RD 0x00001
713 715 #define UIOC_WR 0x00002
714 716
715 717 #define SCP2HOST(scp) (scp)->device->host /* to host */
716 718 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
717 719 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
718 720 #define SCP2TARGET(scp) (scp)->device->id /* to target */
719 721 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
720 722
721 723 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
722 724 #define SCP2ADAPTER(scp) \
723 725 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
724 726
725 727 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
726 728 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
727 729 #define MRDRV_IS_LOGICAL(ap) \
728 730 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
729 731 #define MAP_DEVICE_ID(instance, ap) \
730 732 (ap->a_target)
731 733
732 734 #define HIGH_LEVEL_INTR 1
733 735 #define NORMAL_LEVEL_INTR 0
734 736
735 737 #define IO_TIMEOUT_VAL 0
736 738 #define IO_RETRY_COUNT 3
737 739 #define MAX_FW_RESET_COUNT 3
738 740 /*
739 741 * scsa_cmd - Per-command mr private data
740 742 * @param cmd_dmahandle : dma handle
741 743 * @param cmd_dmacookies : current dma cookies
742 744 * @param cmd_pkt : scsi_pkt reference
743 745 * @param cmd_dmacount : dma count
744 746 * @param cmd_cookie : next cookie
745 747 * @param cmd_ncookies : cookies per window
746 748 * @param cmd_cookiecnt : cookies per sub-win
747 749 * @param cmd_nwin : number of dma windows
748 750 * @param cmd_curwin : current dma window
749 751 * @param cmd_dma_offset : current window offset
750 752 * @param cmd_dma_len : current window length
751 753 * @param cmd_flags : private flags
752 754 * @param cmd_cdblen : length of cdb
753 755 * @param cmd_scblen : length of scb
754 756 * @param cmd_buf : command buffer
755 757 * @param channel : channel for scsi sub-system
756 758 * @param target : target for scsi sub-system
757 759 * @param lun : LUN for scsi sub-system
758 760 *
759 761 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
760 762 * - Pointed to by pkt_ha_private field in scsi_pkt
761 763 */
762 764 struct scsa_cmd {
763 765 ddi_dma_handle_t cmd_dmahandle;
764 766 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT];
765 767 struct scsi_pkt *cmd_pkt;
766 768 ulong_t cmd_dmacount;
767 769 uint_t cmd_cookie;
768 770 uint_t cmd_ncookies;
769 771 uint_t cmd_cookiecnt;
770 772 uint_t cmd_nwin;
771 773 uint_t cmd_curwin;
772 774 off_t cmd_dma_offset;
773 775 ulong_t cmd_dma_len;
774 776 ulong_t cmd_flags;
775 777 uint_t cmd_cdblen;
776 778 uint_t cmd_scblen;
777 779 struct buf *cmd_buf;
778 780 ushort_t device_id;
779 781 uchar_t islogical;
780 782 uchar_t lun;
781 783 struct mrsas_device *mrsas_dev;
782 784 };
783 785
784 786
785 787 struct mrsas_cmd {
786 788 /*
787 789 * ThunderBolt(TB) We would be needing to have a placeholder
788 790 * for RAID_MSG_IO_REQUEST inside this structure. We are
789 791 * supposed to embed the mr_frame inside the RAID_MSG and post
790 792 * it down to the firmware.
791 793 */
792 794 union mrsas_frame *frame;
793 795 uint32_t frame_phys_addr;
794 796 uint8_t *sense;
795 797 uint8_t *sense1;
796 798 uint32_t sense_phys_addr;
797 799 uint32_t sense_phys_addr1;
798 800 dma_obj_t frame_dma_obj;
799 801 uint8_t frame_dma_obj_status;
800 802 uint32_t index;
801 803 uint8_t sync_cmd;
802 804 uint8_t cmd_status;
803 805 uint16_t abort_aen;
804 806 mlist_t list;
805 807 uint32_t frame_count;
806 808 struct scsa_cmd *cmd;
807 809 struct scsi_pkt *pkt;
808 810 Mpi2RaidSCSIIORequest_t *scsi_io_request;
809 811 Mpi2SGEIOUnion_t *sgl;
810 812 uint32_t sgl_phys_addr;
811 813 uint32_t scsi_io_request_phys_addr;
812 814 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
813 815 uint16_t SMID;
814 816 uint16_t retry_count_for_ocr;
815 817 uint16_t drv_pkt_time;
816 818 uint16_t load_balance_flag;
817 819
818 820 };
819 821
820 822 #define MAX_MGMT_ADAPTERS 1024
821 823 #define IOC_SIGNATURE "MR-SAS"
822 824
823 825 #define IOC_CMD_FIRMWARE 0x0
824 826 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
825 827 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
826 828 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
827 829 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
828 830
829 831
830 832 #define MRSAS_MAX_SENSE_LENGTH 32
831 833
832 834 struct mrsas_mgmt_info {
833 835
834 836 uint16_t count;
835 837 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
836 838 uint16_t map[MAX_MGMT_ADAPTERS];
837 839 int max_index;
838 840 };
839 841
840 842
841 843 #pragma pack(1)
842 844 /*
843 845 * SAS controller properties
844 846 */
845 847 struct mrsas_ctrl_prop {
846 848 uint16_t seq_num;
847 849 uint16_t pred_fail_poll_interval;
848 850 uint16_t intr_throttle_count;
849 851 uint16_t intr_throttle_timeouts;
850 852
851 853 uint8_t rebuild_rate;
852 854 uint8_t patrol_read_rate;
853 855 uint8_t bgi_rate;
854 856 uint8_t cc_rate;
855 857 uint8_t recon_rate;
856 858
857 859 uint8_t cache_flush_interval;
858 860
859 861 uint8_t spinup_drv_count;
860 862 uint8_t spinup_delay;
861 863
862 864 uint8_t cluster_enable;
863 865 uint8_t coercion_mode;
864 866 uint8_t alarm_enable;
865 867
866 868 uint8_t reserved_1[13];
867 869 uint32_t on_off_properties;
868 870 uint8_t reserved_4[28];
869 871 };
870 872
871 873
872 874 /*
873 875 * SAS controller information
874 876 */
875 877 struct mrsas_ctrl_info {
876 878 /* PCI device information */
877 879 struct {
878 880 uint16_t vendor_id;
879 881 uint16_t device_id;
880 882 uint16_t sub_vendor_id;
881 883 uint16_t sub_device_id;
882 884 uint8_t reserved[24];
883 885 } pci;
884 886
885 887 /* Host interface information */
886 888 struct {
887 889 uint8_t PCIX : 1;
888 890 uint8_t PCIE : 1;
889 891 uint8_t iSCSI : 1;
890 892 uint8_t SAS_3G : 1;
891 893 uint8_t reserved_0 : 4;
892 894 uint8_t reserved_1[6];
893 895 uint8_t port_count;
894 896 uint64_t port_addr[8];
895 897 } host_interface;
896 898
897 899 /* Device (backend) interface information */
898 900 struct {
899 901 uint8_t SPI : 1;
900 902 uint8_t SAS_3G : 1;
901 903 uint8_t SATA_1_5G : 1;
902 904 uint8_t SATA_3G : 1;
903 905 uint8_t reserved_0 : 4;
904 906 uint8_t reserved_1[6];
905 907 uint8_t port_count;
906 908 uint64_t port_addr[8];
907 909 } device_interface;
908 910
909 911 /* List of components residing in flash. All str are null terminated */
910 912 uint32_t image_check_word;
911 913 uint32_t image_component_count;
912 914
913 915 struct {
914 916 char name[8];
915 917 char version[32];
916 918 char build_date[16];
917 919 char built_time[16];
918 920 } image_component[8];
919 921
920 922 /*
921 923 * List of flash components that have been flashed on the card, but
922 924 * are not in use, pending reset of the adapter. This list will be
923 925 * empty if a flash operation has not occurred. All stings are null
924 926 * terminated
925 927 */
926 928 uint32_t pending_image_component_count;
927 929
928 930 struct {
929 931 char name[8];
930 932 char version[32];
931 933 char build_date[16];
932 934 char build_time[16];
933 935 } pending_image_component[8];
934 936
935 937 uint8_t max_arms;
936 938 uint8_t max_spans;
937 939 uint8_t max_arrays;
938 940 uint8_t max_lds;
939 941
940 942 char product_name[80];
941 943 char serial_no[32];
942 944
943 945 /*
944 946 * Other physical/controller/operation information. Indicates the
945 947 * presence of the hardware
946 948 */
947 949 struct {
948 950 uint32_t bbu : 1;
949 951 uint32_t alarm : 1;
950 952 uint32_t nvram : 1;
951 953 uint32_t uart : 1;
952 954 uint32_t reserved : 28;
953 955 } hw_present;
954 956
955 957 uint32_t current_fw_time;
956 958
957 959 /* Maximum data transfer sizes */
958 960 uint16_t max_concurrent_cmds;
959 961 uint16_t max_sge_count;
960 962 uint32_t max_request_size;
961 963
962 964 /* Logical and physical device counts */
963 965 uint16_t ld_present_count;
964 966 uint16_t ld_degraded_count;
965 967 uint16_t ld_offline_count;
966 968
967 969 uint16_t pd_present_count;
968 970 uint16_t pd_disk_present_count;
969 971 uint16_t pd_disk_pred_failure_count;
970 972 uint16_t pd_disk_failed_count;
971 973
972 974 /* Memory size information */
973 975 uint16_t nvram_size;
974 976 uint16_t memory_size;
975 977 uint16_t flash_size;
976 978
977 979 /* Error counters */
978 980 uint16_t mem_correctable_error_count;
979 981 uint16_t mem_uncorrectable_error_count;
980 982
981 983 /* Cluster information */
982 984 uint8_t cluster_permitted;
983 985 uint8_t cluster_active;
984 986 uint8_t reserved_1[2];
985 987
986 988 /* Controller capabilities structures */
987 989 struct {
988 990 uint32_t raid_level_0 : 1;
989 991 uint32_t raid_level_1 : 1;
990 992 uint32_t raid_level_5 : 1;
991 993 uint32_t raid_level_1E : 1;
992 994 uint32_t reserved : 28;
993 995 } raid_levels;
994 996
995 997 struct {
996 998 uint32_t rbld_rate : 1;
997 999 uint32_t cc_rate : 1;
998 1000 uint32_t bgi_rate : 1;
999 1001 uint32_t recon_rate : 1;
1000 1002 uint32_t patrol_rate : 1;
1001 1003 uint32_t alarm_control : 1;
1002 1004 uint32_t cluster_supported : 1;
1003 1005 uint32_t bbu : 1;
1004 1006 uint32_t spanning_allowed : 1;
1005 1007 uint32_t dedicated_hotspares : 1;
1006 1008 uint32_t revertible_hotspares : 1;
1007 1009 uint32_t foreign_config_import : 1;
1008 1010 uint32_t self_diagnostic : 1;
1009 1011 uint32_t reserved : 19;
1010 1012 } adapter_operations;
1011 1013
1012 1014 struct {
1013 1015 uint32_t read_policy : 1;
1014 1016 uint32_t write_policy : 1;
1015 1017 uint32_t io_policy : 1;
1016 1018 uint32_t access_policy : 1;
1017 1019 uint32_t reserved : 28;
1018 1020 } ld_operations;
1019 1021
1020 1022 struct {
1021 1023 uint8_t min;
1022 1024 uint8_t max;
1023 1025 uint8_t reserved[2];
1024 1026 } stripe_size_operations;
1025 1027
1026 1028 struct {
1027 1029 uint32_t force_online : 1;
1028 1030 uint32_t force_offline : 1;
1029 1031 uint32_t force_rebuild : 1;
1030 1032 uint32_t reserved : 29;
1031 1033 } pd_operations;
1032 1034
1033 1035 struct {
1034 1036 uint32_t ctrl_supports_sas : 1;
1035 1037 uint32_t ctrl_supports_sata : 1;
1036 1038 uint32_t allow_mix_in_encl : 1;
1037 1039 uint32_t allow_mix_in_ld : 1;
1038 1040 uint32_t allow_sata_in_cluster : 1;
1039 1041 uint32_t reserved : 27;
1040 1042 } pd_mix_support;
1041 1043
1042 1044 /* Include the controller properties (changeable items) */
1043 1045 uint8_t reserved_2[12];
1044 1046 struct mrsas_ctrl_prop properties;
1045 1047
1046 1048 uint8_t pad[0x800 - 0x640];
1047 1049 };
1048 1050
1049 1051 /*
1050 1052 * ==================================
1051 1053 * MegaRAID SAS2.0 driver definitions
1052 1054 * ==================================
1053 1055 */
1054 1056 #define MRDRV_MAX_NUM_CMD 1024
1055 1057
1056 1058 #define MRDRV_MAX_PD_CHANNELS 2
1057 1059 #define MRDRV_MAX_LD_CHANNELS 2
1058 1060 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
1059 1061 MRDRV_MAX_LD_CHANNELS)
1060 1062 #define MRDRV_MAX_DEV_PER_CHANNEL 128
1061 1063 #define MRDRV_DEFAULT_INIT_ID -1
1062 1064 #define MRDRV_MAX_CMD_PER_LUN 1000
1063 1065 #define MRDRV_MAX_LUN 1
1064 1066 #define MRDRV_MAX_LD 64
1065 1067
1066 1068 #define MRDRV_RESET_WAIT_TIME 300
1067 1069 #define MRDRV_RESET_NOTICE_INTERVAL 5
1068 1070
1069 1071 #define MRSAS_IOCTL_CMD 0
1070 1072
1071 1073 #define MRDRV_TGT_VALID 1
1072 1074
1073 1075 /*
1074 1076 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1075 1077 * SGLs based on the size of dma_addr_t
1076 1078 */
1077 1079 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
1078 1080
1079 1081 #define RESERVED0_REGISTER 0x00 /* XScale */
1080 1082 #define IB_MSG_0_OFF 0x10 /* XScale */
1081 1083 #define OB_MSG_0_OFF 0x18 /* XScale */
1082 1084 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
1083 1085 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
1084 1086 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
1085 1087 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
1086 1088 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
1087 1089 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
1088 1090 #define OB_INTR_MASK 0xFFFFFFFF
1089 1091 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
1090 1092 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1091 1093 #define OB_SCRATCH_PAD_2_OFF 0xB4
1092 1094 #define WRITE_TBOLT_SEQ_OFF 0x00000004
1093 1095 #define DIAG_TBOLT_RESET_ADAPTER 0x00000004
1094 1096 #define HOST_TBOLT_DIAG_OFF 0x00000008
1095 1097 #define RESET_TBOLT_STATUS_OFF 0x000003C3
1096 1098 #define WRITE_SEQ_OFF 0x000000FC
1097 1099 #define HOST_DIAG_OFF 0x000000F8
1098 1100 #define DIAG_RESET_ADAPTER 0x00000004
1099 1101 #define DIAG_WRITE_ENABLE 0x00000080
1100 1102 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1101 1103
1102 1104 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
1103 1105 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
1104 1106
1105 1107 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
1106 1108 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
1107 1109
1108 1110 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
1109 1111 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
1110 1112
1111 1113 #define IB_LOW_QPORT 0xC0
1112 1114 #define IB_HIGH_QPORT 0xC4
1113 1115 #define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */
1114 1116
1115 1117 /*
1116 1118 * All MFI register set macros accept mrsas_register_set*
1117 1119 */
1118 1120 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
1119 1121 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
1120 1122
1121 1123 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
1122 1124 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
1123 1125
1124 1126 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
1125 1127 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
1126 1128
1127 1129 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
1128 1130 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
1129 1131
1130 1132 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
1131 1133 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
1132 1134
1133 1135 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
1134 1136 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
1135 1137
1136 1138 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
1137 1139 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
1138 1140
1139 1141 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
1140 1142 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
1141 1143
1142 1144 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1143 1145 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
1144 1146
1145 1147 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
1146 1148 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
1147 1149 (v))
1148 1150
1149 1151 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
1150 1152 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
1151 1153
1152 1154 /* Thunderbolt specific registers */
1153 1155 #define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \
1154 1156 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1155 1157
1156 1158 #define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1157 1159 ddi_put32((instance)->regmap_handle, \
1158 1160 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1159 1161
1160 1162 #define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \
1161 1163 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1162 1164
1163 1165 #define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \
1164 1166 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1165 1167
1166 1168 #define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \
1167 1169 (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1168 1170
1169 1171
1170 1172 #define WR_MPI2_REPLY_POST_INDEX(v, instance)\
1171 1173 ddi_put32((instance)->regmap_handle,\
1172 1174 (uint32_t *)\
1173 1175 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1174 1176 (v))
1175 1177
1176 1178
1177 1179 #define RD_MPI2_REPLY_POST_INDEX(instance)\
1178 1180 ddi_get32((instance)->regmap_handle,\
1179 1181 (uint32_t *)\
1180 1182 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1181 1183
1182 1184 #define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1183 1185 (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1184 1186
1185 1187 #define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1186 1188 (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1187 1189
1188 1190 #define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1189 1191 ddi_put32((instance)->regmap_handle,\
1190 1192 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1191 1193 (v))
1192 1194
1193 1195 #define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1194 1196 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1195 1197 (v))
1196 1198
1197 1199 #define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1198 1200 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1199 1201
1200 1202
1201 1203
1202 1204 /*
1203 1205 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
1204 1206 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
1205 1207 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
1206 1208 */
1207 1209 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1208 1210
1209 1211 /*
1210 1212 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
1211 1213 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
1212 1214 * been set in this flag along with bit 1.
1213 1215 */
1214 1216 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
1215 1217 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
1216 1218
1217 1219 /* Fusion interrupt mask */
1218 1220 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
1219 1221
1220 1222 #define MFI_POLL_TIMEOUT_SECS 60
1221 1223
1222 1224 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
1223 1225 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
1224 1226 #define MFI_DISABLE_INTR(instance) \
1225 1227 { \
1226 1228 uint32_t disable = 1; \
1227 1229 uint32_t mask = ddi_get32((instance)->regmap_handle, \
1228 1230 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
1229 1231 mask &= ~disable; \
1230 1232 ddi_put32((instance)->regmap_handle, (uint32_t *) \
1231 1233 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
1232 1234 }
1233 1235
1234 1236 /* By default, the firmware programs for 8 Kbytes of memory */
1235 1237 #define DEFAULT_MFI_MEM_SZ 8192
1236 1238 #define MINIMUM_MFI_MEM_SZ 4096
1237 1239
1238 1240 /* DCMD Message Frame MAILBOX0-11 */
1239 1241 #define DCMD_MBOX_SZ 12
1240 1242
1241 1243 /*
1242 1244 * on_off_property of mrsas_ctrl_prop
1243 1245 * bit0-9, 11-31 are reserved
1244 1246 */
1245 1247 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
1246 1248
1247 1249 struct mrsas_register_set {
1248 1250 uint32_t reserved_0[4]; /* 0000h */
1249 1251
1250 1252 uint32_t inbound_msg_0; /* 0010h */
1251 1253 uint32_t inbound_msg_1; /* 0014h */
1252 1254 uint32_t outbound_msg_0; /* 0018h */
1253 1255 uint32_t outbound_msg_1; /* 001Ch */
1254 1256
1255 1257 uint32_t inbound_doorbell; /* 0020h */
1256 1258 uint32_t inbound_intr_status; /* 0024h */
1257 1259 uint32_t inbound_intr_mask; /* 0028h */
1258 1260
1259 1261 uint32_t outbound_doorbell; /* 002Ch */
1260 1262 uint32_t outbound_intr_status; /* 0030h */
1261 1263 uint32_t outbound_intr_mask; /* 0034h */
1262 1264
1263 1265 uint32_t reserved_1[2]; /* 0038h */
1264 1266
1265 1267 uint32_t inbound_queue_port; /* 0040h */
1266 1268 uint32_t outbound_queue_port; /* 0044h */
1267 1269
1268 1270 uint32_t reserved_2[22]; /* 0048h */
1269 1271
1270 1272 uint32_t outbound_doorbell_clear; /* 00A0h */
1271 1273
1272 1274 uint32_t reserved_3[3]; /* 00A4h */
1273 1275
1274 1276 uint32_t outbound_scratch_pad; /* 00B0h */
1275 1277
1276 1278 uint32_t reserved_4[3]; /* 00B4h */
1277 1279
1278 1280 uint32_t inbound_low_queue_port; /* 00C0h */
1279 1281
1280 1282 uint32_t inbound_high_queue_port; /* 00C4h */
1281 1283
1282 1284 uint32_t reserved_5; /* 00C8h */
1283 1285 uint32_t index_registers[820]; /* 00CCh */
1284 1286 };
1285 1287
1286 1288 struct mrsas_sge32 {
1287 1289 uint32_t phys_addr;
1288 1290 uint32_t length;
1289 1291 };
1290 1292
1291 1293 struct mrsas_sge64 {
1292 1294 uint64_t phys_addr;
1293 1295 uint32_t length;
1294 1296 };
1295 1297
1296 1298 struct mrsas_sge_ieee {
1297 1299 uint64_t phys_addr;
1298 1300 uint32_t length;
1299 1301 uint32_t flag;
1300 1302 };
1301 1303
1302 1304 union mrsas_sgl {
1303 1305 struct mrsas_sge32 sge32[1];
1304 1306 struct mrsas_sge64 sge64[1];
1305 1307 struct mrsas_sge_ieee sge_ieee[1];
1306 1308 };
1307 1309
1308 1310 struct mrsas_header {
1309 1311 uint8_t cmd; /* 00h */
1310 1312 uint8_t sense_len; /* 01h */
1311 1313 uint8_t cmd_status; /* 02h */
1312 1314 uint8_t scsi_status; /* 03h */
1313 1315
1314 1316 uint8_t target_id; /* 04h */
1315 1317 uint8_t lun; /* 05h */
1316 1318 uint8_t cdb_len; /* 06h */
1317 1319 uint8_t sge_count; /* 07h */
1318 1320
1319 1321 uint32_t context; /* 08h */
1320 1322 uint8_t req_id; /* 0Ch */
1321 1323 uint8_t msgvector; /* 0Dh */
1322 1324 uint16_t pad_0; /* 0Eh */
1323 1325
1324 1326 uint16_t flags; /* 10h */
1325 1327 uint16_t timeout; /* 12h */
1326 1328 uint32_t data_xferlen; /* 14h */
1327 1329 };
1328 1330
1329 1331 union mrsas_sgl_frame {
1330 1332 struct mrsas_sge32 sge32[8];
1331 1333 struct mrsas_sge64 sge64[5];
1332 1334 };
1333 1335
1334 1336 struct mrsas_init_frame {
1335 1337 uint8_t cmd; /* 00h */
1336 1338 uint8_t reserved_0; /* 01h */
1337 1339 uint8_t cmd_status; /* 02h */
1338 1340
1339 1341 uint8_t reserved_1; /* 03h */
1340 1342 uint32_t reserved_2; /* 04h */
1341 1343
1342 1344 uint32_t context; /* 08h */
1343 1345 uint8_t req_id; /* 0Ch */
1344 1346 uint8_t msgvector; /* 0Dh */
1345 1347 uint16_t pad_0; /* 0Eh */
1346 1348
1347 1349 uint16_t flags; /* 10h */
1348 1350 uint16_t reserved_3; /* 12h */
1349 1351 uint32_t data_xfer_len; /* 14h */
1350 1352
1351 1353 uint32_t queue_info_new_phys_addr_lo; /* 18h */
1352 1354 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */
1353 1355 uint32_t queue_info_old_phys_addr_lo; /* 20h */
1354 1356 uint32_t queue_info_old_phys_addr_hi; /* 24h */
1355 1357 uint64_t driverversion; /* 28h */
1356 1358 uint32_t reserved_4[4]; /* 30h */
1357 1359 };
1358 1360
1359 1361 struct mrsas_init_queue_info {
1360 1362 uint32_t init_flags; /* 00h */
1361 1363 uint32_t reply_queue_entries; /* 04h */
1362 1364
1363 1365 uint32_t reply_queue_start_phys_addr_lo; /* 08h */
1364 1366 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */
1365 1367 uint32_t producer_index_phys_addr_lo; /* 10h */
1366 1368 uint32_t producer_index_phys_addr_hi; /* 14h */
1367 1369 uint32_t consumer_index_phys_addr_lo; /* 18h */
1368 1370 uint32_t consumer_index_phys_addr_hi; /* 1Ch */
1369 1371 };
1370 1372
1371 1373 struct mrsas_io_frame {
1372 1374 uint8_t cmd; /* 00h */
1373 1375 uint8_t sense_len; /* 01h */
1374 1376 uint8_t cmd_status; /* 02h */
1375 1377 uint8_t scsi_status; /* 03h */
1376 1378
1377 1379 uint8_t target_id; /* 04h */
1378 1380 uint8_t access_byte; /* 05h */
1379 1381 uint8_t reserved_0; /* 06h */
1380 1382 uint8_t sge_count; /* 07h */
1381 1383
1382 1384 uint32_t context; /* 08h */
1383 1385 uint8_t req_id; /* 0Ch */
1384 1386 uint8_t msgvector; /* 0Dh */
1385 1387 uint16_t pad_0; /* 0Eh */
1386 1388
1387 1389 uint16_t flags; /* 10h */
1388 1390 uint16_t timeout; /* 12h */
1389 1391 uint32_t lba_count; /* 14h */
1390 1392
1391 1393 uint32_t sense_buf_phys_addr_lo; /* 18h */
1392 1394 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1393 1395
1394 1396 uint32_t start_lba_lo; /* 20h */
1395 1397 uint32_t start_lba_hi; /* 24h */
1396 1398
1397 1399 union mrsas_sgl sgl; /* 28h */
1398 1400 };
1399 1401
1400 1402 struct mrsas_pthru_frame {
1401 1403 uint8_t cmd; /* 00h */
1402 1404 uint8_t sense_len; /* 01h */
1403 1405 uint8_t cmd_status; /* 02h */
1404 1406 uint8_t scsi_status; /* 03h */
1405 1407
1406 1408 uint8_t target_id; /* 04h */
1407 1409 uint8_t lun; /* 05h */
1408 1410 uint8_t cdb_len; /* 06h */
1409 1411 uint8_t sge_count; /* 07h */
1410 1412
1411 1413 uint32_t context; /* 08h */
1412 1414 uint8_t req_id; /* 0Ch */
1413 1415 uint8_t msgvector; /* 0Dh */
1414 1416 uint16_t pad_0; /* 0Eh */
1415 1417
1416 1418 uint16_t flags; /* 10h */
1417 1419 uint16_t timeout; /* 12h */
1418 1420 uint32_t data_xfer_len; /* 14h */
1419 1421
1420 1422 uint32_t sense_buf_phys_addr_lo; /* 18h */
1421 1423 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1422 1424
1423 1425 uint8_t cdb[16]; /* 20h */
1424 1426 union mrsas_sgl sgl; /* 30h */
1425 1427 };
1426 1428
1427 1429 struct mrsas_dcmd_frame {
1428 1430 uint8_t cmd; /* 00h */
1429 1431 uint8_t reserved_0; /* 01h */
1430 1432 uint8_t cmd_status; /* 02h */
1431 1433 uint8_t reserved_1[4]; /* 03h */
1432 1434 uint8_t sge_count; /* 07h */
1433 1435
1434 1436 uint32_t context; /* 08h */
1435 1437 uint8_t req_id; /* 0Ch */
1436 1438 uint8_t msgvector; /* 0Dh */
1437 1439 uint16_t pad_0; /* 0Eh */
1438 1440
1439 1441 uint16_t flags; /* 10h */
1440 1442 uint16_t timeout; /* 12h */
1441 1443
1442 1444 uint32_t data_xfer_len; /* 14h */
1443 1445 uint32_t opcode; /* 18h */
1444 1446
1445 1447 /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
1446 1448 union { /* 1Ch */
1447 1449 uint8_t b[DCMD_MBOX_SZ];
1448 1450 uint16_t s[6];
1449 1451 uint32_t w[3];
1450 1452 } mbox;
1451 1453
1452 1454 union mrsas_sgl sgl; /* 28h */
1453 1455 };
1454 1456
1455 1457 struct mrsas_abort_frame {
1456 1458 uint8_t cmd; /* 00h */
1457 1459 uint8_t reserved_0; /* 01h */
1458 1460 uint8_t cmd_status; /* 02h */
1459 1461
1460 1462 uint8_t reserved_1; /* 03h */
1461 1463 uint32_t reserved_2; /* 04h */
1462 1464
1463 1465 uint32_t context; /* 08h */
1464 1466 uint8_t req_id; /* 0Ch */
1465 1467 uint8_t msgvector; /* 0Dh */
1466 1468 uint16_t pad_0; /* 0Eh */
1467 1469
1468 1470 uint16_t flags; /* 10h */
1469 1471 uint16_t reserved_3; /* 12h */
1470 1472 uint32_t reserved_4; /* 14h */
1471 1473
1472 1474 uint32_t abort_context; /* 18h */
1473 1475 uint32_t pad_1; /* 1Ch */
1474 1476
1475 1477 uint32_t abort_mfi_phys_addr_lo; /* 20h */
1476 1478 uint32_t abort_mfi_phys_addr_hi; /* 24h */
1477 1479
1478 1480 uint32_t reserved_5[6]; /* 28h */
1479 1481 };
1480 1482
1481 1483 struct mrsas_smp_frame {
1482 1484 uint8_t cmd; /* 00h */
1483 1485 uint8_t reserved_1; /* 01h */
1484 1486 uint8_t cmd_status; /* 02h */
1485 1487 uint8_t connection_status; /* 03h */
1486 1488
1487 1489 uint8_t reserved_2[3]; /* 04h */
1488 1490 uint8_t sge_count; /* 07h */
1489 1491
1490 1492 uint32_t context; /* 08h */
1491 1493 uint8_t req_id; /* 0Ch */
1492 1494 uint8_t msgvector; /* 0Dh */
1493 1495 uint16_t pad_0; /* 0Eh */
1494 1496
1495 1497 uint16_t flags; /* 10h */
1496 1498 uint16_t timeout; /* 12h */
1497 1499
1498 1500 uint32_t data_xfer_len; /* 14h */
1499 1501
1500 1502 uint64_t sas_addr; /* 20h */
1501 1503
1502 1504 union mrsas_sgl sgl[2]; /* 28h */
1503 1505 };
1504 1506
1505 1507 struct mrsas_stp_frame {
1506 1508 uint8_t cmd; /* 00h */
1507 1509 uint8_t reserved_1; /* 01h */
1508 1510 uint8_t cmd_status; /* 02h */
1509 1511 uint8_t connection_status; /* 03h */
1510 1512
1511 1513 uint8_t target_id; /* 04h */
1512 1514 uint8_t reserved_2[2]; /* 04h */
1513 1515 uint8_t sge_count; /* 07h */
1514 1516
1515 1517 uint32_t context; /* 08h */
1516 1518 uint8_t req_id; /* 0Ch */
1517 1519 uint8_t msgvector; /* 0Dh */
1518 1520 uint16_t pad_0; /* 0Eh */
1519 1521
1520 1522 uint16_t flags; /* 10h */
1521 1523 uint16_t timeout; /* 12h */
1522 1524
1523 1525 uint32_t data_xfer_len; /* 14h */
1524 1526
1525 1527 uint16_t fis[10]; /* 28h */
1526 1528 uint32_t stp_flags; /* 3C */
1527 1529 union mrsas_sgl sgl; /* 40 */
1528 1530 };
1529 1531
1530 1532 union mrsas_frame {
1531 1533 struct mrsas_header hdr;
1532 1534 struct mrsas_init_frame init;
1533 1535 struct mrsas_io_frame io;
1534 1536 struct mrsas_pthru_frame pthru;
1535 1537 struct mrsas_dcmd_frame dcmd;
1536 1538 struct mrsas_abort_frame abort;
1537 1539 struct mrsas_smp_frame smp;
1538 1540 struct mrsas_stp_frame stp;
1539 1541
1540 1542 uint8_t raw_bytes[64];
1541 1543 };
1542 1544
1543 1545 typedef struct mrsas_pd_address {
1544 1546 uint16_t device_id;
1545 1547 uint16_t encl_id;
1546 1548
1547 1549 union {
1548 1550 struct {
1549 1551 uint8_t encl_index;
1550 1552 uint8_t slot_number;
1551 1553 } pd_address;
1552 1554 struct {
1553 1555 uint8_t encl_position;
1554 1556 uint8_t encl_connector_index;
1555 1557 } encl_address;
1556 1558 }address;
1557 1559
1558 1560 uint8_t scsi_dev_type;
1559 1561
1560 1562 union {
1561 1563 uint8_t port_bitmap;
1562 1564 uint8_t port_numbers;
1563 1565 } connected;
1564 1566
1565 1567 uint64_t sas_addr[2];
1566 1568 } mrsas_pd_address_t;
1567 1569
1568 1570 union mrsas_evt_class_locale {
1569 1571 struct {
1570 1572 uint16_t locale;
1571 1573 uint8_t reserved;
1572 1574 int8_t class;
1573 1575 } members;
1574 1576
1575 1577 uint32_t word;
1576 1578 };
1577 1579
1578 1580 struct mrsas_evt_log_info {
1579 1581 uint32_t newest_seq_num;
1580 1582 uint32_t oldest_seq_num;
1581 1583 uint32_t clear_seq_num;
1582 1584 uint32_t shutdown_seq_num;
1583 1585 uint32_t boot_seq_num;
1584 1586 };
1585 1587
1586 1588 struct mrsas_progress {
1587 1589 uint16_t progress;
1588 1590 uint16_t elapsed_seconds;
1589 1591 };
1590 1592
1591 1593 struct mrsas_evtarg_ld {
1592 1594 uint16_t target_id;
1593 1595 uint8_t ld_index;
1594 1596 uint8_t reserved;
1595 1597 };
1596 1598
1597 1599 struct mrsas_evtarg_pd {
1598 1600 uint16_t device_id;
1599 1601 uint8_t encl_index;
1600 1602 uint8_t slot_number;
1601 1603 };
1602 1604
1603 1605 struct mrsas_evt_detail {
1604 1606 uint32_t seq_num;
1605 1607 uint32_t time_stamp;
1606 1608 uint32_t code;
1607 1609 union mrsas_evt_class_locale cl;
1608 1610 uint8_t arg_type;
1609 1611 uint8_t reserved1[15];
1610 1612
1611 1613 union {
1612 1614 struct {
1613 1615 struct mrsas_evtarg_pd pd;
1614 1616 uint8_t cdb_length;
1615 1617 uint8_t sense_length;
1616 1618 uint8_t reserved[2];
1617 1619 uint8_t cdb[16];
1618 1620 uint8_t sense[64];
1619 1621 } cdbSense;
1620 1622
1621 1623 struct mrsas_evtarg_ld ld;
1622 1624
1623 1625 struct {
1624 1626 struct mrsas_evtarg_ld ld;
1625 1627 uint64_t count;
1626 1628 } ld_count;
1627 1629
1628 1630 struct {
1629 1631 uint64_t lba;
1630 1632 struct mrsas_evtarg_ld ld;
1631 1633 } ld_lba;
1632 1634
1633 1635 struct {
1634 1636 struct mrsas_evtarg_ld ld;
1635 1637 uint32_t prevOwner;
1636 1638 uint32_t newOwner;
1637 1639 } ld_owner;
1638 1640
1639 1641 struct {
1640 1642 uint64_t ld_lba;
1641 1643 uint64_t pd_lba;
1642 1644 struct mrsas_evtarg_ld ld;
1643 1645 struct mrsas_evtarg_pd pd;
1644 1646 } ld_lba_pd_lba;
1645 1647
1646 1648 struct {
1647 1649 struct mrsas_evtarg_ld ld;
1648 1650 struct mrsas_progress prog;
1649 1651 } ld_prog;
1650 1652
1651 1653 struct {
1652 1654 struct mrsas_evtarg_ld ld;
1653 1655 uint32_t prev_state;
1654 1656 uint32_t new_state;
1655 1657 } ld_state;
1656 1658
1657 1659 struct {
1658 1660 uint64_t strip;
1659 1661 struct mrsas_evtarg_ld ld;
1660 1662 } ld_strip;
1661 1663
1662 1664 struct mrsas_evtarg_pd pd;
1663 1665
1664 1666 struct {
1665 1667 struct mrsas_evtarg_pd pd;
1666 1668 uint32_t err;
1667 1669 } pd_err;
1668 1670
1669 1671 struct {
1670 1672 uint64_t lba;
1671 1673 struct mrsas_evtarg_pd pd;
1672 1674 } pd_lba;
1673 1675
1674 1676 struct {
1675 1677 uint64_t lba;
1676 1678 struct mrsas_evtarg_pd pd;
1677 1679 struct mrsas_evtarg_ld ld;
1678 1680 } pd_lba_ld;
1679 1681
1680 1682 struct {
1681 1683 struct mrsas_evtarg_pd pd;
1682 1684 struct mrsas_progress prog;
1683 1685 } pd_prog;
1684 1686
1685 1687 struct {
1686 1688 struct mrsas_evtarg_pd pd;
1687 1689 uint32_t prevState;
1688 1690 uint32_t newState;
1689 1691 } pd_state;
1690 1692
1691 1693 struct {
1692 1694 uint16_t vendorId;
1693 1695 uint16_t deviceId;
1694 1696 uint16_t subVendorId;
1695 1697 uint16_t subDeviceId;
1696 1698 } pci;
1697 1699
1698 1700 uint32_t rate;
1699 1701 char str[96];
1700 1702
1701 1703 struct {
1702 1704 uint32_t rtc;
1703 1705 uint32_t elapsedSeconds;
1704 1706 } time;
1705 1707
1706 1708 struct {
1707 1709 uint32_t ecar;
1708 1710 uint32_t elog;
1709 1711 char str[64];
1710 1712 } ecc;
1711 1713
1712 1714 mrsas_pd_address_t pd_addr;
1713 1715
1714 1716 uint8_t b[96];
1715 1717 uint16_t s[48];
1716 1718 uint32_t w[24];
1717 1719 uint64_t d[12];
1718 1720 } args;
1719 1721
1720 1722 char description[128];
1721 1723
1722 1724 };
1723 1725
1724 1726 /* only 63 are usable by the application */
1725 1727 #define MAX_LOGICAL_DRIVES 64
1726 1728 /* only 255 physical devices may be used */
1727 1729 #define MAX_PHYSICAL_DEVICES 256
1728 1730 #define MAX_PD_PER_ENCLOSURE 64
1729 1731 /* maximum disks per array */
1730 1732 #define MAX_ROW_SIZE 32
1731 1733 /* maximum spans per logical drive */
1732 1734 #define MAX_SPAN_DEPTH 8
1733 1735 /* maximum number of arrays a hot spare may be dedicated to */
1734 1736 #define MAX_ARRAYS_DEDICATED 16
1735 1737 /* maximum number of arrays which may exist */
1736 1738 #define MAX_ARRAYS 128
1737 1739 /* maximum number of foreign configs that may ha managed at once */
1738 1740 #define MAX_FOREIGN_CONFIGS 8
1739 1741 /* maximum spares (global and dedicated combined) */
1740 1742 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES
1741 1743 /* maximum possible Target IDs (i.e. 0 to 63) */
1742 1744 #define MAX_TARGET_ID 63
1743 1745 /* maximum number of supported enclosures */
1744 1746 #define MAX_ENCLOSURES 32
1745 1747 /* maximum number of PHYs per controller */
1746 1748 #define MAX_PHYS_PER_CONTROLLER 16
1747 1749 /* maximum number of LDs per array (due to DDF limitations) */
1748 1750 #define MAX_LDS_PER_ARRAY 16
1749 1751
1750 1752 /*
1751 1753 * -----------------------------------------------------------------------------
1752 1754 * -----------------------------------------------------------------------------
1753 1755 *
1754 1756 * Logical Drive commands
1755 1757 *
1756 1758 * -----------------------------------------------------------------------------
1757 1759 * -----------------------------------------------------------------------------
1758 1760 */
1759 1761 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */
1760 1762
1761 1763 /*
1762 1764 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
1763 1765 * dcmd.mbox - reserved
1764 1766 * dcmd.sge IN - ptr to returned MR_LD_LIST structure
1765 1767 * Desc: Return the logical drive list structure
1766 1768 * Status: No error
1767 1769 */
1768 1770
1769 1771 /*
1770 1772 * defines the logical drive reference structure
1771 1773 */
1772 1774 typedef union _MR_LD_REF { /* LD reference structure */
1773 1775 struct {
1774 1776 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */
1775 1777 uint8_t reserved; /* reserved for in line with MR_PD_REF */
1776 1778 uint16_t seqNum; /* Sequence Number */
1777 1779 } ld_ref;
1778 1780 uint32_t ref; /* shorthand reference to full 32-bits */
1779 1781 } MR_LD_REF; /* 4 bytes */
1780 1782
1781 1783 /*
1782 1784 * defines the logical drive list structure
1783 1785 */
1784 1786 typedef struct _MR_LD_LIST {
1785 1787 uint32_t ldCount; /* number of LDs */
1786 1788 uint32_t reserved; /* pad to 8-byte boundary */
1787 1789 struct {
1788 1790 MR_LD_REF ref; /* LD reference */
1789 1791 uint8_t state; /* current LD state (MR_LD_STATE) */
1790 1792 uint8_t reserved[3]; /* pad to 8-byte boundary */
1791 1793 uint64_t size; /* LD size */
1792 1794 } ldList[MAX_LOGICAL_DRIVES];
1793 1795 } MR_LD_LIST;
1794 1796
1795 1797 struct mrsas_drv_ver {
1796 1798 uint8_t signature[12];
1797 1799 uint8_t os_name[16];
1798 1800 uint8_t os_ver[12];
1799 1801 uint8_t drv_name[20];
1800 1802 uint8_t drv_ver[32];
1801 1803 uint8_t drv_rel_date[20];
1802 1804 };
1803 1805
1804 1806 #define PCI_TYPE0_ADDRESSES 6
1805 1807 #define PCI_TYPE1_ADDRESSES 2
1806 1808 #define PCI_TYPE2_ADDRESSES 5
1807 1809
1808 1810 struct mrsas_pci_common_header {
1809 1811 uint16_t vendorID; /* (ro) */
1810 1812 uint16_t deviceID; /* (ro) */
1811 1813 uint16_t command; /* Device control */
1812 1814 uint16_t status;
1813 1815 uint8_t revisionID; /* (ro) */
1814 1816 uint8_t progIf; /* (ro) */
1815 1817 uint8_t subClass; /* (ro) */
1816 1818 uint8_t baseClass; /* (ro) */
1817 1819 uint8_t cacheLineSize; /* (ro+) */
1818 1820 uint8_t latencyTimer; /* (ro+) */
1819 1821 uint8_t headerType; /* (ro) */
1820 1822 uint8_t bist; /* Built in self test */
1821 1823
1822 1824 union {
1823 1825 struct {
1824 1826 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES];
1825 1827 uint32_t cis;
1826 1828 uint16_t subVendorID;
1827 1829 uint16_t subSystemID;
1828 1830 uint32_t romBaseAddress;
1829 1831 uint8_t capabilitiesPtr;
1830 1832 uint8_t reserved1[3];
1831 1833 uint32_t reserved2;
1832 1834 uint8_t interruptLine;
1833 1835 uint8_t interruptPin; /* (ro) */
1834 1836 uint8_t minimumGrant; /* (ro) */
1835 1837 uint8_t maximumLatency; /* (ro) */
1836 1838 } type_0;
1837 1839
1838 1840 struct {
1839 1841 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES];
1840 1842 uint8_t primaryBus;
1841 1843 uint8_t secondaryBus;
1842 1844 uint8_t subordinateBus;
1843 1845 uint8_t secondaryLatency;
1844 1846 uint8_t ioBase;
1845 1847 uint8_t ioLimit;
1846 1848 uint16_t secondaryStatus;
1847 1849 uint16_t memoryBase;
1848 1850 uint16_t memoryLimit;
1849 1851 uint16_t prefetchBase;
1850 1852 uint16_t prefetchLimit;
1851 1853 uint32_t prefetchBaseUpper32;
1852 1854 uint32_t prefetchLimitUpper32;
1853 1855 uint16_t ioBaseUpper16;
1854 1856 uint16_t ioLimitUpper16;
1855 1857 uint8_t capabilitiesPtr;
1856 1858 uint8_t reserved1[3];
1857 1859 uint32_t romBaseAddress;
1858 1860 uint8_t interruptLine;
1859 1861 uint8_t interruptPin;
1860 1862 uint16_t bridgeControl;
1861 1863 } type_1;
1862 1864
1863 1865 struct {
1864 1866 uint32_t socketRegistersBaseAddress;
1865 1867 uint8_t capabilitiesPtr;
1866 1868 uint8_t reserved;
1867 1869 uint16_t secondaryStatus;
1868 1870 uint8_t primaryBus;
1869 1871 uint8_t secondaryBus;
1870 1872 uint8_t subordinateBus;
1871 1873 uint8_t secondaryLatency;
1872 1874 struct {
1873 1875 uint32_t base;
1874 1876 uint32_t limit;
1875 1877 } range[PCI_TYPE2_ADDRESSES-1];
1876 1878 uint8_t interruptLine;
1877 1879 uint8_t interruptPin;
1878 1880 uint16_t bridgeControl;
1879 1881 } type_2;
1880 1882 } header;
1881 1883 };
1882 1884
1883 1885 struct mrsas_pci_link_capability {
1884 1886 union {
1885 1887 struct {
1886 1888 uint32_t linkSpeed :4;
1887 1889 uint32_t linkWidth :6;
1888 1890 uint32_t aspmSupport :2;
1889 1891 uint32_t losExitLatency :3;
1890 1892 uint32_t l1ExitLatency :3;
1891 1893 uint32_t rsvdp :6;
1892 1894 uint32_t portNumber :8;
1893 1895 } bits;
1894 1896
1895 1897 uint32_t asUlong;
1896 1898 } cap;
1897 1899
1898 1900 };
1899 1901
1900 1902 struct mrsas_pci_link_status_capability {
1901 1903 union {
1902 1904 struct {
1903 1905 uint16_t linkSpeed :4;
1904 1906 uint16_t negotiatedLinkWidth :6;
1905 1907 uint16_t linkTrainingError :1;
1906 1908 uint16_t linkTraning :1;
1907 1909 uint16_t slotClockConfig :1;
1908 1910 uint16_t rsvdZ :3;
1909 1911 } bits;
1910 1912
1911 1913 uint16_t asUshort;
1912 1914 } stat_cap;
1913 1915
1914 1916 uint16_t reserved;
1915 1917
1916 1918 };
1917 1919
1918 1920 struct mrsas_pci_capabilities {
1919 1921 struct mrsas_pci_link_capability linkCapability;
1920 1922 struct mrsas_pci_link_status_capability linkStatusCapability;
1921 1923 };
1922 1924
1923 1925 struct mrsas_pci_information
1924 1926 {
1925 1927 uint32_t busNumber;
1926 1928 uint8_t deviceNumber;
1927 1929 uint8_t functionNumber;
1928 1930 uint8_t interruptVector;
1929 1931 uint8_t reserved;
1930 1932 struct mrsas_pci_common_header pciHeaderInfo;
1931 1933 struct mrsas_pci_capabilities capability;
1932 1934 uint8_t reserved2[32];
1933 1935 };
1934 1936
1935 1937 struct mrsas_ioctl {
1936 1938 uint16_t version;
1937 1939 uint16_t controller_id;
1938 1940 uint8_t signature[8];
1939 1941 uint32_t reserved_1;
1940 1942 uint32_t control_code;
1941 1943 uint32_t reserved_2[2];
1942 1944 uint8_t frame[64];
1943 1945 union mrsas_sgl_frame sgl_frame;
1944 1946 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1945 1947 uint8_t data[1];
1946 1948 };
1947 1949
1948 1950 struct mrsas_aen {
1949 1951 uint16_t host_no;
1950 1952 uint16_t cmd_status;
1951 1953 uint32_t seq_num;
1952 1954 uint32_t class_locale_word;
1953 1955 };
1954 1956
1955 1957 #pragma pack()
1956 1958
1957 1959 #ifndef DDI_VENDOR_LSI
1958 1960 #define DDI_VENDOR_LSI "LSI"
1959 1961 #endif /* DDI_VENDOR_LSI */
1960 1962
1961 1963 int mrsas_config_scsi_device(struct mrsas_instance *,
1962 1964 struct scsi_device *, dev_info_t **);
1963 1965
1964 1966 #ifdef PDSUPPORT
1965 1967 int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1966 1968 uint8_t, dev_info_t **);
1967 1969 #endif
1968 1970
1969 1971 dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t);
1970 1972 int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t);
1971 1973 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1972 1974 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
1973 1975 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1974 1976
1975 1977 int alloc_space_for_mpi2(struct mrsas_instance *);
1976 1978 void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1977 1979
1978 1980 int mrsas_issue_init_mpi2(struct mrsas_instance *);
1979 1981 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
1980 1982 struct scsi_pkt *, struct buf *, int, int, int, int,
1981 1983 int (*)(), caddr_t);
1982 1984 int mrsas_tbolt_tran_start(struct scsi_address *,
1983 1985 register struct scsi_pkt *);
1984 1986 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
1985 1987 void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
1986 1988 int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
1987 1989 struct mrsas_cmd *);
1988 1990 int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
1989 1991 struct mrsas_cmd *);
1990 1992 void tbolt_enable_intr(struct mrsas_instance *);
1991 1993 void tbolt_disable_intr(struct mrsas_instance *);
1992 1994 int tbolt_intr_ack(struct mrsas_instance *);
1993 1995 uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
1994 1996 uint_t tbolt_softintr();
1995 1997 int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
1996 1998 int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1997 1999 int mrsas_check_acc_handle(ddi_acc_handle_t handle);
1998 2000 int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
1999 2001 struct buf *, int, int (*)());
2000 2002 int mrsas_dma_move(struct mrsas_instance *,
2001 2003 struct scsi_pkt *, struct buf *);
2002 2004 int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
2003 2005 uchar_t);
2004 2006 void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2005 2007 int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2006 2008 void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2007 2009 struct mrsas_cmd *);
2008 2010 int alloc_req_rep_desc(struct mrsas_instance *);
2009 2011 int mrsas_mode_sense_build(struct scsi_pkt *);
2010 2012 void push_pending_mfi_pkt(struct mrsas_instance *,
2011 2013 struct mrsas_cmd *);
2012 2014 int mrsas_issue_pending_cmds(struct mrsas_instance *);
2013 2015 int mrsas_print_pending_cmds(struct mrsas_instance *);
2014 2016 int mrsas_complete_pending_cmds(struct mrsas_instance *);
2015 2017
2016 2018 int create_mfi_frame_pool(struct mrsas_instance *);
2017 2019 void destroy_mfi_frame_pool(struct mrsas_instance *);
2018 2020 int create_mfi_mpi_frame_pool(struct mrsas_instance *);
2019 2021 void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2020 2022 int create_mpi2_frame_pool(struct mrsas_instance *);
2021 2023 void destroy_mpi2_frame_pool(struct mrsas_instance *);
2022 2024 int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2023 2025 void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2024 2026 void free_req_desc_pool(struct mrsas_instance *);
2025 2027 void free_space_for_mpi2(struct mrsas_instance *);
2026 2028 void mrsas_dump_reply_desc(struct mrsas_instance *);
2027 2029 void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2028 2030 void display_scsi_inquiry(caddr_t);
2029 2031 void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2030 2032 int mrsas_mode_sense_build(struct scsi_pkt *);
2031 2033 int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2032 2034 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2033 2035 struct scsi_address *, struct scsi_pkt *, uchar_t *);
2034 2036 int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2035 2037 void mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2036 2038 int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2037 2039 void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],
2038 2040 struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32);
2039 2041
2040 2042
2041 2043 int mrsas_init_adapter_ppc(struct mrsas_instance *instance);
2042 2044 int mrsas_init_adapter_tbolt(struct mrsas_instance *instance);
2043 2045 int mrsas_init_adapter(struct mrsas_instance *instance);
2044 2046
2045 2047 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2046 2048 void mrsas_free_cmd_pool(struct mrsas_instance *instance);
2047 2049
2048 2050 void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int);
2049 2051 struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
2050 2052
2051 2053 int mfi_state_transition_to_ready(struct mrsas_instance *);
2052 2054
2053 2055 struct mrsas_cmd *mrsas_get_mfi_pkt(struct mrsas_instance *);
2054 2056 void mrsas_return_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
2055 2057
2056 2058
2057 2059 /* FMA functions. */
2058 2060 int mrsas_common_check(struct mrsas_instance *, struct mrsas_cmd *);
2059 2061 void mrsas_fm_ereport(struct mrsas_instance *, char *);
2060 2062
2061 2063
2062 2064 #ifdef __cplusplus
2063 2065 }
2064 2066 #endif
2065 2067
2066 2068 #endif /* _MR_SAS_H_ */
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