1 /*
2 * mr_sas.h: header for mr_sas
3 *
4 * Solaris MegaRAID driver for SAS2.0 controllers
5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 * All rights reserved.
7 *
8 * Version:
9 * Author:
10 * Swaminathan K S
11 * Arun Chandrashekhar
12 * Manju R
13 * Rasheed
14 * Shakeel Bukhari
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions are met:
18 *
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 *
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 *
26 * 3. Neither the name of the author nor the names of its contributors may be
27 * used to endorse or promote products derived from this software without
28 * specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 * DAMAGE.
42 */
43
44 /*
45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
47 * Copyright 2015 Garrett D'Amore <garrett@damore.org>
48 */
49
50 #ifndef _MR_SAS_H_
51 #define _MR_SAS_H_
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56
57 #include <sys/scsi/scsi.h>
58 #include "mr_sas_list.h"
59 #include "ld_pd_map.h"
60
61 /*
62 * MegaRAID SAS2.0 Driver meta data
63 */
64 #define MRSAS_VERSION "6.503.00.00ILLUMOS"
65 #define MRSAS_RELDATE "July 30, 2012"
66
67 #define MRSAS_TRUE 1
68 #define MRSAS_FALSE 0
69
70 #define ADAPTER_RESET_NOT_REQUIRED 0
71 #define ADAPTER_RESET_REQUIRED 1
72
73 #define PDSUPPORT 1
74
75 /*
76 * MegaRAID SAS2.0 device id conversion definitions.
77 */
78 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
79 #define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
80 int rem; \
81 rem = (len / boundary_len); \
82 if ((rem * boundary_len) != len) { \
83 new_len = len + ((rem + 1) * boundary_len - len); \
84 } else { \
85 new_len = len; \
86 } \
87 }
88
89
90 /*
91 * MegaRAID SAS2.0 supported controllers
92 */
93 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
94 #define PCI_DEVICE_ID_LSI_2108V 0x0079
95 #define PCI_DEVICE_ID_LSI_SKINNY 0x0071
96 #define PCI_DEVICE_ID_LSI_SKINNY_NEW 0x0073
97 #define PCI_DEVICE_ID_LSI_TBOLT 0x005b
98 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
99 #define PCI_DEVICE_ID_LSI_FURY 0x005f
100
101 /*
102 * Register Index for 2108 Controllers.
103 */
104 #define REGISTER_SET_IO_2108 (2)
105
106 #define MRSAS_MAX_SGE_CNT 0x50
107 #define MRSAS_APP_RESERVED_CMDS 32
108 #define MRSAS_APP_MIN_RESERVED_CMDS 4
109
110 #define MRSAS_IOCTL_DRIVER 0x12341234
111 #define MRSAS_IOCTL_FIRMWARE 0x12345678
112 #define MRSAS_IOCTL_AEN 0x87654321
113
114 #define MRSAS_1_SECOND 1000000
115
116 #ifdef PDSUPPORT
117
118 #define UNCONFIGURED_GOOD 0x0
119 #define PD_SYSTEM 0x40
120 #define MR_EVT_PD_STATE_CHANGE 0x0072
121 #define MR_EVT_PD_REMOVED_EXT 0x00f8
122 #define MR_EVT_PD_INSERTED_EXT 0x00f7
123 #define MR_DCMD_PD_GET_INFO 0x02020000
124 #define MRSAS_TBOLT_PD_LUN 1
125 #define MRSAS_TBOLT_PD_TGT_MAX 255
126 #define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
127
128 #endif
129
130 /* Raid Context Flags */
131 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
132 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
133 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
134 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
135 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
136 } MR_RAID_FLAGS_IO_SUB_TYPE;
137
138 /* Dynamic Enumeration Flags */
139 #define MRSAS_LD_LUN 0
140 #define WWN_STRLEN 17
141 #define LD_SYNC_BIT 1
142 #define LD_SYNC_SHIFT 14
143 /* ThunderBolt (TB) specific */
144 #define MRSAS_THUNDERBOLT_MSG_SIZE 256
145 #define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
146 #define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
147 #define MRSAS_THUNDERBOLT_REPLY_SIZE 8
148 #define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
149
150 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
151 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
152
153 #define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
154
155 #define MR_INTERNAL_MFI_FRAMES_SMID 1
156 #define MR_CTRL_EVENT_WAIT_SMID 2
157 #define MR_INTERNAL_DRIVER_RESET_SMID 3
158
159
160 /*
161 * =====================================
162 * MegaRAID SAS2.0 MFI firmware definitions
163 * =====================================
164 */
165 /*
166 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
167 * protocol between the software and firmware. Commands are issued using
168 * "message frames"
169 */
170
171 /*
172 * FW posts its state in upper 4 bits of outbound_msg_0 register
173 */
174 #define MFI_STATE_MASK 0xF0000000
175 #define MFI_STATE_UNDEFINED 0x00000000
176 #define MFI_STATE_BB_INIT 0x10000000
177 #define MFI_STATE_FW_INIT 0x40000000
178 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
179 #define MFI_STATE_FW_INIT_2 0x70000000
180 #define MFI_STATE_DEVICE_SCAN 0x80000000
181 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
182 #define MFI_STATE_FLUSH_CACHE 0xA0000000
183 #define MFI_STATE_READY 0xB0000000
184 #define MFI_STATE_OPERATIONAL 0xC0000000
185 #define MFI_STATE_FAULT 0xF0000000
186
187 #define MRMFI_FRAME_SIZE 64
188
189 /*
190 * During FW init, clear pending cmds & reset state using inbound_msg_0
191 *
192 * ABORT : Abort all pending cmds
193 * READY : Move from OPERATIONAL to READY state; discard queue info
194 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
195 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
196 */
197 #define MFI_INIT_ABORT 0x00000001
198 #define MFI_INIT_READY 0x00000002
199 #define MFI_INIT_MFIMODE 0x00000004
200 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
201 #define MFI_INIT_HOTPLUG 0x00000010
202 #define MFI_STOP_ADP 0x00000020
203 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
204
205 /*
206 * MFI frame flags
207 */
208 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
209 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
210 #define MFI_FRAME_SGL32 0x0000
211 #define MFI_FRAME_SGL64 0x0002
212 #define MFI_FRAME_SENSE32 0x0000
213 #define MFI_FRAME_SENSE64 0x0004
214 #define MFI_FRAME_DIR_NONE 0x0000
215 #define MFI_FRAME_DIR_WRITE 0x0008
216 #define MFI_FRAME_DIR_READ 0x0010
217 #define MFI_FRAME_DIR_BOTH 0x0018
218 #define MFI_FRAME_IEEE 0x0020
219
220 /*
221 * Definition for cmd_status
222 */
223 #define MFI_CMD_STATUS_POLL_MODE 0xFF
224 #define MFI_CMD_STATUS_SYNC_MODE 0xFF
225
226 /*
227 * MFI command opcodes
228 */
229 #define MFI_CMD_OP_INIT 0x00
230 #define MFI_CMD_OP_LD_READ 0x01
231 #define MFI_CMD_OP_LD_WRITE 0x02
232 #define MFI_CMD_OP_LD_SCSI 0x03
233 #define MFI_CMD_OP_PD_SCSI 0x04
234 #define MFI_CMD_OP_DCMD 0x05
235 #define MFI_CMD_OP_ABORT 0x06
236 #define MFI_CMD_OP_SMP 0x07
237 #define MFI_CMD_OP_STP 0x08
238
239 #define MR_DCMD_CTRL_GET_INFO 0x01010000
240
241 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
242 #define MR_FLUSH_CTRL_CACHE 0x01
243 #define MR_FLUSH_DISK_CACHE 0x02
244
245 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
246 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
247
248 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
249 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
250 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
251 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
252
253 /*
254 * Solaris Specific MAX values
255 */
256 #define MAX_SGL 24
257
258 /*
259 * MFI command completion codes
260 */
261 enum MFI_STAT {
262 MFI_STAT_OK = 0x00,
263 MFI_STAT_INVALID_CMD = 0x01,
264 MFI_STAT_INVALID_DCMD = 0x02,
265 MFI_STAT_INVALID_PARAMETER = 0x03,
266 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
267 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
268 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
269 MFI_STAT_APP_IN_USE = 0x07,
270 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
271 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
272 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
273 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
274 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
275 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
276 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
277 MFI_STAT_FLASH_BUSY = 0x0f,
278 MFI_STAT_FLASH_ERROR = 0x10,
279 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
280 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
281 MFI_STAT_FLASH_NOT_OPEN = 0x13,
282 MFI_STAT_FLASH_NOT_STARTED = 0x14,
283 MFI_STAT_FLUSH_FAILED = 0x15,
284 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
285 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
286 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
287 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
288 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
289 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
290 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
291 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
292 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
293 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
294 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
295 MFI_STAT_MFC_HW_ERROR = 0x21,
296 MFI_STAT_NO_HW_PRESENT = 0x22,
297 MFI_STAT_NOT_FOUND = 0x23,
298 MFI_STAT_NOT_IN_ENCL = 0x24,
299 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
300 MFI_STAT_PD_TYPE_WRONG = 0x26,
301 MFI_STAT_PR_DISABLED = 0x27,
302 MFI_STAT_ROW_INDEX_INVALID = 0x28,
303 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
304 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
305 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
306 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
307 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
308 MFI_STAT_SCSI_IO_FAILED = 0x2e,
309 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
310 MFI_STAT_SHUTDOWN_FAILED = 0x30,
311 MFI_STAT_TIME_NOT_SET = 0x31,
312 MFI_STAT_WRONG_STATE = 0x32,
313 MFI_STAT_LD_OFFLINE = 0x33,
314 MFI_STAT_INVALID_STATUS = 0xFF
315 };
316
317 enum MR_EVT_CLASS {
318 MR_EVT_CLASS_DEBUG = -2,
319 MR_EVT_CLASS_PROGRESS = -1,
320 MR_EVT_CLASS_INFO = 0,
321 MR_EVT_CLASS_WARNING = 1,
322 MR_EVT_CLASS_CRITICAL = 2,
323 MR_EVT_CLASS_FATAL = 3,
324 MR_EVT_CLASS_DEAD = 4
325 };
326
327 enum MR_EVT_LOCALE {
328 MR_EVT_LOCALE_LD = 0x0001,
329 MR_EVT_LOCALE_PD = 0x0002,
330 MR_EVT_LOCALE_ENCL = 0x0004,
331 MR_EVT_LOCALE_BBU = 0x0008,
332 MR_EVT_LOCALE_SAS = 0x0010,
333 MR_EVT_LOCALE_CTRL = 0x0020,
334 MR_EVT_LOCALE_CONFIG = 0x0040,
335 MR_EVT_LOCALE_CLUSTER = 0x0080,
336 MR_EVT_LOCALE_ALL = 0xffff
337 };
338
339 enum MR_EVT_ARGS {
340 MR_EVT_ARGS_NONE,
341 MR_EVT_ARGS_CDB_SENSE,
342 MR_EVT_ARGS_LD,
343 MR_EVT_ARGS_LD_COUNT,
344 MR_EVT_ARGS_LD_LBA,
345 MR_EVT_ARGS_LD_OWNER,
346 MR_EVT_ARGS_LD_LBA_PD_LBA,
347 MR_EVT_ARGS_LD_PROG,
348 MR_EVT_ARGS_LD_STATE,
349 MR_EVT_ARGS_LD_STRIP,
350 MR_EVT_ARGS_PD,
351 MR_EVT_ARGS_PD_ERR,
352 MR_EVT_ARGS_PD_LBA,
353 MR_EVT_ARGS_PD_LBA_LD,
354 MR_EVT_ARGS_PD_PROG,
355 MR_EVT_ARGS_PD_STATE,
356 MR_EVT_ARGS_PCI,
357 MR_EVT_ARGS_RATE,
358 MR_EVT_ARGS_STR,
359 MR_EVT_ARGS_TIME,
360 MR_EVT_ARGS_ECC
361 };
362
363 #define MR_EVT_CFG_CLEARED 0x0004
364 #define MR_EVT_LD_CREATED 0x008a
365 #define MR_EVT_LD_DELETED 0x008b
366 #define MR_EVT_CFG_FP_CHANGE 0x017B
367
368 enum LD_STATE {
369 LD_OFFLINE = 0,
370 LD_PARTIALLY_DEGRADED = 1,
371 LD_DEGRADED = 2,
372 LD_OPTIMAL = 3,
373 LD_INVALID = 0xFF
374 };
375
376 enum MRSAS_EVT {
377 MRSAS_EVT_CONFIG_TGT = 0,
378 MRSAS_EVT_UNCONFIG_TGT = 1,
379 MRSAS_EVT_UNCONFIG_SMP = 2
380 };
381
382 #define DMA_OBJ_ALLOCATED 1
383 #define DMA_OBJ_REALLOCATED 2
384 #define DMA_OBJ_FREED 3
385
386 /*
387 * dma_obj_t - Our DMA object
388 * @param buffer : kernel virtual address
389 * @param size : size of the data to be allocated
390 * @param acc_handle : access handle
391 * @param dma_handle : dma handle
392 * @param dma_cookie : scatter-gather list
393 * @param dma_attr : dma attributes for this buffer
394 *
395 * Our DMA object. The caller must initialize the size and dma attributes
396 * (dma_attr) fields before allocating the resources.
397 */
398 typedef struct {
399 caddr_t buffer;
400 uint32_t size;
401 ddi_acc_handle_t acc_handle;
402 ddi_dma_handle_t dma_handle;
403 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
404 ddi_dma_attr_t dma_attr;
405 uint8_t status;
406 uint8_t reserved[3];
407 } dma_obj_t;
408
409 struct mrsas_eventinfo {
410 struct mrsas_instance *instance;
411 int tgt;
412 int lun;
413 int event;
414 uint64_t wwn;
415 };
416
417 struct mrsas_ld {
418 dev_info_t *dip;
419 uint8_t lun_type;
420 uint8_t flag;
421 uint8_t reserved[2];
422 };
423
424
425 #ifdef PDSUPPORT
426 struct mrsas_tbolt_pd {
427 dev_info_t *dip;
428 uint8_t lun_type;
429 uint8_t dev_id;
430 uint8_t flag;
431 uint8_t reserved;
432 };
433 struct mrsas_tbolt_pd_info {
434 uint16_t deviceId;
435 uint16_t seqNum;
436 uint8_t inquiryData[96];
437 uint8_t vpdPage83[64];
438 uint8_t notSupported;
439 uint8_t scsiDevType;
440 uint8_t a;
441 uint8_t device_speed;
442 uint32_t mediaerrcnt;
443 uint32_t other;
444 uint32_t pred;
445 uint32_t lastpred;
446 uint16_t fwState;
447 uint8_t disabled;
448 uint8_t linkspwwd;
449 uint32_t ddfType;
450 struct {
451 uint8_t count;
452 uint8_t isPathBroken;
453 uint8_t connectorIndex[2];
454 uint8_t reserved[4];
455 uint64_t sasAddr[2];
456 uint8_t reserved2[16];
457 } pathInfo;
458 };
459 #endif
460
461 typedef struct mrsas_instance {
462 uint32_t *producer;
463 uint32_t *consumer;
464
465 uint32_t *reply_queue;
466 dma_obj_t mfi_internal_dma_obj;
467 uint16_t adapterresetinprogress;
468 uint16_t deadadapter;
469 /* ThunderBolt (TB) specific */
470 dma_obj_t mpi2_frame_pool_dma_obj;
471 dma_obj_t request_desc_dma_obj;
472 dma_obj_t reply_desc_dma_obj;
473 dma_obj_t ld_map_obj[2];
474
475 uint8_t init_id;
476 uint8_t flag_ieee;
477 uint8_t disable_online_ctrl_reset;
478 uint8_t fw_fault_count_after_ocr;
479
480 uint16_t max_num_sge;
481 uint16_t max_fw_cmds;
482 uint32_t max_sectors_per_req;
483
484 struct mrsas_cmd **cmd_list;
485
486 mlist_t cmd_pool_list;
487 kmutex_t cmd_pool_mtx;
488 kmutex_t sync_map_mtx;
489
490 mlist_t app_cmd_pool_list;
491 kmutex_t app_cmd_pool_mtx;
492 mlist_t cmd_app_pool_list;
493 kmutex_t cmd_app_pool_mtx;
494
495
496 mlist_t cmd_pend_list;
497 kmutex_t cmd_pend_mtx;
498
499 dma_obj_t mfi_evt_detail_obj;
500 struct mrsas_cmd *aen_cmd;
501
502 uint32_t aen_seq_num;
503 uint32_t aen_class_locale_word;
504
505 scsi_hba_tran_t *tran;
506
507 kcondvar_t int_cmd_cv;
508 kmutex_t int_cmd_mtx;
509
510 kcondvar_t aen_cmd_cv;
511 kmutex_t aen_cmd_mtx;
512
513 kcondvar_t abort_cmd_cv;
514 kmutex_t abort_cmd_mtx;
515
516 kmutex_t reg_write_mtx;
517 kmutex_t chip_mtx;
518
519 dev_info_t *dip;
520 ddi_acc_handle_t pci_handle;
521
522 timeout_id_t timeout_id;
523 uint32_t unique_id;
524 uint16_t fw_outstanding;
525 caddr_t regmap;
526 ddi_acc_handle_t regmap_handle;
527 uint8_t isr_level;
528 ddi_iblock_cookie_t iblock_cookie;
529 ddi_iblock_cookie_t soft_iblock_cookie;
530 ddi_softintr_t soft_intr_id;
531 uint8_t softint_running;
532 uint8_t tbolt_softint_running;
533 kmutex_t completed_pool_mtx;
534 mlist_t completed_pool_list;
535
536 caddr_t internal_buf;
537 uint32_t internal_buf_dmac_add;
538 uint32_t internal_buf_size;
539
540 uint16_t vendor_id;
541 uint16_t device_id;
542 uint16_t subsysvid;
543 uint16_t subsysid;
544 int instance;
545 int baseaddress;
546 char iocnode[16];
547
548 int fm_capabilities;
549 /*
550 * Driver resources unroll flags. The flag is set for resources that
551 * are needed to be free'd at detach() time.
552 */
553 struct _unroll {
554 uint8_t softs; /* The software state was allocated. */
555 uint8_t regs; /* Controller registers mapped. */
556 uint8_t intr; /* Interrupt handler added. */
557 uint8_t reqs; /* Request structs allocated. */
558 uint8_t mutexs; /* Mutex's allocated. */
559 uint8_t taskq; /* Task q's created. */
560 uint8_t tran; /* Tran struct allocated */
561 uint8_t tranSetup; /* Tran attached to the ddi. */
562 uint8_t devctl; /* Device nodes for cfgadm created. */
563 uint8_t scsictl; /* Device nodes for cfgadm created. */
564 uint8_t ioctl; /* Device nodes for ioctl's created. */
565 uint8_t timer; /* Timer started. */
566 uint8_t aenPend; /* AEN cmd pending f/w. */
567 uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */
568 uint8_t soft_isr; /* Soft interrupt handler allocated. */
569 uint8_t ldlist_buff; /* Logical disk list allocated. */
570 uint8_t pdlist_buff; /* Physical disk list allocated. */
571 uint8_t syncCmd; /* Sync map command allocated. */
572 uint8_t verBuff; /* 2108 MFI buffer allocated. */
573 uint8_t alloc_space_mfi; /* Allocated space for 2108 MFI. */
574 uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */
575 } unroll;
576
577
578 /* function template pointer */
579 struct mrsas_function_template *func_ptr;
580
581
582 /* MSI interrupts specific */
583 ddi_intr_handle_t *intr_htable; /* Interrupt handle array */
584 size_t intr_htable_size; /* Int. handle array size */
585 int intr_type;
586 int intr_cnt;
587 uint_t intr_pri;
588 int intr_cap;
589
590 ddi_taskq_t *taskq;
591 struct mrsas_ld *mr_ld_list;
592 kmutex_t config_dev_mtx;
593 /* ThunderBolt (TB) specific */
594 ddi_softintr_t tbolt_soft_intr_id;
595
596 #ifdef PDSUPPORT
597 uint32_t mr_tbolt_pd_max;
598 struct mrsas_tbolt_pd *mr_tbolt_pd_list;
599 #endif
600
601 uint8_t fast_path_io;
602
603 uint8_t skinny;
604 uint8_t tbolt;
605 uint16_t reply_read_index;
606 uint16_t reply_size; /* Single Reply struct size */
607 uint16_t raid_io_msg_size; /* Single message size */
608 uint32_t io_request_frames_phy;
609 uint8_t *io_request_frames;
610 /* Virtual address of request desc frame pool */
611 MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool;
612 /* Physical address of request desc frame pool */
613 uint32_t request_message_pool_phy;
614 /* Virtual address of reply Frame */
615 MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool;
616 /* Physical address of reply Frame */
617 uint32_t reply_frame_pool_phy;
618 uint8_t *reply_pool_limit; /* Last reply frame address */
619 /* Physical address of Last reply frame */
620 uint32_t reply_pool_limit_phy;
621 uint32_t reply_q_depth; /* Reply Queue Depth */
622 uint8_t max_sge_in_main_msg;
623 uint8_t max_sge_in_chain;
624 uint8_t chain_offset_io_req;
625 uint8_t chain_offset_mpt_msg;
626 MR_FW_RAID_MAP_ALL *ld_map[2];
627 uint32_t ld_map_phy[2];
628 uint32_t size_map_info;
629 uint64_t map_id;
630 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
631 struct mrsas_cmd *map_update_cmd;
632 uint32_t SyncRequired;
633 kmutex_t ocr_flags_mtx;
634 dma_obj_t drv_ver_dma_obj;
635 } mrsas_t;
636
637
638 /*
639 * Function templates for various controller specific functions
640 */
641 struct mrsas_function_template {
642 uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
643 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
644 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
645 struct mrsas_cmd *);
646 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
647 struct mrsas_cmd *);
648 void (*enable_intr)(struct mrsas_instance *);
649 void (*disable_intr)(struct mrsas_instance *);
650 int (*intr_ack)(struct mrsas_instance *);
651 int (*init_adapter)(struct mrsas_instance *);
652 /* int (*reset_adapter)(struct mrsas_instance *); */
653 };
654
655 /*
656 * ### Helper routines ###
657 */
658
659 /*
660 * con_log() - console log routine
661 * @param level : indicates the severity of the message.
662 * @fparam mt : format string
663 *
664 * con_log displays the error messages on the console based on the current
665 * debug level. Also it attaches the appropriate kernel severity level with
666 * the message.
667 *
668 *
669 * console messages debug levels
670 */
671 #define CL_NONE 0 /* No debug information */
672 #define CL_ANN 1 /* print unconditionally, announcements */
673 #define CL_ANN1 2 /* No-op */
674 #define CL_DLEVEL1 3 /* debug level 1, informative */
675 #define CL_DLEVEL2 4 /* debug level 2, verbose */
676 #define CL_DLEVEL3 5 /* debug level 3, very verbose */
677
678 #ifdef __SUNPRO_C
679 #define __func__ ""
680 #endif
681
682 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
683
684 /*
685 * ### SCSA definitions ###
686 */
687 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
688 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
689 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
690 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
691
692 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
693 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
694
695 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
696 #define CMD2PKT(sp) ((sp)->cmd_pkt)
697 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
698
699 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address)
700 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran)
701 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd)))
702
703 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */
704 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */
705 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */
706
707 /*
708 * ### Data structures for ioctl inteface and internal commands ###
709 */
710
711 /*
712 * Data direction flags
713 */
714 #define UIOC_RD 0x00001
715 #define UIOC_WR 0x00002
716
717 #define SCP2HOST(scp) (scp)->device->host /* to host */
718 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
719 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
720 #define SCP2TARGET(scp) (scp)->device->id /* to target */
721 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
722
723 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
724 #define SCP2ADAPTER(scp) \
725 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
726
727 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
728 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
729 #define MRDRV_IS_LOGICAL(ap) \
730 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
731 #define MAP_DEVICE_ID(instance, ap) \
732 (ap->a_target)
733
734 #define HIGH_LEVEL_INTR 1
735 #define NORMAL_LEVEL_INTR 0
736
737 #define IO_TIMEOUT_VAL 0
738 #define IO_RETRY_COUNT 3
739 #define MAX_FW_RESET_COUNT 3
740 /*
741 * scsa_cmd - Per-command mr private data
742 * @param cmd_dmahandle : dma handle
743 * @param cmd_dmacookies : current dma cookies
744 * @param cmd_pkt : scsi_pkt reference
745 * @param cmd_dmacount : dma count
746 * @param cmd_cookie : next cookie
747 * @param cmd_ncookies : cookies per window
748 * @param cmd_cookiecnt : cookies per sub-win
749 * @param cmd_nwin : number of dma windows
750 * @param cmd_curwin : current dma window
751 * @param cmd_dma_offset : current window offset
752 * @param cmd_dma_len : current window length
753 * @param cmd_flags : private flags
754 * @param cmd_cdblen : length of cdb
755 * @param cmd_scblen : length of scb
756 * @param cmd_buf : command buffer
757 * @param channel : channel for scsi sub-system
758 * @param target : target for scsi sub-system
759 * @param lun : LUN for scsi sub-system
760 *
761 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
762 * - Pointed to by pkt_ha_private field in scsi_pkt
763 */
764 struct scsa_cmd {
765 ddi_dma_handle_t cmd_dmahandle;
766 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT];
767 struct scsi_pkt *cmd_pkt;
768 ulong_t cmd_dmacount;
769 uint_t cmd_cookie;
770 uint_t cmd_ncookies;
771 uint_t cmd_cookiecnt;
772 uint_t cmd_nwin;
773 uint_t cmd_curwin;
774 off_t cmd_dma_offset;
775 ulong_t cmd_dma_len;
776 ulong_t cmd_flags;
777 uint_t cmd_cdblen;
778 uint_t cmd_scblen;
779 struct buf *cmd_buf;
780 ushort_t device_id;
781 uchar_t islogical;
782 uchar_t lun;
783 struct mrsas_device *mrsas_dev;
784 };
785
786
787 struct mrsas_cmd {
788 /*
789 * ThunderBolt(TB) We would be needing to have a placeholder
790 * for RAID_MSG_IO_REQUEST inside this structure. We are
791 * supposed to embed the mr_frame inside the RAID_MSG and post
792 * it down to the firmware.
793 */
794 union mrsas_frame *frame;
795 uint32_t frame_phys_addr;
796 uint8_t *sense;
797 uint8_t *sense1;
798 uint32_t sense_phys_addr;
799 uint32_t sense_phys_addr1;
800 dma_obj_t frame_dma_obj;
801 uint8_t frame_dma_obj_status;
802 uint32_t index;
803 uint8_t sync_cmd;
804 uint8_t cmd_status;
805 uint16_t abort_aen;
806 mlist_t list;
807 uint32_t frame_count;
808 struct scsa_cmd *cmd;
809 struct scsi_pkt *pkt;
810 Mpi2RaidSCSIIORequest_t *scsi_io_request;
811 Mpi2SGEIOUnion_t *sgl;
812 uint32_t sgl_phys_addr;
813 uint32_t scsi_io_request_phys_addr;
814 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
815 uint16_t SMID;
816 uint16_t retry_count_for_ocr;
817 uint16_t drv_pkt_time;
818 uint16_t load_balance_flag;
819
820 };
821
822 #define MAX_MGMT_ADAPTERS 1024
823 #define IOC_SIGNATURE "MR-SAS"
824
825 #define IOC_CMD_FIRMWARE 0x0
826 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
827 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
828 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
829 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
830
831
832 #define MRSAS_MAX_SENSE_LENGTH 32
833
834 struct mrsas_mgmt_info {
835
836 uint16_t count;
837 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
838 uint16_t map[MAX_MGMT_ADAPTERS];
839 int max_index;
840 };
841
842
843 #pragma pack(1)
844 /*
845 * SAS controller properties
846 */
847 struct mrsas_ctrl_prop {
848 uint16_t seq_num;
849 uint16_t pred_fail_poll_interval;
850 uint16_t intr_throttle_count;
851 uint16_t intr_throttle_timeouts;
852
853 uint8_t rebuild_rate;
854 uint8_t patrol_read_rate;
855 uint8_t bgi_rate;
856 uint8_t cc_rate;
857 uint8_t recon_rate;
858
859 uint8_t cache_flush_interval;
860
861 uint8_t spinup_drv_count;
862 uint8_t spinup_delay;
863
864 uint8_t cluster_enable;
865 uint8_t coercion_mode;
866 uint8_t alarm_enable;
867
868 uint8_t reserved_1[13];
869 uint32_t on_off_properties;
870 uint8_t reserved_4[28];
871 };
872
873
874 /*
875 * SAS controller information
876 */
877 struct mrsas_ctrl_info {
878 /* PCI device information */
879 struct {
880 uint16_t vendor_id;
881 uint16_t device_id;
882 uint16_t sub_vendor_id;
883 uint16_t sub_device_id;
884 uint8_t reserved[24];
885 } pci;
886
887 /* Host interface information */
888 struct {
889 uint8_t PCIX : 1;
890 uint8_t PCIE : 1;
891 uint8_t iSCSI : 1;
892 uint8_t SAS_3G : 1;
893 uint8_t reserved_0 : 4;
894 uint8_t reserved_1[6];
895 uint8_t port_count;
896 uint64_t port_addr[8];
897 } host_interface;
898
899 /* Device (backend) interface information */
900 struct {
901 uint8_t SPI : 1;
902 uint8_t SAS_3G : 1;
903 uint8_t SATA_1_5G : 1;
904 uint8_t SATA_3G : 1;
905 uint8_t reserved_0 : 4;
906 uint8_t reserved_1[6];
907 uint8_t port_count;
908 uint64_t port_addr[8];
909 } device_interface;
910
911 /* List of components residing in flash. All str are null terminated */
912 uint32_t image_check_word;
913 uint32_t image_component_count;
914
915 struct {
916 char name[8];
917 char version[32];
918 char build_date[16];
919 char built_time[16];
920 } image_component[8];
921
922 /*
923 * List of flash components that have been flashed on the card, but
924 * are not in use, pending reset of the adapter. This list will be
925 * empty if a flash operation has not occurred. All stings are null
926 * terminated
927 */
928 uint32_t pending_image_component_count;
929
930 struct {
931 char name[8];
932 char version[32];
933 char build_date[16];
934 char build_time[16];
935 } pending_image_component[8];
936
937 uint8_t max_arms;
938 uint8_t max_spans;
939 uint8_t max_arrays;
940 uint8_t max_lds;
941
942 char product_name[80];
943 char serial_no[32];
944
945 /*
946 * Other physical/controller/operation information. Indicates the
947 * presence of the hardware
948 */
949 struct {
950 uint32_t bbu : 1;
951 uint32_t alarm : 1;
952 uint32_t nvram : 1;
953 uint32_t uart : 1;
954 uint32_t reserved : 28;
955 } hw_present;
956
957 uint32_t current_fw_time;
958
959 /* Maximum data transfer sizes */
960 uint16_t max_concurrent_cmds;
961 uint16_t max_sge_count;
962 uint32_t max_request_size;
963
964 /* Logical and physical device counts */
965 uint16_t ld_present_count;
966 uint16_t ld_degraded_count;
967 uint16_t ld_offline_count;
968
969 uint16_t pd_present_count;
970 uint16_t pd_disk_present_count;
971 uint16_t pd_disk_pred_failure_count;
972 uint16_t pd_disk_failed_count;
973
974 /* Memory size information */
975 uint16_t nvram_size;
976 uint16_t memory_size;
977 uint16_t flash_size;
978
979 /* Error counters */
980 uint16_t mem_correctable_error_count;
981 uint16_t mem_uncorrectable_error_count;
982
983 /* Cluster information */
984 uint8_t cluster_permitted;
985 uint8_t cluster_active;
986 uint8_t reserved_1[2];
987
988 /* Controller capabilities structures */
989 struct {
990 uint32_t raid_level_0 : 1;
991 uint32_t raid_level_1 : 1;
992 uint32_t raid_level_5 : 1;
993 uint32_t raid_level_1E : 1;
994 uint32_t reserved : 28;
995 } raid_levels;
996
997 struct {
998 uint32_t rbld_rate : 1;
999 uint32_t cc_rate : 1;
1000 uint32_t bgi_rate : 1;
1001 uint32_t recon_rate : 1;
1002 uint32_t patrol_rate : 1;
1003 uint32_t alarm_control : 1;
1004 uint32_t cluster_supported : 1;
1005 uint32_t bbu : 1;
1006 uint32_t spanning_allowed : 1;
1007 uint32_t dedicated_hotspares : 1;
1008 uint32_t revertible_hotspares : 1;
1009 uint32_t foreign_config_import : 1;
1010 uint32_t self_diagnostic : 1;
1011 uint32_t reserved : 19;
1012 } adapter_operations;
1013
1014 struct {
1015 uint32_t read_policy : 1;
1016 uint32_t write_policy : 1;
1017 uint32_t io_policy : 1;
1018 uint32_t access_policy : 1;
1019 uint32_t reserved : 28;
1020 } ld_operations;
1021
1022 struct {
1023 uint8_t min;
1024 uint8_t max;
1025 uint8_t reserved[2];
1026 } stripe_size_operations;
1027
1028 struct {
1029 uint32_t force_online : 1;
1030 uint32_t force_offline : 1;
1031 uint32_t force_rebuild : 1;
1032 uint32_t reserved : 29;
1033 } pd_operations;
1034
1035 struct {
1036 uint32_t ctrl_supports_sas : 1;
1037 uint32_t ctrl_supports_sata : 1;
1038 uint32_t allow_mix_in_encl : 1;
1039 uint32_t allow_mix_in_ld : 1;
1040 uint32_t allow_sata_in_cluster : 1;
1041 uint32_t reserved : 27;
1042 } pd_mix_support;
1043
1044 /* Include the controller properties (changeable items) */
1045 uint8_t reserved_2[12];
1046 struct mrsas_ctrl_prop properties;
1047
1048 uint8_t pad[0x800 - 0x640];
1049 };
1050
1051 /*
1052 * ==================================
1053 * MegaRAID SAS2.0 driver definitions
1054 * ==================================
1055 */
1056 #define MRDRV_MAX_NUM_CMD 1024
1057
1058 #define MRDRV_MAX_PD_CHANNELS 2
1059 #define MRDRV_MAX_LD_CHANNELS 2
1060 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
1061 MRDRV_MAX_LD_CHANNELS)
1062 #define MRDRV_MAX_DEV_PER_CHANNEL 128
1063 #define MRDRV_DEFAULT_INIT_ID -1
1064 #define MRDRV_MAX_CMD_PER_LUN 1000
1065 #define MRDRV_MAX_LUN 1
1066 #define MRDRV_MAX_LD 64
1067
1068 #define MRDRV_RESET_WAIT_TIME 300
1069 #define MRDRV_RESET_NOTICE_INTERVAL 5
1070
1071 #define MRSAS_IOCTL_CMD 0
1072
1073 #define MRDRV_TGT_VALID 1
1074
1075 /*
1076 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1077 * SGLs based on the size of dma_addr_t
1078 */
1079 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
1080
1081 #define RESERVED0_REGISTER 0x00 /* XScale */
1082 #define IB_MSG_0_OFF 0x10 /* XScale */
1083 #define OB_MSG_0_OFF 0x18 /* XScale */
1084 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
1085 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
1086 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
1087 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
1088 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
1089 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
1090 #define OB_INTR_MASK 0xFFFFFFFF
1091 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
1092 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1093 #define OB_SCRATCH_PAD_2_OFF 0xB4
1094 #define WRITE_TBOLT_SEQ_OFF 0x00000004
1095 #define DIAG_TBOLT_RESET_ADAPTER 0x00000004
1096 #define HOST_TBOLT_DIAG_OFF 0x00000008
1097 #define RESET_TBOLT_STATUS_OFF 0x000003C3
1098 #define WRITE_SEQ_OFF 0x000000FC
1099 #define HOST_DIAG_OFF 0x000000F8
1100 #define DIAG_RESET_ADAPTER 0x00000004
1101 #define DIAG_WRITE_ENABLE 0x00000080
1102 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1103
1104 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
1105 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
1106
1107 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
1108 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
1109
1110 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
1111 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
1112
1113 #define IB_LOW_QPORT 0xC0
1114 #define IB_HIGH_QPORT 0xC4
1115 #define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */
1116
1117 /*
1118 * All MFI register set macros accept mrsas_register_set*
1119 */
1120 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
1121 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
1122
1123 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
1124 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
1125
1126 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
1127 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
1128
1129 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
1130 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
1131
1132 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
1133 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
1134
1135 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
1136 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
1137
1138 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
1139 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
1140
1141 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
1142 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
1143
1144 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1145 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
1146
1147 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
1148 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
1149 (v))
1150
1151 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
1152 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
1153
1154 /* Thunderbolt specific registers */
1155 #define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \
1156 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1157
1158 #define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1159 ddi_put32((instance)->regmap_handle, \
1160 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1161
1162 #define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \
1163 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1164
1165 #define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \
1166 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1167
1168 #define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \
1169 (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1170
1171
1172 #define WR_MPI2_REPLY_POST_INDEX(v, instance)\
1173 ddi_put32((instance)->regmap_handle,\
1174 (uint32_t *)\
1175 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1176 (v))
1177
1178
1179 #define RD_MPI2_REPLY_POST_INDEX(instance)\
1180 ddi_get32((instance)->regmap_handle,\
1181 (uint32_t *)\
1182 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1183
1184 #define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1185 (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1186
1187 #define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1188 (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1189
1190 #define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1191 ddi_put32((instance)->regmap_handle,\
1192 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1193 (v))
1194
1195 #define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1196 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1197 (v))
1198
1199 #define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1200 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1201
1202
1203
1204 /*
1205 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
1206 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
1207 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
1208 */
1209 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1210
1211 /*
1212 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
1213 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
1214 * been set in this flag along with bit 1.
1215 */
1216 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
1217 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
1218
1219 /* Fusion interrupt mask */
1220 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
1221
1222 #define MFI_POLL_TIMEOUT_SECS 60
1223
1224 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
1225 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
1226 #define MFI_DISABLE_INTR(instance) \
1227 { \
1228 uint32_t disable = 1; \
1229 uint32_t mask = ddi_get32((instance)->regmap_handle, \
1230 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
1231 mask &= ~disable; \
1232 ddi_put32((instance)->regmap_handle, (uint32_t *) \
1233 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
1234 }
1235
1236 /* By default, the firmware programs for 8 Kbytes of memory */
1237 #define DEFAULT_MFI_MEM_SZ 8192
1238 #define MINIMUM_MFI_MEM_SZ 4096
1239
1240 /* DCMD Message Frame MAILBOX0-11 */
1241 #define DCMD_MBOX_SZ 12
1242
1243 /*
1244 * on_off_property of mrsas_ctrl_prop
1245 * bit0-9, 11-31 are reserved
1246 */
1247 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
1248
1249 struct mrsas_register_set {
1250 uint32_t reserved_0[4]; /* 0000h */
1251
1252 uint32_t inbound_msg_0; /* 0010h */
1253 uint32_t inbound_msg_1; /* 0014h */
1254 uint32_t outbound_msg_0; /* 0018h */
1255 uint32_t outbound_msg_1; /* 001Ch */
1256
1257 uint32_t inbound_doorbell; /* 0020h */
1258 uint32_t inbound_intr_status; /* 0024h */
1259 uint32_t inbound_intr_mask; /* 0028h */
1260
1261 uint32_t outbound_doorbell; /* 002Ch */
1262 uint32_t outbound_intr_status; /* 0030h */
1263 uint32_t outbound_intr_mask; /* 0034h */
1264
1265 uint32_t reserved_1[2]; /* 0038h */
1266
1267 uint32_t inbound_queue_port; /* 0040h */
1268 uint32_t outbound_queue_port; /* 0044h */
1269
1270 uint32_t reserved_2[22]; /* 0048h */
1271
1272 uint32_t outbound_doorbell_clear; /* 00A0h */
1273
1274 uint32_t reserved_3[3]; /* 00A4h */
1275
1276 uint32_t outbound_scratch_pad; /* 00B0h */
1277
1278 uint32_t reserved_4[3]; /* 00B4h */
1279
1280 uint32_t inbound_low_queue_port; /* 00C0h */
1281
1282 uint32_t inbound_high_queue_port; /* 00C4h */
1283
1284 uint32_t reserved_5; /* 00C8h */
1285 uint32_t index_registers[820]; /* 00CCh */
1286 };
1287
1288 struct mrsas_sge32 {
1289 uint32_t phys_addr;
1290 uint32_t length;
1291 };
1292
1293 struct mrsas_sge64 {
1294 uint64_t phys_addr;
1295 uint32_t length;
1296 };
1297
1298 struct mrsas_sge_ieee {
1299 uint64_t phys_addr;
1300 uint32_t length;
1301 uint32_t flag;
1302 };
1303
1304 union mrsas_sgl {
1305 struct mrsas_sge32 sge32[1];
1306 struct mrsas_sge64 sge64[1];
1307 struct mrsas_sge_ieee sge_ieee[1];
1308 };
1309
1310 struct mrsas_header {
1311 uint8_t cmd; /* 00h */
1312 uint8_t sense_len; /* 01h */
1313 uint8_t cmd_status; /* 02h */
1314 uint8_t scsi_status; /* 03h */
1315
1316 uint8_t target_id; /* 04h */
1317 uint8_t lun; /* 05h */
1318 uint8_t cdb_len; /* 06h */
1319 uint8_t sge_count; /* 07h */
1320
1321 uint32_t context; /* 08h */
1322 uint8_t req_id; /* 0Ch */
1323 uint8_t msgvector; /* 0Dh */
1324 uint16_t pad_0; /* 0Eh */
1325
1326 uint16_t flags; /* 10h */
1327 uint16_t timeout; /* 12h */
1328 uint32_t data_xferlen; /* 14h */
1329 };
1330
1331 union mrsas_sgl_frame {
1332 struct mrsas_sge32 sge32[8];
1333 struct mrsas_sge64 sge64[5];
1334 };
1335
1336 struct mrsas_init_frame {
1337 uint8_t cmd; /* 00h */
1338 uint8_t reserved_0; /* 01h */
1339 uint8_t cmd_status; /* 02h */
1340
1341 uint8_t reserved_1; /* 03h */
1342 uint32_t reserved_2; /* 04h */
1343
1344 uint32_t context; /* 08h */
1345 uint8_t req_id; /* 0Ch */
1346 uint8_t msgvector; /* 0Dh */
1347 uint16_t pad_0; /* 0Eh */
1348
1349 uint16_t flags; /* 10h */
1350 uint16_t reserved_3; /* 12h */
1351 uint32_t data_xfer_len; /* 14h */
1352
1353 uint32_t queue_info_new_phys_addr_lo; /* 18h */
1354 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */
1355 uint32_t queue_info_old_phys_addr_lo; /* 20h */
1356 uint32_t queue_info_old_phys_addr_hi; /* 24h */
1357 uint64_t driverversion; /* 28h */
1358 uint32_t reserved_4[4]; /* 30h */
1359 };
1360
1361 struct mrsas_init_queue_info {
1362 uint32_t init_flags; /* 00h */
1363 uint32_t reply_queue_entries; /* 04h */
1364
1365 uint32_t reply_queue_start_phys_addr_lo; /* 08h */
1366 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */
1367 uint32_t producer_index_phys_addr_lo; /* 10h */
1368 uint32_t producer_index_phys_addr_hi; /* 14h */
1369 uint32_t consumer_index_phys_addr_lo; /* 18h */
1370 uint32_t consumer_index_phys_addr_hi; /* 1Ch */
1371 };
1372
1373 struct mrsas_io_frame {
1374 uint8_t cmd; /* 00h */
1375 uint8_t sense_len; /* 01h */
1376 uint8_t cmd_status; /* 02h */
1377 uint8_t scsi_status; /* 03h */
1378
1379 uint8_t target_id; /* 04h */
1380 uint8_t access_byte; /* 05h */
1381 uint8_t reserved_0; /* 06h */
1382 uint8_t sge_count; /* 07h */
1383
1384 uint32_t context; /* 08h */
1385 uint8_t req_id; /* 0Ch */
1386 uint8_t msgvector; /* 0Dh */
1387 uint16_t pad_0; /* 0Eh */
1388
1389 uint16_t flags; /* 10h */
1390 uint16_t timeout; /* 12h */
1391 uint32_t lba_count; /* 14h */
1392
1393 uint32_t sense_buf_phys_addr_lo; /* 18h */
1394 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1395
1396 uint32_t start_lba_lo; /* 20h */
1397 uint32_t start_lba_hi; /* 24h */
1398
1399 union mrsas_sgl sgl; /* 28h */
1400 };
1401
1402 struct mrsas_pthru_frame {
1403 uint8_t cmd; /* 00h */
1404 uint8_t sense_len; /* 01h */
1405 uint8_t cmd_status; /* 02h */
1406 uint8_t scsi_status; /* 03h */
1407
1408 uint8_t target_id; /* 04h */
1409 uint8_t lun; /* 05h */
1410 uint8_t cdb_len; /* 06h */
1411 uint8_t sge_count; /* 07h */
1412
1413 uint32_t context; /* 08h */
1414 uint8_t req_id; /* 0Ch */
1415 uint8_t msgvector; /* 0Dh */
1416 uint16_t pad_0; /* 0Eh */
1417
1418 uint16_t flags; /* 10h */
1419 uint16_t timeout; /* 12h */
1420 uint32_t data_xfer_len; /* 14h */
1421
1422 uint32_t sense_buf_phys_addr_lo; /* 18h */
1423 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1424
1425 uint8_t cdb[16]; /* 20h */
1426 union mrsas_sgl sgl; /* 30h */
1427 };
1428
1429 struct mrsas_dcmd_frame {
1430 uint8_t cmd; /* 00h */
1431 uint8_t reserved_0; /* 01h */
1432 uint8_t cmd_status; /* 02h */
1433 uint8_t reserved_1[4]; /* 03h */
1434 uint8_t sge_count; /* 07h */
1435
1436 uint32_t context; /* 08h */
1437 uint8_t req_id; /* 0Ch */
1438 uint8_t msgvector; /* 0Dh */
1439 uint16_t pad_0; /* 0Eh */
1440
1441 uint16_t flags; /* 10h */
1442 uint16_t timeout; /* 12h */
1443
1444 uint32_t data_xfer_len; /* 14h */
1445 uint32_t opcode; /* 18h */
1446
1447 /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
1448 union { /* 1Ch */
1449 uint8_t b[DCMD_MBOX_SZ];
1450 uint16_t s[6];
1451 uint32_t w[3];
1452 } mbox;
1453
1454 union mrsas_sgl sgl; /* 28h */
1455 };
1456
1457 struct mrsas_abort_frame {
1458 uint8_t cmd; /* 00h */
1459 uint8_t reserved_0; /* 01h */
1460 uint8_t cmd_status; /* 02h */
1461
1462 uint8_t reserved_1; /* 03h */
1463 uint32_t reserved_2; /* 04h */
1464
1465 uint32_t context; /* 08h */
1466 uint8_t req_id; /* 0Ch */
1467 uint8_t msgvector; /* 0Dh */
1468 uint16_t pad_0; /* 0Eh */
1469
1470 uint16_t flags; /* 10h */
1471 uint16_t reserved_3; /* 12h */
1472 uint32_t reserved_4; /* 14h */
1473
1474 uint32_t abort_context; /* 18h */
1475 uint32_t pad_1; /* 1Ch */
1476
1477 uint32_t abort_mfi_phys_addr_lo; /* 20h */
1478 uint32_t abort_mfi_phys_addr_hi; /* 24h */
1479
1480 uint32_t reserved_5[6]; /* 28h */
1481 };
1482
1483 struct mrsas_smp_frame {
1484 uint8_t cmd; /* 00h */
1485 uint8_t reserved_1; /* 01h */
1486 uint8_t cmd_status; /* 02h */
1487 uint8_t connection_status; /* 03h */
1488
1489 uint8_t reserved_2[3]; /* 04h */
1490 uint8_t sge_count; /* 07h */
1491
1492 uint32_t context; /* 08h */
1493 uint8_t req_id; /* 0Ch */
1494 uint8_t msgvector; /* 0Dh */
1495 uint16_t pad_0; /* 0Eh */
1496
1497 uint16_t flags; /* 10h */
1498 uint16_t timeout; /* 12h */
1499
1500 uint32_t data_xfer_len; /* 14h */
1501
1502 uint64_t sas_addr; /* 20h */
1503
1504 union mrsas_sgl sgl[2]; /* 28h */
1505 };
1506
1507 struct mrsas_stp_frame {
1508 uint8_t cmd; /* 00h */
1509 uint8_t reserved_1; /* 01h */
1510 uint8_t cmd_status; /* 02h */
1511 uint8_t connection_status; /* 03h */
1512
1513 uint8_t target_id; /* 04h */
1514 uint8_t reserved_2[2]; /* 04h */
1515 uint8_t sge_count; /* 07h */
1516
1517 uint32_t context; /* 08h */
1518 uint8_t req_id; /* 0Ch */
1519 uint8_t msgvector; /* 0Dh */
1520 uint16_t pad_0; /* 0Eh */
1521
1522 uint16_t flags; /* 10h */
1523 uint16_t timeout; /* 12h */
1524
1525 uint32_t data_xfer_len; /* 14h */
1526
1527 uint16_t fis[10]; /* 28h */
1528 uint32_t stp_flags; /* 3C */
1529 union mrsas_sgl sgl; /* 40 */
1530 };
1531
1532 union mrsas_frame {
1533 struct mrsas_header hdr;
1534 struct mrsas_init_frame init;
1535 struct mrsas_io_frame io;
1536 struct mrsas_pthru_frame pthru;
1537 struct mrsas_dcmd_frame dcmd;
1538 struct mrsas_abort_frame abort;
1539 struct mrsas_smp_frame smp;
1540 struct mrsas_stp_frame stp;
1541
1542 uint8_t raw_bytes[64];
1543 };
1544
1545 typedef struct mrsas_pd_address {
1546 uint16_t device_id;
1547 uint16_t encl_id;
1548
1549 union {
1550 struct {
1551 uint8_t encl_index;
1552 uint8_t slot_number;
1553 } pd_address;
1554 struct {
1555 uint8_t encl_position;
1556 uint8_t encl_connector_index;
1557 } encl_address;
1558 }address;
1559
1560 uint8_t scsi_dev_type;
1561
1562 union {
1563 uint8_t port_bitmap;
1564 uint8_t port_numbers;
1565 } connected;
1566
1567 uint64_t sas_addr[2];
1568 } mrsas_pd_address_t;
1569
1570 union mrsas_evt_class_locale {
1571 struct {
1572 uint16_t locale;
1573 uint8_t reserved;
1574 int8_t class;
1575 } members;
1576
1577 uint32_t word;
1578 };
1579
1580 struct mrsas_evt_log_info {
1581 uint32_t newest_seq_num;
1582 uint32_t oldest_seq_num;
1583 uint32_t clear_seq_num;
1584 uint32_t shutdown_seq_num;
1585 uint32_t boot_seq_num;
1586 };
1587
1588 struct mrsas_progress {
1589 uint16_t progress;
1590 uint16_t elapsed_seconds;
1591 };
1592
1593 struct mrsas_evtarg_ld {
1594 uint16_t target_id;
1595 uint8_t ld_index;
1596 uint8_t reserved;
1597 };
1598
1599 struct mrsas_evtarg_pd {
1600 uint16_t device_id;
1601 uint8_t encl_index;
1602 uint8_t slot_number;
1603 };
1604
1605 struct mrsas_evt_detail {
1606 uint32_t seq_num;
1607 uint32_t time_stamp;
1608 uint32_t code;
1609 union mrsas_evt_class_locale cl;
1610 uint8_t arg_type;
1611 uint8_t reserved1[15];
1612
1613 union {
1614 struct {
1615 struct mrsas_evtarg_pd pd;
1616 uint8_t cdb_length;
1617 uint8_t sense_length;
1618 uint8_t reserved[2];
1619 uint8_t cdb[16];
1620 uint8_t sense[64];
1621 } cdbSense;
1622
1623 struct mrsas_evtarg_ld ld;
1624
1625 struct {
1626 struct mrsas_evtarg_ld ld;
1627 uint64_t count;
1628 } ld_count;
1629
1630 struct {
1631 uint64_t lba;
1632 struct mrsas_evtarg_ld ld;
1633 } ld_lba;
1634
1635 struct {
1636 struct mrsas_evtarg_ld ld;
1637 uint32_t prevOwner;
1638 uint32_t newOwner;
1639 } ld_owner;
1640
1641 struct {
1642 uint64_t ld_lba;
1643 uint64_t pd_lba;
1644 struct mrsas_evtarg_ld ld;
1645 struct mrsas_evtarg_pd pd;
1646 } ld_lba_pd_lba;
1647
1648 struct {
1649 struct mrsas_evtarg_ld ld;
1650 struct mrsas_progress prog;
1651 } ld_prog;
1652
1653 struct {
1654 struct mrsas_evtarg_ld ld;
1655 uint32_t prev_state;
1656 uint32_t new_state;
1657 } ld_state;
1658
1659 struct {
1660 uint64_t strip;
1661 struct mrsas_evtarg_ld ld;
1662 } ld_strip;
1663
1664 struct mrsas_evtarg_pd pd;
1665
1666 struct {
1667 struct mrsas_evtarg_pd pd;
1668 uint32_t err;
1669 } pd_err;
1670
1671 struct {
1672 uint64_t lba;
1673 struct mrsas_evtarg_pd pd;
1674 } pd_lba;
1675
1676 struct {
1677 uint64_t lba;
1678 struct mrsas_evtarg_pd pd;
1679 struct mrsas_evtarg_ld ld;
1680 } pd_lba_ld;
1681
1682 struct {
1683 struct mrsas_evtarg_pd pd;
1684 struct mrsas_progress prog;
1685 } pd_prog;
1686
1687 struct {
1688 struct mrsas_evtarg_pd pd;
1689 uint32_t prevState;
1690 uint32_t newState;
1691 } pd_state;
1692
1693 struct {
1694 uint16_t vendorId;
1695 uint16_t deviceId;
1696 uint16_t subVendorId;
1697 uint16_t subDeviceId;
1698 } pci;
1699
1700 uint32_t rate;
1701 char str[96];
1702
1703 struct {
1704 uint32_t rtc;
1705 uint32_t elapsedSeconds;
1706 } time;
1707
1708 struct {
1709 uint32_t ecar;
1710 uint32_t elog;
1711 char str[64];
1712 } ecc;
1713
1714 mrsas_pd_address_t pd_addr;
1715
1716 uint8_t b[96];
1717 uint16_t s[48];
1718 uint32_t w[24];
1719 uint64_t d[12];
1720 } args;
1721
1722 char description[128];
1723
1724 };
1725
1726 /* only 63 are usable by the application */
1727 #define MAX_LOGICAL_DRIVES 64
1728 /* only 255 physical devices may be used */
1729 #define MAX_PHYSICAL_DEVICES 256
1730 #define MAX_PD_PER_ENCLOSURE 64
1731 /* maximum disks per array */
1732 #define MAX_ROW_SIZE 32
1733 /* maximum spans per logical drive */
1734 #define MAX_SPAN_DEPTH 8
1735 /* maximum number of arrays a hot spare may be dedicated to */
1736 #define MAX_ARRAYS_DEDICATED 16
1737 /* maximum number of arrays which may exist */
1738 #define MAX_ARRAYS 128
1739 /* maximum number of foreign configs that may ha managed at once */
1740 #define MAX_FOREIGN_CONFIGS 8
1741 /* maximum spares (global and dedicated combined) */
1742 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES
1743 /* maximum possible Target IDs (i.e. 0 to 63) */
1744 #define MAX_TARGET_ID 63
1745 /* maximum number of supported enclosures */
1746 #define MAX_ENCLOSURES 32
1747 /* maximum number of PHYs per controller */
1748 #define MAX_PHYS_PER_CONTROLLER 16
1749 /* maximum number of LDs per array (due to DDF limitations) */
1750 #define MAX_LDS_PER_ARRAY 16
1751
1752 /*
1753 * -----------------------------------------------------------------------------
1754 * -----------------------------------------------------------------------------
1755 *
1756 * Logical Drive commands
1757 *
1758 * -----------------------------------------------------------------------------
1759 * -----------------------------------------------------------------------------
1760 */
1761 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */
1762
1763 /*
1764 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
1765 * dcmd.mbox - reserved
1766 * dcmd.sge IN - ptr to returned MR_LD_LIST structure
1767 * Desc: Return the logical drive list structure
1768 * Status: No error
1769 */
1770
1771 /*
1772 * defines the logical drive reference structure
1773 */
1774 typedef union _MR_LD_REF { /* LD reference structure */
1775 struct {
1776 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */
1777 uint8_t reserved; /* reserved for in line with MR_PD_REF */
1778 uint16_t seqNum; /* Sequence Number */
1779 } ld_ref;
1780 uint32_t ref; /* shorthand reference to full 32-bits */
1781 } MR_LD_REF; /* 4 bytes */
1782
1783 /*
1784 * defines the logical drive list structure
1785 */
1786 typedef struct _MR_LD_LIST {
1787 uint32_t ldCount; /* number of LDs */
1788 uint32_t reserved; /* pad to 8-byte boundary */
1789 struct {
1790 MR_LD_REF ref; /* LD reference */
1791 uint8_t state; /* current LD state (MR_LD_STATE) */
1792 uint8_t reserved[3]; /* pad to 8-byte boundary */
1793 uint64_t size; /* LD size */
1794 } ldList[MAX_LOGICAL_DRIVES];
1795 } MR_LD_LIST;
1796
1797 struct mrsas_drv_ver {
1798 uint8_t signature[12];
1799 uint8_t os_name[16];
1800 uint8_t os_ver[12];
1801 uint8_t drv_name[20];
1802 uint8_t drv_ver[32];
1803 uint8_t drv_rel_date[20];
1804 };
1805
1806 #define PCI_TYPE0_ADDRESSES 6
1807 #define PCI_TYPE1_ADDRESSES 2
1808 #define PCI_TYPE2_ADDRESSES 5
1809
1810 struct mrsas_pci_common_header {
1811 uint16_t vendorID; /* (ro) */
1812 uint16_t deviceID; /* (ro) */
1813 uint16_t command; /* Device control */
1814 uint16_t status;
1815 uint8_t revisionID; /* (ro) */
1816 uint8_t progIf; /* (ro) */
1817 uint8_t subClass; /* (ro) */
1818 uint8_t baseClass; /* (ro) */
1819 uint8_t cacheLineSize; /* (ro+) */
1820 uint8_t latencyTimer; /* (ro+) */
1821 uint8_t headerType; /* (ro) */
1822 uint8_t bist; /* Built in self test */
1823
1824 union {
1825 struct {
1826 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES];
1827 uint32_t cis;
1828 uint16_t subVendorID;
1829 uint16_t subSystemID;
1830 uint32_t romBaseAddress;
1831 uint8_t capabilitiesPtr;
1832 uint8_t reserved1[3];
1833 uint32_t reserved2;
1834 uint8_t interruptLine;
1835 uint8_t interruptPin; /* (ro) */
1836 uint8_t minimumGrant; /* (ro) */
1837 uint8_t maximumLatency; /* (ro) */
1838 } type_0;
1839
1840 struct {
1841 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES];
1842 uint8_t primaryBus;
1843 uint8_t secondaryBus;
1844 uint8_t subordinateBus;
1845 uint8_t secondaryLatency;
1846 uint8_t ioBase;
1847 uint8_t ioLimit;
1848 uint16_t secondaryStatus;
1849 uint16_t memoryBase;
1850 uint16_t memoryLimit;
1851 uint16_t prefetchBase;
1852 uint16_t prefetchLimit;
1853 uint32_t prefetchBaseUpper32;
1854 uint32_t prefetchLimitUpper32;
1855 uint16_t ioBaseUpper16;
1856 uint16_t ioLimitUpper16;
1857 uint8_t capabilitiesPtr;
1858 uint8_t reserved1[3];
1859 uint32_t romBaseAddress;
1860 uint8_t interruptLine;
1861 uint8_t interruptPin;
1862 uint16_t bridgeControl;
1863 } type_1;
1864
1865 struct {
1866 uint32_t socketRegistersBaseAddress;
1867 uint8_t capabilitiesPtr;
1868 uint8_t reserved;
1869 uint16_t secondaryStatus;
1870 uint8_t primaryBus;
1871 uint8_t secondaryBus;
1872 uint8_t subordinateBus;
1873 uint8_t secondaryLatency;
1874 struct {
1875 uint32_t base;
1876 uint32_t limit;
1877 } range[PCI_TYPE2_ADDRESSES-1];
1878 uint8_t interruptLine;
1879 uint8_t interruptPin;
1880 uint16_t bridgeControl;
1881 } type_2;
1882 } header;
1883 };
1884
1885 struct mrsas_pci_link_capability {
1886 union {
1887 struct {
1888 uint32_t linkSpeed :4;
1889 uint32_t linkWidth :6;
1890 uint32_t aspmSupport :2;
1891 uint32_t losExitLatency :3;
1892 uint32_t l1ExitLatency :3;
1893 uint32_t rsvdp :6;
1894 uint32_t portNumber :8;
1895 } bits;
1896
1897 uint32_t asUlong;
1898 } cap;
1899
1900 };
1901
1902 struct mrsas_pci_link_status_capability {
1903 union {
1904 struct {
1905 uint16_t linkSpeed :4;
1906 uint16_t negotiatedLinkWidth :6;
1907 uint16_t linkTrainingError :1;
1908 uint16_t linkTraning :1;
1909 uint16_t slotClockConfig :1;
1910 uint16_t rsvdZ :3;
1911 } bits;
1912
1913 uint16_t asUshort;
1914 } stat_cap;
1915
1916 uint16_t reserved;
1917
1918 };
1919
1920 struct mrsas_pci_capabilities {
1921 struct mrsas_pci_link_capability linkCapability;
1922 struct mrsas_pci_link_status_capability linkStatusCapability;
1923 };
1924
1925 struct mrsas_pci_information
1926 {
1927 uint32_t busNumber;
1928 uint8_t deviceNumber;
1929 uint8_t functionNumber;
1930 uint8_t interruptVector;
1931 uint8_t reserved;
1932 struct mrsas_pci_common_header pciHeaderInfo;
1933 struct mrsas_pci_capabilities capability;
1934 uint8_t reserved2[32];
1935 };
1936
1937 struct mrsas_ioctl {
1938 uint16_t version;
1939 uint16_t controller_id;
1940 uint8_t signature[8];
1941 uint32_t reserved_1;
1942 uint32_t control_code;
1943 uint32_t reserved_2[2];
1944 uint8_t frame[64];
1945 union mrsas_sgl_frame sgl_frame;
1946 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1947 uint8_t data[1];
1948 };
1949
1950 struct mrsas_aen {
1951 uint16_t host_no;
1952 uint16_t cmd_status;
1953 uint32_t seq_num;
1954 uint32_t class_locale_word;
1955 };
1956
1957 #pragma pack()
1958
1959 #ifndef DDI_VENDOR_LSI
1960 #define DDI_VENDOR_LSI "LSI"
1961 #endif /* DDI_VENDOR_LSI */
1962
1963 int mrsas_config_scsi_device(struct mrsas_instance *,
1964 struct scsi_device *, dev_info_t **);
1965
1966 #ifdef PDSUPPORT
1967 int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1968 uint8_t, dev_info_t **);
1969 #endif
1970
1971 dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t);
1972 int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t);
1973 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1974 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
1975 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1976
1977 int alloc_space_for_mpi2(struct mrsas_instance *);
1978 void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1979
1980 int mrsas_issue_init_mpi2(struct mrsas_instance *);
1981 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
1982 struct scsi_pkt *, struct buf *, int, int, int, int,
1983 int (*)(), caddr_t);
1984 int mrsas_tbolt_tran_start(struct scsi_address *,
1985 register struct scsi_pkt *);
1986 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
1987 void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
1988 int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
1989 struct mrsas_cmd *);
1990 int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
1991 struct mrsas_cmd *);
1992 void tbolt_enable_intr(struct mrsas_instance *);
1993 void tbolt_disable_intr(struct mrsas_instance *);
1994 int tbolt_intr_ack(struct mrsas_instance *);
1995 uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
1996 uint_t tbolt_softintr();
1997 int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
1998 int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1999 int mrsas_check_acc_handle(ddi_acc_handle_t handle);
2000 int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
2001 struct buf *, int, int (*)());
2002 int mrsas_dma_move(struct mrsas_instance *,
2003 struct scsi_pkt *, struct buf *);
2004 int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
2005 uchar_t);
2006 void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2007 int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2008 void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2009 struct mrsas_cmd *);
2010 int alloc_req_rep_desc(struct mrsas_instance *);
2011 int mrsas_mode_sense_build(struct scsi_pkt *);
2012 void push_pending_mfi_pkt(struct mrsas_instance *,
2013 struct mrsas_cmd *);
2014 int mrsas_issue_pending_cmds(struct mrsas_instance *);
2015 int mrsas_print_pending_cmds(struct mrsas_instance *);
2016 int mrsas_complete_pending_cmds(struct mrsas_instance *);
2017
2018 int create_mfi_frame_pool(struct mrsas_instance *);
2019 void destroy_mfi_frame_pool(struct mrsas_instance *);
2020 int create_mfi_mpi_frame_pool(struct mrsas_instance *);
2021 void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2022 int create_mpi2_frame_pool(struct mrsas_instance *);
2023 void destroy_mpi2_frame_pool(struct mrsas_instance *);
2024 int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2025 void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2026 void free_req_desc_pool(struct mrsas_instance *);
2027 void free_space_for_mpi2(struct mrsas_instance *);
2028 void mrsas_dump_reply_desc(struct mrsas_instance *);
2029 void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2030 void display_scsi_inquiry(caddr_t);
2031 void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2032 int mrsas_mode_sense_build(struct scsi_pkt *);
2033 int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2034 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2035 struct scsi_address *, struct scsi_pkt *, uchar_t *);
2036 int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2037 void mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2038 int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2039 void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],
2040 struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32);
2041
2042
2043 int mrsas_init_adapter_ppc(struct mrsas_instance *instance);
2044 int mrsas_init_adapter_tbolt(struct mrsas_instance *instance);
2045 int mrsas_init_adapter(struct mrsas_instance *instance);
2046
2047 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2048 void mrsas_free_cmd_pool(struct mrsas_instance *instance);
2049
2050 void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int);
2051 struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
2052
2053 int mfi_state_transition_to_ready(struct mrsas_instance *);
2054
2055 struct mrsas_cmd *mrsas_get_mfi_pkt(struct mrsas_instance *);
2056 void mrsas_return_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
2057
2058
2059 /* FMA functions. */
2060 int mrsas_common_check(struct mrsas_instance *, struct mrsas_cmd *);
2061 void mrsas_fm_ereport(struct mrsas_instance *, char *);
2062
2063
2064 #ifdef __cplusplus
2065 }
2066 #endif
2067
2068 #endif /* _MR_SAS_H_ */