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4630 clean stale references to ddi_iopb_alloc and ddi_iopb_free
4634 undocument scsi_hba_attach() and ddi_dma_lim(9s)
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--- old/usr/src/uts/common/io/pcic.c
+++ new/usr/src/uts/common/io/pcic.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 /*
28 28 * PCIC device/interrupt handler
29 29 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic
30 30 * and Toshiba (and possibly other clones) PCMCIA adapter chip
31 31 * sets. It implements a subset of Socket Services as defined
32 32 * in the Solaris PCMCIA design documents
33 33 */
34 34
35 35 /*
36 36 * currently defined "properties"
37 37 *
38 38 * clock-frequency bus clock frequency
39 39 * smi system management interrupt override
40 40 * need-mult-irq need status IRQ for each pair of sockets
41 41 * disable-audio don't route audio signal to speaker
42 42 */
43 43
44 44
45 45 #include <sys/types.h>
46 46 #include <sys/inttypes.h>
47 47 #include <sys/param.h>
48 48 #include <sys/systm.h>
49 49 #include <sys/user.h>
50 50 #include <sys/buf.h>
51 51 #include <sys/file.h>
52 52 #include <sys/uio.h>
53 53 #include <sys/conf.h>
54 54 #include <sys/stat.h>
55 55 #include <sys/autoconf.h>
56 56 #include <sys/vtoc.h>
57 57 #include <sys/dkio.h>
58 58 #include <sys/ddi.h>
59 59 #include <sys/sunddi.h>
60 60 #include <sys/sunndi.h>
61 61 #include <sys/var.h>
62 62 #include <sys/callb.h>
63 63 #include <sys/open.h>
64 64 #include <sys/ddidmareq.h>
65 65 #include <sys/dma_engine.h>
66 66 #include <sys/kstat.h>
67 67 #include <sys/kmem.h>
68 68 #include <sys/modctl.h>
69 69 #include <sys/pci.h>
70 70 #include <sys/pci_impl.h>
71 71
72 72 #include <sys/pctypes.h>
73 73 #include <sys/pcmcia.h>
74 74 #include <sys/sservice.h>
75 75
76 76 #include <sys/note.h>
77 77
78 78 #include <sys/pcic_reg.h>
79 79 #include <sys/pcic_var.h>
80 80
81 81 #if defined(__i386) || defined(__amd64)
82 82 #include <sys/pci_cfgspace.h>
83 83 #endif
84 84
85 85 #if defined(__sparc)
86 86 #include <sys/pci/pci_nexus.h>
87 87 #endif
88 88
89 89 #include <sys/hotplug/hpcsvc.h>
90 90 #include "cardbus/cardbus.h"
91 91
92 92 #define SOFTC_SIZE (sizeof (anp_t))
93 93
94 94 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
95 95 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t);
96 96 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t);
97 97 static int32_t pcic_quiesce(dev_info_t *);
98 98 static uint_t pcic_intr(caddr_t, caddr_t);
99 99 static int pcic_do_io_intr(pcicdev_t *, uint32_t);
100 100 static int pcic_probe(dev_info_t *);
101 101
102 102 static int pcic_open(dev_t *, int, int, cred_t *);
103 103 static int pcic_close(dev_t, int, int, cred_t *);
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103 lines elided |
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104 104 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
105 105
106 106 typedef struct pcm_regs pcm_regs_t;
107 107
108 108 static void pcic_init_assigned(dev_info_t *);
109 109 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *,
110 110 pci_regspec_t *, int);
111 111 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int);
112 112
113 113 /*
114 - * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls
115 - * are xlated into DMA ctlops. To make this nexus work on x86, we
116 - * need to have the default ddi_dma_mctl ctlops in the bus_ops
117 - * structure, just to pass the request to the parent. The correct
114 + * To make this nexus work on x86, we need to have the default ddi_dma_mctl
115 + * ctlops in the bus_ops structure, just to pass the request to the parent.
118 116 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA.
119 117 */
120 118 static
121 119 struct bus_ops pcmciabus_ops = {
122 120 BUSO_REV,
123 121 pcmcia_bus_map,
124 122 NULL,
125 123 NULL,
126 124 NULL,
127 125 i_ddi_map_fault,
128 126 ddi_no_dma_map,
129 127 ddi_no_dma_allochdl,
130 128 ddi_no_dma_freehdl,
131 129 ddi_no_dma_bindhdl,
132 130 ddi_no_dma_unbindhdl,
133 131 ddi_no_dma_flush,
134 132 ddi_no_dma_win,
135 133 ddi_dma_mctl,
136 134 pcmcia_ctlops,
137 135 pcmcia_prop_op,
138 136 NULL, /* (*bus_get_eventcookie)(); */
139 137 NULL, /* (*bus_add_eventcall)(); */
140 138 NULL, /* (*bus_remove_eventcall)(); */
141 139 NULL, /* (*bus_post_event)(); */
142 140 NULL, /* (*bus_intr_ctl)(); */
143 141 NULL, /* (*bus_config)(); */
144 142 NULL, /* (*bus_unconfig)(); */
145 143 NULL, /* (*bus_fm_init)(); */
146 144 NULL, /* (*bus_fm_fini)(); */
147 145 NULL, /* (*bus_enter)() */
148 146 NULL, /* (*bus_exit)() */
149 147 NULL, /* (*bus_power)() */
150 148 pcmcia_intr_ops /* (*bus_intr_op)(); */
151 149 };
152 150
153 151 static struct cb_ops pcic_cbops = {
154 152 pcic_open,
155 153 pcic_close,
156 154 nodev,
157 155 nodev,
158 156 nodev,
159 157 nodev,
160 158 nodev,
161 159 pcic_ioctl,
162 160 nodev,
163 161 nodev,
164 162 nodev,
165 163 nochpoll,
166 164 ddi_prop_op,
167 165 NULL,
168 166 #ifdef CARDBUS
169 167 D_NEW | D_MP | D_HOTPLUG
170 168 #else
171 169 D_NEW | D_MP
172 170 #endif
173 171 };
174 172
175 173 static struct dev_ops pcic_devops = {
176 174 DEVO_REV,
177 175 0,
178 176 pcic_getinfo,
179 177 nulldev,
180 178 pcic_probe,
181 179 pcic_attach,
182 180 pcic_detach,
183 181 nulldev,
184 182 &pcic_cbops,
185 183 &pcmciabus_ops,
186 184 NULL,
187 185 pcic_quiesce, /* devo_quiesce */
188 186 };
189 187
190 188 void *pcic_soft_state_p = NULL;
191 189 static int pcic_maxinst = -1;
192 190
193 191 int pcic_do_insertion = 1;
194 192 int pcic_do_removal = 1;
195 193
196 194 struct irqmap {
197 195 int irq;
198 196 int count;
199 197 } pcic_irq_map[16];
200 198
201 199
202 200 int pcic_debug = 0x0;
203 201 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...);
204 202 extern void cardbus_dump_pci_config(dev_info_t *dip);
205 203 extern void cardbus_dump_socket(dev_info_t *dip);
206 204 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle);
207 205 static void pcic_dump_debqueue(char *msg);
208 206
209 207 #if defined(PCIC_DEBUG)
210 208 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t);
211 209
212 210 #define pcic_mutex_enter(a) \
213 211 { \
214 212 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \
215 213 mutex_enter(a); \
216 214 };
217 215
218 216 #define pcic_mutex_exit(a) \
219 217 { \
220 218 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \
221 219 mutex_exit(a); \
222 220 };
223 221
224 222 #else
225 223 #define pcic_mutex_enter(a) mutex_enter(a)
226 224 #define pcic_mutex_exit(a) mutex_exit(a)
227 225 #endif
228 226
229 227 #define PCIC_VCC_3VLEVEL 1
230 228 #define PCIC_VCC_5VLEVEL 2
231 229 #define PCIC_VCC_12LEVEL 3
232 230
233 231 /* bit patterns to select voltage levels */
234 232 int pcic_vpp_levels[13] = {
235 233 0, 0, 0,
236 234 1, /* 3.3V */
237 235 0,
238 236 1, /* 5V */
239 237 0, 0, 0, 0, 0, 0,
240 238 2 /* 12V */
241 239 };
242 240
243 241 uint8_t pcic_cbv_levels[13] = {
244 242 0, 0, 0,
245 243 3, /* 3.3V */
246 244 0,
247 245 2, /* 5V */
248 246 0, 0, 0, 0, 0, 0,
249 247 1 /* 12V */
250 248 };
251 249
252 250 struct power_entry pcic_power[4] = {
253 251 {
254 252 0, VCC|VPP1|VPP2
255 253 },
256 254 {
257 255 33, /* 3.3Volt */
258 256 VCC|VPP1|VPP2
259 257 },
260 258 {
261 259 5*10, /* 5Volt */
262 260 VCC|VPP1|VPP2 /* currently only know about this */
263 261 },
264 262 {
265 263 12*10, /* 12Volt */
266 264 VPP1|VPP2
267 265 }
268 266 };
269 267
270 268 /*
271 269 * Base used to allocate ranges of PCI memory on x86 systems
272 270 * Each instance gets a chunk above the base that is used to map
273 271 * in the memory and I/O windows for that device.
274 272 * Pages below the base are also allocated for the EXCA registers,
275 273 * one per instance.
276 274 */
277 275 #define PCIC_PCI_MEMCHUNK 0x1000000
278 276
279 277 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */
280 278 static int pcic_debounce_time = 200000; /* In micro-seconds */
281 279
282 280 struct debounce {
283 281 pcic_socket_t *pcs;
284 282 clock_t expire;
285 283 struct debounce *next;
286 284 };
287 285
288 286 static struct debounce *pcic_deb_queue = NULL;
289 287 static kmutex_t pcic_deb_mtx;
290 288 static kcondvar_t pcic_deb_cv;
291 289 static kthread_t *pcic_deb_threadid;
292 290
293 291 static inthandler_t *pcic_handlers;
294 292
295 293 static void pcic_setup_adapter(pcicdev_t *);
296 294 static int pcic_change(pcicdev_t *, int);
297 295 static int pcic_ll_reset(pcicdev_t *, int);
298 296 static void pcic_mswait(pcicdev_t *, int, int);
299 297 static boolean_t pcic_check_ready(pcicdev_t *, int);
300 298 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int);
301 299 static void pcic_ready_wait(pcicdev_t *, int);
302 300 extern int pcmcia_get_intr(dev_info_t *, int);
303 301 extern int pcmcia_return_intr(dev_info_t *, int);
304 302 extern void pcmcia_cb_suspended(int);
305 303 extern void pcmcia_cb_resumed(int);
306 304
307 305 static int pcic_callback(dev_info_t *, int (*)(), int);
308 306 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *);
309 307 static int pcic_get_adapter(dev_info_t *, get_adapter_t *);
310 308 static int pcic_get_page(dev_info_t *, get_page_t *);
311 309 static int pcic_get_socket(dev_info_t *, get_socket_t *);
312 310 static int pcic_get_status(dev_info_t *, get_ss_status_t *);
313 311 static int pcic_get_window(dev_info_t *, get_window_t *);
314 312 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *);
315 313 static int pcic_inquire_window(dev_info_t *, inquire_window_t *);
316 314 static int pcic_reset_socket(dev_info_t *, int, int);
317 315 static int pcic_set_page(dev_info_t *, set_page_t *);
318 316 static int pcic_set_window(dev_info_t *, set_window_t *);
319 317 static int pcic_set_socket(dev_info_t *, set_socket_t *);
320 318 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *);
321 319 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *);
322 320 static void pcic_pm_detection(void *);
323 321 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned);
324 322 static int clext_reg_read(pcicdev_t *, int, uchar_t);
325 323 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t);
326 324 static int pcic_calc_speed(pcicdev_t *, uint32_t);
327 325 static int pcic_card_state(pcicdev_t *, pcic_socket_t *);
328 326 static int pcic_find_pci_type(pcicdev_t *);
329 327 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int);
330 328 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t);
331 329 static uint_t pcic_cd_softint(caddr_t, caddr_t);
332 330 static uint8_t pcic_getb(pcicdev_t *, int, int);
333 331 static void pcic_putb(pcicdev_t *, int, int, int8_t);
334 332 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *);
335 333 static uint_t pcic_softintr(caddr_t, caddr_t);
336 334
337 335 static void pcic_debounce(pcic_socket_t *);
338 336 static void pcic_do_resume(pcicdev_t *);
339 337 static void *pcic_add_debqueue(pcic_socket_t *, int);
340 338 static void pcic_rm_debqueue(void *);
341 339 static void pcic_deb_thread();
342 340
343 341 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp);
344 342 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp);
345 343 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg);
346 344 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value);
347 345 static void pcic_cb_enable_intr(dev_info_t *);
348 346 static void pcic_cb_disable_intr(dev_info_t *);
349 347 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq);
350 348 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket);
351 349
352 350 static cb_nexus_cb_t pcic_cbnexus_ops = {
353 351 pcic_cb_enable_intr,
354 352 pcic_cb_disable_intr
355 353 };
356 354
357 355 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel);
358 356 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket);
359 357
360 358 #if defined(__sparc)
361 359 static int pcic_fault(enum pci_fault_ops op, void *arg);
362 360 #endif
363 361
364 362
365 363 /*
366 364 * pcmcia interface operations structure
367 365 * this is the private interface that is exported to the nexus
368 366 */
369 367 pcmcia_if_t pcic_if_ops = {
370 368 PCIF_MAGIC,
371 369 PCIF_VERSION,
372 370 pcic_callback,
373 371 pcic_get_adapter,
374 372 pcic_get_page,
375 373 pcic_get_socket,
376 374 pcic_get_status,
377 375 pcic_get_window,
378 376 pcic_inquire_adapter,
379 377 pcic_inquire_socket,
380 378 pcic_inquire_window,
381 379 pcic_reset_socket,
382 380 pcic_set_page,
383 381 pcic_set_window,
384 382 pcic_set_socket,
385 383 pcic_set_interrupt,
386 384 pcic_clear_interrupt,
387 385 NULL,
388 386 };
389 387
390 388 /*
391 389 * chip type identification routines
392 390 * this list of functions is searched until one of them succeeds
393 391 * or all fail. i82365SL is assumed if failed.
394 392 */
395 393 static int pcic_ci_cirrus(pcicdev_t *);
396 394 static int pcic_ci_vadem(pcicdev_t *);
397 395 static int pcic_ci_ricoh(pcicdev_t *);
398 396
399 397 int (*pcic_ci_funcs[])(pcicdev_t *) = {
400 398 pcic_ci_cirrus,
401 399 pcic_ci_vadem,
402 400 pcic_ci_ricoh,
403 401 NULL
404 402 };
405 403
406 404 static struct modldrv modldrv = {
407 405 &mod_driverops, /* Type of module. This one is a driver */
408 406 "PCIC PCMCIA adapter driver", /* Name of the module. */
409 407 &pcic_devops, /* driver ops */
410 408 };
411 409
412 410 static struct modlinkage modlinkage = {
413 411 MODREV_1, (void *)&modldrv, NULL
414 412 };
415 413
416 414 int
417 415 _init()
418 416 {
419 417 int stat;
420 418
421 419 /* Allocate soft state */
422 420 if ((stat = ddi_soft_state_init(&pcic_soft_state_p,
423 421 SOFTC_SIZE, 2)) != DDI_SUCCESS)
424 422 return (stat);
425 423
426 424 if ((stat = mod_install(&modlinkage)) != 0)
427 425 ddi_soft_state_fini(&pcic_soft_state_p);
428 426
429 427 return (stat);
430 428 }
431 429
432 430 int
433 431 _fini()
434 432 {
435 433 int stat = 0;
436 434
437 435 if ((stat = mod_remove(&modlinkage)) != 0)
438 436 return (stat);
439 437
440 438 if (pcic_deb_threadid) {
441 439 mutex_enter(&pcic_deb_mtx);
442 440 pcic_deb_threadid = 0;
443 441 while (!pcic_deb_threadid)
444 442 cv_wait(&pcic_deb_cv, &pcic_deb_mtx);
445 443 pcic_deb_threadid = 0;
446 444 mutex_exit(&pcic_deb_mtx);
447 445
448 446 mutex_destroy(&pcic_deb_mtx);
449 447 cv_destroy(&pcic_deb_cv);
450 448 }
451 449
452 450 ddi_soft_state_fini(&pcic_soft_state_p);
453 451
454 452 return (stat);
455 453 }
456 454
457 455 int
458 456 _info(struct modinfo *modinfop)
459 457 {
460 458 return (mod_info(&modlinkage, modinfop));
461 459 }
462 460
463 461 /*
464 462 * pcic_getinfo()
465 463 * provide instance/device information about driver
466 464 */
467 465 /*ARGSUSED*/
468 466 static int
469 467 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result)
470 468 {
471 469 anp_t *anp;
472 470 int error = DDI_SUCCESS;
473 471 minor_t minor;
474 472
475 473 switch (cmd) {
476 474 case DDI_INFO_DEVT2DEVINFO:
477 475 minor = getminor((dev_t)arg);
478 476 minor &= 0x7f;
479 477 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor)))
480 478 *result = NULL;
481 479 else
482 480 *result = anp->an_dip;
483 481 break;
484 482 case DDI_INFO_DEVT2INSTANCE:
485 483 minor = getminor((dev_t)arg);
486 484 minor &= 0x7f;
487 485 *result = (void *)((long)minor);
488 486 break;
489 487 default:
490 488 error = DDI_FAILURE;
491 489 break;
492 490 }
493 491 return (error);
494 492 }
495 493
496 494 static int
497 495 pcic_probe(dev_info_t *dip)
498 496 {
499 497 int value;
500 498 ddi_device_acc_attr_t attr;
501 499 ddi_acc_handle_t handle;
502 500 uchar_t *index, *data;
503 501
504 502 if (ddi_dev_is_sid(dip) == DDI_SUCCESS)
505 503 return (DDI_PROBE_DONTCARE);
506 504
507 505 /*
508 506 * find a PCIC device (any vendor)
509 507 * while there can be up to 4 such devices in
510 508 * a system, we currently only look for 1
511 509 * per probe. There will be up to 2 chips per
512 510 * instance since they share I/O space
513 511 */
514 512 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
515 513 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC;
516 514 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
517 515
518 516 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM,
519 517 (caddr_t *)&index,
520 518 PCIC_ISA_CONTROL_REG_OFFSET,
521 519 PCIC_ISA_CONTROL_REG_LENGTH,
522 520 &attr, &handle) != DDI_SUCCESS)
523 521 return (DDI_PROBE_FAILURE);
524 522
525 523 data = index + 1;
526 524
527 525 #if defined(PCIC_DEBUG)
528 526 if (pcic_debug)
529 527 cmn_err(CE_CONT, "pcic_probe: entered\n");
530 528 if (pcic_debug)
531 529 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index);
532 530 #endif
533 531 ddi_put8(handle, index, PCIC_CHIP_REVISION);
534 532 ddi_put8(handle, data, 0);
535 533 value = ddi_get8(handle, data);
536 534 #if defined(PCIC_DEBUG)
537 535 if (pcic_debug)
538 536 cmn_err(CE_CONT, "\tchip revision register = %x\n", value);
539 537 #endif
540 538 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW &&
541 539 (value & 0x30) == 0) {
542 540 /*
543 541 * we probably have a PCIC chip in the system
544 542 * do a little more checking. If we find one,
545 543 * reset everything in case of softboot
546 544 */
547 545 ddi_put8(handle, index, PCIC_MAPPING_ENABLE);
548 546 ddi_put8(handle, data, 0);
549 547 value = ddi_get8(handle, data);
550 548 #if defined(PCIC_DEBUG)
551 549 if (pcic_debug)
552 550 cmn_err(CE_CONT, "\tzero test = %x\n", value);
553 551 #endif
554 552 /* should read back as zero */
555 553 if (value == 0) {
556 554 /*
557 555 * we do have one and it is off the bus
558 556 */
559 557 #if defined(PCIC_DEBUG)
560 558 if (pcic_debug)
561 559 cmn_err(CE_CONT, "pcic_probe: success\n");
562 560 #endif
563 561 ddi_regs_map_free(&handle);
564 562 return (DDI_PROBE_SUCCESS);
565 563 }
566 564 }
567 565 #if defined(PCIC_DEBUG)
568 566 if (pcic_debug)
569 567 cmn_err(CE_CONT, "pcic_probe: failed\n");
570 568 #endif
571 569 ddi_regs_map_free(&handle);
572 570 return (DDI_PROBE_FAILURE);
573 571 }
574 572
575 573 /*
576 574 * These are just defaults they can also be changed via a property in the
577 575 * conf file.
578 576 */
579 577 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM;
580 578 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM;
581 579 static int pcic_do_pcmcia_sr = 1;
582 580 static int pcic_use_cbpwrctl = PCF_CBPWRCTL;
583 581
584 582 /*
585 583 * enable insertion/removal interrupt for 32bit cards
586 584 */
587 585 static int
588 586 cardbus_enable_cd_intr(dev_info_t *dip)
589 587 {
590 588 ddi_acc_handle_t iohandle;
591 589 caddr_t ioaddr;
592 590 ddi_device_acc_attr_t attr;
593 591 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
594 592 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
595 593 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
596 594 (void) ddi_regs_map_setup(dip, 1,
597 595 (caddr_t *)&ioaddr,
598 596 0,
599 597 4096,
600 598 &attr, &iohandle);
601 599
602 600 /* CSC Interrupt: Card detect interrupt on */
603 601 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK),
604 602 ddi_get32(iohandle,
605 603 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK);
606 604
607 605 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT),
608 606 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT)));
609 607
610 608 ddi_regs_map_free(&iohandle);
611 609 return (1);
612 610 }
613 611
614 612 /*
615 613 * quiesce(9E) entry point.
616 614 *
617 615 * This function is called when the system is single-threaded at high
618 616 * PIL with preemption disabled. Therefore, this function must not be
619 617 * blocked.
620 618 *
621 619 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
622 620 * DDI_FAILURE indicates an error condition and should almost never happen.
623 621 */
624 622 static int32_t
625 623 pcic_quiesce(dev_info_t *dip)
626 624 {
627 625 anp_t *anp = ddi_get_driver_private(dip);
628 626 pcicdev_t *pcic = anp->an_private;
629 627 int i;
630 628
631 629 for (i = 0; i < pcic->pc_numsockets; i++) {
632 630 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0);
633 631 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0);
634 632 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
635 633 /* disable interrupts and put card into RESET */
636 634 pcic_putb(pcic, i, PCIC_INTERRUPT, 0);
637 635 /* poweroff socket */
638 636 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0);
639 637 pcic_putcb(pcic, CB_CONTROL, 0);
640 638 }
641 639
642 640 return (DDI_SUCCESS);
643 641 }
644 642
645 643 /*
646 644 * pcic_attach()
647 645 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver
648 646 * to the system. This is a child of "sysbus" since that is where
649 647 * the hardware lives, but it provides services to the "pcmcia"
650 648 * nexus driver. It gives a pointer back via its private data
651 649 * structure which contains both the dip and socket services entry
652 650 * points
653 651 */
654 652 static int
655 653 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
656 654 {
657 655 anp_t *pcic_nexus;
658 656 pcicdev_t *pcic;
659 657 int irqlevel, value;
660 658 int pci_cfrn, pci_ctrn;
661 659 int i, j, smi, actual;
662 660 char *typename;
663 661 char bus_type[16] = "(unknown)";
664 662 int len = sizeof (bus_type);
665 663 ddi_device_acc_attr_t attr;
666 664 anp_t *anp = ddi_get_driver_private(dip);
667 665 uint_t pri;
668 666
669 667 #if defined(PCIC_DEBUG)
670 668 if (pcic_debug) {
671 669 cmn_err(CE_CONT, "pcic_attach: entered\n");
672 670 }
673 671 #endif
674 672 switch (cmd) {
675 673 case DDI_ATTACH:
676 674 break;
677 675 case DDI_RESUME:
678 676 pcic = anp->an_private;
679 677 /*
680 678 * for now, this is a simulated resume.
681 679 * a real one may need different things.
682 680 */
683 681 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) {
684 682 mutex_enter(&pcic->pc_lock);
685 683 /* should probe for new sockets showing up */
686 684 pcic_setup_adapter(pcic);
687 685 pcic->pc_flags &= ~PCF_SUSPENDED;
688 686 mutex_exit(&pcic->pc_lock);
689 687 (void) pcmcia_begin_resume(dip);
690 688
691 689 pcic_do_resume(pcic);
692 690 #ifdef CARDBUS
693 691 cardbus_restore_children(ddi_get_child(dip));
694 692 #endif
695 693
696 694 /*
697 695 * for complete implementation need END_RESUME (later)
698 696 */
699 697 return (DDI_SUCCESS);
700 698
701 699 }
702 700 return (DDI_SUCCESS);
703 701 default:
704 702 return (DDI_FAILURE);
705 703 }
706 704
707 705 /*
708 706 * Allocate soft state associated with this instance.
709 707 */
710 708 if (ddi_soft_state_zalloc(pcic_soft_state_p,
711 709 ddi_get_instance(dip)) != DDI_SUCCESS) {
712 710 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n",
713 711 ddi_get_instance(dip));
714 712 return (DDI_FAILURE);
715 713 }
716 714
717 715 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p,
718 716 ddi_get_instance(dip));
719 717
720 718 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP);
721 719
722 720 pcic->dip = dip;
723 721 pcic_nexus->an_dip = dip;
724 722 pcic_nexus->an_if = &pcic_if_ops;
725 723 pcic_nexus->an_private = pcic;
726 724 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]);
727 725 pcic->pc_power = pcic_power;
728 726
729 727 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
730 728 "pci-control-reg-number", pci_control_reg_num);
731 729 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
732 730 "pci-config-reg-number", pci_config_reg_num);
733 731
734 732 ddi_set_driver_private(dip, pcic_nexus);
735 733
736 734 /*
737 735 * pcic->pc_irq is really the IPL level we want to run at
738 736 * set the default values here and override from intr spec
739 737 */
740 738 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
741 739 "interrupt-priorities", -1);
742 740
743 741 if (pcic->pc_irq == -1) {
744 742 int actual;
745 743 uint_t pri;
746 744 ddi_intr_handle_t hdl;
747 745
748 746 /* see if intrspec tells us different */
749 747 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED,
750 748 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) {
751 749 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS)
752 750 pcic->pc_irq = pri;
753 751 else
754 752 pcic->pc_irq = LOCK_LEVEL + 1;
755 753 (void) ddi_intr_free(hdl);
756 754 }
757 755 }
758 756 pcic_nexus->an_ipl = pcic->pc_irq;
759 757
760 758 /*
761 759 * Check our parent bus type. We do different things based on which
762 760 * bus we're on.
763 761 */
764 762 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip),
765 763 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP,
766 764 "device_type", (caddr_t)&bus_type[0], &len) !=
767 765 DDI_PROP_SUCCESS) {
768 766 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip),
769 767 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP,
770 768 "bus-type", (caddr_t)&bus_type[0], &len) !=
771 769 DDI_PROP_SUCCESS) {
772 770
773 771 cmn_err(CE_CONT,
774 772 "pcic%d: can't find parent bus type\n",
775 773 ddi_get_instance(dip));
776 774
777 775 kmem_free(pcic, sizeof (pcicdev_t));
778 776 ddi_soft_state_free(pcic_soft_state_p,
779 777 ddi_get_instance(dip));
780 778 return (DDI_FAILURE);
781 779 }
782 780 } /* ddi_prop_op("device_type") */
783 781
784 782 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 ||
785 783 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0) {
786 784 pcic->pc_flags = PCF_PCIBUS;
787 785 } else {
788 786 cmn_err(CE_WARN, "!pcic%d: non-pci mode (%s) not supported, "
789 787 "set BIOS to yenta mode if applicable\n",
790 788 ddi_get_instance(dip), bus_type);
791 789 kmem_free(pcic, sizeof (pcicdev_t));
792 790 ddi_soft_state_free(pcic_soft_state_p,
793 791 ddi_get_instance(dip));
794 792 return (DDI_FAILURE);
795 793 }
796 794
797 795 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip),
798 796 DDI_PROP_CANSLEEP,
799 797 "clock-frequency", 0)) == 0) {
800 798 if (pcic->pc_flags & PCF_PCIBUS)
801 799 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK;
802 800 else
803 801 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK;
804 802 } else {
805 803 /*
806 804 * OBP can declare the speed in Hz...
807 805 */
808 806 if (pcic->bus_speed > 1000000)
809 807 pcic->bus_speed /= 1000000;
810 808 } /* ddi_prop_op("clock-frequency") */
811 809
812 810 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */
813 811
814 812 #ifdef PCIC_DEBUG
815 813 if (pcic_debug) {
816 814 cmn_err(CE_CONT,
817 815 "pcic%d: parent bus type = [%s], speed = %d MHz\n",
818 816 ddi_get_instance(dip),
819 817 bus_type, pcic->bus_speed);
820 818 }
821 819 #endif
822 820
823 821 /*
824 822 * The reg properties on a PCI node are different than those
825 823 * on a non-PCI node. Handle that difference here.
826 824 * If it turns out to be a CardBus chip, we have even more
827 825 * differences.
828 826 */
829 827 if (pcic->pc_flags & PCF_PCIBUS) {
830 828 int class_code;
831 829 #if defined(__i386) || defined(__amd64)
832 830 pcic->pc_base = 0x1000000;
833 831 pcic->pc_bound = (uint32_t)~0;
834 832 pcic->pc_iobase = 0x1000;
835 833 pcic->pc_iobound = 0xefff;
836 834 #elif defined(__sparc)
837 835 pcic->pc_base = 0x0;
838 836 pcic->pc_bound = (uint32_t)~0;
839 837 pcic->pc_iobase = 0x00000;
840 838 pcic->pc_iobound = 0xffff;
841 839 #endif
842 840
843 841 /* usually need to get at config space so map first */
844 842 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
845 843 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
846 844 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
847 845
848 846 if (ddi_regs_map_setup(dip, pci_cfrn,
849 847 (caddr_t *)&pcic->cfgaddr,
850 848 PCIC_PCI_CONFIG_REG_OFFSET,
851 849 PCIC_PCI_CONFIG_REG_LENGTH,
852 850 &attr,
853 851 &pcic->cfg_handle) !=
854 852 DDI_SUCCESS) {
855 853 cmn_err(CE_CONT,
856 854 "pcic%d: unable to map config space"
857 855 "regs\n",
858 856 ddi_get_instance(dip));
859 857
860 858 kmem_free(pcic, sizeof (pcicdev_t));
861 859 return (DDI_FAILURE);
862 860 } /* ddi_regs_map_setup */
863 861
864 862 class_code = ddi_getprop(DDI_DEV_T_ANY, dip,
865 863 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS,
866 864 "class-code", -1);
867 865 #ifdef PCIC_DEBUG
868 866 if (pcic_debug) {
869 867 cmn_err(CE_CONT, "pcic_attach class_code=%x\n",
870 868 class_code);
871 869 }
872 870 #endif
873 871
874 872 switch (class_code) {
875 873 case PCIC_PCI_CARDBUS:
876 874 pcic->pc_flags |= PCF_CARDBUS;
877 875 pcic->pc_io_type = PCIC_IO_TYPE_YENTA;
878 876 /*
879 877 * Get access to the adapter registers on the
880 878 * PCI bus. A 4K memory page
881 879 */
882 880 #if defined(PCIC_DEBUG)
883 881 pcic_err(dip, 8, "Is Cardbus device\n");
884 882 if (pcic_debug) {
885 883 int nr;
886 884 long rs;
887 885 (void) ddi_dev_nregs(dip, &nr);
888 886 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p,"
889 887 "cfghndl 0x%p nregs %d",
890 888 (void *)pcic->cfgaddr,
891 889 (void *)pcic->cfg_handle, nr);
892 890
893 891 (void) ddi_dev_regsize(dip,
894 892 PCIC_PCI_CONTROL_REG_NUM, &rs);
895 893
896 894 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n",
897 895 PCIC_PCI_CONTROL_REG_NUM, (int)rs);
898 896 }
899 897 #endif
900 898 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
901 899 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
902 900 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
903 901
904 902 if (ddi_regs_map_setup(dip, pci_ctrn,
905 903 (caddr_t *)&pcic->ioaddr,
906 904 PCIC_PCI_CONTROL_REG_OFFSET,
907 905 PCIC_CB_CONTROL_REG_LENGTH,
908 906 &attr, &pcic->handle) !=
909 907 DDI_SUCCESS) {
910 908 cmn_err(CE_CONT,
911 909 "pcic%d: unable to map PCI regs\n",
912 910 ddi_get_instance(dip));
913 911 ddi_regs_map_free(&pcic->cfg_handle);
914 912 kmem_free(pcic, sizeof (pcicdev_t));
915 913 return (DDI_FAILURE);
916 914 } /* ddi_regs_map_setup */
917 915
918 916 /*
919 917 * Find out the chip type - If we're on a PCI bus,
920 918 * the adapter has that information in the PCI
921 919 * config space.
922 920 * Note that we call pcic_find_pci_type here since
923 921 * it needs a valid mapped pcic->handle to
924 922 * access some of the adapter registers in
925 923 * some cases.
926 924 */
927 925 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) {
928 926 ddi_regs_map_free(&pcic->handle);
929 927 ddi_regs_map_free(&pcic->cfg_handle);
930 928 kmem_free(pcic, sizeof (pcicdev_t));
931 929 cmn_err(CE_WARN, "pcic: %s: unsupported "
932 930 "bridge\n", ddi_get_name_addr(dip));
933 931 return (DDI_FAILURE);
934 932 }
935 933 break;
936 934
937 935 default:
938 936 case PCIC_PCI_PCMCIA:
939 937 /*
940 938 * Get access to the adapter IO registers on the
941 939 * PCI bus config space.
942 940 */
943 941 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
944 942 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
945 943 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
946 944
947 945 /*
948 946 * We need a default mapping to the adapter's IO
949 947 * control register space. For most adapters
950 948 * that are of class PCIC_PCI_PCMCIA (or of
951 949 * a default class) the control registers
952 950 * will be using the 82365-type control/data
953 951 * format.
954 952 */
955 953 if (ddi_regs_map_setup(dip, pci_ctrn,
956 954 (caddr_t *)&pcic->ioaddr,
957 955 PCIC_PCI_CONTROL_REG_OFFSET,
958 956 PCIC_PCI_CONTROL_REG_LENGTH,
959 957 &attr,
960 958 &pcic->handle) != DDI_SUCCESS) {
961 959 cmn_err(CE_CONT,
962 960 "pcic%d: unable to map PCI regs\n",
963 961 ddi_get_instance(dip));
964 962 ddi_regs_map_free(&pcic->cfg_handle);
965 963 kmem_free(pcic, sizeof (pcicdev_t));
966 964 return (DDI_FAILURE);
967 965 } /* ddi_regs_map_setup */
968 966
969 967 /*
970 968 * Find out the chip type - If we're on a PCI bus,
971 969 * the adapter has that information in the PCI
972 970 * config space.
973 971 * Note that we call pcic_find_pci_type here since
974 972 * it needs a valid mapped pcic->handle to
975 973 * access some of the adapter registers in
976 974 * some cases.
977 975 */
978 976 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) {
979 977 ddi_regs_map_free(&pcic->handle);
980 978 ddi_regs_map_free(&pcic->cfg_handle);
981 979 kmem_free(pcic, sizeof (pcicdev_t));
982 980 cmn_err(CE_WARN, "pcic: %s: unsupported "
983 981 "bridge\n",
984 982 ddi_get_name_addr(dip));
985 983 return (DDI_FAILURE);
986 984 }
987 985
988 986 /*
989 987 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant
990 988 * for extended registers even though they are
991 989 * not CardBus adapters. For those adapters,
992 990 * re-map pcic->handle to be large enough to
993 991 * encompass the Yenta registers.
994 992 */
995 993 switch (pcic->pc_type) {
996 994 case PCIC_TI_PCI1031:
997 995 ddi_regs_map_free(&pcic->handle);
998 996
999 997 if (ddi_regs_map_setup(dip,
1000 998 PCIC_PCI_CONTROL_REG_NUM,
1001 999 (caddr_t *)&pcic->ioaddr,
1002 1000 PCIC_PCI_CONTROL_REG_OFFSET,
1003 1001 PCIC_CB_CONTROL_REG_LENGTH,
1004 1002 &attr,
1005 1003 &pcic->handle) != DDI_SUCCESS) {
1006 1004 cmn_err(CE_CONT,
1007 1005 "pcic%d: unable to map "
1008 1006 "PCI regs\n",
1009 1007 ddi_get_instance(dip));
1010 1008 ddi_regs_map_free(&pcic->cfg_handle);
1011 1009 kmem_free(pcic, sizeof (pcicdev_t));
1012 1010 return (DDI_FAILURE);
1013 1011 } /* ddi_regs_map_setup */
1014 1012 break;
1015 1013 default:
1016 1014 break;
1017 1015 } /* switch (pcic->pc_type) */
1018 1016 break;
1019 1017 } /* switch (class_code) */
1020 1018 } else {
1021 1019 /*
1022 1020 * We're not on a PCI bus, so assume an ISA bus type
1023 1021 * register property. Get access to the adapter IO
1024 1022 * registers on a non-PCI bus.
1025 1023 */
1026 1024 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
1027 1025 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC;
1028 1026 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
1029 1027 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM;
1030 1028 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM;
1031 1029
1032 1030 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM,
1033 1031 (caddr_t *)&pcic->ioaddr,
1034 1032 PCIC_ISA_CONTROL_REG_OFFSET,
1035 1033 PCIC_ISA_CONTROL_REG_LENGTH,
1036 1034 &attr,
1037 1035 &pcic->handle) != DDI_SUCCESS) {
1038 1036 cmn_err(CE_CONT,
1039 1037 "pcic%d: unable to map ISA registers\n",
1040 1038 ddi_get_instance(dip));
1041 1039
1042 1040 kmem_free(pcic, sizeof (pcicdev_t));
1043 1041 return (DDI_FAILURE);
1044 1042 } /* ddi_regs_map_setup */
1045 1043
1046 1044 /* ISA bus is limited to 24-bits, but not first 640K */
1047 1045 pcic->pc_base = 0xd0000;
1048 1046 pcic->pc_bound = (uint32_t)~0;
1049 1047 pcic->pc_iobase = 0x1000;
1050 1048 pcic->pc_iobound = 0xefff;
1051 1049 } /* !PCF_PCIBUS */
1052 1050
1053 1051 #ifdef PCIC_DEBUG
1054 1052 if (pcic_debug) {
1055 1053 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n",
1056 1054 pcic->pc_flags, pcic->pc_type);
1057 1055 }
1058 1056 #endif
1059 1057
1060 1058 /*
1061 1059 * Setup various adapter registers for the PCI case. For the
1062 1060 * non-PCI case, find out the chip type.
1063 1061 */
1064 1062 if (pcic->pc_flags & PCF_PCIBUS) {
1065 1063 int iline;
1066 1064 #if defined(__sparc)
1067 1065 iline = 0;
1068 1066 #else
1069 1067 iline = cardbus_validate_iline(dip, pcic->cfg_handle);
1070 1068 #endif
1071 1069
1072 1070 /* set flags and socket counts based on chip type */
1073 1071 switch (pcic->pc_type) {
1074 1072 uint32_t cfg;
1075 1073 case PCIC_INTEL_i82092:
1076 1074 cfg = ddi_get8(pcic->cfg_handle,
1077 1075 pcic->cfgaddr + PCIC_82092_PCICON);
1078 1076 /* we can only support 4 Socket version */
1079 1077 if (cfg & PCIC_82092_4_SOCKETS) {
1080 1078 pcic->pc_numsockets = 4;
1081 1079 pcic->pc_type = PCIC_INTEL_i82092;
1082 1080 if (iline != 0xFF)
1083 1081 pcic->pc_intr_mode =
1084 1082 PCIC_INTR_MODE_PCI_1;
1085 1083 else
1086 1084 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA;
1087 1085 } else {
1088 1086 cmn_err(CE_CONT,
1089 1087 "pcic%d: Intel 82092 adapter "
1090 1088 "in unsupported configuration: 0x%x",
1091 1089 ddi_get_instance(pcic->dip), cfg);
1092 1090 pcic->pc_numsockets = 0;
1093 1091 } /* PCIC_82092_4_SOCKETS */
1094 1092 break;
1095 1093 case PCIC_CL_PD6730:
1096 1094 case PCIC_CL_PD6729:
1097 1095 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1;
1098 1096 cfg = ddi_getprop(DDI_DEV_T_ANY, dip,
1099 1097 DDI_PROP_CANSLEEP,
1100 1098 "interrupts", 0);
1101 1099 /* if not interrupt pin then must use ISA style IRQs */
1102 1100 if (cfg == 0 || iline == 0xFF)
1103 1101 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA;
1104 1102 else {
1105 1103 /*
1106 1104 * we have the option to use PCI interrupts.
1107 1105 * this might not be optimal but in some cases
1108 1106 * is the only thing possible (sparc case).
1109 1107 * we now deterine what is possible.
1110 1108 */
1111 1109 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1;
1112 1110 }
1113 1111 pcic->pc_numsockets = 2;
1114 1112 pcic->pc_flags |= PCF_IO_REMAP;
1115 1113 break;
1116 1114 case PCIC_TI_PCI1031:
1117 1115 /* this chip doesn't do CardBus but looks like one */
1118 1116 pcic->pc_flags &= ~PCF_CARDBUS;
1119 1117 /* FALLTHROUGH */
1120 1118 default:
1121 1119 pcic->pc_flags |= PCF_IO_REMAP;
1122 1120 /* FALLTHROUGH */
1123 1121 /* indicate feature even if not supported */
1124 1122 pcic->pc_flags |= PCF_DMA | PCF_ZV;
1125 1123 /* Not sure if these apply to all these chips */
1126 1124 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP);
1127 1125 pcic->pc_flags |= pcic_use_cbpwrctl;
1128 1126
1129 1127 pcic->pc_numsockets = 1; /* one per function */
1130 1128 if (iline != 0xFF) {
1131 1129 uint8_t cfg;
1132 1130 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1;
1133 1131
1134 1132 cfg = ddi_get8(pcic->cfg_handle,
1135 1133 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG));
1136 1134 cfg &= (~PCIC_FUN_INT_MOD_ISA);
1137 1135 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr +
1138 1136 PCIC_BRIDGE_CTL_REG), cfg);
1139 1137 }
1140 1138 else
1141 1139 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA;
1142 1140 pcic->pc_io_type = PCIC_IOTYPE_YENTA;
1143 1141 break;
1144 1142 }
1145 1143 } else {
1146 1144 /*
1147 1145 * We're not on a PCI bus so do some more
1148 1146 * checking for adapter type here.
1149 1147 * For the non-PCI bus case:
1150 1148 * It could be any one of a number of different chips
1151 1149 * If we can't determine anything else, it is assumed
1152 1150 * to be an Intel 82365SL. The Cirrus Logic PD6710
1153 1151 * has an extension register that provides unique
1154 1152 * identification. Toshiba chip isn't detailed as yet.
1155 1153 */
1156 1154
1157 1155 /* Init the CL id mode */
1158 1156 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0);
1159 1157 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO);
1160 1158
1161 1159 /* default to Intel i82365SL and then refine */
1162 1160 pcic->pc_type = PCIC_I82365SL;
1163 1161 pcic->pc_chipname = PCIC_TYPE_I82365SL;
1164 1162 for (value = 0; pcic_ci_funcs[value] != NULL; value++) {
1165 1163 /* go until one succeeds or none left */
1166 1164 if (pcic_ci_funcs[value](pcic))
1167 1165 break;
1168 1166 }
1169 1167
1170 1168 /* any chip specific flags get set here */
1171 1169 switch (pcic->pc_type) {
1172 1170 case PCIC_CL_PD6722:
1173 1171 pcic->pc_flags |= PCF_DMA;
1174 1172 }
1175 1173
1176 1174 for (i = 0; i < PCIC_MAX_SOCKETS; i++) {
1177 1175 /*
1178 1176 * look for total number of sockets.
1179 1177 * basically check each possible socket for
1180 1178 * presence like in probe
1181 1179 */
1182 1180
1183 1181 /* turn all windows off */
1184 1182 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1185 1183 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE);
1186 1184
1187 1185 /*
1188 1186 * if a zero is read back, then this socket
1189 1187 * might be present. It would be except for
1190 1188 * some systems that map the secondary PCIC
1191 1189 * chip space back to the first.
1192 1190 */
1193 1191 if (value != 0) {
1194 1192 /* definitely not so skip */
1195 1193 /* note: this is for Compaq support */
1196 1194 continue;
1197 1195 }
1198 1196
1199 1197 /* further tests */
1200 1198 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) &
1201 1199 PCIC_REV_MASK;
1202 1200 if (!(value >= PCIC_REV_LEVEL_LOW &&
1203 1201 value <= PCIC_REV_LEVEL_HI))
1204 1202 break;
1205 1203
1206 1204 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa);
1207 1205 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55);
1208 1206 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW);
1209 1207
1210 1208 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW);
1211 1209 if (value != 0xaa || j != 0x55)
1212 1210 break;
1213 1211
1214 1212 /*
1215 1213 * at this point we know if we have hardware
1216 1214 * of some type and not just the bus holding
1217 1215 * a pattern for us. We still have to determine
1218 1216 * the case where more than 2 sockets are
1219 1217 * really the same due to peculiar mappings of
1220 1218 * hardware.
1221 1219 */
1222 1220 j = pcic->pc_numsockets++;
1223 1221 pcic->pc_sockets[j].pcs_flags = 0;
1224 1222 pcic->pc_sockets[j].pcs_io = pcic->ioaddr;
1225 1223 pcic->pc_sockets[j].pcs_socket = i;
1226 1224
1227 1225 /* put PC Card into RESET, just in case */
1228 1226 value = pcic_getb(pcic, i, PCIC_INTERRUPT);
1229 1227 pcic_putb(pcic, i, PCIC_INTERRUPT,
1230 1228 value & ~PCIC_RESET);
1231 1229 }
1232 1230
1233 1231 #if defined(PCIC_DEBUG)
1234 1232 if (pcic_debug)
1235 1233 cmn_err(CE_CONT, "num sockets = %d\n",
1236 1234 pcic->pc_numsockets);
1237 1235 #endif
1238 1236 if (pcic->pc_numsockets == 0) {
1239 1237 ddi_regs_map_free(&pcic->handle);
1240 1238 kmem_free(pcic, sizeof (pcicdev_t));
1241 1239 return (DDI_FAILURE);
1242 1240 }
1243 1241
1244 1242 /*
1245 1243 * need to think this through again in light of
1246 1244 * Compaq not following the model that all the
1247 1245 * chip vendors recommend. IBM 755 seems to be
1248 1246 * afflicted as well. Basically, if the vendor
1249 1247 * wired things wrong, socket 0 responds for socket 2
1250 1248 * accesses, etc.
1251 1249 */
1252 1250 if (pcic->pc_numsockets > 2) {
1253 1251 int count = pcic->pc_numsockets / 4;
1254 1252 for (i = 0; i < count; i++) {
1255 1253 /* put pattern into socket 0 */
1256 1254 pcic_putb(pcic, i,
1257 1255 PCIC_SYSMEM_0_STARTLOW, 0x11);
1258 1256
1259 1257 /* put pattern into socket 2 */
1260 1258 pcic_putb(pcic, i + 2,
1261 1259 PCIC_SYSMEM_0_STARTLOW, 0x33);
1262 1260
1263 1261 /* read back socket 0 */
1264 1262 value = pcic_getb(pcic, i,
1265 1263 PCIC_SYSMEM_0_STARTLOW);
1266 1264
1267 1265 /* read back chip 1 socket 0 */
1268 1266 j = pcic_getb(pcic, i + 2,
1269 1267 PCIC_SYSMEM_0_STARTLOW);
1270 1268 if (j == value) {
1271 1269 pcic->pc_numsockets -= 2;
1272 1270 }
1273 1271 }
1274 1272 }
1275 1273
1276 1274 smi = 0xff; /* no more override */
1277 1275
1278 1276 if (ddi_getprop(DDI_DEV_T_NONE, dip,
1279 1277 DDI_PROP_DONTPASS, "need-mult-irq",
1280 1278 0xffff) != 0xffff)
1281 1279 pcic->pc_flags |= PCF_MULT_IRQ;
1282 1280
1283 1281 } /* !PCF_PCIBUS */
1284 1282
1285 1283 /*
1286 1284 * some platforms/busses need to have resources setup
1287 1285 * this is temporary until a real resource allocator is
1288 1286 * implemented.
1289 1287 */
1290 1288
1291 1289 pcic_init_assigned(dip);
1292 1290
1293 1291 typename = pcic->pc_chipname;
1294 1292
1295 1293 #ifdef PCIC_DEBUG
1296 1294 if (pcic_debug) {
1297 1295 int nregs, nintrs;
1298 1296
1299 1297 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS)
1300 1298 nregs = 0;
1301 1299
1302 1300 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS)
1303 1301 nintrs = 0;
1304 1302
1305 1303 cmn_err(CE_CONT,
1306 1304 "pcic%d: %d register sets, %d interrupts\n",
1307 1305 ddi_get_instance(dip), nregs, nintrs);
1308 1306
1309 1307 nintrs = 0;
1310 1308 while (nregs--) {
1311 1309 off_t size;
1312 1310
1313 1311 if (ddi_dev_regsize(dip, nintrs, &size) ==
1314 1312 DDI_SUCCESS) {
1315 1313 cmn_err(CE_CONT,
1316 1314 "\tregnum %d size %ld (0x%lx)"
1317 1315 "bytes",
1318 1316 nintrs, size, size);
1319 1317 if (nintrs ==
1320 1318 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ?
1321 1319 PCIC_ISA_CONTROL_REG_NUM :
1322 1320 PCIC_PCI_CONTROL_REG_NUM))
1323 1321 cmn_err(CE_CONT,
1324 1322 " mapped at: 0x%p\n",
1325 1323 (void *)pcic->ioaddr);
1326 1324 else
1327 1325 cmn_err(CE_CONT, "\n");
1328 1326 } else {
1329 1327 cmn_err(CE_CONT,
1330 1328 "\tddi_dev_regsize(rnumber"
1331 1329 "= %d) returns DDI_FAILURE\n",
1332 1330 nintrs);
1333 1331 }
1334 1332 nintrs++;
1335 1333 } /* while */
1336 1334 } /* if (pcic_debug) */
1337 1335 #endif
1338 1336
1339 1337 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL);
1340 1338
1341 1339 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
1342 1340 "disable-audio", 0))
1343 1341 pcic->pc_flags |= PCF_AUDIO;
1344 1342
1345 1343 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
1346 1344 "disable-cardbus", 0))
1347 1345 pcic->pc_flags &= ~PCF_CARDBUS;
1348 1346
1349 1347 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL,
1350 1348 typename);
1351 1349
1352 1350 /*
1353 1351 * Init all socket SMI levels to 0 (no SMI)
1354 1352 */
1355 1353 for (i = 0; i < PCIC_MAX_SOCKETS; i++) {
1356 1354 pcic->pc_sockets[i].pcs_smi = 0;
1357 1355 pcic->pc_sockets[i].pcs_debounce_id = 0;
1358 1356 pcic->pc_sockets[i].pcs_pcic = pcic;
1359 1357 }
1360 1358 pcic->pc_lastreg = -1; /* just to make sure we are in sync */
1361 1359
1362 1360 /*
1363 1361 * Setup the IRQ handler(s)
1364 1362 */
1365 1363 switch (pcic->pc_intr_mode) {
1366 1364 int xx;
1367 1365 case PCIC_INTR_MODE_ISA:
1368 1366 /*
1369 1367 * On a non-PCI bus, we just use whatever SMI IRQ level was
1370 1368 * specified above, and the IO IRQ levels are allocated
1371 1369 * dynamically.
1372 1370 */
1373 1371 for (xx = 15, smi = 0; xx >= 0; xx--) {
1374 1372 if (PCIC_IRQ(xx) &
1375 1373 PCIC_AVAIL_IRQS) {
1376 1374 smi = pcmcia_get_intr(dip, xx);
1377 1375 if (smi >= 0)
1378 1376 break;
1379 1377 }
1380 1378 }
1381 1379 #if defined(PCIC_DEBUG)
1382 1380 if (pcic_debug)
1383 1381 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi);
1384 1382 #endif
1385 1383 /* init to same so share is easy */
1386 1384 for (i = 0; i < pcic->pc_numsockets; i++)
1387 1385 pcic->pc_sockets[i].pcs_smi = smi;
1388 1386 /* any special handling of IRQ levels */
1389 1387 if (pcic->pc_flags & PCF_MULT_IRQ) {
1390 1388 for (i = 2; i < pcic->pc_numsockets; i++) {
1391 1389 if ((i & 1) == 0) {
1392 1390 int xx;
1393 1391 for (xx = 15, smi = 0; xx >= 0; xx--) {
1394 1392 if (PCIC_IRQ(xx) &
1395 1393 PCIC_AVAIL_IRQS) {
1396 1394 smi =
1397 1395 pcmcia_get_intr(dip,
1398 1396 xx);
1399 1397 if (smi >= 0)
1400 1398 break;
1401 1399 }
1402 1400 }
1403 1401 }
1404 1402 if (smi >= 0)
1405 1403 pcic->pc_sockets[i].pcs_smi = smi;
1406 1404 }
1407 1405 }
1408 1406 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets *
1409 1407 sizeof (ddi_intr_handle_t), KM_SLEEP);
1410 1408 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) {
1411 1409 struct intrspec *ispecp;
1412 1410 struct ddi_parent_private_data *pdp;
1413 1411
1414 1412 if (irqlevel == pcic->pc_sockets[i].pcs_smi)
1415 1413 continue;
1416 1414 else {
1417 1415 irqlevel = pcic->pc_sockets[i].pcs_smi;
1418 1416 }
1419 1417 /*
1420 1418 * now convert the allocated IRQ into an intrspec
1421 1419 * and ask our parent to add it. Don't use
1422 1420 * the ddi_add_intr since we don't have a
1423 1421 * default intrspec in all cases.
1424 1422 *
1425 1423 * note: this sort of violates DDI but we don't
1426 1424 * get hardware intrspecs for many of the devices.
1427 1425 * at the same time, we know how to allocate them
1428 1426 * so we do the right thing.
1429 1427 */
1430 1428 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i],
1431 1429 DDI_INTR_TYPE_FIXED, 0, 1, &actual,
1432 1430 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) {
1433 1431 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed",
1434 1432 ddi_get_name(dip));
1435 1433 goto isa_exit1;
1436 1434 }
1437 1435
1438 1436 /*
1439 1437 * See earlier note:
1440 1438 * Since some devices don't have 'intrspec'
1441 1439 * we make one up in rootnex.
1442 1440 *
1443 1441 * However, it is not properly initialized as
1444 1442 * the data it needs is present in this driver
1445 1443 * and there is no interface to pass that up.
1446 1444 * Specially 'irqlevel' is very important and
1447 1445 * it is part of pcic struct.
1448 1446 *
1449 1447 * Set 'intrspec' up here; otherwise adding the
1450 1448 * interrupt will fail.
1451 1449 */
1452 1450 pdp = ddi_get_parent_data(dip);
1453 1451 ispecp = (struct intrspec *)&pdp->par_intr[0];
1454 1452 ispecp->intrspec_vec = irqlevel;
1455 1453 ispecp->intrspec_pri = pcic->pc_irq;
1456 1454
1457 1455 /* Stay compatible w/ PCMCIA */
1458 1456 pcic->pc_pri = (ddi_iblock_cookie_t)
1459 1457 (uintptr_t)pcic->pc_irq;
1460 1458 pcic->pc_dcookie.idev_priority =
1461 1459 (uintptr_t)pcic->pc_pri;
1462 1460 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel;
1463 1461
1464 1462 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i],
1465 1463 pcic->pc_irq);
1466 1464
1467 1465 if (i == 0) {
1468 1466 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER,
1469 1467 DDI_INTR_PRI(pcic->pc_irq));
1470 1468 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER,
1471 1469 NULL);
1472 1470 }
1473 1471
1474 1472 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i],
1475 1473 pcic_intr, (caddr_t)pcic, NULL)) {
1476 1474 cmn_err(CE_WARN,
1477 1475 "%s: ddi_intr_add_handler failed",
1478 1476 ddi_get_name(dip));
1479 1477 goto isa_exit2;
1480 1478 }
1481 1479
1482 1480 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) {
1483 1481 cmn_err(CE_WARN, "%s: ddi_intr_enable failed",
1484 1482 ddi_get_name(dip));
1485 1483 for (j = i; j < 0; j--)
1486 1484 (void) ddi_intr_remove_handler(
1487 1485 pcic->pc_intr_htblp[j]);
1488 1486 goto isa_exit2;
1489 1487 }
1490 1488 }
1491 1489 break;
1492 1490 case PCIC_INTR_MODE_PCI_1:
1493 1491 case PCIC_INTR_MODE_PCI:
1494 1492 /*
1495 1493 * If we're on a PCI bus, we route all interrupts, both SMI
1496 1494 * and IO interrupts, through a single interrupt line.
1497 1495 * Assign the SMI IRQ level to the IO IRQ level here.
1498 1496 */
1499 1497 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t),
1500 1498 KM_SLEEP);
1501 1499 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp,
1502 1500 DDI_INTR_TYPE_FIXED, 0, 1, &actual,
1503 1501 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS)
1504 1502 goto pci_exit1;
1505 1503
1506 1504 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0],
1507 1505 &pri) != DDI_SUCCESS) {
1508 1506 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]);
1509 1507 goto pci_exit1;
1510 1508 }
1511 1509
1512 1510 pcic->pc_pri = (void *)(uintptr_t)pri;
1513 1511 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri);
1514 1512 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL);
1515 1513
1516 1514 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0],
1517 1515 pcic_intr, (caddr_t)pcic, NULL))
1518 1516 goto pci_exit2;
1519 1517
1520 1518 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) {
1521 1519 (void) ddi_intr_remove_handler(
1522 1520 pcic->pc_pci_intr_hdlp[0]);
1523 1521 goto pci_exit2;
1524 1522 }
1525 1523
1526 1524 /* Stay compatible w/ PCMCIA */
1527 1525 pcic->pc_dcookie.idev_priority = (ushort_t)pri;
1528 1526
1529 1527 /* init to same (PCI) so share is easy */
1530 1528 for (i = 0; i < pcic->pc_numsockets; i++)
1531 1529 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */
1532 1530 break;
1533 1531 }
1534 1532
1535 1533 /*
1536 1534 * Setup the adapter hardware to some reasonable defaults.
1537 1535 */
1538 1536 mutex_enter(&pcic->pc_lock);
1539 1537 /* mark the driver state as attached */
1540 1538 pcic->pc_flags |= PCF_ATTACHED;
1541 1539 pcic_setup_adapter(pcic);
1542 1540
1543 1541 for (j = 0; j < pcic->pc_numsockets; j++)
1544 1542 if (ddi_intr_add_softint(dip,
1545 1543 &pcic->pc_sockets[j].pcs_cd_softint_hdl,
1546 1544 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint,
1547 1545 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS)
1548 1546 goto pci_exit2;
1549 1547
1550 1548 #if defined(PCIC_DEBUG)
1551 1549 if (pcic_debug)
1552 1550 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename,
1553 1551 pcic->pc_numsockets);
1554 1552 #endif
1555 1553
1556 1554 pcic_nexus->an_iblock = &pcic->pc_pri;
1557 1555 pcic_nexus->an_idev = &pcic->pc_dcookie;
1558 1556
1559 1557 mutex_exit(&pcic->pc_lock);
1560 1558
1561 1559 #ifdef CARDBUS
1562 1560 (void) cardbus_enable_cd_intr(dip);
1563 1561 if (pcic_debug) {
1564 1562
1565 1563 cardbus_dump_pci_config(dip);
1566 1564 cardbus_dump_socket(dip);
1567 1565 }
1568 1566
1569 1567 /*
1570 1568 * Give the Cardbus misc module a chance to do it's per-adapter
1571 1569 * instance setup. Note that there is no corresponding detach()
1572 1570 * call.
1573 1571 */
1574 1572 if (pcic->pc_flags & PCF_CARDBUS)
1575 1573 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) {
1576 1574 cmn_err(CE_CONT,
1577 1575 "pcic_attach: cardbus_attach failed\n");
1578 1576 goto pci_exit2;
1579 1577 }
1580 1578 #endif
1581 1579
1582 1580 /*
1583 1581 * Give the PCMCIA misc module a chance to do it's per-adapter
1584 1582 * instance setup.
1585 1583 */
1586 1584 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS)
1587 1585 goto pci_exit2;
1588 1586
1589 1587 if (pcic_maxinst == -1) {
1590 1588 /* This assumes that all instances run at the same IPL. */
1591 1589 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL);
1592 1590 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL);
1593 1591 pcic_deb_threadid = thread_create((caddr_t)NULL, 0,
1594 1592 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN,
1595 1593 v.v_maxsyspri - 2);
1596 1594 }
1597 1595 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip));
1598 1596 /*
1599 1597 * Setup a debounce timeout to do an initial card detect
1600 1598 * and enable interrupts.
1601 1599 */
1602 1600 for (j = 0; j < pcic->pc_numsockets; j++) {
1603 1601 pcic->pc_sockets[j].pcs_debounce_id =
1604 1602 pcic_add_debqueue(&pcic->pc_sockets[j],
1605 1603 drv_usectohz(pcic_debounce_time));
1606 1604 }
1607 1605
1608 1606 return (i);
1609 1607
1610 1608 isa_exit2:
1611 1609 mutex_destroy(&pcic->intr_lock);
1612 1610 mutex_destroy(&pcic->pc_lock);
1613 1611 for (j = i; j < 0; j--)
1614 1612 (void) ddi_intr_free(pcic->pc_intr_htblp[j]);
1615 1613 isa_exit1:
1616 1614 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi);
1617 1615 ddi_regs_map_free(&pcic->handle);
1618 1616 if (pcic->pc_flags & PCF_PCIBUS)
1619 1617 ddi_regs_map_free(&pcic->cfg_handle);
1620 1618 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets *
1621 1619 sizeof (ddi_intr_handle_t));
1622 1620 kmem_free(pcic, sizeof (pcicdev_t));
1623 1621 return (DDI_FAILURE);
1624 1622
1625 1623 pci_exit2:
1626 1624 mutex_destroy(&pcic->intr_lock);
1627 1625 mutex_destroy(&pcic->pc_lock);
1628 1626 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]);
1629 1627 pci_exit1:
1630 1628 ddi_regs_map_free(&pcic->handle);
1631 1629 if (pcic->pc_flags & PCF_PCIBUS)
1632 1630 ddi_regs_map_free(&pcic->cfg_handle);
1633 1631 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t));
1634 1632 kmem_free(pcic, sizeof (pcicdev_t));
1635 1633 return (DDI_FAILURE);
1636 1634 }
1637 1635
1638 1636 /*
1639 1637 * pcic_detach()
1640 1638 * request to detach from the system
1641 1639 */
1642 1640 static int
1643 1641 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
1644 1642 {
1645 1643 anp_t *anp = ddi_get_driver_private(dip);
1646 1644 pcicdev_t *pcic = anp->an_private;
1647 1645 int i;
1648 1646
1649 1647 switch (cmd) {
1650 1648 case DDI_DETACH:
1651 1649 /* don't detach if the nexus still talks to us */
1652 1650 if (pcic->pc_callback != NULL)
1653 1651 return (DDI_FAILURE);
1654 1652
1655 1653 /* kill off the pm simulation */
1656 1654 if (pcic->pc_pmtimer)
1657 1655 (void) untimeout(pcic->pc_pmtimer);
1658 1656
1659 1657 /* turn everything off for all sockets and chips */
1660 1658 for (i = 0; i < pcic->pc_numsockets; i++) {
1661 1659 if (pcic->pc_sockets[i].pcs_debounce_id)
1662 1660 pcic_rm_debqueue(
1663 1661 pcic->pc_sockets[i].pcs_debounce_id);
1664 1662 pcic->pc_sockets[i].pcs_debounce_id = 0;
1665 1663
1666 1664 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0);
1667 1665 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0);
1668 1666 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1669 1667 /* disable interrupts and put card into RESET */
1670 1668 pcic_putb(pcic, i, PCIC_INTERRUPT, 0);
1671 1669 }
1672 1670 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]);
1673 1671 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]);
1674 1672 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]);
1675 1673 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t));
1676 1674 pcic->pc_flags = 0;
1677 1675 mutex_destroy(&pcic->pc_lock);
1678 1676 mutex_destroy(&pcic->intr_lock);
1679 1677 cv_destroy(&pcic->pm_cv);
1680 1678 if (pcic->pc_flags & PCF_PCIBUS)
1681 1679 ddi_regs_map_free(&pcic->cfg_handle);
1682 1680 if (pcic->handle)
1683 1681 ddi_regs_map_free(&pcic->handle);
1684 1682 kmem_free(pcic, sizeof (pcicdev_t));
1685 1683 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip));
1686 1684 return (DDI_SUCCESS);
1687 1685
1688 1686 case DDI_SUSPEND:
1689 1687 case DDI_PM_SUSPEND:
1690 1688 /*
1691 1689 * we got a suspend event (either real or imagined)
1692 1690 * so notify the nexus proper that all existing cards
1693 1691 * should go away.
1694 1692 */
1695 1693 mutex_enter(&pcic->pc_lock);
1696 1694 #ifdef CARDBUS
1697 1695 if (pcic->pc_flags & PCF_CARDBUS) {
1698 1696 for (i = 0; i < pcic->pc_numsockets; i++) {
1699 1697 if ((pcic->pc_sockets[i].pcs_flags &
1700 1698 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) ==
1701 1699 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) {
1702 1700
1703 1701 pcmcia_cb_suspended(
1704 1702 pcic->pc_sockets[i].pcs_socket);
1705 1703 }
1706 1704 }
1707 1705
1708 1706 cardbus_save_children(ddi_get_child(dip));
1709 1707 }
1710 1708 #endif
1711 1709 /* turn everything off for all sockets and chips */
1712 1710 for (i = 0; i < pcic->pc_numsockets; i++) {
1713 1711 if (pcic->pc_sockets[i].pcs_debounce_id)
1714 1712 pcic_rm_debqueue(
1715 1713 pcic->pc_sockets[i].pcs_debounce_id);
1716 1714 pcic->pc_sockets[i].pcs_debounce_id = 0;
1717 1715
1718 1716 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0);
1719 1717 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0);
1720 1718 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1721 1719 /* disable interrupts and put card into RESET */
1722 1720 pcic_putb(pcic, i, PCIC_INTERRUPT, 0);
1723 1721 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0);
1724 1722 if (pcic->pc_flags & PCF_CBPWRCTL)
1725 1723 pcic_putcb(pcic, CB_CONTROL, 0);
1726 1724
1727 1725 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) {
1728 1726 pcic->pc_sockets[i].pcs_flags = PCS_STARTING;
1729 1727 /*
1730 1728 * Because we are half way through a save
1731 1729 * all this does is schedule a removal event
1732 1730 * to cs for when the system comes back.
1733 1731 * This doesn't actually matter.
1734 1732 */
1735 1733 if (!pcic_do_pcmcia_sr && pcic_do_removal &&
1736 1734 pcic->pc_callback) {
1737 1735 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg,
1738 1736 PCE_CARD_REMOVAL,
1739 1737 pcic->pc_sockets[i].pcs_socket);
1740 1738 }
1741 1739 }
1742 1740 }
1743 1741
1744 1742 pcic->pc_flags |= PCF_SUSPENDED;
1745 1743 mutex_exit(&pcic->pc_lock);
1746 1744
1747 1745 /*
1748 1746 * when true power management exists, save the adapter
1749 1747 * state here to enable a recovery. For the emulation
1750 1748 * condition, the state is gone
1751 1749 */
1752 1750 return (DDI_SUCCESS);
1753 1751
1754 1752 default:
1755 1753 return (EINVAL);
1756 1754 }
1757 1755 }
1758 1756
1759 1757 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14));
1760 1758 static uint32_t pcic_tisysctl_offbits = 0;
1761 1759 static uint32_t pcic_default_latency = 0x40;
1762 1760
1763 1761 static void
1764 1762 pcic_setup_adapter(pcicdev_t *pcic)
1765 1763 {
1766 1764 int i;
1767 1765 int value, flags;
1768 1766
1769 1767 #if defined(__i386) || defined(__amd64)
1770 1768 pci_regspec_t *reg;
1771 1769 uchar_t bus, dev, func;
1772 1770 uint_t classcode;
1773 1771 int length;
1774 1772 #endif
1775 1773
1776 1774 if (pcic->pc_flags & PCF_PCIBUS) {
1777 1775 /*
1778 1776 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled
1779 1777 */
1780 1778 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM);
1781 1779 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags);
1782 1780 }
1783 1781 /* enable each socket */
1784 1782 for (i = 0; i < pcic->pc_numsockets; i++) {
1785 1783 pcic->pc_sockets[i].pcs_flags = 0;
1786 1784 /* find out the socket capabilities (I/O vs memory) */
1787 1785 value = pcic_getb(pcic, i,
1788 1786 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK;
1789 1787 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH)
1790 1788 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO;
1791 1789
1792 1790 /* disable all windows just in case */
1793 1791 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1794 1792
1795 1793 switch (pcic->pc_type) {
1796 1794 uint32_t cfg32;
1797 1795 uint16_t cfg16;
1798 1796 uint8_t cfg;
1799 1797
1800 1798 /* enable extended registers for Vadem */
1801 1799 case PCIC_VADEM_VG469:
1802 1800 case PCIC_VADEM:
1803 1801
1804 1802 /* enable card status change interrupt for socket */
1805 1803 break;
1806 1804
1807 1805 case PCIC_I82365SL:
1808 1806 break;
1809 1807
1810 1808 case PCIC_CL_PD6710:
1811 1809 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE);
1812 1810 break;
1813 1811
1814 1812 /*
1815 1813 * On the CL_6730, we need to set up the interrupt
1816 1814 * signalling mode (PCI mode) and set the SMI and
1817 1815 * IRQ interrupt lines to PCI/level-mode.
1818 1816 */
1819 1817 case PCIC_CL_PD6730:
1820 1818 switch (pcic->pc_intr_mode) {
1821 1819 case PCIC_INTR_MODE_PCI_1:
1822 1820 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3,
1823 1821 ((clext_reg_read(pcic, i,
1824 1822 PCIC_CLEXT_MISC_CTL_3) &
1825 1823 ~PCIC_CLEXT_INT_PCI) |
1826 1824 PCIC_CLEXT_INT_PCI));
1827 1825 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1,
1828 1826 (PCIC_CLEXT_IRQ_LVL_MODE |
1829 1827 PCIC_CLEXT_SMI_LVL_MODE));
1830 1828 cfg = PCIC_CL_LP_DYN_MODE;
1831 1829 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg);
1832 1830 break;
1833 1831 case PCIC_INTR_MODE_ISA:
1834 1832 break;
1835 1833 }
1836 1834 break;
1837 1835 /*
1838 1836 * On the CL_6729, we set the SMI and IRQ interrupt
1839 1837 * lines to PCI/level-mode. as well as program the
1840 1838 * correct clock speed divider bit.
1841 1839 */
1842 1840 case PCIC_CL_PD6729:
1843 1841 switch (pcic->pc_intr_mode) {
1844 1842 case PCIC_INTR_MODE_PCI_1:
1845 1843 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1,
1846 1844 (PCIC_CLEXT_IRQ_LVL_MODE |
1847 1845 PCIC_CLEXT_SMI_LVL_MODE));
1848 1846
1849 1847 break;
1850 1848 case PCIC_INTR_MODE_ISA:
1851 1849 break;
1852 1850 }
1853 1851 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) {
1854 1852 cfg = 0;
1855 1853 cfg |= PCIC_CL_TIMER_CLK_DIV;
1856 1854 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg);
1857 1855 }
1858 1856 break;
1859 1857 case PCIC_INTEL_i82092:
1860 1858 cfg = PCIC_82092_EN_TIMING;
1861 1859 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ)
1862 1860 cfg |= PCIC_82092_PCICLK_25MHZ;
1863 1861 ddi_put8(pcic->cfg_handle, pcic->cfgaddr +
1864 1862 PCIC_82092_PCICON, cfg);
1865 1863 break;
1866 1864 case PCIC_TI_PCI1130:
1867 1865 case PCIC_TI_PCI1131:
1868 1866 case PCIC_TI_PCI1250:
1869 1867 case PCIC_TI_PCI1031:
1870 1868 cfg = ddi_get8(pcic->cfg_handle,
1871 1869 pcic->cfgaddr + PCIC_DEVCTL_REG);
1872 1870 cfg &= ~PCIC_DEVCTL_INTR_MASK;
1873 1871 switch (pcic->pc_intr_mode) {
1874 1872 case PCIC_INTR_MODE_ISA:
1875 1873 cfg |= PCIC_DEVCTL_INTR_ISA;
1876 1874 break;
1877 1875 }
1878 1876 #ifdef PCIC_DEBUG
1879 1877 if (pcic_debug) {
1880 1878 cmn_err(CE_CONT, "pcic_setup_adapter: "
1881 1879 "write reg 0x%x=%x \n",
1882 1880 PCIC_DEVCTL_REG, cfg);
1883 1881 }
1884 1882 #endif
1885 1883 ddi_put8(pcic->cfg_handle,
1886 1884 pcic->cfgaddr + PCIC_DEVCTL_REG,
1887 1885 cfg);
1888 1886
1889 1887 cfg = ddi_get8(pcic->cfg_handle,
1890 1888 pcic->cfgaddr + PCIC_CRDCTL_REG);
1891 1889 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC|
1892 1890 PCIC_CRDCTL_PCIFUNC);
1893 1891 switch (pcic->pc_intr_mode) {
1894 1892 case PCIC_INTR_MODE_PCI_1:
1895 1893 cfg |= PCIC_CRDCTL_PCIINTR |
1896 1894 PCIC_CRDCTL_PCICSC |
1897 1895 PCIC_CRDCTL_PCIFUNC;
1898 1896 pcic->pc_flags |= PCF_USE_SMI;
1899 1897 break;
1900 1898 }
1901 1899 #ifdef PCIC_DEBUG
1902 1900 if (pcic_debug) {
1903 1901 cmn_err(CE_CONT, "pcic_setup_adapter: "
1904 1902 " write reg 0x%x=%x \n",
1905 1903 PCIC_CRDCTL_REG, cfg);
1906 1904 }
1907 1905 #endif
1908 1906 ddi_put8(pcic->cfg_handle,
1909 1907 pcic->cfgaddr + PCIC_CRDCTL_REG,
1910 1908 cfg);
1911 1909 break;
1912 1910 case PCIC_TI_PCI1221:
1913 1911 case PCIC_TI_PCI1225:
1914 1912 cfg = ddi_get8(pcic->cfg_handle,
1915 1913 pcic->cfgaddr + PCIC_DEVCTL_REG);
1916 1914 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE);
1917 1915 #ifdef PCIC_DEBUG
1918 1916 if (pcic_debug) {
1919 1917 cmn_err(CE_CONT, "pcic_setup_adapter: "
1920 1918 " write reg 0x%x=%x \n",
1921 1919 PCIC_DEVCTL_REG, cfg);
1922 1920 }
1923 1921 #endif
1924 1922 ddi_put8(pcic->cfg_handle,
1925 1923 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg);
1926 1924
1927 1925 cfg = ddi_get8(pcic->cfg_handle,
1928 1926 pcic->cfgaddr + PCIC_DIAG_REG);
1929 1927 if (pcic->pc_type == PCIC_TI_PCI1225) {
1930 1928 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC);
1931 1929 } else {
1932 1930 cfg |= PCIC_DIAG_ASYNC;
1933 1931 }
1934 1932 pcic->pc_flags |= PCF_USE_SMI;
1935 1933 #ifdef PCIC_DEBUG
1936 1934 if (pcic_debug) {
1937 1935 cmn_err(CE_CONT, "pcic_setup_adapter: "
1938 1936 " write reg 0x%x=%x \n",
1939 1937 PCIC_DIAG_REG, cfg);
1940 1938 }
1941 1939 #endif
1942 1940 ddi_put8(pcic->cfg_handle,
1943 1941 pcic->cfgaddr + PCIC_DIAG_REG, cfg);
1944 1942 break;
1945 1943 case PCIC_TI_PCI1520:
1946 1944 case PCIC_TI_PCI1510:
1947 1945 case PCIC_TI_VENDOR:
1948 1946 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) {
1949 1947 /* functional intr routed by ExCA register */
1950 1948 cfg = ddi_get8(pcic->cfg_handle,
1951 1949 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
1952 1950 cfg |= PCIC_FUN_INT_MOD_ISA;
1953 1951 ddi_put8(pcic->cfg_handle,
1954 1952 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
1955 1953 cfg);
1956 1954
1957 1955 /* IRQ serialized interrupts */
1958 1956 cfg = ddi_get8(pcic->cfg_handle,
1959 1957 pcic->cfgaddr + PCIC_DEVCTL_REG);
1960 1958 cfg &= ~PCIC_DEVCTL_INTR_MASK;
1961 1959 cfg |= PCIC_DEVCTL_INTR_ISA;
1962 1960 ddi_put8(pcic->cfg_handle,
1963 1961 pcic->cfgaddr + PCIC_DEVCTL_REG,
1964 1962 cfg);
1965 1963 break;
1966 1964 }
1967 1965
1968 1966 /* CSC interrupt routed to PCI */
1969 1967 cfg = ddi_get8(pcic->cfg_handle,
1970 1968 pcic->cfgaddr + PCIC_DIAG_REG);
1971 1969 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC);
1972 1970 ddi_put8(pcic->cfg_handle,
1973 1971 pcic->cfgaddr + PCIC_DIAG_REG, cfg);
1974 1972
1975 1973 #if defined(__i386) || defined(__amd64)
1976 1974 /*
1977 1975 * Some TI chips have 2 cardbus slots(function0 and
1978 1976 * function1), and others may have just 1 cardbus slot.
1979 1977 * The interrupt routing register is shared between the
1980 1978 * 2 functions and can only be accessed through
1981 1979 * function0. Here we check the presence of the second
1982 1980 * cardbus slot and do the right thing.
1983 1981 */
1984 1982
1985 1983 if (ddi_getlongprop(DDI_DEV_T_ANY, pcic->dip,
1986 1984 DDI_PROP_DONTPASS, "reg", (caddr_t)®,
1987 1985 &length) != DDI_PROP_SUCCESS) {
1988 1986 cmn_err(CE_WARN,
1989 1987 "pcic_setup_adapter(), failed to"
1990 1988 " read reg property\n");
1991 1989 break;
1992 1990 }
1993 1991
1994 1992 bus = PCI_REG_BUS_G(reg->pci_phys_hi);
1995 1993 dev = PCI_REG_DEV_G(reg->pci_phys_hi);
1996 1994 func = PCI_REG_FUNC_G(reg->pci_phys_hi);
1997 1995 kmem_free((caddr_t)reg, length);
1998 1996
1999 1997 if (func != 0) {
2000 1998 break;
2001 1999 }
2002 2000
2003 2001 classcode = (*pci_getl_func)(bus, dev, 1,
2004 2002 PCI_CONF_REVID);
2005 2003 classcode >>= 8;
2006 2004 if (classcode != 0x060700 &&
2007 2005 classcode != 0x060500) {
2008 2006 break;
2009 2007 }
2010 2008
2011 2009 /* Parallel PCI interrupts only */
2012 2010 cfg = ddi_get8(pcic->cfg_handle,
2013 2011 pcic->cfgaddr + PCIC_DEVCTL_REG);
2014 2012 cfg &= ~PCIC_DEVCTL_INTR_MASK;
2015 2013 ddi_put8(pcic->cfg_handle,
2016 2014 pcic->cfgaddr + PCIC_DEVCTL_REG,
2017 2015 cfg);
2018 2016
2019 2017 /* tie INTA and INTB together */
2020 2018 cfg = ddi_get8(pcic->cfg_handle,
2021 2019 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3));
2022 2020 cfg |= PCIC_SYSCTL_INTRTIE;
2023 2021 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr +
2024 2022 PCIC_SYSCTL_REG + 3), cfg);
2025 2023 #endif
2026 2024
2027 2025 break;
2028 2026 case PCIC_TI_PCI1410:
2029 2027 cfg = ddi_get8(pcic->cfg_handle,
2030 2028 pcic->cfgaddr + PCIC_DIAG_REG);
2031 2029 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC);
2032 2030 ddi_put8(pcic->cfg_handle,
2033 2031 pcic->cfgaddr + PCIC_DIAG_REG, cfg);
2034 2032 break;
2035 2033 case PCIC_TOSHIBA_TOPIC100:
2036 2034 case PCIC_TOSHIBA_TOPIC95:
2037 2035 case PCIC_TOSHIBA_VENDOR:
2038 2036 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr +
2039 2037 PCIC_TOSHIBA_SLOT_CTL_REG);
2040 2038 cfg |= (PCIC_TOSHIBA_SCR_SLOTON |
2041 2039 PCIC_TOSHIBA_SCR_SLOTEN);
2042 2040 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK);
2043 2041 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2;
2044 2042 ddi_put8(pcic->cfg_handle, pcic->cfgaddr +
2045 2043 PCIC_TOSHIBA_SLOT_CTL_REG, cfg);
2046 2044 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr +
2047 2045 PCIC_TOSHIBA_INTR_CTL_REG);
2048 2046 switch (pcic->pc_intr_mode) {
2049 2047 case PCIC_INTR_MODE_ISA:
2050 2048 cfg &= ~PCIC_TOSHIBA_ICR_SRC;
2051 2049 ddi_put8(pcic->cfg_handle,
2052 2050 pcic->cfgaddr +
2053 2051 PCIC_TOSHIBA_INTR_CTL_REG, cfg);
2054 2052
2055 2053 cfg = ddi_get8(pcic->cfg_handle,
2056 2054 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
2057 2055 cfg |= PCIC_FUN_INT_MOD_ISA;
2058 2056 ddi_put8(pcic->cfg_handle,
2059 2057 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
2060 2058 cfg);
2061 2059 break;
2062 2060 case PCIC_INTR_MODE_PCI_1:
2063 2061 cfg |= PCIC_TOSHIBA_ICR_SRC;
2064 2062 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK);
2065 2063 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA;
2066 2064 ddi_put8(pcic->cfg_handle,
2067 2065 pcic->cfgaddr +
2068 2066 PCIC_TOSHIBA_INTR_CTL_REG, cfg);
2069 2067 break;
2070 2068 }
2071 2069 break;
2072 2070 case PCIC_O2MICRO_VENDOR:
2073 2071 cfg32 = ddi_get32(pcic->cfg_handle,
2074 2072 (uint32_t *)(pcic->cfgaddr +
2075 2073 PCIC_O2MICRO_MISC_CTL));
2076 2074 switch (pcic->pc_intr_mode) {
2077 2075 case PCIC_INTR_MODE_ISA:
2078 2076 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY |
2079 2077 PCIC_O2MICRO_INT_MOD_PCI);
2080 2078 ddi_put32(pcic->cfg_handle,
2081 2079 (uint32_t *)(pcic->cfgaddr +
2082 2080 PCIC_O2MICRO_MISC_CTL),
2083 2081 cfg32);
2084 2082 cfg = ddi_get8(pcic->cfg_handle,
2085 2083 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
2086 2084 cfg |= PCIC_FUN_INT_MOD_ISA;
2087 2085 ddi_put8(pcic->cfg_handle,
2088 2086 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
2089 2087 cfg);
2090 2088 break;
2091 2089 case PCIC_INTR_MODE_PCI_1:
2092 2090 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY;
2093 2091 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI;
2094 2092 ddi_put32(pcic->cfg_handle,
2095 2093 (uint32_t *)(pcic->cfgaddr +
2096 2094 PCIC_O2MICRO_MISC_CTL),
2097 2095 cfg32);
2098 2096 break;
2099 2097 }
2100 2098 break;
2101 2099 case PCIC_RICOH_VENDOR:
2102 2100 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) {
2103 2101 cfg16 = ddi_get16(pcic->cfg_handle,
2104 2102 (uint16_t *)(pcic->cfgaddr +
2105 2103 PCIC_RICOH_MISC_CTL_2));
2106 2104 cfg16 |= (PCIC_RICOH_CSC_INT_MOD |
2107 2105 PCIC_RICOH_FUN_INT_MOD);
2108 2106 ddi_put16(pcic->cfg_handle,
2109 2107 (uint16_t *)(pcic->cfgaddr +
2110 2108 PCIC_RICOH_MISC_CTL_2),
2111 2109 cfg16);
2112 2110
2113 2111 cfg16 = ddi_get16(pcic->cfg_handle,
2114 2112 (uint16_t *)(pcic->cfgaddr +
2115 2113 PCIC_RICOH_MISC_CTL));
2116 2114 cfg16 |= PCIC_RICOH_SIRQ_EN;
2117 2115 ddi_put16(pcic->cfg_handle,
2118 2116 (uint16_t *)(pcic->cfgaddr +
2119 2117 PCIC_RICOH_MISC_CTL),
2120 2118 cfg16);
2121 2119
2122 2120 cfg = ddi_get8(pcic->cfg_handle,
2123 2121 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
2124 2122 cfg |= PCIC_FUN_INT_MOD_ISA;
2125 2123 ddi_put8(pcic->cfg_handle,
2126 2124 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
2127 2125 cfg);
2128 2126 }
2129 2127 break;
2130 2128 default:
2131 2129 break;
2132 2130 } /* switch */
2133 2131
2134 2132 /*
2135 2133 * The default value in the EEPROM (loaded on reset) for
2136 2134 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that
2137 2135 * MFUNC0 is connected to INTA, and MFUNC1 is connected to
2138 2136 * INTB. This applies to all TI CardBus controllers.
2139 2137 */
2140 2138 if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID &&
2141 2139 pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) {
2142 2140 value = ddi_get32(pcic->cfg_handle,
2143 2141 (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG));
2144 2142 value &= ~0xff;
2145 2143 ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr +
2146 2144 PCIC_MFROUTE_REG), value|PCIC_TI_MFUNC_SEL);
2147 2145 }
2148 2146
2149 2147 /* setup general card status change interrupt */
2150 2148 switch (pcic->pc_type) {
2151 2149 case PCIC_TI_PCI1225:
2152 2150 case PCIC_TI_PCI1221:
2153 2151 case PCIC_TI_PCI1031:
2154 2152 case PCIC_TI_PCI1520:
2155 2153 case PCIC_TI_PCI1410:
2156 2154 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT,
2157 2155 PCIC_CHANGE_DEFAULT);
2158 2156 break;
2159 2157 default:
2160 2158 if (pcic->pc_intr_mode ==
2161 2159 PCIC_INTR_MODE_PCI_1) {
2162 2160 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT,
2163 2161 PCIC_CHANGE_DEFAULT);
2164 2162 break;
2165 2163 } else {
2166 2164 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT,
2167 2165 PCIC_CHANGE_DEFAULT |
2168 2166 (pcic->pc_sockets[i].pcs_smi << 4));
2169 2167 break;
2170 2168 }
2171 2169 }
2172 2170
2173 2171 pcic->pc_flags |= PCF_INTRENAB;
2174 2172
2175 2173 /* take card out of RESET */
2176 2174 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET);
2177 2175 /* turn power off and let CS do this */
2178 2176 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0);
2179 2177
2180 2178 /* final chip specific initialization */
2181 2179 switch (pcic->pc_type) {
2182 2180 case PCIC_VADEM:
2183 2181 pcic_putb(pcic, i, PCIC_VG_CONTROL,
2184 2182 PCIC_VC_DELAYENABLE);
2185 2183 pcic->pc_flags |= PCF_DEBOUNCE;
2186 2184 /* FALLTHROUGH */
2187 2185 case PCIC_I82365SL:
2188 2186 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL,
2189 2187 PCIC_GC_CSC_WRITE);
2190 2188 /* clear any pending interrupts */
2191 2189 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE);
2192 2190 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value);
2193 2191 break;
2194 2192 /* The 82092 uses PCI config space to enable interrupts */
2195 2193 case PCIC_INTEL_i82092:
2196 2194 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI,
2197 2195 PCIC_82092_INT_ENABLE);
2198 2196 break;
2199 2197 case PCIC_CL_PD6729:
2200 2198 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) {
2201 2199 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2);
2202 2200 pcic_putb(pcic, i, PCIC_MISC_CTL_2,
2203 2201 value | PCIC_CL_TIMER_CLK_DIV);
2204 2202 }
2205 2203 break;
2206 2204 } /* switch */
2207 2205
2208 2206 #if defined(PCIC_DEBUG)
2209 2207 if (pcic_debug)
2210 2208 cmn_err(CE_CONT,
2211 2209 "socket %d value=%x, flags = %x (%s)\n",
2212 2210 i, value, pcic->pc_sockets[i].pcs_flags,
2213 2211 (pcic->pc_sockets[i].pcs_flags &
2214 2212 PCS_CARD_PRESENT) ?
2215 2213 "card present" : "no card");
2216 2214 #endif
2217 2215 }
2218 2216 }
2219 2217
2220 2218 /*
2221 2219 * pcic_intr(caddr_t, caddr_t)
2222 2220 * interrupt handler for the PCIC style adapter
2223 2221 * handles all basic interrupts and also checks
2224 2222 * for status changes and notifies the nexus if
2225 2223 * necessary
2226 2224 *
2227 2225 * On PCI bus adapters, also handles all card
2228 2226 * IO interrupts.
2229 2227 */
2230 2228 /*ARGSUSED*/
2231 2229 uint32_t
2232 2230 pcic_intr(caddr_t arg1, caddr_t arg2)
2233 2231 {
2234 2232 pcicdev_t *pcic = (pcicdev_t *)arg1;
2235 2233 int value = 0, i, ret = DDI_INTR_UNCLAIMED;
2236 2234 uint8_t status;
2237 2235 uint_t io_ints;
2238 2236
2239 2237 #if defined(PCIC_DEBUG)
2240 2238 pcic_err(pcic->dip, 0xf,
2241 2239 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x"
2242 2240 " pc_numsockets=%d \n",
2243 2241 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets);
2244 2242 #endif
2245 2243
2246 2244 if (!(pcic->pc_flags & PCF_ATTACHED))
2247 2245 return (DDI_INTR_UNCLAIMED);
2248 2246
2249 2247 mutex_enter(&pcic->intr_lock);
2250 2248
2251 2249 if (pcic->pc_flags & PCF_SUSPENDED) {
2252 2250 mutex_exit(&pcic->intr_lock);
2253 2251 return (ret);
2254 2252 }
2255 2253
2256 2254 /*
2257 2255 * need to change to only ACK and touch the slot that
2258 2256 * actually caused the interrupt. Currently everything
2259 2257 * is acked
2260 2258 *
2261 2259 * we need to look at all known sockets to determine
2262 2260 * what might have happened, so step through the list
2263 2261 * of them
2264 2262 */
2265 2263
2266 2264 /*
2267 2265 * Set the bitmask for IO interrupts to initially include all sockets
2268 2266 */
2269 2267 io_ints = (1 << pcic->pc_numsockets) - 1;
2270 2268
2271 2269 for (i = 0; i < pcic->pc_numsockets; i++) {
2272 2270 int card_type;
2273 2271 pcic_socket_t *sockp;
2274 2272 int value_cb = 0;
2275 2273
2276 2274 sockp = &pcic->pc_sockets[i];
2277 2275 /* get the socket's I/O addresses */
2278 2276
2279 2277 if (sockp->pcs_flags & PCS_WAITING) {
2280 2278 io_ints &= ~(1 << i);
2281 2279 continue;
2282 2280 }
2283 2281
2284 2282 if (sockp->pcs_flags & PCS_CARD_IO)
2285 2283 card_type = IF_IO;
2286 2284 else
2287 2285 card_type = IF_MEMORY;
2288 2286
2289 2287 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA)
2290 2288 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT);
2291 2289
2292 2290 value = pcic_change(pcic, i);
2293 2291
2294 2292 if ((value != 0) || (value_cb != 0)) {
2295 2293 int x = pcic->pc_cb_arg;
2296 2294
2297 2295 ret = DDI_INTR_CLAIMED;
2298 2296
2299 2297 #if defined(PCIC_DEBUG)
2300 2298 pcic_err(pcic->dip, 0x9,
2301 2299 "card_type = %d, value_cb = 0x%x\n",
2302 2300 card_type,
2303 2301 value_cb ? value_cb :
2304 2302 pcic_getcb(pcic, CB_STATUS_EVENT));
2305 2303 if (pcic_debug)
2306 2304 cmn_err(CE_CONT,
2307 2305 "\tchange on socket %d (%x)\n", i,
2308 2306 value);
2309 2307 #endif
2310 2308 /* find out what happened */
2311 2309 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS);
2312 2310
2313 2311 /* acknowledge the interrupt */
2314 2312 if (value_cb)
2315 2313 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb);
2316 2314
2317 2315 if (value)
2318 2316 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE,
2319 2317 value);
2320 2318
2321 2319 if (pcic->pc_callback == NULL) {
2322 2320 /* if not callback handler, nothing to do */
2323 2321 continue;
2324 2322 }
2325 2323
2326 2324 /* Card Detect */
2327 2325 if (value & PCIC_CD_DETECT ||
2328 2326 value_cb & CB_PS_CCDMASK) {
2329 2327 uint8_t irq;
2330 2328 #if defined(PCIC_DEBUG)
2331 2329 if (pcic_debug)
2332 2330 cmn_err(CE_CONT,
2333 2331 "\tcd_detect: status=%x,"
2334 2332 " flags=%x\n",
2335 2333 status, sockp->pcs_flags);
2336 2334 #else
2337 2335 #ifdef lint
2338 2336 if (status == 0)
2339 2337 status++;
2340 2338 #endif
2341 2339 #endif
2342 2340 /*
2343 2341 * Turn off all interrupts for this socket here.
2344 2342 */
2345 2343 irq = pcic_getb(pcic, sockp->pcs_socket,
2346 2344 PCIC_MANAGEMENT_INT);
2347 2345 irq &= ~PCIC_CHANGE_MASK;
2348 2346 pcic_putb(pcic, sockp->pcs_socket,
2349 2347 PCIC_MANAGEMENT_INT, irq);
2350 2348
2351 2349 pcic_putcb(pcic, CB_STATUS_MASK, 0x0);
2352 2350
2353 2351 /*
2354 2352 * Put the socket in debouncing state so that
2355 2353 * the leaf driver won't receive interrupts.
2356 2354 * Crucial for handling surprise-removal.
2357 2355 */
2358 2356 sockp->pcs_flags |= PCS_DEBOUNCING;
2359 2357
2360 2358 if (!sockp->pcs_cd_softint_flg) {
2361 2359 sockp->pcs_cd_softint_flg = 1;
2362 2360 (void) ddi_intr_trigger_softint(
2363 2361 sockp->pcs_cd_softint_hdl, NULL);
2364 2362 }
2365 2363
2366 2364 io_ints &= ~(1 << i);
2367 2365 } /* PCIC_CD_DETECT */
2368 2366
2369 2367 /* Ready/Change Detect */
2370 2368 sockp->pcs_state ^= SBM_RDYBSY;
2371 2369 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) {
2372 2370 sockp->pcs_flags |= PCS_READY;
2373 2371 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i);
2374 2372 }
2375 2373
2376 2374 /* Battery Warn Detect */
2377 2375 if (card_type == IF_MEMORY &&
2378 2376 value & PCIC_BW_DETECT &&
2379 2377 !(sockp->pcs_state & SBM_BVD2)) {
2380 2378 sockp->pcs_state |= SBM_BVD2;
2381 2379 PC_CALLBACK(pcic->dip, x,
2382 2380 PCE_CARD_BATTERY_WARN, i);
2383 2381 }
2384 2382
2385 2383 /* Battery Dead Detect */
2386 2384 if (value & PCIC_BD_DETECT) {
2387 2385 /*
2388 2386 * need to work out event if RI not enabled
2389 2387 * and card_type == IF_IO
2390 2388 */
2391 2389 if (card_type == IF_MEMORY &&
2392 2390 !(sockp->pcs_state & SBM_BVD1)) {
2393 2391 sockp->pcs_state |= SBM_BVD1;
2394 2392 PC_CALLBACK(pcic->dip, x,
2395 2393 PCE_CARD_BATTERY_DEAD,
2396 2394 i);
2397 2395 } else {
2398 2396 /*
2399 2397 * information in pin replacement
2400 2398 * register if one is available
2401 2399 */
2402 2400 PC_CALLBACK(pcic->dip, x,
2403 2401 PCE_CARD_STATUS_CHANGE,
2404 2402 i);
2405 2403 } /* IF_MEMORY */
2406 2404 } /* PCIC_BD_DETECT */
2407 2405 } /* if pcic_change */
2408 2406 /*
2409 2407 * for any controllers that we can detect whether a socket
2410 2408 * had an interrupt for the PC Card, we should sort that out
2411 2409 * here.
2412 2410 */
2413 2411 } /* for pc_numsockets */
2414 2412
2415 2413 /*
2416 2414 * If we're on a PCI bus, we may need to cycle through each IO
2417 2415 * interrupt handler that is registered since they all
2418 2416 * share the same interrupt line.
2419 2417 */
2420 2418
2421 2419
2422 2420 #if defined(PCIC_DEBUG)
2423 2421 pcic_err(pcic->dip, 0xf,
2424 2422 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n",
2425 2423 pcic->pc_intr_mode, pcic->pc_type, io_ints);
2426 2424 #endif
2427 2425
2428 2426 if (io_ints) {
2429 2427 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED)
2430 2428 ret = DDI_INTR_CLAIMED;
2431 2429 }
2432 2430
2433 2431 mutex_exit(&pcic->intr_lock);
2434 2432
2435 2433 #if defined(PCIC_DEBUG)
2436 2434 pcic_err(pcic->dip, 0xf,
2437 2435 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n",
2438 2436 ret, value, DDI_INTR_CLAIMED);
2439 2437 #endif
2440 2438
2441 2439 return (ret);
2442 2440 }
2443 2441
2444 2442 /*
2445 2443 * pcic_change()
2446 2444 * check to see if this socket had a change in state
2447 2445 * by checking the status change register
2448 2446 */
2449 2447 static int
2450 2448 pcic_change(pcicdev_t *pcic, int socket)
2451 2449 {
2452 2450 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE));
2453 2451 }
2454 2452
2455 2453 /*
2456 2454 * pcic_do_io_intr - calls client interrupt handlers
2457 2455 */
2458 2456 static int
2459 2457 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets)
2460 2458 {
2461 2459 inthandler_t *tmp;
2462 2460 int ret = DDI_INTR_UNCLAIMED;
2463 2461
2464 2462 #if defined(PCIC_DEBUG)
2465 2463 pcic_err(pcic->dip, 0xf,
2466 2464 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n",
2467 2465 (void *)pcic, (int)sockets, (void *)pcic->irq_top);
2468 2466 #endif
2469 2467
2470 2468 if (pcic->irq_top != NULL) {
2471 2469 tmp = pcic->irq_current;
2472 2470
2473 2471 do {
2474 2472 int cur = pcic->irq_current->socket;
2475 2473 pcic_socket_t *sockp =
2476 2474 &pcic->pc_sockets[cur];
2477 2475
2478 2476 #if defined(PCIC_DEBUG)
2479 2477 pcic_err(pcic->dip, 0xf,
2480 2478 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n",
2481 2479 sockp->pcs_flags, PCS_CARD_PRESENT);
2482 2480 pcic_err(pcic->dip, 0xf,
2483 2481 "\t sockets=%d cur=%d intr=%p arg1=%p "
2484 2482 "arg2=%p\n",
2485 2483 sockets, cur, (void *)pcic->irq_current->intr,
2486 2484 pcic->irq_current->arg1,
2487 2485 pcic->irq_current->arg2);
2488 2486 #endif
2489 2487 if ((sockp->pcs_flags & PCS_CARD_PRESENT) &&
2490 2488 !(sockp->pcs_flags & PCS_DEBOUNCING) &&
2491 2489 (sockets & (1 << cur))) {
2492 2490
2493 2491 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1,
2494 2492 pcic->irq_current->arg2) == DDI_INTR_CLAIMED)
2495 2493 ret = DDI_INTR_CLAIMED;
2496 2494
2497 2495 #if defined(PCIC_DEBUG)
2498 2496 pcic_err(pcic->dip, 0xf,
2499 2497 "\t ret=%d DDI_INTR_CLAIMED=%d\n",
2500 2498 ret, DDI_INTR_CLAIMED);
2501 2499 #endif
2502 2500 }
2503 2501
2504 2502
2505 2503 if ((pcic->irq_current = pcic->irq_current->next) == NULL)
2506 2504 pcic->irq_current = pcic->irq_top;
2507 2505
2508 2506 } while (pcic->irq_current != tmp);
2509 2507
2510 2508 if ((pcic->irq_current = pcic->irq_current->next) == NULL)
2511 2509 pcic->irq_current = pcic->irq_top;
2512 2510
2513 2511 } else {
2514 2512 ret = DDI_INTR_UNCLAIMED;
2515 2513 }
2516 2514
2517 2515 #if defined(PCIC_DEBUG)
2518 2516 pcic_err(pcic->dip, 0xf,
2519 2517 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n",
2520 2518 ret, DDI_INTR_CLAIMED);
2521 2519 #endif
2522 2520
2523 2521 return (ret);
2524 2522
2525 2523 }
2526 2524
2527 2525 /*
2528 2526 * pcic_inquire_adapter()
2529 2527 * SocketServices InquireAdapter function
2530 2528 * get characteristics of the physical adapter
2531 2529 */
2532 2530 /*ARGSUSED*/
2533 2531 static int
2534 2532 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config)
2535 2533 {
2536 2534 anp_t *anp = ddi_get_driver_private(dip);
2537 2535 pcicdev_t *pcic = anp->an_private;
2538 2536
2539 2537 config->NumSockets = pcic->pc_numsockets;
2540 2538 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK;
2541 2539 config->NumEDCs = 0;
2542 2540 config->AdpCaps = 0;
2543 2541 config->ActiveHigh = 0;
2544 2542 config->ActiveLow = PCIC_AVAIL_IRQS;
2545 2543 config->NumPower = pcic->pc_numpower;
2546 2544 config->power_entry = pcic->pc_power; /* until we resolve this */
2547 2545 #if defined(PCIC_DEBUG)
2548 2546 if (pcic_debug) {
2549 2547 cmn_err(CE_CONT, "pcic_inquire_adapter:\n");
2550 2548 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets);
2551 2549 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows);
2552 2550 }
2553 2551 #endif
2554 2552 config->ResourceFlags = 0;
2555 2553 switch (pcic->pc_intr_mode) {
2556 2554 case PCIC_INTR_MODE_PCI_1:
2557 2555 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS |
2558 2556 RES_IRQ_SHAREABLE;
2559 2557 break;
2560 2558 }
2561 2559 return (SUCCESS);
2562 2560 }
2563 2561
2564 2562 /*
2565 2563 * pcic_callback()
2566 2564 * The PCMCIA nexus calls us via this function
2567 2565 * in order to set the callback function we are
2568 2566 * to call the nexus with
2569 2567 */
2570 2568 /*ARGSUSED*/
2571 2569 static int
2572 2570 pcic_callback(dev_info_t *dip, int (*handler)(), int arg)
2573 2571 {
2574 2572 anp_t *anp = ddi_get_driver_private(dip);
2575 2573 pcicdev_t *pcic = anp->an_private;
2576 2574
2577 2575 if (handler != NULL) {
2578 2576 pcic->pc_callback = handler;
2579 2577 pcic->pc_cb_arg = arg;
2580 2578 pcic->pc_flags |= PCF_CALLBACK;
2581 2579 } else {
2582 2580 pcic->pc_callback = NULL;
2583 2581 pcic->pc_cb_arg = 0;
2584 2582 pcic->pc_flags &= ~PCF_CALLBACK;
2585 2583 }
2586 2584 /*
2587 2585 * we're now registered with the nexus
2588 2586 * it is acceptable to do callbacks at this point.
2589 2587 * don't call back from here though since it could block
2590 2588 */
2591 2589 return (PC_SUCCESS);
2592 2590 }
2593 2591
2594 2592 /*
2595 2593 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed)
2596 2594 * calculate the speed bits from the specified memory speed
2597 2595 * there may be more to do here
2598 2596 */
2599 2597
2600 2598 static int
2601 2599 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed)
2602 2600 {
2603 2601 uint32_t wspeed = 1; /* assume 1 wait state when unknown */
2604 2602 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK;
2605 2603
2606 2604 switch (pcic->pc_type) {
2607 2605 case PCIC_I82365SL:
2608 2606 case PCIC_VADEM:
2609 2607 case PCIC_VADEM_VG469:
2610 2608 default:
2611 2609 /* Intel chip wants it in waitstates */
2612 2610 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3;
2613 2611 if (speed <= wspeed)
2614 2612 wspeed = 0;
2615 2613 else if (speed <= (wspeed += mhztons(bspeed)))
2616 2614 wspeed = 1;
2617 2615 else if (speed <= (wspeed += mhztons(bspeed)))
2618 2616 wspeed = 2;
2619 2617 else
2620 2618 wspeed = 3;
2621 2619 wspeed <<= 6; /* put in right bit positions */
2622 2620 break;
2623 2621
2624 2622 case PCIC_INTEL_i82092:
2625 2623 wspeed = SYSMEM_82092_80NS;
2626 2624 if (speed > 80)
2627 2625 wspeed = SYSMEM_82092_100NS;
2628 2626 if (speed > 100)
2629 2627 wspeed = SYSMEM_82092_150NS;
2630 2628 if (speed > 150)
2631 2629 wspeed = SYSMEM_82092_200NS;
2632 2630 if (speed > 200)
2633 2631 wspeed = SYSMEM_82092_250NS;
2634 2632 if (speed > 250)
2635 2633 wspeed = SYSMEM_82092_600NS;
2636 2634 wspeed <<= 5; /* put in right bit positions */
2637 2635 break;
2638 2636
2639 2637 } /* switch */
2640 2638
2641 2639 return (wspeed);
2642 2640 }
2643 2641
2644 2642 /*
2645 2643 * These values are taken from the PC Card Standard Electrical Specification.
2646 2644 * Generally the larger value is taken if 2 are possible.
2647 2645 */
2648 2646 static struct pcic_card_times {
2649 2647 uint16_t cycle; /* Speed as found in the atribute space of he card. */
2650 2648 uint16_t setup; /* Corresponding address setup time. */
2651 2649 uint16_t width; /* Corresponding width, OE or WE. */
2652 2650 uint16_t hold; /* Corresponding data or address hold time. */
2653 2651 } pcic_card_times[] = {
2654 2652
2655 2653 /*
2656 2654 * Note: The rounded up times for 250, 200 & 150 have been increased
2657 2655 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi.
2658 2656 * See BugID 00663.
2659 2657 */
2660 2658
2661 2659 /*
2662 2660 * Rounded up times Original times from
2663 2661 * that add up to the the PCMCIA Spec.
2664 2662 * cycle time.
2665 2663 */
2666 2664 {600, 180, 370, 140}, /* 100, 300, 70 */
2667 2665 {400, 120, 300, 90}, /* Made this one up */
2668 2666 {250, 100, 190, 70}, /* 30, 150, 30 */
2669 2667 {200, 80, 170, 70}, /* 20, 120, 30 */
2670 2668 {150, 50, 110, 40}, /* 20, 80, 20 */
2671 2669 {100, 40, 80, 40}, /* 10, 60, 15 */
2672 2670 {0, 10, 60, 15} /* 10, 60, 15 */
2673 2671 };
2674 2672
2675 2673 /*
2676 2674 * pcic_set_cdtimers
2677 2675 * This is specific to several Cirrus Logic chips
2678 2676 */
2679 2677 static void
2680 2678 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset)
2681 2679 {
2682 2680 int cmd, set, rec, offset, clk_pulse;
2683 2681 struct pcic_card_times *ctp;
2684 2682
2685 2683 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1))
2686 2684 offset = 3;
2687 2685 else
2688 2686 offset = 0;
2689 2687
2690 2688 clk_pulse = mhztons(pcic->bus_speed);
2691 2689 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++)
2692 2690 ;
2693 2691
2694 2692 /*
2695 2693 * Add (clk_pulse/2) and an extra 1 to account for rounding errors.
2696 2694 */
2697 2695 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1;
2698 2696 if (set < 0)
2699 2697 set = 0;
2700 2698
2701 2699 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1;
2702 2700 if (cmd < 0)
2703 2701 cmd = 0;
2704 2702
2705 2703 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2;
2706 2704 if (rec < 0)
2707 2705 rec = 0;
2708 2706
2709 2707 #if defined(PCIC_DEBUG)
2710 2708 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n"
2711 2709 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n",
2712 2710 (unsigned)speed, offset == 3 ? 1 : 0,
2713 2711 ctp->cycle, clk_pulse, cmd, set, rec);
2714 2712 #endif
2715 2713
2716 2714 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd);
2717 2715 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set);
2718 2716 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec);
2719 2717 }
2720 2718
2721 2719 /*
2722 2720 * pcic_set_window
2723 2721 * essentially the same as the Socket Services specification
2724 2722 * We use socket and not adapter since they are identifiable
2725 2723 * but the rest is the same
2726 2724 *
2727 2725 * dip pcic driver's device information
2728 2726 * window parameters for the request
2729 2727 */
2730 2728 static int
2731 2729 pcic_set_window(dev_info_t *dip, set_window_t *window)
2732 2730 {
2733 2731 anp_t *anp = ddi_get_driver_private(dip);
2734 2732 pcicdev_t *pcic = anp->an_private;
2735 2733 int select;
2736 2734 int socket, pages, which, ret;
2737 2735 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket];
2738 2736 ra_return_t res;
2739 2737 ndi_ra_request_t req;
2740 2738 uint32_t base = window->base;
2741 2739
2742 2740 #if defined(PCIC_DEBUG)
2743 2741 if (pcic_debug) {
2744 2742 cmn_err(CE_CONT, "pcic_set_window: entered\n");
2745 2743 cmn_err(CE_CONT,
2746 2744 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n",
2747 2745 window->window, window->socket, window->WindowSize,
2748 2746 window->speed);
2749 2747 cmn_err(CE_CONT,
2750 2748 "\tbase=%x, state=%x\n", (unsigned)window->base,
2751 2749 (unsigned)window->state);
2752 2750 }
2753 2751 #endif
2754 2752
2755 2753 /*
2756 2754 * do some basic sanity checking on what we support
2757 2755 * we don't do paged mode
2758 2756 */
2759 2757 if (window->state & WS_PAGED) {
2760 2758 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n");
2761 2759 return (BAD_ATTRIBUTE);
2762 2760 }
2763 2761
2764 2762 /*
2765 2763 * we don't care about previous mappings.
2766 2764 * Card Services will deal with that so don't
2767 2765 * even check
2768 2766 */
2769 2767
2770 2768 socket = window->socket;
2771 2769
2772 2770 if (!(window->state & WS_IO)) {
2773 2771 int win, tmp;
2774 2772 pcs_memwin_t *memp;
2775 2773 #if defined(PCIC_DEBUG)
2776 2774 if (pcic_debug)
2777 2775 cmn_err(CE_CONT, "\twindow type is memory\n");
2778 2776 #endif
2779 2777 /* this is memory window mapping */
2780 2778 win = window->window % PCIC_NUMWINSOCK;
2781 2779 tmp = window->window / PCIC_NUMWINSOCK;
2782 2780
2783 2781 /* only windows 2-6 can do memory mapping */
2784 2782 if (tmp != window->socket || win < PCIC_IOWINDOWS) {
2785 2783 cmn_err(CE_CONT,
2786 2784 "\tattempt to map to non-mem window\n");
2787 2785 return (BAD_WINDOW);
2788 2786 }
2789 2787
2790 2788 if (window->WindowSize == 0)
2791 2789 window->WindowSize = MEM_MIN;
2792 2790 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) {
2793 2791 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n");
2794 2792 return (BAD_SIZE);
2795 2793 }
2796 2794
2797 2795 mutex_enter(&pcic->pc_lock); /* protect the registers */
2798 2796
2799 2797 memp = &sockp->pcs_windows[win].mem;
2800 2798 memp->pcw_speed = window->speed;
2801 2799
2802 2800 win -= PCIC_IOWINDOWS; /* put in right range */
2803 2801
2804 2802 if (window->WindowSize != memp->pcw_len)
2805 2803 which = memp->pcw_len;
2806 2804 else
2807 2805 which = 0;
2808 2806
2809 2807 if (window->state & WS_ENABLED) {
2810 2808 uint32_t wspeed;
2811 2809 #if defined(PCIC_DEBUG)
2812 2810 if (pcic_debug) {
2813 2811 cmn_err(CE_CONT,
2814 2812 "\tbase=%x, win=%d\n", (unsigned)base,
2815 2813 win);
2816 2814 if (which)
2817 2815 cmn_err(CE_CONT,
2818 2816 "\tneed to remap window\n");
2819 2817 }
2820 2818 #endif
2821 2819
2822 2820 if (which && (memp->pcw_status & PCW_MAPPED)) {
2823 2821 ddi_regs_map_free(&memp->pcw_handle);
2824 2822 res.ra_addr_lo = memp->pcw_base;
2825 2823 res.ra_len = memp->pcw_len;
2826 2824 (void) pcmcia_free_mem(memp->res_dip, &res);
2827 2825 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED);
2828 2826 memp->pcw_hostmem = NULL;
2829 2827 memp->pcw_base = NULL;
2830 2828 memp->pcw_len = 0;
2831 2829 }
2832 2830
2833 2831 which = window->WindowSize >> PAGE_SHIFT;
2834 2832
2835 2833 if (!(memp->pcw_status & PCW_MAPPED)) {
2836 2834 ret = 0;
2837 2835
2838 2836 memp->pcw_base = base;
2839 2837 bzero(&req, sizeof (req));
2840 2838 req.ra_len = which << PAGE_SHIFT;
2841 2839 req.ra_addr = (uint64_t)memp->pcw_base;
2842 2840 req.ra_boundbase = pcic->pc_base;
2843 2841 req.ra_boundlen = pcic->pc_bound;
2844 2842 req.ra_flags = (memp->pcw_base ?
2845 2843 NDI_RA_ALLOC_SPECIFIED : 0) |
2846 2844 NDI_RA_ALLOC_BOUNDED;
2847 2845 req.ra_align_mask =
2848 2846 (PAGESIZE - 1) | (PCIC_PAGE - 1);
2849 2847 #if defined(PCIC_DEBUG)
2850 2848 pcic_err(dip, 8,
2851 2849 "\tlen 0x%"PRIx64
2852 2850 "addr 0x%"PRIx64"bbase 0x%"PRIx64
2853 2851 " blen 0x%"PRIx64" flags 0x%x"
2854 2852 " algn 0x%"PRIx64"\n",
2855 2853 req.ra_len, req.ra_addr,
2856 2854 req.ra_boundbase,
2857 2855 req.ra_boundlen, req.ra_flags,
2858 2856 req.ra_align_mask);
2859 2857 #endif
2860 2858
2861 2859 ret = pcmcia_alloc_mem(dip, &req, &res,
2862 2860 &memp->res_dip);
2863 2861 if (ret == DDI_FAILURE) {
2864 2862 mutex_exit(&pcic->pc_lock);
2865 2863 cmn_err(CE_WARN,
2866 2864 "\tpcmcia_alloc_mem() failed\n");
2867 2865 return (BAD_SIZE);
2868 2866 }
2869 2867 memp->pcw_base = res.ra_addr_lo;
2870 2868 base = memp->pcw_base;
2871 2869
2872 2870 #if defined(PCIC_DEBUG)
2873 2871 if (pcic_debug)
2874 2872 cmn_err(CE_CONT,
2875 2873 "\tsetwindow: new base=%x\n",
2876 2874 (unsigned)memp->pcw_base);
2877 2875 #endif
2878 2876 memp->pcw_len = window->WindowSize;
2879 2877
2880 2878 which = pcmcia_map_reg(pcic->dip,
2881 2879 window->child,
2882 2880 &res,
2883 2881 (uint32_t)(window->state &
2884 2882 0xffff) |
2885 2883 (window->socket << 16),
2886 2884 (caddr_t *)&memp->pcw_hostmem,
2887 2885 &memp->pcw_handle,
2888 2886 &window->attr, NULL);
2889 2887
2890 2888 if (which != DDI_SUCCESS) {
2891 2889
2892 2890 cmn_err(CE_WARN, "\tpcmcia_map_reg() "
2893 2891 "failed\n");
2894 2892
2895 2893 res.ra_addr_lo = memp->pcw_base;
2896 2894 res.ra_len = memp->pcw_len;
2897 2895 (void) pcmcia_free_mem(memp->res_dip,
2898 2896 &res);
2899 2897
2900 2898 mutex_exit(&pcic->pc_lock);
2901 2899
2902 2900 return (BAD_WINDOW);
2903 2901 }
2904 2902 memp->pcw_status |= PCW_MAPPED;
2905 2903 #if defined(PCIC_DEBUG)
2906 2904 if (pcic_debug)
2907 2905 cmn_err(CE_CONT,
2908 2906 "\tmap=%x, hostmem=%p\n",
2909 2907 which,
2910 2908 (void *)memp->pcw_hostmem);
2911 2909 #endif
2912 2910 } else {
2913 2911 base = memp->pcw_base;
2914 2912 }
2915 2913
2916 2914 /* report the handle back to caller */
2917 2915 window->handle = memp->pcw_handle;
2918 2916
2919 2917 #if defined(PCIC_DEBUG)
2920 2918 if (pcic_debug) {
2921 2919 cmn_err(CE_CONT,
2922 2920 "\twindow mapped to %x@%x len=%d\n",
2923 2921 (unsigned)window->base,
2924 2922 (unsigned)memp->pcw_base,
2925 2923 memp->pcw_len);
2926 2924 }
2927 2925 #endif
2928 2926
2929 2927 /* find the register set offset */
2930 2928 select = win * PCIC_MEM_1_OFFSET;
2931 2929 #if defined(PCIC_DEBUG)
2932 2930 if (pcic_debug)
2933 2931 cmn_err(CE_CONT, "\tselect=%x\n", select);
2934 2932 #endif
2935 2933
2936 2934 /*
2937 2935 * at this point, the register window indicator has
2938 2936 * been converted to be an offset from the first
2939 2937 * set of registers that are used for programming
2940 2938 * the window mapping and the offset used to select
2941 2939 * the correct set of registers to access the
2942 2940 * specified socket. This allows basing everything
2943 2941 * off the _0 window
2944 2942 */
2945 2943
2946 2944 /* map the physical page base address */
2947 2945 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0;
2948 2946 which |= (window->speed <= MEM_SPEED_MIN) ?
2949 2947 SYSMEM_ZERO_WAIT : 0;
2950 2948
2951 2949 /* need to select register set */
2952 2950 select = PCIC_MEM_1_OFFSET * win;
2953 2951
2954 2952 pcic_putb(pcic, socket,
2955 2953 PCIC_SYSMEM_0_STARTLOW + select,
2956 2954 SYSMEM_LOW(base));
2957 2955 pcic_putb(pcic, socket,
2958 2956 PCIC_SYSMEM_0_STARTHI + select,
2959 2957 SYSMEM_HIGH(base) | which);
2960 2958
2961 2959 /*
2962 2960 * Some adapters can decode window addresses greater
2963 2961 * than 16-bits worth, so handle them here.
2964 2962 */
2965 2963 switch (pcic->pc_type) {
2966 2964 case PCIC_INTEL_i82092:
2967 2965 pcic_putb(pcic, socket,
2968 2966 PCIC_82092_CPAGE,
2969 2967 SYSMEM_EXT(base));
2970 2968 break;
2971 2969 case PCIC_CL_PD6729:
2972 2970 case PCIC_CL_PD6730:
2973 2971 clext_reg_write(pcic, socket,
2974 2972 PCIC_CLEXT_MMAP0_UA + win,
2975 2973 SYSMEM_EXT(base));
2976 2974 break;
2977 2975 case PCIC_TI_PCI1130:
2978 2976 /*
2979 2977 * Note that the TI chip has one upper byte
2980 2978 * per socket so all windows get bound to a
2981 2979 * 16MB segment. This must be detected and
2982 2980 * handled appropriately. We can detect that
2983 2981 * it is done by seeing if the pc_base has
2984 2982 * changed and changing when the register
2985 2983 * is first set. This will force the bounds
2986 2984 * to be correct.
2987 2985 */
2988 2986 if (pcic->pc_bound == 0xffffffff) {
2989 2987 pcic_putb(pcic, socket,
2990 2988 PCIC_TI_WINDOW_PAGE_PCI,
2991 2989 SYSMEM_EXT(base));
2992 2990 pcic->pc_base = SYSMEM_EXT(base) << 24;
2993 2991 pcic->pc_bound = 0x1000000;
2994 2992 }
2995 2993 break;
2996 2994 case PCIC_TI_PCI1031:
2997 2995 case PCIC_TI_PCI1131:
2998 2996 case PCIC_TI_PCI1250:
2999 2997 case PCIC_TI_PCI1225:
3000 2998 case PCIC_TI_PCI1221:
3001 2999 case PCIC_SMC_34C90:
3002 3000 case PCIC_CL_PD6832:
3003 3001 case PCIC_RICOH_RL5C466:
3004 3002 case PCIC_TI_PCI1410:
3005 3003 case PCIC_ENE_1410:
3006 3004 case PCIC_TI_PCI1510:
3007 3005 case PCIC_TI_PCI1520:
3008 3006 case PCIC_O2_OZ6912:
3009 3007 case PCIC_TI_PCI1420:
3010 3008 case PCIC_ENE_1420:
3011 3009 case PCIC_TI_VENDOR:
3012 3010 case PCIC_TOSHIBA_TOPIC100:
3013 3011 case PCIC_TOSHIBA_TOPIC95:
3014 3012 case PCIC_TOSHIBA_VENDOR:
3015 3013 case PCIC_RICOH_VENDOR:
3016 3014 case PCIC_O2MICRO_VENDOR:
3017 3015 pcic_putb(pcic, socket,
3018 3016 PCIC_YENTA_MEM_PAGE + win,
3019 3017 SYSMEM_EXT(base));
3020 3018 break;
3021 3019 default:
3022 3020 cmn_err(CE_NOTE, "pcic_set_window: unknown "
3023 3021 "cardbus vendor:0x%X\n",
3024 3022 pcic->pc_type);
3025 3023 pcic_putb(pcic, socket,
3026 3024 PCIC_YENTA_MEM_PAGE + win,
3027 3025 SYSMEM_EXT(base));
3028 3026
3029 3027 break;
3030 3028 } /* switch */
3031 3029
3032 3030 /*
3033 3031 * specify the length of the mapped range
3034 3032 * we convert to pages (rounding up) so that
3035 3033 * the hardware gets the right thing
3036 3034 */
3037 3035 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE;
3038 3036
3039 3037 /*
3040 3038 * Setup this window's timing.
3041 3039 */
3042 3040 switch (pcic->pc_type) {
3043 3041 case PCIC_CL_PD6729:
3044 3042 case PCIC_CL_PD6730:
3045 3043 case PCIC_CL_PD6710:
3046 3044 case PCIC_CL_PD6722:
3047 3045 wspeed = SYSMEM_CLTIMER_SET_0;
3048 3046 pcic_set_cdtimers(pcic, socket,
3049 3047 window->speed,
3050 3048 wspeed);
3051 3049 break;
3052 3050
3053 3051 case PCIC_INTEL_i82092:
3054 3052 default:
3055 3053 wspeed = pcic_calc_speed(pcic, window->speed);
3056 3054 break;
3057 3055 } /* switch */
3058 3056
3059 3057 #if defined(PCIC_DEBUG)
3060 3058 if (pcic_debug)
3061 3059 cmn_err(CE_CONT,
3062 3060 "\twindow %d speed bits = %x for "
3063 3061 "%dns\n",
3064 3062 win, (unsigned)wspeed, window->speed);
3065 3063 #endif
3066 3064
3067 3065 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select,
3068 3066 SYSMEM_LOW(base +
3069 3067 (pages * PCIC_PAGE)-1));
3070 3068
3071 3069 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1);
3072 3070 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select,
3073 3071 wspeed);
3074 3072
3075 3073 /*
3076 3074 * now map the card's memory pages - we start with page
3077 3075 * 0
3078 3076 * we also default to AM -- set page might change it
3079 3077 */
3080 3078 base = memp->pcw_base;
3081 3079 pcic_putb(pcic, socket,
3082 3080 PCIC_CARDMEM_0_LOW + select,
3083 3081 CARDMEM_LOW(0 - (uint32_t)base));
3084 3082
3085 3083 pcic_putb(pcic, socket,
3086 3084 PCIC_CARDMEM_0_HI + select,
3087 3085 CARDMEM_HIGH(0 - (uint32_t)base) |
3088 3086 CARDMEM_REG_ACTIVE);
3089 3087
3090 3088 /*
3091 3089 * enable the window even though redundant
3092 3090 * and SetPage may do it again.
3093 3091 */
3094 3092 select = pcic_getb(pcic, socket,
3095 3093 PCIC_MAPPING_ENABLE);
3096 3094 select |= SYSMEM_WINDOW(win);
3097 3095 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select);
3098 3096 memp->pcw_offset = 0;
3099 3097 memp->pcw_status |= PCW_ENABLED;
3100 3098 } else {
3101 3099 /*
3102 3100 * not only do we unmap the memory, the
3103 3101 * window has been turned off.
3104 3102 */
3105 3103 if (which && memp->pcw_status & PCW_MAPPED) {
3106 3104 ddi_regs_map_free(&memp->pcw_handle);
3107 3105 res.ra_addr_lo = memp->pcw_base;
3108 3106 res.ra_len = memp->pcw_len;
3109 3107 (void) pcmcia_free_mem(memp->res_dip, &res);
3110 3108 memp->pcw_hostmem = NULL;
3111 3109 memp->pcw_status &= ~PCW_MAPPED;
3112 3110 }
3113 3111
3114 3112 /* disable current mapping */
3115 3113 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3116 3114 select &= ~SYSMEM_WINDOW(win);
3117 3115 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select);
3118 3116 memp->pcw_status &= ~PCW_ENABLED;
3119 3117 }
3120 3118 memp->pcw_len = window->WindowSize;
3121 3119 window->handle = memp->pcw_handle;
3122 3120 #if defined(PCIC_DEBUG)
3123 3121 if (pcic_debug)
3124 3122 xxdmp_all_regs(pcic, window->socket, -1);
3125 3123 #endif
3126 3124 } else {
3127 3125 /*
3128 3126 * This is a request for an IO window
3129 3127 */
3130 3128 int win, tmp;
3131 3129 pcs_iowin_t *winp;
3132 3130 /* I/O windows */
3133 3131 #if defined(PCIC_DEBUG)
3134 3132 if (pcic_debug)
3135 3133 cmn_err(CE_CONT, "\twindow type is I/O\n");
3136 3134 #endif
3137 3135
3138 3136 /* only windows 0 and 1 can do I/O */
3139 3137 win = window->window % PCIC_NUMWINSOCK;
3140 3138 tmp = window->window / PCIC_NUMWINSOCK;
3141 3139
3142 3140 if (win >= PCIC_IOWINDOWS || tmp != window->socket) {
3143 3141 cmn_err(CE_WARN,
3144 3142 "\twindow is out of range (%d)\n",
3145 3143 window->window);
3146 3144 return (BAD_WINDOW);
3147 3145 }
3148 3146
3149 3147 mutex_enter(&pcic->pc_lock); /* protect the registers */
3150 3148
3151 3149 winp = &sockp->pcs_windows[win].io;
3152 3150 winp->pcw_speed = window->speed;
3153 3151 if (window->WindowSize != 1 && window->WindowSize & 1) {
3154 3152 /* we don't want an odd-size window */
3155 3153 window->WindowSize++;
3156 3154 }
3157 3155 winp->pcw_len = window->WindowSize;
3158 3156
3159 3157 if (window->state & WS_ENABLED) {
3160 3158 if (winp->pcw_status & PCW_MAPPED) {
3161 3159 ddi_regs_map_free(&winp->pcw_handle);
3162 3160 res.ra_addr_lo = winp->pcw_base;
3163 3161 res.ra_len = winp->pcw_len;
3164 3162 (void) pcmcia_free_io(winp->res_dip, &res);
3165 3163 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED);
3166 3164 }
3167 3165
3168 3166 /*
3169 3167 * if the I/O address wasn't allocated, allocate
3170 3168 * it now. If it was allocated, it better
3171 3169 * be free to use.
3172 3170 * The winp->pcw_offset value is set and used
3173 3171 * later on if the particular adapter
3174 3172 * that we're running on has the ability
3175 3173 * to translate IO accesses to the card
3176 3174 * (such as some adapters in the Cirrus
3177 3175 * Logic family).
3178 3176 */
3179 3177 winp->pcw_offset = 0;
3180 3178
3181 3179 /*
3182 3180 * Setup the request parameters for the
3183 3181 * requested base and length. If
3184 3182 * we're on an adapter that has
3185 3183 * IO window offset registers, then
3186 3184 * we don't need a specific base
3187 3185 * address, just a length, and then
3188 3186 * we'll cause the correct IO address
3189 3187 * to be generated on the socket by
3190 3188 * setting up the IO window offset
3191 3189 * registers.
3192 3190 * For adapters that support this capability, we
3193 3191 * always use the IO window offset registers,
3194 3192 * even if the passed base/length would be in
3195 3193 * range.
3196 3194 */
3197 3195 base = window->base;
3198 3196 bzero(&req, sizeof (req));
3199 3197 req.ra_len = window->WindowSize;
3200 3198
3201 3199 req.ra_addr = (uint64_t)
3202 3200 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base);
3203 3201 req.ra_flags = (req.ra_addr) ?
3204 3202 NDI_RA_ALLOC_SPECIFIED : 0;
3205 3203
3206 3204 req.ra_flags |= NDI_RA_ALIGN_SIZE;
3207 3205 /* need to rethink this */
3208 3206 req.ra_boundbase = pcic->pc_iobase;
3209 3207 req.ra_boundlen = pcic->pc_iobound;
3210 3208 req.ra_flags |= NDI_RA_ALLOC_BOUNDED;
3211 3209
3212 3210 #if defined(PCIC_DEBUG)
3213 3211 pcic_err(dip, 8,
3214 3212 "\tlen 0x%"PRIx64" addr 0x%"PRIx64
3215 3213 "bbase 0x%"PRIx64
3216 3214 "blen 0x%"PRIx64" flags 0x%x algn 0x%"
3217 3215 PRIx64"\n",
3218 3216 req.ra_len, (uint64_t)req.ra_addr,
3219 3217 req.ra_boundbase,
3220 3218 req.ra_boundlen, req.ra_flags,
3221 3219 req.ra_align_mask);
3222 3220 #endif
3223 3221
3224 3222 /*
3225 3223 * Try to allocate the space. If we fail this,
3226 3224 * return the appropriate error depending
3227 3225 * on whether the caller specified a
3228 3226 * specific base address or not.
3229 3227 */
3230 3228 if (pcmcia_alloc_io(dip, &req, &res,
3231 3229 &winp->res_dip) == DDI_FAILURE) {
3232 3230 winp->pcw_status &= ~PCW_ENABLED;
3233 3231 mutex_exit(&pcic->pc_lock);
3234 3232 cmn_err(CE_WARN, "Failed to alloc I/O:\n"
3235 3233 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64
3236 3234 "bbase 0x%" PRIx64
3237 3235 "blen 0x%" PRIx64 "flags 0x%x"
3238 3236 "algn 0x%" PRIx64 "\n",
3239 3237 req.ra_len, req.ra_addr,
3240 3238 req.ra_boundbase,
3241 3239 req.ra_boundlen, req.ra_flags,
3242 3240 req.ra_align_mask);
3243 3241
3244 3242 return (base?BAD_BASE:BAD_SIZE);
3245 3243 } /* pcmcia_alloc_io */
3246 3244
3247 3245 /*
3248 3246 * Don't change the original base. Either we use
3249 3247 * the offset registers below (PCF_IO_REMAP is set)
3250 3248 * or it was allocated correctly anyway.
3251 3249 */
3252 3250 winp->pcw_base = res.ra_addr_lo;
3253 3251
3254 3252 #if defined(PCIC_DEBUG)
3255 3253 pcic_err(dip, 8,
3256 3254 "\tsetwindow: new base=%x orig base 0x%x\n",
3257 3255 (unsigned)winp->pcw_base, base);
3258 3256 #endif
3259 3257
3260 3258 if ((which = pcmcia_map_reg(pcic->dip,
3261 3259 window->child,
3262 3260 &res,
3263 3261 (uint32_t)(window->state &
3264 3262 0xffff) |
3265 3263 (window->socket << 16),
3266 3264 (caddr_t *)&winp->pcw_hostmem,
3267 3265 &winp->pcw_handle,
3268 3266 &window->attr,
3269 3267 base)) != DDI_SUCCESS) {
3270 3268
3271 3269 cmn_err(CE_WARN, "pcmcia_map_reg()"
3272 3270 "failed\n");
3273 3271
3274 3272 res.ra_addr_lo = winp->pcw_base;
3275 3273 res.ra_len = winp->pcw_len;
3276 3274 (void) pcmcia_free_io(winp->res_dip,
3277 3275 &res);
3278 3276
3279 3277 mutex_exit(&pcic->pc_lock);
3280 3278 return (BAD_WINDOW);
3281 3279 }
3282 3280
3283 3281 window->handle = winp->pcw_handle;
3284 3282 winp->pcw_status |= PCW_MAPPED;
3285 3283
3286 3284 /* find the register set offset */
3287 3285 select = win * PCIC_IO_OFFSET;
3288 3286
3289 3287 #if defined(PCIC_DEBUG)
3290 3288 if (pcic_debug) {
3291 3289 cmn_err(CE_CONT,
3292 3290 "\tenable: window=%d, select=%x, "
3293 3291 "base=%x, handle=%p\n",
3294 3292 win, select,
3295 3293 (unsigned)window->base,
3296 3294 (void *)window->handle);
3297 3295 }
3298 3296 #endif
3299 3297 /*
3300 3298 * at this point, the register window indicator has
3301 3299 * been converted to be an offset from the first
3302 3300 * set of registers that are used for programming
3303 3301 * the window mapping and the offset used to select
3304 3302 * the correct set of registers to access the
3305 3303 * specified socket. This allows basing everything
3306 3304 * off the _0 window
3307 3305 */
3308 3306
3309 3307 /* map the I/O base in */
3310 3308 pcic_putb(pcic, socket,
3311 3309 PCIC_IO_ADDR_0_STARTLOW + select,
3312 3310 LOW_BYTE((uint32_t)winp->pcw_base));
3313 3311 pcic_putb(pcic, socket,
3314 3312 PCIC_IO_ADDR_0_STARTHI + select,
3315 3313 HIGH_BYTE((uint32_t)winp->pcw_base));
3316 3314
3317 3315 pcic_putb(pcic, socket,
3318 3316 PCIC_IO_ADDR_0_STOPLOW + select,
3319 3317 LOW_BYTE((uint32_t)winp->pcw_base +
3320 3318 window->WindowSize - 1));
3321 3319 pcic_putb(pcic, socket,
3322 3320 PCIC_IO_ADDR_0_STOPHI + select,
3323 3321 HIGH_BYTE((uint32_t)winp->pcw_base +
3324 3322 window->WindowSize - 1));
3325 3323
3326 3324 /*
3327 3325 * We've got the requested IO space, now see if we
3328 3326 * need to adjust the IO window offset registers
3329 3327 * so that the correct IO address is generated
3330 3328 * at the socket. If this window doesn't have
3331 3329 * this capability, then we're all done setting
3332 3330 * up the IO resources.
3333 3331 */
3334 3332 if (pcic->pc_flags & PCF_IO_REMAP) {
3335 3333
3336 3334
3337 3335 /*
3338 3336 * Note that only 16 bits are used to program
3339 3337 * the registers but leave 32 bits on pcw_offset
3340 3338 * so that we can generate the original base
3341 3339 * in get_window()
3342 3340 */
3343 3341 winp->pcw_offset = (base - winp->pcw_base);
3344 3342
3345 3343 pcic_putb(pcic, socket,
3346 3344 PCIC_IO_OFFSET_LOW +
3347 3345 (win * PCIC_IO_OFFSET_OFFSET),
3348 3346 winp->pcw_offset & 0x0ff);
3349 3347 pcic_putb(pcic, socket,
3350 3348 PCIC_IO_OFFSET_HI +
3351 3349 (win * PCIC_IO_OFFSET_OFFSET),
3352 3350 (winp->pcw_offset >> 8) & 0x0ff);
3353 3351
3354 3352 } /* PCF_IO_REMAP */
3355 3353
3356 3354 /* now get the other details (size, etc) right */
3357 3355
3358 3356 /*
3359 3357 * Set the data size control bits here. Most of the
3360 3358 * adapters will ignore IOMEM_16BIT when
3361 3359 * IOMEM_IOCS16 is set, except for the Intel
3362 3360 * 82092, which only pays attention to the
3363 3361 * IOMEM_16BIT bit. Sigh... Intel can't even
3364 3362 * make a proper clone of their own chip.
3365 3363 * The 82092 also apparently can't set the timing
3366 3364 * of I/O windows.
3367 3365 */
3368 3366 which = (window->state & WS_16BIT) ?
3369 3367 (IOMEM_16BIT | IOMEM_IOCS16) : 0;
3370 3368
3371 3369 switch (pcic->pc_type) {
3372 3370 case PCIC_CL_PD6729:
3373 3371 case PCIC_CL_PD6730:
3374 3372 case PCIC_CL_PD6710:
3375 3373 case PCIC_CL_PD6722:
3376 3374 case PCIC_CL_PD6832:
3377 3375 /*
3378 3376 * Select Timer Set 1 - this will take
3379 3377 * effect when the PCIC_IO_CONTROL
3380 3378 * register is written to later on;
3381 3379 * the call to pcic_set_cdtimers
3382 3380 * just sets up the timer itself.
3383 3381 */
3384 3382 which |= IOMEM_CLTIMER_SET_1;
3385 3383 pcic_set_cdtimers(pcic, socket,
3386 3384 window->speed,
3387 3385 IOMEM_CLTIMER_SET_1);
3388 3386 which |= IOMEM_IOCS16;
3389 3387 break;
3390 3388 case PCIC_TI_PCI1031:
3391 3389
3392 3390 if (window->state & WS_16BIT)
3393 3391 which |= IOMEM_WAIT16;
3394 3392
3395 3393 break;
3396 3394 case PCIC_TI_PCI1130:
3397 3395
3398 3396 if (window->state & WS_16BIT)
3399 3397 which |= IOMEM_WAIT16;
3400 3398
3401 3399 break;
3402 3400 case PCIC_INTEL_i82092:
3403 3401 break;
3404 3402 default:
3405 3403 if (window->speed >
3406 3404 mhztons(pcic->bus_speed) * 3)
3407 3405 which |= IOMEM_WAIT16;
3408 3406 #ifdef notdef
3409 3407 if (window->speed <
3410 3408 mhztons(pcic->bus_speed) * 6)
3411 3409 which |= IOMEM_ZERO_WAIT;
3412 3410 #endif
3413 3411 break;
3414 3412 } /* switch (pc_type) */
3415 3413
3416 3414 /*
3417 3415 * Setup the data width and timing
3418 3416 */
3419 3417 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL);
3420 3418 select &= ~(PCIC_IO_WIN_MASK << (win * 4));
3421 3419 select |= IOMEM_SETWIN(win, which);
3422 3420 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select);
3423 3421
3424 3422 /*
3425 3423 * Enable the IO window
3426 3424 */
3427 3425 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3428 3426 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE,
3429 3427 select | IOMEM_WINDOW(win));
3430 3428
3431 3429 winp->pcw_status |= PCW_ENABLED;
3432 3430
3433 3431 #if defined(PCIC_DEBUG)
3434 3432 if (pcic_debug) {
3435 3433 cmn_err(CE_CONT,
3436 3434 "\twhich = %x, select = %x (%x)\n",
3437 3435 which, select,
3438 3436 IOMEM_SETWIN(win, which));
3439 3437 xxdmp_all_regs(pcic, window->socket * 0x40, 24);
3440 3438 }
3441 3439 #endif
3442 3440 } else {
3443 3441 /*
3444 3442 * not only do we unmap the IO space, the
3445 3443 * window has been turned off.
3446 3444 */
3447 3445 if (winp->pcw_status & PCW_MAPPED) {
3448 3446 ddi_regs_map_free(&winp->pcw_handle);
3449 3447 res.ra_addr_lo = winp->pcw_base;
3450 3448 res.ra_len = winp->pcw_len;
3451 3449 (void) pcmcia_free_io(winp->res_dip, &res);
3452 3450 winp->pcw_status &= ~PCW_MAPPED;
3453 3451 }
3454 3452
3455 3453 /* disable current mapping */
3456 3454 select = pcic_getb(pcic, socket,
3457 3455 PCIC_MAPPING_ENABLE);
3458 3456 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE,
3459 3457 select &= ~IOMEM_WINDOW(win));
3460 3458 winp->pcw_status &= ~PCW_ENABLED;
3461 3459
3462 3460 winp->pcw_base = 0;
3463 3461 winp->pcw_len = 0;
3464 3462 winp->pcw_offset = 0;
3465 3463 window->base = 0;
3466 3464 /* now make sure we don't accidentally re-enable */
3467 3465 /* find the register set offset */
3468 3466 select = win * PCIC_IO_OFFSET;
3469 3467 pcic_putb(pcic, socket,
3470 3468 PCIC_IO_ADDR_0_STARTLOW + select, 0);
3471 3469 pcic_putb(pcic, socket,
3472 3470 PCIC_IO_ADDR_0_STARTHI + select, 0);
3473 3471 pcic_putb(pcic, socket,
3474 3472 PCIC_IO_ADDR_0_STOPLOW + select, 0);
3475 3473 pcic_putb(pcic, socket,
3476 3474 PCIC_IO_ADDR_0_STOPHI + select, 0);
3477 3475 }
3478 3476 }
3479 3477 mutex_exit(&pcic->pc_lock);
3480 3478
3481 3479 return (SUCCESS);
3482 3480 }
3483 3481
3484 3482 /*
3485 3483 * pcic_card_state()
3486 3484 * compute the instantaneous Card State information
3487 3485 */
3488 3486 static int
3489 3487 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp)
3490 3488 {
3491 3489 int value, result;
3492 3490 #if defined(PCIC_DEBUG)
3493 3491 int orig_value;
3494 3492 #endif
3495 3493
3496 3494 mutex_enter(&pcic->pc_lock); /* protect the registers */
3497 3495
3498 3496 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS);
3499 3497
3500 3498 #if defined(PCIC_DEBUG)
3501 3499 orig_value = value;
3502 3500 if (pcic_debug >= 8)
3503 3501 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n",
3504 3502 (void *)sockp,
3505 3503 value,
3506 3504 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI",
3507 3505 sockp->pcs_socket);
3508 3506 #endif
3509 3507 /*
3510 3508 * Lie to socket services if we are not ready.
3511 3509 * This is when we are starting up or during debounce timeouts
3512 3510 * or if the card is a cardbus card.
3513 3511 */
3514 3512 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) &&
3515 3513 !sockp->pcs_debounce_id &&
3516 3514 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) {
3517 3515 result = SBM_CD;
3518 3516
3519 3517 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON))
3520 3518 result |= SBM_WP;
3521 3519 if (value & PCIC_POWER_ON) {
3522 3520 if (value & PCIC_READY)
3523 3521 result |= SBM_RDYBSY;
3524 3522 value = (~value) & (PCIC_BVD1 | PCIC_BVD2);
3525 3523 if (value & PCIC_BVD1)
3526 3524 result |= SBM_BVD1;
3527 3525 if (value & PCIC_BVD2)
3528 3526 result |= SBM_BVD2;
3529 3527 }
3530 3528 } else
3531 3529 result = 0;
3532 3530
3533 3531 mutex_exit(&pcic->pc_lock);
3534 3532
3535 3533 #if defined(PCIC_DEBUG)
3536 3534 pcic_err(pcic->dip, 8,
3537 3535 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n",
3538 3536 (void *) sockp, orig_value,
3539 3537 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI",
3540 3538 sockp->pcs_socket, result);
3541 3539 #endif
3542 3540
3543 3541 return (result);
3544 3542 }
3545 3543
3546 3544 /*
3547 3545 * pcic_set_page()
3548 3546 * SocketServices SetPage function
3549 3547 * set the page of PC Card memory that should be in the mapped
3550 3548 * window
3551 3549 */
3552 3550 /*ARGSUSED*/
3553 3551 static int
3554 3552 pcic_set_page(dev_info_t *dip, set_page_t *page)
3555 3553 {
3556 3554 anp_t *anp = ddi_get_driver_private(dip);
3557 3555 pcicdev_t *pcic = anp->an_private;
3558 3556 int select;
3559 3557 int which, socket, window;
3560 3558 uint32_t base;
3561 3559 pcs_memwin_t *memp;
3562 3560
3563 3561 /* get real socket/window numbers */
3564 3562 window = page->window % PCIC_NUMWINSOCK;
3565 3563 socket = page->window / PCIC_NUMWINSOCK;
3566 3564
3567 3565 #if defined(PCIC_DEBUG)
3568 3566 if (pcic_debug) {
3569 3567 cmn_err(CE_CONT,
3570 3568 "pcic_set_page: window=%d, socket=%d, page=%d\n",
3571 3569 window, socket, page->page);
3572 3570 }
3573 3571 #endif
3574 3572 /* only windows 2-6 work on memory */
3575 3573 if (window < PCIC_IOWINDOWS)
3576 3574 return (BAD_WINDOW);
3577 3575
3578 3576 /* only one page supported (but any size) */
3579 3577 if (page->page != 0)
3580 3578 return (BAD_PAGE);
3581 3579
3582 3580 mutex_enter(&pcic->pc_lock); /* protect the registers */
3583 3581
3584 3582 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem;
3585 3583 window -= PCIC_IOWINDOWS;
3586 3584
3587 3585 #if defined(PCIC_DEBUG)
3588 3586 if (pcic_debug)
3589 3587 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n",
3590 3588 (uint32_t)memp->pcw_base,
3591 3589 (void *)memp->pcw_hostmem, memp->pcw_len);
3592 3590 #endif
3593 3591
3594 3592 /* window must be enabled */
3595 3593 if (!(memp->pcw_status & PCW_ENABLED))
3596 3594 return (BAD_ATTRIBUTE);
3597 3595
3598 3596 /* find the register set offset */
3599 3597 select = window * PCIC_MEM_1_OFFSET;
3600 3598 #if defined(PCIC_DEBUG)
3601 3599 if (pcic_debug)
3602 3600 cmn_err(CE_CONT, "\tselect=%x\n", select);
3603 3601 #endif
3604 3602
3605 3603 /*
3606 3604 * now map the card's memory pages - we start with page 0
3607 3605 */
3608 3606
3609 3607 which = 0; /* assume simple case */
3610 3608 if (page->state & PS_ATTRIBUTE) {
3611 3609 which |= CARDMEM_REG_ACTIVE;
3612 3610 memp->pcw_status |= PCW_ATTRIBUTE;
3613 3611 } else {
3614 3612 memp->pcw_status &= ~PCW_ATTRIBUTE;
3615 3613 }
3616 3614
3617 3615 /*
3618 3616 * if caller says Write Protect, enforce it.
3619 3617 */
3620 3618 if (page->state & PS_WP) {
3621 3619 which |= CARDMEM_WRITE_PROTECT;
3622 3620 memp->pcw_status |= PCW_WP;
3623 3621 } else {
3624 3622 memp->pcw_status &= ~PCW_WP;
3625 3623 }
3626 3624 #if defined(PCIC_DEBUG)
3627 3625 if (pcic_debug) {
3628 3626 cmn_err(CE_CONT, "\tmemory type = %s\n",
3629 3627 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common");
3630 3628 if (which & CARDMEM_WRITE_PROTECT)
3631 3629 cmn_err(CE_CONT, "\twrite protect\n");
3632 3630 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n",
3633 3631 (unsigned)page->offset,
3634 3632 (unsigned)memp->pcw_base,
3635 3633 (int)page->offset - (int)memp->pcw_base & 0xffffff);
3636 3634 }
3637 3635 #endif
3638 3636 /* address computation based on 64MB range and not larger */
3639 3637 base = (uint32_t)memp->pcw_base & 0x3ffffff;
3640 3638 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select,
3641 3639 CARDMEM_LOW((int)page->offset - (int)base));
3642 3640 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select);
3643 3641 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select,
3644 3642 CARDMEM_HIGH((int)page->offset - base) | which);
3645 3643 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select);
3646 3644
3647 3645 /*
3648 3646 * while not really necessary, this just makes sure
3649 3647 * nothing turned the window off behind our backs
3650 3648 */
3651 3649 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3652 3650 which |= SYSMEM_WINDOW(window);
3653 3651 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which);
3654 3652 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3655 3653
3656 3654 memp->pcw_offset = (off_t)page->offset;
3657 3655
3658 3656 #if defined(PCIC_DEBUG)
3659 3657 if (pcic_debug) {
3660 3658 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n",
3661 3659 (void *)memp->pcw_hostmem,
3662 3660 (uint32_t)*memp->pcw_hostmem);
3663 3661
3664 3662 xxdmp_all_regs(pcic, socket, -1);
3665 3663
3666 3664 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n",
3667 3665 (void *)memp->pcw_hostmem,
3668 3666 (uint32_t)*memp->pcw_hostmem);
3669 3667 }
3670 3668 #endif
3671 3669
3672 3670 if (which & PCW_ATTRIBUTE)
3673 3671 pcic_mswait(pcic, socket, 2);
3674 3672
3675 3673 mutex_exit(&pcic->pc_lock);
3676 3674
3677 3675 return (SUCCESS);
3678 3676 }
3679 3677
3680 3678 /*
3681 3679 * pcic_set_vcc_level()
3682 3680 *
3683 3681 * set voltage based on adapter information
3684 3682 *
3685 3683 * this routine implements a limited solution for support of 3.3v cards.
3686 3684 * the general solution, which would fully support the pcmcia spec
3687 3685 * as far as allowing client drivers to request which voltage levels
3688 3686 * to be set, requires more framework support and driver changes - ess
3689 3687 */
3690 3688 static int
3691 3689 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket)
3692 3690 {
3693 3691 uint32_t socket_present_state;
3694 3692
3695 3693 #if defined(PCIC_DEBUG)
3696 3694 if (pcic_debug) {
3697 3695 cmn_err(CE_CONT,
3698 3696 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n",
3699 3697 (void *)pcic, socket->VccLevel);
3700 3698 }
3701 3699 #endif
3702 3700
3703 3701 /*
3704 3702 * check VccLevel
3705 3703 * if this is zero, power is being turned off
3706 3704 * if it is non-zero, power is being turned on.
3707 3705 */
3708 3706 if (socket->VccLevel == 0) {
3709 3707 return (0);
3710 3708 }
3711 3709
3712 3710 /*
3713 3711 * range checking for sanity's sake
3714 3712 */
3715 3713 if (socket->VccLevel >= pcic->pc_numpower) {
3716 3714 return (BAD_VCC);
3717 3715 }
3718 3716
3719 3717 switch (pcic->pc_io_type) {
3720 3718 /*
3721 3719 * Yenta-compliant adapters have vcc info in the extended registers
3722 3720 * Other adapters can be added as needed, but the 'default' case
3723 3721 * has been left as it was previously so as not to break existing
3724 3722 * adapters.
3725 3723 */
3726 3724 case PCIC_IO_TYPE_YENTA:
3727 3725 /*
3728 3726 * Here we ignore the VccLevel passed in and read the
3729 3727 * card type from the adapter socket present state register
3730 3728 */
3731 3729 socket_present_state =
3732 3730 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr +
3733 3731 PCIC_PRESENT_STATE_REG));
3734 3732 #if defined(PCIC_DEBUG)
3735 3733 if (pcic_debug) {
3736 3734 cmn_err(CE_CONT,
3737 3735 "socket present state = 0x%x\n",
3738 3736 socket_present_state);
3739 3737 }
3740 3738 #endif
3741 3739 switch (socket_present_state & PCIC_VCC_MASK) {
3742 3740 case PCIC_VCC_3VCARD:
3743 3741 /* fall through */
3744 3742 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD:
3745 3743 socket->VccLevel = PCIC_VCC_3VLEVEL;
3746 3744 return
3747 3745 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE);
3748 3746 case PCIC_VCC_5VCARD:
3749 3747 socket->VccLevel = PCIC_VCC_5VLEVEL;
3750 3748 return
3751 3749 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE);
3752 3750 default:
3753 3751 /*
3754 3752 * if no card is present, this can be the
3755 3753 * case of a client making a SetSocket call
3756 3754 * after card removal. In this case we return
3757 3755 * the current power level
3758 3756 */
3759 3757 return ((unsigned)ddi_get8(pcic->handle,
3760 3758 pcic->ioaddr + CB_R2_OFFSET +
3761 3759 PCIC_POWER_CONTROL));
3762 3760 }
3763 3761
3764 3762 default:
3765 3763
3766 3764 switch (socket->VccLevel) {
3767 3765 case PCIC_VCC_3VLEVEL:
3768 3766 return (BAD_VCC);
3769 3767 case PCIC_VCC_5VLEVEL:
3770 3768 /* enable Vcc */
3771 3769 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE);
3772 3770 default:
3773 3771 return (BAD_VCC);
3774 3772 }
3775 3773 }
3776 3774 }
3777 3775
3778 3776
3779 3777 /*
3780 3778 * pcic_set_socket()
3781 3779 * Socket Services SetSocket call
3782 3780 * sets basic socket configuration
3783 3781 */
3784 3782 static int
3785 3783 pcic_set_socket(dev_info_t *dip, set_socket_t *socket)
3786 3784 {
3787 3785 anp_t *anp = ddi_get_driver_private(dip);
3788 3786 pcicdev_t *pcic = anp->an_private;
3789 3787 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket];
3790 3788 int irq, interrupt, mirq;
3791 3789 int powerlevel = 0;
3792 3790 int ind, value, orig_pwrctl;
3793 3791
3794 3792 #if defined(PCIC_DEBUG)
3795 3793 if (pcic_debug) {
3796 3794 cmn_err(CE_CONT,
3797 3795 "pcic_set_socket(dip=%p, socket=%d)"
3798 3796 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip,
3799 3797 socket->socket, socket->VccLevel, socket->Vpp1Level,
3800 3798 socket->Vpp2Level);
3801 3799 }
3802 3800 #endif
3803 3801 /*
3804 3802 * check VccLevel, etc. before setting mutex
3805 3803 * if this is zero, power is being turned off
3806 3804 * if it is non-zero, power is being turned on.
3807 3805 * the default case is to assume Vcc only.
3808 3806 */
3809 3807
3810 3808 /* this appears to be very implementation specific */
3811 3809
3812 3810 if (socket->Vpp1Level != socket->Vpp2Level)
3813 3811 return (BAD_VPP);
3814 3812
3815 3813 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) {
3816 3814 powerlevel = 0;
3817 3815 sockp->pcs_vcc = 0;
3818 3816 sockp->pcs_vpp1 = 0;
3819 3817 sockp->pcs_vpp2 = 0;
3820 3818 } else {
3821 3819 #if defined(PCIC_DEBUG)
3822 3820 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n",
3823 3821 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level);
3824 3822 #endif
3825 3823 /* valid Vcc power level? */
3826 3824 if (socket->VccLevel >= pcic->pc_numpower)
3827 3825 return (BAD_VCC);
3828 3826
3829 3827 switch (pcic_power[socket->VccLevel].PowerLevel) {
3830 3828 case 33: /* 3.3V */
3831 3829 case 60: /* for bad CIS in Option GPRS card */
3832 3830 if (!(pcic->pc_flags & PCF_33VCAP)) {
3833 3831 cmn_err(CE_WARN,
3834 3832 "%s%d: Bad Request for 3.3V "
3835 3833 "(Controller incapable)\n",
3836 3834 ddi_get_name(pcic->dip),
3837 3835 ddi_get_instance(pcic->dip));
3838 3836 return (BAD_VCC);
3839 3837 }
3840 3838 /* FALLTHROUGH */
3841 3839 case 50: /* 5V */
3842 3840 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) &&
3843 3841 pcic_getcb(pcic, CB_PRESENT_STATE) &
3844 3842 CB_PS_33VCARD) {
3845 3843 /*
3846 3844 * This is actually a 3.3V card.
3847 3845 * Solaris Card Services
3848 3846 * doesn't understand 3.3V
3849 3847 * so we cheat and change
3850 3848 * the setting to the one appropriate to 3.3V.
3851 3849 * Note that this is the entry number
3852 3850 * in the pcic_power[] array.
3853 3851 */
3854 3852 sockp->pcs_vcc = PCIC_VCC_3VLEVEL;
3855 3853 } else
3856 3854 sockp->pcs_vcc = socket->VccLevel;
3857 3855 break;
3858 3856 default:
3859 3857 return (BAD_VCC);
3860 3858 }
3861 3859
3862 3860 /* enable Vcc */
3863 3861 powerlevel = POWER_CARD_ENABLE;
3864 3862
3865 3863 #if defined(PCIC_DEBUG)
3866 3864 if (pcic_debug) {
3867 3865 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n",
3868 3866 socket->VccLevel, powerlevel);
3869 3867 }
3870 3868 #endif
3871 3869 ind = 0; /* default index to 0 power */
3872 3870 if ((int)socket->Vpp1Level >= 0 &&
3873 3871 socket->Vpp1Level < pcic->pc_numpower) {
3874 3872 if (!(pcic_power[socket->Vpp1Level].ValidSignals
3875 3873 & VPP1)) {
3876 3874 return (BAD_VPP);
3877 3875 }
3878 3876 ind = pcic_power[socket->Vpp1Level].PowerLevel/10;
3879 3877 powerlevel |= pcic_vpp_levels[ind];
3880 3878 sockp->pcs_vpp1 = socket->Vpp1Level;
3881 3879 }
3882 3880 if ((int)socket->Vpp2Level >= 0 &&
3883 3881 socket->Vpp2Level < pcic->pc_numpower) {
3884 3882 if (!(pcic_power[socket->Vpp2Level].ValidSignals
3885 3883 & VPP2)) {
3886 3884 return (BAD_VPP);
3887 3885 }
3888 3886 ind = pcic_power[socket->Vpp2Level].PowerLevel/10;
3889 3887 powerlevel |= (pcic_vpp_levels[ind] << 2);
3890 3888 sockp->pcs_vpp2 = socket->Vpp2Level;
3891 3889 }
3892 3890
3893 3891 if (pcic->pc_flags & PCF_VPPX) {
3894 3892 /*
3895 3893 * this adapter doesn't allow separate Vpp1/Vpp2
3896 3894 * if one is turned on, both are turned on and only
3897 3895 * the Vpp1 bits should be set
3898 3896 */
3899 3897 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) {
3900 3898 /* must be the same if one not zero */
3901 3899 if (sockp->pcs_vpp1 != 0 &&
3902 3900 sockp->pcs_vpp2 != 0) {
3903 3901 cmn_err(CE_WARN,
3904 3902 "%s%d: Bad Power Request "
3905 3903 "(Vpp1/2 not the same)\n",
3906 3904 ddi_get_name(pcic->dip),
3907 3905 ddi_get_instance(pcic->dip));
3908 3906 return (BAD_VPP);
3909 3907 }
3910 3908 }
3911 3909 powerlevel &= ~(3<<2);
3912 3910 }
3913 3911
3914 3912 #if defined(PCIC_DEBUG)
3915 3913 if (pcic_debug) {
3916 3914 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n",
3917 3915 powerlevel, ind);
3918 3916 }
3919 3917 #endif
3920 3918 }
3921 3919 mutex_enter(&pcic->pc_lock); /* protect the registers */
3922 3920
3923 3921 /* turn socket->IREQRouting off while programming */
3924 3922 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT);
3925 3923 interrupt &= ~PCIC_INTR_MASK;
3926 3924 if (pcic->pc_flags & PCF_USE_SMI)
3927 3925 interrupt |= PCIC_INTR_ENABLE;
3928 3926 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt);
3929 3927
3930 3928 switch (pcic->pc_type) {
3931 3929 case PCIC_INTEL_i82092:
3932 3930 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ,
3933 3931 PCIC_82092_INT_DISABLE);
3934 3932 break;
3935 3933 default:
3936 3934 break;
3937 3935 } /* switch */
3938 3936
3939 3937 /* the SCIntMask specifies events to detect */
3940 3938 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT);
3941 3939
3942 3940 #if defined(PCIC_DEBUG)
3943 3941 if (pcic_debug)
3944 3942 cmn_err(CE_CONT,
3945 3943 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n",
3946 3944 socket->SCIntMask, interrupt, mirq);
3947 3945 #endif
3948 3946 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT);
3949 3947 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT,
3950 3948 mirq & ~PCIC_CHANGE_MASK);
3951 3949
3952 3950 /* save the mask we want to use */
3953 3951 sockp->pcs_intmask = socket->SCIntMask;
3954 3952
3955 3953 /*
3956 3954 * Until there is a card present it's not worth enabling
3957 3955 * any interrupts except "Card detect". This is done
3958 3956 * elsewhere in the driver so don't change things if
3959 3957 * there is no card!
3960 3958 */
3961 3959 if (sockp->pcs_flags & PCS_CARD_PRESENT) {
3962 3960
3963 3961 /* now update the hardware to reflect events desired */
3964 3962 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO)
3965 3963 mirq |= PCIC_BD_DETECT;
3966 3964
3967 3965 if (sockp->pcs_intmask & SBM_BVD2)
3968 3966 mirq |= PCIC_BW_DETECT;
3969 3967
3970 3968 if (sockp->pcs_intmask & SBM_RDYBSY)
3971 3969 mirq |= PCIC_RD_DETECT;
3972 3970
3973 3971 if (sockp->pcs_intmask & SBM_CD)
3974 3972 mirq |= PCIC_CD_DETECT;
3975 3973 }
3976 3974
3977 3975 if (sockp->pcs_flags & PCS_READY) {
3978 3976 /*
3979 3977 * card just came ready.
3980 3978 * make sure enough time elapses
3981 3979 * before touching it.
3982 3980 */
3983 3981 sockp->pcs_flags &= ~PCS_READY;
3984 3982 pcic_mswait(pcic, socket->socket, 10);
3985 3983 }
3986 3984
3987 3985 #if defined(PCIC_DEBUG)
3988 3986 if (pcic_debug) {
3989 3987 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq);
3990 3988 }
3991 3989 #endif
3992 3990
3993 3991 switch (pcic->pc_type) {
3994 3992 case PCIC_I82365SL:
3995 3993 case PCIC_VADEM:
3996 3994 case PCIC_VADEM_VG469:
3997 3995 /*
3998 3996 * The Intel version has different options. This is a
3999 3997 * special case of GPI which might be used for eject
4000 3998 */
4001 3999
4002 4000 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT);
4003 4001 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) &&
4004 4002 pcic->pc_flags & PCF_GPI_EJECT) {
4005 4003 irq |= PCIC_GPI_ENABLE;
4006 4004 } else {
4007 4005 irq &= ~PCIC_GPI_ENABLE;
4008 4006 }
4009 4007 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq);
4010 4008 break;
4011 4009 case PCIC_CL_PD6710:
4012 4010 case PCIC_CL_PD6722:
4013 4011 if (socket->IFType == IF_IO) {
4014 4012 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0);
4015 4013 value = pcic_getb(pcic, socket->socket,
4016 4014 PCIC_MISC_CTL_1);
4017 4015 if (pcic->pc_flags & PCF_AUDIO)
4018 4016 value |= PCIC_MC_SPEAKER_ENB;
4019 4017 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1,
4020 4018 value);
4021 4019 } else {
4022 4020 value = pcic_getb(pcic, socket->socket,
4023 4021 PCIC_MISC_CTL_1);
4024 4022 value &= ~PCIC_MC_SPEAKER_ENB;
4025 4023 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1,
4026 4024 value);
4027 4025 }
4028 4026 break;
4029 4027 case PCIC_CL_PD6729:
4030 4028 case PCIC_CL_PD6730:
4031 4029 case PCIC_CL_PD6832:
4032 4030 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1);
4033 4031 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) {
4034 4032 value |= PCIC_MC_SPEAKER_ENB;
4035 4033 } else {
4036 4034 value &= ~PCIC_MC_SPEAKER_ENB;
4037 4035 }
4038 4036
4039 4037 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33)
4040 4038 value |= PCIC_MC_3VCC;
4041 4039 else
4042 4040 value &= ~PCIC_MC_3VCC;
4043 4041
4044 4042 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value);
4045 4043 break;
4046 4044
4047 4045 case PCIC_O2_OZ6912:
4048 4046 value = pcic_getcb(pcic, CB_MISCCTRL);
4049 4047 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO))
4050 4048 value |= (1<<25);
4051 4049 else
4052 4050 value &= ~(1<<25);
4053 4051 pcic_putcb(pcic, CB_MISCCTRL, value);
4054 4052 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33)
4055 4053 powerlevel |= 0x08;
4056 4054 break;
4057 4055
4058 4056 case PCIC_TI_PCI1250:
4059 4057 case PCIC_TI_PCI1221:
4060 4058 case PCIC_TI_PCI1225:
4061 4059 case PCIC_TI_PCI1410:
4062 4060 case PCIC_ENE_1410:
4063 4061 case PCIC_TI_PCI1510:
4064 4062 case PCIC_TI_PCI1520:
4065 4063 case PCIC_TI_PCI1420:
4066 4064 case PCIC_ENE_1420:
4067 4065 value = ddi_get8(pcic->cfg_handle,
4068 4066 pcic->cfgaddr + PCIC_CRDCTL_REG);
4069 4067 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) {
4070 4068 value |= PCIC_CRDCTL_SPKR_ENBL;
4071 4069 } else {
4072 4070 value &= ~PCIC_CRDCTL_SPKR_ENBL;
4073 4071 }
4074 4072 ddi_put8(pcic->cfg_handle,
4075 4073 pcic->cfgaddr + PCIC_CRDCTL_REG, value);
4076 4074 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33)
4077 4075 powerlevel |= 0x08;
4078 4076 break;
4079 4077 }
4080 4078
4081 4079 /*
4082 4080 * ctlind processing -- we can ignore this
4083 4081 * there aren't any outputs on the chip for this and
4084 4082 * the GUI will display what it thinks is correct
4085 4083 */
4086 4084
4087 4085 /*
4088 4086 * If outputs are enabled and the power is going off
4089 4087 * turn off outputs first.
4090 4088 */
4091 4089
4092 4090 /* power setup -- if necessary */
4093 4091 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL);
4094 4092 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) {
4095 4093 orig_pwrctl &= ~POWER_OUTPUT_ENABLE;
4096 4094 pcic_putb(pcic, socket->socket,
4097 4095 PCIC_POWER_CONTROL, orig_pwrctl);
4098 4096 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL);
4099 4097 }
4100 4098
4101 4099 if (pcic->pc_flags & PCF_CBPWRCTL) {
4102 4100 value = pcic_cbus_powerctl(pcic, socket->socket);
4103 4101 powerlevel = 0;
4104 4102 } else
4105 4103 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel);
4106 4104
4107 4105 if (value != SUCCESS) {
4108 4106 mutex_exit(&pcic->pc_lock);
4109 4107 return (value);
4110 4108 }
4111 4109
4112 4110 /*
4113 4111 * If outputs were disabled and the power is going on
4114 4112 * turn on outputs afterwards.
4115 4113 */
4116 4114 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) {
4117 4115 orig_pwrctl = pcic_getb(pcic, socket->socket,
4118 4116 PCIC_POWER_CONTROL);
4119 4117 orig_pwrctl |= POWER_OUTPUT_ENABLE;
4120 4118 pcic_putb(pcic, socket->socket,
4121 4119 PCIC_POWER_CONTROL, orig_pwrctl);
4122 4120 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL);
4123 4121 }
4124 4122
4125 4123 /*
4126 4124 * Once we have done the power stuff can re-enable management
4127 4125 * interrupts.
4128 4126 */
4129 4127 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq);
4130 4128
4131 4129 #if defined(PCIC_DEBUG)
4132 4130 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x "
4133 4131 "cbctl 0x%x\n",
4134 4132 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL),
4135 4133 pcic_getcb(pcic, CB_CONTROL));
4136 4134 #endif
4137 4135
4138 4136 /* irq processing */
4139 4137 if (socket->IFType == IF_IO) {
4140 4138 /* IRQ only for I/O */
4141 4139 irq = socket->IREQRouting & PCIC_INTR_MASK;
4142 4140 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT);
4143 4141 value &= ~PCIC_INTR_MASK;
4144 4142
4145 4143 /* to enable I/O operation */
4146 4144 value |= PCIC_IO_CARD | PCIC_RESET;
4147 4145 sockp->pcs_flags |= PCS_CARD_IO;
4148 4146 if (irq != sockp->pcs_irq) {
4149 4147 if (sockp->pcs_irq != 0)
4150 4148 cmn_err(CE_CONT,
4151 4149 "SetSocket: IRQ mismatch %x != %x!\n",
4152 4150 irq, sockp->pcs_irq);
4153 4151 else
4154 4152 sockp->pcs_irq = irq;
4155 4153 }
4156 4154 irq = sockp->pcs_irq;
4157 4155
4158 4156 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value);
4159 4157 if (socket->IREQRouting & IRQ_ENABLE) {
4160 4158 pcic_enable_io_intr(pcic, socket->socket, irq);
4161 4159 sockp->pcs_flags |= PCS_IRQ_ENABLED;
4162 4160 } else {
4163 4161 pcic_disable_io_intr(pcic, socket->socket);
4164 4162 sockp->pcs_flags &= ~PCS_IRQ_ENABLED;
4165 4163 }
4166 4164 #if defined(PCIC_DEBUG)
4167 4165 if (pcic_debug) {
4168 4166 cmn_err(CE_CONT,
4169 4167 "\tsocket type is I/O and irq %x is %s\n", irq,
4170 4168 (socket->IREQRouting & IRQ_ENABLE) ?
4171 4169 "enabled" : "not enabled");
4172 4170 xxdmp_all_regs(pcic, socket->socket, 20);
4173 4171 }
4174 4172 #endif
4175 4173 } else {
4176 4174 /* make sure I/O mode is off */
4177 4175
4178 4176 sockp->pcs_irq = 0;
4179 4177
4180 4178 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT);
4181 4179 value &= ~PCIC_IO_CARD;
4182 4180 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value);
4183 4181 pcic_disable_io_intr(pcic, socket->socket);
4184 4182 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED);
4185 4183 }
4186 4184
4187 4185 sockp->pcs_state &= ~socket->State;
4188 4186
4189 4187 mutex_exit(&pcic->pc_lock);
4190 4188 return (SUCCESS);
4191 4189 }
4192 4190
4193 4191 /*
4194 4192 * pcic_inquire_socket()
4195 4193 * SocketServices InquireSocket function
4196 4194 * returns basic characteristics of the socket
4197 4195 */
4198 4196 /*ARGSUSED*/
4199 4197 static int
4200 4198 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket)
4201 4199 {
4202 4200 anp_t *anp = ddi_get_driver_private(dip);
4203 4201 pcicdev_t *pcic = anp->an_private;
4204 4202 int value;
4205 4203
4206 4204 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS;
4207 4205 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS;
4208 4206 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS;
4209 4207 value = pcic->pc_sockets[socket->socket].pcs_flags;
4210 4208 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY;
4211 4209 socket->ActiveHigh = 0;
4212 4210 /* these are the usable IRQs */
4213 4211 socket->ActiveLow = 0xfff0;
4214 4212 return (SUCCESS);
4215 4213 }
4216 4214
4217 4215 /*
4218 4216 * pcic_inquire_window()
4219 4217 * SocketServices InquireWindow function
4220 4218 * returns detailed characteristics of the window
4221 4219 * this is where windows get tied to sockets
4222 4220 */
4223 4221 /*ARGSUSED*/
4224 4222 static int
4225 4223 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window)
4226 4224 {
4227 4225 int type, socket;
4228 4226
4229 4227 type = window->window % PCIC_NUMWINSOCK;
4230 4228 socket = window->window / PCIC_NUMWINSOCK;
4231 4229
4232 4230 #if defined(PCIC_DEBUG)
4233 4231 if (pcic_debug >= 8)
4234 4232 cmn_err(CE_CONT,
4235 4233 "pcic_inquire_window: window = %d/%d socket=%d\n",
4236 4234 window->window, type, socket);
4237 4235 #endif
4238 4236 if (type < PCIC_IOWINDOWS) {
4239 4237 window->WndCaps = WC_IO|WC_WAIT;
4240 4238 type = IF_IO;
4241 4239 } else {
4242 4240 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT;
4243 4241 type = IF_MEMORY;
4244 4242 }
4245 4243
4246 4244 /* initialize the socket map - one socket per window */
4247 4245 PR_ZERO(window->Sockets);
4248 4246 PR_SET(window->Sockets, socket);
4249 4247
4250 4248 if (type == IF_IO) {
4251 4249 iowin_char_t *io;
4252 4250 io = &window->iowin_char;
4253 4251 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT|
4254 4252 WC_16BIT;
4255 4253 io->FirstByte = (baseaddr_t)IOMEM_FIRST;
4256 4254 io->LastByte = (baseaddr_t)IOMEM_LAST;
4257 4255 io->MinSize = IOMEM_MIN;
4258 4256 io->MaxSize = IOMEM_MAX;
4259 4257 io->ReqGran = IOMEM_GRAN;
4260 4258 io->AddrLines = IOMEM_DECODE;
4261 4259 io->EISASlot = 0;
4262 4260 } else {
4263 4261 mem_win_char_t *mem;
4264 4262 mem = &window->mem_win_char;
4265 4263 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT|
4266 4264 WC_16BIT|WC_WP;
4267 4265
4268 4266 mem->FirstByte = (baseaddr_t)MEM_FIRST;
4269 4267 mem->LastByte = (baseaddr_t)MEM_LAST;
4270 4268
4271 4269 mem->MinSize = MEM_MIN;
4272 4270 mem->MaxSize = MEM_MAX;
4273 4271 mem->ReqGran = PCIC_PAGE;
4274 4272 mem->ReqBase = 0;
4275 4273 mem->ReqOffset = PCIC_PAGE;
4276 4274 mem->Slowest = MEM_SPEED_MAX;
4277 4275 mem->Fastest = MEM_SPEED_MIN;
4278 4276 }
4279 4277 return (SUCCESS);
4280 4278 }
4281 4279
4282 4280 /*
4283 4281 * pcic_get_adapter()
4284 4282 * SocketServices GetAdapter function
4285 4283 * this is nearly a no-op.
4286 4284 */
4287 4285 /*ARGSUSED*/
4288 4286 static int
4289 4287 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt)
4290 4288 {
4291 4289 anp_t *anp = ddi_get_driver_private(dip);
4292 4290 pcicdev_t *pcic = anp->an_private;
4293 4291
4294 4292 if (pcic->pc_flags & PCF_INTRENAB)
4295 4293 adapt->SCRouting = IRQ_ENABLE;
4296 4294 adapt->state = 0;
4297 4295 return (SUCCESS);
4298 4296 }
4299 4297
4300 4298 /*
4301 4299 * pcic_get_page()
4302 4300 * SocketServices GetPage function
4303 4301 * returns info about the window
4304 4302 */
4305 4303 /*ARGSUSED*/
4306 4304 static int
4307 4305 pcic_get_page(dev_info_t *dip, get_page_t *page)
4308 4306 {
4309 4307 anp_t *anp = ddi_get_driver_private(dip);
4310 4308 pcicdev_t *pcic = anp->an_private;
4311 4309 int socket, window;
4312 4310 pcs_memwin_t *winp;
4313 4311
4314 4312 socket = page->window / PCIC_NUMWINSOCK;
4315 4313 window = page->window % PCIC_NUMWINSOCK;
4316 4314
4317 4315 /* I/O windows are the first two */
4318 4316 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) {
4319 4317 return (BAD_WINDOW);
4320 4318 }
4321 4319
4322 4320 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem;
4323 4321
4324 4322 if (page->page != 0)
4325 4323 return (BAD_PAGE);
4326 4324
4327 4325 page->state = 0;
4328 4326 if (winp->pcw_status & PCW_ENABLED)
4329 4327 page->state |= PS_ENABLED;
4330 4328 if (winp->pcw_status & PCW_ATTRIBUTE)
4331 4329 page->state |= PS_ATTRIBUTE;
4332 4330 if (winp->pcw_status & PCW_WP)
4333 4331 page->state |= PS_WP;
4334 4332
4335 4333 page->offset = (off_t)winp->pcw_offset;
4336 4334
4337 4335 return (SUCCESS);
4338 4336 }
4339 4337
4340 4338 /*
4341 4339 * pcic_get_socket()
4342 4340 * SocketServices GetSocket
4343 4341 * returns information about the current socket setting
4344 4342 */
4345 4343 /*ARGSUSED*/
4346 4344 static int
4347 4345 pcic_get_socket(dev_info_t *dip, get_socket_t *socket)
4348 4346 {
4349 4347 anp_t *anp = ddi_get_driver_private(dip);
4350 4348 pcicdev_t *pcic = anp->an_private;
4351 4349 int socknum, irq_enabled;
4352 4350 pcic_socket_t *sockp;
4353 4351
4354 4352 socknum = socket->socket;
4355 4353 sockp = &pcic->pc_sockets[socknum];
4356 4354
4357 4355 socket->SCIntMask = sockp->pcs_intmask;
4358 4356 sockp->pcs_state = pcic_card_state(pcic, sockp);
4359 4357
4360 4358 socket->state = sockp->pcs_state;
4361 4359 if (socket->state & SBM_CD) {
4362 4360 socket->VccLevel = sockp->pcs_vcc;
4363 4361 socket->Vpp1Level = sockp->pcs_vpp1;
4364 4362 socket->Vpp2Level = sockp->pcs_vpp2;
4365 4363 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ?
4366 4364 IRQ_ENABLE : 0;
4367 4365 socket->IRQRouting = sockp->pcs_irq | irq_enabled;
4368 4366 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ?
4369 4367 IF_IO : IF_MEMORY;
4370 4368 } else {
4371 4369 socket->VccLevel = 0;
4372 4370 socket->Vpp1Level = 0;
4373 4371 socket->Vpp2Level = 0;
4374 4372 socket->IRQRouting = 0;
4375 4373 socket->IFType = IF_MEMORY;
4376 4374 }
4377 4375 socket->CtlInd = 0; /* no indicators */
4378 4376
4379 4377 return (SUCCESS);
4380 4378 }
4381 4379
4382 4380 /*
4383 4381 * pcic_get_status()
4384 4382 * SocketServices GetStatus
4385 4383 * returns status information about the PC Card in
4386 4384 * the selected socket
4387 4385 */
4388 4386 /*ARGSUSED*/
4389 4387 static int
4390 4388 pcic_get_status(dev_info_t *dip, get_ss_status_t *status)
4391 4389 {
4392 4390 anp_t *anp = ddi_get_driver_private(dip);
4393 4391 pcicdev_t *pcic = anp->an_private;
4394 4392 int socknum, irq_enabled;
4395 4393 pcic_socket_t *sockp;
4396 4394
4397 4395 socknum = status->socket;
4398 4396 sockp = &pcic->pc_sockets[socknum];
4399 4397
4400 4398 status->CardState = pcic_card_state(pcic, sockp);
4401 4399 status->SocketState = sockp->pcs_state;
4402 4400 status->CtlInd = 0; /* no indicators */
4403 4401
4404 4402 if (sockp->pcs_flags & PCS_CARD_PRESENT)
4405 4403 status->SocketState |= SBM_CD;
4406 4404 if (status->CardState & SBM_CD) {
4407 4405 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ?
4408 4406 IRQ_ENABLE : 0;
4409 4407 status->IRQRouting = sockp->pcs_irq | irq_enabled;
4410 4408 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ?
4411 4409 IF_IO : IF_MEMORY;
4412 4410 } else {
4413 4411 status->IRQRouting = 0;
4414 4412 status->IFType = IF_MEMORY;
4415 4413 }
4416 4414
4417 4415 #if defined(PCIC_DEBUG)
4418 4416 if (pcic_debug >= 8)
4419 4417 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x,"
4420 4418 "SocketState=%x\n",
4421 4419 socknum, status->CardState, status->SocketState);
4422 4420 #endif
4423 4421 switch (pcic->pc_type) {
4424 4422 uint32_t present_state;
4425 4423 case PCIC_TI_PCI1410:
4426 4424 case PCIC_TI_PCI1520:
4427 4425 case PCIC_TI_PCI1420:
4428 4426 case PCIC_ENE_1420:
4429 4427 case PCIC_TOSHIBA_TOPIC100:
4430 4428 case PCIC_TOSHIBA_TOPIC95:
4431 4429 case PCIC_TOSHIBA_VENDOR:
4432 4430 case PCIC_O2MICRO_VENDOR:
4433 4431 case PCIC_TI_VENDOR:
4434 4432 case PCIC_RICOH_VENDOR:
4435 4433 present_state = pcic_getcb(pcic, CB_PRESENT_STATE);
4436 4434 if (present_state & PCIC_CB_CARD)
4437 4435 status->IFType = IF_CARDBUS;
4438 4436 #if defined(PCIC_DEBUG)
4439 4437 if (pcic_debug >= 8)
4440 4438 cmn_err(CE_CONT,
4441 4439 "pcic_get_status: present_state=0x%x\n",
4442 4440 present_state);
4443 4441 #endif
4444 4442 break;
4445 4443 default:
4446 4444 break;
4447 4445 }
4448 4446
4449 4447 return (SUCCESS);
4450 4448 }
4451 4449
4452 4450 /*
4453 4451 * pcic_get_window()
4454 4452 * SocketServices GetWindow function
4455 4453 * returns state information about the specified window
4456 4454 */
4457 4455 /*ARGSUSED*/
4458 4456 static int
4459 4457 pcic_get_window(dev_info_t *dip, get_window_t *window)
4460 4458 {
4461 4459 anp_t *anp = ddi_get_driver_private(dip);
4462 4460 pcicdev_t *pcic = anp->an_private;
4463 4461 int socket, win;
4464 4462 pcic_socket_t *sockp;
4465 4463 pcs_memwin_t *winp;
4466 4464
4467 4465 socket = window->window / PCIC_NUMWINSOCK;
4468 4466 win = window->window % PCIC_NUMWINSOCK;
4469 4467 #if defined(PCIC_DEBUG)
4470 4468 if (pcic_debug) {
4471 4469 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n",
4472 4470 socket, win);
4473 4471 }
4474 4472 #endif
4475 4473
4476 4474 if (socket > pcic->pc_numsockets)
4477 4475 return (BAD_WINDOW);
4478 4476
4479 4477 sockp = &pcic->pc_sockets[socket];
4480 4478 winp = &sockp->pcs_windows[win].mem;
4481 4479
4482 4480 window->socket = socket;
4483 4481 window->size = winp->pcw_len;
4484 4482 window->speed = winp->pcw_speed;
4485 4483 window->handle = (ddi_acc_handle_t)winp->pcw_handle;
4486 4484 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset;
4487 4485
4488 4486 if (win >= PCIC_IOWINDOWS) {
4489 4487 window->state = 0;
4490 4488 } else {
4491 4489 window->state = WS_IO;
4492 4490 }
4493 4491 if (winp->pcw_status & PCW_ENABLED)
4494 4492 window->state |= WS_ENABLED;
4495 4493
4496 4494 if (winp->pcw_status & PCS_CARD_16BIT)
4497 4495 window->state |= WS_16BIT;
4498 4496 #if defined(PCIC_DEBUG)
4499 4497 if (pcic_debug)
4500 4498 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n",
4501 4499 window->size, (unsigned)window->speed,
4502 4500 (void *)window->handle, window->state);
4503 4501 #endif
4504 4502
4505 4503 return (SUCCESS);
4506 4504 }
4507 4505
4508 4506 /*
4509 4507 * pcic_ll_reset
4510 4508 * low level reset
4511 4509 * separated out so it can be called when already locked
4512 4510 *
4513 4511 * There are two variables that control the RESET timing:
4514 4512 * pcic_prereset_time - time in mS before asserting RESET
4515 4513 * pcic_reset_time - time in mS to assert RESET
4516 4514 *
4517 4515 */
4518 4516 int pcic_prereset_time = 1;
4519 4517 int pcic_reset_time = 10;
4520 4518 int pcic_postreset_time = 20;
4521 4519 int pcic_vpp_is_vcc_during_reset = 0;
4522 4520
4523 4521 static int
4524 4522 pcic_ll_reset(pcicdev_t *pcic, int socket)
4525 4523 {
4526 4524 int windowbits, iobits;
4527 4525 uint32_t pwr;
4528 4526
4529 4527 /* save windows that were on */
4530 4528 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
4531 4529 if (pcic_reset_time == 0)
4532 4530 return (windowbits);
4533 4531 /* turn all windows off */
4534 4532 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0);
4535 4533
4536 4534 #if defined(PCIC_DEBUG)
4537 4535 pcic_err(pcic->dip, 6,
4538 4536 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n",
4539 4537 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL),
4540 4538 pcic_getcb(pcic, CB_CONTROL),
4541 4539 pcic_getcb(pcic, CB_PRESENT_STATE));
4542 4540 #endif
4543 4541
4544 4542 if (pcic_vpp_is_vcc_during_reset) {
4545 4543
4546 4544 /*
4547 4545 * Set VPP to VCC for the duration of the reset - for aironet
4548 4546 * card.
4549 4547 */
4550 4548 if (pcic->pc_flags & PCF_CBPWRCTL) {
4551 4549 pwr = pcic_getcb(pcic, CB_CONTROL);
4552 4550 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC);
4553 4551 (void) pcic_getcb(pcic, CB_CONTROL);
4554 4552 } else {
4555 4553 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
4556 4554 pcic_putb(pcic, socket, PCIC_POWER_CONTROL,
4557 4555 pwr | 1);
4558 4556 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
4559 4557 }
4560 4558 }
4561 4559
4562 4560 if (pcic_prereset_time > 0) {
4563 4561 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n",
4564 4562 pcic_prereset_time);
4565 4563 pcic_mswait(pcic, socket, pcic_prereset_time);
4566 4564 }
4567 4565
4568 4566 /* turn interrupts off and start a reset */
4569 4567 pcic_err(pcic->dip, 8,
4570 4568 "pcic_ll_reset turn interrupts off and start a reset\n");
4571 4569 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT);
4572 4570 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET);
4573 4571 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits);
4574 4572 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT);
4575 4573
4576 4574 switch (pcic->pc_type) {
4577 4575 case PCIC_INTEL_i82092:
4578 4576 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ,
4579 4577 PCIC_82092_INT_DISABLE);
4580 4578 break;
4581 4579 default:
4582 4580 break;
4583 4581 } /* switch */
4584 4582
4585 4583 pcic->pc_sockets[socket].pcs_state = 0;
4586 4584
4587 4585 if (pcic_reset_time > 0) {
4588 4586 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n",
4589 4587 pcic_reset_time);
4590 4588 pcic_mswait(pcic, socket, pcic_reset_time);
4591 4589 }
4592 4590
4593 4591 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n");
4594 4592
4595 4593 /* take it out of RESET now */
4596 4594 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits);
4597 4595 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT);
4598 4596
4599 4597 /*
4600 4598 * can't access the card for 20ms, but we really don't
4601 4599 * want to sit around that long. The pcic is still usable.
4602 4600 * memory accesses must wait for RDY to come up.
4603 4601 */
4604 4602 if (pcic_postreset_time > 0) {
4605 4603 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n",
4606 4604 pcic_postreset_time);
4607 4605 pcic_mswait(pcic, socket, pcic_postreset_time);
4608 4606 }
4609 4607
4610 4608 if (pcic_vpp_is_vcc_during_reset > 1) {
4611 4609
4612 4610 /*
4613 4611 * Return VPP power to whatever it was before.
4614 4612 */
4615 4613 if (pcic->pc_flags & PCF_CBPWRCTL) {
4616 4614 pcic_putcb(pcic, CB_CONTROL, pwr);
4617 4615 (void) pcic_getcb(pcic, CB_CONTROL);
4618 4616 } else {
4619 4617 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr);
4620 4618 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
4621 4619 }
4622 4620 }
4623 4621
4624 4622 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits);
4625 4623
4626 4624 return (windowbits);
4627 4625 }
4628 4626
4629 4627 /*
4630 4628 * pcic_reset_socket()
4631 4629 * SocketServices ResetSocket function
4632 4630 * puts the PC Card in the socket into the RESET state
4633 4631 * and then takes it out after the the cycle time
4634 4632 * The socket is back to initial state when done
4635 4633 */
4636 4634 static int
4637 4635 pcic_reset_socket(dev_info_t *dip, int socket, int mode)
4638 4636 {
4639 4637 anp_t *anp = ddi_get_driver_private(dip);
4640 4638 pcicdev_t *pcic = anp->an_private;
4641 4639 int value;
4642 4640 int i, mint;
4643 4641 pcic_socket_t *sockp;
4644 4642
4645 4643 #if defined(PCIC_DEBUG)
4646 4644 if (pcic_debug >= 8)
4647 4645 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n",
4648 4646 (void *)dip, socket, mode,
4649 4647 mode == RESET_MODE_FULL ? "full" : "partial");
4650 4648 #endif
4651 4649
4652 4650 mutex_enter(&pcic->pc_lock); /* protect the registers */
4653 4651
4654 4652 /* Turn off management interupts. */
4655 4653 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT);
4656 4654 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK);
4657 4655
4658 4656 sockp = &pcic->pc_sockets[socket];
4659 4657
4660 4658 value = pcic_ll_reset(pcic, socket);
4661 4659 if (mode == RESET_MODE_FULL) {
4662 4660 /* disable and unmap all mapped windows */
4663 4661 for (i = 0; i < PCIC_NUMWINSOCK; i++) {
4664 4662 if (i < PCIC_IOWINDOWS) {
4665 4663 if (sockp->pcs_windows[i].io.pcw_status &
4666 4664 PCW_MAPPED) {
4667 4665 pcs_iowin_t *io;
4668 4666 io = &sockp->pcs_windows[i].io;
4669 4667 io->pcw_status &= ~PCW_ENABLED;
4670 4668 }
4671 4669 } else {
4672 4670 if (sockp->pcs_windows[i].mem.pcw_status &
4673 4671 PCW_MAPPED) {
4674 4672 pcs_memwin_t *mem;
4675 4673 mem = &sockp->pcs_windows[i].mem;
4676 4674 mem->pcw_status &= ~PCW_ENABLED;
4677 4675 }
4678 4676 }
4679 4677 }
4680 4678 } else {
4681 4679 /* turn windows back on */
4682 4680 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value);
4683 4681 /* wait the rest of the time here */
4684 4682 pcic_mswait(pcic, socket, 10);
4685 4683 }
4686 4684 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint);
4687 4685 mutex_exit(&pcic->pc_lock);
4688 4686 return (SUCCESS);
4689 4687 }
4690 4688
4691 4689 /*
4692 4690 * pcic_set_interrupt()
4693 4691 * SocketServices SetInterrupt function
4694 4692 */
4695 4693 static int
4696 4694 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler)
4697 4695 {
4698 4696 anp_t *anp = ddi_get_driver_private(dip);
4699 4697 pcicdev_t *pcic = anp->an_private;
4700 4698 int value = DDI_SUCCESS;
4701 4699 inthandler_t *intr;
4702 4700
4703 4701 #if defined(PCIC_DEBUG)
4704 4702 if (pcic_debug) {
4705 4703 cmn_err(CE_CONT,
4706 4704 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n",
4707 4705 pcic->pc_intr_mode);
4708 4706 cmn_err(CE_CONT,
4709 4707 "\t irq_top=%p handler=%p handler_id=%x\n",
4710 4708 (void *)pcic->irq_top, (void *)handler->handler,
4711 4709 handler->handler_id);
4712 4710 }
4713 4711 #endif
4714 4712
4715 4713 /*
4716 4714 * If we're on a PCI bus, we route all IO IRQs through a single
4717 4715 * PCI interrupt (typically INT A#) so we don't have to do
4718 4716 * much other than add the caller to general interrupt handler
4719 4717 * and set some state.
4720 4718 */
4721 4719
4722 4720 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP);
4723 4721 if (intr == NULL)
4724 4722 return (NO_RESOURCE);
4725 4723
4726 4724 switch (pcic->pc_intr_mode) {
4727 4725 case PCIC_INTR_MODE_PCI_1:
4728 4726 /*
4729 4727 * We only allow above-lock-level IO IRQ handlers
4730 4728 * in the PCI bus case.
4731 4729 */
4732 4730
4733 4731 mutex_enter(&pcic->intr_lock);
4734 4732
4735 4733 if (pcic->irq_top == NULL) {
4736 4734 pcic->irq_top = intr;
4737 4735 pcic->irq_current = pcic->irq_top;
4738 4736 } else {
4739 4737 while (pcic->irq_current->next != NULL)
4740 4738 pcic->irq_current = pcic->irq_current->next;
4741 4739 pcic->irq_current->next = intr;
4742 4740 pcic->irq_current = pcic->irq_current->next;
4743 4741 }
4744 4742
4745 4743 pcic->irq_current->intr =
4746 4744 (ddi_intr_handler_t *)handler->handler;
4747 4745 pcic->irq_current->handler_id = handler->handler_id;
4748 4746 pcic->irq_current->arg1 = handler->arg1;
4749 4747 pcic->irq_current->arg2 = handler->arg2;
4750 4748 pcic->irq_current->socket = handler->socket;
4751 4749
4752 4750 mutex_exit(&pcic->intr_lock);
4753 4751
4754 4752 handler->iblk_cookie = &pcic->pc_pri;
4755 4753 handler->idev_cookie = &pcic->pc_dcookie;
4756 4754 break;
4757 4755
4758 4756 default:
4759 4757 intr->intr = (ddi_intr_handler_t *)handler->handler;
4760 4758 intr->handler_id = handler->handler_id;
4761 4759 intr->arg1 = handler->arg1;
4762 4760 intr->arg2 = handler->arg2;
4763 4761 intr->socket = handler->socket;
4764 4762 intr->irq = handler->irq;
4765 4763
4766 4764 /*
4767 4765 * need to revisit this to see if interrupts can be
4768 4766 * shared someday. Note that IRQ is set in the common
4769 4767 * code.
4770 4768 */
4771 4769 mutex_enter(&pcic->pc_lock);
4772 4770 if (pcic->pc_handlers == NULL) {
4773 4771 pcic->pc_handlers = intr;
4774 4772 intr->next = intr->prev = intr;
4775 4773 } else {
4776 4774 insque(intr, pcic->pc_handlers);
4777 4775 }
4778 4776 mutex_exit(&pcic->pc_lock);
4779 4777
4780 4778 break;
4781 4779 }
4782 4780
4783 4781 /*
4784 4782 * need to fill in cookies in event of multiple high priority
4785 4783 * interrupt handlers on same IRQ
4786 4784 */
4787 4785
4788 4786 #if defined(PCIC_DEBUG)
4789 4787 if (pcic_debug) {
4790 4788 cmn_err(CE_CONT,
4791 4789 "pcic_set_interrupt: exit irq_top=%p value=%d\n",
4792 4790 (void *)pcic->irq_top, value);
4793 4791 }
4794 4792 #endif
4795 4793
4796 4794 if (value == DDI_SUCCESS) {
4797 4795 return (SUCCESS);
4798 4796 } else {
4799 4797 return (BAD_IRQ);
4800 4798 }
4801 4799 }
4802 4800
4803 4801 /*
4804 4802 * pcic_clear_interrupt()
4805 4803 * SocketServices ClearInterrupt function
4806 4804 *
4807 4805 * Interrupts for PCIC are complicated by the fact that we must
4808 4806 * follow several different models for interrupts.
4809 4807 * ISA: there is an interrupt per adapter and per socket and
4810 4808 * they can't be shared.
4811 4809 * PCI: some adapters have one PCI interrupt available while others
4812 4810 * have up to 4. Solaris may or may not allow us to use more
4813 4811 * than 1 so we essentially share them all at this point.
4814 4812 * Hybrid: PCI bridge but interrupts wired to host interrupt controller.
4815 4813 * This is like ISA but we have to fudge and create an intrspec
4816 4814 * that PCI's parent understands and bypass the PCI nexus.
4817 4815 * multifunction: this requires sharing the interrupts on a per-socket
4818 4816 * basis.
4819 4817 */
4820 4818 static int
4821 4819 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler)
4822 4820 {
4823 4821 anp_t *anp = ddi_get_driver_private(dip);
4824 4822 pcicdev_t *pcic = anp->an_private;
4825 4823 inthandler_t *intr, *prev, *current;
4826 4824 int i;
4827 4825
4828 4826 /*
4829 4827 * If we're on a PCI bus, we route all IO IRQs through a single
4830 4828 * PCI interrupt (typically INT A#) so we don't have to do
4831 4829 * much other than remove the caller from the general
4832 4830 * interrupt handler callout list.
4833 4831 */
4834 4832
4835 4833 #if defined(PCIC_DEBUG)
4836 4834 if (pcic_debug) {
4837 4835 cmn_err(CE_CONT,
4838 4836 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n",
4839 4837 pcic->pc_intr_mode);
4840 4838 cmn_err(CE_CONT,
4841 4839 "\t irq_top=%p handler=%p handler_id=%x\n",
4842 4840 (void *)pcic->irq_top, (void *)handler->handler,
4843 4841 handler->handler_id);
4844 4842 }
4845 4843 #endif
4846 4844
4847 4845 switch (pcic->pc_intr_mode) {
4848 4846 case PCIC_INTR_MODE_PCI_1:
4849 4847
4850 4848 mutex_enter(&pcic->intr_lock);
4851 4849 if (pcic->irq_top == NULL) {
4852 4850 mutex_exit(&pcic->intr_lock);
4853 4851 return (BAD_IRQ);
4854 4852 }
4855 4853
4856 4854 intr = NULL;
4857 4855 pcic->irq_current = pcic->irq_top;
4858 4856
4859 4857 while ((pcic->irq_current != NULL) &&
4860 4858 (pcic->irq_current->handler_id !=
4861 4859 handler->handler_id)) {
4862 4860 intr = pcic->irq_current;
4863 4861 pcic->irq_current = pcic->irq_current->next;
4864 4862 }
4865 4863
4866 4864 if (pcic->irq_current == NULL) {
4867 4865 mutex_exit(&pcic->intr_lock);
4868 4866 return (BAD_IRQ);
4869 4867 }
4870 4868
4871 4869 if (intr != NULL) {
4872 4870 intr->next = pcic->irq_current->next;
4873 4871 } else {
4874 4872 pcic->irq_top = pcic->irq_current->next;
4875 4873 }
4876 4874
4877 4875 current = pcic->irq_current;
4878 4876 pcic->irq_current = pcic->irq_top;
4879 4877 mutex_exit(&pcic->intr_lock);
4880 4878 kmem_free(current, sizeof (inthandler_t));
4881 4879
4882 4880 break;
4883 4881
4884 4882 default:
4885 4883
4886 4884 mutex_enter(&pcic->pc_lock);
4887 4885 intr = pcic_handlers;
4888 4886 prev = (inthandler_t *)&pcic_handlers;
4889 4887
4890 4888 while (intr != NULL) {
4891 4889 if (intr->handler_id == handler->handler_id) {
4892 4890 i = intr->irq & PCIC_INTR_MASK;
4893 4891 if (--pcic_irq_map[i].count == 0) {
4894 4892 /* multi-handler form */
4895 4893 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]);
4896 4894 (void) ddi_intr_remove_handler(
4897 4895 pcic->pc_intr_htblp[i]);
4898 4896 (void) ddi_intr_free(pcic->pc_intr_htblp[i]);
4899 4897 (void) pcmcia_return_intr(pcic->dip, i);
4900 4898 #if defined(PCIC_DEBUG)
4901 4899 if (pcic_debug) {
4902 4900 cmn_err(CE_CONT,
4903 4901 "removing interrupt %d at %s "
4904 4902 "priority\n", i, "high");
4905 4903 cmn_err(CE_CONT,
4906 4904 "ddi_remove_intr(%p, %x, %p)\n",
4907 4905 (void *)dip,
4908 4906 0,
4909 4907 (void *)intr->iblk_cookie);
4910 4908 }
4911 4909 #endif
4912 4910 }
4913 4911 prev->next = intr->next;
4914 4912 kmem_free(intr, sizeof (inthandler_t));
4915 4913 intr = prev->next;
4916 4914 } else {
4917 4915 prev = intr;
4918 4916 intr = intr->next;
4919 4917 } /* if (handler_id) */
4920 4918 } /* while */
4921 4919
4922 4920 mutex_exit(&pcic->pc_lock);
4923 4921 }
4924 4922
4925 4923 #if defined(PCIC_DEBUG)
4926 4924 if (pcic_debug) {
4927 4925 cmn_err(CE_CONT,
4928 4926 "pcic_clear_interrupt: exit irq_top=%p\n",
4929 4927 (void *)pcic->irq_top);
4930 4928 }
4931 4929 #endif
4932 4930
4933 4931
4934 4932 return (SUCCESS);
4935 4933 }
4936 4934
4937 4935 struct intel_regs {
4938 4936 char *name;
4939 4937 int off;
4940 4938 char *fmt;
4941 4939 } iregs[] = {
4942 4940 {"ident ", 0},
4943 4941 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"},
4944 4942 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO"
4945 4943 "\7DRD\10OE"},
4946 4944 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"},
4947 4945 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"},
4948 4946 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"},
4949 4947 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"},
4950 4948 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"},
4951 4949 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"},
4952 4950 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"},
4953 4951 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"},
4954 4952 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"},
4955 4953 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"},
4956 4954 {"io0-slow ", 8},
4957 4955 {"io0-shi ", 9},
4958 4956 {"io0-elow ", 0xa},
4959 4957 {"io0-ehi ", 0xb},
4960 4958 {"io1-slow ", 0xc},
4961 4959 {"io1-shi ", 0xd},
4962 4960 {"io1-elow ", 0xe},
4963 4961 {"io1-ehi ", 0xf},
4964 4962 {"mem0-slow ", 0x10},
4965 4963 {"mem0-shi ", 0x11, "\020\7ZW\10DS"},
4966 4964 {"mem0-elow ", 0x12},
4967 4965 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"},
4968 4966 {"card0-low ", 0x14},
4969 4967 {"card0-hi ", 0x15, "\020\7AM\10WP"},
4970 4968 {"mem1-slow ", 0x18},
4971 4969 {"mem1-shi ", 0x19, "\020\7ZW\10DS"},
4972 4970 {"mem1-elow ", 0x1a},
4973 4971 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"},
4974 4972 {"card1-low ", 0x1c},
4975 4973 {"card1-hi ", 0x1d, "\020\7AM\10WP"},
4976 4974 {"mem2-slow ", 0x20},
4977 4975 {"mem2-shi ", 0x21, "\020\7ZW\10DS"},
4978 4976 {"mem2-elow ", 0x22},
4979 4977 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"},
4980 4978 {"card2-low ", 0x24},
4981 4979 {"card2-hi ", 0x25, "\020\7AM\10WP"},
4982 4980 {"mem3-slow ", 0x28},
4983 4981 {"mem3-shi ", 0x29, "\020\7ZW\10DS"},
4984 4982 {"mem3-elow ", 0x2a},
4985 4983 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"},
4986 4984 {"card3-low ", 0x2c},
4987 4985 {"card3-hi ", 0x2d, "\020\7AM\10WP"},
4988 4986
4989 4987 {"mem4-slow ", 0x30},
4990 4988 {"mem4-shi ", 0x31, "\020\7ZW\10DS"},
4991 4989 {"mem4-elow ", 0x32},
4992 4990 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"},
4993 4991 {"card4-low ", 0x34},
4994 4992 {"card4-hi ", 0x35, "\020\7AM\10WP"},
4995 4993 {"mpage0 ", 0x40},
4996 4994 {"mpage1 ", 0x41},
4997 4995 {"mpage2 ", 0x42},
4998 4996 {"mpage3 ", 0x43},
4999 4997 {"mpage4 ", 0x44},
5000 4998 {NULL},
5001 4999 };
5002 5000
5003 5001 static struct intel_regs cregs[] = {
5004 5002 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"},
5005 5003 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"},
5006 5004 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"},
5007 5005 {"chip-info ", 0x1f, "\20\6DUAL"},
5008 5006 {"IO-offlow0", 0x36},
5009 5007 {"IO-offhi0 ", 0x37},
5010 5008 {"IO-offlow1", 0x38},
5011 5009 {"IO-offhi1 ", 0x39},
5012 5010 NULL,
5013 5011 };
5014 5012
5015 5013 static struct intel_regs cxregs[] = {
5016 5014 {"ext-ctl-1 ", 0x03,
5017 5015 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"},
5018 5016 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"},
5019 5017 {"mem0-up ", 0x05},
5020 5018 {"mem1-up ", 0x06},
5021 5019 {"mem2-up ", 0x07},
5022 5020 {"mem3-up ", 0x08},
5023 5021 {"mem4-up ", 0x09},
5024 5022 {NULL}
5025 5023 };
5026 5024
5027 5025 void
5028 5026 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len)
5029 5027 {
5030 5028 int i, value, j;
5031 5029 char buff[256];
5032 5030 char *fmt;
5033 5031
5034 5032 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n");
5035 5033 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) {
5036 5034 int sval;
5037 5035 if (cregs[i].off == PCIC_MISC_CTL_2)
5038 5036 sval = 0;
5039 5037 else
5040 5038 sval = socket;
5041 5039 value = pcic_getb(pcic, sval, cregs[i].off);
5042 5040 if (i & 1) {
5043 5041 if (cregs[i].fmt)
5044 5042 fmt = "%s\t%s\t%b\n";
5045 5043 else
5046 5044 fmt = "%s\t%s\t%x\n";
5047 5045 cmn_err(CE_CONT, fmt, buff,
5048 5046 cregs[i].name, value, cregs[i].fmt);
5049 5047 buff[0] = '\0';
5050 5048 } else {
5051 5049 if (cregs[i].fmt)
5052 5050 fmt = "\t%s\t%b";
5053 5051 else
5054 5052 fmt = "\t%s\t%x";
5055 5053 (void) sprintf(buff, fmt,
5056 5054 cregs[i].name, value, cregs[i].fmt);
5057 5055 for (j = strlen(buff); j < 40; j++)
5058 5056 buff[j] = ' ';
5059 5057 buff[40] = '\0';
5060 5058 }
5061 5059 }
5062 5060 cmn_err(CE_CONT, "%s\n", buff);
5063 5061
5064 5062 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0);
5065 5063 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1);
5066 5064 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j);
5067 5065
5068 5066 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0);
5069 5067 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1);
5070 5068 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j);
5071 5069
5072 5070 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0);
5073 5071 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1);
5074 5072 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j);
5075 5073
5076 5074 cmn_err(CE_CONT, "--------- Extended Registers --------\n");
5077 5075
5078 5076 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) {
5079 5077 value = clext_reg_read(pcic, socket, cxregs[i].off);
5080 5078 if (i & 1) {
5081 5079 if (cxregs[i].fmt)
5082 5080 fmt = "%s\t%s\t%b\n";
5083 5081 else
5084 5082 fmt = "%s\t%s\t%x\n";
5085 5083 cmn_err(CE_CONT, fmt, buff,
5086 5084 cxregs[i].name, value, cxregs[i].fmt);
5087 5085 buff[0] = '\0';
5088 5086 } else {
5089 5087 if (cxregs[i].fmt)
5090 5088 fmt = "\t%s\t%b";
5091 5089 else
5092 5090 fmt = "\t%s\t%x";
5093 5091 (void) sprintf(buff, fmt,
5094 5092 cxregs[i].name, value, cxregs[i].fmt);
5095 5093 for (j = strlen(buff); j < 40; j++)
5096 5094 buff[j] = ' ';
5097 5095 buff[40] = '\0';
5098 5096 }
5099 5097 }
5100 5098 }
5101 5099
5102 5100 #if defined(PCIC_DEBUG)
5103 5101 static void
5104 5102 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len)
5105 5103 {
5106 5104 int i, value, j;
5107 5105 char buff[256];
5108 5106 char *fmt;
5109 5107
5110 5108 #if defined(PCIC_DEBUG)
5111 5109 if (pcic_debug < 2)
5112 5110 return;
5113 5111 #endif
5114 5112 cmn_err(CE_CONT,
5115 5113 "----------- PCIC Registers for socket %d---------\n",
5116 5114 socket);
5117 5115 cmn_err(CE_CONT,
5118 5116 "\tname value name value\n");
5119 5117
5120 5118 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) {
5121 5119 value = pcic_getb(pcic, socket, iregs[i].off);
5122 5120 if (i & 1) {
5123 5121 if (iregs[i].fmt)
5124 5122 fmt = "%s\t%s\t%b\n";
5125 5123 else
5126 5124 fmt = "%s\t%s\t%x\n";
5127 5125 cmn_err(CE_CONT, fmt, buff,
5128 5126 iregs[i].name, value, iregs[i].fmt);
5129 5127 buff[0] = '\0';
5130 5128 } else {
5131 5129 if (iregs[i].fmt)
5132 5130 fmt = "\t%s\t%b";
5133 5131 else
5134 5132 fmt = "\t%s\t%x";
5135 5133 (void) sprintf(buff, fmt,
5136 5134 iregs[i].name, value, iregs[i].fmt);
5137 5135 for (j = strlen(buff); j < 40; j++)
5138 5136 buff[j] = ' ';
5139 5137 buff[40] = '\0';
5140 5138 }
5141 5139 }
5142 5140 switch (pcic->pc_type) {
5143 5141 case PCIC_CL_PD6710:
5144 5142 case PCIC_CL_PD6722:
5145 5143 case PCIC_CL_PD6729:
5146 5144 case PCIC_CL_PD6832:
5147 5145 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF);
5148 5146 break;
5149 5147 }
5150 5148 cmn_err(CE_CONT, "%s\n", buff);
5151 5149 }
5152 5150 #endif
5153 5151
5154 5152 /*
5155 5153 * pcic_mswait(ms)
5156 5154 * sleep ms milliseconds
5157 5155 * call drv_usecwait once for each ms
5158 5156 */
5159 5157 static void
5160 5158 pcic_mswait(pcicdev_t *pcic, int socket, int ms)
5161 5159 {
5162 5160 if (ms) {
5163 5161 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING;
5164 5162 pcic_mutex_exit(&pcic->pc_lock);
5165 5163 delay(drv_usectohz(ms*1000));
5166 5164 pcic_mutex_enter(&pcic->pc_lock);
5167 5165 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING;
5168 5166 }
5169 5167 }
5170 5168
5171 5169 /*
5172 5170 * pcic_check_ready(pcic, index, off)
5173 5171 * Wait for card to come ready
5174 5172 * We only wait if the card is NOT in RESET
5175 5173 * and power is on.
5176 5174 */
5177 5175 static boolean_t
5178 5176 pcic_check_ready(pcicdev_t *pcic, int socket)
5179 5177 {
5180 5178 int ifstate, intstate;
5181 5179
5182 5180 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT);
5183 5181 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS);
5184 5182
5185 5183 if ((intstate & PCIC_RESET) &&
5186 5184 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) ==
5187 5185 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK)))
5188 5186 return (B_TRUE);
5189 5187
5190 5188 #ifdef PCIC_DEBUG
5191 5189 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, "
5192 5190 "ifstate = 0x%x\n", intstate, ifstate);
5193 5191 if (pcic_debug) {
5194 5192 pcic_debug += 4;
5195 5193 xxdmp_all_regs(pcic, socket, -1);
5196 5194 pcic_debug -= 4;
5197 5195 }
5198 5196 #endif
5199 5197 return (B_FALSE);
5200 5198 }
5201 5199
5202 5200 /*
5203 5201 * Cirrus Logic extended register read/write routines
5204 5202 */
5205 5203 static int
5206 5204 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg)
5207 5205 {
5208 5206 int val;
5209 5207
5210 5208 switch (pcic->pc_io_type) {
5211 5209 case PCIC_IO_TYPE_YENTA:
5212 5210 val = ddi_get8(pcic->handle,
5213 5211 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg);
5214 5212 break;
5215 5213 default:
5216 5214 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg);
5217 5215 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1);
5218 5216 break;
5219 5217 }
5220 5218
5221 5219 return (val);
5222 5220 }
5223 5221
5224 5222 static void
5225 5223 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value)
5226 5224 {
5227 5225 switch (pcic->pc_io_type) {
5228 5226 case PCIC_IO_TYPE_YENTA:
5229 5227 ddi_put8(pcic->handle,
5230 5228 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value);
5231 5229 break;
5232 5230 default:
5233 5231 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg);
5234 5232 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value);
5235 5233 break;
5236 5234 }
5237 5235 }
5238 5236
5239 5237 /*
5240 5238 * Misc PCI functions
5241 5239 */
5242 5240 static void
5243 5241 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags)
5244 5242 {
5245 5243 unsigned cmd;
5246 5244
5247 5245 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) {
5248 5246 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4));
5249 5247 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) ==
5250 5248 (PCI_COMM_IO|PCI_COMM_MAE))
5251 5249 return;
5252 5250
5253 5251 if (flags & PCIC_ENABLE_IO)
5254 5252 cmd |= PCI_COMM_IO;
5255 5253
5256 5254 if (flags & PCIC_ENABLE_MEM)
5257 5255 cmd |= PCI_COMM_MAE;
5258 5256
5259 5257 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd);
5260 5258 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */
5261 5259 }
5262 5260
5263 5261 /*
5264 5262 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type
5265 5263 */
5266 5264 static int
5267 5265 pcic_find_pci_type(pcicdev_t *pcic)
5268 5266 {
5269 5267 uint32_t vend, device;
5270 5268
5271 5269 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip,
5272 5270 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS,
5273 5271 "vendor-id", -1);
5274 5272 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip,
5275 5273 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS,
5276 5274 "device-id", -1);
5277 5275
5278 5276 device = PCI_ID(vend, device);
5279 5277 pcic->pc_type = device;
5280 5278 pcic->pc_chipname = "PCI:unknown";
5281 5279
5282 5280 switch (device) {
5283 5281 case PCIC_INTEL_i82092:
5284 5282 pcic->pc_chipname = PCIC_TYPE_i82092;
5285 5283 break;
5286 5284 case PCIC_CL_PD6729:
5287 5285 pcic->pc_chipname = PCIC_TYPE_PD6729;
5288 5286 /*
5289 5287 * Some 6730's incorrectly identify themselves
5290 5288 * as a 6729, so we need to do some more tests
5291 5289 * here to see if the device that's claiming
5292 5290 * to be a 6729 is really a 6730.
5293 5291 */
5294 5292 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) &
5295 5293 PCIC_CLEXT_MISC_CTL_3_REV_MASK) ==
5296 5294 0) {
5297 5295 pcic->pc_chipname = PCIC_TYPE_PD6730;
5298 5296 pcic->pc_type = PCIC_CL_PD6730;
5299 5297 }
5300 5298 break;
5301 5299 case PCIC_CL_PD6730:
5302 5300 pcic->pc_chipname = PCIC_TYPE_PD6730;
5303 5301 break;
5304 5302 case PCIC_CL_PD6832:
5305 5303 pcic->pc_chipname = PCIC_TYPE_PD6832;
5306 5304 break;
5307 5305 case PCIC_SMC_34C90:
5308 5306 pcic->pc_chipname = PCIC_TYPE_34C90;
5309 5307 break;
5310 5308 case PCIC_TOSHIBA_TOPIC95:
5311 5309 pcic->pc_chipname = PCIC_TYPE_TOPIC95;
5312 5310 break;
5313 5311 case PCIC_TOSHIBA_TOPIC100:
5314 5312 pcic->pc_chipname = PCIC_TYPE_TOPIC100;
5315 5313 break;
5316 5314 case PCIC_TI_PCI1031:
5317 5315 pcic->pc_chipname = PCIC_TYPE_PCI1031;
5318 5316 break;
5319 5317 case PCIC_TI_PCI1130:
5320 5318 pcic->pc_chipname = PCIC_TYPE_PCI1130;
5321 5319 break;
5322 5320 case PCIC_TI_PCI1131:
5323 5321 pcic->pc_chipname = PCIC_TYPE_PCI1131;
5324 5322 break;
5325 5323 case PCIC_TI_PCI1250:
5326 5324 pcic->pc_chipname = PCIC_TYPE_PCI1250;
5327 5325 break;
5328 5326 case PCIC_TI_PCI1225:
5329 5327 pcic->pc_chipname = PCIC_TYPE_PCI1225;
5330 5328 break;
5331 5329 case PCIC_TI_PCI1410:
5332 5330 pcic->pc_chipname = PCIC_TYPE_PCI1410;
5333 5331 break;
5334 5332 case PCIC_TI_PCI1510:
5335 5333 pcic->pc_chipname = PCIC_TYPE_PCI1510;
5336 5334 break;
5337 5335 case PCIC_TI_PCI1520:
5338 5336 pcic->pc_chipname = PCIC_TYPE_PCI1520;
5339 5337 break;
5340 5338 case PCIC_TI_PCI1221:
5341 5339 pcic->pc_chipname = PCIC_TYPE_PCI1221;
5342 5340 break;
5343 5341 case PCIC_TI_PCI1050:
5344 5342 pcic->pc_chipname = PCIC_TYPE_PCI1050;
5345 5343 break;
5346 5344 case PCIC_ENE_1410:
5347 5345 pcic->pc_chipname = PCIC_TYPE_1410;
5348 5346 break;
5349 5347 case PCIC_O2_OZ6912:
5350 5348 pcic->pc_chipname = PCIC_TYPE_OZ6912;
5351 5349 break;
5352 5350 case PCIC_RICOH_RL5C466:
5353 5351 pcic->pc_chipname = PCIC_TYPE_RL5C466;
5354 5352 break;
5355 5353 case PCIC_TI_PCI1420:
5356 5354 pcic->pc_chipname = PCIC_TYPE_PCI1420;
5357 5355 break;
5358 5356 case PCIC_ENE_1420:
5359 5357 pcic->pc_chipname = PCIC_TYPE_1420;
5360 5358 break;
5361 5359 default:
5362 5360 switch (PCI_ID(vend, (uint32_t)0)) {
5363 5361 case PCIC_TOSHIBA_VENDOR:
5364 5362 pcic->pc_chipname = PCIC_TYPE_TOSHIBA;
5365 5363 pcic->pc_type = PCIC_TOSHIBA_VENDOR;
5366 5364 break;
5367 5365 case PCIC_TI_VENDOR:
5368 5366 pcic->pc_chipname = PCIC_TYPE_TI;
5369 5367 pcic->pc_type = PCIC_TI_VENDOR;
5370 5368 break;
5371 5369 case PCIC_O2MICRO_VENDOR:
5372 5370 pcic->pc_chipname = PCIC_TYPE_O2MICRO;
5373 5371 pcic->pc_type = PCIC_O2MICRO_VENDOR;
5374 5372 break;
5375 5373 case PCIC_RICOH_VENDOR:
5376 5374 pcic->pc_chipname = PCIC_TYPE_RICOH;
5377 5375 pcic->pc_type = PCIC_RICOH_VENDOR;
5378 5376 break;
5379 5377 default:
5380 5378 if (!(pcic->pc_flags & PCF_CARDBUS))
5381 5379 return (DDI_FAILURE);
5382 5380 pcic->pc_chipname = PCIC_TYPE_YENTA;
5383 5381 break;
5384 5382 }
5385 5383 }
5386 5384 return (DDI_SUCCESS);
5387 5385 }
5388 5386
5389 5387 static void
5390 5388 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state)
5391 5389 {
5392 5390 uchar_t ppirr = ddi_get8(pcic->cfg_handle,
5393 5391 pcic->cfgaddr + PCIC_82092_PPIRR);
5394 5392 uchar_t val;
5395 5393
5396 5394 if (intr == PCIC_82092_CTL_SMI) {
5397 5395 val = PCIC_82092_SMI_CTL(socket,
5398 5396 PCIC_82092_INT_DISABLE);
5399 5397 ppirr &= ~val;
5400 5398 val = PCIC_82092_SMI_CTL(socket, state);
5401 5399 ppirr |= val;
5402 5400 } else {
5403 5401 val = PCIC_82092_IRQ_CTL(socket,
5404 5402 PCIC_82092_INT_DISABLE);
5405 5403 ppirr &= ~val;
5406 5404 val = PCIC_82092_IRQ_CTL(socket, state);
5407 5405 ppirr |= val;
5408 5406 }
5409 5407 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR,
5410 5408 ppirr);
5411 5409 }
5412 5410
5413 5411 static uint_t
5414 5412 pcic_cd_softint(caddr_t arg1, caddr_t arg2)
5415 5413 {
5416 5414 pcic_socket_t *sockp = (pcic_socket_t *)arg1;
5417 5415 uint_t rc = DDI_INTR_UNCLAIMED;
5418 5416
5419 5417 _NOTE(ARGUNUSED(arg2))
5420 5418
5421 5419 mutex_enter(&sockp->pcs_pcic->pc_lock);
5422 5420 if (sockp->pcs_cd_softint_flg) {
5423 5421 uint8_t status;
5424 5422 sockp->pcs_cd_softint_flg = 0;
5425 5423 rc = DDI_INTR_CLAIMED;
5426 5424 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket,
5427 5425 PCIC_INTERFACE_STATUS);
5428 5426 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status);
5429 5427 }
5430 5428 mutex_exit(&sockp->pcs_pcic->pc_lock);
5431 5429 return (rc);
5432 5430 }
5433 5431
5434 5432 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT;
5435 5433 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME;
5436 5434 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT;
5437 5435
5438 5436 #ifdef CARDBUS
5439 5437 static uint32_t pcic_cbps_on = 0;
5440 5438 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK |
5441 5439 CB_PS_XVCARD | CB_PS_YVCARD;
5442 5440 #else
5443 5441 static uint32_t pcic_cbps_on = CB_PS_16BITCARD;
5444 5442 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK |
5445 5443 CB_PS_CBCARD |
5446 5444 CB_PS_XVCARD | CB_PS_YVCARD;
5447 5445 #endif
5448 5446 static void
5449 5447 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status)
5450 5448 {
5451 5449 boolean_t do_debounce = B_FALSE;
5452 5450 int debounce_time = drv_usectohz(pcic_debounce_time);
5453 5451 uint8_t irq;
5454 5452 timeout_id_t debounce;
5455 5453
5456 5454 /*
5457 5455 * Always reset debounce but may need to check original state later.
5458 5456 */
5459 5457 debounce = sockp->pcs_debounce_id;
5460 5458 sockp->pcs_debounce_id = 0;
5461 5459
5462 5460 /*
5463 5461 * Check to see whether a card is present or not. There are
5464 5462 * only two states that we are concerned with - the state
5465 5463 * where both CD pins are asserted, which means that the
5466 5464 * card is fully seated, and the state where neither CD
5467 5465 * pin is asserted, which means that the card is not
5468 5466 * present.
5469 5467 * The CD signals are generally very noisy and cause a lot of
5470 5468 * contact bounce as the card is being inserted and
5471 5469 * removed, so we need to do some software debouncing.
5472 5470 */
5473 5471
5474 5472 #ifdef PCIC_DEBUG
5475 5473 pcic_err(pcic->dip, 6,
5476 5474 "pcic%d handle_cd_change: socket %d card status 0x%x"
5477 5475 " deb 0x%p\n", ddi_get_instance(pcic->dip),
5478 5476 sockp->pcs_socket, status, debounce);
5479 5477 #endif
5480 5478 switch (status & PCIC_ISTAT_CD_MASK) {
5481 5479 case PCIC_CD_PRESENT_OK:
5482 5480 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM);
5483 5481 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) {
5484 5482 uint32_t cbps;
5485 5483 #ifdef PCIC_DEBUG
5486 5484 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags);
5487 5485 #endif
5488 5486 cbps = pcic_getcb(pcic, CB_PRESENT_STATE);
5489 5487 #ifdef PCIC_DEBUG
5490 5488 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps);
5491 5489 #endif
5492 5490 /*
5493 5491 * Check the CB bits are sane.
5494 5492 */
5495 5493 if ((cbps & pcic_cbps_on) != pcic_cbps_on ||
5496 5494 cbps & pcic_cbps_off) {
5497 5495 cmn_err(CE_WARN,
5498 5496 "%s%d: Odd Cardbus Present State 0x%x\n",
5499 5497 ddi_get_name(pcic->dip),
5500 5498 ddi_get_instance(pcic->dip),
5501 5499 cbps);
5502 5500 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST);
5503 5501 debounce = 0;
5504 5502 debounce_time = drv_usectohz(1000000);
5505 5503 }
5506 5504 if (debounce) {
5507 5505 sockp->pcs_flags |= PCS_CARD_PRESENT;
5508 5506 if (pcic_do_insertion) {
5509 5507
5510 5508 cbps = pcic_getcb(pcic, CB_PRESENT_STATE);
5511 5509
5512 5510 if (cbps & CB_PS_16BITCARD) {
5513 5511 pcic_err(pcic->dip,
5514 5512 8, "16 bit card inserted\n");
5515 5513 sockp->pcs_flags |= PCS_CARD_IS16BIT;
5516 5514 /* calls pcm_adapter_callback() */
5517 5515 if (pcic->pc_callback) {
5518 5516
5519 5517 (void) ddi_prop_update_string(
5520 5518 DDI_DEV_T_NONE,
5521 5519 pcic->dip, PCM_DEVICETYPE,
5522 5520 "pccard");
5523 5521 PC_CALLBACK(pcic->dip,
5524 5522 pcic->pc_cb_arg,
5525 5523 PCE_CARD_INSERT,
5526 5524 sockp->pcs_socket);
5527 5525 }
5528 5526 } else if (cbps & CB_PS_CBCARD) {
5529 5527 pcic_err(pcic->dip,
5530 5528 8, "32 bit card inserted\n");
5531 5529
5532 5530 if (pcic->pc_flags & PCF_CARDBUS) {
5533 5531 sockp->pcs_flags |=
5534 5532 PCS_CARD_ISCARDBUS;
5535 5533 #ifdef CARDBUS
5536 5534 if (!pcic_load_cardbus(pcic,
5537 5535 sockp)) {
5538 5536 pcic_unload_cardbus(
5539 5537 pcic, sockp);
5540 5538 }
5541 5539
5542 5540 #else
5543 5541 cmn_err(CE_NOTE,
5544 5542 "32 bit Cardbus not"
5545 5543 " supported in"
5546 5544 " this device driver\n");
5547 5545 #endif
5548 5546 } else {
5549 5547 /*
5550 5548 * Ignore the card
5551 5549 */
5552 5550 cmn_err(CE_NOTE,
5553 5551 "32 bit Cardbus not"
5554 5552 " supported on this"
5555 5553 " device\n");
5556 5554 }
5557 5555 } else {
5558 5556 cmn_err(CE_NOTE,
5559 5557 "Unsupported PCMCIA card"
5560 5558 " inserted\n");
5561 5559 }
5562 5560 }
5563 5561 } else {
5564 5562 do_debounce = B_TRUE;
5565 5563 }
5566 5564 } else {
5567 5565 /*
5568 5566 * It is possible to come through here if the system
5569 5567 * starts up with cards already inserted. Do nothing
5570 5568 * and don't worry about it.
5571 5569 */
5572 5570 #ifdef PCIC_DEBUG
5573 5571 pcic_err(pcic->dip, 5,
5574 5572 "pcic%d: Odd card insertion indication on socket %d\n",
5575 5573 ddi_get_instance(pcic->dip),
5576 5574 sockp->pcs_socket);
5577 5575 #endif
5578 5576 }
5579 5577 break;
5580 5578
5581 5579 default:
5582 5580 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) {
5583 5581 /*
5584 5582 * Someone has started to insert a card so delay a while.
5585 5583 */
5586 5584 do_debounce = B_TRUE;
5587 5585 break;
5588 5586 }
5589 5587 /*
5590 5588 * Otherwise this is basically the same as not present
5591 5589 * so fall through.
5592 5590 */
5593 5591
5594 5592 /* FALLTHRU */
5595 5593 case 0:
5596 5594 if (sockp->pcs_flags & PCS_CARD_PRESENT) {
5597 5595 if (pcic->pc_flags & PCF_CBPWRCTL) {
5598 5596 pcic_putcb(pcic, CB_CONTROL, 0);
5599 5597 } else {
5600 5598 pcic_putb(pcic, sockp->pcs_socket,
5601 5599 PCIC_POWER_CONTROL, 0);
5602 5600 (void) pcic_getb(pcic, sockp->pcs_socket,
5603 5601 PCIC_POWER_CONTROL);
5604 5602 }
5605 5603 #ifdef PCIC_DEBUG
5606 5604 pcic_err(pcic->dip, 8, "Card removed\n");
5607 5605 #endif
5608 5606 sockp->pcs_flags &= ~PCS_CARD_PRESENT;
5609 5607
5610 5608 if (sockp->pcs_flags & PCS_CARD_IS16BIT) {
5611 5609 sockp->pcs_flags &= ~PCS_CARD_IS16BIT;
5612 5610 if (pcic_do_removal && pcic->pc_callback) {
5613 5611 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg,
5614 5612 PCE_CARD_REMOVAL, sockp->pcs_socket);
5615 5613 }
5616 5614 }
5617 5615 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) {
5618 5616 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS;
5619 5617 sockp->pcs_flags |= PCS_CARD_CBREM;
5620 5618 }
5621 5619 sockp->pcs_flags |= PCS_CARD_REMOVED;
5622 5620
5623 5621 do_debounce = B_TRUE;
5624 5622 }
5625 5623 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) {
5626 5624 if (sockp->pcs_flags & PCS_CARD_CBREM) {
5627 5625 /*
5628 5626 * Ensure that we do the unloading in the
5629 5627 * debounce handler, that way we're not doing
5630 5628 * nasty things in an interrupt handler. e.g.
5631 5629 * a USB device will wait for data which will
5632 5630 * obviously never come because we've
5633 5631 * unplugged the device, but the wait will
5634 5632 * wait forever because no interrupts can
5635 5633 * come in...
5636 5634 */
5637 5635 #ifdef CARDBUS
5638 5636 pcic_unload_cardbus(pcic, sockp);
5639 5637 /* pcic_dump_all(pcic); */
5640 5638 #endif
5641 5639 sockp->pcs_flags &= ~PCS_CARD_CBREM;
5642 5640 }
5643 5641 sockp->pcs_flags &= ~PCS_CARD_REMOVED;
5644 5642 }
5645 5643 break;
5646 5644 } /* switch */
5647 5645
5648 5646 if (do_debounce) {
5649 5647 /*
5650 5648 * Delay doing
5651 5649 * anything for a while so that things can settle
5652 5650 * down a little. Interrupts are already disabled.
5653 5651 * Reset the state and we'll reevaluate the
5654 5652 * whole kit 'n kaboodle when the timeout fires
5655 5653 */
5656 5654 #ifdef PCIC_DEBUG
5657 5655 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for "
5658 5656 "socket %d.%d\n",
5659 5657 ddi_get_instance(pcic->dip),
5660 5658 sockp->pcs_socket);
5661 5659 #endif
5662 5660 sockp->pcs_debounce_id =
5663 5661 pcic_add_debqueue(sockp, debounce_time);
5664 5662
5665 5663 /*
5666 5664 * We bug out here without re-enabling interrupts. They will
5667 5665 * be re-enabled when the debounce timeout swings through
5668 5666 * here.
5669 5667 */
5670 5668 return;
5671 5669 }
5672 5670
5673 5671 /*
5674 5672 * Turn on Card detect interrupts. Other interrupts will be
5675 5673 * enabled during set_socket calls.
5676 5674 *
5677 5675 * Note that set_socket only changes interrupt settings when there
5678 5676 * is a card present.
5679 5677 */
5680 5678 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT);
5681 5679 irq |= PCIC_CD_DETECT;
5682 5680 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq);
5683 5681 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK);
5684 5682
5685 5683 /* Out from debouncing state */
5686 5684 sockp->pcs_flags &= ~PCS_DEBOUNCING;
5687 5685
5688 5686 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n");
5689 5687 }
5690 5688
5691 5689 /*
5692 5690 * pcic_getb()
5693 5691 * get an I/O byte based on the yardware decode method
5694 5692 */
5695 5693 static uint8_t
5696 5694 pcic_getb(pcicdev_t *pcic, int socket, int reg)
5697 5695 {
5698 5696 int work;
5699 5697
5700 5698 #if defined(PCIC_DEBUG)
5701 5699 if (pcic_debug == 0x7fff) {
5702 5700 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n",
5703 5701 (void *)pcic, socket, reg);
5704 5702 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n",
5705 5703 pcic->pc_io_type, (void *)pcic->handle,
5706 5704 (void *)pcic->ioaddr);
5707 5705 }
5708 5706 #endif
5709 5707
5710 5708 switch (pcic->pc_io_type) {
5711 5709 case PCIC_IO_TYPE_YENTA:
5712 5710 return (ddi_get8(pcic->handle,
5713 5711 pcic->ioaddr + CB_R2_OFFSET + reg));
5714 5712 default:
5715 5713 work = (socket * PCIC_SOCKET_1) | reg;
5716 5714 ddi_put8(pcic->handle, pcic->ioaddr, work);
5717 5715 return (ddi_get8(pcic->handle, pcic->ioaddr + 1));
5718 5716 }
5719 5717 }
5720 5718
5721 5719 static void
5722 5720 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value)
5723 5721 {
5724 5722 int work;
5725 5723
5726 5724 #if defined(PCIC_DEBUG)
5727 5725 if (pcic_debug == 0x7fff) {
5728 5726 cmn_err(CE_CONT,
5729 5727 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n",
5730 5728 (void *)pcic, socket, reg, value);
5731 5729 cmn_err(CE_CONT,
5732 5730 "pcic_putb1: type=%d handle=%p ioaddr=%p \n",
5733 5731 pcic->pc_io_type, (void *)pcic->handle,
5734 5732 (void *)pcic->ioaddr);
5735 5733 }
5736 5734 #endif
5737 5735
5738 5736
5739 5737 switch (pcic->pc_io_type) {
5740 5738 case PCIC_IO_TYPE_YENTA:
5741 5739 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg,
5742 5740 value);
5743 5741 break;
5744 5742 default:
5745 5743 work = (socket * PCIC_SOCKET_1) | reg;
5746 5744 ddi_put8(pcic->handle, pcic->ioaddr, work);
5747 5745 ddi_put8(pcic->handle, pcic->ioaddr + 1, value);
5748 5746 break;
5749 5747 }
5750 5748 }
5751 5749
5752 5750 /*
5753 5751 * chip identification functions
5754 5752 */
5755 5753
5756 5754 /*
5757 5755 * chip identification: Cirrus Logic PD6710/6720/6722
5758 5756 */
5759 5757 static int
5760 5758 pcic_ci_cirrus(pcicdev_t *pcic)
5761 5759 {
5762 5760 int value1, value2;
5763 5761
5764 5762 /* Init the CL id mode */
5765 5763 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO);
5766 5764 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0);
5767 5765 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO);
5768 5766 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO);
5769 5767
5770 5768 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID &&
5771 5769 (value2 & PCIC_CI_ID) == 0) {
5772 5770 /* chip is a Cirrus Logic and not Intel */
5773 5771 pcic->pc_type = PCIC_CL_PD6710;
5774 5772 if (value1 & PCIC_CI_SLOTS)
5775 5773 pcic->pc_chipname = PCIC_TYPE_PD6720;
5776 5774 else
5777 5775 pcic->pc_chipname = PCIC_TYPE_PD6710;
5778 5776 /* now fine tune things just in case a 6722 */
5779 5777 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0);
5780 5778 if (value1 == 0) {
5781 5779 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55);
5782 5780 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH);
5783 5781 if (value1 == 0x55) {
5784 5782 pcic->pc_chipname = PCIC_TYPE_PD6722;
5785 5783 pcic->pc_type = PCIC_CL_PD6722;
5786 5784 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0);
5787 5785 }
5788 5786 }
5789 5787 return (1);
5790 5788 }
5791 5789 return (0);
5792 5790 }
5793 5791
5794 5792 /*
5795 5793 * chip identification: Vadem (VG365/465/468/469)
5796 5794 */
5797 5795
5798 5796 static void
5799 5797 pcic_vadem_enable(pcicdev_t *pcic)
5800 5798 {
5801 5799 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1);
5802 5800 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2);
5803 5801 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg);
5804 5802 }
5805 5803
5806 5804 static int
5807 5805 pcic_ci_vadem(pcicdev_t *pcic)
5808 5806 {
5809 5807 int value;
5810 5808
5811 5809 pcic_vadem_enable(pcic);
5812 5810 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION);
5813 5811 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF);
5814 5812 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) ==
5815 5813 (value | PCIC_VADEM_D3) ||
5816 5814 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) ==
5817 5815 PCIC_VADEM_469) {
5818 5816 int vadem, new;
5819 5817 pcic_vadem_enable(pcic);
5820 5818 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) &
5821 5819 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV);
5822 5820 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK);
5823 5821 pcic_putb(pcic, 0, PCIC_VG_DMA, new);
5824 5822 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION);
5825 5823
5826 5824 /* want to lock but leave mouse or other on */
5827 5825 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem);
5828 5826 switch (value & PCIC_REV_MASK) {
5829 5827 case PCIC_VADEM_365:
5830 5828 pcic->pc_chipname = PCIC_VG_365;
5831 5829 pcic->pc_type = PCIC_VADEM;
5832 5830 break;
5833 5831 case PCIC_VADEM_465:
5834 5832 pcic->pc_chipname = PCIC_VG_465;
5835 5833 pcic->pc_type = PCIC_VADEM;
5836 5834 pcic->pc_flags |= PCF_1SOCKET;
5837 5835 break;
5838 5836 case PCIC_VADEM_468:
5839 5837 pcic->pc_chipname = PCIC_VG_468;
5840 5838 pcic->pc_type = PCIC_VADEM;
5841 5839 break;
5842 5840 case PCIC_VADEM_469:
5843 5841 pcic->pc_chipname = PCIC_VG_469;
5844 5842 pcic->pc_type = PCIC_VADEM_VG469;
5845 5843 break;
5846 5844 }
5847 5845 return (1);
5848 5846 }
5849 5847 return (0);
5850 5848 }
5851 5849
5852 5850 /*
5853 5851 * chip identification: Ricoh
5854 5852 */
5855 5853 static int
5856 5854 pcic_ci_ricoh(pcicdev_t *pcic)
5857 5855 {
5858 5856 int value;
5859 5857
5860 5858 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT);
5861 5859 switch (value) {
5862 5860 case PCIC_RF_296:
5863 5861 pcic->pc_type = PCIC_RICOH;
5864 5862 pcic->pc_chipname = PCIC_TYPE_RF5C296;
5865 5863 return (1);
5866 5864 case PCIC_RF_396:
5867 5865 pcic->pc_type = PCIC_RICOH;
5868 5866 pcic->pc_chipname = PCIC_TYPE_RF5C396;
5869 5867 return (1);
5870 5868 }
5871 5869 return (0);
5872 5870 }
5873 5871
5874 5872
5875 5873 /*
5876 5874 * set up available address spaces in busra
5877 5875 */
5878 5876 static void
5879 5877 pcic_init_assigned(dev_info_t *dip)
5880 5878 {
5881 5879 pcm_regs_t *pcic_avail_p;
5882 5880 pci_regspec_t *pci_avail_p, *regs;
5883 5881 int len, entries, rlen;
5884 5882 dev_info_t *pdip;
5885 5883
5886 5884 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
5887 5885 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) {
5888 5886 /*
5889 5887 * found "available" property at the cardbus/pcmcia node
5890 5888 * need to translate address space entries from pcmcia
5891 5889 * format to pci format
5892 5890 */
5893 5891 entries = len / sizeof (pcm_regs_t);
5894 5892 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries,
5895 5893 KM_SLEEP);
5896 5894 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p,
5897 5895 entries) == DDI_SUCCESS)
5898 5896 (void) pci_resource_setup_avail(dip, pci_avail_p,
5899 5897 entries);
5900 5898 kmem_free(pcic_avail_p, len);
5901 5899 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t));
5902 5900 return;
5903 5901 }
5904 5902
5905 5903 /*
5906 5904 * "legacy" platforms will have "available" property in pci node
5907 5905 */
5908 5906 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) {
5909 5907 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS,
5910 5908 "available", (caddr_t)&pci_avail_p, &len) ==
5911 5909 DDI_PROP_SUCCESS) {
5912 5910 /* (void) pci_resource_setup(pdip); */
5913 5911 kmem_free(pci_avail_p, len);
5914 5912 break;
5915 5913 }
5916 5914 }
5917 5915
5918 5916 if (pdip == NULL) {
5919 5917 int len;
5920 5918 char bus_type[16] = "(unknown)";
5921 5919 dev_info_t *par;
5922 5920
5923 5921 cmn_err(CE_CONT,
5924 5922 "?pcic_init_assigned: no available property for pcmcia\n");
5925 5923
5926 5924 /*
5927 5925 * This code is taken from pci_resource_setup() but does
5928 5926 * not attempt to use the "available" property to populate
5929 5927 * the ndi maps that are created.
5930 5928 * The fact that we will actually
5931 5929 * free some resource below (that was allocated by OBP)
5932 5930 * should be enough to be going on with.
5933 5931 */
5934 5932 for (par = dip; par != NULL; par = ddi_get_parent(par)) {
5935 5933 len = sizeof (bus_type);
5936 5934
5937 5935 if ((ddi_prop_op(DDI_DEV_T_ANY, par,
5938 5936 PROP_LEN_AND_VAL_BUF,
5939 5937 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS,
5940 5938 "device_type",
5941 5939 (caddr_t)&bus_type, &len) == DDI_SUCCESS) &&
5942 5940 (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 ||
5943 5941 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0))
5944 5942 break;
5945 5943 }
5946 5944 if (par != NULL &&
5947 5945 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS ||
5948 5946 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS))
5949 5947 par = NULL;
5950 5948 } else {
5951 5949 #ifdef CARDBUS
5952 5950 cardbus_bus_range_t *bus_range;
5953 5951 int k;
5954 5952
5955 5953 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range",
5956 5954 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) {
5957 5955 if (bus_range->lo != bus_range->hi)
5958 5956 pcic_err(pdip, 9, "allowable bus range is "
5959 5957 "%u->%u\n", bus_range->lo, bus_range->hi);
5960 5958 else {
5961 5959 pcic_err(pdip, 0,
5962 5960 "!No spare PCI bus numbers, range is "
5963 5961 "%u->%u, cardbus isn't usable\n",
5964 5962 bus_range->lo, bus_range->hi);
5965 5963 }
5966 5964 kmem_free(bus_range, k);
5967 5965 } else
5968 5966 pcic_err(pdip, 0, "!No bus-range property seems to "
5969 5967 "have been set up\n");
5970 5968 #endif
5971 5969 /*
5972 5970 * Have a valid parent with the "available" property
5973 5971 */
5974 5972 (void) pci_resource_setup(pdip);
5975 5973 }
5976 5974
5977 5975 if ((strcmp(ddi_get_name(dip), "pcma") == 0) &&
5978 5976 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
5979 5977 "assigned-addresses",
5980 5978 (caddr_t)®s, &rlen) == DDI_SUCCESS) {
5981 5979 ra_return_t ra;
5982 5980
5983 5981 /*
5984 5982 * On the UltraBook IIi the ranges are assigned under
5985 5983 * openboot. If we don't free them here the first I/O
5986 5984 * space that can be used is up above 0x10000 which
5987 5985 * doesn't work for this driver due to restrictions
5988 5986 * on the PCI I/O addresses the controllers can cope with.
5989 5987 * They are never going to be used by anything else
5990 5988 * so free them up to the general pool. AG.
5991 5989 */
5992 5990 pcic_err(dip, 1, "Free assigned addresses\n");
5993 5991
5994 5992 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) ==
5995 5993 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) &&
5996 5994 regs[0].pci_size_low == 0x1000000) {
5997 5995 ra.ra_addr_lo = regs[0].pci_phys_low;
5998 5996 ra.ra_len = regs[0].pci_size_low;
5999 5997 (void) pcmcia_free_mem(dip, &ra);
6000 5998 }
6001 5999 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) ==
6002 6000 PCI_REG_ADDR_G(PCI_ADDR_IO)) &&
6003 6001 (regs[1].pci_size_low == 0x8000 ||
6004 6002 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */
6005 6003 {
6006 6004 ra.ra_addr_lo = regs[1].pci_phys_low;
6007 6005 ra.ra_len = regs[1].pci_size_low;
6008 6006 (void) pcmcia_free_io(dip, &ra);
6009 6007 }
6010 6008 kmem_free((caddr_t)regs, rlen);
6011 6009 }
6012 6010 }
6013 6011
6014 6012 /*
6015 6013 * translate "available" from pcmcia format to pci format
6016 6014 */
6017 6015 static int
6018 6016 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p,
6019 6017 pci_regspec_t *pci_p, int entries)
6020 6018 {
6021 6019 int i, range_len, range_entries;
6022 6020 pcic_ranges_t *pcic_range_p;
6023 6021
6024 6022 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges",
6025 6023 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) {
6026 6024 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: "
6027 6025 "no ranges property for pcmcia\n");
6028 6026 return (DDI_FAILURE);
6029 6027 }
6030 6028
6031 6029 range_entries = range_len / sizeof (pcic_ranges_t);
6032 6030
6033 6031 /* for each "available" entry to be translated */
6034 6032 for (i = 0; i < entries; i++, pcic_p++, pci_p++) {
6035 6033 int j;
6036 6034 pcic_ranges_t *range_p = pcic_range_p;
6037 6035 pci_p->pci_phys_hi = -1u; /* default invalid value */
6038 6036
6039 6037 /* for each "ranges" entry to be searched */
6040 6038 for (j = 0; j < range_entries; j++, range_p++) {
6041 6039 uint64_t range_end = range_p->pcic_range_caddrlo +
6042 6040 range_p->pcic_range_size;
6043 6041 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len;
6044 6042
6045 6043 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) ||
6046 6044 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) ||
6047 6045 (range_end < avail_end))
6048 6046 continue;
6049 6047
6050 6048 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi;
6051 6049 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid;
6052 6050 pci_p->pci_phys_low = range_p->pcic_range_paddrlo
6053 6051 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo);
6054 6052 pci_p->pci_size_hi = 0;
6055 6053 pci_p->pci_size_low = pcic_p->phys_len;
6056 6054 }
6057 6055 }
6058 6056 kmem_free(pcic_range_p, range_len);
6059 6057 return (DDI_SUCCESS);
6060 6058 }
6061 6059
6062 6060 static int
6063 6061 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred)
6064 6062 {
6065 6063 #ifdef CARDBUS
6066 6064 if (cardbus_is_cb_minor(*dev))
6067 6065 return (cardbus_open(dev, flag, otyp, cred));
6068 6066 #endif
6069 6067 return (EINVAL);
6070 6068 }
6071 6069
6072 6070 static int
6073 6071 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred)
6074 6072 {
6075 6073 #ifdef CARDBUS
6076 6074 if (cardbus_is_cb_minor(dev))
6077 6075 return (cardbus_close(dev, flag, otyp, cred));
6078 6076 #endif
6079 6077 return (EINVAL);
6080 6078 }
6081 6079
6082 6080 static int
6083 6081 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred,
6084 6082 int *rval)
6085 6083 {
6086 6084 #ifdef CARDBUS
6087 6085 if (cardbus_is_cb_minor(dev))
6088 6086 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval));
6089 6087 #endif
6090 6088 return (EINVAL);
6091 6089 }
6092 6090
6093 6091
6094 6092 static boolean_t
6095 6093 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp)
6096 6094 {
6097 6095 uint32_t present_state;
6098 6096 dev_info_t *dip = pcic->dip;
6099 6097 set_socket_t s;
6100 6098 get_socket_t g;
6101 6099 boolean_t retval;
6102 6100 unsigned vccLevel;
6103 6101
6104 6102 pcic_err(dip, 8, "entering pcic_load_cardbus\n");
6105 6103
6106 6104 pcic_mutex_exit(&pcic->pc_lock);
6107 6105
6108 6106 bzero(&s, sizeof (set_socket_t));
6109 6107 s.socket = sockp->pcs_socket;
6110 6108 s.SCIntMask = SBM_CD|SBM_RDYBSY;
6111 6109 s.IFType = IF_CARDBUS;
6112 6110 s.State = (unsigned)~0;
6113 6111
6114 6112 present_state = pcic_getcb(pcic, CB_PRESENT_STATE);
6115 6113 if (present_state & PCIC_VCC_3VCARD)
6116 6114 s.VccLevel = PCIC_VCC_3VLEVEL;
6117 6115 else if (present_state & PCIC_VCC_5VCARD)
6118 6116 s.VccLevel = PCIC_VCC_5VLEVEL;
6119 6117 else {
6120 6118 cmn_err(CE_CONT,
6121 6119 "pcic_load_cardbus: unsupported card voltage\n");
6122 6120 goto failure;
6123 6121 }
6124 6122 vccLevel = s.VccLevel;
6125 6123 s.Vpp1Level = s.Vpp2Level = 0;
6126 6124
6127 6125 if (pcic_set_socket(dip, &s) != SUCCESS)
6128 6126 goto failure;
6129 6127
6130 6128 if (pcic_reset_socket(dip, sockp->pcs_socket,
6131 6129 RESET_MODE_CARD_ONLY) != SUCCESS)
6132 6130 goto failure;
6133 6131
6134 6132 bzero(&g, sizeof (get_socket_t));
6135 6133 g.socket = sockp->pcs_socket;
6136 6134 if (pcic_get_socket(dip, &g) != SUCCESS)
6137 6135 goto failure;
6138 6136
6139 6137 bzero(&s, sizeof (set_socket_t));
6140 6138 s.socket = sockp->pcs_socket;
6141 6139 s.SCIntMask = SBM_CD;
6142 6140 s.IREQRouting = g.IRQRouting;
6143 6141 s.IFType = g.IFType;
6144 6142 s.CtlInd = g.CtlInd;
6145 6143 s.State = (unsigned)~0;
6146 6144 s.VccLevel = vccLevel;
6147 6145 s.Vpp1Level = s.Vpp2Level = 0;
6148 6146
6149 6147 retval = pcic_set_socket(dip, &s);
6150 6148 pcmcia_cb_resumed(s.socket);
6151 6149 if (retval != SUCCESS)
6152 6150 goto failure;
6153 6151
6154 6152 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base);
6155 6153 goto exit;
6156 6154
6157 6155 failure:
6158 6156 retval = B_FALSE;
6159 6157
6160 6158 exit:
6161 6159 pcic_mutex_enter(&pcic->pc_lock);
6162 6160 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n",
6163 6161 retval ? "success" : "failure");
6164 6162 return (retval);
6165 6163 }
6166 6164
6167 6165 static void
6168 6166 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp)
6169 6167 {
6170 6168 dev_info_t *dip = pcic->dip;
6171 6169 set_socket_t s;
6172 6170
6173 6171 pcic_mutex_exit(&pcic->pc_lock);
6174 6172
6175 6173 cardbus_unload_cardbus(dip);
6176 6174
6177 6175 bzero(&s, sizeof (set_socket_t));
6178 6176 s.socket = sockp->pcs_socket;
6179 6177 s.SCIntMask = SBM_CD|SBM_RDYBSY;
6180 6178 s.IREQRouting = 0;
6181 6179 s.IFType = IF_MEMORY;
6182 6180 s.CtlInd = 0;
6183 6181 s.State = 0;
6184 6182 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0;
6185 6183
6186 6184 (void) pcic_set_socket(dip, &s);
6187 6185
6188 6186 pcic_mutex_enter(&pcic->pc_lock);
6189 6187 }
6190 6188
6191 6189 static uint32_t
6192 6190 pcic_getcb(pcicdev_t *pcic, int reg)
6193 6191 {
6194 6192 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA);
6195 6193
6196 6194 return (ddi_get32(pcic->handle,
6197 6195 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg)));
6198 6196 }
6199 6197
6200 6198 static void
6201 6199 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value)
6202 6200 {
6203 6201 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA);
6204 6202
6205 6203 ddi_put32(pcic->handle,
6206 6204 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value);
6207 6205 }
6208 6206
6209 6207 static void
6210 6208 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq)
6211 6209 {
6212 6210 uint8_t value;
6213 6211 uint16_t brdgctl;
6214 6212
6215 6213 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK;
6216 6214 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq);
6217 6215
6218 6216 switch (pcic->pc_type) {
6219 6217 case PCIC_INTEL_i82092:
6220 6218 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ,
6221 6219 PCIC_82092_INT_ENABLE);
6222 6220 break;
6223 6221 case PCIC_O2_OZ6912:
6224 6222 value = pcic_getb(pcic, 0, PCIC_CENTDMA);
6225 6223 value |= 0x8;
6226 6224 pcic_putb(pcic, 0, PCIC_CENTDMA, value);
6227 6225 break;
6228 6226 case PCIC_CL_PD6832:
6229 6227 case PCIC_TI_PCI1250:
6230 6228 case PCIC_TI_PCI1221:
6231 6229 case PCIC_TI_PCI1225:
6232 6230 case PCIC_TI_PCI1410:
6233 6231 case PCIC_ENE_1410:
6234 6232 case PCIC_TI_PCI1510:
6235 6233 case PCIC_TI_PCI1520:
6236 6234 case PCIC_TI_PCI1420:
6237 6235 case PCIC_ENE_1420:
6238 6236 /* route card functional interrupts to PCI interrupts */
6239 6237 brdgctl = ddi_get16(pcic->cfg_handle,
6240 6238 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL));
6241 6239 pcic_err(NULL, 1,
6242 6240 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n",
6243 6241 PCI_CBUS_BRIDGE_CTRL, brdgctl);
6244 6242 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK;
6245 6243 ddi_put16(pcic->cfg_handle,
6246 6244 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL),
6247 6245 brdgctl);
6248 6246 /* Flush the write */
6249 6247 (void) ddi_get16(pcic->cfg_handle,
6250 6248 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL));
6251 6249 break;
6252 6250 default:
6253 6251 break;
6254 6252 }
6255 6253 }
6256 6254
6257 6255 static void
6258 6256 pcic_disable_io_intr(pcicdev_t *pcic, int socket)
6259 6257 {
6260 6258 uint8_t value;
6261 6259 uint16_t brdgctl;
6262 6260
6263 6261 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK;
6264 6262 pcic_putb(pcic, socket, PCIC_INTERRUPT, value);
6265 6263
6266 6264 switch (pcic->pc_type) {
6267 6265 case PCIC_INTEL_i82092:
6268 6266 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ,
6269 6267 PCIC_82092_INT_DISABLE);
6270 6268 break;
6271 6269 case PCIC_O2_OZ6912:
6272 6270 value = pcic_getb(pcic, 0, PCIC_CENTDMA);
6273 6271 value &= ~0x8;
6274 6272 pcic_putb(pcic, 0, PCIC_CENTDMA, value);
6275 6273 /* Flush the write */
6276 6274 (void) pcic_getb(pcic, 0, PCIC_CENTDMA);
6277 6275 break;
6278 6276 case PCIC_CL_PD6832:
6279 6277 case PCIC_TI_PCI1250:
6280 6278 case PCIC_TI_PCI1221:
6281 6279 case PCIC_TI_PCI1225:
6282 6280 case PCIC_TI_PCI1410:
6283 6281 case PCIC_ENE_1410:
6284 6282 case PCIC_TI_PCI1510:
6285 6283 case PCIC_TI_PCI1520:
6286 6284 case PCIC_TI_PCI1420:
6287 6285 case PCIC_ENE_1420:
6288 6286 /*
6289 6287 * This maps I/O interrupts to ExCA which
6290 6288 * have been turned off by the write to
6291 6289 * PCIC_INTERRUPT above. It would appear to
6292 6290 * be the only way to actually turn I/O Ints off
6293 6291 * while retaining CS Ints.
6294 6292 */
6295 6293 brdgctl = ddi_get16(pcic->cfg_handle,
6296 6294 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL));
6297 6295 pcic_err(NULL, 1,
6298 6296 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n",
6299 6297 PCI_CBUS_BRIDGE_CTRL, brdgctl);
6300 6298 brdgctl |= PCIC_BRDGCTL_INTR_MASK;
6301 6299 ddi_put16(pcic->cfg_handle,
6302 6300 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL),
6303 6301 brdgctl);
6304 6302 /* Flush the write */
6305 6303 (void) ddi_get16(pcic->cfg_handle,
6306 6304 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL));
6307 6305 break;
6308 6306 default:
6309 6307 break;
6310 6308 }
6311 6309 }
6312 6310
6313 6311 static void
6314 6312 pcic_cb_enable_intr(dev_info_t *dip)
6315 6313 {
6316 6314 anp_t *anp = ddi_get_driver_private(dip);
6317 6315 pcicdev_t *pcic = anp->an_private;
6318 6316
6319 6317 mutex_enter(&pcic->pc_lock);
6320 6318 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq);
6321 6319 mutex_exit(&pcic->pc_lock);
6322 6320 }
6323 6321
6324 6322 static void
6325 6323 pcic_cb_disable_intr(dev_info_t *dip)
6326 6324 {
6327 6325 anp_t *anp = ddi_get_driver_private(dip);
6328 6326 pcicdev_t *pcic = anp->an_private;
6329 6327
6330 6328 mutex_enter(&pcic->pc_lock);
6331 6329 pcic_disable_io_intr(pcic, 0);
6332 6330 mutex_exit(&pcic->pc_lock);
6333 6331 }
6334 6332
6335 6333 static int
6336 6334 log_pci_cfg_err(ushort_t e, int bridge_secondary)
6337 6335 {
6338 6336 int nerr = 0;
6339 6337 if (e & PCI_STAT_PERROR) {
6340 6338 nerr++;
6341 6339 cmn_err(CE_CONT, "detected parity error.\n");
6342 6340 }
6343 6341 if (e & PCI_STAT_S_SYSERR) {
6344 6342 nerr++;
6345 6343 if (bridge_secondary)
6346 6344 cmn_err(CE_CONT, "received system error.\n");
6347 6345 else
6348 6346 cmn_err(CE_CONT, "signalled system error.\n");
6349 6347 }
6350 6348 if (e & PCI_STAT_R_MAST_AB) {
6351 6349 nerr++;
6352 6350 cmn_err(CE_CONT, "received master abort.\n");
6353 6351 }
6354 6352 if (e & PCI_STAT_R_TARG_AB)
6355 6353 cmn_err(CE_CONT, "received target abort.\n");
6356 6354 if (e & PCI_STAT_S_TARG_AB)
6357 6355 cmn_err(CE_CONT, "signalled target abort\n");
6358 6356 if (e & PCI_STAT_S_PERROR) {
6359 6357 nerr++;
6360 6358 cmn_err(CE_CONT, "signalled parity error\n");
6361 6359 }
6362 6360 return (nerr);
6363 6361 }
6364 6362
6365 6363 #if defined(__sparc)
6366 6364 static int
6367 6365 pcic_fault(enum pci_fault_ops op, void *arg)
6368 6366 {
6369 6367 pcicdev_t *pcic = (pcicdev_t *)arg;
6370 6368 ushort_t pci_cfg_stat =
6371 6369 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT);
6372 6370 ushort_t pci_cfg_sec_stat =
6373 6371 pci_config_get16(pcic->cfg_handle, 0x16);
6374 6372 char nm[24];
6375 6373 int nerr = 0;
6376 6374
6377 6375 cardbus_dump_pci_config(pcic->dip);
6378 6376
6379 6377 switch (op) {
6380 6378 case FAULT_LOG:
6381 6379 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip),
6382 6380 ddi_get_instance(pcic->dip));
6383 6381
6384 6382 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm);
6385 6383 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat);
6386 6384 nerr += log_pci_cfg_err(pci_cfg_stat, 0);
6387 6385 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat);
6388 6386 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1);
6389 6387 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm);
6390 6388 return (nerr);
6391 6389 case FAULT_POKEFINI:
6392 6390 case FAULT_RESET:
6393 6391 pci_config_put16(pcic->cfg_handle,
6394 6392 PCI_CONF_STAT, pci_cfg_stat);
6395 6393 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat);
6396 6394 break;
6397 6395 case FAULT_POKEFLT:
6398 6396 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR))
6399 6397 return (1);
6400 6398 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB))
6401 6399 return (1);
6402 6400 break;
6403 6401 default:
6404 6402 break;
6405 6403 }
6406 6404 return (DDI_SUCCESS);
6407 6405 }
6408 6406 #endif
6409 6407
6410 6408 static void
6411 6409 pcic_do_resume(pcicdev_t *pcic)
6412 6410 {
6413 6411 int i, interrupt;
6414 6412 uint8_t cfg;
6415 6413
6416 6414
6417 6415 #if defined(PCIC_DEBUG)
6418 6416 pcic_err(NULL, 6, "pcic_do_resume(): entered\n");
6419 6417 #endif
6420 6418
6421 6419 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */
6422 6420 for (i = 0; i < pcic->pc_numsockets; i++) {
6423 6421 /* Enable interrupts on PCI if needs be */
6424 6422 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT);
6425 6423 if (pcic->pc_flags & PCF_USE_SMI)
6426 6424 interrupt |= PCIC_INTR_ENABLE;
6427 6425 pcic_putb(pcic, i, PCIC_INTERRUPT,
6428 6426 PCIC_RESET | interrupt);
6429 6427 pcic->pc_sockets[i].pcs_debounce_id =
6430 6428 pcic_add_debqueue(&pcic->pc_sockets[i],
6431 6429 drv_usectohz(pcic_debounce_time));
6432 6430 }
6433 6431 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */
6434 6432 if (pcic_do_pcmcia_sr)
6435 6433 (void) pcmcia_wait_insert(pcic->dip);
6436 6434 /*
6437 6435 * The CardBus controller may be in RESET state after the
6438 6436 * system is resumed from sleeping. The RESET bit is in
6439 6437 * the Bridge Control register. This is true for all(TI,
6440 6438 * Toshiba ToPIC95/97, RICOH, and O2Micro) CardBus
6441 6439 * controllers. Need to clear the RESET bit explicitly.
6442 6440 */
6443 6441 cfg = ddi_get8(pcic->cfg_handle,
6444 6442 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
6445 6443 if (cfg & (1<<6)) {
6446 6444 cfg &= ~(1<<6);
6447 6445 ddi_put8(pcic->cfg_handle,
6448 6446 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
6449 6447 cfg);
6450 6448 cfg = ddi_get8(pcic->cfg_handle,
6451 6449 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
6452 6450 if (cfg & (1<<6)) {
6453 6451 pcic_err(pcic->dip, 1,
6454 6452 "Failed to take pcic out of reset");
6455 6453 }
6456 6454 }
6457 6455
6458 6456 }
6459 6457
6460 6458 static void
6461 6459 pcic_debounce(pcic_socket_t *pcs)
6462 6460 {
6463 6461 uint8_t status, stschng;
6464 6462
6465 6463 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock);
6466 6464 pcs->pcs_flags &= ~PCS_STARTING;
6467 6465 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket,
6468 6466 PCIC_CARD_STATUS_CHANGE);
6469 6467 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket,
6470 6468 PCIC_INTERFACE_STATUS);
6471 6469 #ifdef PCIC_DEBUG
6472 6470 pcic_err(pcs->pcs_pcic->dip, 8,
6473 6471 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x "
6474 6472 "chg 0x%x flg 0x%x\n",
6475 6473 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket,
6476 6474 status, stschng, pcs->pcs_flags);
6477 6475 #endif
6478 6476
6479 6477 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE,
6480 6478 PCIC_CD_DETECT);
6481 6479 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status);
6482 6480 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock);
6483 6481 }
6484 6482
6485 6483 static void
6486 6484 pcic_deb_thread()
6487 6485 {
6488 6486 callb_cpr_t cprinfo;
6489 6487 struct debounce *debp;
6490 6488 clock_t lastt;
6491 6489
6492 6490 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx,
6493 6491 callb_generic_cpr, "pcic debounce thread");
6494 6492 mutex_enter(&pcic_deb_mtx);
6495 6493 while (pcic_deb_threadid) {
6496 6494 while (pcic_deb_queue) {
6497 6495 #ifdef PCIC_DEBUG
6498 6496 pcic_dump_debqueue("Thread");
6499 6497 #endif
6500 6498 debp = pcic_deb_queue;
6501 6499 (void) drv_getparm(LBOLT, &lastt);
6502 6500 if (lastt >= debp->expire) {
6503 6501 pcic_deb_queue = debp->next;
6504 6502 mutex_exit(&pcic_deb_mtx);
6505 6503 pcic_debounce(debp->pcs);
6506 6504 mutex_enter(&pcic_deb_mtx);
6507 6505 kmem_free(debp, sizeof (*debp));
6508 6506 } else {
6509 6507 (void) cv_timedwait(&pcic_deb_cv,
6510 6508 &pcic_deb_mtx, debp->expire);
6511 6509 }
6512 6510 }
6513 6511 CALLB_CPR_SAFE_BEGIN(&cprinfo);
6514 6512 cv_wait(&pcic_deb_cv, &pcic_deb_mtx);
6515 6513 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx);
6516 6514 }
6517 6515 pcic_deb_threadid = (kthread_t *)1;
6518 6516 cv_signal(&pcic_deb_cv);
6519 6517 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */
6520 6518 thread_exit();
6521 6519 }
6522 6520
6523 6521 static void *
6524 6522 pcic_add_debqueue(pcic_socket_t *pcs, int clocks)
6525 6523 {
6526 6524 clock_t lbolt;
6527 6525 struct debounce *dbp, **dbpp = &pcic_deb_queue;
6528 6526
6529 6527 (void) drv_getparm(LBOLT, &lbolt);
6530 6528 dbp = kmem_alloc(sizeof (struct debounce), KM_SLEEP);
6531 6529
6532 6530 dbp->expire = lbolt + clocks;
6533 6531 dbp->pcs = pcs;
6534 6532 mutex_enter(&pcic_deb_mtx);
6535 6533 while (*dbpp) {
6536 6534 if (dbp->expire > (*dbpp)->expire)
6537 6535 dbpp = &((*dbpp)->next);
6538 6536 else
6539 6537 break;
6540 6538 }
6541 6539 dbp->next = *dbpp;
6542 6540 *dbpp = dbp;
6543 6541 #ifdef PCIC_DEBUG
6544 6542 pcic_dump_debqueue("Add");
6545 6543 #endif
6546 6544 cv_signal(&pcic_deb_cv);
6547 6545 mutex_exit(&pcic_deb_mtx);
6548 6546 return (dbp);
6549 6547 }
6550 6548
6551 6549 static void
6552 6550 pcic_rm_debqueue(void *id)
6553 6551 {
6554 6552 struct debounce *dbp, **dbpp = &pcic_deb_queue;
6555 6553
6556 6554 dbp = (struct debounce *)id;
6557 6555 mutex_enter(&pcic_deb_mtx);
6558 6556 while (*dbpp) {
6559 6557 if (*dbpp == dbp) {
6560 6558 *dbpp = dbp->next;
6561 6559 kmem_free(dbp, sizeof (*dbp));
6562 6560 #ifdef PCIC_DEBUG
6563 6561 pcic_dump_debqueue("Remove");
6564 6562 #endif
6565 6563 cv_signal(&pcic_deb_cv);
6566 6564 mutex_exit(&pcic_deb_mtx);
6567 6565 return;
6568 6566 }
6569 6567 dbpp = &((*dbpp)->next);
6570 6568 }
6571 6569 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id);
6572 6570 mutex_exit(&pcic_deb_mtx);
6573 6571 }
6574 6572
6575 6573
6576 6574 static int pcic_powerdelay = 0;
6577 6575
6578 6576 static int
6579 6577 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel)
6580 6578 {
6581 6579 int ind, value, orig_pwrctl;
6582 6580
6583 6581 /* power setup -- if necessary */
6584 6582 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
6585 6583
6586 6584 #if defined(PCIC_DEBUG)
6587 6585 pcic_err(pcic->dip, 6,
6588 6586 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n",
6589 6587 socket, powerlevel, orig_pwrctl);
6590 6588 #endif
6591 6589 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */
6592 6590 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) |
6593 6591 (orig_pwrctl & POWER_OUTPUT_ENABLE);
6594 6592 if (powerlevel != orig_pwrctl) {
6595 6593 if (powerlevel & ~POWER_OUTPUT_ENABLE) {
6596 6594 int ifs;
6597 6595 /*
6598 6596 * set power to socket
6599 6597 * note that the powerlevel was calculated earlier
6600 6598 */
6601 6599 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel);
6602 6600 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
6603 6601
6604 6602 /*
6605 6603 * this second write to the power control register
6606 6604 * is needed to resolve a problem on
6607 6605 * the IBM ThinkPad 750
6608 6606 * where the first write doesn't latch.
6609 6607 * The second write appears to always work and
6610 6608 * doesn't hurt the operation of other chips
6611 6609 * so we can just use it -- this is good since we can't
6612 6610 * determine what chip the 750 actually uses
6613 6611 * (I suspect an early Ricoh).
6614 6612 */
6615 6613 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel);
6616 6614
6617 6615 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
6618 6616 pcic_mswait(pcic, socket, pcic_powerdelay);
6619 6617 #if defined(PCIC_DEBUG)
6620 6618 pcic_err(pcic->dip, 8,
6621 6619 "\tpowerlevel reg = %x (ifs %x)\n",
6622 6620 value, pcic_getb(pcic, socket,
6623 6621 PCIC_INTERFACE_STATUS));
6624 6622 pcic_err(pcic->dip, 8,
6625 6623 "CBus regs: PS 0x%x, Control 0x%x\n",
6626 6624 pcic_getcb(pcic, CB_PRESENT_STATE),
6627 6625 pcic_getcb(pcic, CB_CONTROL));
6628 6626 #endif
6629 6627 /*
6630 6628 * since power was touched, make sure it says it
6631 6629 * is on. This lets it become stable.
6632 6630 */
6633 6631 for (ind = 0; ind < 20; ind++) {
6634 6632 ifs = pcic_getb(pcic, socket,
6635 6633 PCIC_INTERFACE_STATUS);
6636 6634 if (ifs & PCIC_POWER_ON)
6637 6635 break;
6638 6636 else {
6639 6637 pcic_putb(pcic, socket,
6640 6638 PCIC_POWER_CONTROL, 0);
6641 6639 (void) pcic_getb(pcic, socket,
6642 6640 PCIC_POWER_CONTROL);
6643 6641 pcic_mswait(pcic, socket, 40);
6644 6642 if (ind == 10) {
6645 6643 pcic_putcb(pcic, CB_EVENT_FORCE,
6646 6644 CB_EF_CVTEST);
6647 6645 pcic_mswait(pcic, socket, 100);
6648 6646 }
6649 6647 pcic_putb(pcic, socket,
6650 6648 PCIC_POWER_CONTROL,
6651 6649 powerlevel & ~POWER_OUTPUT_ENABLE);
6652 6650 (void) pcic_getb(pcic, socket,
6653 6651 PCIC_POWER_CONTROL);
6654 6652 pcic_mswait(pcic, socket,
6655 6653 pcic_powerdelay);
6656 6654 pcic_putb(pcic, socket,
6657 6655 PCIC_POWER_CONTROL, powerlevel);
6658 6656 (void) pcic_getb(pcic, socket,
6659 6657 PCIC_POWER_CONTROL);
6660 6658 pcic_mswait(pcic, socket,
6661 6659 pcic_powerdelay);
6662 6660 }
6663 6661 }
6664 6662
6665 6663 if (!(ifs & PCIC_POWER_ON)) {
6666 6664 cmn_err(CE_WARN,
6667 6665 "pcic socket %d: Power didn't get turned"
6668 6666 "on!\nif status 0x%x pwrc 0x%x(x%x) "
6669 6667 "misc1 0x%x igc 0x%x ind %d\n",
6670 6668 socket, ifs,
6671 6669 pcic_getb(pcic, socket, PCIC_POWER_CONTROL),
6672 6670 orig_pwrctl,
6673 6671 pcic_getb(pcic, socket, PCIC_MISC_CTL_1),
6674 6672 pcic_getb(pcic, socket, PCIC_INTERRUPT),
6675 6673 ind);
6676 6674 return (BAD_VCC);
6677 6675 }
6678 6676 #if defined(PCIC_DEBUG)
6679 6677 pcic_err(pcic->dip, 8,
6680 6678 "\tind = %d, if status %x pwrc 0x%x "
6681 6679 "misc1 0x%x igc 0x%x\n",
6682 6680 ind, ifs,
6683 6681 pcic_getb(pcic, socket, PCIC_POWER_CONTROL),
6684 6682 pcic_getb(pcic, socket, PCIC_MISC_CTL_1),
6685 6683 pcic_getb(pcic, socket, PCIC_INTERRUPT));
6686 6684 #endif
6687 6685 } else {
6688 6686 /* explicitly turned off the power */
6689 6687 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel);
6690 6688 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
6691 6689 }
6692 6690 }
6693 6691 return (SUCCESS);
6694 6692 }
6695 6693
6696 6694 static int pcic_cbdoreset_during_poweron = 1;
6697 6695 static int
6698 6696 pcic_cbus_powerctl(pcicdev_t *pcic, int socket)
6699 6697 {
6700 6698 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps;
6701 6699 int ind, iobits;
6702 6700 pcic_socket_t *sockp = &pcic->pc_sockets[socket];
6703 6701
6704 6702 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE);
6705 6703
6706 6704 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10;
6707 6705 cbctl |= pcic_cbv_levels[ind];
6708 6706
6709 6707 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10;
6710 6708 cbctl |= (pcic_cbv_levels[ind]<<4);
6711 6709
6712 6710 orig_cbctl = pcic_getcb(pcic, CB_CONTROL);
6713 6711
6714 6712 #if defined(PCIC_DEBUG)
6715 6713 pcic_err(pcic->dip, 6,
6716 6714 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d "
6717 6715 "cbctl 0x%x->0x%x\n",
6718 6716 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl);
6719 6717 #endif
6720 6718 if (cbctl != orig_cbctl) {
6721 6719 if (pcic_cbdoreset_during_poweron &&
6722 6720 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) {
6723 6721 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT);
6724 6722 pcic_putb(pcic, socket, PCIC_INTERRUPT,
6725 6723 iobits & ~PCIC_RESET);
6726 6724 }
6727 6725 pcic_putcb(pcic, CB_CONTROL, cbctl);
6728 6726
6729 6727 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) {
6730 6728 pcic_mswait(pcic, socket, pcic_powerdelay);
6731 6729 return (SUCCESS);
6732 6730 }
6733 6731 for (ind = 0; ind < 20; ind++) {
6734 6732 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT);
6735 6733
6736 6734 if (cbstev & CB_SE_POWER_CYCLE) {
6737 6735
6738 6736 /*
6739 6737 * delay 400 ms: though the standard defines that the Vcc
6740 6738 * set-up time is 20 ms, some PC-Card bridge requires longer
6741 6739 * duration.
6742 6740 * Note: We should check the status AFTER the delay to give time
6743 6741 * for things to stabilize.
6744 6742 */
6745 6743 pcic_mswait(pcic, socket, 400);
6746 6744
6747 6745 cbps = pcic_getcb(pcic, CB_PRESENT_STATE);
6748 6746 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) {
6749 6747 /* break; */
6750 6748 cmn_err(CE_WARN, "cbus_powerctl: power off??\n");
6751 6749 }
6752 6750 if (cbctl & CB_PS_BADVCC) {
6753 6751 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n");
6754 6752 break;
6755 6753 }
6756 6754
6757 6755 #if defined(PCIC_DEBUG)
6758 6756 pcic_err(pcic->dip, 8,
6759 6757 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)",
6760 6758 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE),
6761 6759 cbctl, orig_cbctl);
6762 6760 #endif
6763 6761 if (pcic_cbdoreset_during_poweron &&
6764 6762 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) {
6765 6763 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits);
6766 6764 }
6767 6765 return (SUCCESS);
6768 6766 }
6769 6767 pcic_mswait(pcic, socket, 40);
6770 6768 }
6771 6769 if (pcic_cbdoreset_during_poweron &&
6772 6770 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) {
6773 6771 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits);
6774 6772 }
6775 6773 cmn_err(CE_WARN,
6776 6774 "pcic socket %d: Power didn't get turned on/off!\n"
6777 6775 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) "
6778 6776 "vcc %d vpp1 %d", socket, cbstev,
6779 6777 pcic_getcb(pcic, CB_PRESENT_STATE),
6780 6778 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1);
6781 6779 return (BAD_VCC);
6782 6780 }
6783 6781 return (SUCCESS);
6784 6782 }
6785 6783
6786 6784 static int pcic_do_pprintf = 0;
6787 6785
6788 6786 static void
6789 6787 pcic_dump_debqueue(char *msg)
6790 6788 {
6791 6789 struct debounce *debp = pcic_deb_queue;
6792 6790 clock_t lbolt;
6793 6791
6794 6792 (void) drv_getparm(LBOLT, &lbolt);
6795 6793 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" :
6796 6794 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt);
6797 6795 while (debp) {
6798 6796 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n",
6799 6797 (void *) debp, (int)debp->expire, (void *) debp->next,
6800 6798 debp->pcs->pcs_debounce_id);
6801 6799 debp = debp->next;
6802 6800 }
6803 6801 }
6804 6802
6805 6803
6806 6804 /* PRINTFLIKE3 */
6807 6805 static void
6808 6806 pcic_err(dev_info_t *dip, int level, const char *fmt, ...)
6809 6807 {
6810 6808 if (pcic_debug && (level <= pcic_debug)) {
6811 6809 va_list adx;
6812 6810 int instance;
6813 6811 char buf[256];
6814 6812 const char *name;
6815 6813 #if !defined(PCIC_DEBUG)
6816 6814 int ce;
6817 6815 char qmark = 0;
6818 6816
6819 6817 if (level <= 3)
6820 6818 ce = CE_WARN;
6821 6819 else
6822 6820 ce = CE_CONT;
6823 6821 if (level == 4)
6824 6822 qmark = 1;
6825 6823 #endif
6826 6824
6827 6825 if (dip) {
6828 6826 instance = ddi_get_instance(dip);
6829 6827 /* name = ddi_binding_name(dip); */
6830 6828 name = ddi_driver_name(dip);
6831 6829 } else {
6832 6830 instance = 0;
6833 6831 name = "";
6834 6832 }
6835 6833
6836 6834 va_start(adx, fmt);
6837 6835 (void) vsprintf(buf, fmt, adx);
6838 6836 va_end(adx);
6839 6837
6840 6838 #if defined(PCIC_DEBUG)
6841 6839 if (pcic_do_pprintf) {
6842 6840 if (dip) {
6843 6841 if (instance >= 0)
6844 6842 prom_printf("%s(%d),0x%p: %s", name,
6845 6843 instance, (void *)dip, buf);
6846 6844 else
6847 6845 prom_printf("%s,0x%p: %s",
6848 6846 name, (void *)dip, buf);
6849 6847 } else
6850 6848 prom_printf(buf);
6851 6849 } else {
6852 6850 if (dip) {
6853 6851 if (instance >= 0)
6854 6852 cmn_err(CE_CONT, "%s(%d),0x%p: %s",
6855 6853 name, instance, (void *) dip, buf);
6856 6854 else
6857 6855 cmn_err(CE_CONT, "%s,0x%p: %s",
6858 6856 name, (void *) dip, buf);
6859 6857 } else
6860 6858 cmn_err(CE_CONT, buf);
6861 6859 }
6862 6860 #else
6863 6861 if (dip)
6864 6862 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name,
6865 6863 instance, buf);
6866 6864 else
6867 6865 cmn_err(ce, qmark ? "?%s" : buf, buf);
6868 6866 #endif
6869 6867 }
6870 6868 }
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