1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 /*
28 * PCIC device/interrupt handler
29 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic
30 * and Toshiba (and possibly other clones) PCMCIA adapter chip
31 * sets. It implements a subset of Socket Services as defined
32 * in the Solaris PCMCIA design documents
33 */
34
35 /*
36 * currently defined "properties"
37 *
38 * clock-frequency bus clock frequency
39 * smi system management interrupt override
40 * need-mult-irq need status IRQ for each pair of sockets
41 * disable-audio don't route audio signal to speaker
42 */
43
44
45 #include <sys/types.h>
46 #include <sys/inttypes.h>
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/user.h>
50 #include <sys/buf.h>
51 #include <sys/file.h>
52 #include <sys/uio.h>
53 #include <sys/conf.h>
54 #include <sys/stat.h>
55 #include <sys/autoconf.h>
56 #include <sys/vtoc.h>
57 #include <sys/dkio.h>
58 #include <sys/ddi.h>
59 #include <sys/sunddi.h>
60 #include <sys/sunndi.h>
61 #include <sys/var.h>
62 #include <sys/callb.h>
63 #include <sys/open.h>
64 #include <sys/ddidmareq.h>
65 #include <sys/dma_engine.h>
66 #include <sys/kstat.h>
67 #include <sys/kmem.h>
68 #include <sys/modctl.h>
69 #include <sys/pci.h>
70 #include <sys/pci_impl.h>
71
72 #include <sys/pctypes.h>
73 #include <sys/pcmcia.h>
74 #include <sys/sservice.h>
75
76 #include <sys/note.h>
77
78 #include <sys/pcic_reg.h>
79 #include <sys/pcic_var.h>
80
81 #if defined(__i386) || defined(__amd64)
82 #include <sys/pci_cfgspace.h>
83 #endif
84
85 #if defined(__sparc)
86 #include <sys/pci/pci_nexus.h>
87 #endif
88
89 #include <sys/hotplug/hpcsvc.h>
90 #include "cardbus/cardbus.h"
91
92 #define SOFTC_SIZE (sizeof (anp_t))
93
94 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
95 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t);
96 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t);
97 static int32_t pcic_quiesce(dev_info_t *);
98 static uint_t pcic_intr(caddr_t, caddr_t);
99 static int pcic_do_io_intr(pcicdev_t *, uint32_t);
100 static int pcic_probe(dev_info_t *);
101
102 static int pcic_open(dev_t *, int, int, cred_t *);
103 static int pcic_close(dev_t, int, int, cred_t *);
104 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
105
106 typedef struct pcm_regs pcm_regs_t;
107
108 static void pcic_init_assigned(dev_info_t *);
109 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *,
110 pci_regspec_t *, int);
111 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int);
112
113 /*
114 * To make this nexus work on x86, we need to have the default ddi_dma_mctl
115 * ctlops in the bus_ops structure, just to pass the request to the parent.
116 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA.
117 */
118 static
119 struct bus_ops pcmciabus_ops = {
120 BUSO_REV,
121 pcmcia_bus_map,
122 NULL,
123 NULL,
124 NULL,
125 i_ddi_map_fault,
126 ddi_no_dma_map,
127 ddi_no_dma_allochdl,
128 ddi_no_dma_freehdl,
129 ddi_no_dma_bindhdl,
130 ddi_no_dma_unbindhdl,
131 ddi_no_dma_flush,
132 ddi_no_dma_win,
133 ddi_dma_mctl,
134 pcmcia_ctlops,
135 pcmcia_prop_op,
136 NULL, /* (*bus_get_eventcookie)(); */
137 NULL, /* (*bus_add_eventcall)(); */
138 NULL, /* (*bus_remove_eventcall)(); */
139 NULL, /* (*bus_post_event)(); */
140 NULL, /* (*bus_intr_ctl)(); */
141 NULL, /* (*bus_config)(); */
142 NULL, /* (*bus_unconfig)(); */
143 NULL, /* (*bus_fm_init)(); */
144 NULL, /* (*bus_fm_fini)(); */
145 NULL, /* (*bus_enter)() */
146 NULL, /* (*bus_exit)() */
147 NULL, /* (*bus_power)() */
148 pcmcia_intr_ops /* (*bus_intr_op)(); */
149 };
150
151 static struct cb_ops pcic_cbops = {
152 pcic_open,
153 pcic_close,
154 nodev,
155 nodev,
156 nodev,
157 nodev,
158 nodev,
159 pcic_ioctl,
160 nodev,
161 nodev,
162 nodev,
163 nochpoll,
164 ddi_prop_op,
165 NULL,
166 #ifdef CARDBUS
167 D_NEW | D_MP | D_HOTPLUG
168 #else
169 D_NEW | D_MP
170 #endif
171 };
172
173 static struct dev_ops pcic_devops = {
174 DEVO_REV,
175 0,
176 pcic_getinfo,
177 nulldev,
178 pcic_probe,
179 pcic_attach,
180 pcic_detach,
181 nulldev,
182 &pcic_cbops,
183 &pcmciabus_ops,
184 NULL,
185 pcic_quiesce, /* devo_quiesce */
186 };
187
188 void *pcic_soft_state_p = NULL;
189 static int pcic_maxinst = -1;
190
191 int pcic_do_insertion = 1;
192 int pcic_do_removal = 1;
193
194 struct irqmap {
195 int irq;
196 int count;
197 } pcic_irq_map[16];
198
199
200 int pcic_debug = 0x0;
201 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...);
202 extern void cardbus_dump_pci_config(dev_info_t *dip);
203 extern void cardbus_dump_socket(dev_info_t *dip);
204 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle);
205 static void pcic_dump_debqueue(char *msg);
206
207 #if defined(PCIC_DEBUG)
208 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t);
209
210 #define pcic_mutex_enter(a) \
211 { \
212 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \
213 mutex_enter(a); \
214 };
215
216 #define pcic_mutex_exit(a) \
217 { \
218 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \
219 mutex_exit(a); \
220 };
221
222 #else
223 #define pcic_mutex_enter(a) mutex_enter(a)
224 #define pcic_mutex_exit(a) mutex_exit(a)
225 #endif
226
227 #define PCIC_VCC_3VLEVEL 1
228 #define PCIC_VCC_5VLEVEL 2
229 #define PCIC_VCC_12LEVEL 3
230
231 /* bit patterns to select voltage levels */
232 int pcic_vpp_levels[13] = {
233 0, 0, 0,
234 1, /* 3.3V */
235 0,
236 1, /* 5V */
237 0, 0, 0, 0, 0, 0,
238 2 /* 12V */
239 };
240
241 uint8_t pcic_cbv_levels[13] = {
242 0, 0, 0,
243 3, /* 3.3V */
244 0,
245 2, /* 5V */
246 0, 0, 0, 0, 0, 0,
247 1 /* 12V */
248 };
249
250 struct power_entry pcic_power[4] = {
251 {
252 0, VCC|VPP1|VPP2
253 },
254 {
255 33, /* 3.3Volt */
256 VCC|VPP1|VPP2
257 },
258 {
259 5*10, /* 5Volt */
260 VCC|VPP1|VPP2 /* currently only know about this */
261 },
262 {
263 12*10, /* 12Volt */
264 VPP1|VPP2
265 }
266 };
267
268 /*
269 * Base used to allocate ranges of PCI memory on x86 systems
270 * Each instance gets a chunk above the base that is used to map
271 * in the memory and I/O windows for that device.
272 * Pages below the base are also allocated for the EXCA registers,
273 * one per instance.
274 */
275 #define PCIC_PCI_MEMCHUNK 0x1000000
276
277 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */
278 static int pcic_debounce_time = 200000; /* In micro-seconds */
279
280 struct debounce {
281 pcic_socket_t *pcs;
282 clock_t expire;
283 struct debounce *next;
284 };
285
286 static struct debounce *pcic_deb_queue = NULL;
287 static kmutex_t pcic_deb_mtx;
288 static kcondvar_t pcic_deb_cv;
289 static kthread_t *pcic_deb_threadid;
290
291 static inthandler_t *pcic_handlers;
292
293 static void pcic_setup_adapter(pcicdev_t *);
294 static int pcic_change(pcicdev_t *, int);
295 static int pcic_ll_reset(pcicdev_t *, int);
296 static void pcic_mswait(pcicdev_t *, int, int);
297 static boolean_t pcic_check_ready(pcicdev_t *, int);
298 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int);
299 static void pcic_ready_wait(pcicdev_t *, int);
300 extern int pcmcia_get_intr(dev_info_t *, int);
301 extern int pcmcia_return_intr(dev_info_t *, int);
302 extern void pcmcia_cb_suspended(int);
303 extern void pcmcia_cb_resumed(int);
304
305 static int pcic_callback(dev_info_t *, int (*)(), int);
306 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *);
307 static int pcic_get_adapter(dev_info_t *, get_adapter_t *);
308 static int pcic_get_page(dev_info_t *, get_page_t *);
309 static int pcic_get_socket(dev_info_t *, get_socket_t *);
310 static int pcic_get_status(dev_info_t *, get_ss_status_t *);
311 static int pcic_get_window(dev_info_t *, get_window_t *);
312 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *);
313 static int pcic_inquire_window(dev_info_t *, inquire_window_t *);
314 static int pcic_reset_socket(dev_info_t *, int, int);
315 static int pcic_set_page(dev_info_t *, set_page_t *);
316 static int pcic_set_window(dev_info_t *, set_window_t *);
317 static int pcic_set_socket(dev_info_t *, set_socket_t *);
318 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *);
319 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *);
320 static void pcic_pm_detection(void *);
321 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned);
322 static int clext_reg_read(pcicdev_t *, int, uchar_t);
323 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t);
324 static int pcic_calc_speed(pcicdev_t *, uint32_t);
325 static int pcic_card_state(pcicdev_t *, pcic_socket_t *);
326 static int pcic_find_pci_type(pcicdev_t *);
327 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int);
328 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t);
329 static uint_t pcic_cd_softint(caddr_t, caddr_t);
330 static uint8_t pcic_getb(pcicdev_t *, int, int);
331 static void pcic_putb(pcicdev_t *, int, int, int8_t);
332 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *);
333 static uint_t pcic_softintr(caddr_t, caddr_t);
334
335 static void pcic_debounce(pcic_socket_t *);
336 static void pcic_do_resume(pcicdev_t *);
337 static void *pcic_add_debqueue(pcic_socket_t *, int);
338 static void pcic_rm_debqueue(void *);
339 static void pcic_deb_thread();
340
341 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp);
342 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp);
343 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg);
344 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value);
345 static void pcic_cb_enable_intr(dev_info_t *);
346 static void pcic_cb_disable_intr(dev_info_t *);
347 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq);
348 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket);
349
350 static cb_nexus_cb_t pcic_cbnexus_ops = {
351 pcic_cb_enable_intr,
352 pcic_cb_disable_intr
353 };
354
355 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel);
356 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket);
357
358 #if defined(__sparc)
359 static int pcic_fault(enum pci_fault_ops op, void *arg);
360 #endif
361
362
363 /*
364 * pcmcia interface operations structure
365 * this is the private interface that is exported to the nexus
366 */
367 pcmcia_if_t pcic_if_ops = {
368 PCIF_MAGIC,
369 PCIF_VERSION,
370 pcic_callback,
371 pcic_get_adapter,
372 pcic_get_page,
373 pcic_get_socket,
374 pcic_get_status,
375 pcic_get_window,
376 pcic_inquire_adapter,
377 pcic_inquire_socket,
378 pcic_inquire_window,
379 pcic_reset_socket,
380 pcic_set_page,
381 pcic_set_window,
382 pcic_set_socket,
383 pcic_set_interrupt,
384 pcic_clear_interrupt,
385 NULL,
386 };
387
388 /*
389 * chip type identification routines
390 * this list of functions is searched until one of them succeeds
391 * or all fail. i82365SL is assumed if failed.
392 */
393 static int pcic_ci_cirrus(pcicdev_t *);
394 static int pcic_ci_vadem(pcicdev_t *);
395 static int pcic_ci_ricoh(pcicdev_t *);
396
397 int (*pcic_ci_funcs[])(pcicdev_t *) = {
398 pcic_ci_cirrus,
399 pcic_ci_vadem,
400 pcic_ci_ricoh,
401 NULL
402 };
403
404 static struct modldrv modldrv = {
405 &mod_driverops, /* Type of module. This one is a driver */
406 "PCIC PCMCIA adapter driver", /* Name of the module. */
407 &pcic_devops, /* driver ops */
408 };
409
410 static struct modlinkage modlinkage = {
411 MODREV_1, (void *)&modldrv, NULL
412 };
413
414 int
415 _init()
416 {
417 int stat;
418
419 /* Allocate soft state */
420 if ((stat = ddi_soft_state_init(&pcic_soft_state_p,
421 SOFTC_SIZE, 2)) != DDI_SUCCESS)
422 return (stat);
423
424 if ((stat = mod_install(&modlinkage)) != 0)
425 ddi_soft_state_fini(&pcic_soft_state_p);
426
427 return (stat);
428 }
429
430 int
431 _fini()
432 {
433 int stat = 0;
434
435 if ((stat = mod_remove(&modlinkage)) != 0)
436 return (stat);
437
438 if (pcic_deb_threadid) {
439 mutex_enter(&pcic_deb_mtx);
440 pcic_deb_threadid = 0;
441 while (!pcic_deb_threadid)
442 cv_wait(&pcic_deb_cv, &pcic_deb_mtx);
443 pcic_deb_threadid = 0;
444 mutex_exit(&pcic_deb_mtx);
445
446 mutex_destroy(&pcic_deb_mtx);
447 cv_destroy(&pcic_deb_cv);
448 }
449
450 ddi_soft_state_fini(&pcic_soft_state_p);
451
452 return (stat);
453 }
454
455 int
456 _info(struct modinfo *modinfop)
457 {
458 return (mod_info(&modlinkage, modinfop));
459 }
460
461 /*
462 * pcic_getinfo()
463 * provide instance/device information about driver
464 */
465 /*ARGSUSED*/
466 static int
467 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result)
468 {
469 anp_t *anp;
470 int error = DDI_SUCCESS;
471 minor_t minor;
472
473 switch (cmd) {
474 case DDI_INFO_DEVT2DEVINFO:
475 minor = getminor((dev_t)arg);
476 minor &= 0x7f;
477 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor)))
478 *result = NULL;
479 else
480 *result = anp->an_dip;
481 break;
482 case DDI_INFO_DEVT2INSTANCE:
483 minor = getminor((dev_t)arg);
484 minor &= 0x7f;
485 *result = (void *)((long)minor);
486 break;
487 default:
488 error = DDI_FAILURE;
489 break;
490 }
491 return (error);
492 }
493
494 static int
495 pcic_probe(dev_info_t *dip)
496 {
497 int value;
498 ddi_device_acc_attr_t attr;
499 ddi_acc_handle_t handle;
500 uchar_t *index, *data;
501
502 if (ddi_dev_is_sid(dip) == DDI_SUCCESS)
503 return (DDI_PROBE_DONTCARE);
504
505 /*
506 * find a PCIC device (any vendor)
507 * while there can be up to 4 such devices in
508 * a system, we currently only look for 1
509 * per probe. There will be up to 2 chips per
510 * instance since they share I/O space
511 */
512 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
513 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC;
514 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
515
516 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM,
517 (caddr_t *)&index,
518 PCIC_ISA_CONTROL_REG_OFFSET,
519 PCIC_ISA_CONTROL_REG_LENGTH,
520 &attr, &handle) != DDI_SUCCESS)
521 return (DDI_PROBE_FAILURE);
522
523 data = index + 1;
524
525 #if defined(PCIC_DEBUG)
526 if (pcic_debug)
527 cmn_err(CE_CONT, "pcic_probe: entered\n");
528 if (pcic_debug)
529 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index);
530 #endif
531 ddi_put8(handle, index, PCIC_CHIP_REVISION);
532 ddi_put8(handle, data, 0);
533 value = ddi_get8(handle, data);
534 #if defined(PCIC_DEBUG)
535 if (pcic_debug)
536 cmn_err(CE_CONT, "\tchip revision register = %x\n", value);
537 #endif
538 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW &&
539 (value & 0x30) == 0) {
540 /*
541 * we probably have a PCIC chip in the system
542 * do a little more checking. If we find one,
543 * reset everything in case of softboot
544 */
545 ddi_put8(handle, index, PCIC_MAPPING_ENABLE);
546 ddi_put8(handle, data, 0);
547 value = ddi_get8(handle, data);
548 #if defined(PCIC_DEBUG)
549 if (pcic_debug)
550 cmn_err(CE_CONT, "\tzero test = %x\n", value);
551 #endif
552 /* should read back as zero */
553 if (value == 0) {
554 /*
555 * we do have one and it is off the bus
556 */
557 #if defined(PCIC_DEBUG)
558 if (pcic_debug)
559 cmn_err(CE_CONT, "pcic_probe: success\n");
560 #endif
561 ddi_regs_map_free(&handle);
562 return (DDI_PROBE_SUCCESS);
563 }
564 }
565 #if defined(PCIC_DEBUG)
566 if (pcic_debug)
567 cmn_err(CE_CONT, "pcic_probe: failed\n");
568 #endif
569 ddi_regs_map_free(&handle);
570 return (DDI_PROBE_FAILURE);
571 }
572
573 /*
574 * These are just defaults they can also be changed via a property in the
575 * conf file.
576 */
577 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM;
578 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM;
579 static int pcic_do_pcmcia_sr = 1;
580 static int pcic_use_cbpwrctl = PCF_CBPWRCTL;
581
582 /*
583 * enable insertion/removal interrupt for 32bit cards
584 */
585 static int
586 cardbus_enable_cd_intr(dev_info_t *dip)
587 {
588 ddi_acc_handle_t iohandle;
589 caddr_t ioaddr;
590 ddi_device_acc_attr_t attr;
591 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
592 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
593 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
594 (void) ddi_regs_map_setup(dip, 1,
595 (caddr_t *)&ioaddr,
596 0,
597 4096,
598 &attr, &iohandle);
599
600 /* CSC Interrupt: Card detect interrupt on */
601 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK),
602 ddi_get32(iohandle,
603 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK);
604
605 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT),
606 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT)));
607
608 ddi_regs_map_free(&iohandle);
609 return (1);
610 }
611
612 /*
613 * quiesce(9E) entry point.
614 *
615 * This function is called when the system is single-threaded at high
616 * PIL with preemption disabled. Therefore, this function must not be
617 * blocked.
618 *
619 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
620 * DDI_FAILURE indicates an error condition and should almost never happen.
621 */
622 static int32_t
623 pcic_quiesce(dev_info_t *dip)
624 {
625 anp_t *anp = ddi_get_driver_private(dip);
626 pcicdev_t *pcic = anp->an_private;
627 int i;
628
629 for (i = 0; i < pcic->pc_numsockets; i++) {
630 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0);
631 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0);
632 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
633 /* disable interrupts and put card into RESET */
634 pcic_putb(pcic, i, PCIC_INTERRUPT, 0);
635 /* poweroff socket */
636 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0);
637 pcic_putcb(pcic, CB_CONTROL, 0);
638 }
639
640 return (DDI_SUCCESS);
641 }
642
643 /*
644 * pcic_attach()
645 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver
646 * to the system. This is a child of "sysbus" since that is where
647 * the hardware lives, but it provides services to the "pcmcia"
648 * nexus driver. It gives a pointer back via its private data
649 * structure which contains both the dip and socket services entry
650 * points
651 */
652 static int
653 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
654 {
655 anp_t *pcic_nexus;
656 pcicdev_t *pcic;
657 int irqlevel, value;
658 int pci_cfrn, pci_ctrn;
659 int i, j, smi, actual;
660 char *typename;
661 char bus_type[16] = "(unknown)";
662 int len = sizeof (bus_type);
663 ddi_device_acc_attr_t attr;
664 anp_t *anp = ddi_get_driver_private(dip);
665 uint_t pri;
666
667 #if defined(PCIC_DEBUG)
668 if (pcic_debug) {
669 cmn_err(CE_CONT, "pcic_attach: entered\n");
670 }
671 #endif
672 switch (cmd) {
673 case DDI_ATTACH:
674 break;
675 case DDI_RESUME:
676 pcic = anp->an_private;
677 /*
678 * for now, this is a simulated resume.
679 * a real one may need different things.
680 */
681 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) {
682 mutex_enter(&pcic->pc_lock);
683 /* should probe for new sockets showing up */
684 pcic_setup_adapter(pcic);
685 pcic->pc_flags &= ~PCF_SUSPENDED;
686 mutex_exit(&pcic->pc_lock);
687 (void) pcmcia_begin_resume(dip);
688
689 pcic_do_resume(pcic);
690 #ifdef CARDBUS
691 cardbus_restore_children(ddi_get_child(dip));
692 #endif
693
694 /*
695 * for complete implementation need END_RESUME (later)
696 */
697 return (DDI_SUCCESS);
698
699 }
700 return (DDI_SUCCESS);
701 default:
702 return (DDI_FAILURE);
703 }
704
705 /*
706 * Allocate soft state associated with this instance.
707 */
708 if (ddi_soft_state_zalloc(pcic_soft_state_p,
709 ddi_get_instance(dip)) != DDI_SUCCESS) {
710 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n",
711 ddi_get_instance(dip));
712 return (DDI_FAILURE);
713 }
714
715 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p,
716 ddi_get_instance(dip));
717
718 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP);
719
720 pcic->dip = dip;
721 pcic_nexus->an_dip = dip;
722 pcic_nexus->an_if = &pcic_if_ops;
723 pcic_nexus->an_private = pcic;
724 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]);
725 pcic->pc_power = pcic_power;
726
727 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
728 "pci-control-reg-number", pci_control_reg_num);
729 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
730 "pci-config-reg-number", pci_config_reg_num);
731
732 ddi_set_driver_private(dip, pcic_nexus);
733
734 /*
735 * pcic->pc_irq is really the IPL level we want to run at
736 * set the default values here and override from intr spec
737 */
738 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
739 "interrupt-priorities", -1);
740
741 if (pcic->pc_irq == -1) {
742 int actual;
743 uint_t pri;
744 ddi_intr_handle_t hdl;
745
746 /* see if intrspec tells us different */
747 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED,
748 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) {
749 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS)
750 pcic->pc_irq = pri;
751 else
752 pcic->pc_irq = LOCK_LEVEL + 1;
753 (void) ddi_intr_free(hdl);
754 }
755 }
756 pcic_nexus->an_ipl = pcic->pc_irq;
757
758 /*
759 * Check our parent bus type. We do different things based on which
760 * bus we're on.
761 */
762 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip),
763 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP,
764 "device_type", (caddr_t)&bus_type[0], &len) !=
765 DDI_PROP_SUCCESS) {
766 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip),
767 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP,
768 "bus-type", (caddr_t)&bus_type[0], &len) !=
769 DDI_PROP_SUCCESS) {
770
771 cmn_err(CE_CONT,
772 "pcic%d: can't find parent bus type\n",
773 ddi_get_instance(dip));
774
775 kmem_free(pcic, sizeof (pcicdev_t));
776 ddi_soft_state_free(pcic_soft_state_p,
777 ddi_get_instance(dip));
778 return (DDI_FAILURE);
779 }
780 } /* ddi_prop_op("device_type") */
781
782 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 ||
783 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0) {
784 pcic->pc_flags = PCF_PCIBUS;
785 } else {
786 cmn_err(CE_WARN, "!pcic%d: non-pci mode (%s) not supported, "
787 "set BIOS to yenta mode if applicable\n",
788 ddi_get_instance(dip), bus_type);
789 kmem_free(pcic, sizeof (pcicdev_t));
790 ddi_soft_state_free(pcic_soft_state_p,
791 ddi_get_instance(dip));
792 return (DDI_FAILURE);
793 }
794
795 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip),
796 DDI_PROP_CANSLEEP,
797 "clock-frequency", 0)) == 0) {
798 if (pcic->pc_flags & PCF_PCIBUS)
799 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK;
800 else
801 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK;
802 } else {
803 /*
804 * OBP can declare the speed in Hz...
805 */
806 if (pcic->bus_speed > 1000000)
807 pcic->bus_speed /= 1000000;
808 } /* ddi_prop_op("clock-frequency") */
809
810 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */
811
812 #ifdef PCIC_DEBUG
813 if (pcic_debug) {
814 cmn_err(CE_CONT,
815 "pcic%d: parent bus type = [%s], speed = %d MHz\n",
816 ddi_get_instance(dip),
817 bus_type, pcic->bus_speed);
818 }
819 #endif
820
821 /*
822 * The reg properties on a PCI node are different than those
823 * on a non-PCI node. Handle that difference here.
824 * If it turns out to be a CardBus chip, we have even more
825 * differences.
826 */
827 if (pcic->pc_flags & PCF_PCIBUS) {
828 int class_code;
829 #if defined(__i386) || defined(__amd64)
830 pcic->pc_base = 0x1000000;
831 pcic->pc_bound = (uint32_t)~0;
832 pcic->pc_iobase = 0x1000;
833 pcic->pc_iobound = 0xefff;
834 #elif defined(__sparc)
835 pcic->pc_base = 0x0;
836 pcic->pc_bound = (uint32_t)~0;
837 pcic->pc_iobase = 0x00000;
838 pcic->pc_iobound = 0xffff;
839 #endif
840
841 /* usually need to get at config space so map first */
842 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
843 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
844 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
845
846 if (ddi_regs_map_setup(dip, pci_cfrn,
847 (caddr_t *)&pcic->cfgaddr,
848 PCIC_PCI_CONFIG_REG_OFFSET,
849 PCIC_PCI_CONFIG_REG_LENGTH,
850 &attr,
851 &pcic->cfg_handle) !=
852 DDI_SUCCESS) {
853 cmn_err(CE_CONT,
854 "pcic%d: unable to map config space"
855 "regs\n",
856 ddi_get_instance(dip));
857
858 kmem_free(pcic, sizeof (pcicdev_t));
859 return (DDI_FAILURE);
860 } /* ddi_regs_map_setup */
861
862 class_code = ddi_getprop(DDI_DEV_T_ANY, dip,
863 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS,
864 "class-code", -1);
865 #ifdef PCIC_DEBUG
866 if (pcic_debug) {
867 cmn_err(CE_CONT, "pcic_attach class_code=%x\n",
868 class_code);
869 }
870 #endif
871
872 switch (class_code) {
873 case PCIC_PCI_CARDBUS:
874 pcic->pc_flags |= PCF_CARDBUS;
875 pcic->pc_io_type = PCIC_IO_TYPE_YENTA;
876 /*
877 * Get access to the adapter registers on the
878 * PCI bus. A 4K memory page
879 */
880 #if defined(PCIC_DEBUG)
881 pcic_err(dip, 8, "Is Cardbus device\n");
882 if (pcic_debug) {
883 int nr;
884 long rs;
885 (void) ddi_dev_nregs(dip, &nr);
886 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p,"
887 "cfghndl 0x%p nregs %d",
888 (void *)pcic->cfgaddr,
889 (void *)pcic->cfg_handle, nr);
890
891 (void) ddi_dev_regsize(dip,
892 PCIC_PCI_CONTROL_REG_NUM, &rs);
893
894 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n",
895 PCIC_PCI_CONTROL_REG_NUM, (int)rs);
896 }
897 #endif
898 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
899 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
900 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
901
902 if (ddi_regs_map_setup(dip, pci_ctrn,
903 (caddr_t *)&pcic->ioaddr,
904 PCIC_PCI_CONTROL_REG_OFFSET,
905 PCIC_CB_CONTROL_REG_LENGTH,
906 &attr, &pcic->handle) !=
907 DDI_SUCCESS) {
908 cmn_err(CE_CONT,
909 "pcic%d: unable to map PCI regs\n",
910 ddi_get_instance(dip));
911 ddi_regs_map_free(&pcic->cfg_handle);
912 kmem_free(pcic, sizeof (pcicdev_t));
913 return (DDI_FAILURE);
914 } /* ddi_regs_map_setup */
915
916 /*
917 * Find out the chip type - If we're on a PCI bus,
918 * the adapter has that information in the PCI
919 * config space.
920 * Note that we call pcic_find_pci_type here since
921 * it needs a valid mapped pcic->handle to
922 * access some of the adapter registers in
923 * some cases.
924 */
925 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) {
926 ddi_regs_map_free(&pcic->handle);
927 ddi_regs_map_free(&pcic->cfg_handle);
928 kmem_free(pcic, sizeof (pcicdev_t));
929 cmn_err(CE_WARN, "pcic: %s: unsupported "
930 "bridge\n", ddi_get_name_addr(dip));
931 return (DDI_FAILURE);
932 }
933 break;
934
935 default:
936 case PCIC_PCI_PCMCIA:
937 /*
938 * Get access to the adapter IO registers on the
939 * PCI bus config space.
940 */
941 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
942 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
943 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
944
945 /*
946 * We need a default mapping to the adapter's IO
947 * control register space. For most adapters
948 * that are of class PCIC_PCI_PCMCIA (or of
949 * a default class) the control registers
950 * will be using the 82365-type control/data
951 * format.
952 */
953 if (ddi_regs_map_setup(dip, pci_ctrn,
954 (caddr_t *)&pcic->ioaddr,
955 PCIC_PCI_CONTROL_REG_OFFSET,
956 PCIC_PCI_CONTROL_REG_LENGTH,
957 &attr,
958 &pcic->handle) != DDI_SUCCESS) {
959 cmn_err(CE_CONT,
960 "pcic%d: unable to map PCI regs\n",
961 ddi_get_instance(dip));
962 ddi_regs_map_free(&pcic->cfg_handle);
963 kmem_free(pcic, sizeof (pcicdev_t));
964 return (DDI_FAILURE);
965 } /* ddi_regs_map_setup */
966
967 /*
968 * Find out the chip type - If we're on a PCI bus,
969 * the adapter has that information in the PCI
970 * config space.
971 * Note that we call pcic_find_pci_type here since
972 * it needs a valid mapped pcic->handle to
973 * access some of the adapter registers in
974 * some cases.
975 */
976 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) {
977 ddi_regs_map_free(&pcic->handle);
978 ddi_regs_map_free(&pcic->cfg_handle);
979 kmem_free(pcic, sizeof (pcicdev_t));
980 cmn_err(CE_WARN, "pcic: %s: unsupported "
981 "bridge\n",
982 ddi_get_name_addr(dip));
983 return (DDI_FAILURE);
984 }
985
986 /*
987 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant
988 * for extended registers even though they are
989 * not CardBus adapters. For those adapters,
990 * re-map pcic->handle to be large enough to
991 * encompass the Yenta registers.
992 */
993 switch (pcic->pc_type) {
994 case PCIC_TI_PCI1031:
995 ddi_regs_map_free(&pcic->handle);
996
997 if (ddi_regs_map_setup(dip,
998 PCIC_PCI_CONTROL_REG_NUM,
999 (caddr_t *)&pcic->ioaddr,
1000 PCIC_PCI_CONTROL_REG_OFFSET,
1001 PCIC_CB_CONTROL_REG_LENGTH,
1002 &attr,
1003 &pcic->handle) != DDI_SUCCESS) {
1004 cmn_err(CE_CONT,
1005 "pcic%d: unable to map "
1006 "PCI regs\n",
1007 ddi_get_instance(dip));
1008 ddi_regs_map_free(&pcic->cfg_handle);
1009 kmem_free(pcic, sizeof (pcicdev_t));
1010 return (DDI_FAILURE);
1011 } /* ddi_regs_map_setup */
1012 break;
1013 default:
1014 break;
1015 } /* switch (pcic->pc_type) */
1016 break;
1017 } /* switch (class_code) */
1018 } else {
1019 /*
1020 * We're not on a PCI bus, so assume an ISA bus type
1021 * register property. Get access to the adapter IO
1022 * registers on a non-PCI bus.
1023 */
1024 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
1025 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC;
1026 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
1027 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM;
1028 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM;
1029
1030 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM,
1031 (caddr_t *)&pcic->ioaddr,
1032 PCIC_ISA_CONTROL_REG_OFFSET,
1033 PCIC_ISA_CONTROL_REG_LENGTH,
1034 &attr,
1035 &pcic->handle) != DDI_SUCCESS) {
1036 cmn_err(CE_CONT,
1037 "pcic%d: unable to map ISA registers\n",
1038 ddi_get_instance(dip));
1039
1040 kmem_free(pcic, sizeof (pcicdev_t));
1041 return (DDI_FAILURE);
1042 } /* ddi_regs_map_setup */
1043
1044 /* ISA bus is limited to 24-bits, but not first 640K */
1045 pcic->pc_base = 0xd0000;
1046 pcic->pc_bound = (uint32_t)~0;
1047 pcic->pc_iobase = 0x1000;
1048 pcic->pc_iobound = 0xefff;
1049 } /* !PCF_PCIBUS */
1050
1051 #ifdef PCIC_DEBUG
1052 if (pcic_debug) {
1053 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n",
1054 pcic->pc_flags, pcic->pc_type);
1055 }
1056 #endif
1057
1058 /*
1059 * Setup various adapter registers for the PCI case. For the
1060 * non-PCI case, find out the chip type.
1061 */
1062 if (pcic->pc_flags & PCF_PCIBUS) {
1063 int iline;
1064 #if defined(__sparc)
1065 iline = 0;
1066 #else
1067 iline = cardbus_validate_iline(dip, pcic->cfg_handle);
1068 #endif
1069
1070 /* set flags and socket counts based on chip type */
1071 switch (pcic->pc_type) {
1072 uint32_t cfg;
1073 case PCIC_INTEL_i82092:
1074 cfg = ddi_get8(pcic->cfg_handle,
1075 pcic->cfgaddr + PCIC_82092_PCICON);
1076 /* we can only support 4 Socket version */
1077 if (cfg & PCIC_82092_4_SOCKETS) {
1078 pcic->pc_numsockets = 4;
1079 pcic->pc_type = PCIC_INTEL_i82092;
1080 if (iline != 0xFF)
1081 pcic->pc_intr_mode =
1082 PCIC_INTR_MODE_PCI_1;
1083 else
1084 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA;
1085 } else {
1086 cmn_err(CE_CONT,
1087 "pcic%d: Intel 82092 adapter "
1088 "in unsupported configuration: 0x%x",
1089 ddi_get_instance(pcic->dip), cfg);
1090 pcic->pc_numsockets = 0;
1091 } /* PCIC_82092_4_SOCKETS */
1092 break;
1093 case PCIC_CL_PD6730:
1094 case PCIC_CL_PD6729:
1095 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1;
1096 cfg = ddi_getprop(DDI_DEV_T_ANY, dip,
1097 DDI_PROP_CANSLEEP,
1098 "interrupts", 0);
1099 /* if not interrupt pin then must use ISA style IRQs */
1100 if (cfg == 0 || iline == 0xFF)
1101 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA;
1102 else {
1103 /*
1104 * we have the option to use PCI interrupts.
1105 * this might not be optimal but in some cases
1106 * is the only thing possible (sparc case).
1107 * we now deterine what is possible.
1108 */
1109 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1;
1110 }
1111 pcic->pc_numsockets = 2;
1112 pcic->pc_flags |= PCF_IO_REMAP;
1113 break;
1114 case PCIC_TI_PCI1031:
1115 /* this chip doesn't do CardBus but looks like one */
1116 pcic->pc_flags &= ~PCF_CARDBUS;
1117 /* FALLTHROUGH */
1118 default:
1119 pcic->pc_flags |= PCF_IO_REMAP;
1120 /* FALLTHROUGH */
1121 /* indicate feature even if not supported */
1122 pcic->pc_flags |= PCF_DMA | PCF_ZV;
1123 /* Not sure if these apply to all these chips */
1124 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP);
1125 pcic->pc_flags |= pcic_use_cbpwrctl;
1126
1127 pcic->pc_numsockets = 1; /* one per function */
1128 if (iline != 0xFF) {
1129 uint8_t cfg;
1130 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1;
1131
1132 cfg = ddi_get8(pcic->cfg_handle,
1133 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG));
1134 cfg &= (~PCIC_FUN_INT_MOD_ISA);
1135 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr +
1136 PCIC_BRIDGE_CTL_REG), cfg);
1137 }
1138 else
1139 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA;
1140 pcic->pc_io_type = PCIC_IOTYPE_YENTA;
1141 break;
1142 }
1143 } else {
1144 /*
1145 * We're not on a PCI bus so do some more
1146 * checking for adapter type here.
1147 * For the non-PCI bus case:
1148 * It could be any one of a number of different chips
1149 * If we can't determine anything else, it is assumed
1150 * to be an Intel 82365SL. The Cirrus Logic PD6710
1151 * has an extension register that provides unique
1152 * identification. Toshiba chip isn't detailed as yet.
1153 */
1154
1155 /* Init the CL id mode */
1156 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0);
1157 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO);
1158
1159 /* default to Intel i82365SL and then refine */
1160 pcic->pc_type = PCIC_I82365SL;
1161 pcic->pc_chipname = PCIC_TYPE_I82365SL;
1162 for (value = 0; pcic_ci_funcs[value] != NULL; value++) {
1163 /* go until one succeeds or none left */
1164 if (pcic_ci_funcs[value](pcic))
1165 break;
1166 }
1167
1168 /* any chip specific flags get set here */
1169 switch (pcic->pc_type) {
1170 case PCIC_CL_PD6722:
1171 pcic->pc_flags |= PCF_DMA;
1172 }
1173
1174 for (i = 0; i < PCIC_MAX_SOCKETS; i++) {
1175 /*
1176 * look for total number of sockets.
1177 * basically check each possible socket for
1178 * presence like in probe
1179 */
1180
1181 /* turn all windows off */
1182 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1183 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE);
1184
1185 /*
1186 * if a zero is read back, then this socket
1187 * might be present. It would be except for
1188 * some systems that map the secondary PCIC
1189 * chip space back to the first.
1190 */
1191 if (value != 0) {
1192 /* definitely not so skip */
1193 /* note: this is for Compaq support */
1194 continue;
1195 }
1196
1197 /* further tests */
1198 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) &
1199 PCIC_REV_MASK;
1200 if (!(value >= PCIC_REV_LEVEL_LOW &&
1201 value <= PCIC_REV_LEVEL_HI))
1202 break;
1203
1204 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa);
1205 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55);
1206 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW);
1207
1208 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW);
1209 if (value != 0xaa || j != 0x55)
1210 break;
1211
1212 /*
1213 * at this point we know if we have hardware
1214 * of some type and not just the bus holding
1215 * a pattern for us. We still have to determine
1216 * the case where more than 2 sockets are
1217 * really the same due to peculiar mappings of
1218 * hardware.
1219 */
1220 j = pcic->pc_numsockets++;
1221 pcic->pc_sockets[j].pcs_flags = 0;
1222 pcic->pc_sockets[j].pcs_io = pcic->ioaddr;
1223 pcic->pc_sockets[j].pcs_socket = i;
1224
1225 /* put PC Card into RESET, just in case */
1226 value = pcic_getb(pcic, i, PCIC_INTERRUPT);
1227 pcic_putb(pcic, i, PCIC_INTERRUPT,
1228 value & ~PCIC_RESET);
1229 }
1230
1231 #if defined(PCIC_DEBUG)
1232 if (pcic_debug)
1233 cmn_err(CE_CONT, "num sockets = %d\n",
1234 pcic->pc_numsockets);
1235 #endif
1236 if (pcic->pc_numsockets == 0) {
1237 ddi_regs_map_free(&pcic->handle);
1238 kmem_free(pcic, sizeof (pcicdev_t));
1239 return (DDI_FAILURE);
1240 }
1241
1242 /*
1243 * need to think this through again in light of
1244 * Compaq not following the model that all the
1245 * chip vendors recommend. IBM 755 seems to be
1246 * afflicted as well. Basically, if the vendor
1247 * wired things wrong, socket 0 responds for socket 2
1248 * accesses, etc.
1249 */
1250 if (pcic->pc_numsockets > 2) {
1251 int count = pcic->pc_numsockets / 4;
1252 for (i = 0; i < count; i++) {
1253 /* put pattern into socket 0 */
1254 pcic_putb(pcic, i,
1255 PCIC_SYSMEM_0_STARTLOW, 0x11);
1256
1257 /* put pattern into socket 2 */
1258 pcic_putb(pcic, i + 2,
1259 PCIC_SYSMEM_0_STARTLOW, 0x33);
1260
1261 /* read back socket 0 */
1262 value = pcic_getb(pcic, i,
1263 PCIC_SYSMEM_0_STARTLOW);
1264
1265 /* read back chip 1 socket 0 */
1266 j = pcic_getb(pcic, i + 2,
1267 PCIC_SYSMEM_0_STARTLOW);
1268 if (j == value) {
1269 pcic->pc_numsockets -= 2;
1270 }
1271 }
1272 }
1273
1274 smi = 0xff; /* no more override */
1275
1276 if (ddi_getprop(DDI_DEV_T_NONE, dip,
1277 DDI_PROP_DONTPASS, "need-mult-irq",
1278 0xffff) != 0xffff)
1279 pcic->pc_flags |= PCF_MULT_IRQ;
1280
1281 } /* !PCF_PCIBUS */
1282
1283 /*
1284 * some platforms/busses need to have resources setup
1285 * this is temporary until a real resource allocator is
1286 * implemented.
1287 */
1288
1289 pcic_init_assigned(dip);
1290
1291 typename = pcic->pc_chipname;
1292
1293 #ifdef PCIC_DEBUG
1294 if (pcic_debug) {
1295 int nregs, nintrs;
1296
1297 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS)
1298 nregs = 0;
1299
1300 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS)
1301 nintrs = 0;
1302
1303 cmn_err(CE_CONT,
1304 "pcic%d: %d register sets, %d interrupts\n",
1305 ddi_get_instance(dip), nregs, nintrs);
1306
1307 nintrs = 0;
1308 while (nregs--) {
1309 off_t size;
1310
1311 if (ddi_dev_regsize(dip, nintrs, &size) ==
1312 DDI_SUCCESS) {
1313 cmn_err(CE_CONT,
1314 "\tregnum %d size %ld (0x%lx)"
1315 "bytes",
1316 nintrs, size, size);
1317 if (nintrs ==
1318 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ?
1319 PCIC_ISA_CONTROL_REG_NUM :
1320 PCIC_PCI_CONTROL_REG_NUM))
1321 cmn_err(CE_CONT,
1322 " mapped at: 0x%p\n",
1323 (void *)pcic->ioaddr);
1324 else
1325 cmn_err(CE_CONT, "\n");
1326 } else {
1327 cmn_err(CE_CONT,
1328 "\tddi_dev_regsize(rnumber"
1329 "= %d) returns DDI_FAILURE\n",
1330 nintrs);
1331 }
1332 nintrs++;
1333 } /* while */
1334 } /* if (pcic_debug) */
1335 #endif
1336
1337 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL);
1338
1339 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
1340 "disable-audio", 0))
1341 pcic->pc_flags |= PCF_AUDIO;
1342
1343 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP,
1344 "disable-cardbus", 0))
1345 pcic->pc_flags &= ~PCF_CARDBUS;
1346
1347 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL,
1348 typename);
1349
1350 /*
1351 * Init all socket SMI levels to 0 (no SMI)
1352 */
1353 for (i = 0; i < PCIC_MAX_SOCKETS; i++) {
1354 pcic->pc_sockets[i].pcs_smi = 0;
1355 pcic->pc_sockets[i].pcs_debounce_id = 0;
1356 pcic->pc_sockets[i].pcs_pcic = pcic;
1357 }
1358 pcic->pc_lastreg = -1; /* just to make sure we are in sync */
1359
1360 /*
1361 * Setup the IRQ handler(s)
1362 */
1363 switch (pcic->pc_intr_mode) {
1364 int xx;
1365 case PCIC_INTR_MODE_ISA:
1366 /*
1367 * On a non-PCI bus, we just use whatever SMI IRQ level was
1368 * specified above, and the IO IRQ levels are allocated
1369 * dynamically.
1370 */
1371 for (xx = 15, smi = 0; xx >= 0; xx--) {
1372 if (PCIC_IRQ(xx) &
1373 PCIC_AVAIL_IRQS) {
1374 smi = pcmcia_get_intr(dip, xx);
1375 if (smi >= 0)
1376 break;
1377 }
1378 }
1379 #if defined(PCIC_DEBUG)
1380 if (pcic_debug)
1381 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi);
1382 #endif
1383 /* init to same so share is easy */
1384 for (i = 0; i < pcic->pc_numsockets; i++)
1385 pcic->pc_sockets[i].pcs_smi = smi;
1386 /* any special handling of IRQ levels */
1387 if (pcic->pc_flags & PCF_MULT_IRQ) {
1388 for (i = 2; i < pcic->pc_numsockets; i++) {
1389 if ((i & 1) == 0) {
1390 int xx;
1391 for (xx = 15, smi = 0; xx >= 0; xx--) {
1392 if (PCIC_IRQ(xx) &
1393 PCIC_AVAIL_IRQS) {
1394 smi =
1395 pcmcia_get_intr(dip,
1396 xx);
1397 if (smi >= 0)
1398 break;
1399 }
1400 }
1401 }
1402 if (smi >= 0)
1403 pcic->pc_sockets[i].pcs_smi = smi;
1404 }
1405 }
1406 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets *
1407 sizeof (ddi_intr_handle_t), KM_SLEEP);
1408 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) {
1409 struct intrspec *ispecp;
1410 struct ddi_parent_private_data *pdp;
1411
1412 if (irqlevel == pcic->pc_sockets[i].pcs_smi)
1413 continue;
1414 else {
1415 irqlevel = pcic->pc_sockets[i].pcs_smi;
1416 }
1417 /*
1418 * now convert the allocated IRQ into an intrspec
1419 * and ask our parent to add it. Don't use
1420 * the ddi_add_intr since we don't have a
1421 * default intrspec in all cases.
1422 *
1423 * note: this sort of violates DDI but we don't
1424 * get hardware intrspecs for many of the devices.
1425 * at the same time, we know how to allocate them
1426 * so we do the right thing.
1427 */
1428 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i],
1429 DDI_INTR_TYPE_FIXED, 0, 1, &actual,
1430 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) {
1431 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed",
1432 ddi_get_name(dip));
1433 goto isa_exit1;
1434 }
1435
1436 /*
1437 * See earlier note:
1438 * Since some devices don't have 'intrspec'
1439 * we make one up in rootnex.
1440 *
1441 * However, it is not properly initialized as
1442 * the data it needs is present in this driver
1443 * and there is no interface to pass that up.
1444 * Specially 'irqlevel' is very important and
1445 * it is part of pcic struct.
1446 *
1447 * Set 'intrspec' up here; otherwise adding the
1448 * interrupt will fail.
1449 */
1450 pdp = ddi_get_parent_data(dip);
1451 ispecp = (struct intrspec *)&pdp->par_intr[0];
1452 ispecp->intrspec_vec = irqlevel;
1453 ispecp->intrspec_pri = pcic->pc_irq;
1454
1455 /* Stay compatible w/ PCMCIA */
1456 pcic->pc_pri = (ddi_iblock_cookie_t)
1457 (uintptr_t)pcic->pc_irq;
1458 pcic->pc_dcookie.idev_priority =
1459 (uintptr_t)pcic->pc_pri;
1460 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel;
1461
1462 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i],
1463 pcic->pc_irq);
1464
1465 if (i == 0) {
1466 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER,
1467 DDI_INTR_PRI(pcic->pc_irq));
1468 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER,
1469 NULL);
1470 }
1471
1472 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i],
1473 pcic_intr, (caddr_t)pcic, NULL)) {
1474 cmn_err(CE_WARN,
1475 "%s: ddi_intr_add_handler failed",
1476 ddi_get_name(dip));
1477 goto isa_exit2;
1478 }
1479
1480 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) {
1481 cmn_err(CE_WARN, "%s: ddi_intr_enable failed",
1482 ddi_get_name(dip));
1483 for (j = i; j < 0; j--)
1484 (void) ddi_intr_remove_handler(
1485 pcic->pc_intr_htblp[j]);
1486 goto isa_exit2;
1487 }
1488 }
1489 break;
1490 case PCIC_INTR_MODE_PCI_1:
1491 case PCIC_INTR_MODE_PCI:
1492 /*
1493 * If we're on a PCI bus, we route all interrupts, both SMI
1494 * and IO interrupts, through a single interrupt line.
1495 * Assign the SMI IRQ level to the IO IRQ level here.
1496 */
1497 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t),
1498 KM_SLEEP);
1499 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp,
1500 DDI_INTR_TYPE_FIXED, 0, 1, &actual,
1501 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS)
1502 goto pci_exit1;
1503
1504 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0],
1505 &pri) != DDI_SUCCESS) {
1506 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]);
1507 goto pci_exit1;
1508 }
1509
1510 pcic->pc_pri = (void *)(uintptr_t)pri;
1511 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri);
1512 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL);
1513
1514 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0],
1515 pcic_intr, (caddr_t)pcic, NULL))
1516 goto pci_exit2;
1517
1518 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) {
1519 (void) ddi_intr_remove_handler(
1520 pcic->pc_pci_intr_hdlp[0]);
1521 goto pci_exit2;
1522 }
1523
1524 /* Stay compatible w/ PCMCIA */
1525 pcic->pc_dcookie.idev_priority = (ushort_t)pri;
1526
1527 /* init to same (PCI) so share is easy */
1528 for (i = 0; i < pcic->pc_numsockets; i++)
1529 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */
1530 break;
1531 }
1532
1533 /*
1534 * Setup the adapter hardware to some reasonable defaults.
1535 */
1536 mutex_enter(&pcic->pc_lock);
1537 /* mark the driver state as attached */
1538 pcic->pc_flags |= PCF_ATTACHED;
1539 pcic_setup_adapter(pcic);
1540
1541 for (j = 0; j < pcic->pc_numsockets; j++)
1542 if (ddi_intr_add_softint(dip,
1543 &pcic->pc_sockets[j].pcs_cd_softint_hdl,
1544 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint,
1545 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS)
1546 goto pci_exit2;
1547
1548 #if defined(PCIC_DEBUG)
1549 if (pcic_debug)
1550 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename,
1551 pcic->pc_numsockets);
1552 #endif
1553
1554 pcic_nexus->an_iblock = &pcic->pc_pri;
1555 pcic_nexus->an_idev = &pcic->pc_dcookie;
1556
1557 mutex_exit(&pcic->pc_lock);
1558
1559 #ifdef CARDBUS
1560 (void) cardbus_enable_cd_intr(dip);
1561 if (pcic_debug) {
1562
1563 cardbus_dump_pci_config(dip);
1564 cardbus_dump_socket(dip);
1565 }
1566
1567 /*
1568 * Give the Cardbus misc module a chance to do it's per-adapter
1569 * instance setup. Note that there is no corresponding detach()
1570 * call.
1571 */
1572 if (pcic->pc_flags & PCF_CARDBUS)
1573 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) {
1574 cmn_err(CE_CONT,
1575 "pcic_attach: cardbus_attach failed\n");
1576 goto pci_exit2;
1577 }
1578 #endif
1579
1580 /*
1581 * Give the PCMCIA misc module a chance to do it's per-adapter
1582 * instance setup.
1583 */
1584 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS)
1585 goto pci_exit2;
1586
1587 if (pcic_maxinst == -1) {
1588 /* This assumes that all instances run at the same IPL. */
1589 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL);
1590 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL);
1591 pcic_deb_threadid = thread_create((caddr_t)NULL, 0,
1592 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN,
1593 v.v_maxsyspri - 2);
1594 }
1595 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip));
1596 /*
1597 * Setup a debounce timeout to do an initial card detect
1598 * and enable interrupts.
1599 */
1600 for (j = 0; j < pcic->pc_numsockets; j++) {
1601 pcic->pc_sockets[j].pcs_debounce_id =
1602 pcic_add_debqueue(&pcic->pc_sockets[j],
1603 drv_usectohz(pcic_debounce_time));
1604 }
1605
1606 return (i);
1607
1608 isa_exit2:
1609 mutex_destroy(&pcic->intr_lock);
1610 mutex_destroy(&pcic->pc_lock);
1611 for (j = i; j < 0; j--)
1612 (void) ddi_intr_free(pcic->pc_intr_htblp[j]);
1613 isa_exit1:
1614 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi);
1615 ddi_regs_map_free(&pcic->handle);
1616 if (pcic->pc_flags & PCF_PCIBUS)
1617 ddi_regs_map_free(&pcic->cfg_handle);
1618 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets *
1619 sizeof (ddi_intr_handle_t));
1620 kmem_free(pcic, sizeof (pcicdev_t));
1621 return (DDI_FAILURE);
1622
1623 pci_exit2:
1624 mutex_destroy(&pcic->intr_lock);
1625 mutex_destroy(&pcic->pc_lock);
1626 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]);
1627 pci_exit1:
1628 ddi_regs_map_free(&pcic->handle);
1629 if (pcic->pc_flags & PCF_PCIBUS)
1630 ddi_regs_map_free(&pcic->cfg_handle);
1631 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t));
1632 kmem_free(pcic, sizeof (pcicdev_t));
1633 return (DDI_FAILURE);
1634 }
1635
1636 /*
1637 * pcic_detach()
1638 * request to detach from the system
1639 */
1640 static int
1641 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
1642 {
1643 anp_t *anp = ddi_get_driver_private(dip);
1644 pcicdev_t *pcic = anp->an_private;
1645 int i;
1646
1647 switch (cmd) {
1648 case DDI_DETACH:
1649 /* don't detach if the nexus still talks to us */
1650 if (pcic->pc_callback != NULL)
1651 return (DDI_FAILURE);
1652
1653 /* kill off the pm simulation */
1654 if (pcic->pc_pmtimer)
1655 (void) untimeout(pcic->pc_pmtimer);
1656
1657 /* turn everything off for all sockets and chips */
1658 for (i = 0; i < pcic->pc_numsockets; i++) {
1659 if (pcic->pc_sockets[i].pcs_debounce_id)
1660 pcic_rm_debqueue(
1661 pcic->pc_sockets[i].pcs_debounce_id);
1662 pcic->pc_sockets[i].pcs_debounce_id = 0;
1663
1664 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0);
1665 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0);
1666 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1667 /* disable interrupts and put card into RESET */
1668 pcic_putb(pcic, i, PCIC_INTERRUPT, 0);
1669 }
1670 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]);
1671 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]);
1672 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]);
1673 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t));
1674 pcic->pc_flags = 0;
1675 mutex_destroy(&pcic->pc_lock);
1676 mutex_destroy(&pcic->intr_lock);
1677 cv_destroy(&pcic->pm_cv);
1678 if (pcic->pc_flags & PCF_PCIBUS)
1679 ddi_regs_map_free(&pcic->cfg_handle);
1680 if (pcic->handle)
1681 ddi_regs_map_free(&pcic->handle);
1682 kmem_free(pcic, sizeof (pcicdev_t));
1683 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip));
1684 return (DDI_SUCCESS);
1685
1686 case DDI_SUSPEND:
1687 case DDI_PM_SUSPEND:
1688 /*
1689 * we got a suspend event (either real or imagined)
1690 * so notify the nexus proper that all existing cards
1691 * should go away.
1692 */
1693 mutex_enter(&pcic->pc_lock);
1694 #ifdef CARDBUS
1695 if (pcic->pc_flags & PCF_CARDBUS) {
1696 for (i = 0; i < pcic->pc_numsockets; i++) {
1697 if ((pcic->pc_sockets[i].pcs_flags &
1698 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) ==
1699 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) {
1700
1701 pcmcia_cb_suspended(
1702 pcic->pc_sockets[i].pcs_socket);
1703 }
1704 }
1705
1706 cardbus_save_children(ddi_get_child(dip));
1707 }
1708 #endif
1709 /* turn everything off for all sockets and chips */
1710 for (i = 0; i < pcic->pc_numsockets; i++) {
1711 if (pcic->pc_sockets[i].pcs_debounce_id)
1712 pcic_rm_debqueue(
1713 pcic->pc_sockets[i].pcs_debounce_id);
1714 pcic->pc_sockets[i].pcs_debounce_id = 0;
1715
1716 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0);
1717 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0);
1718 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1719 /* disable interrupts and put card into RESET */
1720 pcic_putb(pcic, i, PCIC_INTERRUPT, 0);
1721 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0);
1722 if (pcic->pc_flags & PCF_CBPWRCTL)
1723 pcic_putcb(pcic, CB_CONTROL, 0);
1724
1725 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) {
1726 pcic->pc_sockets[i].pcs_flags = PCS_STARTING;
1727 /*
1728 * Because we are half way through a save
1729 * all this does is schedule a removal event
1730 * to cs for when the system comes back.
1731 * This doesn't actually matter.
1732 */
1733 if (!pcic_do_pcmcia_sr && pcic_do_removal &&
1734 pcic->pc_callback) {
1735 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg,
1736 PCE_CARD_REMOVAL,
1737 pcic->pc_sockets[i].pcs_socket);
1738 }
1739 }
1740 }
1741
1742 pcic->pc_flags |= PCF_SUSPENDED;
1743 mutex_exit(&pcic->pc_lock);
1744
1745 /*
1746 * when true power management exists, save the adapter
1747 * state here to enable a recovery. For the emulation
1748 * condition, the state is gone
1749 */
1750 return (DDI_SUCCESS);
1751
1752 default:
1753 return (EINVAL);
1754 }
1755 }
1756
1757 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14));
1758 static uint32_t pcic_tisysctl_offbits = 0;
1759 static uint32_t pcic_default_latency = 0x40;
1760
1761 static void
1762 pcic_setup_adapter(pcicdev_t *pcic)
1763 {
1764 int i;
1765 int value, flags;
1766
1767 #if defined(__i386) || defined(__amd64)
1768 pci_regspec_t *reg;
1769 uchar_t bus, dev, func;
1770 uint_t classcode;
1771 int length;
1772 #endif
1773
1774 if (pcic->pc_flags & PCF_PCIBUS) {
1775 /*
1776 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled
1777 */
1778 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM);
1779 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags);
1780 }
1781 /* enable each socket */
1782 for (i = 0; i < pcic->pc_numsockets; i++) {
1783 pcic->pc_sockets[i].pcs_flags = 0;
1784 /* find out the socket capabilities (I/O vs memory) */
1785 value = pcic_getb(pcic, i,
1786 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK;
1787 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH)
1788 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO;
1789
1790 /* disable all windows just in case */
1791 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0);
1792
1793 switch (pcic->pc_type) {
1794 uint32_t cfg32;
1795 uint16_t cfg16;
1796 uint8_t cfg;
1797
1798 /* enable extended registers for Vadem */
1799 case PCIC_VADEM_VG469:
1800 case PCIC_VADEM:
1801
1802 /* enable card status change interrupt for socket */
1803 break;
1804
1805 case PCIC_I82365SL:
1806 break;
1807
1808 case PCIC_CL_PD6710:
1809 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE);
1810 break;
1811
1812 /*
1813 * On the CL_6730, we need to set up the interrupt
1814 * signalling mode (PCI mode) and set the SMI and
1815 * IRQ interrupt lines to PCI/level-mode.
1816 */
1817 case PCIC_CL_PD6730:
1818 switch (pcic->pc_intr_mode) {
1819 case PCIC_INTR_MODE_PCI_1:
1820 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3,
1821 ((clext_reg_read(pcic, i,
1822 PCIC_CLEXT_MISC_CTL_3) &
1823 ~PCIC_CLEXT_INT_PCI) |
1824 PCIC_CLEXT_INT_PCI));
1825 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1,
1826 (PCIC_CLEXT_IRQ_LVL_MODE |
1827 PCIC_CLEXT_SMI_LVL_MODE));
1828 cfg = PCIC_CL_LP_DYN_MODE;
1829 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg);
1830 break;
1831 case PCIC_INTR_MODE_ISA:
1832 break;
1833 }
1834 break;
1835 /*
1836 * On the CL_6729, we set the SMI and IRQ interrupt
1837 * lines to PCI/level-mode. as well as program the
1838 * correct clock speed divider bit.
1839 */
1840 case PCIC_CL_PD6729:
1841 switch (pcic->pc_intr_mode) {
1842 case PCIC_INTR_MODE_PCI_1:
1843 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1,
1844 (PCIC_CLEXT_IRQ_LVL_MODE |
1845 PCIC_CLEXT_SMI_LVL_MODE));
1846
1847 break;
1848 case PCIC_INTR_MODE_ISA:
1849 break;
1850 }
1851 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) {
1852 cfg = 0;
1853 cfg |= PCIC_CL_TIMER_CLK_DIV;
1854 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg);
1855 }
1856 break;
1857 case PCIC_INTEL_i82092:
1858 cfg = PCIC_82092_EN_TIMING;
1859 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ)
1860 cfg |= PCIC_82092_PCICLK_25MHZ;
1861 ddi_put8(pcic->cfg_handle, pcic->cfgaddr +
1862 PCIC_82092_PCICON, cfg);
1863 break;
1864 case PCIC_TI_PCI1130:
1865 case PCIC_TI_PCI1131:
1866 case PCIC_TI_PCI1250:
1867 case PCIC_TI_PCI1031:
1868 cfg = ddi_get8(pcic->cfg_handle,
1869 pcic->cfgaddr + PCIC_DEVCTL_REG);
1870 cfg &= ~PCIC_DEVCTL_INTR_MASK;
1871 switch (pcic->pc_intr_mode) {
1872 case PCIC_INTR_MODE_ISA:
1873 cfg |= PCIC_DEVCTL_INTR_ISA;
1874 break;
1875 }
1876 #ifdef PCIC_DEBUG
1877 if (pcic_debug) {
1878 cmn_err(CE_CONT, "pcic_setup_adapter: "
1879 "write reg 0x%x=%x \n",
1880 PCIC_DEVCTL_REG, cfg);
1881 }
1882 #endif
1883 ddi_put8(pcic->cfg_handle,
1884 pcic->cfgaddr + PCIC_DEVCTL_REG,
1885 cfg);
1886
1887 cfg = ddi_get8(pcic->cfg_handle,
1888 pcic->cfgaddr + PCIC_CRDCTL_REG);
1889 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC|
1890 PCIC_CRDCTL_PCIFUNC);
1891 switch (pcic->pc_intr_mode) {
1892 case PCIC_INTR_MODE_PCI_1:
1893 cfg |= PCIC_CRDCTL_PCIINTR |
1894 PCIC_CRDCTL_PCICSC |
1895 PCIC_CRDCTL_PCIFUNC;
1896 pcic->pc_flags |= PCF_USE_SMI;
1897 break;
1898 }
1899 #ifdef PCIC_DEBUG
1900 if (pcic_debug) {
1901 cmn_err(CE_CONT, "pcic_setup_adapter: "
1902 " write reg 0x%x=%x \n",
1903 PCIC_CRDCTL_REG, cfg);
1904 }
1905 #endif
1906 ddi_put8(pcic->cfg_handle,
1907 pcic->cfgaddr + PCIC_CRDCTL_REG,
1908 cfg);
1909 break;
1910 case PCIC_TI_PCI1221:
1911 case PCIC_TI_PCI1225:
1912 cfg = ddi_get8(pcic->cfg_handle,
1913 pcic->cfgaddr + PCIC_DEVCTL_REG);
1914 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE);
1915 #ifdef PCIC_DEBUG
1916 if (pcic_debug) {
1917 cmn_err(CE_CONT, "pcic_setup_adapter: "
1918 " write reg 0x%x=%x \n",
1919 PCIC_DEVCTL_REG, cfg);
1920 }
1921 #endif
1922 ddi_put8(pcic->cfg_handle,
1923 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg);
1924
1925 cfg = ddi_get8(pcic->cfg_handle,
1926 pcic->cfgaddr + PCIC_DIAG_REG);
1927 if (pcic->pc_type == PCIC_TI_PCI1225) {
1928 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC);
1929 } else {
1930 cfg |= PCIC_DIAG_ASYNC;
1931 }
1932 pcic->pc_flags |= PCF_USE_SMI;
1933 #ifdef PCIC_DEBUG
1934 if (pcic_debug) {
1935 cmn_err(CE_CONT, "pcic_setup_adapter: "
1936 " write reg 0x%x=%x \n",
1937 PCIC_DIAG_REG, cfg);
1938 }
1939 #endif
1940 ddi_put8(pcic->cfg_handle,
1941 pcic->cfgaddr + PCIC_DIAG_REG, cfg);
1942 break;
1943 case PCIC_TI_PCI1520:
1944 case PCIC_TI_PCI1510:
1945 case PCIC_TI_VENDOR:
1946 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) {
1947 /* functional intr routed by ExCA register */
1948 cfg = ddi_get8(pcic->cfg_handle,
1949 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
1950 cfg |= PCIC_FUN_INT_MOD_ISA;
1951 ddi_put8(pcic->cfg_handle,
1952 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
1953 cfg);
1954
1955 /* IRQ serialized interrupts */
1956 cfg = ddi_get8(pcic->cfg_handle,
1957 pcic->cfgaddr + PCIC_DEVCTL_REG);
1958 cfg &= ~PCIC_DEVCTL_INTR_MASK;
1959 cfg |= PCIC_DEVCTL_INTR_ISA;
1960 ddi_put8(pcic->cfg_handle,
1961 pcic->cfgaddr + PCIC_DEVCTL_REG,
1962 cfg);
1963 break;
1964 }
1965
1966 /* CSC interrupt routed to PCI */
1967 cfg = ddi_get8(pcic->cfg_handle,
1968 pcic->cfgaddr + PCIC_DIAG_REG);
1969 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC);
1970 ddi_put8(pcic->cfg_handle,
1971 pcic->cfgaddr + PCIC_DIAG_REG, cfg);
1972
1973 #if defined(__i386) || defined(__amd64)
1974 /*
1975 * Some TI chips have 2 cardbus slots(function0 and
1976 * function1), and others may have just 1 cardbus slot.
1977 * The interrupt routing register is shared between the
1978 * 2 functions and can only be accessed through
1979 * function0. Here we check the presence of the second
1980 * cardbus slot and do the right thing.
1981 */
1982
1983 if (ddi_getlongprop(DDI_DEV_T_ANY, pcic->dip,
1984 DDI_PROP_DONTPASS, "reg", (caddr_t)®,
1985 &length) != DDI_PROP_SUCCESS) {
1986 cmn_err(CE_WARN,
1987 "pcic_setup_adapter(), failed to"
1988 " read reg property\n");
1989 break;
1990 }
1991
1992 bus = PCI_REG_BUS_G(reg->pci_phys_hi);
1993 dev = PCI_REG_DEV_G(reg->pci_phys_hi);
1994 func = PCI_REG_FUNC_G(reg->pci_phys_hi);
1995 kmem_free((caddr_t)reg, length);
1996
1997 if (func != 0) {
1998 break;
1999 }
2000
2001 classcode = (*pci_getl_func)(bus, dev, 1,
2002 PCI_CONF_REVID);
2003 classcode >>= 8;
2004 if (classcode != 0x060700 &&
2005 classcode != 0x060500) {
2006 break;
2007 }
2008
2009 /* Parallel PCI interrupts only */
2010 cfg = ddi_get8(pcic->cfg_handle,
2011 pcic->cfgaddr + PCIC_DEVCTL_REG);
2012 cfg &= ~PCIC_DEVCTL_INTR_MASK;
2013 ddi_put8(pcic->cfg_handle,
2014 pcic->cfgaddr + PCIC_DEVCTL_REG,
2015 cfg);
2016
2017 /* tie INTA and INTB together */
2018 cfg = ddi_get8(pcic->cfg_handle,
2019 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3));
2020 cfg |= PCIC_SYSCTL_INTRTIE;
2021 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr +
2022 PCIC_SYSCTL_REG + 3), cfg);
2023 #endif
2024
2025 break;
2026 case PCIC_TI_PCI1410:
2027 cfg = ddi_get8(pcic->cfg_handle,
2028 pcic->cfgaddr + PCIC_DIAG_REG);
2029 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC);
2030 ddi_put8(pcic->cfg_handle,
2031 pcic->cfgaddr + PCIC_DIAG_REG, cfg);
2032 break;
2033 case PCIC_TOSHIBA_TOPIC100:
2034 case PCIC_TOSHIBA_TOPIC95:
2035 case PCIC_TOSHIBA_VENDOR:
2036 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr +
2037 PCIC_TOSHIBA_SLOT_CTL_REG);
2038 cfg |= (PCIC_TOSHIBA_SCR_SLOTON |
2039 PCIC_TOSHIBA_SCR_SLOTEN);
2040 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK);
2041 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2;
2042 ddi_put8(pcic->cfg_handle, pcic->cfgaddr +
2043 PCIC_TOSHIBA_SLOT_CTL_REG, cfg);
2044 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr +
2045 PCIC_TOSHIBA_INTR_CTL_REG);
2046 switch (pcic->pc_intr_mode) {
2047 case PCIC_INTR_MODE_ISA:
2048 cfg &= ~PCIC_TOSHIBA_ICR_SRC;
2049 ddi_put8(pcic->cfg_handle,
2050 pcic->cfgaddr +
2051 PCIC_TOSHIBA_INTR_CTL_REG, cfg);
2052
2053 cfg = ddi_get8(pcic->cfg_handle,
2054 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
2055 cfg |= PCIC_FUN_INT_MOD_ISA;
2056 ddi_put8(pcic->cfg_handle,
2057 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
2058 cfg);
2059 break;
2060 case PCIC_INTR_MODE_PCI_1:
2061 cfg |= PCIC_TOSHIBA_ICR_SRC;
2062 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK);
2063 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA;
2064 ddi_put8(pcic->cfg_handle,
2065 pcic->cfgaddr +
2066 PCIC_TOSHIBA_INTR_CTL_REG, cfg);
2067 break;
2068 }
2069 break;
2070 case PCIC_O2MICRO_VENDOR:
2071 cfg32 = ddi_get32(pcic->cfg_handle,
2072 (uint32_t *)(pcic->cfgaddr +
2073 PCIC_O2MICRO_MISC_CTL));
2074 switch (pcic->pc_intr_mode) {
2075 case PCIC_INTR_MODE_ISA:
2076 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY |
2077 PCIC_O2MICRO_INT_MOD_PCI);
2078 ddi_put32(pcic->cfg_handle,
2079 (uint32_t *)(pcic->cfgaddr +
2080 PCIC_O2MICRO_MISC_CTL),
2081 cfg32);
2082 cfg = ddi_get8(pcic->cfg_handle,
2083 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
2084 cfg |= PCIC_FUN_INT_MOD_ISA;
2085 ddi_put8(pcic->cfg_handle,
2086 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
2087 cfg);
2088 break;
2089 case PCIC_INTR_MODE_PCI_1:
2090 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY;
2091 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI;
2092 ddi_put32(pcic->cfg_handle,
2093 (uint32_t *)(pcic->cfgaddr +
2094 PCIC_O2MICRO_MISC_CTL),
2095 cfg32);
2096 break;
2097 }
2098 break;
2099 case PCIC_RICOH_VENDOR:
2100 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) {
2101 cfg16 = ddi_get16(pcic->cfg_handle,
2102 (uint16_t *)(pcic->cfgaddr +
2103 PCIC_RICOH_MISC_CTL_2));
2104 cfg16 |= (PCIC_RICOH_CSC_INT_MOD |
2105 PCIC_RICOH_FUN_INT_MOD);
2106 ddi_put16(pcic->cfg_handle,
2107 (uint16_t *)(pcic->cfgaddr +
2108 PCIC_RICOH_MISC_CTL_2),
2109 cfg16);
2110
2111 cfg16 = ddi_get16(pcic->cfg_handle,
2112 (uint16_t *)(pcic->cfgaddr +
2113 PCIC_RICOH_MISC_CTL));
2114 cfg16 |= PCIC_RICOH_SIRQ_EN;
2115 ddi_put16(pcic->cfg_handle,
2116 (uint16_t *)(pcic->cfgaddr +
2117 PCIC_RICOH_MISC_CTL),
2118 cfg16);
2119
2120 cfg = ddi_get8(pcic->cfg_handle,
2121 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
2122 cfg |= PCIC_FUN_INT_MOD_ISA;
2123 ddi_put8(pcic->cfg_handle,
2124 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
2125 cfg);
2126 }
2127 break;
2128 default:
2129 break;
2130 } /* switch */
2131
2132 /*
2133 * The default value in the EEPROM (loaded on reset) for
2134 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that
2135 * MFUNC0 is connected to INTA, and MFUNC1 is connected to
2136 * INTB. This applies to all TI CardBus controllers.
2137 */
2138 if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID &&
2139 pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) {
2140 value = ddi_get32(pcic->cfg_handle,
2141 (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG));
2142 value &= ~0xff;
2143 ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr +
2144 PCIC_MFROUTE_REG), value|PCIC_TI_MFUNC_SEL);
2145 }
2146
2147 /* setup general card status change interrupt */
2148 switch (pcic->pc_type) {
2149 case PCIC_TI_PCI1225:
2150 case PCIC_TI_PCI1221:
2151 case PCIC_TI_PCI1031:
2152 case PCIC_TI_PCI1520:
2153 case PCIC_TI_PCI1410:
2154 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT,
2155 PCIC_CHANGE_DEFAULT);
2156 break;
2157 default:
2158 if (pcic->pc_intr_mode ==
2159 PCIC_INTR_MODE_PCI_1) {
2160 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT,
2161 PCIC_CHANGE_DEFAULT);
2162 break;
2163 } else {
2164 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT,
2165 PCIC_CHANGE_DEFAULT |
2166 (pcic->pc_sockets[i].pcs_smi << 4));
2167 break;
2168 }
2169 }
2170
2171 pcic->pc_flags |= PCF_INTRENAB;
2172
2173 /* take card out of RESET */
2174 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET);
2175 /* turn power off and let CS do this */
2176 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0);
2177
2178 /* final chip specific initialization */
2179 switch (pcic->pc_type) {
2180 case PCIC_VADEM:
2181 pcic_putb(pcic, i, PCIC_VG_CONTROL,
2182 PCIC_VC_DELAYENABLE);
2183 pcic->pc_flags |= PCF_DEBOUNCE;
2184 /* FALLTHROUGH */
2185 case PCIC_I82365SL:
2186 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL,
2187 PCIC_GC_CSC_WRITE);
2188 /* clear any pending interrupts */
2189 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE);
2190 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value);
2191 break;
2192 /* The 82092 uses PCI config space to enable interrupts */
2193 case PCIC_INTEL_i82092:
2194 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI,
2195 PCIC_82092_INT_ENABLE);
2196 break;
2197 case PCIC_CL_PD6729:
2198 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) {
2199 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2);
2200 pcic_putb(pcic, i, PCIC_MISC_CTL_2,
2201 value | PCIC_CL_TIMER_CLK_DIV);
2202 }
2203 break;
2204 } /* switch */
2205
2206 #if defined(PCIC_DEBUG)
2207 if (pcic_debug)
2208 cmn_err(CE_CONT,
2209 "socket %d value=%x, flags = %x (%s)\n",
2210 i, value, pcic->pc_sockets[i].pcs_flags,
2211 (pcic->pc_sockets[i].pcs_flags &
2212 PCS_CARD_PRESENT) ?
2213 "card present" : "no card");
2214 #endif
2215 }
2216 }
2217
2218 /*
2219 * pcic_intr(caddr_t, caddr_t)
2220 * interrupt handler for the PCIC style adapter
2221 * handles all basic interrupts and also checks
2222 * for status changes and notifies the nexus if
2223 * necessary
2224 *
2225 * On PCI bus adapters, also handles all card
2226 * IO interrupts.
2227 */
2228 /*ARGSUSED*/
2229 uint32_t
2230 pcic_intr(caddr_t arg1, caddr_t arg2)
2231 {
2232 pcicdev_t *pcic = (pcicdev_t *)arg1;
2233 int value = 0, i, ret = DDI_INTR_UNCLAIMED;
2234 uint8_t status;
2235 uint_t io_ints;
2236
2237 #if defined(PCIC_DEBUG)
2238 pcic_err(pcic->dip, 0xf,
2239 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x"
2240 " pc_numsockets=%d \n",
2241 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets);
2242 #endif
2243
2244 if (!(pcic->pc_flags & PCF_ATTACHED))
2245 return (DDI_INTR_UNCLAIMED);
2246
2247 mutex_enter(&pcic->intr_lock);
2248
2249 if (pcic->pc_flags & PCF_SUSPENDED) {
2250 mutex_exit(&pcic->intr_lock);
2251 return (ret);
2252 }
2253
2254 /*
2255 * need to change to only ACK and touch the slot that
2256 * actually caused the interrupt. Currently everything
2257 * is acked
2258 *
2259 * we need to look at all known sockets to determine
2260 * what might have happened, so step through the list
2261 * of them
2262 */
2263
2264 /*
2265 * Set the bitmask for IO interrupts to initially include all sockets
2266 */
2267 io_ints = (1 << pcic->pc_numsockets) - 1;
2268
2269 for (i = 0; i < pcic->pc_numsockets; i++) {
2270 int card_type;
2271 pcic_socket_t *sockp;
2272 int value_cb = 0;
2273
2274 sockp = &pcic->pc_sockets[i];
2275 /* get the socket's I/O addresses */
2276
2277 if (sockp->pcs_flags & PCS_WAITING) {
2278 io_ints &= ~(1 << i);
2279 continue;
2280 }
2281
2282 if (sockp->pcs_flags & PCS_CARD_IO)
2283 card_type = IF_IO;
2284 else
2285 card_type = IF_MEMORY;
2286
2287 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA)
2288 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT);
2289
2290 value = pcic_change(pcic, i);
2291
2292 if ((value != 0) || (value_cb != 0)) {
2293 int x = pcic->pc_cb_arg;
2294
2295 ret = DDI_INTR_CLAIMED;
2296
2297 #if defined(PCIC_DEBUG)
2298 pcic_err(pcic->dip, 0x9,
2299 "card_type = %d, value_cb = 0x%x\n",
2300 card_type,
2301 value_cb ? value_cb :
2302 pcic_getcb(pcic, CB_STATUS_EVENT));
2303 if (pcic_debug)
2304 cmn_err(CE_CONT,
2305 "\tchange on socket %d (%x)\n", i,
2306 value);
2307 #endif
2308 /* find out what happened */
2309 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS);
2310
2311 /* acknowledge the interrupt */
2312 if (value_cb)
2313 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb);
2314
2315 if (value)
2316 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE,
2317 value);
2318
2319 if (pcic->pc_callback == NULL) {
2320 /* if not callback handler, nothing to do */
2321 continue;
2322 }
2323
2324 /* Card Detect */
2325 if (value & PCIC_CD_DETECT ||
2326 value_cb & CB_PS_CCDMASK) {
2327 uint8_t irq;
2328 #if defined(PCIC_DEBUG)
2329 if (pcic_debug)
2330 cmn_err(CE_CONT,
2331 "\tcd_detect: status=%x,"
2332 " flags=%x\n",
2333 status, sockp->pcs_flags);
2334 #else
2335 #ifdef lint
2336 if (status == 0)
2337 status++;
2338 #endif
2339 #endif
2340 /*
2341 * Turn off all interrupts for this socket here.
2342 */
2343 irq = pcic_getb(pcic, sockp->pcs_socket,
2344 PCIC_MANAGEMENT_INT);
2345 irq &= ~PCIC_CHANGE_MASK;
2346 pcic_putb(pcic, sockp->pcs_socket,
2347 PCIC_MANAGEMENT_INT, irq);
2348
2349 pcic_putcb(pcic, CB_STATUS_MASK, 0x0);
2350
2351 /*
2352 * Put the socket in debouncing state so that
2353 * the leaf driver won't receive interrupts.
2354 * Crucial for handling surprise-removal.
2355 */
2356 sockp->pcs_flags |= PCS_DEBOUNCING;
2357
2358 if (!sockp->pcs_cd_softint_flg) {
2359 sockp->pcs_cd_softint_flg = 1;
2360 (void) ddi_intr_trigger_softint(
2361 sockp->pcs_cd_softint_hdl, NULL);
2362 }
2363
2364 io_ints &= ~(1 << i);
2365 } /* PCIC_CD_DETECT */
2366
2367 /* Ready/Change Detect */
2368 sockp->pcs_state ^= SBM_RDYBSY;
2369 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) {
2370 sockp->pcs_flags |= PCS_READY;
2371 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i);
2372 }
2373
2374 /* Battery Warn Detect */
2375 if (card_type == IF_MEMORY &&
2376 value & PCIC_BW_DETECT &&
2377 !(sockp->pcs_state & SBM_BVD2)) {
2378 sockp->pcs_state |= SBM_BVD2;
2379 PC_CALLBACK(pcic->dip, x,
2380 PCE_CARD_BATTERY_WARN, i);
2381 }
2382
2383 /* Battery Dead Detect */
2384 if (value & PCIC_BD_DETECT) {
2385 /*
2386 * need to work out event if RI not enabled
2387 * and card_type == IF_IO
2388 */
2389 if (card_type == IF_MEMORY &&
2390 !(sockp->pcs_state & SBM_BVD1)) {
2391 sockp->pcs_state |= SBM_BVD1;
2392 PC_CALLBACK(pcic->dip, x,
2393 PCE_CARD_BATTERY_DEAD,
2394 i);
2395 } else {
2396 /*
2397 * information in pin replacement
2398 * register if one is available
2399 */
2400 PC_CALLBACK(pcic->dip, x,
2401 PCE_CARD_STATUS_CHANGE,
2402 i);
2403 } /* IF_MEMORY */
2404 } /* PCIC_BD_DETECT */
2405 } /* if pcic_change */
2406 /*
2407 * for any controllers that we can detect whether a socket
2408 * had an interrupt for the PC Card, we should sort that out
2409 * here.
2410 */
2411 } /* for pc_numsockets */
2412
2413 /*
2414 * If we're on a PCI bus, we may need to cycle through each IO
2415 * interrupt handler that is registered since they all
2416 * share the same interrupt line.
2417 */
2418
2419
2420 #if defined(PCIC_DEBUG)
2421 pcic_err(pcic->dip, 0xf,
2422 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n",
2423 pcic->pc_intr_mode, pcic->pc_type, io_ints);
2424 #endif
2425
2426 if (io_ints) {
2427 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED)
2428 ret = DDI_INTR_CLAIMED;
2429 }
2430
2431 mutex_exit(&pcic->intr_lock);
2432
2433 #if defined(PCIC_DEBUG)
2434 pcic_err(pcic->dip, 0xf,
2435 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n",
2436 ret, value, DDI_INTR_CLAIMED);
2437 #endif
2438
2439 return (ret);
2440 }
2441
2442 /*
2443 * pcic_change()
2444 * check to see if this socket had a change in state
2445 * by checking the status change register
2446 */
2447 static int
2448 pcic_change(pcicdev_t *pcic, int socket)
2449 {
2450 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE));
2451 }
2452
2453 /*
2454 * pcic_do_io_intr - calls client interrupt handlers
2455 */
2456 static int
2457 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets)
2458 {
2459 inthandler_t *tmp;
2460 int ret = DDI_INTR_UNCLAIMED;
2461
2462 #if defined(PCIC_DEBUG)
2463 pcic_err(pcic->dip, 0xf,
2464 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n",
2465 (void *)pcic, (int)sockets, (void *)pcic->irq_top);
2466 #endif
2467
2468 if (pcic->irq_top != NULL) {
2469 tmp = pcic->irq_current;
2470
2471 do {
2472 int cur = pcic->irq_current->socket;
2473 pcic_socket_t *sockp =
2474 &pcic->pc_sockets[cur];
2475
2476 #if defined(PCIC_DEBUG)
2477 pcic_err(pcic->dip, 0xf,
2478 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n",
2479 sockp->pcs_flags, PCS_CARD_PRESENT);
2480 pcic_err(pcic->dip, 0xf,
2481 "\t sockets=%d cur=%d intr=%p arg1=%p "
2482 "arg2=%p\n",
2483 sockets, cur, (void *)pcic->irq_current->intr,
2484 pcic->irq_current->arg1,
2485 pcic->irq_current->arg2);
2486 #endif
2487 if ((sockp->pcs_flags & PCS_CARD_PRESENT) &&
2488 !(sockp->pcs_flags & PCS_DEBOUNCING) &&
2489 (sockets & (1 << cur))) {
2490
2491 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1,
2492 pcic->irq_current->arg2) == DDI_INTR_CLAIMED)
2493 ret = DDI_INTR_CLAIMED;
2494
2495 #if defined(PCIC_DEBUG)
2496 pcic_err(pcic->dip, 0xf,
2497 "\t ret=%d DDI_INTR_CLAIMED=%d\n",
2498 ret, DDI_INTR_CLAIMED);
2499 #endif
2500 }
2501
2502
2503 if ((pcic->irq_current = pcic->irq_current->next) == NULL)
2504 pcic->irq_current = pcic->irq_top;
2505
2506 } while (pcic->irq_current != tmp);
2507
2508 if ((pcic->irq_current = pcic->irq_current->next) == NULL)
2509 pcic->irq_current = pcic->irq_top;
2510
2511 } else {
2512 ret = DDI_INTR_UNCLAIMED;
2513 }
2514
2515 #if defined(PCIC_DEBUG)
2516 pcic_err(pcic->dip, 0xf,
2517 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n",
2518 ret, DDI_INTR_CLAIMED);
2519 #endif
2520
2521 return (ret);
2522
2523 }
2524
2525 /*
2526 * pcic_inquire_adapter()
2527 * SocketServices InquireAdapter function
2528 * get characteristics of the physical adapter
2529 */
2530 /*ARGSUSED*/
2531 static int
2532 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config)
2533 {
2534 anp_t *anp = ddi_get_driver_private(dip);
2535 pcicdev_t *pcic = anp->an_private;
2536
2537 config->NumSockets = pcic->pc_numsockets;
2538 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK;
2539 config->NumEDCs = 0;
2540 config->AdpCaps = 0;
2541 config->ActiveHigh = 0;
2542 config->ActiveLow = PCIC_AVAIL_IRQS;
2543 config->NumPower = pcic->pc_numpower;
2544 config->power_entry = pcic->pc_power; /* until we resolve this */
2545 #if defined(PCIC_DEBUG)
2546 if (pcic_debug) {
2547 cmn_err(CE_CONT, "pcic_inquire_adapter:\n");
2548 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets);
2549 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows);
2550 }
2551 #endif
2552 config->ResourceFlags = 0;
2553 switch (pcic->pc_intr_mode) {
2554 case PCIC_INTR_MODE_PCI_1:
2555 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS |
2556 RES_IRQ_SHAREABLE;
2557 break;
2558 }
2559 return (SUCCESS);
2560 }
2561
2562 /*
2563 * pcic_callback()
2564 * The PCMCIA nexus calls us via this function
2565 * in order to set the callback function we are
2566 * to call the nexus with
2567 */
2568 /*ARGSUSED*/
2569 static int
2570 pcic_callback(dev_info_t *dip, int (*handler)(), int arg)
2571 {
2572 anp_t *anp = ddi_get_driver_private(dip);
2573 pcicdev_t *pcic = anp->an_private;
2574
2575 if (handler != NULL) {
2576 pcic->pc_callback = handler;
2577 pcic->pc_cb_arg = arg;
2578 pcic->pc_flags |= PCF_CALLBACK;
2579 } else {
2580 pcic->pc_callback = NULL;
2581 pcic->pc_cb_arg = 0;
2582 pcic->pc_flags &= ~PCF_CALLBACK;
2583 }
2584 /*
2585 * we're now registered with the nexus
2586 * it is acceptable to do callbacks at this point.
2587 * don't call back from here though since it could block
2588 */
2589 return (PC_SUCCESS);
2590 }
2591
2592 /*
2593 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed)
2594 * calculate the speed bits from the specified memory speed
2595 * there may be more to do here
2596 */
2597
2598 static int
2599 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed)
2600 {
2601 uint32_t wspeed = 1; /* assume 1 wait state when unknown */
2602 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK;
2603
2604 switch (pcic->pc_type) {
2605 case PCIC_I82365SL:
2606 case PCIC_VADEM:
2607 case PCIC_VADEM_VG469:
2608 default:
2609 /* Intel chip wants it in waitstates */
2610 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3;
2611 if (speed <= wspeed)
2612 wspeed = 0;
2613 else if (speed <= (wspeed += mhztons(bspeed)))
2614 wspeed = 1;
2615 else if (speed <= (wspeed += mhztons(bspeed)))
2616 wspeed = 2;
2617 else
2618 wspeed = 3;
2619 wspeed <<= 6; /* put in right bit positions */
2620 break;
2621
2622 case PCIC_INTEL_i82092:
2623 wspeed = SYSMEM_82092_80NS;
2624 if (speed > 80)
2625 wspeed = SYSMEM_82092_100NS;
2626 if (speed > 100)
2627 wspeed = SYSMEM_82092_150NS;
2628 if (speed > 150)
2629 wspeed = SYSMEM_82092_200NS;
2630 if (speed > 200)
2631 wspeed = SYSMEM_82092_250NS;
2632 if (speed > 250)
2633 wspeed = SYSMEM_82092_600NS;
2634 wspeed <<= 5; /* put in right bit positions */
2635 break;
2636
2637 } /* switch */
2638
2639 return (wspeed);
2640 }
2641
2642 /*
2643 * These values are taken from the PC Card Standard Electrical Specification.
2644 * Generally the larger value is taken if 2 are possible.
2645 */
2646 static struct pcic_card_times {
2647 uint16_t cycle; /* Speed as found in the atribute space of he card. */
2648 uint16_t setup; /* Corresponding address setup time. */
2649 uint16_t width; /* Corresponding width, OE or WE. */
2650 uint16_t hold; /* Corresponding data or address hold time. */
2651 } pcic_card_times[] = {
2652
2653 /*
2654 * Note: The rounded up times for 250, 200 & 150 have been increased
2655 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi.
2656 * See BugID 00663.
2657 */
2658
2659 /*
2660 * Rounded up times Original times from
2661 * that add up to the the PCMCIA Spec.
2662 * cycle time.
2663 */
2664 {600, 180, 370, 140}, /* 100, 300, 70 */
2665 {400, 120, 300, 90}, /* Made this one up */
2666 {250, 100, 190, 70}, /* 30, 150, 30 */
2667 {200, 80, 170, 70}, /* 20, 120, 30 */
2668 {150, 50, 110, 40}, /* 20, 80, 20 */
2669 {100, 40, 80, 40}, /* 10, 60, 15 */
2670 {0, 10, 60, 15} /* 10, 60, 15 */
2671 };
2672
2673 /*
2674 * pcic_set_cdtimers
2675 * This is specific to several Cirrus Logic chips
2676 */
2677 static void
2678 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset)
2679 {
2680 int cmd, set, rec, offset, clk_pulse;
2681 struct pcic_card_times *ctp;
2682
2683 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1))
2684 offset = 3;
2685 else
2686 offset = 0;
2687
2688 clk_pulse = mhztons(pcic->bus_speed);
2689 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++)
2690 ;
2691
2692 /*
2693 * Add (clk_pulse/2) and an extra 1 to account for rounding errors.
2694 */
2695 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1;
2696 if (set < 0)
2697 set = 0;
2698
2699 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1;
2700 if (cmd < 0)
2701 cmd = 0;
2702
2703 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2;
2704 if (rec < 0)
2705 rec = 0;
2706
2707 #if defined(PCIC_DEBUG)
2708 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n"
2709 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n",
2710 (unsigned)speed, offset == 3 ? 1 : 0,
2711 ctp->cycle, clk_pulse, cmd, set, rec);
2712 #endif
2713
2714 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd);
2715 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set);
2716 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec);
2717 }
2718
2719 /*
2720 * pcic_set_window
2721 * essentially the same as the Socket Services specification
2722 * We use socket and not adapter since they are identifiable
2723 * but the rest is the same
2724 *
2725 * dip pcic driver's device information
2726 * window parameters for the request
2727 */
2728 static int
2729 pcic_set_window(dev_info_t *dip, set_window_t *window)
2730 {
2731 anp_t *anp = ddi_get_driver_private(dip);
2732 pcicdev_t *pcic = anp->an_private;
2733 int select;
2734 int socket, pages, which, ret;
2735 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket];
2736 ra_return_t res;
2737 ndi_ra_request_t req;
2738 uint32_t base = window->base;
2739
2740 #if defined(PCIC_DEBUG)
2741 if (pcic_debug) {
2742 cmn_err(CE_CONT, "pcic_set_window: entered\n");
2743 cmn_err(CE_CONT,
2744 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n",
2745 window->window, window->socket, window->WindowSize,
2746 window->speed);
2747 cmn_err(CE_CONT,
2748 "\tbase=%x, state=%x\n", (unsigned)window->base,
2749 (unsigned)window->state);
2750 }
2751 #endif
2752
2753 /*
2754 * do some basic sanity checking on what we support
2755 * we don't do paged mode
2756 */
2757 if (window->state & WS_PAGED) {
2758 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n");
2759 return (BAD_ATTRIBUTE);
2760 }
2761
2762 /*
2763 * we don't care about previous mappings.
2764 * Card Services will deal with that so don't
2765 * even check
2766 */
2767
2768 socket = window->socket;
2769
2770 if (!(window->state & WS_IO)) {
2771 int win, tmp;
2772 pcs_memwin_t *memp;
2773 #if defined(PCIC_DEBUG)
2774 if (pcic_debug)
2775 cmn_err(CE_CONT, "\twindow type is memory\n");
2776 #endif
2777 /* this is memory window mapping */
2778 win = window->window % PCIC_NUMWINSOCK;
2779 tmp = window->window / PCIC_NUMWINSOCK;
2780
2781 /* only windows 2-6 can do memory mapping */
2782 if (tmp != window->socket || win < PCIC_IOWINDOWS) {
2783 cmn_err(CE_CONT,
2784 "\tattempt to map to non-mem window\n");
2785 return (BAD_WINDOW);
2786 }
2787
2788 if (window->WindowSize == 0)
2789 window->WindowSize = MEM_MIN;
2790 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) {
2791 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n");
2792 return (BAD_SIZE);
2793 }
2794
2795 mutex_enter(&pcic->pc_lock); /* protect the registers */
2796
2797 memp = &sockp->pcs_windows[win].mem;
2798 memp->pcw_speed = window->speed;
2799
2800 win -= PCIC_IOWINDOWS; /* put in right range */
2801
2802 if (window->WindowSize != memp->pcw_len)
2803 which = memp->pcw_len;
2804 else
2805 which = 0;
2806
2807 if (window->state & WS_ENABLED) {
2808 uint32_t wspeed;
2809 #if defined(PCIC_DEBUG)
2810 if (pcic_debug) {
2811 cmn_err(CE_CONT,
2812 "\tbase=%x, win=%d\n", (unsigned)base,
2813 win);
2814 if (which)
2815 cmn_err(CE_CONT,
2816 "\tneed to remap window\n");
2817 }
2818 #endif
2819
2820 if (which && (memp->pcw_status & PCW_MAPPED)) {
2821 ddi_regs_map_free(&memp->pcw_handle);
2822 res.ra_addr_lo = memp->pcw_base;
2823 res.ra_len = memp->pcw_len;
2824 (void) pcmcia_free_mem(memp->res_dip, &res);
2825 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED);
2826 memp->pcw_hostmem = NULL;
2827 memp->pcw_base = NULL;
2828 memp->pcw_len = 0;
2829 }
2830
2831 which = window->WindowSize >> PAGE_SHIFT;
2832
2833 if (!(memp->pcw_status & PCW_MAPPED)) {
2834 ret = 0;
2835
2836 memp->pcw_base = base;
2837 bzero(&req, sizeof (req));
2838 req.ra_len = which << PAGE_SHIFT;
2839 req.ra_addr = (uint64_t)memp->pcw_base;
2840 req.ra_boundbase = pcic->pc_base;
2841 req.ra_boundlen = pcic->pc_bound;
2842 req.ra_flags = (memp->pcw_base ?
2843 NDI_RA_ALLOC_SPECIFIED : 0) |
2844 NDI_RA_ALLOC_BOUNDED;
2845 req.ra_align_mask =
2846 (PAGESIZE - 1) | (PCIC_PAGE - 1);
2847 #if defined(PCIC_DEBUG)
2848 pcic_err(dip, 8,
2849 "\tlen 0x%"PRIx64
2850 "addr 0x%"PRIx64"bbase 0x%"PRIx64
2851 " blen 0x%"PRIx64" flags 0x%x"
2852 " algn 0x%"PRIx64"\n",
2853 req.ra_len, req.ra_addr,
2854 req.ra_boundbase,
2855 req.ra_boundlen, req.ra_flags,
2856 req.ra_align_mask);
2857 #endif
2858
2859 ret = pcmcia_alloc_mem(dip, &req, &res,
2860 &memp->res_dip);
2861 if (ret == DDI_FAILURE) {
2862 mutex_exit(&pcic->pc_lock);
2863 cmn_err(CE_WARN,
2864 "\tpcmcia_alloc_mem() failed\n");
2865 return (BAD_SIZE);
2866 }
2867 memp->pcw_base = res.ra_addr_lo;
2868 base = memp->pcw_base;
2869
2870 #if defined(PCIC_DEBUG)
2871 if (pcic_debug)
2872 cmn_err(CE_CONT,
2873 "\tsetwindow: new base=%x\n",
2874 (unsigned)memp->pcw_base);
2875 #endif
2876 memp->pcw_len = window->WindowSize;
2877
2878 which = pcmcia_map_reg(pcic->dip,
2879 window->child,
2880 &res,
2881 (uint32_t)(window->state &
2882 0xffff) |
2883 (window->socket << 16),
2884 (caddr_t *)&memp->pcw_hostmem,
2885 &memp->pcw_handle,
2886 &window->attr, NULL);
2887
2888 if (which != DDI_SUCCESS) {
2889
2890 cmn_err(CE_WARN, "\tpcmcia_map_reg() "
2891 "failed\n");
2892
2893 res.ra_addr_lo = memp->pcw_base;
2894 res.ra_len = memp->pcw_len;
2895 (void) pcmcia_free_mem(memp->res_dip,
2896 &res);
2897
2898 mutex_exit(&pcic->pc_lock);
2899
2900 return (BAD_WINDOW);
2901 }
2902 memp->pcw_status |= PCW_MAPPED;
2903 #if defined(PCIC_DEBUG)
2904 if (pcic_debug)
2905 cmn_err(CE_CONT,
2906 "\tmap=%x, hostmem=%p\n",
2907 which,
2908 (void *)memp->pcw_hostmem);
2909 #endif
2910 } else {
2911 base = memp->pcw_base;
2912 }
2913
2914 /* report the handle back to caller */
2915 window->handle = memp->pcw_handle;
2916
2917 #if defined(PCIC_DEBUG)
2918 if (pcic_debug) {
2919 cmn_err(CE_CONT,
2920 "\twindow mapped to %x@%x len=%d\n",
2921 (unsigned)window->base,
2922 (unsigned)memp->pcw_base,
2923 memp->pcw_len);
2924 }
2925 #endif
2926
2927 /* find the register set offset */
2928 select = win * PCIC_MEM_1_OFFSET;
2929 #if defined(PCIC_DEBUG)
2930 if (pcic_debug)
2931 cmn_err(CE_CONT, "\tselect=%x\n", select);
2932 #endif
2933
2934 /*
2935 * at this point, the register window indicator has
2936 * been converted to be an offset from the first
2937 * set of registers that are used for programming
2938 * the window mapping and the offset used to select
2939 * the correct set of registers to access the
2940 * specified socket. This allows basing everything
2941 * off the _0 window
2942 */
2943
2944 /* map the physical page base address */
2945 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0;
2946 which |= (window->speed <= MEM_SPEED_MIN) ?
2947 SYSMEM_ZERO_WAIT : 0;
2948
2949 /* need to select register set */
2950 select = PCIC_MEM_1_OFFSET * win;
2951
2952 pcic_putb(pcic, socket,
2953 PCIC_SYSMEM_0_STARTLOW + select,
2954 SYSMEM_LOW(base));
2955 pcic_putb(pcic, socket,
2956 PCIC_SYSMEM_0_STARTHI + select,
2957 SYSMEM_HIGH(base) | which);
2958
2959 /*
2960 * Some adapters can decode window addresses greater
2961 * than 16-bits worth, so handle them here.
2962 */
2963 switch (pcic->pc_type) {
2964 case PCIC_INTEL_i82092:
2965 pcic_putb(pcic, socket,
2966 PCIC_82092_CPAGE,
2967 SYSMEM_EXT(base));
2968 break;
2969 case PCIC_CL_PD6729:
2970 case PCIC_CL_PD6730:
2971 clext_reg_write(pcic, socket,
2972 PCIC_CLEXT_MMAP0_UA + win,
2973 SYSMEM_EXT(base));
2974 break;
2975 case PCIC_TI_PCI1130:
2976 /*
2977 * Note that the TI chip has one upper byte
2978 * per socket so all windows get bound to a
2979 * 16MB segment. This must be detected and
2980 * handled appropriately. We can detect that
2981 * it is done by seeing if the pc_base has
2982 * changed and changing when the register
2983 * is first set. This will force the bounds
2984 * to be correct.
2985 */
2986 if (pcic->pc_bound == 0xffffffff) {
2987 pcic_putb(pcic, socket,
2988 PCIC_TI_WINDOW_PAGE_PCI,
2989 SYSMEM_EXT(base));
2990 pcic->pc_base = SYSMEM_EXT(base) << 24;
2991 pcic->pc_bound = 0x1000000;
2992 }
2993 break;
2994 case PCIC_TI_PCI1031:
2995 case PCIC_TI_PCI1131:
2996 case PCIC_TI_PCI1250:
2997 case PCIC_TI_PCI1225:
2998 case PCIC_TI_PCI1221:
2999 case PCIC_SMC_34C90:
3000 case PCIC_CL_PD6832:
3001 case PCIC_RICOH_RL5C466:
3002 case PCIC_TI_PCI1410:
3003 case PCIC_ENE_1410:
3004 case PCIC_TI_PCI1510:
3005 case PCIC_TI_PCI1520:
3006 case PCIC_O2_OZ6912:
3007 case PCIC_TI_PCI1420:
3008 case PCIC_ENE_1420:
3009 case PCIC_TI_VENDOR:
3010 case PCIC_TOSHIBA_TOPIC100:
3011 case PCIC_TOSHIBA_TOPIC95:
3012 case PCIC_TOSHIBA_VENDOR:
3013 case PCIC_RICOH_VENDOR:
3014 case PCIC_O2MICRO_VENDOR:
3015 pcic_putb(pcic, socket,
3016 PCIC_YENTA_MEM_PAGE + win,
3017 SYSMEM_EXT(base));
3018 break;
3019 default:
3020 cmn_err(CE_NOTE, "pcic_set_window: unknown "
3021 "cardbus vendor:0x%X\n",
3022 pcic->pc_type);
3023 pcic_putb(pcic, socket,
3024 PCIC_YENTA_MEM_PAGE + win,
3025 SYSMEM_EXT(base));
3026
3027 break;
3028 } /* switch */
3029
3030 /*
3031 * specify the length of the mapped range
3032 * we convert to pages (rounding up) so that
3033 * the hardware gets the right thing
3034 */
3035 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE;
3036
3037 /*
3038 * Setup this window's timing.
3039 */
3040 switch (pcic->pc_type) {
3041 case PCIC_CL_PD6729:
3042 case PCIC_CL_PD6730:
3043 case PCIC_CL_PD6710:
3044 case PCIC_CL_PD6722:
3045 wspeed = SYSMEM_CLTIMER_SET_0;
3046 pcic_set_cdtimers(pcic, socket,
3047 window->speed,
3048 wspeed);
3049 break;
3050
3051 case PCIC_INTEL_i82092:
3052 default:
3053 wspeed = pcic_calc_speed(pcic, window->speed);
3054 break;
3055 } /* switch */
3056
3057 #if defined(PCIC_DEBUG)
3058 if (pcic_debug)
3059 cmn_err(CE_CONT,
3060 "\twindow %d speed bits = %x for "
3061 "%dns\n",
3062 win, (unsigned)wspeed, window->speed);
3063 #endif
3064
3065 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select,
3066 SYSMEM_LOW(base +
3067 (pages * PCIC_PAGE)-1));
3068
3069 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1);
3070 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select,
3071 wspeed);
3072
3073 /*
3074 * now map the card's memory pages - we start with page
3075 * 0
3076 * we also default to AM -- set page might change it
3077 */
3078 base = memp->pcw_base;
3079 pcic_putb(pcic, socket,
3080 PCIC_CARDMEM_0_LOW + select,
3081 CARDMEM_LOW(0 - (uint32_t)base));
3082
3083 pcic_putb(pcic, socket,
3084 PCIC_CARDMEM_0_HI + select,
3085 CARDMEM_HIGH(0 - (uint32_t)base) |
3086 CARDMEM_REG_ACTIVE);
3087
3088 /*
3089 * enable the window even though redundant
3090 * and SetPage may do it again.
3091 */
3092 select = pcic_getb(pcic, socket,
3093 PCIC_MAPPING_ENABLE);
3094 select |= SYSMEM_WINDOW(win);
3095 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select);
3096 memp->pcw_offset = 0;
3097 memp->pcw_status |= PCW_ENABLED;
3098 } else {
3099 /*
3100 * not only do we unmap the memory, the
3101 * window has been turned off.
3102 */
3103 if (which && memp->pcw_status & PCW_MAPPED) {
3104 ddi_regs_map_free(&memp->pcw_handle);
3105 res.ra_addr_lo = memp->pcw_base;
3106 res.ra_len = memp->pcw_len;
3107 (void) pcmcia_free_mem(memp->res_dip, &res);
3108 memp->pcw_hostmem = NULL;
3109 memp->pcw_status &= ~PCW_MAPPED;
3110 }
3111
3112 /* disable current mapping */
3113 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3114 select &= ~SYSMEM_WINDOW(win);
3115 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select);
3116 memp->pcw_status &= ~PCW_ENABLED;
3117 }
3118 memp->pcw_len = window->WindowSize;
3119 window->handle = memp->pcw_handle;
3120 #if defined(PCIC_DEBUG)
3121 if (pcic_debug)
3122 xxdmp_all_regs(pcic, window->socket, -1);
3123 #endif
3124 } else {
3125 /*
3126 * This is a request for an IO window
3127 */
3128 int win, tmp;
3129 pcs_iowin_t *winp;
3130 /* I/O windows */
3131 #if defined(PCIC_DEBUG)
3132 if (pcic_debug)
3133 cmn_err(CE_CONT, "\twindow type is I/O\n");
3134 #endif
3135
3136 /* only windows 0 and 1 can do I/O */
3137 win = window->window % PCIC_NUMWINSOCK;
3138 tmp = window->window / PCIC_NUMWINSOCK;
3139
3140 if (win >= PCIC_IOWINDOWS || tmp != window->socket) {
3141 cmn_err(CE_WARN,
3142 "\twindow is out of range (%d)\n",
3143 window->window);
3144 return (BAD_WINDOW);
3145 }
3146
3147 mutex_enter(&pcic->pc_lock); /* protect the registers */
3148
3149 winp = &sockp->pcs_windows[win].io;
3150 winp->pcw_speed = window->speed;
3151 if (window->WindowSize != 1 && window->WindowSize & 1) {
3152 /* we don't want an odd-size window */
3153 window->WindowSize++;
3154 }
3155 winp->pcw_len = window->WindowSize;
3156
3157 if (window->state & WS_ENABLED) {
3158 if (winp->pcw_status & PCW_MAPPED) {
3159 ddi_regs_map_free(&winp->pcw_handle);
3160 res.ra_addr_lo = winp->pcw_base;
3161 res.ra_len = winp->pcw_len;
3162 (void) pcmcia_free_io(winp->res_dip, &res);
3163 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED);
3164 }
3165
3166 /*
3167 * if the I/O address wasn't allocated, allocate
3168 * it now. If it was allocated, it better
3169 * be free to use.
3170 * The winp->pcw_offset value is set and used
3171 * later on if the particular adapter
3172 * that we're running on has the ability
3173 * to translate IO accesses to the card
3174 * (such as some adapters in the Cirrus
3175 * Logic family).
3176 */
3177 winp->pcw_offset = 0;
3178
3179 /*
3180 * Setup the request parameters for the
3181 * requested base and length. If
3182 * we're on an adapter that has
3183 * IO window offset registers, then
3184 * we don't need a specific base
3185 * address, just a length, and then
3186 * we'll cause the correct IO address
3187 * to be generated on the socket by
3188 * setting up the IO window offset
3189 * registers.
3190 * For adapters that support this capability, we
3191 * always use the IO window offset registers,
3192 * even if the passed base/length would be in
3193 * range.
3194 */
3195 base = window->base;
3196 bzero(&req, sizeof (req));
3197 req.ra_len = window->WindowSize;
3198
3199 req.ra_addr = (uint64_t)
3200 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base);
3201 req.ra_flags = (req.ra_addr) ?
3202 NDI_RA_ALLOC_SPECIFIED : 0;
3203
3204 req.ra_flags |= NDI_RA_ALIGN_SIZE;
3205 /* need to rethink this */
3206 req.ra_boundbase = pcic->pc_iobase;
3207 req.ra_boundlen = pcic->pc_iobound;
3208 req.ra_flags |= NDI_RA_ALLOC_BOUNDED;
3209
3210 #if defined(PCIC_DEBUG)
3211 pcic_err(dip, 8,
3212 "\tlen 0x%"PRIx64" addr 0x%"PRIx64
3213 "bbase 0x%"PRIx64
3214 "blen 0x%"PRIx64" flags 0x%x algn 0x%"
3215 PRIx64"\n",
3216 req.ra_len, (uint64_t)req.ra_addr,
3217 req.ra_boundbase,
3218 req.ra_boundlen, req.ra_flags,
3219 req.ra_align_mask);
3220 #endif
3221
3222 /*
3223 * Try to allocate the space. If we fail this,
3224 * return the appropriate error depending
3225 * on whether the caller specified a
3226 * specific base address or not.
3227 */
3228 if (pcmcia_alloc_io(dip, &req, &res,
3229 &winp->res_dip) == DDI_FAILURE) {
3230 winp->pcw_status &= ~PCW_ENABLED;
3231 mutex_exit(&pcic->pc_lock);
3232 cmn_err(CE_WARN, "Failed to alloc I/O:\n"
3233 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64
3234 "bbase 0x%" PRIx64
3235 "blen 0x%" PRIx64 "flags 0x%x"
3236 "algn 0x%" PRIx64 "\n",
3237 req.ra_len, req.ra_addr,
3238 req.ra_boundbase,
3239 req.ra_boundlen, req.ra_flags,
3240 req.ra_align_mask);
3241
3242 return (base?BAD_BASE:BAD_SIZE);
3243 } /* pcmcia_alloc_io */
3244
3245 /*
3246 * Don't change the original base. Either we use
3247 * the offset registers below (PCF_IO_REMAP is set)
3248 * or it was allocated correctly anyway.
3249 */
3250 winp->pcw_base = res.ra_addr_lo;
3251
3252 #if defined(PCIC_DEBUG)
3253 pcic_err(dip, 8,
3254 "\tsetwindow: new base=%x orig base 0x%x\n",
3255 (unsigned)winp->pcw_base, base);
3256 #endif
3257
3258 if ((which = pcmcia_map_reg(pcic->dip,
3259 window->child,
3260 &res,
3261 (uint32_t)(window->state &
3262 0xffff) |
3263 (window->socket << 16),
3264 (caddr_t *)&winp->pcw_hostmem,
3265 &winp->pcw_handle,
3266 &window->attr,
3267 base)) != DDI_SUCCESS) {
3268
3269 cmn_err(CE_WARN, "pcmcia_map_reg()"
3270 "failed\n");
3271
3272 res.ra_addr_lo = winp->pcw_base;
3273 res.ra_len = winp->pcw_len;
3274 (void) pcmcia_free_io(winp->res_dip,
3275 &res);
3276
3277 mutex_exit(&pcic->pc_lock);
3278 return (BAD_WINDOW);
3279 }
3280
3281 window->handle = winp->pcw_handle;
3282 winp->pcw_status |= PCW_MAPPED;
3283
3284 /* find the register set offset */
3285 select = win * PCIC_IO_OFFSET;
3286
3287 #if defined(PCIC_DEBUG)
3288 if (pcic_debug) {
3289 cmn_err(CE_CONT,
3290 "\tenable: window=%d, select=%x, "
3291 "base=%x, handle=%p\n",
3292 win, select,
3293 (unsigned)window->base,
3294 (void *)window->handle);
3295 }
3296 #endif
3297 /*
3298 * at this point, the register window indicator has
3299 * been converted to be an offset from the first
3300 * set of registers that are used for programming
3301 * the window mapping and the offset used to select
3302 * the correct set of registers to access the
3303 * specified socket. This allows basing everything
3304 * off the _0 window
3305 */
3306
3307 /* map the I/O base in */
3308 pcic_putb(pcic, socket,
3309 PCIC_IO_ADDR_0_STARTLOW + select,
3310 LOW_BYTE((uint32_t)winp->pcw_base));
3311 pcic_putb(pcic, socket,
3312 PCIC_IO_ADDR_0_STARTHI + select,
3313 HIGH_BYTE((uint32_t)winp->pcw_base));
3314
3315 pcic_putb(pcic, socket,
3316 PCIC_IO_ADDR_0_STOPLOW + select,
3317 LOW_BYTE((uint32_t)winp->pcw_base +
3318 window->WindowSize - 1));
3319 pcic_putb(pcic, socket,
3320 PCIC_IO_ADDR_0_STOPHI + select,
3321 HIGH_BYTE((uint32_t)winp->pcw_base +
3322 window->WindowSize - 1));
3323
3324 /*
3325 * We've got the requested IO space, now see if we
3326 * need to adjust the IO window offset registers
3327 * so that the correct IO address is generated
3328 * at the socket. If this window doesn't have
3329 * this capability, then we're all done setting
3330 * up the IO resources.
3331 */
3332 if (pcic->pc_flags & PCF_IO_REMAP) {
3333
3334
3335 /*
3336 * Note that only 16 bits are used to program
3337 * the registers but leave 32 bits on pcw_offset
3338 * so that we can generate the original base
3339 * in get_window()
3340 */
3341 winp->pcw_offset = (base - winp->pcw_base);
3342
3343 pcic_putb(pcic, socket,
3344 PCIC_IO_OFFSET_LOW +
3345 (win * PCIC_IO_OFFSET_OFFSET),
3346 winp->pcw_offset & 0x0ff);
3347 pcic_putb(pcic, socket,
3348 PCIC_IO_OFFSET_HI +
3349 (win * PCIC_IO_OFFSET_OFFSET),
3350 (winp->pcw_offset >> 8) & 0x0ff);
3351
3352 } /* PCF_IO_REMAP */
3353
3354 /* now get the other details (size, etc) right */
3355
3356 /*
3357 * Set the data size control bits here. Most of the
3358 * adapters will ignore IOMEM_16BIT when
3359 * IOMEM_IOCS16 is set, except for the Intel
3360 * 82092, which only pays attention to the
3361 * IOMEM_16BIT bit. Sigh... Intel can't even
3362 * make a proper clone of their own chip.
3363 * The 82092 also apparently can't set the timing
3364 * of I/O windows.
3365 */
3366 which = (window->state & WS_16BIT) ?
3367 (IOMEM_16BIT | IOMEM_IOCS16) : 0;
3368
3369 switch (pcic->pc_type) {
3370 case PCIC_CL_PD6729:
3371 case PCIC_CL_PD6730:
3372 case PCIC_CL_PD6710:
3373 case PCIC_CL_PD6722:
3374 case PCIC_CL_PD6832:
3375 /*
3376 * Select Timer Set 1 - this will take
3377 * effect when the PCIC_IO_CONTROL
3378 * register is written to later on;
3379 * the call to pcic_set_cdtimers
3380 * just sets up the timer itself.
3381 */
3382 which |= IOMEM_CLTIMER_SET_1;
3383 pcic_set_cdtimers(pcic, socket,
3384 window->speed,
3385 IOMEM_CLTIMER_SET_1);
3386 which |= IOMEM_IOCS16;
3387 break;
3388 case PCIC_TI_PCI1031:
3389
3390 if (window->state & WS_16BIT)
3391 which |= IOMEM_WAIT16;
3392
3393 break;
3394 case PCIC_TI_PCI1130:
3395
3396 if (window->state & WS_16BIT)
3397 which |= IOMEM_WAIT16;
3398
3399 break;
3400 case PCIC_INTEL_i82092:
3401 break;
3402 default:
3403 if (window->speed >
3404 mhztons(pcic->bus_speed) * 3)
3405 which |= IOMEM_WAIT16;
3406 #ifdef notdef
3407 if (window->speed <
3408 mhztons(pcic->bus_speed) * 6)
3409 which |= IOMEM_ZERO_WAIT;
3410 #endif
3411 break;
3412 } /* switch (pc_type) */
3413
3414 /*
3415 * Setup the data width and timing
3416 */
3417 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL);
3418 select &= ~(PCIC_IO_WIN_MASK << (win * 4));
3419 select |= IOMEM_SETWIN(win, which);
3420 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select);
3421
3422 /*
3423 * Enable the IO window
3424 */
3425 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3426 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE,
3427 select | IOMEM_WINDOW(win));
3428
3429 winp->pcw_status |= PCW_ENABLED;
3430
3431 #if defined(PCIC_DEBUG)
3432 if (pcic_debug) {
3433 cmn_err(CE_CONT,
3434 "\twhich = %x, select = %x (%x)\n",
3435 which, select,
3436 IOMEM_SETWIN(win, which));
3437 xxdmp_all_regs(pcic, window->socket * 0x40, 24);
3438 }
3439 #endif
3440 } else {
3441 /*
3442 * not only do we unmap the IO space, the
3443 * window has been turned off.
3444 */
3445 if (winp->pcw_status & PCW_MAPPED) {
3446 ddi_regs_map_free(&winp->pcw_handle);
3447 res.ra_addr_lo = winp->pcw_base;
3448 res.ra_len = winp->pcw_len;
3449 (void) pcmcia_free_io(winp->res_dip, &res);
3450 winp->pcw_status &= ~PCW_MAPPED;
3451 }
3452
3453 /* disable current mapping */
3454 select = pcic_getb(pcic, socket,
3455 PCIC_MAPPING_ENABLE);
3456 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE,
3457 select &= ~IOMEM_WINDOW(win));
3458 winp->pcw_status &= ~PCW_ENABLED;
3459
3460 winp->pcw_base = 0;
3461 winp->pcw_len = 0;
3462 winp->pcw_offset = 0;
3463 window->base = 0;
3464 /* now make sure we don't accidentally re-enable */
3465 /* find the register set offset */
3466 select = win * PCIC_IO_OFFSET;
3467 pcic_putb(pcic, socket,
3468 PCIC_IO_ADDR_0_STARTLOW + select, 0);
3469 pcic_putb(pcic, socket,
3470 PCIC_IO_ADDR_0_STARTHI + select, 0);
3471 pcic_putb(pcic, socket,
3472 PCIC_IO_ADDR_0_STOPLOW + select, 0);
3473 pcic_putb(pcic, socket,
3474 PCIC_IO_ADDR_0_STOPHI + select, 0);
3475 }
3476 }
3477 mutex_exit(&pcic->pc_lock);
3478
3479 return (SUCCESS);
3480 }
3481
3482 /*
3483 * pcic_card_state()
3484 * compute the instantaneous Card State information
3485 */
3486 static int
3487 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp)
3488 {
3489 int value, result;
3490 #if defined(PCIC_DEBUG)
3491 int orig_value;
3492 #endif
3493
3494 mutex_enter(&pcic->pc_lock); /* protect the registers */
3495
3496 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS);
3497
3498 #if defined(PCIC_DEBUG)
3499 orig_value = value;
3500 if (pcic_debug >= 8)
3501 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n",
3502 (void *)sockp,
3503 value,
3504 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI",
3505 sockp->pcs_socket);
3506 #endif
3507 /*
3508 * Lie to socket services if we are not ready.
3509 * This is when we are starting up or during debounce timeouts
3510 * or if the card is a cardbus card.
3511 */
3512 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) &&
3513 !sockp->pcs_debounce_id &&
3514 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) {
3515 result = SBM_CD;
3516
3517 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON))
3518 result |= SBM_WP;
3519 if (value & PCIC_POWER_ON) {
3520 if (value & PCIC_READY)
3521 result |= SBM_RDYBSY;
3522 value = (~value) & (PCIC_BVD1 | PCIC_BVD2);
3523 if (value & PCIC_BVD1)
3524 result |= SBM_BVD1;
3525 if (value & PCIC_BVD2)
3526 result |= SBM_BVD2;
3527 }
3528 } else
3529 result = 0;
3530
3531 mutex_exit(&pcic->pc_lock);
3532
3533 #if defined(PCIC_DEBUG)
3534 pcic_err(pcic->dip, 8,
3535 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n",
3536 (void *) sockp, orig_value,
3537 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI",
3538 sockp->pcs_socket, result);
3539 #endif
3540
3541 return (result);
3542 }
3543
3544 /*
3545 * pcic_set_page()
3546 * SocketServices SetPage function
3547 * set the page of PC Card memory that should be in the mapped
3548 * window
3549 */
3550 /*ARGSUSED*/
3551 static int
3552 pcic_set_page(dev_info_t *dip, set_page_t *page)
3553 {
3554 anp_t *anp = ddi_get_driver_private(dip);
3555 pcicdev_t *pcic = anp->an_private;
3556 int select;
3557 int which, socket, window;
3558 uint32_t base;
3559 pcs_memwin_t *memp;
3560
3561 /* get real socket/window numbers */
3562 window = page->window % PCIC_NUMWINSOCK;
3563 socket = page->window / PCIC_NUMWINSOCK;
3564
3565 #if defined(PCIC_DEBUG)
3566 if (pcic_debug) {
3567 cmn_err(CE_CONT,
3568 "pcic_set_page: window=%d, socket=%d, page=%d\n",
3569 window, socket, page->page);
3570 }
3571 #endif
3572 /* only windows 2-6 work on memory */
3573 if (window < PCIC_IOWINDOWS)
3574 return (BAD_WINDOW);
3575
3576 /* only one page supported (but any size) */
3577 if (page->page != 0)
3578 return (BAD_PAGE);
3579
3580 mutex_enter(&pcic->pc_lock); /* protect the registers */
3581
3582 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem;
3583 window -= PCIC_IOWINDOWS;
3584
3585 #if defined(PCIC_DEBUG)
3586 if (pcic_debug)
3587 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n",
3588 (uint32_t)memp->pcw_base,
3589 (void *)memp->pcw_hostmem, memp->pcw_len);
3590 #endif
3591
3592 /* window must be enabled */
3593 if (!(memp->pcw_status & PCW_ENABLED))
3594 return (BAD_ATTRIBUTE);
3595
3596 /* find the register set offset */
3597 select = window * PCIC_MEM_1_OFFSET;
3598 #if defined(PCIC_DEBUG)
3599 if (pcic_debug)
3600 cmn_err(CE_CONT, "\tselect=%x\n", select);
3601 #endif
3602
3603 /*
3604 * now map the card's memory pages - we start with page 0
3605 */
3606
3607 which = 0; /* assume simple case */
3608 if (page->state & PS_ATTRIBUTE) {
3609 which |= CARDMEM_REG_ACTIVE;
3610 memp->pcw_status |= PCW_ATTRIBUTE;
3611 } else {
3612 memp->pcw_status &= ~PCW_ATTRIBUTE;
3613 }
3614
3615 /*
3616 * if caller says Write Protect, enforce it.
3617 */
3618 if (page->state & PS_WP) {
3619 which |= CARDMEM_WRITE_PROTECT;
3620 memp->pcw_status |= PCW_WP;
3621 } else {
3622 memp->pcw_status &= ~PCW_WP;
3623 }
3624 #if defined(PCIC_DEBUG)
3625 if (pcic_debug) {
3626 cmn_err(CE_CONT, "\tmemory type = %s\n",
3627 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common");
3628 if (which & CARDMEM_WRITE_PROTECT)
3629 cmn_err(CE_CONT, "\twrite protect\n");
3630 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n",
3631 (unsigned)page->offset,
3632 (unsigned)memp->pcw_base,
3633 (int)page->offset - (int)memp->pcw_base & 0xffffff);
3634 }
3635 #endif
3636 /* address computation based on 64MB range and not larger */
3637 base = (uint32_t)memp->pcw_base & 0x3ffffff;
3638 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select,
3639 CARDMEM_LOW((int)page->offset - (int)base));
3640 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select);
3641 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select,
3642 CARDMEM_HIGH((int)page->offset - base) | which);
3643 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select);
3644
3645 /*
3646 * while not really necessary, this just makes sure
3647 * nothing turned the window off behind our backs
3648 */
3649 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3650 which |= SYSMEM_WINDOW(window);
3651 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which);
3652 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
3653
3654 memp->pcw_offset = (off_t)page->offset;
3655
3656 #if defined(PCIC_DEBUG)
3657 if (pcic_debug) {
3658 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n",
3659 (void *)memp->pcw_hostmem,
3660 (uint32_t)*memp->pcw_hostmem);
3661
3662 xxdmp_all_regs(pcic, socket, -1);
3663
3664 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n",
3665 (void *)memp->pcw_hostmem,
3666 (uint32_t)*memp->pcw_hostmem);
3667 }
3668 #endif
3669
3670 if (which & PCW_ATTRIBUTE)
3671 pcic_mswait(pcic, socket, 2);
3672
3673 mutex_exit(&pcic->pc_lock);
3674
3675 return (SUCCESS);
3676 }
3677
3678 /*
3679 * pcic_set_vcc_level()
3680 *
3681 * set voltage based on adapter information
3682 *
3683 * this routine implements a limited solution for support of 3.3v cards.
3684 * the general solution, which would fully support the pcmcia spec
3685 * as far as allowing client drivers to request which voltage levels
3686 * to be set, requires more framework support and driver changes - ess
3687 */
3688 static int
3689 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket)
3690 {
3691 uint32_t socket_present_state;
3692
3693 #if defined(PCIC_DEBUG)
3694 if (pcic_debug) {
3695 cmn_err(CE_CONT,
3696 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n",
3697 (void *)pcic, socket->VccLevel);
3698 }
3699 #endif
3700
3701 /*
3702 * check VccLevel
3703 * if this is zero, power is being turned off
3704 * if it is non-zero, power is being turned on.
3705 */
3706 if (socket->VccLevel == 0) {
3707 return (0);
3708 }
3709
3710 /*
3711 * range checking for sanity's sake
3712 */
3713 if (socket->VccLevel >= pcic->pc_numpower) {
3714 return (BAD_VCC);
3715 }
3716
3717 switch (pcic->pc_io_type) {
3718 /*
3719 * Yenta-compliant adapters have vcc info in the extended registers
3720 * Other adapters can be added as needed, but the 'default' case
3721 * has been left as it was previously so as not to break existing
3722 * adapters.
3723 */
3724 case PCIC_IO_TYPE_YENTA:
3725 /*
3726 * Here we ignore the VccLevel passed in and read the
3727 * card type from the adapter socket present state register
3728 */
3729 socket_present_state =
3730 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr +
3731 PCIC_PRESENT_STATE_REG));
3732 #if defined(PCIC_DEBUG)
3733 if (pcic_debug) {
3734 cmn_err(CE_CONT,
3735 "socket present state = 0x%x\n",
3736 socket_present_state);
3737 }
3738 #endif
3739 switch (socket_present_state & PCIC_VCC_MASK) {
3740 case PCIC_VCC_3VCARD:
3741 /* fall through */
3742 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD:
3743 socket->VccLevel = PCIC_VCC_3VLEVEL;
3744 return
3745 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE);
3746 case PCIC_VCC_5VCARD:
3747 socket->VccLevel = PCIC_VCC_5VLEVEL;
3748 return
3749 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE);
3750 default:
3751 /*
3752 * if no card is present, this can be the
3753 * case of a client making a SetSocket call
3754 * after card removal. In this case we return
3755 * the current power level
3756 */
3757 return ((unsigned)ddi_get8(pcic->handle,
3758 pcic->ioaddr + CB_R2_OFFSET +
3759 PCIC_POWER_CONTROL));
3760 }
3761
3762 default:
3763
3764 switch (socket->VccLevel) {
3765 case PCIC_VCC_3VLEVEL:
3766 return (BAD_VCC);
3767 case PCIC_VCC_5VLEVEL:
3768 /* enable Vcc */
3769 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE);
3770 default:
3771 return (BAD_VCC);
3772 }
3773 }
3774 }
3775
3776
3777 /*
3778 * pcic_set_socket()
3779 * Socket Services SetSocket call
3780 * sets basic socket configuration
3781 */
3782 static int
3783 pcic_set_socket(dev_info_t *dip, set_socket_t *socket)
3784 {
3785 anp_t *anp = ddi_get_driver_private(dip);
3786 pcicdev_t *pcic = anp->an_private;
3787 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket];
3788 int irq, interrupt, mirq;
3789 int powerlevel = 0;
3790 int ind, value, orig_pwrctl;
3791
3792 #if defined(PCIC_DEBUG)
3793 if (pcic_debug) {
3794 cmn_err(CE_CONT,
3795 "pcic_set_socket(dip=%p, socket=%d)"
3796 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip,
3797 socket->socket, socket->VccLevel, socket->Vpp1Level,
3798 socket->Vpp2Level);
3799 }
3800 #endif
3801 /*
3802 * check VccLevel, etc. before setting mutex
3803 * if this is zero, power is being turned off
3804 * if it is non-zero, power is being turned on.
3805 * the default case is to assume Vcc only.
3806 */
3807
3808 /* this appears to be very implementation specific */
3809
3810 if (socket->Vpp1Level != socket->Vpp2Level)
3811 return (BAD_VPP);
3812
3813 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) {
3814 powerlevel = 0;
3815 sockp->pcs_vcc = 0;
3816 sockp->pcs_vpp1 = 0;
3817 sockp->pcs_vpp2 = 0;
3818 } else {
3819 #if defined(PCIC_DEBUG)
3820 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n",
3821 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level);
3822 #endif
3823 /* valid Vcc power level? */
3824 if (socket->VccLevel >= pcic->pc_numpower)
3825 return (BAD_VCC);
3826
3827 switch (pcic_power[socket->VccLevel].PowerLevel) {
3828 case 33: /* 3.3V */
3829 case 60: /* for bad CIS in Option GPRS card */
3830 if (!(pcic->pc_flags & PCF_33VCAP)) {
3831 cmn_err(CE_WARN,
3832 "%s%d: Bad Request for 3.3V "
3833 "(Controller incapable)\n",
3834 ddi_get_name(pcic->dip),
3835 ddi_get_instance(pcic->dip));
3836 return (BAD_VCC);
3837 }
3838 /* FALLTHROUGH */
3839 case 50: /* 5V */
3840 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) &&
3841 pcic_getcb(pcic, CB_PRESENT_STATE) &
3842 CB_PS_33VCARD) {
3843 /*
3844 * This is actually a 3.3V card.
3845 * Solaris Card Services
3846 * doesn't understand 3.3V
3847 * so we cheat and change
3848 * the setting to the one appropriate to 3.3V.
3849 * Note that this is the entry number
3850 * in the pcic_power[] array.
3851 */
3852 sockp->pcs_vcc = PCIC_VCC_3VLEVEL;
3853 } else
3854 sockp->pcs_vcc = socket->VccLevel;
3855 break;
3856 default:
3857 return (BAD_VCC);
3858 }
3859
3860 /* enable Vcc */
3861 powerlevel = POWER_CARD_ENABLE;
3862
3863 #if defined(PCIC_DEBUG)
3864 if (pcic_debug) {
3865 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n",
3866 socket->VccLevel, powerlevel);
3867 }
3868 #endif
3869 ind = 0; /* default index to 0 power */
3870 if ((int)socket->Vpp1Level >= 0 &&
3871 socket->Vpp1Level < pcic->pc_numpower) {
3872 if (!(pcic_power[socket->Vpp1Level].ValidSignals
3873 & VPP1)) {
3874 return (BAD_VPP);
3875 }
3876 ind = pcic_power[socket->Vpp1Level].PowerLevel/10;
3877 powerlevel |= pcic_vpp_levels[ind];
3878 sockp->pcs_vpp1 = socket->Vpp1Level;
3879 }
3880 if ((int)socket->Vpp2Level >= 0 &&
3881 socket->Vpp2Level < pcic->pc_numpower) {
3882 if (!(pcic_power[socket->Vpp2Level].ValidSignals
3883 & VPP2)) {
3884 return (BAD_VPP);
3885 }
3886 ind = pcic_power[socket->Vpp2Level].PowerLevel/10;
3887 powerlevel |= (pcic_vpp_levels[ind] << 2);
3888 sockp->pcs_vpp2 = socket->Vpp2Level;
3889 }
3890
3891 if (pcic->pc_flags & PCF_VPPX) {
3892 /*
3893 * this adapter doesn't allow separate Vpp1/Vpp2
3894 * if one is turned on, both are turned on and only
3895 * the Vpp1 bits should be set
3896 */
3897 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) {
3898 /* must be the same if one not zero */
3899 if (sockp->pcs_vpp1 != 0 &&
3900 sockp->pcs_vpp2 != 0) {
3901 cmn_err(CE_WARN,
3902 "%s%d: Bad Power Request "
3903 "(Vpp1/2 not the same)\n",
3904 ddi_get_name(pcic->dip),
3905 ddi_get_instance(pcic->dip));
3906 return (BAD_VPP);
3907 }
3908 }
3909 powerlevel &= ~(3<<2);
3910 }
3911
3912 #if defined(PCIC_DEBUG)
3913 if (pcic_debug) {
3914 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n",
3915 powerlevel, ind);
3916 }
3917 #endif
3918 }
3919 mutex_enter(&pcic->pc_lock); /* protect the registers */
3920
3921 /* turn socket->IREQRouting off while programming */
3922 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT);
3923 interrupt &= ~PCIC_INTR_MASK;
3924 if (pcic->pc_flags & PCF_USE_SMI)
3925 interrupt |= PCIC_INTR_ENABLE;
3926 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt);
3927
3928 switch (pcic->pc_type) {
3929 case PCIC_INTEL_i82092:
3930 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ,
3931 PCIC_82092_INT_DISABLE);
3932 break;
3933 default:
3934 break;
3935 } /* switch */
3936
3937 /* the SCIntMask specifies events to detect */
3938 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT);
3939
3940 #if defined(PCIC_DEBUG)
3941 if (pcic_debug)
3942 cmn_err(CE_CONT,
3943 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n",
3944 socket->SCIntMask, interrupt, mirq);
3945 #endif
3946 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT);
3947 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT,
3948 mirq & ~PCIC_CHANGE_MASK);
3949
3950 /* save the mask we want to use */
3951 sockp->pcs_intmask = socket->SCIntMask;
3952
3953 /*
3954 * Until there is a card present it's not worth enabling
3955 * any interrupts except "Card detect". This is done
3956 * elsewhere in the driver so don't change things if
3957 * there is no card!
3958 */
3959 if (sockp->pcs_flags & PCS_CARD_PRESENT) {
3960
3961 /* now update the hardware to reflect events desired */
3962 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO)
3963 mirq |= PCIC_BD_DETECT;
3964
3965 if (sockp->pcs_intmask & SBM_BVD2)
3966 mirq |= PCIC_BW_DETECT;
3967
3968 if (sockp->pcs_intmask & SBM_RDYBSY)
3969 mirq |= PCIC_RD_DETECT;
3970
3971 if (sockp->pcs_intmask & SBM_CD)
3972 mirq |= PCIC_CD_DETECT;
3973 }
3974
3975 if (sockp->pcs_flags & PCS_READY) {
3976 /*
3977 * card just came ready.
3978 * make sure enough time elapses
3979 * before touching it.
3980 */
3981 sockp->pcs_flags &= ~PCS_READY;
3982 pcic_mswait(pcic, socket->socket, 10);
3983 }
3984
3985 #if defined(PCIC_DEBUG)
3986 if (pcic_debug) {
3987 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq);
3988 }
3989 #endif
3990
3991 switch (pcic->pc_type) {
3992 case PCIC_I82365SL:
3993 case PCIC_VADEM:
3994 case PCIC_VADEM_VG469:
3995 /*
3996 * The Intel version has different options. This is a
3997 * special case of GPI which might be used for eject
3998 */
3999
4000 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT);
4001 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) &&
4002 pcic->pc_flags & PCF_GPI_EJECT) {
4003 irq |= PCIC_GPI_ENABLE;
4004 } else {
4005 irq &= ~PCIC_GPI_ENABLE;
4006 }
4007 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq);
4008 break;
4009 case PCIC_CL_PD6710:
4010 case PCIC_CL_PD6722:
4011 if (socket->IFType == IF_IO) {
4012 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0);
4013 value = pcic_getb(pcic, socket->socket,
4014 PCIC_MISC_CTL_1);
4015 if (pcic->pc_flags & PCF_AUDIO)
4016 value |= PCIC_MC_SPEAKER_ENB;
4017 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1,
4018 value);
4019 } else {
4020 value = pcic_getb(pcic, socket->socket,
4021 PCIC_MISC_CTL_1);
4022 value &= ~PCIC_MC_SPEAKER_ENB;
4023 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1,
4024 value);
4025 }
4026 break;
4027 case PCIC_CL_PD6729:
4028 case PCIC_CL_PD6730:
4029 case PCIC_CL_PD6832:
4030 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1);
4031 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) {
4032 value |= PCIC_MC_SPEAKER_ENB;
4033 } else {
4034 value &= ~PCIC_MC_SPEAKER_ENB;
4035 }
4036
4037 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33)
4038 value |= PCIC_MC_3VCC;
4039 else
4040 value &= ~PCIC_MC_3VCC;
4041
4042 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value);
4043 break;
4044
4045 case PCIC_O2_OZ6912:
4046 value = pcic_getcb(pcic, CB_MISCCTRL);
4047 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO))
4048 value |= (1<<25);
4049 else
4050 value &= ~(1<<25);
4051 pcic_putcb(pcic, CB_MISCCTRL, value);
4052 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33)
4053 powerlevel |= 0x08;
4054 break;
4055
4056 case PCIC_TI_PCI1250:
4057 case PCIC_TI_PCI1221:
4058 case PCIC_TI_PCI1225:
4059 case PCIC_TI_PCI1410:
4060 case PCIC_ENE_1410:
4061 case PCIC_TI_PCI1510:
4062 case PCIC_TI_PCI1520:
4063 case PCIC_TI_PCI1420:
4064 case PCIC_ENE_1420:
4065 value = ddi_get8(pcic->cfg_handle,
4066 pcic->cfgaddr + PCIC_CRDCTL_REG);
4067 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) {
4068 value |= PCIC_CRDCTL_SPKR_ENBL;
4069 } else {
4070 value &= ~PCIC_CRDCTL_SPKR_ENBL;
4071 }
4072 ddi_put8(pcic->cfg_handle,
4073 pcic->cfgaddr + PCIC_CRDCTL_REG, value);
4074 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33)
4075 powerlevel |= 0x08;
4076 break;
4077 }
4078
4079 /*
4080 * ctlind processing -- we can ignore this
4081 * there aren't any outputs on the chip for this and
4082 * the GUI will display what it thinks is correct
4083 */
4084
4085 /*
4086 * If outputs are enabled and the power is going off
4087 * turn off outputs first.
4088 */
4089
4090 /* power setup -- if necessary */
4091 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL);
4092 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) {
4093 orig_pwrctl &= ~POWER_OUTPUT_ENABLE;
4094 pcic_putb(pcic, socket->socket,
4095 PCIC_POWER_CONTROL, orig_pwrctl);
4096 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL);
4097 }
4098
4099 if (pcic->pc_flags & PCF_CBPWRCTL) {
4100 value = pcic_cbus_powerctl(pcic, socket->socket);
4101 powerlevel = 0;
4102 } else
4103 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel);
4104
4105 if (value != SUCCESS) {
4106 mutex_exit(&pcic->pc_lock);
4107 return (value);
4108 }
4109
4110 /*
4111 * If outputs were disabled and the power is going on
4112 * turn on outputs afterwards.
4113 */
4114 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) {
4115 orig_pwrctl = pcic_getb(pcic, socket->socket,
4116 PCIC_POWER_CONTROL);
4117 orig_pwrctl |= POWER_OUTPUT_ENABLE;
4118 pcic_putb(pcic, socket->socket,
4119 PCIC_POWER_CONTROL, orig_pwrctl);
4120 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL);
4121 }
4122
4123 /*
4124 * Once we have done the power stuff can re-enable management
4125 * interrupts.
4126 */
4127 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq);
4128
4129 #if defined(PCIC_DEBUG)
4130 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x "
4131 "cbctl 0x%x\n",
4132 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL),
4133 pcic_getcb(pcic, CB_CONTROL));
4134 #endif
4135
4136 /* irq processing */
4137 if (socket->IFType == IF_IO) {
4138 /* IRQ only for I/O */
4139 irq = socket->IREQRouting & PCIC_INTR_MASK;
4140 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT);
4141 value &= ~PCIC_INTR_MASK;
4142
4143 /* to enable I/O operation */
4144 value |= PCIC_IO_CARD | PCIC_RESET;
4145 sockp->pcs_flags |= PCS_CARD_IO;
4146 if (irq != sockp->pcs_irq) {
4147 if (sockp->pcs_irq != 0)
4148 cmn_err(CE_CONT,
4149 "SetSocket: IRQ mismatch %x != %x!\n",
4150 irq, sockp->pcs_irq);
4151 else
4152 sockp->pcs_irq = irq;
4153 }
4154 irq = sockp->pcs_irq;
4155
4156 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value);
4157 if (socket->IREQRouting & IRQ_ENABLE) {
4158 pcic_enable_io_intr(pcic, socket->socket, irq);
4159 sockp->pcs_flags |= PCS_IRQ_ENABLED;
4160 } else {
4161 pcic_disable_io_intr(pcic, socket->socket);
4162 sockp->pcs_flags &= ~PCS_IRQ_ENABLED;
4163 }
4164 #if defined(PCIC_DEBUG)
4165 if (pcic_debug) {
4166 cmn_err(CE_CONT,
4167 "\tsocket type is I/O and irq %x is %s\n", irq,
4168 (socket->IREQRouting & IRQ_ENABLE) ?
4169 "enabled" : "not enabled");
4170 xxdmp_all_regs(pcic, socket->socket, 20);
4171 }
4172 #endif
4173 } else {
4174 /* make sure I/O mode is off */
4175
4176 sockp->pcs_irq = 0;
4177
4178 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT);
4179 value &= ~PCIC_IO_CARD;
4180 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value);
4181 pcic_disable_io_intr(pcic, socket->socket);
4182 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED);
4183 }
4184
4185 sockp->pcs_state &= ~socket->State;
4186
4187 mutex_exit(&pcic->pc_lock);
4188 return (SUCCESS);
4189 }
4190
4191 /*
4192 * pcic_inquire_socket()
4193 * SocketServices InquireSocket function
4194 * returns basic characteristics of the socket
4195 */
4196 /*ARGSUSED*/
4197 static int
4198 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket)
4199 {
4200 anp_t *anp = ddi_get_driver_private(dip);
4201 pcicdev_t *pcic = anp->an_private;
4202 int value;
4203
4204 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS;
4205 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS;
4206 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS;
4207 value = pcic->pc_sockets[socket->socket].pcs_flags;
4208 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY;
4209 socket->ActiveHigh = 0;
4210 /* these are the usable IRQs */
4211 socket->ActiveLow = 0xfff0;
4212 return (SUCCESS);
4213 }
4214
4215 /*
4216 * pcic_inquire_window()
4217 * SocketServices InquireWindow function
4218 * returns detailed characteristics of the window
4219 * this is where windows get tied to sockets
4220 */
4221 /*ARGSUSED*/
4222 static int
4223 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window)
4224 {
4225 int type, socket;
4226
4227 type = window->window % PCIC_NUMWINSOCK;
4228 socket = window->window / PCIC_NUMWINSOCK;
4229
4230 #if defined(PCIC_DEBUG)
4231 if (pcic_debug >= 8)
4232 cmn_err(CE_CONT,
4233 "pcic_inquire_window: window = %d/%d socket=%d\n",
4234 window->window, type, socket);
4235 #endif
4236 if (type < PCIC_IOWINDOWS) {
4237 window->WndCaps = WC_IO|WC_WAIT;
4238 type = IF_IO;
4239 } else {
4240 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT;
4241 type = IF_MEMORY;
4242 }
4243
4244 /* initialize the socket map - one socket per window */
4245 PR_ZERO(window->Sockets);
4246 PR_SET(window->Sockets, socket);
4247
4248 if (type == IF_IO) {
4249 iowin_char_t *io;
4250 io = &window->iowin_char;
4251 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT|
4252 WC_16BIT;
4253 io->FirstByte = (baseaddr_t)IOMEM_FIRST;
4254 io->LastByte = (baseaddr_t)IOMEM_LAST;
4255 io->MinSize = IOMEM_MIN;
4256 io->MaxSize = IOMEM_MAX;
4257 io->ReqGran = IOMEM_GRAN;
4258 io->AddrLines = IOMEM_DECODE;
4259 io->EISASlot = 0;
4260 } else {
4261 mem_win_char_t *mem;
4262 mem = &window->mem_win_char;
4263 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT|
4264 WC_16BIT|WC_WP;
4265
4266 mem->FirstByte = (baseaddr_t)MEM_FIRST;
4267 mem->LastByte = (baseaddr_t)MEM_LAST;
4268
4269 mem->MinSize = MEM_MIN;
4270 mem->MaxSize = MEM_MAX;
4271 mem->ReqGran = PCIC_PAGE;
4272 mem->ReqBase = 0;
4273 mem->ReqOffset = PCIC_PAGE;
4274 mem->Slowest = MEM_SPEED_MAX;
4275 mem->Fastest = MEM_SPEED_MIN;
4276 }
4277 return (SUCCESS);
4278 }
4279
4280 /*
4281 * pcic_get_adapter()
4282 * SocketServices GetAdapter function
4283 * this is nearly a no-op.
4284 */
4285 /*ARGSUSED*/
4286 static int
4287 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt)
4288 {
4289 anp_t *anp = ddi_get_driver_private(dip);
4290 pcicdev_t *pcic = anp->an_private;
4291
4292 if (pcic->pc_flags & PCF_INTRENAB)
4293 adapt->SCRouting = IRQ_ENABLE;
4294 adapt->state = 0;
4295 return (SUCCESS);
4296 }
4297
4298 /*
4299 * pcic_get_page()
4300 * SocketServices GetPage function
4301 * returns info about the window
4302 */
4303 /*ARGSUSED*/
4304 static int
4305 pcic_get_page(dev_info_t *dip, get_page_t *page)
4306 {
4307 anp_t *anp = ddi_get_driver_private(dip);
4308 pcicdev_t *pcic = anp->an_private;
4309 int socket, window;
4310 pcs_memwin_t *winp;
4311
4312 socket = page->window / PCIC_NUMWINSOCK;
4313 window = page->window % PCIC_NUMWINSOCK;
4314
4315 /* I/O windows are the first two */
4316 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) {
4317 return (BAD_WINDOW);
4318 }
4319
4320 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem;
4321
4322 if (page->page != 0)
4323 return (BAD_PAGE);
4324
4325 page->state = 0;
4326 if (winp->pcw_status & PCW_ENABLED)
4327 page->state |= PS_ENABLED;
4328 if (winp->pcw_status & PCW_ATTRIBUTE)
4329 page->state |= PS_ATTRIBUTE;
4330 if (winp->pcw_status & PCW_WP)
4331 page->state |= PS_WP;
4332
4333 page->offset = (off_t)winp->pcw_offset;
4334
4335 return (SUCCESS);
4336 }
4337
4338 /*
4339 * pcic_get_socket()
4340 * SocketServices GetSocket
4341 * returns information about the current socket setting
4342 */
4343 /*ARGSUSED*/
4344 static int
4345 pcic_get_socket(dev_info_t *dip, get_socket_t *socket)
4346 {
4347 anp_t *anp = ddi_get_driver_private(dip);
4348 pcicdev_t *pcic = anp->an_private;
4349 int socknum, irq_enabled;
4350 pcic_socket_t *sockp;
4351
4352 socknum = socket->socket;
4353 sockp = &pcic->pc_sockets[socknum];
4354
4355 socket->SCIntMask = sockp->pcs_intmask;
4356 sockp->pcs_state = pcic_card_state(pcic, sockp);
4357
4358 socket->state = sockp->pcs_state;
4359 if (socket->state & SBM_CD) {
4360 socket->VccLevel = sockp->pcs_vcc;
4361 socket->Vpp1Level = sockp->pcs_vpp1;
4362 socket->Vpp2Level = sockp->pcs_vpp2;
4363 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ?
4364 IRQ_ENABLE : 0;
4365 socket->IRQRouting = sockp->pcs_irq | irq_enabled;
4366 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ?
4367 IF_IO : IF_MEMORY;
4368 } else {
4369 socket->VccLevel = 0;
4370 socket->Vpp1Level = 0;
4371 socket->Vpp2Level = 0;
4372 socket->IRQRouting = 0;
4373 socket->IFType = IF_MEMORY;
4374 }
4375 socket->CtlInd = 0; /* no indicators */
4376
4377 return (SUCCESS);
4378 }
4379
4380 /*
4381 * pcic_get_status()
4382 * SocketServices GetStatus
4383 * returns status information about the PC Card in
4384 * the selected socket
4385 */
4386 /*ARGSUSED*/
4387 static int
4388 pcic_get_status(dev_info_t *dip, get_ss_status_t *status)
4389 {
4390 anp_t *anp = ddi_get_driver_private(dip);
4391 pcicdev_t *pcic = anp->an_private;
4392 int socknum, irq_enabled;
4393 pcic_socket_t *sockp;
4394
4395 socknum = status->socket;
4396 sockp = &pcic->pc_sockets[socknum];
4397
4398 status->CardState = pcic_card_state(pcic, sockp);
4399 status->SocketState = sockp->pcs_state;
4400 status->CtlInd = 0; /* no indicators */
4401
4402 if (sockp->pcs_flags & PCS_CARD_PRESENT)
4403 status->SocketState |= SBM_CD;
4404 if (status->CardState & SBM_CD) {
4405 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ?
4406 IRQ_ENABLE : 0;
4407 status->IRQRouting = sockp->pcs_irq | irq_enabled;
4408 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ?
4409 IF_IO : IF_MEMORY;
4410 } else {
4411 status->IRQRouting = 0;
4412 status->IFType = IF_MEMORY;
4413 }
4414
4415 #if defined(PCIC_DEBUG)
4416 if (pcic_debug >= 8)
4417 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x,"
4418 "SocketState=%x\n",
4419 socknum, status->CardState, status->SocketState);
4420 #endif
4421 switch (pcic->pc_type) {
4422 uint32_t present_state;
4423 case PCIC_TI_PCI1410:
4424 case PCIC_TI_PCI1520:
4425 case PCIC_TI_PCI1420:
4426 case PCIC_ENE_1420:
4427 case PCIC_TOSHIBA_TOPIC100:
4428 case PCIC_TOSHIBA_TOPIC95:
4429 case PCIC_TOSHIBA_VENDOR:
4430 case PCIC_O2MICRO_VENDOR:
4431 case PCIC_TI_VENDOR:
4432 case PCIC_RICOH_VENDOR:
4433 present_state = pcic_getcb(pcic, CB_PRESENT_STATE);
4434 if (present_state & PCIC_CB_CARD)
4435 status->IFType = IF_CARDBUS;
4436 #if defined(PCIC_DEBUG)
4437 if (pcic_debug >= 8)
4438 cmn_err(CE_CONT,
4439 "pcic_get_status: present_state=0x%x\n",
4440 present_state);
4441 #endif
4442 break;
4443 default:
4444 break;
4445 }
4446
4447 return (SUCCESS);
4448 }
4449
4450 /*
4451 * pcic_get_window()
4452 * SocketServices GetWindow function
4453 * returns state information about the specified window
4454 */
4455 /*ARGSUSED*/
4456 static int
4457 pcic_get_window(dev_info_t *dip, get_window_t *window)
4458 {
4459 anp_t *anp = ddi_get_driver_private(dip);
4460 pcicdev_t *pcic = anp->an_private;
4461 int socket, win;
4462 pcic_socket_t *sockp;
4463 pcs_memwin_t *winp;
4464
4465 socket = window->window / PCIC_NUMWINSOCK;
4466 win = window->window % PCIC_NUMWINSOCK;
4467 #if defined(PCIC_DEBUG)
4468 if (pcic_debug) {
4469 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n",
4470 socket, win);
4471 }
4472 #endif
4473
4474 if (socket > pcic->pc_numsockets)
4475 return (BAD_WINDOW);
4476
4477 sockp = &pcic->pc_sockets[socket];
4478 winp = &sockp->pcs_windows[win].mem;
4479
4480 window->socket = socket;
4481 window->size = winp->pcw_len;
4482 window->speed = winp->pcw_speed;
4483 window->handle = (ddi_acc_handle_t)winp->pcw_handle;
4484 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset;
4485
4486 if (win >= PCIC_IOWINDOWS) {
4487 window->state = 0;
4488 } else {
4489 window->state = WS_IO;
4490 }
4491 if (winp->pcw_status & PCW_ENABLED)
4492 window->state |= WS_ENABLED;
4493
4494 if (winp->pcw_status & PCS_CARD_16BIT)
4495 window->state |= WS_16BIT;
4496 #if defined(PCIC_DEBUG)
4497 if (pcic_debug)
4498 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n",
4499 window->size, (unsigned)window->speed,
4500 (void *)window->handle, window->state);
4501 #endif
4502
4503 return (SUCCESS);
4504 }
4505
4506 /*
4507 * pcic_ll_reset
4508 * low level reset
4509 * separated out so it can be called when already locked
4510 *
4511 * There are two variables that control the RESET timing:
4512 * pcic_prereset_time - time in mS before asserting RESET
4513 * pcic_reset_time - time in mS to assert RESET
4514 *
4515 */
4516 int pcic_prereset_time = 1;
4517 int pcic_reset_time = 10;
4518 int pcic_postreset_time = 20;
4519 int pcic_vpp_is_vcc_during_reset = 0;
4520
4521 static int
4522 pcic_ll_reset(pcicdev_t *pcic, int socket)
4523 {
4524 int windowbits, iobits;
4525 uint32_t pwr;
4526
4527 /* save windows that were on */
4528 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE);
4529 if (pcic_reset_time == 0)
4530 return (windowbits);
4531 /* turn all windows off */
4532 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0);
4533
4534 #if defined(PCIC_DEBUG)
4535 pcic_err(pcic->dip, 6,
4536 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n",
4537 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL),
4538 pcic_getcb(pcic, CB_CONTROL),
4539 pcic_getcb(pcic, CB_PRESENT_STATE));
4540 #endif
4541
4542 if (pcic_vpp_is_vcc_during_reset) {
4543
4544 /*
4545 * Set VPP to VCC for the duration of the reset - for aironet
4546 * card.
4547 */
4548 if (pcic->pc_flags & PCF_CBPWRCTL) {
4549 pwr = pcic_getcb(pcic, CB_CONTROL);
4550 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC);
4551 (void) pcic_getcb(pcic, CB_CONTROL);
4552 } else {
4553 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
4554 pcic_putb(pcic, socket, PCIC_POWER_CONTROL,
4555 pwr | 1);
4556 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
4557 }
4558 }
4559
4560 if (pcic_prereset_time > 0) {
4561 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n",
4562 pcic_prereset_time);
4563 pcic_mswait(pcic, socket, pcic_prereset_time);
4564 }
4565
4566 /* turn interrupts off and start a reset */
4567 pcic_err(pcic->dip, 8,
4568 "pcic_ll_reset turn interrupts off and start a reset\n");
4569 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT);
4570 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET);
4571 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits);
4572 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT);
4573
4574 switch (pcic->pc_type) {
4575 case PCIC_INTEL_i82092:
4576 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ,
4577 PCIC_82092_INT_DISABLE);
4578 break;
4579 default:
4580 break;
4581 } /* switch */
4582
4583 pcic->pc_sockets[socket].pcs_state = 0;
4584
4585 if (pcic_reset_time > 0) {
4586 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n",
4587 pcic_reset_time);
4588 pcic_mswait(pcic, socket, pcic_reset_time);
4589 }
4590
4591 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n");
4592
4593 /* take it out of RESET now */
4594 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits);
4595 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT);
4596
4597 /*
4598 * can't access the card for 20ms, but we really don't
4599 * want to sit around that long. The pcic is still usable.
4600 * memory accesses must wait for RDY to come up.
4601 */
4602 if (pcic_postreset_time > 0) {
4603 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n",
4604 pcic_postreset_time);
4605 pcic_mswait(pcic, socket, pcic_postreset_time);
4606 }
4607
4608 if (pcic_vpp_is_vcc_during_reset > 1) {
4609
4610 /*
4611 * Return VPP power to whatever it was before.
4612 */
4613 if (pcic->pc_flags & PCF_CBPWRCTL) {
4614 pcic_putcb(pcic, CB_CONTROL, pwr);
4615 (void) pcic_getcb(pcic, CB_CONTROL);
4616 } else {
4617 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr);
4618 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
4619 }
4620 }
4621
4622 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits);
4623
4624 return (windowbits);
4625 }
4626
4627 /*
4628 * pcic_reset_socket()
4629 * SocketServices ResetSocket function
4630 * puts the PC Card in the socket into the RESET state
4631 * and then takes it out after the the cycle time
4632 * The socket is back to initial state when done
4633 */
4634 static int
4635 pcic_reset_socket(dev_info_t *dip, int socket, int mode)
4636 {
4637 anp_t *anp = ddi_get_driver_private(dip);
4638 pcicdev_t *pcic = anp->an_private;
4639 int value;
4640 int i, mint;
4641 pcic_socket_t *sockp;
4642
4643 #if defined(PCIC_DEBUG)
4644 if (pcic_debug >= 8)
4645 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n",
4646 (void *)dip, socket, mode,
4647 mode == RESET_MODE_FULL ? "full" : "partial");
4648 #endif
4649
4650 mutex_enter(&pcic->pc_lock); /* protect the registers */
4651
4652 /* Turn off management interupts. */
4653 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT);
4654 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK);
4655
4656 sockp = &pcic->pc_sockets[socket];
4657
4658 value = pcic_ll_reset(pcic, socket);
4659 if (mode == RESET_MODE_FULL) {
4660 /* disable and unmap all mapped windows */
4661 for (i = 0; i < PCIC_NUMWINSOCK; i++) {
4662 if (i < PCIC_IOWINDOWS) {
4663 if (sockp->pcs_windows[i].io.pcw_status &
4664 PCW_MAPPED) {
4665 pcs_iowin_t *io;
4666 io = &sockp->pcs_windows[i].io;
4667 io->pcw_status &= ~PCW_ENABLED;
4668 }
4669 } else {
4670 if (sockp->pcs_windows[i].mem.pcw_status &
4671 PCW_MAPPED) {
4672 pcs_memwin_t *mem;
4673 mem = &sockp->pcs_windows[i].mem;
4674 mem->pcw_status &= ~PCW_ENABLED;
4675 }
4676 }
4677 }
4678 } else {
4679 /* turn windows back on */
4680 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value);
4681 /* wait the rest of the time here */
4682 pcic_mswait(pcic, socket, 10);
4683 }
4684 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint);
4685 mutex_exit(&pcic->pc_lock);
4686 return (SUCCESS);
4687 }
4688
4689 /*
4690 * pcic_set_interrupt()
4691 * SocketServices SetInterrupt function
4692 */
4693 static int
4694 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler)
4695 {
4696 anp_t *anp = ddi_get_driver_private(dip);
4697 pcicdev_t *pcic = anp->an_private;
4698 int value = DDI_SUCCESS;
4699 inthandler_t *intr;
4700
4701 #if defined(PCIC_DEBUG)
4702 if (pcic_debug) {
4703 cmn_err(CE_CONT,
4704 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n",
4705 pcic->pc_intr_mode);
4706 cmn_err(CE_CONT,
4707 "\t irq_top=%p handler=%p handler_id=%x\n",
4708 (void *)pcic->irq_top, (void *)handler->handler,
4709 handler->handler_id);
4710 }
4711 #endif
4712
4713 /*
4714 * If we're on a PCI bus, we route all IO IRQs through a single
4715 * PCI interrupt (typically INT A#) so we don't have to do
4716 * much other than add the caller to general interrupt handler
4717 * and set some state.
4718 */
4719
4720 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP);
4721 if (intr == NULL)
4722 return (NO_RESOURCE);
4723
4724 switch (pcic->pc_intr_mode) {
4725 case PCIC_INTR_MODE_PCI_1:
4726 /*
4727 * We only allow above-lock-level IO IRQ handlers
4728 * in the PCI bus case.
4729 */
4730
4731 mutex_enter(&pcic->intr_lock);
4732
4733 if (pcic->irq_top == NULL) {
4734 pcic->irq_top = intr;
4735 pcic->irq_current = pcic->irq_top;
4736 } else {
4737 while (pcic->irq_current->next != NULL)
4738 pcic->irq_current = pcic->irq_current->next;
4739 pcic->irq_current->next = intr;
4740 pcic->irq_current = pcic->irq_current->next;
4741 }
4742
4743 pcic->irq_current->intr =
4744 (ddi_intr_handler_t *)handler->handler;
4745 pcic->irq_current->handler_id = handler->handler_id;
4746 pcic->irq_current->arg1 = handler->arg1;
4747 pcic->irq_current->arg2 = handler->arg2;
4748 pcic->irq_current->socket = handler->socket;
4749
4750 mutex_exit(&pcic->intr_lock);
4751
4752 handler->iblk_cookie = &pcic->pc_pri;
4753 handler->idev_cookie = &pcic->pc_dcookie;
4754 break;
4755
4756 default:
4757 intr->intr = (ddi_intr_handler_t *)handler->handler;
4758 intr->handler_id = handler->handler_id;
4759 intr->arg1 = handler->arg1;
4760 intr->arg2 = handler->arg2;
4761 intr->socket = handler->socket;
4762 intr->irq = handler->irq;
4763
4764 /*
4765 * need to revisit this to see if interrupts can be
4766 * shared someday. Note that IRQ is set in the common
4767 * code.
4768 */
4769 mutex_enter(&pcic->pc_lock);
4770 if (pcic->pc_handlers == NULL) {
4771 pcic->pc_handlers = intr;
4772 intr->next = intr->prev = intr;
4773 } else {
4774 insque(intr, pcic->pc_handlers);
4775 }
4776 mutex_exit(&pcic->pc_lock);
4777
4778 break;
4779 }
4780
4781 /*
4782 * need to fill in cookies in event of multiple high priority
4783 * interrupt handlers on same IRQ
4784 */
4785
4786 #if defined(PCIC_DEBUG)
4787 if (pcic_debug) {
4788 cmn_err(CE_CONT,
4789 "pcic_set_interrupt: exit irq_top=%p value=%d\n",
4790 (void *)pcic->irq_top, value);
4791 }
4792 #endif
4793
4794 if (value == DDI_SUCCESS) {
4795 return (SUCCESS);
4796 } else {
4797 return (BAD_IRQ);
4798 }
4799 }
4800
4801 /*
4802 * pcic_clear_interrupt()
4803 * SocketServices ClearInterrupt function
4804 *
4805 * Interrupts for PCIC are complicated by the fact that we must
4806 * follow several different models for interrupts.
4807 * ISA: there is an interrupt per adapter and per socket and
4808 * they can't be shared.
4809 * PCI: some adapters have one PCI interrupt available while others
4810 * have up to 4. Solaris may or may not allow us to use more
4811 * than 1 so we essentially share them all at this point.
4812 * Hybrid: PCI bridge but interrupts wired to host interrupt controller.
4813 * This is like ISA but we have to fudge and create an intrspec
4814 * that PCI's parent understands and bypass the PCI nexus.
4815 * multifunction: this requires sharing the interrupts on a per-socket
4816 * basis.
4817 */
4818 static int
4819 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler)
4820 {
4821 anp_t *anp = ddi_get_driver_private(dip);
4822 pcicdev_t *pcic = anp->an_private;
4823 inthandler_t *intr, *prev, *current;
4824 int i;
4825
4826 /*
4827 * If we're on a PCI bus, we route all IO IRQs through a single
4828 * PCI interrupt (typically INT A#) so we don't have to do
4829 * much other than remove the caller from the general
4830 * interrupt handler callout list.
4831 */
4832
4833 #if defined(PCIC_DEBUG)
4834 if (pcic_debug) {
4835 cmn_err(CE_CONT,
4836 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n",
4837 pcic->pc_intr_mode);
4838 cmn_err(CE_CONT,
4839 "\t irq_top=%p handler=%p handler_id=%x\n",
4840 (void *)pcic->irq_top, (void *)handler->handler,
4841 handler->handler_id);
4842 }
4843 #endif
4844
4845 switch (pcic->pc_intr_mode) {
4846 case PCIC_INTR_MODE_PCI_1:
4847
4848 mutex_enter(&pcic->intr_lock);
4849 if (pcic->irq_top == NULL) {
4850 mutex_exit(&pcic->intr_lock);
4851 return (BAD_IRQ);
4852 }
4853
4854 intr = NULL;
4855 pcic->irq_current = pcic->irq_top;
4856
4857 while ((pcic->irq_current != NULL) &&
4858 (pcic->irq_current->handler_id !=
4859 handler->handler_id)) {
4860 intr = pcic->irq_current;
4861 pcic->irq_current = pcic->irq_current->next;
4862 }
4863
4864 if (pcic->irq_current == NULL) {
4865 mutex_exit(&pcic->intr_lock);
4866 return (BAD_IRQ);
4867 }
4868
4869 if (intr != NULL) {
4870 intr->next = pcic->irq_current->next;
4871 } else {
4872 pcic->irq_top = pcic->irq_current->next;
4873 }
4874
4875 current = pcic->irq_current;
4876 pcic->irq_current = pcic->irq_top;
4877 mutex_exit(&pcic->intr_lock);
4878 kmem_free(current, sizeof (inthandler_t));
4879
4880 break;
4881
4882 default:
4883
4884 mutex_enter(&pcic->pc_lock);
4885 intr = pcic_handlers;
4886 prev = (inthandler_t *)&pcic_handlers;
4887
4888 while (intr != NULL) {
4889 if (intr->handler_id == handler->handler_id) {
4890 i = intr->irq & PCIC_INTR_MASK;
4891 if (--pcic_irq_map[i].count == 0) {
4892 /* multi-handler form */
4893 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]);
4894 (void) ddi_intr_remove_handler(
4895 pcic->pc_intr_htblp[i]);
4896 (void) ddi_intr_free(pcic->pc_intr_htblp[i]);
4897 (void) pcmcia_return_intr(pcic->dip, i);
4898 #if defined(PCIC_DEBUG)
4899 if (pcic_debug) {
4900 cmn_err(CE_CONT,
4901 "removing interrupt %d at %s "
4902 "priority\n", i, "high");
4903 cmn_err(CE_CONT,
4904 "ddi_remove_intr(%p, %x, %p)\n",
4905 (void *)dip,
4906 0,
4907 (void *)intr->iblk_cookie);
4908 }
4909 #endif
4910 }
4911 prev->next = intr->next;
4912 kmem_free(intr, sizeof (inthandler_t));
4913 intr = prev->next;
4914 } else {
4915 prev = intr;
4916 intr = intr->next;
4917 } /* if (handler_id) */
4918 } /* while */
4919
4920 mutex_exit(&pcic->pc_lock);
4921 }
4922
4923 #if defined(PCIC_DEBUG)
4924 if (pcic_debug) {
4925 cmn_err(CE_CONT,
4926 "pcic_clear_interrupt: exit irq_top=%p\n",
4927 (void *)pcic->irq_top);
4928 }
4929 #endif
4930
4931
4932 return (SUCCESS);
4933 }
4934
4935 struct intel_regs {
4936 char *name;
4937 int off;
4938 char *fmt;
4939 } iregs[] = {
4940 {"ident ", 0},
4941 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"},
4942 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO"
4943 "\7DRD\10OE"},
4944 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"},
4945 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"},
4946 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"},
4947 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"},
4948 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"},
4949 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"},
4950 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"},
4951 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"},
4952 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"},
4953 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"},
4954 {"io0-slow ", 8},
4955 {"io0-shi ", 9},
4956 {"io0-elow ", 0xa},
4957 {"io0-ehi ", 0xb},
4958 {"io1-slow ", 0xc},
4959 {"io1-shi ", 0xd},
4960 {"io1-elow ", 0xe},
4961 {"io1-ehi ", 0xf},
4962 {"mem0-slow ", 0x10},
4963 {"mem0-shi ", 0x11, "\020\7ZW\10DS"},
4964 {"mem0-elow ", 0x12},
4965 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"},
4966 {"card0-low ", 0x14},
4967 {"card0-hi ", 0x15, "\020\7AM\10WP"},
4968 {"mem1-slow ", 0x18},
4969 {"mem1-shi ", 0x19, "\020\7ZW\10DS"},
4970 {"mem1-elow ", 0x1a},
4971 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"},
4972 {"card1-low ", 0x1c},
4973 {"card1-hi ", 0x1d, "\020\7AM\10WP"},
4974 {"mem2-slow ", 0x20},
4975 {"mem2-shi ", 0x21, "\020\7ZW\10DS"},
4976 {"mem2-elow ", 0x22},
4977 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"},
4978 {"card2-low ", 0x24},
4979 {"card2-hi ", 0x25, "\020\7AM\10WP"},
4980 {"mem3-slow ", 0x28},
4981 {"mem3-shi ", 0x29, "\020\7ZW\10DS"},
4982 {"mem3-elow ", 0x2a},
4983 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"},
4984 {"card3-low ", 0x2c},
4985 {"card3-hi ", 0x2d, "\020\7AM\10WP"},
4986
4987 {"mem4-slow ", 0x30},
4988 {"mem4-shi ", 0x31, "\020\7ZW\10DS"},
4989 {"mem4-elow ", 0x32},
4990 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"},
4991 {"card4-low ", 0x34},
4992 {"card4-hi ", 0x35, "\020\7AM\10WP"},
4993 {"mpage0 ", 0x40},
4994 {"mpage1 ", 0x41},
4995 {"mpage2 ", 0x42},
4996 {"mpage3 ", 0x43},
4997 {"mpage4 ", 0x44},
4998 {NULL},
4999 };
5000
5001 static struct intel_regs cregs[] = {
5002 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"},
5003 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"},
5004 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"},
5005 {"chip-info ", 0x1f, "\20\6DUAL"},
5006 {"IO-offlow0", 0x36},
5007 {"IO-offhi0 ", 0x37},
5008 {"IO-offlow1", 0x38},
5009 {"IO-offhi1 ", 0x39},
5010 NULL,
5011 };
5012
5013 static struct intel_regs cxregs[] = {
5014 {"ext-ctl-1 ", 0x03,
5015 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"},
5016 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"},
5017 {"mem0-up ", 0x05},
5018 {"mem1-up ", 0x06},
5019 {"mem2-up ", 0x07},
5020 {"mem3-up ", 0x08},
5021 {"mem4-up ", 0x09},
5022 {NULL}
5023 };
5024
5025 void
5026 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len)
5027 {
5028 int i, value, j;
5029 char buff[256];
5030 char *fmt;
5031
5032 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n");
5033 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) {
5034 int sval;
5035 if (cregs[i].off == PCIC_MISC_CTL_2)
5036 sval = 0;
5037 else
5038 sval = socket;
5039 value = pcic_getb(pcic, sval, cregs[i].off);
5040 if (i & 1) {
5041 if (cregs[i].fmt)
5042 fmt = "%s\t%s\t%b\n";
5043 else
5044 fmt = "%s\t%s\t%x\n";
5045 cmn_err(CE_CONT, fmt, buff,
5046 cregs[i].name, value, cregs[i].fmt);
5047 buff[0] = '\0';
5048 } else {
5049 if (cregs[i].fmt)
5050 fmt = "\t%s\t%b";
5051 else
5052 fmt = "\t%s\t%x";
5053 (void) sprintf(buff, fmt,
5054 cregs[i].name, value, cregs[i].fmt);
5055 for (j = strlen(buff); j < 40; j++)
5056 buff[j] = ' ';
5057 buff[40] = '\0';
5058 }
5059 }
5060 cmn_err(CE_CONT, "%s\n", buff);
5061
5062 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0);
5063 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1);
5064 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j);
5065
5066 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0);
5067 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1);
5068 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j);
5069
5070 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0);
5071 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1);
5072 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j);
5073
5074 cmn_err(CE_CONT, "--------- Extended Registers --------\n");
5075
5076 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) {
5077 value = clext_reg_read(pcic, socket, cxregs[i].off);
5078 if (i & 1) {
5079 if (cxregs[i].fmt)
5080 fmt = "%s\t%s\t%b\n";
5081 else
5082 fmt = "%s\t%s\t%x\n";
5083 cmn_err(CE_CONT, fmt, buff,
5084 cxregs[i].name, value, cxregs[i].fmt);
5085 buff[0] = '\0';
5086 } else {
5087 if (cxregs[i].fmt)
5088 fmt = "\t%s\t%b";
5089 else
5090 fmt = "\t%s\t%x";
5091 (void) sprintf(buff, fmt,
5092 cxregs[i].name, value, cxregs[i].fmt);
5093 for (j = strlen(buff); j < 40; j++)
5094 buff[j] = ' ';
5095 buff[40] = '\0';
5096 }
5097 }
5098 }
5099
5100 #if defined(PCIC_DEBUG)
5101 static void
5102 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len)
5103 {
5104 int i, value, j;
5105 char buff[256];
5106 char *fmt;
5107
5108 #if defined(PCIC_DEBUG)
5109 if (pcic_debug < 2)
5110 return;
5111 #endif
5112 cmn_err(CE_CONT,
5113 "----------- PCIC Registers for socket %d---------\n",
5114 socket);
5115 cmn_err(CE_CONT,
5116 "\tname value name value\n");
5117
5118 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) {
5119 value = pcic_getb(pcic, socket, iregs[i].off);
5120 if (i & 1) {
5121 if (iregs[i].fmt)
5122 fmt = "%s\t%s\t%b\n";
5123 else
5124 fmt = "%s\t%s\t%x\n";
5125 cmn_err(CE_CONT, fmt, buff,
5126 iregs[i].name, value, iregs[i].fmt);
5127 buff[0] = '\0';
5128 } else {
5129 if (iregs[i].fmt)
5130 fmt = "\t%s\t%b";
5131 else
5132 fmt = "\t%s\t%x";
5133 (void) sprintf(buff, fmt,
5134 iregs[i].name, value, iregs[i].fmt);
5135 for (j = strlen(buff); j < 40; j++)
5136 buff[j] = ' ';
5137 buff[40] = '\0';
5138 }
5139 }
5140 switch (pcic->pc_type) {
5141 case PCIC_CL_PD6710:
5142 case PCIC_CL_PD6722:
5143 case PCIC_CL_PD6729:
5144 case PCIC_CL_PD6832:
5145 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF);
5146 break;
5147 }
5148 cmn_err(CE_CONT, "%s\n", buff);
5149 }
5150 #endif
5151
5152 /*
5153 * pcic_mswait(ms)
5154 * sleep ms milliseconds
5155 * call drv_usecwait once for each ms
5156 */
5157 static void
5158 pcic_mswait(pcicdev_t *pcic, int socket, int ms)
5159 {
5160 if (ms) {
5161 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING;
5162 pcic_mutex_exit(&pcic->pc_lock);
5163 delay(drv_usectohz(ms*1000));
5164 pcic_mutex_enter(&pcic->pc_lock);
5165 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING;
5166 }
5167 }
5168
5169 /*
5170 * pcic_check_ready(pcic, index, off)
5171 * Wait for card to come ready
5172 * We only wait if the card is NOT in RESET
5173 * and power is on.
5174 */
5175 static boolean_t
5176 pcic_check_ready(pcicdev_t *pcic, int socket)
5177 {
5178 int ifstate, intstate;
5179
5180 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT);
5181 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS);
5182
5183 if ((intstate & PCIC_RESET) &&
5184 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) ==
5185 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK)))
5186 return (B_TRUE);
5187
5188 #ifdef PCIC_DEBUG
5189 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, "
5190 "ifstate = 0x%x\n", intstate, ifstate);
5191 if (pcic_debug) {
5192 pcic_debug += 4;
5193 xxdmp_all_regs(pcic, socket, -1);
5194 pcic_debug -= 4;
5195 }
5196 #endif
5197 return (B_FALSE);
5198 }
5199
5200 /*
5201 * Cirrus Logic extended register read/write routines
5202 */
5203 static int
5204 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg)
5205 {
5206 int val;
5207
5208 switch (pcic->pc_io_type) {
5209 case PCIC_IO_TYPE_YENTA:
5210 val = ddi_get8(pcic->handle,
5211 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg);
5212 break;
5213 default:
5214 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg);
5215 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1);
5216 break;
5217 }
5218
5219 return (val);
5220 }
5221
5222 static void
5223 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value)
5224 {
5225 switch (pcic->pc_io_type) {
5226 case PCIC_IO_TYPE_YENTA:
5227 ddi_put8(pcic->handle,
5228 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value);
5229 break;
5230 default:
5231 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg);
5232 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value);
5233 break;
5234 }
5235 }
5236
5237 /*
5238 * Misc PCI functions
5239 */
5240 static void
5241 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags)
5242 {
5243 unsigned cmd;
5244
5245 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) {
5246 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4));
5247 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) ==
5248 (PCI_COMM_IO|PCI_COMM_MAE))
5249 return;
5250
5251 if (flags & PCIC_ENABLE_IO)
5252 cmd |= PCI_COMM_IO;
5253
5254 if (flags & PCIC_ENABLE_MEM)
5255 cmd |= PCI_COMM_MAE;
5256
5257 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd);
5258 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */
5259 }
5260
5261 /*
5262 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type
5263 */
5264 static int
5265 pcic_find_pci_type(pcicdev_t *pcic)
5266 {
5267 uint32_t vend, device;
5268
5269 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip,
5270 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS,
5271 "vendor-id", -1);
5272 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip,
5273 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS,
5274 "device-id", -1);
5275
5276 device = PCI_ID(vend, device);
5277 pcic->pc_type = device;
5278 pcic->pc_chipname = "PCI:unknown";
5279
5280 switch (device) {
5281 case PCIC_INTEL_i82092:
5282 pcic->pc_chipname = PCIC_TYPE_i82092;
5283 break;
5284 case PCIC_CL_PD6729:
5285 pcic->pc_chipname = PCIC_TYPE_PD6729;
5286 /*
5287 * Some 6730's incorrectly identify themselves
5288 * as a 6729, so we need to do some more tests
5289 * here to see if the device that's claiming
5290 * to be a 6729 is really a 6730.
5291 */
5292 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) &
5293 PCIC_CLEXT_MISC_CTL_3_REV_MASK) ==
5294 0) {
5295 pcic->pc_chipname = PCIC_TYPE_PD6730;
5296 pcic->pc_type = PCIC_CL_PD6730;
5297 }
5298 break;
5299 case PCIC_CL_PD6730:
5300 pcic->pc_chipname = PCIC_TYPE_PD6730;
5301 break;
5302 case PCIC_CL_PD6832:
5303 pcic->pc_chipname = PCIC_TYPE_PD6832;
5304 break;
5305 case PCIC_SMC_34C90:
5306 pcic->pc_chipname = PCIC_TYPE_34C90;
5307 break;
5308 case PCIC_TOSHIBA_TOPIC95:
5309 pcic->pc_chipname = PCIC_TYPE_TOPIC95;
5310 break;
5311 case PCIC_TOSHIBA_TOPIC100:
5312 pcic->pc_chipname = PCIC_TYPE_TOPIC100;
5313 break;
5314 case PCIC_TI_PCI1031:
5315 pcic->pc_chipname = PCIC_TYPE_PCI1031;
5316 break;
5317 case PCIC_TI_PCI1130:
5318 pcic->pc_chipname = PCIC_TYPE_PCI1130;
5319 break;
5320 case PCIC_TI_PCI1131:
5321 pcic->pc_chipname = PCIC_TYPE_PCI1131;
5322 break;
5323 case PCIC_TI_PCI1250:
5324 pcic->pc_chipname = PCIC_TYPE_PCI1250;
5325 break;
5326 case PCIC_TI_PCI1225:
5327 pcic->pc_chipname = PCIC_TYPE_PCI1225;
5328 break;
5329 case PCIC_TI_PCI1410:
5330 pcic->pc_chipname = PCIC_TYPE_PCI1410;
5331 break;
5332 case PCIC_TI_PCI1510:
5333 pcic->pc_chipname = PCIC_TYPE_PCI1510;
5334 break;
5335 case PCIC_TI_PCI1520:
5336 pcic->pc_chipname = PCIC_TYPE_PCI1520;
5337 break;
5338 case PCIC_TI_PCI1221:
5339 pcic->pc_chipname = PCIC_TYPE_PCI1221;
5340 break;
5341 case PCIC_TI_PCI1050:
5342 pcic->pc_chipname = PCIC_TYPE_PCI1050;
5343 break;
5344 case PCIC_ENE_1410:
5345 pcic->pc_chipname = PCIC_TYPE_1410;
5346 break;
5347 case PCIC_O2_OZ6912:
5348 pcic->pc_chipname = PCIC_TYPE_OZ6912;
5349 break;
5350 case PCIC_RICOH_RL5C466:
5351 pcic->pc_chipname = PCIC_TYPE_RL5C466;
5352 break;
5353 case PCIC_TI_PCI1420:
5354 pcic->pc_chipname = PCIC_TYPE_PCI1420;
5355 break;
5356 case PCIC_ENE_1420:
5357 pcic->pc_chipname = PCIC_TYPE_1420;
5358 break;
5359 default:
5360 switch (PCI_ID(vend, (uint32_t)0)) {
5361 case PCIC_TOSHIBA_VENDOR:
5362 pcic->pc_chipname = PCIC_TYPE_TOSHIBA;
5363 pcic->pc_type = PCIC_TOSHIBA_VENDOR;
5364 break;
5365 case PCIC_TI_VENDOR:
5366 pcic->pc_chipname = PCIC_TYPE_TI;
5367 pcic->pc_type = PCIC_TI_VENDOR;
5368 break;
5369 case PCIC_O2MICRO_VENDOR:
5370 pcic->pc_chipname = PCIC_TYPE_O2MICRO;
5371 pcic->pc_type = PCIC_O2MICRO_VENDOR;
5372 break;
5373 case PCIC_RICOH_VENDOR:
5374 pcic->pc_chipname = PCIC_TYPE_RICOH;
5375 pcic->pc_type = PCIC_RICOH_VENDOR;
5376 break;
5377 default:
5378 if (!(pcic->pc_flags & PCF_CARDBUS))
5379 return (DDI_FAILURE);
5380 pcic->pc_chipname = PCIC_TYPE_YENTA;
5381 break;
5382 }
5383 }
5384 return (DDI_SUCCESS);
5385 }
5386
5387 static void
5388 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state)
5389 {
5390 uchar_t ppirr = ddi_get8(pcic->cfg_handle,
5391 pcic->cfgaddr + PCIC_82092_PPIRR);
5392 uchar_t val;
5393
5394 if (intr == PCIC_82092_CTL_SMI) {
5395 val = PCIC_82092_SMI_CTL(socket,
5396 PCIC_82092_INT_DISABLE);
5397 ppirr &= ~val;
5398 val = PCIC_82092_SMI_CTL(socket, state);
5399 ppirr |= val;
5400 } else {
5401 val = PCIC_82092_IRQ_CTL(socket,
5402 PCIC_82092_INT_DISABLE);
5403 ppirr &= ~val;
5404 val = PCIC_82092_IRQ_CTL(socket, state);
5405 ppirr |= val;
5406 }
5407 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR,
5408 ppirr);
5409 }
5410
5411 static uint_t
5412 pcic_cd_softint(caddr_t arg1, caddr_t arg2)
5413 {
5414 pcic_socket_t *sockp = (pcic_socket_t *)arg1;
5415 uint_t rc = DDI_INTR_UNCLAIMED;
5416
5417 _NOTE(ARGUNUSED(arg2))
5418
5419 mutex_enter(&sockp->pcs_pcic->pc_lock);
5420 if (sockp->pcs_cd_softint_flg) {
5421 uint8_t status;
5422 sockp->pcs_cd_softint_flg = 0;
5423 rc = DDI_INTR_CLAIMED;
5424 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket,
5425 PCIC_INTERFACE_STATUS);
5426 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status);
5427 }
5428 mutex_exit(&sockp->pcs_pcic->pc_lock);
5429 return (rc);
5430 }
5431
5432 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT;
5433 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME;
5434 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT;
5435
5436 #ifdef CARDBUS
5437 static uint32_t pcic_cbps_on = 0;
5438 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK |
5439 CB_PS_XVCARD | CB_PS_YVCARD;
5440 #else
5441 static uint32_t pcic_cbps_on = CB_PS_16BITCARD;
5442 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK |
5443 CB_PS_CBCARD |
5444 CB_PS_XVCARD | CB_PS_YVCARD;
5445 #endif
5446 static void
5447 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status)
5448 {
5449 boolean_t do_debounce = B_FALSE;
5450 int debounce_time = drv_usectohz(pcic_debounce_time);
5451 uint8_t irq;
5452 timeout_id_t debounce;
5453
5454 /*
5455 * Always reset debounce but may need to check original state later.
5456 */
5457 debounce = sockp->pcs_debounce_id;
5458 sockp->pcs_debounce_id = 0;
5459
5460 /*
5461 * Check to see whether a card is present or not. There are
5462 * only two states that we are concerned with - the state
5463 * where both CD pins are asserted, which means that the
5464 * card is fully seated, and the state where neither CD
5465 * pin is asserted, which means that the card is not
5466 * present.
5467 * The CD signals are generally very noisy and cause a lot of
5468 * contact bounce as the card is being inserted and
5469 * removed, so we need to do some software debouncing.
5470 */
5471
5472 #ifdef PCIC_DEBUG
5473 pcic_err(pcic->dip, 6,
5474 "pcic%d handle_cd_change: socket %d card status 0x%x"
5475 " deb 0x%p\n", ddi_get_instance(pcic->dip),
5476 sockp->pcs_socket, status, debounce);
5477 #endif
5478 switch (status & PCIC_ISTAT_CD_MASK) {
5479 case PCIC_CD_PRESENT_OK:
5480 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM);
5481 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) {
5482 uint32_t cbps;
5483 #ifdef PCIC_DEBUG
5484 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags);
5485 #endif
5486 cbps = pcic_getcb(pcic, CB_PRESENT_STATE);
5487 #ifdef PCIC_DEBUG
5488 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps);
5489 #endif
5490 /*
5491 * Check the CB bits are sane.
5492 */
5493 if ((cbps & pcic_cbps_on) != pcic_cbps_on ||
5494 cbps & pcic_cbps_off) {
5495 cmn_err(CE_WARN,
5496 "%s%d: Odd Cardbus Present State 0x%x\n",
5497 ddi_get_name(pcic->dip),
5498 ddi_get_instance(pcic->dip),
5499 cbps);
5500 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST);
5501 debounce = 0;
5502 debounce_time = drv_usectohz(1000000);
5503 }
5504 if (debounce) {
5505 sockp->pcs_flags |= PCS_CARD_PRESENT;
5506 if (pcic_do_insertion) {
5507
5508 cbps = pcic_getcb(pcic, CB_PRESENT_STATE);
5509
5510 if (cbps & CB_PS_16BITCARD) {
5511 pcic_err(pcic->dip,
5512 8, "16 bit card inserted\n");
5513 sockp->pcs_flags |= PCS_CARD_IS16BIT;
5514 /* calls pcm_adapter_callback() */
5515 if (pcic->pc_callback) {
5516
5517 (void) ddi_prop_update_string(
5518 DDI_DEV_T_NONE,
5519 pcic->dip, PCM_DEVICETYPE,
5520 "pccard");
5521 PC_CALLBACK(pcic->dip,
5522 pcic->pc_cb_arg,
5523 PCE_CARD_INSERT,
5524 sockp->pcs_socket);
5525 }
5526 } else if (cbps & CB_PS_CBCARD) {
5527 pcic_err(pcic->dip,
5528 8, "32 bit card inserted\n");
5529
5530 if (pcic->pc_flags & PCF_CARDBUS) {
5531 sockp->pcs_flags |=
5532 PCS_CARD_ISCARDBUS;
5533 #ifdef CARDBUS
5534 if (!pcic_load_cardbus(pcic,
5535 sockp)) {
5536 pcic_unload_cardbus(
5537 pcic, sockp);
5538 }
5539
5540 #else
5541 cmn_err(CE_NOTE,
5542 "32 bit Cardbus not"
5543 " supported in"
5544 " this device driver\n");
5545 #endif
5546 } else {
5547 /*
5548 * Ignore the card
5549 */
5550 cmn_err(CE_NOTE,
5551 "32 bit Cardbus not"
5552 " supported on this"
5553 " device\n");
5554 }
5555 } else {
5556 cmn_err(CE_NOTE,
5557 "Unsupported PCMCIA card"
5558 " inserted\n");
5559 }
5560 }
5561 } else {
5562 do_debounce = B_TRUE;
5563 }
5564 } else {
5565 /*
5566 * It is possible to come through here if the system
5567 * starts up with cards already inserted. Do nothing
5568 * and don't worry about it.
5569 */
5570 #ifdef PCIC_DEBUG
5571 pcic_err(pcic->dip, 5,
5572 "pcic%d: Odd card insertion indication on socket %d\n",
5573 ddi_get_instance(pcic->dip),
5574 sockp->pcs_socket);
5575 #endif
5576 }
5577 break;
5578
5579 default:
5580 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) {
5581 /*
5582 * Someone has started to insert a card so delay a while.
5583 */
5584 do_debounce = B_TRUE;
5585 break;
5586 }
5587 /*
5588 * Otherwise this is basically the same as not present
5589 * so fall through.
5590 */
5591
5592 /* FALLTHRU */
5593 case 0:
5594 if (sockp->pcs_flags & PCS_CARD_PRESENT) {
5595 if (pcic->pc_flags & PCF_CBPWRCTL) {
5596 pcic_putcb(pcic, CB_CONTROL, 0);
5597 } else {
5598 pcic_putb(pcic, sockp->pcs_socket,
5599 PCIC_POWER_CONTROL, 0);
5600 (void) pcic_getb(pcic, sockp->pcs_socket,
5601 PCIC_POWER_CONTROL);
5602 }
5603 #ifdef PCIC_DEBUG
5604 pcic_err(pcic->dip, 8, "Card removed\n");
5605 #endif
5606 sockp->pcs_flags &= ~PCS_CARD_PRESENT;
5607
5608 if (sockp->pcs_flags & PCS_CARD_IS16BIT) {
5609 sockp->pcs_flags &= ~PCS_CARD_IS16BIT;
5610 if (pcic_do_removal && pcic->pc_callback) {
5611 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg,
5612 PCE_CARD_REMOVAL, sockp->pcs_socket);
5613 }
5614 }
5615 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) {
5616 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS;
5617 sockp->pcs_flags |= PCS_CARD_CBREM;
5618 }
5619 sockp->pcs_flags |= PCS_CARD_REMOVED;
5620
5621 do_debounce = B_TRUE;
5622 }
5623 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) {
5624 if (sockp->pcs_flags & PCS_CARD_CBREM) {
5625 /*
5626 * Ensure that we do the unloading in the
5627 * debounce handler, that way we're not doing
5628 * nasty things in an interrupt handler. e.g.
5629 * a USB device will wait for data which will
5630 * obviously never come because we've
5631 * unplugged the device, but the wait will
5632 * wait forever because no interrupts can
5633 * come in...
5634 */
5635 #ifdef CARDBUS
5636 pcic_unload_cardbus(pcic, sockp);
5637 /* pcic_dump_all(pcic); */
5638 #endif
5639 sockp->pcs_flags &= ~PCS_CARD_CBREM;
5640 }
5641 sockp->pcs_flags &= ~PCS_CARD_REMOVED;
5642 }
5643 break;
5644 } /* switch */
5645
5646 if (do_debounce) {
5647 /*
5648 * Delay doing
5649 * anything for a while so that things can settle
5650 * down a little. Interrupts are already disabled.
5651 * Reset the state and we'll reevaluate the
5652 * whole kit 'n kaboodle when the timeout fires
5653 */
5654 #ifdef PCIC_DEBUG
5655 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for "
5656 "socket %d.%d\n",
5657 ddi_get_instance(pcic->dip),
5658 sockp->pcs_socket);
5659 #endif
5660 sockp->pcs_debounce_id =
5661 pcic_add_debqueue(sockp, debounce_time);
5662
5663 /*
5664 * We bug out here without re-enabling interrupts. They will
5665 * be re-enabled when the debounce timeout swings through
5666 * here.
5667 */
5668 return;
5669 }
5670
5671 /*
5672 * Turn on Card detect interrupts. Other interrupts will be
5673 * enabled during set_socket calls.
5674 *
5675 * Note that set_socket only changes interrupt settings when there
5676 * is a card present.
5677 */
5678 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT);
5679 irq |= PCIC_CD_DETECT;
5680 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq);
5681 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK);
5682
5683 /* Out from debouncing state */
5684 sockp->pcs_flags &= ~PCS_DEBOUNCING;
5685
5686 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n");
5687 }
5688
5689 /*
5690 * pcic_getb()
5691 * get an I/O byte based on the yardware decode method
5692 */
5693 static uint8_t
5694 pcic_getb(pcicdev_t *pcic, int socket, int reg)
5695 {
5696 int work;
5697
5698 #if defined(PCIC_DEBUG)
5699 if (pcic_debug == 0x7fff) {
5700 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n",
5701 (void *)pcic, socket, reg);
5702 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n",
5703 pcic->pc_io_type, (void *)pcic->handle,
5704 (void *)pcic->ioaddr);
5705 }
5706 #endif
5707
5708 switch (pcic->pc_io_type) {
5709 case PCIC_IO_TYPE_YENTA:
5710 return (ddi_get8(pcic->handle,
5711 pcic->ioaddr + CB_R2_OFFSET + reg));
5712 default:
5713 work = (socket * PCIC_SOCKET_1) | reg;
5714 ddi_put8(pcic->handle, pcic->ioaddr, work);
5715 return (ddi_get8(pcic->handle, pcic->ioaddr + 1));
5716 }
5717 }
5718
5719 static void
5720 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value)
5721 {
5722 int work;
5723
5724 #if defined(PCIC_DEBUG)
5725 if (pcic_debug == 0x7fff) {
5726 cmn_err(CE_CONT,
5727 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n",
5728 (void *)pcic, socket, reg, value);
5729 cmn_err(CE_CONT,
5730 "pcic_putb1: type=%d handle=%p ioaddr=%p \n",
5731 pcic->pc_io_type, (void *)pcic->handle,
5732 (void *)pcic->ioaddr);
5733 }
5734 #endif
5735
5736
5737 switch (pcic->pc_io_type) {
5738 case PCIC_IO_TYPE_YENTA:
5739 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg,
5740 value);
5741 break;
5742 default:
5743 work = (socket * PCIC_SOCKET_1) | reg;
5744 ddi_put8(pcic->handle, pcic->ioaddr, work);
5745 ddi_put8(pcic->handle, pcic->ioaddr + 1, value);
5746 break;
5747 }
5748 }
5749
5750 /*
5751 * chip identification functions
5752 */
5753
5754 /*
5755 * chip identification: Cirrus Logic PD6710/6720/6722
5756 */
5757 static int
5758 pcic_ci_cirrus(pcicdev_t *pcic)
5759 {
5760 int value1, value2;
5761
5762 /* Init the CL id mode */
5763 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO);
5764 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0);
5765 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO);
5766 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO);
5767
5768 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID &&
5769 (value2 & PCIC_CI_ID) == 0) {
5770 /* chip is a Cirrus Logic and not Intel */
5771 pcic->pc_type = PCIC_CL_PD6710;
5772 if (value1 & PCIC_CI_SLOTS)
5773 pcic->pc_chipname = PCIC_TYPE_PD6720;
5774 else
5775 pcic->pc_chipname = PCIC_TYPE_PD6710;
5776 /* now fine tune things just in case a 6722 */
5777 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0);
5778 if (value1 == 0) {
5779 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55);
5780 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH);
5781 if (value1 == 0x55) {
5782 pcic->pc_chipname = PCIC_TYPE_PD6722;
5783 pcic->pc_type = PCIC_CL_PD6722;
5784 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0);
5785 }
5786 }
5787 return (1);
5788 }
5789 return (0);
5790 }
5791
5792 /*
5793 * chip identification: Vadem (VG365/465/468/469)
5794 */
5795
5796 static void
5797 pcic_vadem_enable(pcicdev_t *pcic)
5798 {
5799 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1);
5800 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2);
5801 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg);
5802 }
5803
5804 static int
5805 pcic_ci_vadem(pcicdev_t *pcic)
5806 {
5807 int value;
5808
5809 pcic_vadem_enable(pcic);
5810 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION);
5811 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF);
5812 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) ==
5813 (value | PCIC_VADEM_D3) ||
5814 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) ==
5815 PCIC_VADEM_469) {
5816 int vadem, new;
5817 pcic_vadem_enable(pcic);
5818 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) &
5819 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV);
5820 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK);
5821 pcic_putb(pcic, 0, PCIC_VG_DMA, new);
5822 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION);
5823
5824 /* want to lock but leave mouse or other on */
5825 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem);
5826 switch (value & PCIC_REV_MASK) {
5827 case PCIC_VADEM_365:
5828 pcic->pc_chipname = PCIC_VG_365;
5829 pcic->pc_type = PCIC_VADEM;
5830 break;
5831 case PCIC_VADEM_465:
5832 pcic->pc_chipname = PCIC_VG_465;
5833 pcic->pc_type = PCIC_VADEM;
5834 pcic->pc_flags |= PCF_1SOCKET;
5835 break;
5836 case PCIC_VADEM_468:
5837 pcic->pc_chipname = PCIC_VG_468;
5838 pcic->pc_type = PCIC_VADEM;
5839 break;
5840 case PCIC_VADEM_469:
5841 pcic->pc_chipname = PCIC_VG_469;
5842 pcic->pc_type = PCIC_VADEM_VG469;
5843 break;
5844 }
5845 return (1);
5846 }
5847 return (0);
5848 }
5849
5850 /*
5851 * chip identification: Ricoh
5852 */
5853 static int
5854 pcic_ci_ricoh(pcicdev_t *pcic)
5855 {
5856 int value;
5857
5858 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT);
5859 switch (value) {
5860 case PCIC_RF_296:
5861 pcic->pc_type = PCIC_RICOH;
5862 pcic->pc_chipname = PCIC_TYPE_RF5C296;
5863 return (1);
5864 case PCIC_RF_396:
5865 pcic->pc_type = PCIC_RICOH;
5866 pcic->pc_chipname = PCIC_TYPE_RF5C396;
5867 return (1);
5868 }
5869 return (0);
5870 }
5871
5872
5873 /*
5874 * set up available address spaces in busra
5875 */
5876 static void
5877 pcic_init_assigned(dev_info_t *dip)
5878 {
5879 pcm_regs_t *pcic_avail_p;
5880 pci_regspec_t *pci_avail_p, *regs;
5881 int len, entries, rlen;
5882 dev_info_t *pdip;
5883
5884 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
5885 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) {
5886 /*
5887 * found "available" property at the cardbus/pcmcia node
5888 * need to translate address space entries from pcmcia
5889 * format to pci format
5890 */
5891 entries = len / sizeof (pcm_regs_t);
5892 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries,
5893 KM_SLEEP);
5894 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p,
5895 entries) == DDI_SUCCESS)
5896 (void) pci_resource_setup_avail(dip, pci_avail_p,
5897 entries);
5898 kmem_free(pcic_avail_p, len);
5899 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t));
5900 return;
5901 }
5902
5903 /*
5904 * "legacy" platforms will have "available" property in pci node
5905 */
5906 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) {
5907 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS,
5908 "available", (caddr_t)&pci_avail_p, &len) ==
5909 DDI_PROP_SUCCESS) {
5910 /* (void) pci_resource_setup(pdip); */
5911 kmem_free(pci_avail_p, len);
5912 break;
5913 }
5914 }
5915
5916 if (pdip == NULL) {
5917 int len;
5918 char bus_type[16] = "(unknown)";
5919 dev_info_t *par;
5920
5921 cmn_err(CE_CONT,
5922 "?pcic_init_assigned: no available property for pcmcia\n");
5923
5924 /*
5925 * This code is taken from pci_resource_setup() but does
5926 * not attempt to use the "available" property to populate
5927 * the ndi maps that are created.
5928 * The fact that we will actually
5929 * free some resource below (that was allocated by OBP)
5930 * should be enough to be going on with.
5931 */
5932 for (par = dip; par != NULL; par = ddi_get_parent(par)) {
5933 len = sizeof (bus_type);
5934
5935 if ((ddi_prop_op(DDI_DEV_T_ANY, par,
5936 PROP_LEN_AND_VAL_BUF,
5937 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS,
5938 "device_type",
5939 (caddr_t)&bus_type, &len) == DDI_SUCCESS) &&
5940 (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 ||
5941 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0))
5942 break;
5943 }
5944 if (par != NULL &&
5945 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS ||
5946 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS))
5947 par = NULL;
5948 } else {
5949 #ifdef CARDBUS
5950 cardbus_bus_range_t *bus_range;
5951 int k;
5952
5953 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range",
5954 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) {
5955 if (bus_range->lo != bus_range->hi)
5956 pcic_err(pdip, 9, "allowable bus range is "
5957 "%u->%u\n", bus_range->lo, bus_range->hi);
5958 else {
5959 pcic_err(pdip, 0,
5960 "!No spare PCI bus numbers, range is "
5961 "%u->%u, cardbus isn't usable\n",
5962 bus_range->lo, bus_range->hi);
5963 }
5964 kmem_free(bus_range, k);
5965 } else
5966 pcic_err(pdip, 0, "!No bus-range property seems to "
5967 "have been set up\n");
5968 #endif
5969 /*
5970 * Have a valid parent with the "available" property
5971 */
5972 (void) pci_resource_setup(pdip);
5973 }
5974
5975 if ((strcmp(ddi_get_name(dip), "pcma") == 0) &&
5976 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
5977 "assigned-addresses",
5978 (caddr_t)®s, &rlen) == DDI_SUCCESS) {
5979 ra_return_t ra;
5980
5981 /*
5982 * On the UltraBook IIi the ranges are assigned under
5983 * openboot. If we don't free them here the first I/O
5984 * space that can be used is up above 0x10000 which
5985 * doesn't work for this driver due to restrictions
5986 * on the PCI I/O addresses the controllers can cope with.
5987 * They are never going to be used by anything else
5988 * so free them up to the general pool. AG.
5989 */
5990 pcic_err(dip, 1, "Free assigned addresses\n");
5991
5992 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) ==
5993 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) &&
5994 regs[0].pci_size_low == 0x1000000) {
5995 ra.ra_addr_lo = regs[0].pci_phys_low;
5996 ra.ra_len = regs[0].pci_size_low;
5997 (void) pcmcia_free_mem(dip, &ra);
5998 }
5999 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) ==
6000 PCI_REG_ADDR_G(PCI_ADDR_IO)) &&
6001 (regs[1].pci_size_low == 0x8000 ||
6002 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */
6003 {
6004 ra.ra_addr_lo = regs[1].pci_phys_low;
6005 ra.ra_len = regs[1].pci_size_low;
6006 (void) pcmcia_free_io(dip, &ra);
6007 }
6008 kmem_free((caddr_t)regs, rlen);
6009 }
6010 }
6011
6012 /*
6013 * translate "available" from pcmcia format to pci format
6014 */
6015 static int
6016 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p,
6017 pci_regspec_t *pci_p, int entries)
6018 {
6019 int i, range_len, range_entries;
6020 pcic_ranges_t *pcic_range_p;
6021
6022 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges",
6023 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) {
6024 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: "
6025 "no ranges property for pcmcia\n");
6026 return (DDI_FAILURE);
6027 }
6028
6029 range_entries = range_len / sizeof (pcic_ranges_t);
6030
6031 /* for each "available" entry to be translated */
6032 for (i = 0; i < entries; i++, pcic_p++, pci_p++) {
6033 int j;
6034 pcic_ranges_t *range_p = pcic_range_p;
6035 pci_p->pci_phys_hi = -1u; /* default invalid value */
6036
6037 /* for each "ranges" entry to be searched */
6038 for (j = 0; j < range_entries; j++, range_p++) {
6039 uint64_t range_end = range_p->pcic_range_caddrlo +
6040 range_p->pcic_range_size;
6041 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len;
6042
6043 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) ||
6044 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) ||
6045 (range_end < avail_end))
6046 continue;
6047
6048 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi;
6049 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid;
6050 pci_p->pci_phys_low = range_p->pcic_range_paddrlo
6051 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo);
6052 pci_p->pci_size_hi = 0;
6053 pci_p->pci_size_low = pcic_p->phys_len;
6054 }
6055 }
6056 kmem_free(pcic_range_p, range_len);
6057 return (DDI_SUCCESS);
6058 }
6059
6060 static int
6061 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred)
6062 {
6063 #ifdef CARDBUS
6064 if (cardbus_is_cb_minor(*dev))
6065 return (cardbus_open(dev, flag, otyp, cred));
6066 #endif
6067 return (EINVAL);
6068 }
6069
6070 static int
6071 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred)
6072 {
6073 #ifdef CARDBUS
6074 if (cardbus_is_cb_minor(dev))
6075 return (cardbus_close(dev, flag, otyp, cred));
6076 #endif
6077 return (EINVAL);
6078 }
6079
6080 static int
6081 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred,
6082 int *rval)
6083 {
6084 #ifdef CARDBUS
6085 if (cardbus_is_cb_minor(dev))
6086 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval));
6087 #endif
6088 return (EINVAL);
6089 }
6090
6091
6092 static boolean_t
6093 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp)
6094 {
6095 uint32_t present_state;
6096 dev_info_t *dip = pcic->dip;
6097 set_socket_t s;
6098 get_socket_t g;
6099 boolean_t retval;
6100 unsigned vccLevel;
6101
6102 pcic_err(dip, 8, "entering pcic_load_cardbus\n");
6103
6104 pcic_mutex_exit(&pcic->pc_lock);
6105
6106 bzero(&s, sizeof (set_socket_t));
6107 s.socket = sockp->pcs_socket;
6108 s.SCIntMask = SBM_CD|SBM_RDYBSY;
6109 s.IFType = IF_CARDBUS;
6110 s.State = (unsigned)~0;
6111
6112 present_state = pcic_getcb(pcic, CB_PRESENT_STATE);
6113 if (present_state & PCIC_VCC_3VCARD)
6114 s.VccLevel = PCIC_VCC_3VLEVEL;
6115 else if (present_state & PCIC_VCC_5VCARD)
6116 s.VccLevel = PCIC_VCC_5VLEVEL;
6117 else {
6118 cmn_err(CE_CONT,
6119 "pcic_load_cardbus: unsupported card voltage\n");
6120 goto failure;
6121 }
6122 vccLevel = s.VccLevel;
6123 s.Vpp1Level = s.Vpp2Level = 0;
6124
6125 if (pcic_set_socket(dip, &s) != SUCCESS)
6126 goto failure;
6127
6128 if (pcic_reset_socket(dip, sockp->pcs_socket,
6129 RESET_MODE_CARD_ONLY) != SUCCESS)
6130 goto failure;
6131
6132 bzero(&g, sizeof (get_socket_t));
6133 g.socket = sockp->pcs_socket;
6134 if (pcic_get_socket(dip, &g) != SUCCESS)
6135 goto failure;
6136
6137 bzero(&s, sizeof (set_socket_t));
6138 s.socket = sockp->pcs_socket;
6139 s.SCIntMask = SBM_CD;
6140 s.IREQRouting = g.IRQRouting;
6141 s.IFType = g.IFType;
6142 s.CtlInd = g.CtlInd;
6143 s.State = (unsigned)~0;
6144 s.VccLevel = vccLevel;
6145 s.Vpp1Level = s.Vpp2Level = 0;
6146
6147 retval = pcic_set_socket(dip, &s);
6148 pcmcia_cb_resumed(s.socket);
6149 if (retval != SUCCESS)
6150 goto failure;
6151
6152 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base);
6153 goto exit;
6154
6155 failure:
6156 retval = B_FALSE;
6157
6158 exit:
6159 pcic_mutex_enter(&pcic->pc_lock);
6160 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n",
6161 retval ? "success" : "failure");
6162 return (retval);
6163 }
6164
6165 static void
6166 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp)
6167 {
6168 dev_info_t *dip = pcic->dip;
6169 set_socket_t s;
6170
6171 pcic_mutex_exit(&pcic->pc_lock);
6172
6173 cardbus_unload_cardbus(dip);
6174
6175 bzero(&s, sizeof (set_socket_t));
6176 s.socket = sockp->pcs_socket;
6177 s.SCIntMask = SBM_CD|SBM_RDYBSY;
6178 s.IREQRouting = 0;
6179 s.IFType = IF_MEMORY;
6180 s.CtlInd = 0;
6181 s.State = 0;
6182 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0;
6183
6184 (void) pcic_set_socket(dip, &s);
6185
6186 pcic_mutex_enter(&pcic->pc_lock);
6187 }
6188
6189 static uint32_t
6190 pcic_getcb(pcicdev_t *pcic, int reg)
6191 {
6192 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA);
6193
6194 return (ddi_get32(pcic->handle,
6195 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg)));
6196 }
6197
6198 static void
6199 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value)
6200 {
6201 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA);
6202
6203 ddi_put32(pcic->handle,
6204 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value);
6205 }
6206
6207 static void
6208 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq)
6209 {
6210 uint8_t value;
6211 uint16_t brdgctl;
6212
6213 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK;
6214 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq);
6215
6216 switch (pcic->pc_type) {
6217 case PCIC_INTEL_i82092:
6218 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ,
6219 PCIC_82092_INT_ENABLE);
6220 break;
6221 case PCIC_O2_OZ6912:
6222 value = pcic_getb(pcic, 0, PCIC_CENTDMA);
6223 value |= 0x8;
6224 pcic_putb(pcic, 0, PCIC_CENTDMA, value);
6225 break;
6226 case PCIC_CL_PD6832:
6227 case PCIC_TI_PCI1250:
6228 case PCIC_TI_PCI1221:
6229 case PCIC_TI_PCI1225:
6230 case PCIC_TI_PCI1410:
6231 case PCIC_ENE_1410:
6232 case PCIC_TI_PCI1510:
6233 case PCIC_TI_PCI1520:
6234 case PCIC_TI_PCI1420:
6235 case PCIC_ENE_1420:
6236 /* route card functional interrupts to PCI interrupts */
6237 brdgctl = ddi_get16(pcic->cfg_handle,
6238 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL));
6239 pcic_err(NULL, 1,
6240 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n",
6241 PCI_CBUS_BRIDGE_CTRL, brdgctl);
6242 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK;
6243 ddi_put16(pcic->cfg_handle,
6244 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL),
6245 brdgctl);
6246 /* Flush the write */
6247 (void) ddi_get16(pcic->cfg_handle,
6248 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL));
6249 break;
6250 default:
6251 break;
6252 }
6253 }
6254
6255 static void
6256 pcic_disable_io_intr(pcicdev_t *pcic, int socket)
6257 {
6258 uint8_t value;
6259 uint16_t brdgctl;
6260
6261 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK;
6262 pcic_putb(pcic, socket, PCIC_INTERRUPT, value);
6263
6264 switch (pcic->pc_type) {
6265 case PCIC_INTEL_i82092:
6266 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ,
6267 PCIC_82092_INT_DISABLE);
6268 break;
6269 case PCIC_O2_OZ6912:
6270 value = pcic_getb(pcic, 0, PCIC_CENTDMA);
6271 value &= ~0x8;
6272 pcic_putb(pcic, 0, PCIC_CENTDMA, value);
6273 /* Flush the write */
6274 (void) pcic_getb(pcic, 0, PCIC_CENTDMA);
6275 break;
6276 case PCIC_CL_PD6832:
6277 case PCIC_TI_PCI1250:
6278 case PCIC_TI_PCI1221:
6279 case PCIC_TI_PCI1225:
6280 case PCIC_TI_PCI1410:
6281 case PCIC_ENE_1410:
6282 case PCIC_TI_PCI1510:
6283 case PCIC_TI_PCI1520:
6284 case PCIC_TI_PCI1420:
6285 case PCIC_ENE_1420:
6286 /*
6287 * This maps I/O interrupts to ExCA which
6288 * have been turned off by the write to
6289 * PCIC_INTERRUPT above. It would appear to
6290 * be the only way to actually turn I/O Ints off
6291 * while retaining CS Ints.
6292 */
6293 brdgctl = ddi_get16(pcic->cfg_handle,
6294 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL));
6295 pcic_err(NULL, 1,
6296 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n",
6297 PCI_CBUS_BRIDGE_CTRL, brdgctl);
6298 brdgctl |= PCIC_BRDGCTL_INTR_MASK;
6299 ddi_put16(pcic->cfg_handle,
6300 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL),
6301 brdgctl);
6302 /* Flush the write */
6303 (void) ddi_get16(pcic->cfg_handle,
6304 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL));
6305 break;
6306 default:
6307 break;
6308 }
6309 }
6310
6311 static void
6312 pcic_cb_enable_intr(dev_info_t *dip)
6313 {
6314 anp_t *anp = ddi_get_driver_private(dip);
6315 pcicdev_t *pcic = anp->an_private;
6316
6317 mutex_enter(&pcic->pc_lock);
6318 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq);
6319 mutex_exit(&pcic->pc_lock);
6320 }
6321
6322 static void
6323 pcic_cb_disable_intr(dev_info_t *dip)
6324 {
6325 anp_t *anp = ddi_get_driver_private(dip);
6326 pcicdev_t *pcic = anp->an_private;
6327
6328 mutex_enter(&pcic->pc_lock);
6329 pcic_disable_io_intr(pcic, 0);
6330 mutex_exit(&pcic->pc_lock);
6331 }
6332
6333 static int
6334 log_pci_cfg_err(ushort_t e, int bridge_secondary)
6335 {
6336 int nerr = 0;
6337 if (e & PCI_STAT_PERROR) {
6338 nerr++;
6339 cmn_err(CE_CONT, "detected parity error.\n");
6340 }
6341 if (e & PCI_STAT_S_SYSERR) {
6342 nerr++;
6343 if (bridge_secondary)
6344 cmn_err(CE_CONT, "received system error.\n");
6345 else
6346 cmn_err(CE_CONT, "signalled system error.\n");
6347 }
6348 if (e & PCI_STAT_R_MAST_AB) {
6349 nerr++;
6350 cmn_err(CE_CONT, "received master abort.\n");
6351 }
6352 if (e & PCI_STAT_R_TARG_AB)
6353 cmn_err(CE_CONT, "received target abort.\n");
6354 if (e & PCI_STAT_S_TARG_AB)
6355 cmn_err(CE_CONT, "signalled target abort\n");
6356 if (e & PCI_STAT_S_PERROR) {
6357 nerr++;
6358 cmn_err(CE_CONT, "signalled parity error\n");
6359 }
6360 return (nerr);
6361 }
6362
6363 #if defined(__sparc)
6364 static int
6365 pcic_fault(enum pci_fault_ops op, void *arg)
6366 {
6367 pcicdev_t *pcic = (pcicdev_t *)arg;
6368 ushort_t pci_cfg_stat =
6369 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT);
6370 ushort_t pci_cfg_sec_stat =
6371 pci_config_get16(pcic->cfg_handle, 0x16);
6372 char nm[24];
6373 int nerr = 0;
6374
6375 cardbus_dump_pci_config(pcic->dip);
6376
6377 switch (op) {
6378 case FAULT_LOG:
6379 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip),
6380 ddi_get_instance(pcic->dip));
6381
6382 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm);
6383 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat);
6384 nerr += log_pci_cfg_err(pci_cfg_stat, 0);
6385 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat);
6386 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1);
6387 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm);
6388 return (nerr);
6389 case FAULT_POKEFINI:
6390 case FAULT_RESET:
6391 pci_config_put16(pcic->cfg_handle,
6392 PCI_CONF_STAT, pci_cfg_stat);
6393 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat);
6394 break;
6395 case FAULT_POKEFLT:
6396 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR))
6397 return (1);
6398 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB))
6399 return (1);
6400 break;
6401 default:
6402 break;
6403 }
6404 return (DDI_SUCCESS);
6405 }
6406 #endif
6407
6408 static void
6409 pcic_do_resume(pcicdev_t *pcic)
6410 {
6411 int i, interrupt;
6412 uint8_t cfg;
6413
6414
6415 #if defined(PCIC_DEBUG)
6416 pcic_err(NULL, 6, "pcic_do_resume(): entered\n");
6417 #endif
6418
6419 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */
6420 for (i = 0; i < pcic->pc_numsockets; i++) {
6421 /* Enable interrupts on PCI if needs be */
6422 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT);
6423 if (pcic->pc_flags & PCF_USE_SMI)
6424 interrupt |= PCIC_INTR_ENABLE;
6425 pcic_putb(pcic, i, PCIC_INTERRUPT,
6426 PCIC_RESET | interrupt);
6427 pcic->pc_sockets[i].pcs_debounce_id =
6428 pcic_add_debqueue(&pcic->pc_sockets[i],
6429 drv_usectohz(pcic_debounce_time));
6430 }
6431 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */
6432 if (pcic_do_pcmcia_sr)
6433 (void) pcmcia_wait_insert(pcic->dip);
6434 /*
6435 * The CardBus controller may be in RESET state after the
6436 * system is resumed from sleeping. The RESET bit is in
6437 * the Bridge Control register. This is true for all(TI,
6438 * Toshiba ToPIC95/97, RICOH, and O2Micro) CardBus
6439 * controllers. Need to clear the RESET bit explicitly.
6440 */
6441 cfg = ddi_get8(pcic->cfg_handle,
6442 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
6443 if (cfg & (1<<6)) {
6444 cfg &= ~(1<<6);
6445 ddi_put8(pcic->cfg_handle,
6446 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG,
6447 cfg);
6448 cfg = ddi_get8(pcic->cfg_handle,
6449 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG);
6450 if (cfg & (1<<6)) {
6451 pcic_err(pcic->dip, 1,
6452 "Failed to take pcic out of reset");
6453 }
6454 }
6455
6456 }
6457
6458 static void
6459 pcic_debounce(pcic_socket_t *pcs)
6460 {
6461 uint8_t status, stschng;
6462
6463 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock);
6464 pcs->pcs_flags &= ~PCS_STARTING;
6465 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket,
6466 PCIC_CARD_STATUS_CHANGE);
6467 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket,
6468 PCIC_INTERFACE_STATUS);
6469 #ifdef PCIC_DEBUG
6470 pcic_err(pcs->pcs_pcic->dip, 8,
6471 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x "
6472 "chg 0x%x flg 0x%x\n",
6473 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket,
6474 status, stschng, pcs->pcs_flags);
6475 #endif
6476
6477 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE,
6478 PCIC_CD_DETECT);
6479 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status);
6480 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock);
6481 }
6482
6483 static void
6484 pcic_deb_thread()
6485 {
6486 callb_cpr_t cprinfo;
6487 struct debounce *debp;
6488 clock_t lastt;
6489
6490 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx,
6491 callb_generic_cpr, "pcic debounce thread");
6492 mutex_enter(&pcic_deb_mtx);
6493 while (pcic_deb_threadid) {
6494 while (pcic_deb_queue) {
6495 #ifdef PCIC_DEBUG
6496 pcic_dump_debqueue("Thread");
6497 #endif
6498 debp = pcic_deb_queue;
6499 (void) drv_getparm(LBOLT, &lastt);
6500 if (lastt >= debp->expire) {
6501 pcic_deb_queue = debp->next;
6502 mutex_exit(&pcic_deb_mtx);
6503 pcic_debounce(debp->pcs);
6504 mutex_enter(&pcic_deb_mtx);
6505 kmem_free(debp, sizeof (*debp));
6506 } else {
6507 (void) cv_timedwait(&pcic_deb_cv,
6508 &pcic_deb_mtx, debp->expire);
6509 }
6510 }
6511 CALLB_CPR_SAFE_BEGIN(&cprinfo);
6512 cv_wait(&pcic_deb_cv, &pcic_deb_mtx);
6513 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx);
6514 }
6515 pcic_deb_threadid = (kthread_t *)1;
6516 cv_signal(&pcic_deb_cv);
6517 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */
6518 thread_exit();
6519 }
6520
6521 static void *
6522 pcic_add_debqueue(pcic_socket_t *pcs, int clocks)
6523 {
6524 clock_t lbolt;
6525 struct debounce *dbp, **dbpp = &pcic_deb_queue;
6526
6527 (void) drv_getparm(LBOLT, &lbolt);
6528 dbp = kmem_alloc(sizeof (struct debounce), KM_SLEEP);
6529
6530 dbp->expire = lbolt + clocks;
6531 dbp->pcs = pcs;
6532 mutex_enter(&pcic_deb_mtx);
6533 while (*dbpp) {
6534 if (dbp->expire > (*dbpp)->expire)
6535 dbpp = &((*dbpp)->next);
6536 else
6537 break;
6538 }
6539 dbp->next = *dbpp;
6540 *dbpp = dbp;
6541 #ifdef PCIC_DEBUG
6542 pcic_dump_debqueue("Add");
6543 #endif
6544 cv_signal(&pcic_deb_cv);
6545 mutex_exit(&pcic_deb_mtx);
6546 return (dbp);
6547 }
6548
6549 static void
6550 pcic_rm_debqueue(void *id)
6551 {
6552 struct debounce *dbp, **dbpp = &pcic_deb_queue;
6553
6554 dbp = (struct debounce *)id;
6555 mutex_enter(&pcic_deb_mtx);
6556 while (*dbpp) {
6557 if (*dbpp == dbp) {
6558 *dbpp = dbp->next;
6559 kmem_free(dbp, sizeof (*dbp));
6560 #ifdef PCIC_DEBUG
6561 pcic_dump_debqueue("Remove");
6562 #endif
6563 cv_signal(&pcic_deb_cv);
6564 mutex_exit(&pcic_deb_mtx);
6565 return;
6566 }
6567 dbpp = &((*dbpp)->next);
6568 }
6569 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id);
6570 mutex_exit(&pcic_deb_mtx);
6571 }
6572
6573
6574 static int pcic_powerdelay = 0;
6575
6576 static int
6577 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel)
6578 {
6579 int ind, value, orig_pwrctl;
6580
6581 /* power setup -- if necessary */
6582 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
6583
6584 #if defined(PCIC_DEBUG)
6585 pcic_err(pcic->dip, 6,
6586 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n",
6587 socket, powerlevel, orig_pwrctl);
6588 #endif
6589 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */
6590 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) |
6591 (orig_pwrctl & POWER_OUTPUT_ENABLE);
6592 if (powerlevel != orig_pwrctl) {
6593 if (powerlevel & ~POWER_OUTPUT_ENABLE) {
6594 int ifs;
6595 /*
6596 * set power to socket
6597 * note that the powerlevel was calculated earlier
6598 */
6599 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel);
6600 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
6601
6602 /*
6603 * this second write to the power control register
6604 * is needed to resolve a problem on
6605 * the IBM ThinkPad 750
6606 * where the first write doesn't latch.
6607 * The second write appears to always work and
6608 * doesn't hurt the operation of other chips
6609 * so we can just use it -- this is good since we can't
6610 * determine what chip the 750 actually uses
6611 * (I suspect an early Ricoh).
6612 */
6613 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel);
6614
6615 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
6616 pcic_mswait(pcic, socket, pcic_powerdelay);
6617 #if defined(PCIC_DEBUG)
6618 pcic_err(pcic->dip, 8,
6619 "\tpowerlevel reg = %x (ifs %x)\n",
6620 value, pcic_getb(pcic, socket,
6621 PCIC_INTERFACE_STATUS));
6622 pcic_err(pcic->dip, 8,
6623 "CBus regs: PS 0x%x, Control 0x%x\n",
6624 pcic_getcb(pcic, CB_PRESENT_STATE),
6625 pcic_getcb(pcic, CB_CONTROL));
6626 #endif
6627 /*
6628 * since power was touched, make sure it says it
6629 * is on. This lets it become stable.
6630 */
6631 for (ind = 0; ind < 20; ind++) {
6632 ifs = pcic_getb(pcic, socket,
6633 PCIC_INTERFACE_STATUS);
6634 if (ifs & PCIC_POWER_ON)
6635 break;
6636 else {
6637 pcic_putb(pcic, socket,
6638 PCIC_POWER_CONTROL, 0);
6639 (void) pcic_getb(pcic, socket,
6640 PCIC_POWER_CONTROL);
6641 pcic_mswait(pcic, socket, 40);
6642 if (ind == 10) {
6643 pcic_putcb(pcic, CB_EVENT_FORCE,
6644 CB_EF_CVTEST);
6645 pcic_mswait(pcic, socket, 100);
6646 }
6647 pcic_putb(pcic, socket,
6648 PCIC_POWER_CONTROL,
6649 powerlevel & ~POWER_OUTPUT_ENABLE);
6650 (void) pcic_getb(pcic, socket,
6651 PCIC_POWER_CONTROL);
6652 pcic_mswait(pcic, socket,
6653 pcic_powerdelay);
6654 pcic_putb(pcic, socket,
6655 PCIC_POWER_CONTROL, powerlevel);
6656 (void) pcic_getb(pcic, socket,
6657 PCIC_POWER_CONTROL);
6658 pcic_mswait(pcic, socket,
6659 pcic_powerdelay);
6660 }
6661 }
6662
6663 if (!(ifs & PCIC_POWER_ON)) {
6664 cmn_err(CE_WARN,
6665 "pcic socket %d: Power didn't get turned"
6666 "on!\nif status 0x%x pwrc 0x%x(x%x) "
6667 "misc1 0x%x igc 0x%x ind %d\n",
6668 socket, ifs,
6669 pcic_getb(pcic, socket, PCIC_POWER_CONTROL),
6670 orig_pwrctl,
6671 pcic_getb(pcic, socket, PCIC_MISC_CTL_1),
6672 pcic_getb(pcic, socket, PCIC_INTERRUPT),
6673 ind);
6674 return (BAD_VCC);
6675 }
6676 #if defined(PCIC_DEBUG)
6677 pcic_err(pcic->dip, 8,
6678 "\tind = %d, if status %x pwrc 0x%x "
6679 "misc1 0x%x igc 0x%x\n",
6680 ind, ifs,
6681 pcic_getb(pcic, socket, PCIC_POWER_CONTROL),
6682 pcic_getb(pcic, socket, PCIC_MISC_CTL_1),
6683 pcic_getb(pcic, socket, PCIC_INTERRUPT));
6684 #endif
6685 } else {
6686 /* explicitly turned off the power */
6687 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel);
6688 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL);
6689 }
6690 }
6691 return (SUCCESS);
6692 }
6693
6694 static int pcic_cbdoreset_during_poweron = 1;
6695 static int
6696 pcic_cbus_powerctl(pcicdev_t *pcic, int socket)
6697 {
6698 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps;
6699 int ind, iobits;
6700 pcic_socket_t *sockp = &pcic->pc_sockets[socket];
6701
6702 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE);
6703
6704 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10;
6705 cbctl |= pcic_cbv_levels[ind];
6706
6707 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10;
6708 cbctl |= (pcic_cbv_levels[ind]<<4);
6709
6710 orig_cbctl = pcic_getcb(pcic, CB_CONTROL);
6711
6712 #if defined(PCIC_DEBUG)
6713 pcic_err(pcic->dip, 6,
6714 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d "
6715 "cbctl 0x%x->0x%x\n",
6716 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl);
6717 #endif
6718 if (cbctl != orig_cbctl) {
6719 if (pcic_cbdoreset_during_poweron &&
6720 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) {
6721 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT);
6722 pcic_putb(pcic, socket, PCIC_INTERRUPT,
6723 iobits & ~PCIC_RESET);
6724 }
6725 pcic_putcb(pcic, CB_CONTROL, cbctl);
6726
6727 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) {
6728 pcic_mswait(pcic, socket, pcic_powerdelay);
6729 return (SUCCESS);
6730 }
6731 for (ind = 0; ind < 20; ind++) {
6732 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT);
6733
6734 if (cbstev & CB_SE_POWER_CYCLE) {
6735
6736 /*
6737 * delay 400 ms: though the standard defines that the Vcc
6738 * set-up time is 20 ms, some PC-Card bridge requires longer
6739 * duration.
6740 * Note: We should check the status AFTER the delay to give time
6741 * for things to stabilize.
6742 */
6743 pcic_mswait(pcic, socket, 400);
6744
6745 cbps = pcic_getcb(pcic, CB_PRESENT_STATE);
6746 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) {
6747 /* break; */
6748 cmn_err(CE_WARN, "cbus_powerctl: power off??\n");
6749 }
6750 if (cbctl & CB_PS_BADVCC) {
6751 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n");
6752 break;
6753 }
6754
6755 #if defined(PCIC_DEBUG)
6756 pcic_err(pcic->dip, 8,
6757 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)",
6758 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE),
6759 cbctl, orig_cbctl);
6760 #endif
6761 if (pcic_cbdoreset_during_poweron &&
6762 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) {
6763 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits);
6764 }
6765 return (SUCCESS);
6766 }
6767 pcic_mswait(pcic, socket, 40);
6768 }
6769 if (pcic_cbdoreset_during_poweron &&
6770 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) {
6771 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits);
6772 }
6773 cmn_err(CE_WARN,
6774 "pcic socket %d: Power didn't get turned on/off!\n"
6775 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) "
6776 "vcc %d vpp1 %d", socket, cbstev,
6777 pcic_getcb(pcic, CB_PRESENT_STATE),
6778 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1);
6779 return (BAD_VCC);
6780 }
6781 return (SUCCESS);
6782 }
6783
6784 static int pcic_do_pprintf = 0;
6785
6786 static void
6787 pcic_dump_debqueue(char *msg)
6788 {
6789 struct debounce *debp = pcic_deb_queue;
6790 clock_t lbolt;
6791
6792 (void) drv_getparm(LBOLT, &lbolt);
6793 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" :
6794 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt);
6795 while (debp) {
6796 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n",
6797 (void *) debp, (int)debp->expire, (void *) debp->next,
6798 debp->pcs->pcs_debounce_id);
6799 debp = debp->next;
6800 }
6801 }
6802
6803
6804 /* PRINTFLIKE3 */
6805 static void
6806 pcic_err(dev_info_t *dip, int level, const char *fmt, ...)
6807 {
6808 if (pcic_debug && (level <= pcic_debug)) {
6809 va_list adx;
6810 int instance;
6811 char buf[256];
6812 const char *name;
6813 #if !defined(PCIC_DEBUG)
6814 int ce;
6815 char qmark = 0;
6816
6817 if (level <= 3)
6818 ce = CE_WARN;
6819 else
6820 ce = CE_CONT;
6821 if (level == 4)
6822 qmark = 1;
6823 #endif
6824
6825 if (dip) {
6826 instance = ddi_get_instance(dip);
6827 /* name = ddi_binding_name(dip); */
6828 name = ddi_driver_name(dip);
6829 } else {
6830 instance = 0;
6831 name = "";
6832 }
6833
6834 va_start(adx, fmt);
6835 (void) vsprintf(buf, fmt, adx);
6836 va_end(adx);
6837
6838 #if defined(PCIC_DEBUG)
6839 if (pcic_do_pprintf) {
6840 if (dip) {
6841 if (instance >= 0)
6842 prom_printf("%s(%d),0x%p: %s", name,
6843 instance, (void *)dip, buf);
6844 else
6845 prom_printf("%s,0x%p: %s",
6846 name, (void *)dip, buf);
6847 } else
6848 prom_printf(buf);
6849 } else {
6850 if (dip) {
6851 if (instance >= 0)
6852 cmn_err(CE_CONT, "%s(%d),0x%p: %s",
6853 name, instance, (void *) dip, buf);
6854 else
6855 cmn_err(CE_CONT, "%s,0x%p: %s",
6856 name, (void *) dip, buf);
6857 } else
6858 cmn_err(CE_CONT, buf);
6859 }
6860 #else
6861 if (dip)
6862 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name,
6863 instance, buf);
6864 else
6865 cmn_err(ce, qmark ? "?%s" : buf, buf);
6866 #endif
6867 }
6868 }