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4431 igb support for I354
4616 igb has uninitialized kstats
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--- old/usr/src/uts/common/io/igb/igb_sw.h
+++ new/usr/src/uts/common/io/igb/igb_sw.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
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18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 + * Copyright 2014 Pluribus Networks Inc.
28 29 */
29 30
30 31 #ifndef _IGB_SW_H
31 32 #define _IGB_SW_H
32 33
33 34 #ifdef __cplusplus
34 35 extern "C" {
35 36 #endif
36 37
37 38 #include <sys/types.h>
38 39 #include <sys/conf.h>
39 40 #include <sys/debug.h>
40 41 #include <sys/stropts.h>
41 42 #include <sys/stream.h>
42 43 #include <sys/strsun.h>
43 44 #include <sys/strlog.h>
44 45 #include <sys/kmem.h>
45 46 #include <sys/stat.h>
46 47 #include <sys/kstat.h>
47 48 #include <sys/modctl.h>
48 49 #include <sys/errno.h>
49 50 #include <sys/dlpi.h>
50 51 #include <sys/mac_provider.h>
51 52 #include <sys/mac_ether.h>
52 53 #include <sys/vlan.h>
53 54 #include <sys/ddi.h>
54 55 #include <sys/sunddi.h>
55 56 #include <sys/pci.h>
56 57 #include <sys/pcie.h>
57 58 #include <sys/sdt.h>
58 59 #include <sys/ethernet.h>
59 60 #include <sys/pattr.h>
60 61 #include <sys/strsubr.h>
61 62 #include <sys/netlb.h>
62 63 #include <sys/random.h>
63 64 #include <inet/common.h>
64 65 #include <inet/tcp.h>
65 66 #include <inet/ip.h>
66 67 #include <inet/mi.h>
67 68 #include <inet/nd.h>
68 69 #include <sys/ddifm.h>
69 70 #include <sys/fm/protocol.h>
70 71 #include <sys/fm/util.h>
71 72 #include <sys/fm/io/ddi.h>
72 73 #include "e1000_api.h"
73 74 #include "e1000_82575.h"
74 75
75 76
76 77 #define MODULE_NAME "igb" /* module name */
77 78
78 79 #define IGB_SUCCESS DDI_SUCCESS
79 80 #define IGB_FAILURE DDI_FAILURE
80 81
81 82 #define IGB_UNKNOWN 0x00
82 83 #define IGB_INITIALIZED 0x01
83 84 #define IGB_STARTED 0x02
84 85 #define IGB_SUSPENDED 0x04
85 86 #define IGB_STALL 0x08
86 87 #define IGB_ERROR 0x80
87 88
88 89 #define IGB_RX_STOPPED 0x1
89 90
90 91 #define IGB_INTR_NONE 0
91 92 #define IGB_INTR_MSIX 1
92 93 #define IGB_INTR_MSI 2
93 94 #define IGB_INTR_LEGACY 3
94 95
95 96 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */
96 97 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */
97 98
98 99 #define IGB_NO_POLL -1
99 100 #define IGB_NO_FREE_SLOT -1
100 101
101 102 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES
102 103 #define MCAST_ALLOC_COUNT 256
103 104 #define MAX_COOKIE 18
104 105 #define MIN_NUM_TX_DESC 2
105 106
106 107 /*
107 108 * Number of settings for interrupt throttle rate (ITR). There is one of
108 109 * these per msi-x vector and it needs to be the maximum of all silicon
109 110 * types supported by this driver.
110 111 */
111 112 #define MAX_NUM_EITR 25
112 113
113 114 /*
114 115 * Maximum values for user configurable parameters
115 116 */
116 117 #define MAX_TX_RING_SIZE 4096
117 118 #define MAX_RX_RING_SIZE 4096
118 119 #define MAX_RX_GROUP_NUM 4
119 120
120 121 #define MAX_MTU 9000
121 122 #define MAX_RX_LIMIT_PER_INTR 4096
122 123
123 124 #define MAX_RX_COPY_THRESHOLD 9216
124 125 #define MAX_TX_COPY_THRESHOLD 9216
125 126 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE
126 127 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE
127 128 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE
128 129 #define MAX_MCAST_NUM 8192
129 130
130 131 /*
131 132 * Minimum values for user configurable parameters
132 133 */
133 134 #define MIN_TX_RING_SIZE 64
134 135 #define MIN_RX_RING_SIZE 64
135 136 #define MIN_RX_GROUP_NUM 1
136 137
137 138 #define MIN_MTU ETHERMIN
138 139 #define MIN_RX_LIMIT_PER_INTR 16
139 140
140 141 #define MIN_RX_COPY_THRESHOLD 0
141 142 #define MIN_TX_COPY_THRESHOLD 0
142 143 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC
143 144 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
144 145 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC
145 146 #define MIN_MCAST_NUM 8
146 147
147 148 /*
148 149 * Default values for user configurable parameters
149 150 */
150 151 #define DEFAULT_TX_RING_SIZE 512
151 152 #define DEFAULT_RX_RING_SIZE 512
152 153 #define DEFAULT_RX_GROUP_NUM 1
153 154
154 155 #define DEFAULT_MTU ETHERMTU
155 156 #define DEFAULT_RX_LIMIT_PER_INTR 256
156 157
157 158 #define DEFAULT_RX_COPY_THRESHOLD 128
158 159 #define DEFAULT_TX_COPY_THRESHOLD 512
159 160 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1)
160 161 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
161 162 #define DEFAULT_TX_RESCHED_THRESHOLD 128
162 163 #define DEFAULT_TX_RESCHED_THRESHOLD_LOW 32
163 164 #define DEFAULT_MCAST_NUM 4096
164 165
165 166 #define IGB_LSO_MAXLEN 65535
166 167
167 168 #define TX_DRAIN_TIME 200
168 169 #define RX_DRAIN_TIME 200
169 170
170 171 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */
171 172
172 173 /*
173 174 * Defined for IP header alignment.
174 175 */
175 176 #define IPHDR_ALIGN_ROOM 2
176 177
177 178 /*
178 179 * Bit flags for attach_progress
179 180 */
180 181 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
181 182 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
182 183 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
183 184 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
184 185 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
185 186 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
186 187 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
187 188 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */
188 189 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
189 190 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
190 191 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
191 192 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */
192 193
193 194 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap"
194 195 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap"
195 196 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap"
196 197 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap"
197 198 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap"
198 199 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap"
199 200 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap"
200 201 #define PROP_DEFAULT_MTU "default_mtu"
201 202 #define PROP_FLOW_CONTROL "flow_control"
202 203 #define PROP_TX_RING_SIZE "tx_ring_size"
203 204 #define PROP_RX_RING_SIZE "rx_ring_size"
204 205 #define PROP_MR_ENABLE "mr_enable"
205 206 #define PROP_RX_GROUP_NUM "rx_group_number"
206 207
207 208 #define PROP_INTR_FORCE "intr_force"
208 209 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
209 210 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
210 211 #define PROP_LSO_ENABLE "lso_enable"
211 212 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
212 213 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
213 214 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
214 215 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
215 216 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold"
216 217 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold"
217 218 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr"
218 219 #define PROP_INTR_THROTTLING "intr_throttling"
219 220 #define PROP_MCAST_MAX_NUM "mcast_max_num"
220 221
221 222 #define IGB_LB_NONE 0
222 223 #define IGB_LB_EXTERNAL 1
223 224 #define IGB_LB_INTERNAL_PHY 3
224 225 #define IGB_LB_INTERNAL_SERDES 4
225 226
226 227 enum ioc_reply {
227 228 IOC_INVAL = -1, /* bad, NAK with EINVAL */
228 229 IOC_DONE, /* OK, reply sent */
229 230 IOC_ACK, /* OK, just send ACK */
230 231 IOC_REPLY /* OK, just send reply */
231 232 };
232 233
233 234 /*
234 235 * For s/w context extraction from a tx frame
235 236 */
236 237 #define TX_CXT_SUCCESS 0
237 238 #define TX_CXT_E_LSO_CSUM (-1)
238 239 #define TX_CXT_E_ETHER_TYPE (-2)
239 240
240 241 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
241 242 0, 0, (flag)))
242 243
243 244 /*
244 245 * Defined for ring index operations
245 246 * ASSERT(index < limit)
246 247 * ASSERT(step < limit)
247 248 * ASSERT(index1 < limit)
248 249 * ASSERT(index2 < limit)
249 250 */
250 251 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \
251 252 (index) + (step) : (index) + (step) - (limit))
252 253 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \
253 254 (index) - (step) : (index) + (limit) - (step))
254 255 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \
255 256 (index2) - (index1) : (index2) + (limit) - (index1))
256 257
257 258 #define LINK_LIST_INIT(_LH) \
258 259 (_LH)->head = (_LH)->tail = NULL
259 260
260 261 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head))
261 262
262 263 #define LIST_POP_HEAD(_LH) \
263 264 (single_link_t *)(_LH)->head; \
264 265 { \
265 266 if ((_LH)->head != NULL) { \
266 267 (_LH)->head = (_LH)->head->link; \
267 268 if ((_LH)->head == NULL) \
268 269 (_LH)->tail = NULL; \
269 270 } \
270 271 }
271 272
272 273 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail))
273 274
274 275 #define LIST_PUSH_TAIL(_LH, _E) \
275 276 if ((_LH)->tail != NULL) { \
276 277 (_LH)->tail->link = (single_link_t *)(_E); \
277 278 (_LH)->tail = (single_link_t *)(_E); \
278 279 } else { \
279 280 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
280 281 } \
281 282 (_E)->link = NULL;
282 283
283 284 #define LIST_GET_NEXT(_LH, _E) \
284 285 (((_LH)->tail == (single_link_t *)(_E)) ? \
285 286 NULL : ((single_link_t *)(_E))->link)
286 287
287 288
288 289 typedef struct single_link {
289 290 struct single_link *link;
290 291 } single_link_t;
291 292
292 293 typedef struct link_list {
293 294 single_link_t *head;
294 295 single_link_t *tail;
295 296 } link_list_t;
296 297
297 298 /*
298 299 * Property lookups
299 300 */
300 301 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
301 302 DDI_PROP_DONTPASS, (n))
302 303 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
303 304 DDI_PROP_DONTPASS, (n), -1)
304 305
305 306
306 307 /* capability/feature flags */
307 308 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */
308 309 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */
309 310 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */
310 311
311 312 /* function pointer for nic-specific functions */
312 313 typedef void (*igb_nic_func_t)(struct igb *);
313 314
314 315 /* adapter-specific info for each supported device type */
315 316 typedef struct adapter_info {
316 317 /* limits */
317 318 uint32_t max_rx_que_num; /* maximum number of rx queues */
318 319 uint32_t min_rx_que_num; /* minimum number of rx queues */
319 320 uint32_t def_rx_que_num; /* default number of rx queues */
320 321 uint32_t max_tx_que_num; /* maximum number of tx queues */
321 322 uint32_t min_tx_que_num; /* minimum number of tx queues */
322 323 uint32_t def_tx_que_num; /* default number of tx queues */
323 324 uint32_t max_intr_throttle; /* maximum interrupt throttle */
324 325 uint32_t min_intr_throttle; /* minimum interrupt throttle */
325 326 uint32_t def_intr_throttle; /* default interrupt throttle */
326 327 /* function pointers */
327 328 igb_nic_func_t enable_intr; /* enable adapter interrupts */
328 329 igb_nic_func_t setup_msix; /* set up msi-x vectors */
329 330 /* capabilities */
330 331 uint32_t flags; /* capability flags */
331 332 uint32_t rxdctl_mask; /* mask for RXDCTL register */
332 333 } adapter_info_t;
333 334
334 335 typedef union igb_ether_addr {
335 336 struct {
336 337 uint32_t high;
337 338 uint32_t low;
338 339 } reg;
339 340 struct {
340 341 uint8_t set;
341 342 uint8_t group_index;
342 343 uint8_t addr[ETHERADDRL];
343 344 } mac;
344 345 } igb_ether_addr_t;
345 346
346 347 typedef enum {
347 348 USE_NONE,
348 349 USE_COPY,
349 350 USE_DMA
350 351 } tx_type_t;
351 352
352 353 typedef struct tx_context {
353 354 uint32_t hcksum_flags;
354 355 uint32_t ip_hdr_len;
355 356 uint32_t mac_hdr_len;
356 357 uint32_t l4_proto;
357 358 uint32_t mss;
358 359 uint32_t l4_hdr_len;
359 360 boolean_t lso_flag;
360 361 } tx_context_t;
361 362
362 363 /* Hold address/length of each DMA segment */
363 364 typedef struct sw_desc {
364 365 uint64_t address;
365 366 size_t length;
366 367 } sw_desc_t;
367 368
368 369 /* Handles and addresses of DMA buffer */
369 370 typedef struct dma_buffer {
370 371 caddr_t address; /* Virtual address */
371 372 uint64_t dma_address; /* DMA (Hardware) address */
372 373 ddi_acc_handle_t acc_handle; /* Data access handle */
373 374 ddi_dma_handle_t dma_handle; /* DMA handle */
374 375 size_t size; /* Buffer size */
375 376 size_t len; /* Data length in the buffer */
376 377 } dma_buffer_t;
377 378
378 379 /*
379 380 * Tx Control Block
380 381 */
381 382 typedef struct tx_control_block {
382 383 single_link_t link;
383 384 uint32_t last_index;
384 385 uint32_t frag_num;
385 386 uint32_t desc_num;
386 387 mblk_t *mp;
387 388 tx_type_t tx_type;
388 389 ddi_dma_handle_t tx_dma_handle;
389 390 dma_buffer_t tx_buf;
390 391 sw_desc_t desc[MAX_COOKIE];
391 392 } tx_control_block_t;
392 393
393 394 /*
394 395 * RX Control Block
395 396 */
396 397 typedef struct rx_control_block {
397 398 mblk_t *mp;
398 399 uint32_t ref_cnt;
399 400 dma_buffer_t rx_buf;
400 401 frtn_t free_rtn;
401 402 struct igb_rx_data *rx_data;
402 403 } rx_control_block_t;
403 404
404 405 /*
405 406 * Software Data Structure for Tx Ring
406 407 */
407 408 typedef struct igb_tx_ring {
408 409 uint32_t index; /* Ring index */
409 410 uint32_t intr_vector; /* Interrupt vector index */
410 411
411 412 /*
412 413 * Mutexes
413 414 */
414 415 kmutex_t tx_lock;
415 416 kmutex_t recycle_lock;
416 417 kmutex_t tcb_head_lock;
417 418 kmutex_t tcb_tail_lock;
418 419
419 420 /*
420 421 * Tx descriptor ring definitions
421 422 */
422 423 dma_buffer_t tbd_area;
423 424 union e1000_adv_tx_desc *tbd_ring;
424 425 uint32_t tbd_head; /* Index of next tbd to recycle */
425 426 uint32_t tbd_tail; /* Index of next tbd to transmit */
426 427 uint32_t tbd_free; /* Number of free tbd */
427 428
428 429 /*
429 430 * Tx control block list definitions
430 431 */
431 432 tx_control_block_t *tcb_area;
432 433 tx_control_block_t **work_list;
433 434 tx_control_block_t **free_list;
434 435 uint32_t tcb_head; /* Head index of free list */
435 436 uint32_t tcb_tail; /* Tail index of free list */
436 437 uint32_t tcb_free; /* Number of free tcb in free list */
437 438
438 439 uint32_t *tbd_head_wb; /* Head write-back */
439 440 uint32_t (*tx_recycle)(struct igb_tx_ring *);
440 441
441 442 /*
442 443 * s/w context structure for TCP/UDP checksum offload and LSO.
443 444 */
444 445 tx_context_t tx_context;
445 446
446 447 /*
447 448 * Tx ring settings and status
448 449 */
449 450 uint32_t ring_size; /* Tx descriptor ring size */
450 451 uint32_t free_list_size; /* Tx free list size */
451 452
452 453 boolean_t reschedule;
453 454 uint32_t recycle_fail;
454 455 uint32_t stall_watchdog;
455 456
456 457 /*
457 458 * Per-ring statistics
458 459 */
459 460 uint64_t tx_pkts; /* Packets Transmitted Count */
460 461 uint64_t tx_bytes; /* Bytes Transmitted Count */
461 462
462 463 #ifdef IGB_DEBUG
463 464 /*
464 465 * Debug statistics
465 466 */
466 467 uint32_t stat_overload;
467 468 uint32_t stat_fail_no_tbd;
468 469 uint32_t stat_fail_no_tcb;
469 470 uint32_t stat_fail_dma_bind;
470 471 uint32_t stat_reschedule;
471 472 uint32_t stat_pkt_cnt;
472 473 #endif
473 474
474 475 /*
475 476 * Pointer to the igb struct
476 477 */
477 478 struct igb *igb;
478 479 mac_ring_handle_t ring_handle; /* call back ring handle */
479 480 } igb_tx_ring_t;
480 481
481 482 /*
482 483 * Software Receive Ring
483 484 */
484 485 typedef struct igb_rx_data {
485 486 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */
486 487
487 488 /*
488 489 * Rx descriptor ring definitions
489 490 */
490 491 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */
491 492 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */
492 493 uint32_t rbd_next; /* Index of next rx desc */
493 494
494 495 /*
495 496 * Rx control block list definitions
496 497 */
497 498 rx_control_block_t *rcb_area;
498 499 rx_control_block_t **work_list; /* Work list of rcbs */
499 500 rx_control_block_t **free_list; /* Free list of rcbs */
500 501 uint32_t rcb_head; /* Index of next free rcb */
501 502 uint32_t rcb_tail; /* Index to put recycled rcb */
502 503 uint32_t rcb_free; /* Number of free rcbs */
503 504
504 505 /*
505 506 * Rx sw ring settings and status
506 507 */
507 508 uint32_t ring_size; /* Rx descriptor ring size */
508 509 uint32_t free_list_size; /* Rx free list size */
509 510
510 511 uint32_t rcb_pending;
511 512 uint32_t flag;
512 513
513 514 struct igb_rx_ring *rx_ring; /* Pointer to rx ring */
514 515 } igb_rx_data_t;
515 516
516 517 /*
517 518 * Software Data Structure for Rx Ring
518 519 */
519 520 typedef struct igb_rx_ring {
520 521 uint32_t index; /* Ring index */
521 522 uint32_t intr_vector; /* Interrupt vector index */
522 523
523 524 igb_rx_data_t *rx_data; /* Rx software ring */
524 525
525 526 kmutex_t rx_lock; /* Rx access lock */
526 527
527 528 /*
528 529 * Per-ring statistics
529 530 */
530 531 uint64_t rx_pkts; /* Packets Received Count */
531 532 uint64_t rx_bytes; /* Bytes Received Count */
532 533
533 534 #ifdef IGB_DEBUG
534 535 /*
535 536 * Debug statistics
536 537 */
537 538 uint32_t stat_frame_error;
538 539 uint32_t stat_cksum_error;
539 540 uint32_t stat_exceed_pkt;
540 541 uint32_t stat_pkt_cnt;
541 542 #endif
542 543
543 544 struct igb *igb; /* Pointer to igb struct */
544 545 mac_ring_handle_t ring_handle; /* call back ring handle */
545 546 uint32_t group_index; /* group index */
546 547 uint64_t ring_gen_num;
547 548 } igb_rx_ring_t;
548 549
549 550 /*
550 551 * Software Receive Ring Group
551 552 */
552 553 typedef struct igb_rx_group {
553 554 uint32_t index; /* Group index */
554 555 mac_group_handle_t group_handle; /* call back group handle */
555 556 struct igb *igb; /* Pointer to igb struct */
556 557 } igb_rx_group_t;
557 558
558 559 typedef struct igb {
559 560 int instance;
560 561 mac_handle_t mac_hdl;
561 562 dev_info_t *dip;
562 563 struct e1000_hw hw;
563 564 struct igb_osdep osdep;
564 565
565 566 adapter_info_t *capab; /* adapter capabilities */
566 567
567 568 uint32_t igb_state;
568 569 link_state_t link_state;
569 570 uint32_t link_speed;
570 571 uint32_t link_duplex;
571 572 boolean_t link_complete;
572 573 timeout_id_t link_tid;
573 574
574 575 uint32_t reset_count;
575 576 uint32_t attach_progress;
576 577 uint32_t loopback_mode;
577 578 uint32_t default_mtu;
578 579 uint32_t max_frame_size;
579 580 uint32_t dout_sync;
580 581
581 582 uint32_t rcb_pending;
582 583
583 584 uint32_t mr_enable; /* Enable multiple rings */
584 585 uint32_t vmdq_mode; /* Mode of VMDq */
585 586
586 587 /*
587 588 * Receive Rings and Groups
588 589 */
589 590 igb_rx_ring_t *rx_rings; /* Array of rx rings */
590 591 uint32_t num_rx_rings; /* Number of rx rings in use */
591 592 uint32_t rx_ring_size; /* Rx descriptor ring size */
592 593 uint32_t rx_buf_size; /* Rx buffer size */
593 594 igb_rx_group_t *rx_groups; /* Array of rx groups */
594 595 uint32_t num_rx_groups; /* Number of rx groups in use */
595 596
596 597 /*
597 598 * Transmit Rings
598 599 */
599 600 igb_tx_ring_t *tx_rings; /* Array of tx rings */
600 601 uint32_t num_tx_rings; /* Number of tx rings in use */
601 602 uint32_t tx_ring_size; /* Tx descriptor ring size */
602 603 uint32_t tx_buf_size; /* Tx buffer size */
603 604
604 605 boolean_t tx_ring_init;
605 606 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */
606 607 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */
607 608 boolean_t lso_enable; /* Large Segment Offload */
608 609 uint32_t tx_copy_thresh; /* Tx copy threshold */
609 610 uint32_t tx_recycle_thresh; /* Tx recycle threshold */
610 611 uint32_t tx_overload_thresh; /* Tx overload threshold */
611 612 uint32_t tx_resched_thresh; /* Tx reschedule threshold */
612 613 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */
613 614 uint32_t rx_copy_thresh; /* Rx copy threshold */
614 615 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */
615 616
616 617 uint32_t intr_throttling[MAX_NUM_EITR];
617 618 uint32_t intr_force;
618 619
619 620 int intr_type;
620 621 int intr_cnt;
621 622 int intr_cap;
622 623 size_t intr_size;
623 624 uint_t intr_pri;
624 625 ddi_intr_handle_t *htable;
625 626 uint32_t eims_mask;
626 627 uint32_t ims_mask;
627 628
628 629 kmutex_t gen_lock; /* General lock for device access */
629 630 kmutex_t watchdog_lock;
630 631 kmutex_t link_lock;
631 632 kmutex_t rx_pending_lock;
632 633
633 634 boolean_t watchdog_enable;
634 635 boolean_t watchdog_start;
635 636 timeout_id_t watchdog_tid;
636 637
637 638 boolean_t unicst_init;
638 639 uint32_t unicst_avail;
639 640 uint32_t unicst_total;
640 641 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
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641 642 uint32_t mcast_count;
642 643 uint32_t mcast_alloc_count;
643 644 uint32_t mcast_max_num;
644 645 struct ether_addr *mcast_table;
645 646
646 647 /*
647 648 * Kstat definitions
648 649 */
649 650 kstat_t *igb_ks;
650 651
652 + /*
653 + * Backing store for MAC stats. These are reported via GLDv3, instead of
654 + * via our private kstat structure.
655 + */
656 + uint64_t stat_tor; /* rbytes */
657 + uint64_t stat_tpr; /* rpackets */
658 + uint64_t stat_tot; /* obytes */
659 + uint64_t stat_tpt; /* opackets */
660 + uint64_t stat_colc; /* collisions */
661 + uint64_t stat_mcc; /* multi colls */
662 + uint64_t stat_scc; /* single colls */
663 + uint64_t stat_ecol; /* excessive colls */
664 + uint64_t stat_latecol; /* late colls */
665 + uint64_t stat_bptc; /* xmit bcast */
666 + uint64_t stat_mptc; /* xmit bcast */
667 + uint64_t stat_bprc; /* recv bcast */
668 + uint64_t stat_mprc; /* recv mcast */
669 + uint64_t stat_rnbc; /* recv nobuf */
670 + uint64_t stat_roc; /* recv toolong */
671 + uint64_t stat_sec; /* sqe errors */
672 + uint64_t stat_dc; /* defer */
673 + uint64_t stat_algnerrc; /* align errors */
674 + uint64_t stat_crcerrs; /* crc errors */
675 + uint64_t stat_cexterr; /* carrier extension errors */
676 + uint64_t stat_ruc; /* recv tooshort */
677 + uint64_t stat_rjc; /* recv jabber */
678 + uint64_t stat_rxerrc; /* recv errors */
679 +
651 680 uint32_t param_en_1000fdx_cap:1,
652 681 param_en_1000hdx_cap:1,
653 682 param_en_100t4_cap:1,
654 683 param_en_100fdx_cap:1,
655 684 param_en_100hdx_cap:1,
656 685 param_en_10fdx_cap:1,
657 686 param_en_10hdx_cap:1,
658 687 param_1000fdx_cap:1,
659 688 param_1000hdx_cap:1,
660 689 param_100t4_cap:1,
661 690 param_100fdx_cap:1,
662 691 param_100hdx_cap:1,
663 692 param_10fdx_cap:1,
664 693 param_10hdx_cap:1,
665 694 param_autoneg_cap:1,
666 695 param_pause_cap:1,
667 696 param_asym_pause_cap:1,
668 697 param_rem_fault:1,
669 698 param_adv_1000fdx_cap:1,
670 699 param_adv_1000hdx_cap:1,
671 700 param_adv_100t4_cap:1,
672 701 param_adv_100fdx_cap:1,
673 702 param_adv_100hdx_cap:1,
674 703 param_adv_10fdx_cap:1,
675 704 param_adv_10hdx_cap:1,
676 705 param_adv_autoneg_cap:1,
677 706 param_adv_pause_cap:1,
678 707 param_adv_asym_pause_cap:1,
679 708 param_adv_rem_fault:1,
680 709 param_lp_1000fdx_cap:1,
681 710 param_lp_1000hdx_cap:1,
682 711 param_lp_100t4_cap:1;
683 712
684 713 uint32_t param_lp_100fdx_cap:1,
685 714 param_lp_100hdx_cap:1,
686 715 param_lp_10fdx_cap:1,
687 716 param_lp_10hdx_cap:1,
688 717 param_lp_autoneg_cap:1,
689 718 param_lp_pause_cap:1,
690 719 param_lp_asym_pause_cap:1,
691 720 param_lp_rem_fault:1,
692 721 param_pad_to_32:24;
693 722
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694 723 /*
695 724 * FMA capabilities
696 725 */
697 726 int fm_capabilities;
698 727
699 728 ulong_t page_size;
700 729 } igb_t;
701 730
702 731 typedef struct igb_stat {
703 732
704 - kstat_named_t link_speed; /* Link Speed */
705 733 kstat_named_t reset_count; /* Reset Count */
706 734 kstat_named_t dout_sync; /* DMA out of sync */
707 735 #ifdef IGB_DEBUG
708 736 kstat_named_t rx_frame_error; /* Rx Error in Packet */
709 737 kstat_named_t rx_cksum_error; /* Rx Checksum Error */
710 738 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
711 739
712 740 kstat_named_t tx_overload; /* Tx Desc Ring Overload */
713 741 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
714 742 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
715 743 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */
716 744 kstat_named_t tx_reschedule; /* Tx Reschedule */
717 745
718 746 kstat_named_t gprc; /* Good Packets Received Count */
719 747 kstat_named_t gptc; /* Good Packets Xmitted Count */
720 748 kstat_named_t gor; /* Good Octets Received Count */
721 749 kstat_named_t got; /* Good Octets Xmitd Count */
722 750 kstat_named_t prc64; /* Packets Received - 64b */
723 751 kstat_named_t prc127; /* Packets Received - 65-127b */
724 752 kstat_named_t prc255; /* Packets Received - 127-255b */
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725 753 kstat_named_t prc511; /* Packets Received - 256-511b */
726 754 kstat_named_t prc1023; /* Packets Received - 511-1023b */
727 755 kstat_named_t prc1522; /* Packets Received - 1024-1522b */
728 756 kstat_named_t ptc64; /* Packets Xmitted (64b) */
729 757 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */
730 758 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */
731 759 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */
732 760 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */
733 761 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */
734 762 #endif
735 - kstat_named_t crcerrs; /* CRC Error Count */
736 763 kstat_named_t symerrs; /* Symbol Error Count */
737 764 kstat_named_t mpc; /* Missed Packet Count */
738 - kstat_named_t scc; /* Single Collision Count */
739 - kstat_named_t ecol; /* Excessive Collision Count */
740 - kstat_named_t mcc; /* Multiple Collision Count */
741 - kstat_named_t latecol; /* Late Collision Count */
742 - kstat_named_t colc; /* Collision Count */
743 - kstat_named_t dc; /* Defer Count */
744 - kstat_named_t sec; /* Sequence Error Count */
745 765 kstat_named_t rlec; /* Receive Length Error Count */
746 766 kstat_named_t xonrxc; /* XON Received Count */
747 767 kstat_named_t xontxc; /* XON Xmitted Count */
748 768 kstat_named_t xoffrxc; /* XOFF Received Count */
749 769 kstat_named_t xofftxc; /* Xoff Xmitted Count */
750 770 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */
751 - kstat_named_t bprc; /* Broadcasts Pkts Received Count */
752 - kstat_named_t mprc; /* Multicast Pkts Received Count */
753 - kstat_named_t rnbc; /* Receive No Buffers Count */
754 - kstat_named_t ruc; /* Receive Undersize Count */
755 771 kstat_named_t rfc; /* Receive Frag Count */
756 - kstat_named_t roc; /* Receive Oversize Count */
757 - kstat_named_t rjc; /* Receive Jabber Count */
758 - kstat_named_t tor; /* Total Octets Recvd Count */
759 - kstat_named_t tot; /* Total Octets Xmted Count */
760 - kstat_named_t tpr; /* Total Packets Received */
761 - kstat_named_t tpt; /* Total Packets Xmitted */
762 - kstat_named_t mptc; /* Multicast Packets Xmited Count */
763 - kstat_named_t bptc; /* Broadcast Packets Xmited Count */
764 - kstat_named_t algnerrc; /* Alignment Error count */
765 - kstat_named_t rxerrc; /* Rx Error Count */
766 772 kstat_named_t tncrs; /* Transmit with no CRS */
767 - kstat_named_t cexterr; /* Carrier Extension Error count */
768 773 kstat_named_t tsctc; /* TCP seg contexts xmit count */
769 774 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */
770 775 } igb_stat_t;
771 776
772 777 /*
773 778 * Function prototypes in e1000_osdep.c
774 779 */
775 780 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *);
776 781 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *);
777 782 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *);
778 783 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *);
779 784 void e1000_rar_clear(struct e1000_hw *, uint32_t);
780 785 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t,
781 786 uint32_t, uint8_t);
782 787
783 788 /*
784 789 * Function prototypes in igb_buf.c
785 790 */
786 791 int igb_alloc_dma(igb_t *);
787 792 void igb_free_dma(igb_t *);
788 793 void igb_free_dma_buffer(dma_buffer_t *);
789 794 int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring);
790 795 void igb_free_rx_ring_data(igb_rx_data_t *rx_data);
791 796
792 797 /*
793 798 * Function prototypes in igb_main.c
794 799 */
795 800 int igb_start(igb_t *, boolean_t);
796 801 void igb_stop(igb_t *, boolean_t);
797 802 int igb_setup_link(igb_t *, boolean_t);
798 803 int igb_unicst_find(igb_t *, const uint8_t *);
799 804 int igb_unicst_set(igb_t *, const uint8_t *, int);
800 805 int igb_multicst_add(igb_t *, const uint8_t *);
801 806 int igb_multicst_remove(igb_t *, const uint8_t *);
802 807 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *);
803 808 void igb_enable_watchdog_timer(igb_t *);
804 809 void igb_disable_watchdog_timer(igb_t *);
805 810 int igb_atomic_reserve(uint32_t *, uint32_t);
806 811 int igb_check_acc_handle(ddi_acc_handle_t);
807 812 int igb_check_dma_handle(ddi_dma_handle_t);
808 813 void igb_fm_ereport(igb_t *, char *);
809 814 void igb_set_fma_flags(int);
810 815
811 816 /*
812 817 * Function prototypes in igb_gld.c
813 818 */
814 819 int igb_m_start(void *);
815 820 void igb_m_stop(void *);
816 821 int igb_m_promisc(void *, boolean_t);
817 822 int igb_m_multicst(void *, boolean_t, const uint8_t *);
818 823 int igb_m_unicst(void *, const uint8_t *);
819 824 int igb_m_stat(void *, uint_t, uint64_t *);
820 825 void igb_m_resources(void *);
821 826 void igb_m_ioctl(void *, queue_t *, mblk_t *);
822 827 boolean_t igb_m_getcapab(void *, mac_capab_t, void *);
823 828 void igb_fill_ring(void *, mac_ring_type_t, const int, const int,
824 829 mac_ring_info_t *, mac_ring_handle_t);
825 830 int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
826 831 int igb_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *);
827 832 void igb_m_propinfo(void *, const char *, mac_prop_id_t,
828 833 mac_prop_info_handle_t);
829 834 int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *);
830 835 int igb_get_priv_prop(igb_t *, const char *, uint_t, void *);
831 836 void igb_priv_prop_info(igb_t *, const char *, mac_prop_info_handle_t);
832 837 boolean_t igb_param_locked(mac_prop_id_t);
833 838 void igb_fill_group(void *arg, mac_ring_type_t, const int,
834 839 mac_group_info_t *, mac_group_handle_t);
835 840 int igb_rx_ring_intr_enable(mac_intr_handle_t);
836 841 int igb_rx_ring_intr_disable(mac_intr_handle_t);
837 842 int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *);
838 843
839 844 /*
840 845 * Function prototypes in igb_rx.c
841 846 */
842 847 mblk_t *igb_rx(igb_rx_ring_t *, int);
843 848 void igb_rx_recycle(caddr_t arg);
844 849
845 850 /*
846 851 * Function prototypes in igb_tx.c
847 852 */
848 853 void igb_free_tcb(tx_control_block_t *);
849 854 void igb_put_free_list(igb_tx_ring_t *, link_list_t *);
850 855 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *);
851 856 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *);
852 857
853 858 /*
854 859 * Function prototypes in igb_log.c
855 860 */
856 861 void igb_notice(void *, const char *, ...);
857 862 void igb_log(void *, const char *, ...);
858 863 void igb_error(void *, const char *, ...);
859 864
860 865 /*
861 866 * Function prototypes in igb_stat.c
862 867 */
863 868 int igb_init_stats(igb_t *);
864 869
865 870 mblk_t *igb_rx_ring_poll(void *, int);
866 871 mblk_t *igb_tx_ring_send(void *, mblk_t *);
867 872 int igb_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
868 873 int igb_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
869 874
870 875 #ifdef __cplusplus
871 876 }
872 877 #endif
873 878
874 879 #endif /* _IGB_SW_H */
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