1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright 2014 Pluribus Networks Inc.
29 */
30
31 #ifndef _IGB_SW_H
32 #define _IGB_SW_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 #include <sys/types.h>
39 #include <sys/conf.h>
40 #include <sys/debug.h>
41 #include <sys/stropts.h>
42 #include <sys/stream.h>
43 #include <sys/strsun.h>
44 #include <sys/strlog.h>
45 #include <sys/kmem.h>
46 #include <sys/stat.h>
47 #include <sys/kstat.h>
48 #include <sys/modctl.h>
49 #include <sys/errno.h>
50 #include <sys/dlpi.h>
51 #include <sys/mac_provider.h>
52 #include <sys/mac_ether.h>
53 #include <sys/vlan.h>
54 #include <sys/ddi.h>
55 #include <sys/sunddi.h>
56 #include <sys/pci.h>
57 #include <sys/pcie.h>
58 #include <sys/sdt.h>
59 #include <sys/ethernet.h>
60 #include <sys/pattr.h>
61 #include <sys/strsubr.h>
62 #include <sys/netlb.h>
63 #include <sys/random.h>
64 #include <inet/common.h>
65 #include <inet/tcp.h>
66 #include <inet/ip.h>
67 #include <inet/mi.h>
68 #include <inet/nd.h>
69 #include <sys/ddifm.h>
70 #include <sys/fm/protocol.h>
71 #include <sys/fm/util.h>
72 #include <sys/fm/io/ddi.h>
73 #include "e1000_api.h"
74 #include "e1000_82575.h"
75
76
77 #define MODULE_NAME "igb" /* module name */
78
79 #define IGB_SUCCESS DDI_SUCCESS
80 #define IGB_FAILURE DDI_FAILURE
81
82 #define IGB_UNKNOWN 0x00
83 #define IGB_INITIALIZED 0x01
84 #define IGB_STARTED 0x02
85 #define IGB_SUSPENDED 0x04
86 #define IGB_STALL 0x08
87 #define IGB_ERROR 0x80
88
89 #define IGB_RX_STOPPED 0x1
90
91 #define IGB_INTR_NONE 0
92 #define IGB_INTR_MSIX 1
93 #define IGB_INTR_MSI 2
94 #define IGB_INTR_LEGACY 3
95
96 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */
97 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */
98
99 #define IGB_NO_POLL -1
100 #define IGB_NO_FREE_SLOT -1
101
102 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES
103 #define MCAST_ALLOC_COUNT 256
104 #define MAX_COOKIE 18
105 #define MIN_NUM_TX_DESC 2
106
107 /*
108 * Number of settings for interrupt throttle rate (ITR). There is one of
109 * these per msi-x vector and it needs to be the maximum of all silicon
110 * types supported by this driver.
111 */
112 #define MAX_NUM_EITR 25
113
114 /*
115 * Maximum values for user configurable parameters
116 */
117 #define MAX_TX_RING_SIZE 4096
118 #define MAX_RX_RING_SIZE 4096
119 #define MAX_RX_GROUP_NUM 4
120
121 #define MAX_MTU 9000
122 #define MAX_RX_LIMIT_PER_INTR 4096
123
124 #define MAX_RX_COPY_THRESHOLD 9216
125 #define MAX_TX_COPY_THRESHOLD 9216
126 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE
127 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE
128 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE
129 #define MAX_MCAST_NUM 8192
130
131 /*
132 * Minimum values for user configurable parameters
133 */
134 #define MIN_TX_RING_SIZE 64
135 #define MIN_RX_RING_SIZE 64
136 #define MIN_RX_GROUP_NUM 1
137
138 #define MIN_MTU ETHERMIN
139 #define MIN_RX_LIMIT_PER_INTR 16
140
141 #define MIN_RX_COPY_THRESHOLD 0
142 #define MIN_TX_COPY_THRESHOLD 0
143 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC
144 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
145 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC
146 #define MIN_MCAST_NUM 8
147
148 /*
149 * Default values for user configurable parameters
150 */
151 #define DEFAULT_TX_RING_SIZE 512
152 #define DEFAULT_RX_RING_SIZE 512
153 #define DEFAULT_RX_GROUP_NUM 1
154
155 #define DEFAULT_MTU ETHERMTU
156 #define DEFAULT_RX_LIMIT_PER_INTR 256
157
158 #define DEFAULT_RX_COPY_THRESHOLD 128
159 #define DEFAULT_TX_COPY_THRESHOLD 512
160 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1)
161 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
162 #define DEFAULT_TX_RESCHED_THRESHOLD 128
163 #define DEFAULT_TX_RESCHED_THRESHOLD_LOW 32
164 #define DEFAULT_MCAST_NUM 4096
165
166 #define IGB_LSO_MAXLEN 65535
167
168 #define TX_DRAIN_TIME 200
169 #define RX_DRAIN_TIME 200
170
171 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */
172
173 /*
174 * Defined for IP header alignment.
175 */
176 #define IPHDR_ALIGN_ROOM 2
177
178 /*
179 * Bit flags for attach_progress
180 */
181 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
182 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
183 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
184 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
185 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
186 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
187 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
188 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */
189 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
190 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
191 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
192 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */
193
194 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap"
195 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap"
196 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap"
197 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap"
198 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap"
199 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap"
200 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap"
201 #define PROP_DEFAULT_MTU "default_mtu"
202 #define PROP_FLOW_CONTROL "flow_control"
203 #define PROP_TX_RING_SIZE "tx_ring_size"
204 #define PROP_RX_RING_SIZE "rx_ring_size"
205 #define PROP_MR_ENABLE "mr_enable"
206 #define PROP_RX_GROUP_NUM "rx_group_number"
207
208 #define PROP_INTR_FORCE "intr_force"
209 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
210 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
211 #define PROP_LSO_ENABLE "lso_enable"
212 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
213 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
214 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
215 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
216 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold"
217 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold"
218 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr"
219 #define PROP_INTR_THROTTLING "intr_throttling"
220 #define PROP_MCAST_MAX_NUM "mcast_max_num"
221
222 #define IGB_LB_NONE 0
223 #define IGB_LB_EXTERNAL 1
224 #define IGB_LB_INTERNAL_PHY 3
225 #define IGB_LB_INTERNAL_SERDES 4
226
227 enum ioc_reply {
228 IOC_INVAL = -1, /* bad, NAK with EINVAL */
229 IOC_DONE, /* OK, reply sent */
230 IOC_ACK, /* OK, just send ACK */
231 IOC_REPLY /* OK, just send reply */
232 };
233
234 /*
235 * For s/w context extraction from a tx frame
236 */
237 #define TX_CXT_SUCCESS 0
238 #define TX_CXT_E_LSO_CSUM (-1)
239 #define TX_CXT_E_ETHER_TYPE (-2)
240
241 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
242 0, 0, (flag)))
243
244 /*
245 * Defined for ring index operations
246 * ASSERT(index < limit)
247 * ASSERT(step < limit)
248 * ASSERT(index1 < limit)
249 * ASSERT(index2 < limit)
250 */
251 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \
252 (index) + (step) : (index) + (step) - (limit))
253 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \
254 (index) - (step) : (index) + (limit) - (step))
255 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \
256 (index2) - (index1) : (index2) + (limit) - (index1))
257
258 #define LINK_LIST_INIT(_LH) \
259 (_LH)->head = (_LH)->tail = NULL
260
261 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head))
262
263 #define LIST_POP_HEAD(_LH) \
264 (single_link_t *)(_LH)->head; \
265 { \
266 if ((_LH)->head != NULL) { \
267 (_LH)->head = (_LH)->head->link; \
268 if ((_LH)->head == NULL) \
269 (_LH)->tail = NULL; \
270 } \
271 }
272
273 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail))
274
275 #define LIST_PUSH_TAIL(_LH, _E) \
276 if ((_LH)->tail != NULL) { \
277 (_LH)->tail->link = (single_link_t *)(_E); \
278 (_LH)->tail = (single_link_t *)(_E); \
279 } else { \
280 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
281 } \
282 (_E)->link = NULL;
283
284 #define LIST_GET_NEXT(_LH, _E) \
285 (((_LH)->tail == (single_link_t *)(_E)) ? \
286 NULL : ((single_link_t *)(_E))->link)
287
288
289 typedef struct single_link {
290 struct single_link *link;
291 } single_link_t;
292
293 typedef struct link_list {
294 single_link_t *head;
295 single_link_t *tail;
296 } link_list_t;
297
298 /*
299 * Property lookups
300 */
301 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
302 DDI_PROP_DONTPASS, (n))
303 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
304 DDI_PROP_DONTPASS, (n), -1)
305
306
307 /* capability/feature flags */
308 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */
309 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */
310 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */
311
312 /* function pointer for nic-specific functions */
313 typedef void (*igb_nic_func_t)(struct igb *);
314
315 /* adapter-specific info for each supported device type */
316 typedef struct adapter_info {
317 /* limits */
318 uint32_t max_rx_que_num; /* maximum number of rx queues */
319 uint32_t min_rx_que_num; /* minimum number of rx queues */
320 uint32_t def_rx_que_num; /* default number of rx queues */
321 uint32_t max_tx_que_num; /* maximum number of tx queues */
322 uint32_t min_tx_que_num; /* minimum number of tx queues */
323 uint32_t def_tx_que_num; /* default number of tx queues */
324 uint32_t max_intr_throttle; /* maximum interrupt throttle */
325 uint32_t min_intr_throttle; /* minimum interrupt throttle */
326 uint32_t def_intr_throttle; /* default interrupt throttle */
327 /* function pointers */
328 igb_nic_func_t enable_intr; /* enable adapter interrupts */
329 igb_nic_func_t setup_msix; /* set up msi-x vectors */
330 /* capabilities */
331 uint32_t flags; /* capability flags */
332 uint32_t rxdctl_mask; /* mask for RXDCTL register */
333 } adapter_info_t;
334
335 typedef union igb_ether_addr {
336 struct {
337 uint32_t high;
338 uint32_t low;
339 } reg;
340 struct {
341 uint8_t set;
342 uint8_t group_index;
343 uint8_t addr[ETHERADDRL];
344 } mac;
345 } igb_ether_addr_t;
346
347 typedef enum {
348 USE_NONE,
349 USE_COPY,
350 USE_DMA
351 } tx_type_t;
352
353 typedef struct tx_context {
354 uint32_t hcksum_flags;
355 uint32_t ip_hdr_len;
356 uint32_t mac_hdr_len;
357 uint32_t l4_proto;
358 uint32_t mss;
359 uint32_t l4_hdr_len;
360 boolean_t lso_flag;
361 } tx_context_t;
362
363 /* Hold address/length of each DMA segment */
364 typedef struct sw_desc {
365 uint64_t address;
366 size_t length;
367 } sw_desc_t;
368
369 /* Handles and addresses of DMA buffer */
370 typedef struct dma_buffer {
371 caddr_t address; /* Virtual address */
372 uint64_t dma_address; /* DMA (Hardware) address */
373 ddi_acc_handle_t acc_handle; /* Data access handle */
374 ddi_dma_handle_t dma_handle; /* DMA handle */
375 size_t size; /* Buffer size */
376 size_t len; /* Data length in the buffer */
377 } dma_buffer_t;
378
379 /*
380 * Tx Control Block
381 */
382 typedef struct tx_control_block {
383 single_link_t link;
384 uint32_t last_index;
385 uint32_t frag_num;
386 uint32_t desc_num;
387 mblk_t *mp;
388 tx_type_t tx_type;
389 ddi_dma_handle_t tx_dma_handle;
390 dma_buffer_t tx_buf;
391 sw_desc_t desc[MAX_COOKIE];
392 } tx_control_block_t;
393
394 /*
395 * RX Control Block
396 */
397 typedef struct rx_control_block {
398 mblk_t *mp;
399 uint32_t ref_cnt;
400 dma_buffer_t rx_buf;
401 frtn_t free_rtn;
402 struct igb_rx_data *rx_data;
403 } rx_control_block_t;
404
405 /*
406 * Software Data Structure for Tx Ring
407 */
408 typedef struct igb_tx_ring {
409 uint32_t index; /* Ring index */
410 uint32_t intr_vector; /* Interrupt vector index */
411
412 /*
413 * Mutexes
414 */
415 kmutex_t tx_lock;
416 kmutex_t recycle_lock;
417 kmutex_t tcb_head_lock;
418 kmutex_t tcb_tail_lock;
419
420 /*
421 * Tx descriptor ring definitions
422 */
423 dma_buffer_t tbd_area;
424 union e1000_adv_tx_desc *tbd_ring;
425 uint32_t tbd_head; /* Index of next tbd to recycle */
426 uint32_t tbd_tail; /* Index of next tbd to transmit */
427 uint32_t tbd_free; /* Number of free tbd */
428
429 /*
430 * Tx control block list definitions
431 */
432 tx_control_block_t *tcb_area;
433 tx_control_block_t **work_list;
434 tx_control_block_t **free_list;
435 uint32_t tcb_head; /* Head index of free list */
436 uint32_t tcb_tail; /* Tail index of free list */
437 uint32_t tcb_free; /* Number of free tcb in free list */
438
439 uint32_t *tbd_head_wb; /* Head write-back */
440 uint32_t (*tx_recycle)(struct igb_tx_ring *);
441
442 /*
443 * s/w context structure for TCP/UDP checksum offload and LSO.
444 */
445 tx_context_t tx_context;
446
447 /*
448 * Tx ring settings and status
449 */
450 uint32_t ring_size; /* Tx descriptor ring size */
451 uint32_t free_list_size; /* Tx free list size */
452
453 boolean_t reschedule;
454 uint32_t recycle_fail;
455 uint32_t stall_watchdog;
456
457 /*
458 * Per-ring statistics
459 */
460 uint64_t tx_pkts; /* Packets Transmitted Count */
461 uint64_t tx_bytes; /* Bytes Transmitted Count */
462
463 #ifdef IGB_DEBUG
464 /*
465 * Debug statistics
466 */
467 uint32_t stat_overload;
468 uint32_t stat_fail_no_tbd;
469 uint32_t stat_fail_no_tcb;
470 uint32_t stat_fail_dma_bind;
471 uint32_t stat_reschedule;
472 uint32_t stat_pkt_cnt;
473 #endif
474
475 /*
476 * Pointer to the igb struct
477 */
478 struct igb *igb;
479 mac_ring_handle_t ring_handle; /* call back ring handle */
480 } igb_tx_ring_t;
481
482 /*
483 * Software Receive Ring
484 */
485 typedef struct igb_rx_data {
486 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */
487
488 /*
489 * Rx descriptor ring definitions
490 */
491 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */
492 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */
493 uint32_t rbd_next; /* Index of next rx desc */
494
495 /*
496 * Rx control block list definitions
497 */
498 rx_control_block_t *rcb_area;
499 rx_control_block_t **work_list; /* Work list of rcbs */
500 rx_control_block_t **free_list; /* Free list of rcbs */
501 uint32_t rcb_head; /* Index of next free rcb */
502 uint32_t rcb_tail; /* Index to put recycled rcb */
503 uint32_t rcb_free; /* Number of free rcbs */
504
505 /*
506 * Rx sw ring settings and status
507 */
508 uint32_t ring_size; /* Rx descriptor ring size */
509 uint32_t free_list_size; /* Rx free list size */
510
511 uint32_t rcb_pending;
512 uint32_t flag;
513
514 struct igb_rx_ring *rx_ring; /* Pointer to rx ring */
515 } igb_rx_data_t;
516
517 /*
518 * Software Data Structure for Rx Ring
519 */
520 typedef struct igb_rx_ring {
521 uint32_t index; /* Ring index */
522 uint32_t intr_vector; /* Interrupt vector index */
523
524 igb_rx_data_t *rx_data; /* Rx software ring */
525
526 kmutex_t rx_lock; /* Rx access lock */
527
528 /*
529 * Per-ring statistics
530 */
531 uint64_t rx_pkts; /* Packets Received Count */
532 uint64_t rx_bytes; /* Bytes Received Count */
533
534 #ifdef IGB_DEBUG
535 /*
536 * Debug statistics
537 */
538 uint32_t stat_frame_error;
539 uint32_t stat_cksum_error;
540 uint32_t stat_exceed_pkt;
541 uint32_t stat_pkt_cnt;
542 #endif
543
544 struct igb *igb; /* Pointer to igb struct */
545 mac_ring_handle_t ring_handle; /* call back ring handle */
546 uint32_t group_index; /* group index */
547 uint64_t ring_gen_num;
548 } igb_rx_ring_t;
549
550 /*
551 * Software Receive Ring Group
552 */
553 typedef struct igb_rx_group {
554 uint32_t index; /* Group index */
555 mac_group_handle_t group_handle; /* call back group handle */
556 struct igb *igb; /* Pointer to igb struct */
557 } igb_rx_group_t;
558
559 typedef struct igb {
560 int instance;
561 mac_handle_t mac_hdl;
562 dev_info_t *dip;
563 struct e1000_hw hw;
564 struct igb_osdep osdep;
565
566 adapter_info_t *capab; /* adapter capabilities */
567
568 uint32_t igb_state;
569 link_state_t link_state;
570 uint32_t link_speed;
571 uint32_t link_duplex;
572 boolean_t link_complete;
573 timeout_id_t link_tid;
574
575 uint32_t reset_count;
576 uint32_t attach_progress;
577 uint32_t loopback_mode;
578 uint32_t default_mtu;
579 uint32_t max_frame_size;
580 uint32_t dout_sync;
581
582 uint32_t rcb_pending;
583
584 uint32_t mr_enable; /* Enable multiple rings */
585 uint32_t vmdq_mode; /* Mode of VMDq */
586
587 /*
588 * Receive Rings and Groups
589 */
590 igb_rx_ring_t *rx_rings; /* Array of rx rings */
591 uint32_t num_rx_rings; /* Number of rx rings in use */
592 uint32_t rx_ring_size; /* Rx descriptor ring size */
593 uint32_t rx_buf_size; /* Rx buffer size */
594 igb_rx_group_t *rx_groups; /* Array of rx groups */
595 uint32_t num_rx_groups; /* Number of rx groups in use */
596
597 /*
598 * Transmit Rings
599 */
600 igb_tx_ring_t *tx_rings; /* Array of tx rings */
601 uint32_t num_tx_rings; /* Number of tx rings in use */
602 uint32_t tx_ring_size; /* Tx descriptor ring size */
603 uint32_t tx_buf_size; /* Tx buffer size */
604
605 boolean_t tx_ring_init;
606 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */
607 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */
608 boolean_t lso_enable; /* Large Segment Offload */
609 uint32_t tx_copy_thresh; /* Tx copy threshold */
610 uint32_t tx_recycle_thresh; /* Tx recycle threshold */
611 uint32_t tx_overload_thresh; /* Tx overload threshold */
612 uint32_t tx_resched_thresh; /* Tx reschedule threshold */
613 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */
614 uint32_t rx_copy_thresh; /* Rx copy threshold */
615 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */
616
617 uint32_t intr_throttling[MAX_NUM_EITR];
618 uint32_t intr_force;
619
620 int intr_type;
621 int intr_cnt;
622 int intr_cap;
623 size_t intr_size;
624 uint_t intr_pri;
625 ddi_intr_handle_t *htable;
626 uint32_t eims_mask;
627 uint32_t ims_mask;
628
629 kmutex_t gen_lock; /* General lock for device access */
630 kmutex_t watchdog_lock;
631 kmutex_t link_lock;
632 kmutex_t rx_pending_lock;
633
634 boolean_t watchdog_enable;
635 boolean_t watchdog_start;
636 timeout_id_t watchdog_tid;
637
638 boolean_t unicst_init;
639 uint32_t unicst_avail;
640 uint32_t unicst_total;
641 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
642 uint32_t mcast_count;
643 uint32_t mcast_alloc_count;
644 uint32_t mcast_max_num;
645 struct ether_addr *mcast_table;
646
647 /*
648 * Kstat definitions
649 */
650 kstat_t *igb_ks;
651
652 /*
653 * Backing store for MAC stats. These are reported via GLDv3, instead of
654 * via our private kstat structure.
655 */
656 uint64_t stat_tor; /* rbytes */
657 uint64_t stat_tpr; /* rpackets */
658 uint64_t stat_tot; /* obytes */
659 uint64_t stat_tpt; /* opackets */
660 uint64_t stat_colc; /* collisions */
661 uint64_t stat_mcc; /* multi colls */
662 uint64_t stat_scc; /* single colls */
663 uint64_t stat_ecol; /* excessive colls */
664 uint64_t stat_latecol; /* late colls */
665 uint64_t stat_bptc; /* xmit bcast */
666 uint64_t stat_mptc; /* xmit bcast */
667 uint64_t stat_bprc; /* recv bcast */
668 uint64_t stat_mprc; /* recv mcast */
669 uint64_t stat_rnbc; /* recv nobuf */
670 uint64_t stat_roc; /* recv toolong */
671 uint64_t stat_sec; /* sqe errors */
672 uint64_t stat_dc; /* defer */
673 uint64_t stat_algnerrc; /* align errors */
674 uint64_t stat_crcerrs; /* crc errors */
675 uint64_t stat_cexterr; /* carrier extension errors */
676 uint64_t stat_ruc; /* recv tooshort */
677 uint64_t stat_rjc; /* recv jabber */
678 uint64_t stat_rxerrc; /* recv errors */
679
680 uint32_t param_en_1000fdx_cap:1,
681 param_en_1000hdx_cap:1,
682 param_en_100t4_cap:1,
683 param_en_100fdx_cap:1,
684 param_en_100hdx_cap:1,
685 param_en_10fdx_cap:1,
686 param_en_10hdx_cap:1,
687 param_1000fdx_cap:1,
688 param_1000hdx_cap:1,
689 param_100t4_cap:1,
690 param_100fdx_cap:1,
691 param_100hdx_cap:1,
692 param_10fdx_cap:1,
693 param_10hdx_cap:1,
694 param_autoneg_cap:1,
695 param_pause_cap:1,
696 param_asym_pause_cap:1,
697 param_rem_fault:1,
698 param_adv_1000fdx_cap:1,
699 param_adv_1000hdx_cap:1,
700 param_adv_100t4_cap:1,
701 param_adv_100fdx_cap:1,
702 param_adv_100hdx_cap:1,
703 param_adv_10fdx_cap:1,
704 param_adv_10hdx_cap:1,
705 param_adv_autoneg_cap:1,
706 param_adv_pause_cap:1,
707 param_adv_asym_pause_cap:1,
708 param_adv_rem_fault:1,
709 param_lp_1000fdx_cap:1,
710 param_lp_1000hdx_cap:1,
711 param_lp_100t4_cap:1;
712
713 uint32_t param_lp_100fdx_cap:1,
714 param_lp_100hdx_cap:1,
715 param_lp_10fdx_cap:1,
716 param_lp_10hdx_cap:1,
717 param_lp_autoneg_cap:1,
718 param_lp_pause_cap:1,
719 param_lp_asym_pause_cap:1,
720 param_lp_rem_fault:1,
721 param_pad_to_32:24;
722
723 /*
724 * FMA capabilities
725 */
726 int fm_capabilities;
727
728 ulong_t page_size;
729 } igb_t;
730
731 typedef struct igb_stat {
732
733 kstat_named_t reset_count; /* Reset Count */
734 kstat_named_t dout_sync; /* DMA out of sync */
735 #ifdef IGB_DEBUG
736 kstat_named_t rx_frame_error; /* Rx Error in Packet */
737 kstat_named_t rx_cksum_error; /* Rx Checksum Error */
738 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
739
740 kstat_named_t tx_overload; /* Tx Desc Ring Overload */
741 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
742 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
743 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */
744 kstat_named_t tx_reschedule; /* Tx Reschedule */
745
746 kstat_named_t gprc; /* Good Packets Received Count */
747 kstat_named_t gptc; /* Good Packets Xmitted Count */
748 kstat_named_t gor; /* Good Octets Received Count */
749 kstat_named_t got; /* Good Octets Xmitd Count */
750 kstat_named_t prc64; /* Packets Received - 64b */
751 kstat_named_t prc127; /* Packets Received - 65-127b */
752 kstat_named_t prc255; /* Packets Received - 127-255b */
753 kstat_named_t prc511; /* Packets Received - 256-511b */
754 kstat_named_t prc1023; /* Packets Received - 511-1023b */
755 kstat_named_t prc1522; /* Packets Received - 1024-1522b */
756 kstat_named_t ptc64; /* Packets Xmitted (64b) */
757 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */
758 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */
759 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */
760 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */
761 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */
762 #endif
763 kstat_named_t symerrs; /* Symbol Error Count */
764 kstat_named_t mpc; /* Missed Packet Count */
765 kstat_named_t rlec; /* Receive Length Error Count */
766 kstat_named_t xonrxc; /* XON Received Count */
767 kstat_named_t xontxc; /* XON Xmitted Count */
768 kstat_named_t xoffrxc; /* XOFF Received Count */
769 kstat_named_t xofftxc; /* Xoff Xmitted Count */
770 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */
771 kstat_named_t rfc; /* Receive Frag Count */
772 kstat_named_t tncrs; /* Transmit with no CRS */
773 kstat_named_t tsctc; /* TCP seg contexts xmit count */
774 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */
775 } igb_stat_t;
776
777 /*
778 * Function prototypes in e1000_osdep.c
779 */
780 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *);
781 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *);
782 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *);
783 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *);
784 void e1000_rar_clear(struct e1000_hw *, uint32_t);
785 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t,
786 uint32_t, uint8_t);
787
788 /*
789 * Function prototypes in igb_buf.c
790 */
791 int igb_alloc_dma(igb_t *);
792 void igb_free_dma(igb_t *);
793 void igb_free_dma_buffer(dma_buffer_t *);
794 int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring);
795 void igb_free_rx_ring_data(igb_rx_data_t *rx_data);
796
797 /*
798 * Function prototypes in igb_main.c
799 */
800 int igb_start(igb_t *, boolean_t);
801 void igb_stop(igb_t *, boolean_t);
802 int igb_setup_link(igb_t *, boolean_t);
803 int igb_unicst_find(igb_t *, const uint8_t *);
804 int igb_unicst_set(igb_t *, const uint8_t *, int);
805 int igb_multicst_add(igb_t *, const uint8_t *);
806 int igb_multicst_remove(igb_t *, const uint8_t *);
807 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *);
808 void igb_enable_watchdog_timer(igb_t *);
809 void igb_disable_watchdog_timer(igb_t *);
810 int igb_atomic_reserve(uint32_t *, uint32_t);
811 int igb_check_acc_handle(ddi_acc_handle_t);
812 int igb_check_dma_handle(ddi_dma_handle_t);
813 void igb_fm_ereport(igb_t *, char *);
814 void igb_set_fma_flags(int);
815
816 /*
817 * Function prototypes in igb_gld.c
818 */
819 int igb_m_start(void *);
820 void igb_m_stop(void *);
821 int igb_m_promisc(void *, boolean_t);
822 int igb_m_multicst(void *, boolean_t, const uint8_t *);
823 int igb_m_unicst(void *, const uint8_t *);
824 int igb_m_stat(void *, uint_t, uint64_t *);
825 void igb_m_resources(void *);
826 void igb_m_ioctl(void *, queue_t *, mblk_t *);
827 boolean_t igb_m_getcapab(void *, mac_capab_t, void *);
828 void igb_fill_ring(void *, mac_ring_type_t, const int, const int,
829 mac_ring_info_t *, mac_ring_handle_t);
830 int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
831 int igb_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *);
832 void igb_m_propinfo(void *, const char *, mac_prop_id_t,
833 mac_prop_info_handle_t);
834 int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *);
835 int igb_get_priv_prop(igb_t *, const char *, uint_t, void *);
836 void igb_priv_prop_info(igb_t *, const char *, mac_prop_info_handle_t);
837 boolean_t igb_param_locked(mac_prop_id_t);
838 void igb_fill_group(void *arg, mac_ring_type_t, const int,
839 mac_group_info_t *, mac_group_handle_t);
840 int igb_rx_ring_intr_enable(mac_intr_handle_t);
841 int igb_rx_ring_intr_disable(mac_intr_handle_t);
842 int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *);
843
844 /*
845 * Function prototypes in igb_rx.c
846 */
847 mblk_t *igb_rx(igb_rx_ring_t *, int);
848 void igb_rx_recycle(caddr_t arg);
849
850 /*
851 * Function prototypes in igb_tx.c
852 */
853 void igb_free_tcb(tx_control_block_t *);
854 void igb_put_free_list(igb_tx_ring_t *, link_list_t *);
855 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *);
856 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *);
857
858 /*
859 * Function prototypes in igb_log.c
860 */
861 void igb_notice(void *, const char *, ...);
862 void igb_log(void *, const char *, ...);
863 void igb_error(void *, const char *, ...);
864
865 /*
866 * Function prototypes in igb_stat.c
867 */
868 int igb_init_stats(igb_t *);
869
870 mblk_t *igb_rx_ring_poll(void *, int);
871 mblk_t *igb_tx_ring_send(void *, mblk_t *);
872 int igb_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
873 int igb_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
874
875 #ifdef __cplusplus
876 }
877 #endif
878
879 #endif /* _IGB_SW_H */