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4431 igb support for I354
4616 igb has uninitialized kstats
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--- old/usr/src/uts/common/io/igb/igb_main.c
+++ new/usr/src/uts/common/io/igb/igb_main.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 28 * Copyright 2013, Nexenta Systems, Inc. All rights reserved.
29 29 */
30 30
31 31 #include "igb_sw.h"
32 32
33 33 static char ident[] = "Intel 1Gb Ethernet";
34 34 static char igb_version[] = "igb 2.3.8-ish";
35 35
36 36 /*
37 37 * Local function protoypes
38 38 */
39 39 static int igb_register_mac(igb_t *);
40 40 static int igb_identify_hardware(igb_t *);
41 41 static int igb_regs_map(igb_t *);
42 42 static void igb_init_properties(igb_t *);
43 43 static int igb_init_driver_settings(igb_t *);
44 44 static void igb_init_locks(igb_t *);
45 45 static void igb_destroy_locks(igb_t *);
46 46 static int igb_init_mac_address(igb_t *);
47 47 static int igb_init(igb_t *);
48 48 static int igb_init_adapter(igb_t *);
49 49 static void igb_stop_adapter(igb_t *);
50 50 static int igb_reset(igb_t *);
51 51 static void igb_tx_clean(igb_t *);
52 52 static boolean_t igb_tx_drain(igb_t *);
53 53 static boolean_t igb_rx_drain(igb_t *);
54 54 static int igb_alloc_rings(igb_t *);
55 55 static int igb_alloc_rx_data(igb_t *);
56 56 static void igb_free_rx_data(igb_t *);
57 57 static void igb_free_rings(igb_t *);
58 58 static void igb_setup_rings(igb_t *);
59 59 static void igb_setup_rx(igb_t *);
60 60 static void igb_setup_tx(igb_t *);
61 61 static void igb_setup_rx_ring(igb_rx_ring_t *);
62 62 static void igb_setup_tx_ring(igb_tx_ring_t *);
63 63 static void igb_setup_rss(igb_t *);
64 64 static void igb_setup_mac_rss_classify(igb_t *);
65 65 static void igb_setup_mac_classify(igb_t *);
66 66 static void igb_init_unicst(igb_t *);
67 67 static void igb_setup_multicst(igb_t *);
68 68 static void igb_get_phy_state(igb_t *);
69 69 static void igb_param_sync(igb_t *);
70 70 static void igb_get_conf(igb_t *);
71 71 static int igb_get_prop(igb_t *, char *, int, int, int);
72 72 static boolean_t igb_is_link_up(igb_t *);
73 73 static boolean_t igb_link_check(igb_t *);
74 74 static void igb_local_timer(void *);
75 75 static void igb_link_timer(void *);
76 76 static void igb_arm_watchdog_timer(igb_t *);
77 77 static void igb_start_watchdog_timer(igb_t *);
78 78 static void igb_restart_watchdog_timer(igb_t *);
79 79 static void igb_stop_watchdog_timer(igb_t *);
80 80 static void igb_start_link_timer(igb_t *);
81 81 static void igb_stop_link_timer(igb_t *);
82 82 static void igb_disable_adapter_interrupts(igb_t *);
83 83 static void igb_enable_adapter_interrupts_82575(igb_t *);
84 84 static void igb_enable_adapter_interrupts_82576(igb_t *);
85 85 static void igb_enable_adapter_interrupts_82580(igb_t *);
86 86 static boolean_t is_valid_mac_addr(uint8_t *);
87 87 static boolean_t igb_stall_check(igb_t *);
88 88 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t);
89 89 static void igb_set_external_loopback(igb_t *);
90 90 static void igb_set_internal_phy_loopback(igb_t *);
91 91 static void igb_set_internal_serdes_loopback(igb_t *);
92 92 static boolean_t igb_find_mac_address(igb_t *);
93 93 static int igb_alloc_intrs(igb_t *);
94 94 static int igb_alloc_intr_handles(igb_t *, int);
95 95 static int igb_add_intr_handlers(igb_t *);
96 96 static void igb_rem_intr_handlers(igb_t *);
97 97 static void igb_rem_intrs(igb_t *);
98 98 static int igb_enable_intrs(igb_t *);
99 99 static int igb_disable_intrs(igb_t *);
100 100 static void igb_setup_msix_82575(igb_t *);
101 101 static void igb_setup_msix_82576(igb_t *);
102 102 static void igb_setup_msix_82580(igb_t *);
103 103 static uint_t igb_intr_legacy(void *, void *);
104 104 static uint_t igb_intr_msi(void *, void *);
105 105 static uint_t igb_intr_rx(void *, void *);
106 106 static uint_t igb_intr_tx(void *, void *);
107 107 static uint_t igb_intr_tx_other(void *, void *);
108 108 static void igb_intr_rx_work(igb_rx_ring_t *);
109 109 static void igb_intr_tx_work(igb_tx_ring_t *);
110 110 static void igb_intr_link_work(igb_t *);
111 111 static void igb_get_driver_control(struct e1000_hw *);
112 112 static void igb_release_driver_control(struct e1000_hw *);
113 113
114 114 static int igb_attach(dev_info_t *, ddi_attach_cmd_t);
115 115 static int igb_detach(dev_info_t *, ddi_detach_cmd_t);
116 116 static int igb_resume(dev_info_t *);
117 117 static int igb_suspend(dev_info_t *);
118 118 static int igb_quiesce(dev_info_t *);
119 119 static void igb_unconfigure(dev_info_t *, igb_t *);
120 120 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *,
121 121 const void *);
122 122 static void igb_fm_init(igb_t *);
123 123 static void igb_fm_fini(igb_t *);
124 124 static void igb_release_multicast(igb_t *);
125 125
126 126 char *igb_priv_props[] = {
127 127 "_eee_support",
128 128 "_tx_copy_thresh",
129 129 "_tx_recycle_thresh",
130 130 "_tx_overload_thresh",
131 131 "_tx_resched_thresh",
132 132 "_rx_copy_thresh",
133 133 "_rx_limit_per_intr",
134 134 "_intr_throttling",
135 135 "_adv_pause_cap",
136 136 "_adv_asym_pause_cap",
137 137 NULL
138 138 };
139 139
140 140 static struct cb_ops igb_cb_ops = {
141 141 nulldev, /* cb_open */
142 142 nulldev, /* cb_close */
143 143 nodev, /* cb_strategy */
144 144 nodev, /* cb_print */
145 145 nodev, /* cb_dump */
146 146 nodev, /* cb_read */
147 147 nodev, /* cb_write */
148 148 nodev, /* cb_ioctl */
149 149 nodev, /* cb_devmap */
150 150 nodev, /* cb_mmap */
151 151 nodev, /* cb_segmap */
152 152 nochpoll, /* cb_chpoll */
153 153 ddi_prop_op, /* cb_prop_op */
154 154 NULL, /* cb_stream */
155 155 D_MP | D_HOTPLUG, /* cb_flag */
156 156 CB_REV, /* cb_rev */
157 157 nodev, /* cb_aread */
158 158 nodev /* cb_awrite */
159 159 };
160 160
161 161 static struct dev_ops igb_dev_ops = {
162 162 DEVO_REV, /* devo_rev */
163 163 0, /* devo_refcnt */
164 164 NULL, /* devo_getinfo */
165 165 nulldev, /* devo_identify */
166 166 nulldev, /* devo_probe */
167 167 igb_attach, /* devo_attach */
168 168 igb_detach, /* devo_detach */
169 169 nodev, /* devo_reset */
170 170 &igb_cb_ops, /* devo_cb_ops */
171 171 NULL, /* devo_bus_ops */
172 172 ddi_power, /* devo_power */
173 173 igb_quiesce, /* devo_quiesce */
174 174 };
175 175
176 176 static struct modldrv igb_modldrv = {
177 177 &mod_driverops, /* Type of module. This one is a driver */
178 178 ident, /* Discription string */
179 179 &igb_dev_ops, /* driver ops */
180 180 };
181 181
182 182 static struct modlinkage igb_modlinkage = {
183 183 MODREV_1, &igb_modldrv, NULL
184 184 };
185 185
186 186 /* Access attributes for register mapping */
187 187 ddi_device_acc_attr_t igb_regs_acc_attr = {
188 188 DDI_DEVICE_ATTR_V1,
189 189 DDI_STRUCTURE_LE_ACC,
190 190 DDI_STRICTORDER_ACC,
191 191 DDI_FLAGERR_ACC
192 192 };
193 193
194 194 #define IGB_M_CALLBACK_FLAGS \
195 195 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
196 196
197 197 static mac_callbacks_t igb_m_callbacks = {
198 198 IGB_M_CALLBACK_FLAGS,
199 199 igb_m_stat,
200 200 igb_m_start,
201 201 igb_m_stop,
202 202 igb_m_promisc,
203 203 igb_m_multicst,
204 204 NULL,
205 205 NULL,
206 206 NULL,
207 207 igb_m_ioctl,
208 208 igb_m_getcapab,
209 209 NULL,
210 210 NULL,
211 211 igb_m_setprop,
212 212 igb_m_getprop,
213 213 igb_m_propinfo
214 214 };
215 215
216 216 /*
217 217 * Initialize capabilities of each supported adapter type
218 218 */
219 219 static adapter_info_t igb_82575_cap = {
220 220 /* limits */
221 221 4, /* maximum number of rx queues */
222 222 1, /* minimum number of rx queues */
223 223 4, /* default number of rx queues */
224 224 4, /* maximum number of tx queues */
225 225 1, /* minimum number of tx queues */
226 226 4, /* default number of tx queues */
227 227 65535, /* maximum interrupt throttle rate */
228 228 0, /* minimum interrupt throttle rate */
229 229 200, /* default interrupt throttle rate */
230 230
231 231 /* function pointers */
232 232 igb_enable_adapter_interrupts_82575,
233 233 igb_setup_msix_82575,
234 234
235 235 /* capabilities */
236 236 (IGB_FLAG_HAS_DCA | /* capability flags */
237 237 IGB_FLAG_VMDQ_POOL),
238 238
239 239 0xffc00000 /* mask for RXDCTL register */
240 240 };
241 241
242 242 static adapter_info_t igb_82576_cap = {
243 243 /* limits */
244 244 16, /* maximum number of rx queues */
245 245 1, /* minimum number of rx queues */
246 246 4, /* default number of rx queues */
247 247 16, /* maximum number of tx queues */
248 248 1, /* minimum number of tx queues */
249 249 4, /* default number of tx queues */
250 250 65535, /* maximum interrupt throttle rate */
251 251 0, /* minimum interrupt throttle rate */
252 252 200, /* default interrupt throttle rate */
253 253
254 254 /* function pointers */
255 255 igb_enable_adapter_interrupts_82576,
256 256 igb_setup_msix_82576,
257 257
258 258 /* capabilities */
259 259 (IGB_FLAG_HAS_DCA | /* capability flags */
260 260 IGB_FLAG_VMDQ_POOL |
261 261 IGB_FLAG_NEED_CTX_IDX),
262 262
263 263 0xffe00000 /* mask for RXDCTL register */
264 264 };
265 265
266 266 static adapter_info_t igb_82580_cap = {
267 267 /* limits */
268 268 8, /* maximum number of rx queues */
269 269 1, /* minimum number of rx queues */
270 270 4, /* default number of rx queues */
271 271 8, /* maximum number of tx queues */
272 272 1, /* minimum number of tx queues */
273 273 4, /* default number of tx queues */
274 274 65535, /* maximum interrupt throttle rate */
275 275 0, /* minimum interrupt throttle rate */
276 276 200, /* default interrupt throttle rate */
277 277
278 278 /* function pointers */
279 279 igb_enable_adapter_interrupts_82580,
280 280 igb_setup_msix_82580,
281 281
282 282 /* capabilities */
283 283 (IGB_FLAG_HAS_DCA | /* capability flags */
284 284 IGB_FLAG_VMDQ_POOL |
285 285 IGB_FLAG_NEED_CTX_IDX),
286 286
287 287 0xffe00000 /* mask for RXDCTL register */
288 288 };
289 289
290 290 static adapter_info_t igb_i350_cap = {
291 291 /* limits */
292 292 8, /* maximum number of rx queues */
293 293 1, /* minimum number of rx queues */
294 294 4, /* default number of rx queues */
295 295 8, /* maximum number of tx queues */
296 296 1, /* minimum number of tx queues */
297 297 4, /* default number of tx queues */
298 298 65535, /* maximum interrupt throttle rate */
299 299 0, /* minimum interrupt throttle rate */
300 300 200, /* default interrupt throttle rate */
301 301
302 302 /* function pointers */
303 303 igb_enable_adapter_interrupts_82580,
304 304 igb_setup_msix_82580,
305 305
306 306 /* capabilities */
307 307 (IGB_FLAG_HAS_DCA | /* capability flags */
308 308 IGB_FLAG_VMDQ_POOL |
309 309 IGB_FLAG_NEED_CTX_IDX),
310 310
311 311 0xffe00000 /* mask for RXDCTL register */
312 312 };
313 313
314 314 static adapter_info_t igb_i210_cap = {
315 315 /* limits */
316 316 4, /* maximum number of rx queues */
317 317 1, /* minimum number of rx queues */
318 318 4, /* default number of rx queues */
319 319 4, /* maximum number of tx queues */
320 320 1, /* minimum number of tx queues */
321 321 4, /* default number of tx queues */
322 322 65535, /* maximum interrupt throttle rate */
323 323 0, /* minimum interrupt throttle rate */
324 324 200, /* default interrupt throttle rate */
325 325
326 326 /* function pointers */
327 327 igb_enable_adapter_interrupts_82580,
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328 328 igb_setup_msix_82580,
329 329
330 330 /* capabilities */
331 331 (IGB_FLAG_HAS_DCA | /* capability flags */
332 332 IGB_FLAG_VMDQ_POOL |
333 333 IGB_FLAG_NEED_CTX_IDX),
334 334
335 335 0xfff00000 /* mask for RXDCTL register */
336 336 };
337 337
338 +static adapter_info_t igb_i354_cap = {
339 + /* limits */
340 + 8, /* maximum number of rx queues */
341 + 1, /* minimum number of rx queues */
342 + 4, /* default number of rx queues */
343 + 8, /* maximum number of tx queues */
344 + 1, /* minimum number of tx queues */
345 + 4, /* default number of tx queues */
346 + 65535, /* maximum interrupt throttle rate */
347 + 0, /* minimum interrupt throttle rate */
348 + 200, /* default interrupt throttle rate */
349 +
350 + /* function pointers */
351 + igb_enable_adapter_interrupts_82580,
352 + igb_setup_msix_82580,
353 +
354 + /* capabilities */
355 + (IGB_FLAG_HAS_DCA | /* capability flags */
356 + IGB_FLAG_VMDQ_POOL |
357 + IGB_FLAG_NEED_CTX_IDX),
358 +
359 + 0xfff00000 /* mask for RXDCTL register */
360 +};
361 +
338 362 /*
339 363 * Module Initialization Functions
340 364 */
341 365
342 366 int
343 367 _init(void)
344 368 {
345 369 int status;
346 370
347 371 mac_init_ops(&igb_dev_ops, MODULE_NAME);
348 372
349 373 status = mod_install(&igb_modlinkage);
350 374
351 375 if (status != DDI_SUCCESS) {
352 376 mac_fini_ops(&igb_dev_ops);
353 377 }
354 378
355 379 return (status);
356 380 }
357 381
358 382 int
359 383 _fini(void)
360 384 {
361 385 int status;
362 386
363 387 status = mod_remove(&igb_modlinkage);
364 388
365 389 if (status == DDI_SUCCESS) {
366 390 mac_fini_ops(&igb_dev_ops);
367 391 }
368 392
369 393 return (status);
370 394
371 395 }
372 396
373 397 int
374 398 _info(struct modinfo *modinfop)
375 399 {
376 400 int status;
377 401
378 402 status = mod_info(&igb_modlinkage, modinfop);
379 403
380 404 return (status);
381 405 }
382 406
383 407 /*
384 408 * igb_attach - driver attach
385 409 *
386 410 * This function is the device specific initialization entry
387 411 * point. This entry point is required and must be written.
388 412 * The DDI_ATTACH command must be provided in the attach entry
389 413 * point. When attach() is called with cmd set to DDI_ATTACH,
390 414 * all normal kernel services (such as kmem_alloc(9F)) are
391 415 * available for use by the driver.
392 416 *
393 417 * The attach() function will be called once for each instance
394 418 * of the device on the system with cmd set to DDI_ATTACH.
395 419 * Until attach() succeeds, the only driver entry points which
396 420 * may be called are open(9E) and getinfo(9E).
397 421 */
398 422 static int
399 423 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
400 424 {
401 425 igb_t *igb;
402 426 struct igb_osdep *osdep;
403 427 struct e1000_hw *hw;
404 428 int instance;
405 429
406 430 /*
407 431 * Check the command and perform corresponding operations
408 432 */
409 433 switch (cmd) {
410 434 default:
411 435 return (DDI_FAILURE);
412 436
413 437 case DDI_RESUME:
414 438 return (igb_resume(devinfo));
415 439
416 440 case DDI_ATTACH:
417 441 break;
418 442 }
419 443
420 444 /* Get the device instance */
421 445 instance = ddi_get_instance(devinfo);
422 446
423 447 /* Allocate memory for the instance data structure */
424 448 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP);
425 449
426 450 igb->dip = devinfo;
427 451 igb->instance = instance;
428 452
429 453 hw = &igb->hw;
430 454 osdep = &igb->osdep;
431 455 hw->back = osdep;
432 456 osdep->igb = igb;
433 457
434 458 /* Attach the instance pointer to the dev_info data structure */
435 459 ddi_set_driver_private(devinfo, igb);
436 460
437 461
438 462 /* Initialize for fma support */
439 463 igb->fm_capabilities = igb_get_prop(igb, "fm-capable",
440 464 0, 0x0f,
441 465 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
442 466 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
443 467 igb_fm_init(igb);
444 468 igb->attach_progress |= ATTACH_PROGRESS_FMINIT;
445 469
446 470 /*
447 471 * Map PCI config space registers
448 472 */
449 473 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) {
450 474 igb_error(igb, "Failed to map PCI configurations");
451 475 goto attach_fail;
452 476 }
453 477 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
454 478
455 479 /*
456 480 * Identify the chipset family
457 481 */
458 482 if (igb_identify_hardware(igb) != IGB_SUCCESS) {
459 483 igb_error(igb, "Failed to identify hardware");
460 484 goto attach_fail;
461 485 }
462 486
463 487 /*
464 488 * Map device registers
465 489 */
466 490 if (igb_regs_map(igb) != IGB_SUCCESS) {
467 491 igb_error(igb, "Failed to map device registers");
468 492 goto attach_fail;
469 493 }
470 494 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
471 495
472 496 /*
473 497 * Initialize driver parameters
474 498 */
475 499 igb_init_properties(igb);
476 500 igb->attach_progress |= ATTACH_PROGRESS_PROPS;
477 501
478 502 /*
479 503 * Allocate interrupts
480 504 */
481 505 if (igb_alloc_intrs(igb) != IGB_SUCCESS) {
482 506 igb_error(igb, "Failed to allocate interrupts");
483 507 goto attach_fail;
484 508 }
485 509 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
486 510
487 511 /*
488 512 * Allocate rx/tx rings based on the ring numbers.
489 513 * The actual numbers of rx/tx rings are decided by the number of
490 514 * allocated interrupt vectors, so we should allocate the rings after
491 515 * interrupts are allocated.
492 516 */
493 517 if (igb_alloc_rings(igb) != IGB_SUCCESS) {
494 518 igb_error(igb, "Failed to allocate rx/tx rings or groups");
495 519 goto attach_fail;
496 520 }
497 521 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS;
498 522
499 523 /*
500 524 * Add interrupt handlers
501 525 */
502 526 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) {
503 527 igb_error(igb, "Failed to add interrupt handlers");
504 528 goto attach_fail;
505 529 }
506 530 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
507 531
508 532 /*
509 533 * Initialize driver parameters
510 534 */
511 535 if (igb_init_driver_settings(igb) != IGB_SUCCESS) {
512 536 igb_error(igb, "Failed to initialize driver settings");
513 537 goto attach_fail;
514 538 }
515 539
516 540 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) {
517 541 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
518 542 goto attach_fail;
519 543 }
520 544
521 545 /*
522 546 * Initialize mutexes for this device.
523 547 * Do this before enabling the interrupt handler and
524 548 * register the softint to avoid the condition where
525 549 * interrupt handler can try using uninitialized mutex
526 550 */
527 551 igb_init_locks(igb);
528 552 igb->attach_progress |= ATTACH_PROGRESS_LOCKS;
529 553
530 554 /*
531 555 * Initialize the adapter
532 556 */
533 557 if (igb_init(igb) != IGB_SUCCESS) {
534 558 igb_error(igb, "Failed to initialize adapter");
535 559 goto attach_fail;
536 560 }
537 561 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
538 562
539 563 /*
540 564 * Initialize statistics
541 565 */
542 566 if (igb_init_stats(igb) != IGB_SUCCESS) {
543 567 igb_error(igb, "Failed to initialize statistics");
544 568 goto attach_fail;
545 569 }
546 570 igb->attach_progress |= ATTACH_PROGRESS_STATS;
547 571
548 572 /*
549 573 * Register the driver to the MAC
550 574 */
551 575 if (igb_register_mac(igb) != IGB_SUCCESS) {
552 576 igb_error(igb, "Failed to register MAC");
553 577 goto attach_fail;
554 578 }
555 579 igb->attach_progress |= ATTACH_PROGRESS_MAC;
556 580
557 581 /*
558 582 * Now that mutex locks are initialized, and the chip is also
559 583 * initialized, enable interrupts.
560 584 */
561 585 if (igb_enable_intrs(igb) != IGB_SUCCESS) {
562 586 igb_error(igb, "Failed to enable DDI interrupts");
563 587 goto attach_fail;
564 588 }
565 589 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
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566 590
567 591 igb_log(igb, "%s", igb_version);
568 592 atomic_or_32(&igb->igb_state, IGB_INITIALIZED);
569 593
570 594 /*
571 595 * Newer models have Energy Efficient Ethernet, let's disable this by
572 596 * default.
573 597 */
574 598 if (igb->hw.mac.type == e1000_i350)
575 599 (void) e1000_set_eee_i350(&igb->hw);
600 + else if (igb->hw.mac.type == e1000_i354)
601 + (void) e1000_set_eee_i354(&igb->hw);
576 602
577 603 return (DDI_SUCCESS);
578 604
579 605 attach_fail:
580 606 igb_unconfigure(devinfo, igb);
581 607 return (DDI_FAILURE);
582 608 }
583 609
584 610 /*
585 611 * igb_detach - driver detach
586 612 *
587 613 * The detach() function is the complement of the attach routine.
588 614 * If cmd is set to DDI_DETACH, detach() is used to remove the
589 615 * state associated with a given instance of a device node
590 616 * prior to the removal of that instance from the system.
591 617 *
592 618 * The detach() function will be called once for each instance
593 619 * of the device for which there has been a successful attach()
594 620 * once there are no longer any opens on the device.
595 621 *
596 622 * Interrupts routine are disabled, All memory allocated by this
597 623 * driver are freed.
598 624 */
599 625 static int
600 626 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
601 627 {
602 628 igb_t *igb;
603 629
604 630 /*
605 631 * Check detach command
606 632 */
607 633 switch (cmd) {
608 634 default:
609 635 return (DDI_FAILURE);
610 636
611 637 case DDI_SUSPEND:
612 638 return (igb_suspend(devinfo));
613 639
614 640 case DDI_DETACH:
615 641 break;
616 642 }
617 643
618 644
619 645 /*
620 646 * Get the pointer to the driver private data structure
621 647 */
622 648 igb = (igb_t *)ddi_get_driver_private(devinfo);
623 649 if (igb == NULL)
624 650 return (DDI_FAILURE);
625 651
626 652 /*
627 653 * Unregister MAC. If failed, we have to fail the detach
628 654 */
629 655 if (mac_unregister(igb->mac_hdl) != 0) {
630 656 igb_error(igb, "Failed to unregister MAC");
631 657 return (DDI_FAILURE);
632 658 }
633 659 igb->attach_progress &= ~ATTACH_PROGRESS_MAC;
634 660
635 661 /*
636 662 * If the device is still running, it needs to be stopped first.
637 663 * This check is necessary because under some specific circumstances,
638 664 * the detach routine can be called without stopping the interface
639 665 * first.
640 666 */
641 667 mutex_enter(&igb->gen_lock);
642 668 if (igb->igb_state & IGB_STARTED) {
643 669 atomic_and_32(&igb->igb_state, ~IGB_STARTED);
644 670 igb_stop(igb, B_TRUE);
645 671 mutex_exit(&igb->gen_lock);
646 672 /* Disable and stop the watchdog timer */
647 673 igb_disable_watchdog_timer(igb);
648 674 } else
649 675 mutex_exit(&igb->gen_lock);
650 676
651 677 /*
652 678 * Check if there are still rx buffers held by the upper layer.
653 679 * If so, fail the detach.
654 680 */
655 681 if (!igb_rx_drain(igb))
656 682 return (DDI_FAILURE);
657 683
658 684 /*
659 685 * Do the remaining unconfigure routines
660 686 */
661 687 igb_unconfigure(devinfo, igb);
662 688
663 689 return (DDI_SUCCESS);
664 690 }
665 691
666 692 /*
667 693 * quiesce(9E) entry point.
668 694 *
669 695 * This function is called when the system is single-threaded at high
670 696 * PIL with preemption disabled. Therefore, this function must not be
671 697 * blocked.
672 698 *
673 699 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
674 700 * DDI_FAILURE indicates an error condition and should almost never happen.
675 701 */
676 702 static int
677 703 igb_quiesce(dev_info_t *devinfo)
678 704 {
679 705 igb_t *igb;
680 706 struct e1000_hw *hw;
681 707
682 708 igb = (igb_t *)ddi_get_driver_private(devinfo);
683 709
684 710 if (igb == NULL)
685 711 return (DDI_FAILURE);
686 712
687 713 hw = &igb->hw;
688 714
689 715 /*
690 716 * Disable the adapter interrupts
691 717 */
692 718 igb_disable_adapter_interrupts(igb);
693 719
694 720 /* Tell firmware driver is no longer in control */
695 721 igb_release_driver_control(hw);
696 722
697 723 /*
698 724 * Reset the chipset
699 725 */
700 726 (void) e1000_reset_hw(hw);
701 727
702 728 /*
703 729 * Reset PHY if possible
704 730 */
705 731 if (e1000_check_reset_block(hw) == E1000_SUCCESS)
706 732 (void) e1000_phy_hw_reset(hw);
707 733
708 734 return (DDI_SUCCESS);
709 735 }
710 736
711 737 /*
712 738 * igb_unconfigure - release all resources held by this instance
713 739 */
714 740 static void
715 741 igb_unconfigure(dev_info_t *devinfo, igb_t *igb)
716 742 {
717 743 /*
718 744 * Disable interrupt
719 745 */
720 746 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
721 747 (void) igb_disable_intrs(igb);
722 748 }
723 749
724 750 /*
725 751 * Unregister MAC
726 752 */
727 753 if (igb->attach_progress & ATTACH_PROGRESS_MAC) {
728 754 (void) mac_unregister(igb->mac_hdl);
729 755 }
730 756
731 757 /*
732 758 * Free statistics
733 759 */
734 760 if (igb->attach_progress & ATTACH_PROGRESS_STATS) {
735 761 kstat_delete((kstat_t *)igb->igb_ks);
736 762 }
737 763
738 764 /*
739 765 * Remove interrupt handlers
740 766 */
741 767 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
742 768 igb_rem_intr_handlers(igb);
743 769 }
744 770
745 771 /*
746 772 * Remove interrupts
747 773 */
748 774 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) {
749 775 igb_rem_intrs(igb);
750 776 }
751 777
752 778 /*
753 779 * Remove driver properties
754 780 */
755 781 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) {
756 782 (void) ddi_prop_remove_all(devinfo);
757 783 }
758 784
759 785 /*
760 786 * Stop the adapter
761 787 */
762 788 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) {
763 789 mutex_enter(&igb->gen_lock);
764 790 igb_stop_adapter(igb);
765 791 mutex_exit(&igb->gen_lock);
766 792 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
767 793 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED);
768 794 }
769 795
770 796 /*
771 797 * Free multicast table
772 798 */
773 799 igb_release_multicast(igb);
774 800
775 801 /*
776 802 * Free register handle
777 803 */
778 804 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
779 805 if (igb->osdep.reg_handle != NULL)
780 806 ddi_regs_map_free(&igb->osdep.reg_handle);
781 807 }
782 808
783 809 /*
784 810 * Free PCI config handle
785 811 */
786 812 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
787 813 if (igb->osdep.cfg_handle != NULL)
788 814 pci_config_teardown(&igb->osdep.cfg_handle);
789 815 }
790 816
791 817 /*
792 818 * Free locks
793 819 */
794 820 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) {
795 821 igb_destroy_locks(igb);
796 822 }
797 823
798 824 /*
799 825 * Free the rx/tx rings
800 826 */
801 827 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) {
802 828 igb_free_rings(igb);
803 829 }
804 830
805 831 /*
806 832 * Remove FMA
807 833 */
808 834 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) {
809 835 igb_fm_fini(igb);
810 836 }
811 837
812 838 /*
813 839 * Free the driver data structure
814 840 */
815 841 kmem_free(igb, sizeof (igb_t));
816 842
817 843 ddi_set_driver_private(devinfo, NULL);
818 844 }
819 845
820 846 /*
821 847 * igb_register_mac - Register the driver and its function pointers with
822 848 * the GLD interface
823 849 */
824 850 static int
825 851 igb_register_mac(igb_t *igb)
826 852 {
827 853 struct e1000_hw *hw = &igb->hw;
828 854 mac_register_t *mac;
829 855 int status;
830 856
831 857 if ((mac = mac_alloc(MAC_VERSION)) == NULL)
832 858 return (IGB_FAILURE);
833 859
834 860 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
835 861 mac->m_driver = igb;
836 862 mac->m_dip = igb->dip;
837 863 mac->m_src_addr = hw->mac.addr;
838 864 mac->m_callbacks = &igb_m_callbacks;
839 865 mac->m_min_sdu = 0;
840 866 mac->m_max_sdu = igb->max_frame_size -
841 867 sizeof (struct ether_vlan_header) - ETHERFCSL;
842 868 mac->m_margin = VLAN_TAGSZ;
843 869 mac->m_priv_props = igb_priv_props;
844 870 mac->m_v12n = MAC_VIRT_LEVEL1;
845 871
846 872 status = mac_register(mac, &igb->mac_hdl);
847 873
848 874 mac_free(mac);
849 875
850 876 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE);
851 877 }
852 878
853 879 /*
854 880 * igb_identify_hardware - Identify the type of the chipset
855 881 */
856 882 static int
857 883 igb_identify_hardware(igb_t *igb)
858 884 {
859 885 struct e1000_hw *hw = &igb->hw;
860 886 struct igb_osdep *osdep = &igb->osdep;
861 887
862 888 /*
863 889 * Get the device id
864 890 */
865 891 hw->vendor_id =
866 892 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID);
867 893 hw->device_id =
868 894 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID);
869 895 hw->revision_id =
870 896 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID);
871 897 hw->subsystem_device_id =
872 898 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID);
873 899 hw->subsystem_vendor_id =
874 900 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID);
875 901
876 902 /*
877 903 * Set the mac type of the adapter based on the device id
878 904 */
879 905 if (e1000_set_mac_type(hw) != E1000_SUCCESS) {
880 906 return (IGB_FAILURE);
881 907 }
882 908
883 909 /*
884 910 * Install adapter capabilities based on mac type
885 911 */
886 912 switch (hw->mac.type) {
887 913 case e1000_82575:
888 914 igb->capab = &igb_82575_cap;
889 915 break;
890 916 case e1000_82576:
891 917 igb->capab = &igb_82576_cap;
892 918 break;
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893 919 case e1000_82580:
894 920 igb->capab = &igb_82580_cap;
895 921 break;
896 922 case e1000_i350:
897 923 igb->capab = &igb_i350_cap;
898 924 break;
899 925 case e1000_i210:
900 926 case e1000_i211:
901 927 igb->capab = &igb_i210_cap;
902 928 break;
929 + case e1000_i354:
930 + igb->capab = &igb_i354_cap;
931 + break;
903 932 default:
904 933 return (IGB_FAILURE);
905 934 }
906 935
907 936 return (IGB_SUCCESS);
908 937 }
909 938
910 939 /*
911 940 * igb_regs_map - Map the device registers
912 941 */
913 942 static int
914 943 igb_regs_map(igb_t *igb)
915 944 {
916 945 dev_info_t *devinfo = igb->dip;
917 946 struct e1000_hw *hw = &igb->hw;
918 947 struct igb_osdep *osdep = &igb->osdep;
919 948 off_t mem_size;
920 949
921 950 /*
922 951 * First get the size of device registers to be mapped.
923 952 */
924 953 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) !=
925 954 DDI_SUCCESS) {
926 955 return (IGB_FAILURE);
927 956 }
928 957
929 958 /*
930 959 * Call ddi_regs_map_setup() to map registers
931 960 */
932 961 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET,
933 962 (caddr_t *)&hw->hw_addr, 0,
934 963 mem_size, &igb_regs_acc_attr,
935 964 &osdep->reg_handle)) != DDI_SUCCESS) {
936 965 return (IGB_FAILURE);
937 966 }
938 967
939 968 return (IGB_SUCCESS);
940 969 }
941 970
942 971 /*
943 972 * igb_init_properties - Initialize driver properties
944 973 */
945 974 static void
946 975 igb_init_properties(igb_t *igb)
947 976 {
948 977 /*
949 978 * Get conf file properties, including link settings
950 979 * jumbo frames, ring number, descriptor number, etc.
951 980 */
952 981 igb_get_conf(igb);
953 982 }
954 983
955 984 /*
956 985 * igb_init_driver_settings - Initialize driver settings
957 986 *
958 987 * The settings include hardware function pointers, bus information,
959 988 * rx/tx rings settings, link state, and any other parameters that
960 989 * need to be setup during driver initialization.
961 990 */
962 991 static int
963 992 igb_init_driver_settings(igb_t *igb)
964 993 {
965 994 struct e1000_hw *hw = &igb->hw;
966 995 igb_rx_ring_t *rx_ring;
967 996 igb_tx_ring_t *tx_ring;
968 997 uint32_t rx_size;
969 998 uint32_t tx_size;
970 999 int i;
971 1000
972 1001 /*
973 1002 * Initialize chipset specific hardware function pointers
974 1003 */
975 1004 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
976 1005 return (IGB_FAILURE);
977 1006 }
978 1007
979 1008 /*
980 1009 * Get bus information
981 1010 */
982 1011 if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
983 1012 return (IGB_FAILURE);
984 1013 }
985 1014
986 1015 /*
987 1016 * Get the system page size
988 1017 */
989 1018 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1);
990 1019
991 1020 /*
992 1021 * Set rx buffer size
993 1022 * The IP header alignment room is counted in the calculation.
994 1023 * The rx buffer size is in unit of 1K that is required by the
995 1024 * chipset hardware.
996 1025 */
997 1026 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM;
998 1027 igb->rx_buf_size = ((rx_size >> 10) +
999 1028 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
1000 1029
1001 1030 /*
1002 1031 * Set tx buffer size
1003 1032 */
1004 1033 tx_size = igb->max_frame_size;
1005 1034 igb->tx_buf_size = ((tx_size >> 10) +
1006 1035 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
1007 1036
1008 1037 /*
1009 1038 * Initialize rx/tx rings parameters
1010 1039 */
1011 1040 for (i = 0; i < igb->num_rx_rings; i++) {
1012 1041 rx_ring = &igb->rx_rings[i];
1013 1042 rx_ring->index = i;
1014 1043 rx_ring->igb = igb;
1015 1044 }
1016 1045
1017 1046 for (i = 0; i < igb->num_tx_rings; i++) {
1018 1047 tx_ring = &igb->tx_rings[i];
1019 1048 tx_ring->index = i;
1020 1049 tx_ring->igb = igb;
1021 1050 if (igb->tx_head_wb_enable)
1022 1051 tx_ring->tx_recycle = igb_tx_recycle_head_wb;
1023 1052 else
1024 1053 tx_ring->tx_recycle = igb_tx_recycle_legacy;
1025 1054
1026 1055 tx_ring->ring_size = igb->tx_ring_size;
1027 1056 tx_ring->free_list_size = igb->tx_ring_size +
1028 1057 (igb->tx_ring_size >> 1);
1029 1058 }
1030 1059
1031 1060 /*
1032 1061 * Initialize values of interrupt throttling rates
1033 1062 */
1034 1063 for (i = 1; i < MAX_NUM_EITR; i++)
1035 1064 igb->intr_throttling[i] = igb->intr_throttling[0];
1036 1065
1037 1066 /*
1038 1067 * The initial link state should be "unknown"
1039 1068 */
1040 1069 igb->link_state = LINK_STATE_UNKNOWN;
1041 1070
1042 1071 return (IGB_SUCCESS);
1043 1072 }
1044 1073
1045 1074 /*
1046 1075 * igb_init_locks - Initialize locks
1047 1076 */
1048 1077 static void
1049 1078 igb_init_locks(igb_t *igb)
1050 1079 {
1051 1080 igb_rx_ring_t *rx_ring;
1052 1081 igb_tx_ring_t *tx_ring;
1053 1082 int i;
1054 1083
1055 1084 for (i = 0; i < igb->num_rx_rings; i++) {
1056 1085 rx_ring = &igb->rx_rings[i];
1057 1086 mutex_init(&rx_ring->rx_lock, NULL,
1058 1087 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1059 1088 }
1060 1089
1061 1090 for (i = 0; i < igb->num_tx_rings; i++) {
1062 1091 tx_ring = &igb->tx_rings[i];
1063 1092 mutex_init(&tx_ring->tx_lock, NULL,
1064 1093 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1065 1094 mutex_init(&tx_ring->recycle_lock, NULL,
1066 1095 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1067 1096 mutex_init(&tx_ring->tcb_head_lock, NULL,
1068 1097 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1069 1098 mutex_init(&tx_ring->tcb_tail_lock, NULL,
1070 1099 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1071 1100 }
1072 1101
1073 1102 mutex_init(&igb->gen_lock, NULL,
1074 1103 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1075 1104
1076 1105 mutex_init(&igb->watchdog_lock, NULL,
1077 1106 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1078 1107
1079 1108 mutex_init(&igb->link_lock, NULL,
1080 1109 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1081 1110 }
1082 1111
1083 1112 /*
1084 1113 * igb_destroy_locks - Destroy locks
1085 1114 */
1086 1115 static void
1087 1116 igb_destroy_locks(igb_t *igb)
1088 1117 {
1089 1118 igb_rx_ring_t *rx_ring;
1090 1119 igb_tx_ring_t *tx_ring;
1091 1120 int i;
1092 1121
1093 1122 for (i = 0; i < igb->num_rx_rings; i++) {
1094 1123 rx_ring = &igb->rx_rings[i];
1095 1124 mutex_destroy(&rx_ring->rx_lock);
1096 1125 }
1097 1126
1098 1127 for (i = 0; i < igb->num_tx_rings; i++) {
1099 1128 tx_ring = &igb->tx_rings[i];
1100 1129 mutex_destroy(&tx_ring->tx_lock);
1101 1130 mutex_destroy(&tx_ring->recycle_lock);
1102 1131 mutex_destroy(&tx_ring->tcb_head_lock);
1103 1132 mutex_destroy(&tx_ring->tcb_tail_lock);
1104 1133 }
1105 1134
1106 1135 mutex_destroy(&igb->gen_lock);
1107 1136 mutex_destroy(&igb->watchdog_lock);
1108 1137 mutex_destroy(&igb->link_lock);
1109 1138 }
1110 1139
1111 1140 static int
1112 1141 igb_resume(dev_info_t *devinfo)
1113 1142 {
1114 1143 igb_t *igb;
1115 1144
1116 1145 igb = (igb_t *)ddi_get_driver_private(devinfo);
1117 1146 if (igb == NULL)
1118 1147 return (DDI_FAILURE);
1119 1148
1120 1149 mutex_enter(&igb->gen_lock);
1121 1150
1122 1151 /*
1123 1152 * Enable interrupts
1124 1153 */
1125 1154 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1126 1155 if (igb_enable_intrs(igb) != IGB_SUCCESS) {
1127 1156 igb_error(igb, "Failed to enable DDI interrupts");
1128 1157 mutex_exit(&igb->gen_lock);
1129 1158 return (DDI_FAILURE);
1130 1159 }
1131 1160 }
1132 1161
1133 1162 if (igb->igb_state & IGB_STARTED) {
1134 1163 if (igb_start(igb, B_FALSE) != IGB_SUCCESS) {
1135 1164 mutex_exit(&igb->gen_lock);
1136 1165 return (DDI_FAILURE);
1137 1166 }
1138 1167
1139 1168 /*
1140 1169 * Enable and start the watchdog timer
1141 1170 */
1142 1171 igb_enable_watchdog_timer(igb);
1143 1172 }
1144 1173
1145 1174 atomic_and_32(&igb->igb_state, ~IGB_SUSPENDED);
1146 1175
1147 1176 mutex_exit(&igb->gen_lock);
1148 1177
1149 1178 return (DDI_SUCCESS);
1150 1179 }
1151 1180
1152 1181 static int
1153 1182 igb_suspend(dev_info_t *devinfo)
1154 1183 {
1155 1184 igb_t *igb;
1156 1185
1157 1186 igb = (igb_t *)ddi_get_driver_private(devinfo);
1158 1187 if (igb == NULL)
1159 1188 return (DDI_FAILURE);
1160 1189
1161 1190 mutex_enter(&igb->gen_lock);
1162 1191
1163 1192 atomic_or_32(&igb->igb_state, IGB_SUSPENDED);
1164 1193
1165 1194 /*
1166 1195 * Disable interrupts
1167 1196 */
1168 1197 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1169 1198 (void) igb_disable_intrs(igb);
1170 1199 }
1171 1200
1172 1201 if (!(igb->igb_state & IGB_STARTED)) {
1173 1202 mutex_exit(&igb->gen_lock);
1174 1203 return (DDI_SUCCESS);
1175 1204 }
1176 1205
1177 1206 igb_stop(igb, B_FALSE);
1178 1207
1179 1208 mutex_exit(&igb->gen_lock);
1180 1209
1181 1210 /*
1182 1211 * Disable and stop the watchdog timer
1183 1212 */
1184 1213 igb_disable_watchdog_timer(igb);
1185 1214
1186 1215 return (DDI_SUCCESS);
1187 1216 }
1188 1217
1189 1218 static int
1190 1219 igb_init(igb_t *igb)
1191 1220 {
1192 1221 mutex_enter(&igb->gen_lock);
1193 1222
1194 1223 /*
1195 1224 * Initilize the adapter
1196 1225 */
1197 1226 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1198 1227 mutex_exit(&igb->gen_lock);
1199 1228 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1200 1229 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1201 1230 return (IGB_FAILURE);
1202 1231 }
1203 1232
1204 1233 mutex_exit(&igb->gen_lock);
1205 1234
1206 1235 return (IGB_SUCCESS);
1207 1236 }
1208 1237
1209 1238 /*
1210 1239 * igb_init_mac_address - Initialize the default MAC address
1211 1240 *
1212 1241 * On success, the MAC address is entered in the igb->hw.mac.addr
1213 1242 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive
1214 1243 * address register.
1215 1244 *
1216 1245 * Important side effects:
1217 1246 * 1. adapter is reset - this is required to put it in a known state.
1218 1247 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where
1219 1248 * MAC address and all default settings are stored, so a valid checksum
1220 1249 * is required.
1221 1250 */
1222 1251 static int
1223 1252 igb_init_mac_address(igb_t *igb)
1224 1253 {
1225 1254 struct e1000_hw *hw = &igb->hw;
1226 1255
1227 1256 ASSERT(mutex_owned(&igb->gen_lock));
1228 1257
1229 1258 /*
1230 1259 * Reset chipset to put the hardware in a known state
1231 1260 * before we try to get MAC address from NVM.
1232 1261 */
1233 1262 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1234 1263 igb_error(igb, "Adapter reset failed.");
1235 1264 goto init_mac_fail;
1236 1265 }
1237 1266
1238 1267 /*
1239 1268 * NVM validation
1240 1269 */
1241 1270 if (((igb->hw.mac.type != e1000_i210) &&
1242 1271 (igb->hw.mac.type != e1000_i211)) &&
1243 1272 (e1000_validate_nvm_checksum(hw) < 0)) {
1244 1273 /*
1245 1274 * Some PCI-E parts fail the first check due to
1246 1275 * the link being in sleep state. Call it again,
1247 1276 * if it fails a second time its a real issue.
1248 1277 */
1249 1278 if (e1000_validate_nvm_checksum(hw) < 0) {
1250 1279 igb_error(igb,
1251 1280 "Invalid NVM checksum. Please contact "
1252 1281 "the vendor to update the NVM.");
1253 1282 goto init_mac_fail;
1254 1283 }
1255 1284 }
1256 1285
1257 1286 /*
1258 1287 * Get the mac address
1259 1288 * This function should handle SPARC case correctly.
1260 1289 */
1261 1290 if (!igb_find_mac_address(igb)) {
1262 1291 igb_error(igb, "Failed to get the mac address");
1263 1292 goto init_mac_fail;
1264 1293 }
1265 1294
1266 1295 /* Validate mac address */
1267 1296 if (!is_valid_mac_addr(hw->mac.addr)) {
1268 1297 igb_error(igb, "Invalid mac address");
1269 1298 goto init_mac_fail;
1270 1299 }
1271 1300
1272 1301 return (IGB_SUCCESS);
1273 1302
1274 1303 init_mac_fail:
1275 1304 return (IGB_FAILURE);
1276 1305 }
1277 1306
1278 1307 /*
1279 1308 * igb_init_adapter - Initialize the adapter
1280 1309 */
1281 1310 static int
1282 1311 igb_init_adapter(igb_t *igb)
1283 1312 {
1284 1313 struct e1000_hw *hw = &igb->hw;
1285 1314 uint32_t pba;
1286 1315 int oemid[2];
1287 1316 uint16_t nvmword;
1288 1317 uint32_t hwm;
1289 1318 uint32_t default_mtu;
1290 1319 u8 pbanum[E1000_PBANUM_LENGTH];
1291 1320 char eepromver[5]; /* f.ff */
1292 1321 int i;
1293 1322
1294 1323 ASSERT(mutex_owned(&igb->gen_lock));
1295 1324
1296 1325 /*
1297 1326 * In order to obtain the default MAC address, this will reset the
1298 1327 * adapter and validate the NVM that the address and many other
1299 1328 * default settings come from.
1300 1329 */
1301 1330 if (igb_init_mac_address(igb) != IGB_SUCCESS) {
1302 1331 igb_error(igb, "Failed to initialize MAC address");
1303 1332 goto init_adapter_fail;
1304 1333 }
1305 1334
1306 1335 /*
1307 1336 * Packet Buffer Allocation (PBA)
1308 1337 * Writing PBA sets the receive portion of the buffer
1309 1338 * the remainder is used for the transmit buffer.
1310 1339 */
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1311 1340 switch (hw->mac.type) {
1312 1341 case e1000_82575:
1313 1342 pba = E1000_PBA_32K;
1314 1343 break;
1315 1344 case e1000_82576:
1316 1345 pba = E1000_READ_REG(hw, E1000_RXPBS);
1317 1346 pba &= E1000_RXPBS_SIZE_MASK_82576;
1318 1347 break;
1319 1348 case e1000_82580:
1320 1349 case e1000_i350:
1350 + case e1000_i354:
1321 1351 pba = E1000_READ_REG(hw, E1000_RXPBS);
1322 1352 pba = e1000_rxpbs_adjust_82580(pba);
1323 1353 break;
1324 1354 case e1000_i210:
1325 1355 case e1000_i211:
1326 1356 pba = E1000_PBA_34K;
1327 1357 default:
1328 1358 break;
1329 1359 }
1330 1360
1331 1361 /* Special needs in case of Jumbo frames */
1332 1362 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU,
1333 1363 MIN_MTU, MAX_MTU, DEFAULT_MTU);
1334 1364 if ((hw->mac.type == e1000_82575) && (default_mtu > ETHERMTU)) {
1335 1365 u32 tx_space, min_tx, min_rx;
1336 1366 pba = E1000_READ_REG(hw, E1000_PBA);
1337 1367 tx_space = pba >> 16;
1338 1368 pba &= 0xffff;
1339 1369 min_tx = (igb->max_frame_size +
1340 1370 sizeof (struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
1341 1371 min_tx = roundup(min_tx, 1024);
1342 1372 min_tx >>= 10;
1343 1373 min_rx = igb->max_frame_size;
1344 1374 min_rx = roundup(min_rx, 1024);
1345 1375 min_rx >>= 10;
1346 1376 if (tx_space < min_tx &&
1347 1377 ((min_tx - tx_space) < pba)) {
1348 1378 pba = pba - (min_tx - tx_space);
1349 1379 /*
1350 1380 * if short on rx space, rx wins
1351 1381 * and must trump tx adjustment
1352 1382 */
1353 1383 if (pba < min_rx)
1354 1384 pba = min_rx;
1355 1385 }
1356 1386 E1000_WRITE_REG(hw, E1000_PBA, pba);
1357 1387 }
1358 1388
1359 1389 DEBUGOUT1("igb_init: pba=%dK", pba);
1360 1390
1361 1391 /*
1362 1392 * These parameters control the automatic generation (Tx) and
1363 1393 * response (Rx) to Ethernet PAUSE frames.
1364 1394 * - High water mark should allow for at least two frames to be
1365 1395 * received after sending an XOFF.
1366 1396 * - Low water mark works best when it is very near the high water mark.
1367 1397 * This allows the receiver to restart by sending XON when it has
1368 1398 * drained a bit.
1369 1399 */
1370 1400 hwm = min(((pba << 10) * 9 / 10),
1371 1401 ((pba << 10) - 2 * igb->max_frame_size));
1372 1402
1373 1403 if (hw->mac.type < e1000_82576) {
1374 1404 hw->fc.high_water = hwm & 0xFFF8; /* 8-byte granularity */
1375 1405 hw->fc.low_water = hw->fc.high_water - 8;
1376 1406 } else {
1377 1407 hw->fc.high_water = hwm & 0xFFF0; /* 16-byte granularity */
1378 1408 hw->fc.low_water = hw->fc.high_water - 16;
1379 1409 }
1380 1410
1381 1411 hw->fc.pause_time = E1000_FC_PAUSE_TIME;
1382 1412 hw->fc.send_xon = B_TRUE;
1383 1413
1384 1414 (void) e1000_validate_mdi_setting(hw);
1385 1415
1386 1416 /*
1387 1417 * Reset the chipset hardware the second time to put PBA settings
1388 1418 * into effect.
1389 1419 */
1390 1420 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1391 1421 igb_error(igb, "Second reset failed");
1392 1422 goto init_adapter_fail;
1393 1423 }
1394 1424
1395 1425 /*
1396 1426 * Don't wait for auto-negotiation to complete
1397 1427 */
1398 1428 hw->phy.autoneg_wait_to_complete = B_FALSE;
1399 1429
1400 1430 /*
1401 1431 * Copper options
1402 1432 */
1403 1433 if (hw->phy.media_type == e1000_media_type_copper) {
1404 1434 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
1405 1435 hw->phy.disable_polarity_correction = B_FALSE;
1406 1436 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */
1407 1437 }
1408 1438
1409 1439 /*
1410 1440 * Initialize link settings
1411 1441 */
1412 1442 (void) igb_setup_link(igb, B_FALSE);
1413 1443
1414 1444 /*
1415 1445 * Configure/Initialize hardware
1416 1446 */
1417 1447 if (e1000_init_hw(hw) != E1000_SUCCESS) {
1418 1448 igb_error(igb, "Failed to initialize hardware");
1419 1449 goto init_adapter_fail;
1420 1450 }
1421 1451
1422 1452 /*
1423 1453 * Start the link setup timer
1424 1454 */
1425 1455 igb_start_link_timer(igb);
1426 1456
1427 1457 /*
1428 1458 * Disable wakeup control by default
1429 1459 */
1430 1460 E1000_WRITE_REG(hw, E1000_WUC, 0);
1431 1461
1432 1462 /*
1433 1463 * Record phy info in hw struct
1434 1464 */
1435 1465 (void) e1000_get_phy_info(hw);
1436 1466
1437 1467 /*
1438 1468 * Make sure driver has control
1439 1469 */
1440 1470 igb_get_driver_control(hw);
1441 1471
1442 1472 /*
1443 1473 * Restore LED settings to the default from EEPROM
1444 1474 * to meet the standard for Sun platforms.
1445 1475 */
1446 1476 (void) e1000_cleanup_led(hw);
1447 1477
1448 1478 /*
1449 1479 * Setup MSI-X interrupts
1450 1480 */
1451 1481 if (igb->intr_type == DDI_INTR_TYPE_MSIX)
1452 1482 igb->capab->setup_msix(igb);
1453 1483
1454 1484 /*
1455 1485 * Initialize unicast addresses.
1456 1486 */
1457 1487 igb_init_unicst(igb);
1458 1488
1459 1489 /*
1460 1490 * Setup and initialize the mctable structures.
1461 1491 */
1462 1492 igb_setup_multicst(igb);
1463 1493
1464 1494 /*
1465 1495 * Set interrupt throttling rate
1466 1496 */
1467 1497 for (i = 0; i < igb->intr_cnt; i++)
1468 1498 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]);
1469 1499
1470 1500 /*
1471 1501 * Read identifying information and place in devinfo.
1472 1502 */
1473 1503 nvmword = 0xffff;
1474 1504 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_0, 1, &nvmword);
1475 1505 oemid[0] = (int)nvmword;
1476 1506 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_1, 1, &nvmword);
1477 1507 oemid[1] = (int)nvmword;
1478 1508 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, igb->dip,
1479 1509 "oem-identifier", oemid, 2);
1480 1510
1481 1511 pbanum[0] = '\0';
1482 1512 (void) e1000_read_pba_string(&igb->hw, pbanum, sizeof (pbanum));
1483 1513 if (*pbanum != '\0') {
1484 1514 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip,
1485 1515 "printed-board-assembly", (char *)pbanum);
1486 1516 }
1487 1517
1488 1518 nvmword = 0xffff;
1489 1519 (void) e1000_read_nvm(&igb->hw, NVM_VERSION, 1, &nvmword);
1490 1520 if ((nvmword & 0xf00) == 0) {
1491 1521 (void) snprintf(eepromver, sizeof (eepromver), "%x.%x",
1492 1522 (nvmword & 0xf000) >> 12, (nvmword & 0xff));
1493 1523 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip,
1494 1524 "nvm-version", eepromver);
1495 1525 }
1496 1526
1497 1527 /*
1498 1528 * Save the state of the phy
1499 1529 */
1500 1530 igb_get_phy_state(igb);
1501 1531
1502 1532 igb_param_sync(igb);
1503 1533
1504 1534 return (IGB_SUCCESS);
1505 1535
1506 1536 init_adapter_fail:
1507 1537 /*
1508 1538 * Reset PHY if possible
1509 1539 */
1510 1540 if (e1000_check_reset_block(hw) == E1000_SUCCESS)
1511 1541 (void) e1000_phy_hw_reset(hw);
1512 1542
1513 1543 return (IGB_FAILURE);
1514 1544 }
1515 1545
1516 1546 /*
1517 1547 * igb_stop_adapter - Stop the adapter
1518 1548 */
1519 1549 static void
1520 1550 igb_stop_adapter(igb_t *igb)
1521 1551 {
1522 1552 struct e1000_hw *hw = &igb->hw;
1523 1553
1524 1554 ASSERT(mutex_owned(&igb->gen_lock));
1525 1555
1526 1556 /* Stop the link setup timer */
1527 1557 igb_stop_link_timer(igb);
1528 1558
1529 1559 /* Tell firmware driver is no longer in control */
1530 1560 igb_release_driver_control(hw);
1531 1561
1532 1562 /*
1533 1563 * Reset the chipset
1534 1564 */
1535 1565 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1536 1566 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1537 1567 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1538 1568 }
1539 1569
1540 1570 /*
1541 1571 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient
1542 1572 */
1543 1573 }
1544 1574
1545 1575 /*
1546 1576 * igb_reset - Reset the chipset and restart the driver.
1547 1577 *
1548 1578 * It involves stopping and re-starting the chipset,
1549 1579 * and re-configuring the rx/tx rings.
1550 1580 */
1551 1581 static int
1552 1582 igb_reset(igb_t *igb)
1553 1583 {
1554 1584 int i;
1555 1585
1556 1586 mutex_enter(&igb->gen_lock);
1557 1587
1558 1588 ASSERT(igb->igb_state & IGB_STARTED);
1559 1589 atomic_and_32(&igb->igb_state, ~IGB_STARTED);
1560 1590
1561 1591 /*
1562 1592 * Disable the adapter interrupts to stop any rx/tx activities
1563 1593 * before draining pending data and resetting hardware.
1564 1594 */
1565 1595 igb_disable_adapter_interrupts(igb);
1566 1596
1567 1597 /*
1568 1598 * Drain the pending transmit packets
1569 1599 */
1570 1600 (void) igb_tx_drain(igb);
1571 1601
1572 1602 for (i = 0; i < igb->num_rx_rings; i++)
1573 1603 mutex_enter(&igb->rx_rings[i].rx_lock);
1574 1604 for (i = 0; i < igb->num_tx_rings; i++)
1575 1605 mutex_enter(&igb->tx_rings[i].tx_lock);
1576 1606
1577 1607 /*
1578 1608 * Stop the adapter
1579 1609 */
1580 1610 igb_stop_adapter(igb);
1581 1611
1582 1612 /*
1583 1613 * Clean the pending tx data/resources
1584 1614 */
1585 1615 igb_tx_clean(igb);
1586 1616
1587 1617 /*
1588 1618 * Start the adapter
1589 1619 */
1590 1620 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1591 1621 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1592 1622 goto reset_failure;
1593 1623 }
1594 1624
1595 1625 /*
1596 1626 * Setup the rx/tx rings
1597 1627 */
1598 1628 igb->tx_ring_init = B_FALSE;
1599 1629 igb_setup_rings(igb);
1600 1630
1601 1631 atomic_and_32(&igb->igb_state, ~(IGB_ERROR | IGB_STALL));
1602 1632
1603 1633 /*
1604 1634 * Enable adapter interrupts
1605 1635 * The interrupts must be enabled after the driver state is START
1606 1636 */
1607 1637 igb->capab->enable_intr(igb);
1608 1638
1609 1639 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
1610 1640 goto reset_failure;
1611 1641
1612 1642 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1613 1643 goto reset_failure;
1614 1644
1615 1645 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1616 1646 mutex_exit(&igb->tx_rings[i].tx_lock);
1617 1647 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1618 1648 mutex_exit(&igb->rx_rings[i].rx_lock);
1619 1649
1620 1650 atomic_or_32(&igb->igb_state, IGB_STARTED);
1621 1651
1622 1652 mutex_exit(&igb->gen_lock);
1623 1653
1624 1654 return (IGB_SUCCESS);
1625 1655
1626 1656 reset_failure:
1627 1657 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1628 1658 mutex_exit(&igb->tx_rings[i].tx_lock);
1629 1659 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1630 1660 mutex_exit(&igb->rx_rings[i].rx_lock);
1631 1661
1632 1662 mutex_exit(&igb->gen_lock);
1633 1663
1634 1664 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1635 1665
1636 1666 return (IGB_FAILURE);
1637 1667 }
1638 1668
1639 1669 /*
1640 1670 * igb_tx_clean - Clean the pending transmit packets and DMA resources
1641 1671 */
1642 1672 static void
1643 1673 igb_tx_clean(igb_t *igb)
1644 1674 {
1645 1675 igb_tx_ring_t *tx_ring;
1646 1676 tx_control_block_t *tcb;
1647 1677 link_list_t pending_list;
1648 1678 uint32_t desc_num;
1649 1679 int i, j;
1650 1680
1651 1681 LINK_LIST_INIT(&pending_list);
1652 1682
1653 1683 for (i = 0; i < igb->num_tx_rings; i++) {
1654 1684 tx_ring = &igb->tx_rings[i];
1655 1685
1656 1686 mutex_enter(&tx_ring->recycle_lock);
1657 1687
1658 1688 /*
1659 1689 * Clean the pending tx data - the pending packets in the
1660 1690 * work_list that have no chances to be transmitted again.
1661 1691 *
1662 1692 * We must ensure the chipset is stopped or the link is down
1663 1693 * before cleaning the transmit packets.
1664 1694 */
1665 1695 desc_num = 0;
1666 1696 for (j = 0; j < tx_ring->ring_size; j++) {
1667 1697 tcb = tx_ring->work_list[j];
1668 1698 if (tcb != NULL) {
1669 1699 desc_num += tcb->desc_num;
1670 1700
1671 1701 tx_ring->work_list[j] = NULL;
1672 1702
1673 1703 igb_free_tcb(tcb);
1674 1704
1675 1705 LIST_PUSH_TAIL(&pending_list, &tcb->link);
1676 1706 }
1677 1707 }
1678 1708
1679 1709 if (desc_num > 0) {
1680 1710 atomic_add_32(&tx_ring->tbd_free, desc_num);
1681 1711 ASSERT(tx_ring->tbd_free == tx_ring->ring_size);
1682 1712
1683 1713 /*
1684 1714 * Reset the head and tail pointers of the tbd ring;
1685 1715 * Reset the head write-back if it is enabled.
1686 1716 */
1687 1717 tx_ring->tbd_head = 0;
1688 1718 tx_ring->tbd_tail = 0;
1689 1719 if (igb->tx_head_wb_enable)
1690 1720 *tx_ring->tbd_head_wb = 0;
1691 1721
1692 1722 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0);
1693 1723 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0);
1694 1724 }
1695 1725
1696 1726 mutex_exit(&tx_ring->recycle_lock);
1697 1727
1698 1728 /*
1699 1729 * Add the tx control blocks in the pending list to
1700 1730 * the free list.
1701 1731 */
1702 1732 igb_put_free_list(tx_ring, &pending_list);
1703 1733 }
1704 1734 }
1705 1735
1706 1736 /*
1707 1737 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted
1708 1738 */
1709 1739 static boolean_t
1710 1740 igb_tx_drain(igb_t *igb)
1711 1741 {
1712 1742 igb_tx_ring_t *tx_ring;
1713 1743 boolean_t done;
1714 1744 int i, j;
1715 1745
1716 1746 /*
1717 1747 * Wait for a specific time to allow pending tx packets
1718 1748 * to be transmitted.
1719 1749 *
1720 1750 * Check the counter tbd_free to see if transmission is done.
1721 1751 * No lock protection is needed here.
1722 1752 *
1723 1753 * Return B_TRUE if all pending packets have been transmitted;
1724 1754 * Otherwise return B_FALSE;
1725 1755 */
1726 1756 for (i = 0; i < TX_DRAIN_TIME; i++) {
1727 1757
1728 1758 done = B_TRUE;
1729 1759 for (j = 0; j < igb->num_tx_rings; j++) {
1730 1760 tx_ring = &igb->tx_rings[j];
1731 1761 done = done &&
1732 1762 (tx_ring->tbd_free == tx_ring->ring_size);
1733 1763 }
1734 1764
1735 1765 if (done)
1736 1766 break;
1737 1767
1738 1768 msec_delay(1);
1739 1769 }
1740 1770
1741 1771 return (done);
1742 1772 }
1743 1773
1744 1774 /*
1745 1775 * igb_rx_drain - Wait for all rx buffers to be released by upper layer
1746 1776 */
1747 1777 static boolean_t
1748 1778 igb_rx_drain(igb_t *igb)
1749 1779 {
1750 1780 boolean_t done;
1751 1781 int i;
1752 1782
1753 1783 /*
1754 1784 * Polling the rx free list to check if those rx buffers held by
1755 1785 * the upper layer are released.
1756 1786 *
1757 1787 * Check the counter rcb_free to see if all pending buffers are
1758 1788 * released. No lock protection is needed here.
1759 1789 *
1760 1790 * Return B_TRUE if all pending buffers have been released;
1761 1791 * Otherwise return B_FALSE;
1762 1792 */
1763 1793 for (i = 0; i < RX_DRAIN_TIME; i++) {
1764 1794 done = (igb->rcb_pending == 0);
1765 1795
1766 1796 if (done)
1767 1797 break;
1768 1798
1769 1799 msec_delay(1);
1770 1800 }
1771 1801
1772 1802 return (done);
1773 1803 }
1774 1804
1775 1805 /*
1776 1806 * igb_start - Start the driver/chipset
1777 1807 */
1778 1808 int
1779 1809 igb_start(igb_t *igb, boolean_t alloc_buffer)
1780 1810 {
1781 1811 int i;
1782 1812
1783 1813 ASSERT(mutex_owned(&igb->gen_lock));
1784 1814
1785 1815 if (alloc_buffer) {
1786 1816 if (igb_alloc_rx_data(igb) != IGB_SUCCESS) {
1787 1817 igb_error(igb,
1788 1818 "Failed to allocate software receive rings");
1789 1819 return (IGB_FAILURE);
1790 1820 }
1791 1821
1792 1822 /* Allocate buffers for all the rx/tx rings */
1793 1823 if (igb_alloc_dma(igb) != IGB_SUCCESS) {
1794 1824 igb_error(igb, "Failed to allocate DMA resource");
1795 1825 return (IGB_FAILURE);
1796 1826 }
1797 1827
1798 1828 igb->tx_ring_init = B_TRUE;
1799 1829 } else {
1800 1830 igb->tx_ring_init = B_FALSE;
1801 1831 }
1802 1832
1803 1833 for (i = 0; i < igb->num_rx_rings; i++)
1804 1834 mutex_enter(&igb->rx_rings[i].rx_lock);
1805 1835 for (i = 0; i < igb->num_tx_rings; i++)
1806 1836 mutex_enter(&igb->tx_rings[i].tx_lock);
1807 1837
1808 1838 /*
1809 1839 * Start the adapter
1810 1840 */
1811 1841 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) {
1812 1842 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1813 1843 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1814 1844 goto start_failure;
1815 1845 }
1816 1846 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
1817 1847 }
1818 1848
1819 1849 /*
1820 1850 * Setup the rx/tx rings
1821 1851 */
1822 1852 igb_setup_rings(igb);
1823 1853
1824 1854 /*
1825 1855 * Enable adapter interrupts
1826 1856 * The interrupts must be enabled after the driver state is START
1827 1857 */
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1828 1858 igb->capab->enable_intr(igb);
1829 1859
1830 1860 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
1831 1861 goto start_failure;
1832 1862
1833 1863 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1834 1864 goto start_failure;
1835 1865
1836 1866 if (igb->hw.mac.type == e1000_i350)
1837 1867 (void) e1000_set_eee_i350(&igb->hw);
1868 + else if (igb->hw.mac.type == e1000_i354)
1869 + (void) e1000_set_eee_i354(&igb->hw);
1838 1870
1839 1871 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1840 1872 mutex_exit(&igb->tx_rings[i].tx_lock);
1841 1873 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1842 1874 mutex_exit(&igb->rx_rings[i].rx_lock);
1843 1875
1844 1876 return (IGB_SUCCESS);
1845 1877
1846 1878 start_failure:
1847 1879 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1848 1880 mutex_exit(&igb->tx_rings[i].tx_lock);
1849 1881 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1850 1882 mutex_exit(&igb->rx_rings[i].rx_lock);
1851 1883
1852 1884 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1853 1885
1854 1886 return (IGB_FAILURE);
1855 1887 }
1856 1888
1857 1889 /*
1858 1890 * igb_stop - Stop the driver/chipset
1859 1891 */
1860 1892 void
1861 1893 igb_stop(igb_t *igb, boolean_t free_buffer)
1862 1894 {
1863 1895 int i;
1864 1896
1865 1897 ASSERT(mutex_owned(&igb->gen_lock));
1866 1898
1867 1899 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER;
1868 1900
1869 1901 /*
1870 1902 * Disable the adapter interrupts
1871 1903 */
1872 1904 igb_disable_adapter_interrupts(igb);
1873 1905
1874 1906 /*
1875 1907 * Drain the pending tx packets
1876 1908 */
1877 1909 (void) igb_tx_drain(igb);
1878 1910
1879 1911 for (i = 0; i < igb->num_rx_rings; i++)
1880 1912 mutex_enter(&igb->rx_rings[i].rx_lock);
1881 1913 for (i = 0; i < igb->num_tx_rings; i++)
1882 1914 mutex_enter(&igb->tx_rings[i].tx_lock);
1883 1915
1884 1916 /*
1885 1917 * Stop the adapter
1886 1918 */
1887 1919 igb_stop_adapter(igb);
1888 1920
1889 1921 /*
1890 1922 * Clean the pending tx data/resources
1891 1923 */
1892 1924 igb_tx_clean(igb);
1893 1925
1894 1926 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1895 1927 mutex_exit(&igb->tx_rings[i].tx_lock);
1896 1928 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1897 1929 mutex_exit(&igb->rx_rings[i].rx_lock);
1898 1930
1899 1931 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1900 1932 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1901 1933
1902 1934 if (igb->link_state == LINK_STATE_UP) {
1903 1935 igb->link_state = LINK_STATE_UNKNOWN;
1904 1936 mac_link_update(igb->mac_hdl, igb->link_state);
1905 1937 }
1906 1938
1907 1939 if (free_buffer) {
1908 1940 /*
1909 1941 * Release the DMA/memory resources of rx/tx rings
1910 1942 */
1911 1943 igb_free_dma(igb);
1912 1944 igb_free_rx_data(igb);
1913 1945 }
1914 1946 }
1915 1947
1916 1948 /*
1917 1949 * igb_alloc_rings - Allocate memory space for rx/tx rings
1918 1950 */
1919 1951 static int
1920 1952 igb_alloc_rings(igb_t *igb)
1921 1953 {
1922 1954 /*
1923 1955 * Allocate memory space for rx rings
1924 1956 */
1925 1957 igb->rx_rings = kmem_zalloc(
1926 1958 sizeof (igb_rx_ring_t) * igb->num_rx_rings,
1927 1959 KM_NOSLEEP);
1928 1960
1929 1961 if (igb->rx_rings == NULL) {
1930 1962 return (IGB_FAILURE);
1931 1963 }
1932 1964
1933 1965 /*
1934 1966 * Allocate memory space for tx rings
1935 1967 */
1936 1968 igb->tx_rings = kmem_zalloc(
1937 1969 sizeof (igb_tx_ring_t) * igb->num_tx_rings,
1938 1970 KM_NOSLEEP);
1939 1971
1940 1972 if (igb->tx_rings == NULL) {
1941 1973 kmem_free(igb->rx_rings,
1942 1974 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1943 1975 igb->rx_rings = NULL;
1944 1976 return (IGB_FAILURE);
1945 1977 }
1946 1978
1947 1979 /*
1948 1980 * Allocate memory space for rx ring groups
1949 1981 */
1950 1982 igb->rx_groups = kmem_zalloc(
1951 1983 sizeof (igb_rx_group_t) * igb->num_rx_groups,
1952 1984 KM_NOSLEEP);
1953 1985
1954 1986 if (igb->rx_groups == NULL) {
1955 1987 kmem_free(igb->rx_rings,
1956 1988 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1957 1989 kmem_free(igb->tx_rings,
1958 1990 sizeof (igb_tx_ring_t) * igb->num_tx_rings);
1959 1991 igb->rx_rings = NULL;
1960 1992 igb->tx_rings = NULL;
1961 1993 return (IGB_FAILURE);
1962 1994 }
1963 1995
1964 1996 return (IGB_SUCCESS);
1965 1997 }
1966 1998
1967 1999 /*
1968 2000 * igb_free_rings - Free the memory space of rx/tx rings.
1969 2001 */
1970 2002 static void
1971 2003 igb_free_rings(igb_t *igb)
1972 2004 {
1973 2005 if (igb->rx_rings != NULL) {
1974 2006 kmem_free(igb->rx_rings,
1975 2007 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1976 2008 igb->rx_rings = NULL;
1977 2009 }
1978 2010
1979 2011 if (igb->tx_rings != NULL) {
1980 2012 kmem_free(igb->tx_rings,
1981 2013 sizeof (igb_tx_ring_t) * igb->num_tx_rings);
1982 2014 igb->tx_rings = NULL;
1983 2015 }
1984 2016
1985 2017 if (igb->rx_groups != NULL) {
1986 2018 kmem_free(igb->rx_groups,
1987 2019 sizeof (igb_rx_group_t) * igb->num_rx_groups);
1988 2020 igb->rx_groups = NULL;
1989 2021 }
1990 2022 }
1991 2023
1992 2024 static int
1993 2025 igb_alloc_rx_data(igb_t *igb)
1994 2026 {
1995 2027 igb_rx_ring_t *rx_ring;
1996 2028 int i;
1997 2029
1998 2030 for (i = 0; i < igb->num_rx_rings; i++) {
1999 2031 rx_ring = &igb->rx_rings[i];
2000 2032 if (igb_alloc_rx_ring_data(rx_ring) != IGB_SUCCESS)
2001 2033 goto alloc_rx_rings_failure;
2002 2034 }
2003 2035 return (IGB_SUCCESS);
2004 2036
2005 2037 alloc_rx_rings_failure:
2006 2038 igb_free_rx_data(igb);
2007 2039 return (IGB_FAILURE);
2008 2040 }
2009 2041
2010 2042 static void
2011 2043 igb_free_rx_data(igb_t *igb)
2012 2044 {
2013 2045 igb_rx_ring_t *rx_ring;
2014 2046 igb_rx_data_t *rx_data;
2015 2047 int i;
2016 2048
2017 2049 for (i = 0; i < igb->num_rx_rings; i++) {
2018 2050 rx_ring = &igb->rx_rings[i];
2019 2051
2020 2052 mutex_enter(&igb->rx_pending_lock);
2021 2053 rx_data = rx_ring->rx_data;
2022 2054
2023 2055 if (rx_data != NULL) {
2024 2056 rx_data->flag |= IGB_RX_STOPPED;
2025 2057
2026 2058 if (rx_data->rcb_pending == 0) {
2027 2059 igb_free_rx_ring_data(rx_data);
2028 2060 rx_ring->rx_data = NULL;
2029 2061 }
2030 2062 }
2031 2063
2032 2064 mutex_exit(&igb->rx_pending_lock);
2033 2065 }
2034 2066 }
2035 2067
2036 2068 /*
2037 2069 * igb_setup_rings - Setup rx/tx rings
2038 2070 */
2039 2071 static void
2040 2072 igb_setup_rings(igb_t *igb)
2041 2073 {
2042 2074 /*
2043 2075 * Setup the rx/tx rings, including the following:
2044 2076 *
2045 2077 * 1. Setup the descriptor ring and the control block buffers;
2046 2078 * 2. Initialize necessary registers for receive/transmit;
2047 2079 * 3. Initialize software pointers/parameters for receive/transmit;
2048 2080 */
2049 2081 igb_setup_rx(igb);
2050 2082
2051 2083 igb_setup_tx(igb);
2052 2084 }
2053 2085
2054 2086 static void
2055 2087 igb_setup_rx_ring(igb_rx_ring_t *rx_ring)
2056 2088 {
2057 2089 igb_t *igb = rx_ring->igb;
2058 2090 igb_rx_data_t *rx_data = rx_ring->rx_data;
2059 2091 struct e1000_hw *hw = &igb->hw;
2060 2092 rx_control_block_t *rcb;
2061 2093 union e1000_adv_rx_desc *rbd;
2062 2094 uint32_t size;
2063 2095 uint32_t buf_low;
2064 2096 uint32_t buf_high;
2065 2097 uint32_t rxdctl;
2066 2098 int i;
2067 2099
2068 2100 ASSERT(mutex_owned(&rx_ring->rx_lock));
2069 2101 ASSERT(mutex_owned(&igb->gen_lock));
2070 2102
2071 2103 /*
2072 2104 * Initialize descriptor ring with buffer addresses
2073 2105 */
2074 2106 for (i = 0; i < igb->rx_ring_size; i++) {
2075 2107 rcb = rx_data->work_list[i];
2076 2108 rbd = &rx_data->rbd_ring[i];
2077 2109
2078 2110 rbd->read.pkt_addr = rcb->rx_buf.dma_address;
2079 2111 rbd->read.hdr_addr = NULL;
2080 2112 }
2081 2113
2082 2114 /*
2083 2115 * Initialize the base address registers
2084 2116 */
2085 2117 buf_low = (uint32_t)rx_data->rbd_area.dma_address;
2086 2118 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32);
2087 2119 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high);
2088 2120 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low);
2089 2121
2090 2122 /*
2091 2123 * Initialize the length register
2092 2124 */
2093 2125 size = rx_data->ring_size * sizeof (union e1000_adv_rx_desc);
2094 2126 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size);
2095 2127
2096 2128 /*
2097 2129 * Initialize buffer size & descriptor type
2098 2130 */
2099 2131 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index),
2100 2132 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) |
2101 2133 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF));
2102 2134
2103 2135 /*
2104 2136 * Setup the Receive Descriptor Control Register (RXDCTL)
2105 2137 */
2106 2138 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index));
2107 2139 rxdctl &= igb->capab->rxdctl_mask;
2108 2140 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2109 2141 rxdctl |= 16; /* pthresh */
2110 2142 rxdctl |= 8 << 8; /* hthresh */
2111 2143 rxdctl |= 1 << 16; /* wthresh */
2112 2144 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl);
2113 2145
2114 2146 rx_data->rbd_next = 0;
2115 2147 }
2116 2148
2117 2149 static void
2118 2150 igb_setup_rx(igb_t *igb)
2119 2151 {
2120 2152 igb_rx_ring_t *rx_ring;
2121 2153 igb_rx_data_t *rx_data;
2122 2154 igb_rx_group_t *rx_group;
2123 2155 struct e1000_hw *hw = &igb->hw;
2124 2156 uint32_t rctl, rxcsum;
2125 2157 uint32_t ring_per_group;
2126 2158 int i;
2127 2159
2128 2160 /*
2129 2161 * Setup the Receive Control Register (RCTL), and enable the
2130 2162 * receiver. The initial configuration is to: enable the receiver,
2131 2163 * accept broadcasts, discard bad packets, accept long packets,
2132 2164 * disable VLAN filter checking, and set receive buffer size to
2133 2165 * 2k. For 82575, also set the receive descriptor minimum
2134 2166 * threshold size to 1/2 the ring.
2135 2167 */
2136 2168 rctl = E1000_READ_REG(hw, E1000_RCTL);
2137 2169
2138 2170 /*
2139 2171 * Clear the field used for wakeup control. This driver doesn't do
2140 2172 * wakeup but leave this here for completeness.
2141 2173 */
2142 2174 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2143 2175 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2144 2176
2145 2177 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */
2146 2178 E1000_RCTL_BAM | /* Accept Broadcast Packets */
2147 2179 E1000_RCTL_LPE | /* Large Packet Enable */
2148 2180 /* Multicast filter offset */
2149 2181 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) |
2150 2182 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */
2151 2183 E1000_RCTL_SECRC); /* Strip Ethernet CRC */
2152 2184
2153 2185 for (i = 0; i < igb->num_rx_groups; i++) {
2154 2186 rx_group = &igb->rx_groups[i];
2155 2187 rx_group->index = i;
2156 2188 rx_group->igb = igb;
2157 2189 }
2158 2190
2159 2191 /*
2160 2192 * Set up all rx descriptor rings - must be called before receive unit
2161 2193 * enabled.
2162 2194 */
2163 2195 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2164 2196 for (i = 0; i < igb->num_rx_rings; i++) {
2165 2197 rx_ring = &igb->rx_rings[i];
2166 2198 igb_setup_rx_ring(rx_ring);
2167 2199
2168 2200 /*
2169 2201 * Map a ring to a group by assigning a group index
2170 2202 */
2171 2203 rx_ring->group_index = i / ring_per_group;
2172 2204 }
2173 2205
2174 2206 /*
2175 2207 * Setup the Rx Long Packet Max Length register
2176 2208 */
2177 2209 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size);
2178 2210
2179 2211 /*
2180 2212 * Hardware checksum settings
2181 2213 */
2182 2214 if (igb->rx_hcksum_enable) {
2183 2215 rxcsum =
2184 2216 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */
2185 2217 E1000_RXCSUM_IPOFL; /* IP checksum */
2186 2218
2187 2219 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2188 2220 }
2189 2221
2190 2222 /*
2191 2223 * Setup classify and RSS for multiple receive queues
2192 2224 */
2193 2225 switch (igb->vmdq_mode) {
2194 2226 case E1000_VMDQ_OFF:
2195 2227 /*
2196 2228 * One ring group, only RSS is needed when more than
2197 2229 * one ring enabled.
2198 2230 */
2199 2231 if (igb->num_rx_rings > 1)
2200 2232 igb_setup_rss(igb);
2201 2233 break;
2202 2234 case E1000_VMDQ_MAC:
2203 2235 /*
2204 2236 * Multiple groups, each group has one ring,
2205 2237 * only the MAC classification is needed.
2206 2238 */
2207 2239 igb_setup_mac_classify(igb);
2208 2240 break;
2209 2241 case E1000_VMDQ_MAC_RSS:
2210 2242 /*
2211 2243 * Multiple groups and multiple rings, both
2212 2244 * MAC classification and RSS are needed.
2213 2245 */
2214 2246 igb_setup_mac_rss_classify(igb);
2215 2247 break;
2216 2248 }
2217 2249
2218 2250 /*
2219 2251 * Enable the receive unit - must be done after all
2220 2252 * the rx setup above.
2221 2253 */
2222 2254 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2223 2255
2224 2256 /*
2225 2257 * Initialize all adapter ring head & tail pointers - must
2226 2258 * be done after receive unit is enabled
2227 2259 */
2228 2260 for (i = 0; i < igb->num_rx_rings; i++) {
2229 2261 rx_ring = &igb->rx_rings[i];
2230 2262 rx_data = rx_ring->rx_data;
2231 2263 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2232 2264 E1000_WRITE_REG(hw, E1000_RDT(i), rx_data->ring_size - 1);
2233 2265 }
2234 2266
2235 2267 /*
2236 2268 * 82575 with manageability enabled needs a special flush to make
2237 2269 * sure the fifos start clean.
2238 2270 */
2239 2271 if ((hw->mac.type == e1000_82575) &&
2240 2272 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) {
2241 2273 e1000_rx_fifo_flush_82575(hw);
2242 2274 }
2243 2275 }
2244 2276
2245 2277 static void
2246 2278 igb_setup_tx_ring(igb_tx_ring_t *tx_ring)
2247 2279 {
2248 2280 igb_t *igb = tx_ring->igb;
2249 2281 struct e1000_hw *hw = &igb->hw;
2250 2282 uint32_t size;
2251 2283 uint32_t buf_low;
2252 2284 uint32_t buf_high;
2253 2285 uint32_t reg_val;
2254 2286
2255 2287 ASSERT(mutex_owned(&tx_ring->tx_lock));
2256 2288 ASSERT(mutex_owned(&igb->gen_lock));
2257 2289
2258 2290
2259 2291 /*
2260 2292 * Initialize the length register
2261 2293 */
2262 2294 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc);
2263 2295 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size);
2264 2296
2265 2297 /*
2266 2298 * Initialize the base address registers
2267 2299 */
2268 2300 buf_low = (uint32_t)tx_ring->tbd_area.dma_address;
2269 2301 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32);
2270 2302 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low);
2271 2303 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high);
2272 2304
2273 2305 /*
2274 2306 * Setup head & tail pointers
2275 2307 */
2276 2308 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0);
2277 2309 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0);
2278 2310
2279 2311 /*
2280 2312 * Setup head write-back
2281 2313 */
2282 2314 if (igb->tx_head_wb_enable) {
2283 2315 /*
2284 2316 * The memory of the head write-back is allocated using
2285 2317 * the extra tbd beyond the tail of the tbd ring.
2286 2318 */
2287 2319 tx_ring->tbd_head_wb = (uint32_t *)
2288 2320 ((uintptr_t)tx_ring->tbd_area.address + size);
2289 2321 *tx_ring->tbd_head_wb = 0;
2290 2322
2291 2323 buf_low = (uint32_t)
2292 2324 (tx_ring->tbd_area.dma_address + size);
2293 2325 buf_high = (uint32_t)
2294 2326 ((tx_ring->tbd_area.dma_address + size) >> 32);
2295 2327
2296 2328 /* Set the head write-back enable bit */
2297 2329 buf_low |= E1000_TX_HEAD_WB_ENABLE;
2298 2330
2299 2331 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low);
2300 2332 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high);
2301 2333
2302 2334 /*
2303 2335 * Turn off relaxed ordering for head write back or it will
2304 2336 * cause problems with the tx recycling
2305 2337 */
2306 2338 reg_val = E1000_READ_REG(hw,
2307 2339 E1000_DCA_TXCTRL(tx_ring->index));
2308 2340 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
2309 2341 E1000_WRITE_REG(hw,
2310 2342 E1000_DCA_TXCTRL(tx_ring->index), reg_val);
2311 2343 } else {
2312 2344 tx_ring->tbd_head_wb = NULL;
2313 2345 }
2314 2346
2315 2347 tx_ring->tbd_head = 0;
2316 2348 tx_ring->tbd_tail = 0;
2317 2349 tx_ring->tbd_free = tx_ring->ring_size;
2318 2350
2319 2351 if (igb->tx_ring_init == B_TRUE) {
2320 2352 tx_ring->tcb_head = 0;
2321 2353 tx_ring->tcb_tail = 0;
2322 2354 tx_ring->tcb_free = tx_ring->free_list_size;
2323 2355 }
2324 2356
2325 2357 /*
2326 2358 * Enable TXDCTL per queue
2327 2359 */
2328 2360 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index));
2329 2361 reg_val |= E1000_TXDCTL_QUEUE_ENABLE;
2330 2362 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val);
2331 2363
2332 2364 /*
2333 2365 * Initialize hardware checksum offload settings
2334 2366 */
2335 2367 bzero(&tx_ring->tx_context, sizeof (tx_context_t));
2336 2368 }
2337 2369
2338 2370 static void
2339 2371 igb_setup_tx(igb_t *igb)
2340 2372 {
2341 2373 igb_tx_ring_t *tx_ring;
2342 2374 struct e1000_hw *hw = &igb->hw;
2343 2375 uint32_t reg_val;
2344 2376 int i;
2345 2377
2346 2378 for (i = 0; i < igb->num_tx_rings; i++) {
2347 2379 tx_ring = &igb->tx_rings[i];
2348 2380 igb_setup_tx_ring(tx_ring);
2349 2381 }
2350 2382
2351 2383 /*
2352 2384 * Setup the Transmit Control Register (TCTL)
2353 2385 */
2354 2386 reg_val = E1000_READ_REG(hw, E1000_TCTL);
2355 2387 reg_val &= ~E1000_TCTL_CT;
2356 2388 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2357 2389 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2358 2390
2359 2391 /* Enable transmits */
2360 2392 reg_val |= E1000_TCTL_EN;
2361 2393
2362 2394 E1000_WRITE_REG(hw, E1000_TCTL, reg_val);
2363 2395 }
2364 2396
2365 2397 /*
2366 2398 * igb_setup_rss - Setup receive-side scaling feature
2367 2399 */
2368 2400 static void
2369 2401 igb_setup_rss(igb_t *igb)
2370 2402 {
2371 2403 struct e1000_hw *hw = &igb->hw;
2372 2404 uint32_t i, mrqc, rxcsum;
2373 2405 int shift = 0;
2374 2406 uint32_t random;
2375 2407 union e1000_reta {
2376 2408 uint32_t dword;
2377 2409 uint8_t bytes[4];
2378 2410 } reta;
2379 2411
2380 2412 /* Setup the Redirection Table */
2381 2413 if (hw->mac.type == e1000_82576) {
2382 2414 shift = 3;
2383 2415 } else if (hw->mac.type == e1000_82575) {
2384 2416 shift = 6;
2385 2417 }
2386 2418 for (i = 0; i < (32 * 4); i++) {
2387 2419 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift;
2388 2420 if ((i & 3) == 3) {
2389 2421 E1000_WRITE_REG(hw,
2390 2422 (E1000_RETA(0) + (i & ~3)), reta.dword);
2391 2423 }
2392 2424 }
2393 2425
2394 2426 /* Fill out hash function seeds */
2395 2427 for (i = 0; i < 10; i++) {
2396 2428 (void) random_get_pseudo_bytes((uint8_t *)&random,
2397 2429 sizeof (uint32_t));
2398 2430 E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
2399 2431 }
2400 2432
2401 2433 /* Setup the Multiple Receive Queue Control register */
2402 2434 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2403 2435 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2404 2436 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2405 2437 E1000_MRQC_RSS_FIELD_IPV6 |
2406 2438 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2407 2439 E1000_MRQC_RSS_FIELD_IPV4_UDP |
2408 2440 E1000_MRQC_RSS_FIELD_IPV6_UDP |
2409 2441 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2410 2442 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2411 2443
2412 2444 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2413 2445
2414 2446 /*
2415 2447 * Disable Packet Checksum to enable RSS for multiple receive queues.
2416 2448 *
2417 2449 * The Packet Checksum is not ethernet CRC. It is another kind of
2418 2450 * checksum offloading provided by the 82575 chipset besides the IP
2419 2451 * header checksum offloading and the TCP/UDP checksum offloading.
2420 2452 * The Packet Checksum is by default computed over the entire packet
2421 2453 * from the first byte of the DA through the last byte of the CRC,
2422 2454 * including the Ethernet and IP headers.
2423 2455 *
2424 2456 * It is a hardware limitation that Packet Checksum is mutually
2425 2457 * exclusive with RSS.
2426 2458 */
2427 2459 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2428 2460 rxcsum |= E1000_RXCSUM_PCSD;
2429 2461 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2430 2462 }
2431 2463
2432 2464 /*
2433 2465 * igb_setup_mac_rss_classify - Setup MAC classification and rss
2434 2466 */
2435 2467 static void
2436 2468 igb_setup_mac_rss_classify(igb_t *igb)
2437 2469 {
2438 2470 struct e1000_hw *hw = &igb->hw;
2439 2471 uint32_t i, mrqc, vmdctl, rxcsum;
2440 2472 uint32_t ring_per_group;
2441 2473 int shift_group0, shift_group1;
2442 2474 uint32_t random;
2443 2475 union e1000_reta {
2444 2476 uint32_t dword;
2445 2477 uint8_t bytes[4];
2446 2478 } reta;
2447 2479
2448 2480 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2449 2481
2450 2482 /* Setup the Redirection Table, it is shared between two groups */
2451 2483 shift_group0 = 2;
2452 2484 shift_group1 = 6;
2453 2485 for (i = 0; i < (32 * 4); i++) {
2454 2486 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) |
2455 2487 ((ring_per_group + (i % ring_per_group)) << shift_group1);
2456 2488 if ((i & 3) == 3) {
2457 2489 E1000_WRITE_REG(hw,
2458 2490 (E1000_RETA(0) + (i & ~3)), reta.dword);
2459 2491 }
2460 2492 }
2461 2493
2462 2494 /* Fill out hash function seeds */
2463 2495 for (i = 0; i < 10; i++) {
2464 2496 (void) random_get_pseudo_bytes((uint8_t *)&random,
2465 2497 sizeof (uint32_t));
2466 2498 E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
2467 2499 }
2468 2500
2469 2501 /*
2470 2502 * Setup the Multiple Receive Queue Control register,
2471 2503 * enable VMDq based on packet destination MAC address and RSS.
2472 2504 */
2473 2505 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP;
2474 2506 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2475 2507 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2476 2508 E1000_MRQC_RSS_FIELD_IPV6 |
2477 2509 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2478 2510 E1000_MRQC_RSS_FIELD_IPV4_UDP |
2479 2511 E1000_MRQC_RSS_FIELD_IPV6_UDP |
2480 2512 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2481 2513 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2482 2514
2483 2515 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2484 2516
2485 2517
2486 2518 /* Define the default group and default queues */
2487 2519 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE;
2488 2520 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl);
2489 2521
2490 2522 /*
2491 2523 * Disable Packet Checksum to enable RSS for multiple receive queues.
2492 2524 *
2493 2525 * The Packet Checksum is not ethernet CRC. It is another kind of
2494 2526 * checksum offloading provided by the 82575 chipset besides the IP
2495 2527 * header checksum offloading and the TCP/UDP checksum offloading.
2496 2528 * The Packet Checksum is by default computed over the entire packet
2497 2529 * from the first byte of the DA through the last byte of the CRC,
2498 2530 * including the Ethernet and IP headers.
2499 2531 *
2500 2532 * It is a hardware limitation that Packet Checksum is mutually
2501 2533 * exclusive with RSS.
2502 2534 */
2503 2535 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2504 2536 rxcsum |= E1000_RXCSUM_PCSD;
2505 2537 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2506 2538 }
2507 2539
2508 2540 /*
2509 2541 * igb_setup_mac_classify - Setup MAC classification feature
2510 2542 */
2511 2543 static void
2512 2544 igb_setup_mac_classify(igb_t *igb)
2513 2545 {
2514 2546 struct e1000_hw *hw = &igb->hw;
2515 2547 uint32_t mrqc, rxcsum;
2516 2548
2517 2549 /*
2518 2550 * Setup the Multiple Receive Queue Control register,
2519 2551 * enable VMDq based on packet destination MAC address.
2520 2552 */
2521 2553 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP;
2522 2554 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2523 2555
2524 2556 /*
2525 2557 * Disable Packet Checksum to enable RSS for multiple receive queues.
2526 2558 *
2527 2559 * The Packet Checksum is not ethernet CRC. It is another kind of
2528 2560 * checksum offloading provided by the 82575 chipset besides the IP
2529 2561 * header checksum offloading and the TCP/UDP checksum offloading.
2530 2562 * The Packet Checksum is by default computed over the entire packet
2531 2563 * from the first byte of the DA through the last byte of the CRC,
2532 2564 * including the Ethernet and IP headers.
2533 2565 *
2534 2566 * It is a hardware limitation that Packet Checksum is mutually
2535 2567 * exclusive with RSS.
2536 2568 */
2537 2569 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2538 2570 rxcsum |= E1000_RXCSUM_PCSD;
2539 2571 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2540 2572
2541 2573 }
2542 2574
2543 2575 /*
2544 2576 * igb_init_unicst - Initialize the unicast addresses
2545 2577 */
2546 2578 static void
2547 2579 igb_init_unicst(igb_t *igb)
2548 2580 {
2549 2581 struct e1000_hw *hw = &igb->hw;
2550 2582 int slot;
2551 2583
2552 2584 /*
2553 2585 * Here we should consider two situations:
2554 2586 *
2555 2587 * 1. Chipset is initialized the first time
2556 2588 * Initialize the multiple unicast addresses, and
2557 2589 * save the default MAC address.
2558 2590 *
2559 2591 * 2. Chipset is reset
2560 2592 * Recover the multiple unicast addresses from the
2561 2593 * software data structure to the RAR registers.
2562 2594 */
2563 2595
2564 2596 /*
2565 2597 * Clear the default MAC address in the RAR0 rgister,
2566 2598 * which is loaded from EEPROM when system boot or chipreset,
2567 2599 * this will cause the conficts with add_mac/rem_mac entry
2568 2600 * points when VMDq is enabled. For this reason, the RAR0
2569 2601 * must be cleared for both cases mentioned above.
2570 2602 */
2571 2603 e1000_rar_clear(hw, 0);
2572 2604
2573 2605 if (!igb->unicst_init) {
2574 2606
2575 2607 /* Initialize the multiple unicast addresses */
2576 2608 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES;
2577 2609 igb->unicst_avail = igb->unicst_total;
2578 2610
2579 2611 for (slot = 0; slot < igb->unicst_total; slot++)
2580 2612 igb->unicst_addr[slot].mac.set = 0;
2581 2613
2582 2614 igb->unicst_init = B_TRUE;
2583 2615 } else {
2584 2616 /* Re-configure the RAR registers */
2585 2617 for (slot = 0; slot < igb->unicst_total; slot++) {
2586 2618 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr,
2587 2619 slot, igb->vmdq_mode,
2588 2620 igb->unicst_addr[slot].mac.group_index);
2589 2621 }
2590 2622 }
2591 2623 }
2592 2624
2593 2625 /*
2594 2626 * igb_unicst_find - Find the slot for the specified unicast address
2595 2627 */
2596 2628 int
2597 2629 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr)
2598 2630 {
2599 2631 int slot;
2600 2632
2601 2633 ASSERT(mutex_owned(&igb->gen_lock));
2602 2634
2603 2635 for (slot = 0; slot < igb->unicst_total; slot++) {
2604 2636 if (bcmp(igb->unicst_addr[slot].mac.addr,
2605 2637 mac_addr, ETHERADDRL) == 0)
2606 2638 return (slot);
2607 2639 }
2608 2640
2609 2641 return (-1);
2610 2642 }
2611 2643
2612 2644 /*
2613 2645 * igb_unicst_set - Set the unicast address to the specified slot
2614 2646 */
2615 2647 int
2616 2648 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr,
2617 2649 int slot)
2618 2650 {
2619 2651 struct e1000_hw *hw = &igb->hw;
2620 2652
2621 2653 ASSERT(mutex_owned(&igb->gen_lock));
2622 2654
2623 2655 /*
2624 2656 * Save the unicast address in the software data structure
2625 2657 */
2626 2658 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL);
2627 2659
2628 2660 /*
2629 2661 * Set the unicast address to the RAR register
2630 2662 */
2631 2663 e1000_rar_set(hw, (uint8_t *)mac_addr, slot);
2632 2664
2633 2665 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2634 2666 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2635 2667 return (EIO);
2636 2668 }
2637 2669
2638 2670 return (0);
2639 2671 }
2640 2672
2641 2673 /*
2642 2674 * igb_multicst_add - Add a multicst address
2643 2675 */
2644 2676 int
2645 2677 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr)
2646 2678 {
2647 2679 struct ether_addr *new_table;
2648 2680 size_t new_len;
2649 2681 size_t old_len;
2650 2682
2651 2683 ASSERT(mutex_owned(&igb->gen_lock));
2652 2684
2653 2685 if ((multiaddr[0] & 01) == 0) {
2654 2686 igb_error(igb, "Illegal multicast address");
2655 2687 return (EINVAL);
2656 2688 }
2657 2689
2658 2690 if (igb->mcast_count >= igb->mcast_max_num) {
2659 2691 igb_error(igb, "Adapter requested more than %d mcast addresses",
2660 2692 igb->mcast_max_num);
2661 2693 return (ENOENT);
2662 2694 }
2663 2695
2664 2696 if (igb->mcast_count == igb->mcast_alloc_count) {
2665 2697 old_len = igb->mcast_alloc_count *
2666 2698 sizeof (struct ether_addr);
2667 2699 new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) *
2668 2700 sizeof (struct ether_addr);
2669 2701
2670 2702 new_table = kmem_alloc(new_len, KM_NOSLEEP);
2671 2703 if (new_table == NULL) {
2672 2704 igb_error(igb,
2673 2705 "Not enough memory to alloc mcast table");
2674 2706 return (ENOMEM);
2675 2707 }
2676 2708
2677 2709 if (igb->mcast_table != NULL) {
2678 2710 bcopy(igb->mcast_table, new_table, old_len);
2679 2711 kmem_free(igb->mcast_table, old_len);
2680 2712 }
2681 2713 igb->mcast_alloc_count += MCAST_ALLOC_COUNT;
2682 2714 igb->mcast_table = new_table;
2683 2715 }
2684 2716
2685 2717 bcopy(multiaddr,
2686 2718 &igb->mcast_table[igb->mcast_count], ETHERADDRL);
2687 2719 igb->mcast_count++;
2688 2720
2689 2721 /*
2690 2722 * Update the multicast table in the hardware
2691 2723 */
2692 2724 igb_setup_multicst(igb);
2693 2725
2694 2726 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2695 2727 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2696 2728 return (EIO);
2697 2729 }
2698 2730
2699 2731 return (0);
2700 2732 }
2701 2733
2702 2734 /*
2703 2735 * igb_multicst_remove - Remove a multicst address
2704 2736 */
2705 2737 int
2706 2738 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr)
2707 2739 {
2708 2740 struct ether_addr *new_table;
2709 2741 size_t new_len;
2710 2742 size_t old_len;
2711 2743 int i;
2712 2744
2713 2745 ASSERT(mutex_owned(&igb->gen_lock));
2714 2746
2715 2747 for (i = 0; i < igb->mcast_count; i++) {
2716 2748 if (bcmp(multiaddr, &igb->mcast_table[i],
2717 2749 ETHERADDRL) == 0) {
2718 2750 for (i++; i < igb->mcast_count; i++) {
2719 2751 igb->mcast_table[i - 1] =
2720 2752 igb->mcast_table[i];
2721 2753 }
2722 2754 igb->mcast_count--;
2723 2755 break;
2724 2756 }
2725 2757 }
2726 2758
2727 2759 if ((igb->mcast_alloc_count - igb->mcast_count) >
2728 2760 MCAST_ALLOC_COUNT) {
2729 2761 old_len = igb->mcast_alloc_count *
2730 2762 sizeof (struct ether_addr);
2731 2763 new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) *
2732 2764 sizeof (struct ether_addr);
2733 2765
2734 2766 new_table = kmem_alloc(new_len, KM_NOSLEEP);
2735 2767 if (new_table != NULL) {
2736 2768 bcopy(igb->mcast_table, new_table, new_len);
2737 2769 kmem_free(igb->mcast_table, old_len);
2738 2770 igb->mcast_alloc_count -= MCAST_ALLOC_COUNT;
2739 2771 igb->mcast_table = new_table;
2740 2772 }
2741 2773 }
2742 2774
2743 2775 /*
2744 2776 * Update the multicast table in the hardware
2745 2777 */
2746 2778 igb_setup_multicst(igb);
2747 2779
2748 2780 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2749 2781 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2750 2782 return (EIO);
2751 2783 }
2752 2784
2753 2785 return (0);
2754 2786 }
2755 2787
2756 2788 static void
2757 2789 igb_release_multicast(igb_t *igb)
2758 2790 {
2759 2791 if (igb->mcast_table != NULL) {
2760 2792 kmem_free(igb->mcast_table,
2761 2793 igb->mcast_alloc_count * sizeof (struct ether_addr));
2762 2794 igb->mcast_table = NULL;
2763 2795 }
2764 2796 }
2765 2797
2766 2798 /*
2767 2799 * igb_setup_multicast - setup multicast data structures
2768 2800 *
2769 2801 * This routine initializes all of the multicast related structures
2770 2802 * and save them in the hardware registers.
2771 2803 */
2772 2804 static void
2773 2805 igb_setup_multicst(igb_t *igb)
2774 2806 {
2775 2807 uint8_t *mc_addr_list;
2776 2808 uint32_t mc_addr_count;
2777 2809 struct e1000_hw *hw = &igb->hw;
2778 2810
2779 2811 ASSERT(mutex_owned(&igb->gen_lock));
2780 2812 ASSERT(igb->mcast_count <= igb->mcast_max_num);
2781 2813
2782 2814 mc_addr_list = (uint8_t *)igb->mcast_table;
2783 2815 mc_addr_count = igb->mcast_count;
2784 2816
2785 2817 /*
2786 2818 * Update the multicase addresses to the MTA registers
2787 2819 */
2788 2820 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count);
2789 2821 }
2790 2822
2791 2823 /*
2792 2824 * igb_get_conf - Get driver configurations set in driver.conf
2793 2825 *
2794 2826 * This routine gets user-configured values out of the configuration
2795 2827 * file igb.conf.
2796 2828 *
2797 2829 * For each configurable value, there is a minimum, a maximum, and a
2798 2830 * default.
2799 2831 * If user does not configure a value, use the default.
2800 2832 * If user configures below the minimum, use the minumum.
2801 2833 * If user configures above the maximum, use the maxumum.
2802 2834 */
2803 2835 static void
2804 2836 igb_get_conf(igb_t *igb)
2805 2837 {
2806 2838 struct e1000_hw *hw = &igb->hw;
2807 2839 uint32_t default_mtu;
2808 2840 uint32_t flow_control;
2809 2841 uint32_t ring_per_group;
2810 2842 int i;
2811 2843
2812 2844 /*
2813 2845 * igb driver supports the following user configurations:
2814 2846 *
2815 2847 * Link configurations:
2816 2848 * adv_autoneg_cap
2817 2849 * adv_1000fdx_cap
2818 2850 * adv_100fdx_cap
2819 2851 * adv_100hdx_cap
2820 2852 * adv_10fdx_cap
2821 2853 * adv_10hdx_cap
2822 2854 * Note: 1000hdx is not supported.
2823 2855 *
2824 2856 * Jumbo frame configuration:
2825 2857 * default_mtu
2826 2858 *
2827 2859 * Ethernet flow control configuration:
2828 2860 * flow_control
2829 2861 *
2830 2862 * Multiple rings configurations:
2831 2863 * tx_queue_number
2832 2864 * tx_ring_size
2833 2865 * rx_queue_number
2834 2866 * rx_ring_size
2835 2867 *
2836 2868 * Call igb_get_prop() to get the value for a specific
2837 2869 * configuration parameter.
2838 2870 */
2839 2871
2840 2872 /*
2841 2873 * Link configurations
2842 2874 */
2843 2875 igb->param_adv_autoneg_cap = igb_get_prop(igb,
2844 2876 PROP_ADV_AUTONEG_CAP, 0, 1, 1);
2845 2877 igb->param_adv_1000fdx_cap = igb_get_prop(igb,
2846 2878 PROP_ADV_1000FDX_CAP, 0, 1, 1);
2847 2879 igb->param_adv_100fdx_cap = igb_get_prop(igb,
2848 2880 PROP_ADV_100FDX_CAP, 0, 1, 1);
2849 2881 igb->param_adv_100hdx_cap = igb_get_prop(igb,
2850 2882 PROP_ADV_100HDX_CAP, 0, 1, 1);
2851 2883 igb->param_adv_10fdx_cap = igb_get_prop(igb,
2852 2884 PROP_ADV_10FDX_CAP, 0, 1, 1);
2853 2885 igb->param_adv_10hdx_cap = igb_get_prop(igb,
2854 2886 PROP_ADV_10HDX_CAP, 0, 1, 1);
2855 2887
2856 2888 /*
2857 2889 * Jumbo frame configurations
2858 2890 */
2859 2891 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU,
2860 2892 MIN_MTU, MAX_MTU, DEFAULT_MTU);
2861 2893
2862 2894 igb->max_frame_size = default_mtu +
2863 2895 sizeof (struct ether_vlan_header) + ETHERFCSL;
2864 2896
2865 2897 /*
2866 2898 * Ethernet flow control configuration
2867 2899 */
2868 2900 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL,
2869 2901 e1000_fc_none, 4, e1000_fc_full);
2870 2902 if (flow_control == 4)
2871 2903 flow_control = e1000_fc_default;
2872 2904
2873 2905 hw->fc.requested_mode = flow_control;
2874 2906
2875 2907 /*
2876 2908 * Multiple rings configurations
2877 2909 */
2878 2910 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE,
2879 2911 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE);
2880 2912 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE,
2881 2913 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE);
2882 2914
2883 2915 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0);
2884 2916 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM,
2885 2917 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM);
2886 2918 /*
2887 2919 * Currently we do not support VMDq for 82576 and 82580.
2888 2920 * If it is e1000_82576, set num_rx_groups to 1.
2889 2921 */
2890 2922 if (hw->mac.type >= e1000_82576)
2891 2923 igb->num_rx_groups = 1;
2892 2924
2893 2925 if (igb->mr_enable) {
2894 2926 igb->num_tx_rings = igb->capab->def_tx_que_num;
2895 2927 igb->num_rx_rings = igb->capab->def_rx_que_num;
2896 2928 } else {
2897 2929 igb->num_tx_rings = 1;
2898 2930 igb->num_rx_rings = 1;
2899 2931
2900 2932 if (igb->num_rx_groups > 1) {
2901 2933 igb_error(igb,
2902 2934 "Invalid rx groups number. Please enable multiple "
2903 2935 "rings first");
2904 2936 igb->num_rx_groups = 1;
2905 2937 }
2906 2938 }
2907 2939
2908 2940 /*
2909 2941 * Check the divisibility between rx rings and rx groups.
2910 2942 */
2911 2943 for (i = igb->num_rx_groups; i > 0; i--) {
2912 2944 if ((igb->num_rx_rings % i) == 0)
2913 2945 break;
2914 2946 }
2915 2947 if (i != igb->num_rx_groups) {
2916 2948 igb_error(igb,
2917 2949 "Invalid rx groups number. Downgrade the rx group "
2918 2950 "number to %d.", i);
2919 2951 igb->num_rx_groups = i;
2920 2952 }
2921 2953
2922 2954 /*
2923 2955 * Get the ring number per group.
2924 2956 */
2925 2957 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2926 2958
2927 2959 if (igb->num_rx_groups == 1) {
2928 2960 /*
2929 2961 * One rx ring group, the rx ring number is num_rx_rings.
2930 2962 */
2931 2963 igb->vmdq_mode = E1000_VMDQ_OFF;
2932 2964 } else if (ring_per_group == 1) {
2933 2965 /*
2934 2966 * Multiple rx groups, each group has one rx ring.
2935 2967 */
2936 2968 igb->vmdq_mode = E1000_VMDQ_MAC;
2937 2969 } else {
2938 2970 /*
2939 2971 * Multiple groups and multiple rings.
2940 2972 */
2941 2973 igb->vmdq_mode = E1000_VMDQ_MAC_RSS;
2942 2974 }
2943 2975
2944 2976 /*
2945 2977 * Tunable used to force an interrupt type. The only use is
2946 2978 * for testing of the lesser interrupt types.
2947 2979 * 0 = don't force interrupt type
2948 2980 * 1 = force interrupt type MSIX
2949 2981 * 2 = force interrupt type MSI
2950 2982 * 3 = force interrupt type Legacy
2951 2983 */
2952 2984 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE,
2953 2985 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE);
2954 2986
2955 2987 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE,
2956 2988 0, 1, 1);
2957 2989 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE,
2958 2990 0, 1, 1);
2959 2991 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE,
2960 2992 0, 1, 1);
2961 2993 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE,
2962 2994 0, 1, 1);
2963 2995
2964 2996 /*
2965 2997 * igb LSO needs the tx h/w checksum support.
2966 2998 * Here LSO will be disabled if tx h/w checksum has been disabled.
2967 2999 */
2968 3000 if (igb->tx_hcksum_enable == B_FALSE)
2969 3001 igb->lso_enable = B_FALSE;
2970 3002
2971 3003 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD,
2972 3004 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD,
2973 3005 DEFAULT_TX_COPY_THRESHOLD);
2974 3006 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD,
2975 3007 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD,
2976 3008 DEFAULT_TX_RECYCLE_THRESHOLD);
2977 3009 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD,
2978 3010 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD,
2979 3011 DEFAULT_TX_OVERLOAD_THRESHOLD);
2980 3012 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD,
2981 3013 MIN_TX_RESCHED_THRESHOLD,
2982 3014 MIN(igb->tx_ring_size, MAX_TX_RESCHED_THRESHOLD),
2983 3015 igb->tx_ring_size > DEFAULT_TX_RESCHED_THRESHOLD ?
2984 3016 DEFAULT_TX_RESCHED_THRESHOLD : DEFAULT_TX_RESCHED_THRESHOLD_LOW);
2985 3017
2986 3018 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD,
2987 3019 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD,
2988 3020 DEFAULT_RX_COPY_THRESHOLD);
2989 3021 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR,
2990 3022 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR,
2991 3023 DEFAULT_RX_LIMIT_PER_INTR);
2992 3024
2993 3025 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING,
2994 3026 igb->capab->min_intr_throttle,
2995 3027 igb->capab->max_intr_throttle,
2996 3028 igb->capab->def_intr_throttle);
2997 3029
2998 3030 /*
2999 3031 * Max number of multicast addresses
3000 3032 */
3001 3033 igb->mcast_max_num =
3002 3034 igb_get_prop(igb, PROP_MCAST_MAX_NUM,
3003 3035 MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM);
3004 3036 }
3005 3037
3006 3038 /*
3007 3039 * igb_get_prop - Get a property value out of the configuration file igb.conf
3008 3040 *
3009 3041 * Caller provides the name of the property, a default value, a minimum
3010 3042 * value, and a maximum value.
3011 3043 *
3012 3044 * Return configured value of the property, with default, minimum and
3013 3045 * maximum properly applied.
3014 3046 */
3015 3047 static int
3016 3048 igb_get_prop(igb_t *igb,
3017 3049 char *propname, /* name of the property */
3018 3050 int minval, /* minimum acceptable value */
3019 3051 int maxval, /* maximim acceptable value */
3020 3052 int defval) /* default value */
3021 3053 {
3022 3054 int value;
3023 3055
3024 3056 /*
3025 3057 * Call ddi_prop_get_int() to read the conf settings
3026 3058 */
3027 3059 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip,
3028 3060 DDI_PROP_DONTPASS, propname, defval);
3029 3061
3030 3062 if (value > maxval)
3031 3063 value = maxval;
3032 3064
3033 3065 if (value < minval)
3034 3066 value = minval;
3035 3067
3036 3068 return (value);
3037 3069 }
3038 3070
3039 3071 /*
3040 3072 * igb_setup_link - Using the link properties to setup the link
3041 3073 */
3042 3074 int
3043 3075 igb_setup_link(igb_t *igb, boolean_t setup_hw)
3044 3076 {
3045 3077 struct e1000_mac_info *mac;
3046 3078 struct e1000_phy_info *phy;
3047 3079 boolean_t invalid;
3048 3080
3049 3081 mac = &igb->hw.mac;
3050 3082 phy = &igb->hw.phy;
3051 3083 invalid = B_FALSE;
3052 3084
3053 3085 if (igb->param_adv_autoneg_cap == 1) {
3054 3086 mac->autoneg = B_TRUE;
3055 3087 phy->autoneg_advertised = 0;
3056 3088
3057 3089 /*
3058 3090 * 1000hdx is not supported for autonegotiation
3059 3091 */
3060 3092 if (igb->param_adv_1000fdx_cap == 1)
3061 3093 phy->autoneg_advertised |= ADVERTISE_1000_FULL;
3062 3094
3063 3095 if (igb->param_adv_100fdx_cap == 1)
3064 3096 phy->autoneg_advertised |= ADVERTISE_100_FULL;
3065 3097
3066 3098 if (igb->param_adv_100hdx_cap == 1)
3067 3099 phy->autoneg_advertised |= ADVERTISE_100_HALF;
3068 3100
3069 3101 if (igb->param_adv_10fdx_cap == 1)
3070 3102 phy->autoneg_advertised |= ADVERTISE_10_FULL;
3071 3103
3072 3104 if (igb->param_adv_10hdx_cap == 1)
3073 3105 phy->autoneg_advertised |= ADVERTISE_10_HALF;
3074 3106
3075 3107 if (phy->autoneg_advertised == 0)
3076 3108 invalid = B_TRUE;
3077 3109 } else {
3078 3110 mac->autoneg = B_FALSE;
3079 3111
3080 3112 /*
3081 3113 * 1000fdx and 1000hdx are not supported for forced link
3082 3114 */
3083 3115 if (igb->param_adv_100fdx_cap == 1)
3084 3116 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3085 3117 else if (igb->param_adv_100hdx_cap == 1)
3086 3118 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3087 3119 else if (igb->param_adv_10fdx_cap == 1)
3088 3120 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3089 3121 else if (igb->param_adv_10hdx_cap == 1)
3090 3122 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3091 3123 else
3092 3124 invalid = B_TRUE;
3093 3125 }
3094 3126
3095 3127 if (invalid) {
3096 3128 igb_notice(igb, "Invalid link settings. Setup link to "
3097 3129 "autonegotiation with full link capabilities.");
3098 3130 mac->autoneg = B_TRUE;
3099 3131 phy->autoneg_advertised = ADVERTISE_1000_FULL |
3100 3132 ADVERTISE_100_FULL | ADVERTISE_100_HALF |
3101 3133 ADVERTISE_10_FULL | ADVERTISE_10_HALF;
3102 3134 }
3103 3135
3104 3136 if (setup_hw) {
3105 3137 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS)
3106 3138 return (IGB_FAILURE);
3107 3139 }
3108 3140
3109 3141 return (IGB_SUCCESS);
3110 3142 }
3111 3143
3112 3144
3113 3145 /*
3114 3146 * igb_is_link_up - Check if the link is up
3115 3147 */
3116 3148 static boolean_t
3117 3149 igb_is_link_up(igb_t *igb)
3118 3150 {
3119 3151 struct e1000_hw *hw = &igb->hw;
3120 3152 boolean_t link_up = B_FALSE;
3121 3153
3122 3154 ASSERT(mutex_owned(&igb->gen_lock));
3123 3155
3124 3156 /*
3125 3157 * get_link_status is set in the interrupt handler on link-status-change
3126 3158 * or rx sequence error interrupt. get_link_status will stay
3127 3159 * false until the e1000_check_for_link establishes link only
3128 3160 * for copper adapters.
3129 3161 */
3130 3162 switch (hw->phy.media_type) {
3131 3163 case e1000_media_type_copper:
3132 3164 if (hw->mac.get_link_status) {
3133 3165 (void) e1000_check_for_link(hw);
3134 3166 link_up = !hw->mac.get_link_status;
3135 3167 } else {
3136 3168 link_up = B_TRUE;
3137 3169 }
3138 3170 break;
3139 3171 case e1000_media_type_fiber:
3140 3172 (void) e1000_check_for_link(hw);
3141 3173 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
3142 3174 break;
3143 3175 case e1000_media_type_internal_serdes:
3144 3176 (void) e1000_check_for_link(hw);
3145 3177 link_up = hw->mac.serdes_has_link;
3146 3178 break;
3147 3179 }
3148 3180
3149 3181 return (link_up);
3150 3182 }
3151 3183
3152 3184 /*
3153 3185 * igb_link_check - Link status processing
3154 3186 */
3155 3187 static boolean_t
3156 3188 igb_link_check(igb_t *igb)
3157 3189 {
3158 3190 struct e1000_hw *hw = &igb->hw;
3159 3191 uint16_t speed = 0, duplex = 0;
3160 3192 boolean_t link_changed = B_FALSE;
3161 3193
3162 3194 ASSERT(mutex_owned(&igb->gen_lock));
3163 3195
3164 3196 if (igb_is_link_up(igb)) {
3165 3197 /*
3166 3198 * The Link is up, check whether it was marked as down earlier
3167 3199 */
3168 3200 if (igb->link_state != LINK_STATE_UP) {
3169 3201 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex);
3170 3202 igb->link_speed = speed;
3171 3203 igb->link_duplex = duplex;
3172 3204 igb->link_state = LINK_STATE_UP;
3173 3205 link_changed = B_TRUE;
3174 3206 if (!igb->link_complete)
3175 3207 igb_stop_link_timer(igb);
3176 3208 }
3177 3209 } else if (igb->link_complete) {
3178 3210 if (igb->link_state != LINK_STATE_DOWN) {
3179 3211 igb->link_speed = 0;
3180 3212 igb->link_duplex = 0;
3181 3213 igb->link_state = LINK_STATE_DOWN;
3182 3214 link_changed = B_TRUE;
3183 3215 }
3184 3216 }
3185 3217
3186 3218 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3187 3219 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3188 3220 return (B_FALSE);
3189 3221 }
3190 3222
3191 3223 return (link_changed);
3192 3224 }
3193 3225
3194 3226 /*
3195 3227 * igb_local_timer - driver watchdog function
3196 3228 *
3197 3229 * This function will handle the hardware stall check, link status
3198 3230 * check and other routines.
3199 3231 */
3200 3232 static void
3201 3233 igb_local_timer(void *arg)
3202 3234 {
3203 3235 igb_t *igb = (igb_t *)arg;
3204 3236 boolean_t link_changed = B_FALSE;
3205 3237
3206 3238 if (igb->igb_state & IGB_ERROR) {
3207 3239 igb->reset_count++;
3208 3240 if (igb_reset(igb) == IGB_SUCCESS)
3209 3241 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
3210 3242
3211 3243 igb_restart_watchdog_timer(igb);
3212 3244 return;
3213 3245 }
3214 3246
3215 3247 if (igb_stall_check(igb) || (igb->igb_state & IGB_STALL)) {
3216 3248 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL);
3217 3249 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
3218 3250 igb->reset_count++;
3219 3251 if (igb_reset(igb) == IGB_SUCCESS)
3220 3252 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
3221 3253
3222 3254 igb_restart_watchdog_timer(igb);
3223 3255 return;
3224 3256 }
3225 3257
3226 3258 mutex_enter(&igb->gen_lock);
3227 3259 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED))
3228 3260 link_changed = igb_link_check(igb);
3229 3261 mutex_exit(&igb->gen_lock);
3230 3262
3231 3263 if (link_changed)
3232 3264 mac_link_update(igb->mac_hdl, igb->link_state);
3233 3265
3234 3266 igb_restart_watchdog_timer(igb);
3235 3267 }
3236 3268
3237 3269 /*
3238 3270 * igb_link_timer - link setup timer function
3239 3271 *
3240 3272 * It is called when the timer for link setup is expired, which indicates
3241 3273 * the completion of the link setup. The link state will not be updated
3242 3274 * until the link setup is completed. And the link state will not be sent
3243 3275 * to the upper layer through mac_link_update() in this function. It will
3244 3276 * be updated in the local timer routine or the interrupts service routine
3245 3277 * after the interface is started (plumbed).
3246 3278 */
3247 3279 static void
3248 3280 igb_link_timer(void *arg)
3249 3281 {
3250 3282 igb_t *igb = (igb_t *)arg;
3251 3283
3252 3284 mutex_enter(&igb->link_lock);
3253 3285 igb->link_complete = B_TRUE;
3254 3286 igb->link_tid = 0;
3255 3287 mutex_exit(&igb->link_lock);
3256 3288 }
3257 3289 /*
3258 3290 * igb_stall_check - check for transmit stall
3259 3291 *
3260 3292 * This function checks if the adapter is stalled (in transmit).
3261 3293 *
3262 3294 * It is called each time the watchdog timeout is invoked.
3263 3295 * If the transmit descriptor reclaim continuously fails,
3264 3296 * the watchdog value will increment by 1. If the watchdog
3265 3297 * value exceeds the threshold, the igb is assumed to
3266 3298 * have stalled and need to be reset.
3267 3299 */
3268 3300 static boolean_t
3269 3301 igb_stall_check(igb_t *igb)
3270 3302 {
3271 3303 igb_tx_ring_t *tx_ring;
3272 3304 struct e1000_hw *hw = &igb->hw;
3273 3305 boolean_t result;
3274 3306 int i;
3275 3307
3276 3308 if (igb->link_state != LINK_STATE_UP)
3277 3309 return (B_FALSE);
3278 3310
3279 3311 /*
3280 3312 * If any tx ring is stalled, we'll reset the chipset
3281 3313 */
3282 3314 result = B_FALSE;
3283 3315 for (i = 0; i < igb->num_tx_rings; i++) {
3284 3316 tx_ring = &igb->tx_rings[i];
3285 3317
3286 3318 if (tx_ring->recycle_fail > 0)
3287 3319 tx_ring->stall_watchdog++;
3288 3320 else
3289 3321 tx_ring->stall_watchdog = 0;
3290 3322
3291 3323 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) {
3292 3324 result = B_TRUE;
3293 3325 if (hw->mac.type == e1000_82580) {
3294 3326 hw->dev_spec._82575.global_device_reset
3295 3327 = B_TRUE;
3296 3328 }
3297 3329 break;
3298 3330 }
3299 3331 }
3300 3332
3301 3333 if (result) {
3302 3334 tx_ring->stall_watchdog = 0;
3303 3335 tx_ring->recycle_fail = 0;
3304 3336 }
3305 3337
3306 3338 return (result);
3307 3339 }
3308 3340
3309 3341
3310 3342 /*
3311 3343 * is_valid_mac_addr - Check if the mac address is valid
3312 3344 */
3313 3345 static boolean_t
3314 3346 is_valid_mac_addr(uint8_t *mac_addr)
3315 3347 {
3316 3348 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 };
3317 3349 const uint8_t addr_test2[6] =
3318 3350 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3319 3351
3320 3352 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) ||
3321 3353 !(bcmp(addr_test2, mac_addr, ETHERADDRL)))
3322 3354 return (B_FALSE);
3323 3355
3324 3356 return (B_TRUE);
3325 3357 }
3326 3358
3327 3359 static boolean_t
3328 3360 igb_find_mac_address(igb_t *igb)
3329 3361 {
3330 3362 struct e1000_hw *hw = &igb->hw;
3331 3363 #ifdef __sparc
3332 3364 uchar_t *bytes;
3333 3365 struct ether_addr sysaddr;
3334 3366 uint_t nelts;
3335 3367 int err;
3336 3368 boolean_t found = B_FALSE;
3337 3369
3338 3370 /*
3339 3371 * The "vendor's factory-set address" may already have
3340 3372 * been extracted from the chip, but if the property
3341 3373 * "local-mac-address" is set we use that instead.
3342 3374 *
3343 3375 * We check whether it looks like an array of 6
3344 3376 * bytes (which it should, if OBP set it). If we can't
3345 3377 * make sense of it this way, we'll ignore it.
3346 3378 */
3347 3379 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
3348 3380 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts);
3349 3381 if (err == DDI_PROP_SUCCESS) {
3350 3382 if (nelts == ETHERADDRL) {
3351 3383 while (nelts--)
3352 3384 hw->mac.addr[nelts] = bytes[nelts];
3353 3385 found = B_TRUE;
3354 3386 }
3355 3387 ddi_prop_free(bytes);
3356 3388 }
3357 3389
3358 3390 /*
3359 3391 * Look up the OBP property "local-mac-address?". If the user has set
3360 3392 * 'local-mac-address? = false', use "the system address" instead.
3361 3393 */
3362 3394 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0,
3363 3395 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) {
3364 3396 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) {
3365 3397 if (localetheraddr(NULL, &sysaddr) != 0) {
3366 3398 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
3367 3399 found = B_TRUE;
3368 3400 }
3369 3401 }
3370 3402 ddi_prop_free(bytes);
3371 3403 }
3372 3404
3373 3405 /*
3374 3406 * Finally(!), if there's a valid "mac-address" property (created
3375 3407 * if we netbooted from this interface), we must use this instead
3376 3408 * of any of the above to ensure that the NFS/install server doesn't
3377 3409 * get confused by the address changing as Solaris takes over!
3378 3410 */
3379 3411 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
3380 3412 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts);
3381 3413 if (err == DDI_PROP_SUCCESS) {
3382 3414 if (nelts == ETHERADDRL) {
3383 3415 while (nelts--)
3384 3416 hw->mac.addr[nelts] = bytes[nelts];
3385 3417 found = B_TRUE;
3386 3418 }
3387 3419 ddi_prop_free(bytes);
3388 3420 }
3389 3421
3390 3422 if (found) {
3391 3423 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL);
3392 3424 return (B_TRUE);
3393 3425 }
3394 3426 #endif
3395 3427
3396 3428 /*
3397 3429 * Read the device MAC address from the EEPROM
3398 3430 */
3399 3431 if (e1000_read_mac_addr(hw) != E1000_SUCCESS)
3400 3432 return (B_FALSE);
3401 3433
3402 3434 return (B_TRUE);
3403 3435 }
3404 3436
3405 3437 #pragma inline(igb_arm_watchdog_timer)
3406 3438
3407 3439 static void
3408 3440 igb_arm_watchdog_timer(igb_t *igb)
3409 3441 {
3410 3442 /*
3411 3443 * Fire a watchdog timer
3412 3444 */
3413 3445 igb->watchdog_tid =
3414 3446 timeout(igb_local_timer,
3415 3447 (void *)igb, 1 * drv_usectohz(1000000));
3416 3448
3417 3449 }
3418 3450
3419 3451 /*
3420 3452 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer
3421 3453 */
3422 3454 void
3423 3455 igb_enable_watchdog_timer(igb_t *igb)
3424 3456 {
3425 3457 mutex_enter(&igb->watchdog_lock);
3426 3458
3427 3459 if (!igb->watchdog_enable) {
3428 3460 igb->watchdog_enable = B_TRUE;
3429 3461 igb->watchdog_start = B_TRUE;
3430 3462 igb_arm_watchdog_timer(igb);
3431 3463 }
3432 3464
3433 3465 mutex_exit(&igb->watchdog_lock);
3434 3466
3435 3467 }
3436 3468
3437 3469 /*
3438 3470 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer
3439 3471 */
3440 3472 void
3441 3473 igb_disable_watchdog_timer(igb_t *igb)
3442 3474 {
3443 3475 timeout_id_t tid;
3444 3476
3445 3477 mutex_enter(&igb->watchdog_lock);
3446 3478
3447 3479 igb->watchdog_enable = B_FALSE;
3448 3480 igb->watchdog_start = B_FALSE;
3449 3481 tid = igb->watchdog_tid;
3450 3482 igb->watchdog_tid = 0;
3451 3483
3452 3484 mutex_exit(&igb->watchdog_lock);
3453 3485
3454 3486 if (tid != 0)
3455 3487 (void) untimeout(tid);
3456 3488
3457 3489 }
3458 3490
3459 3491 /*
3460 3492 * igb_start_watchdog_timer - Start the driver watchdog timer
3461 3493 */
3462 3494 static void
3463 3495 igb_start_watchdog_timer(igb_t *igb)
3464 3496 {
3465 3497 mutex_enter(&igb->watchdog_lock);
3466 3498
3467 3499 if (igb->watchdog_enable) {
3468 3500 if (!igb->watchdog_start) {
3469 3501 igb->watchdog_start = B_TRUE;
3470 3502 igb_arm_watchdog_timer(igb);
3471 3503 }
3472 3504 }
3473 3505
3474 3506 mutex_exit(&igb->watchdog_lock);
3475 3507 }
3476 3508
3477 3509 /*
3478 3510 * igb_restart_watchdog_timer - Restart the driver watchdog timer
3479 3511 */
3480 3512 static void
3481 3513 igb_restart_watchdog_timer(igb_t *igb)
3482 3514 {
3483 3515 mutex_enter(&igb->watchdog_lock);
3484 3516
3485 3517 if (igb->watchdog_start)
3486 3518 igb_arm_watchdog_timer(igb);
3487 3519
3488 3520 mutex_exit(&igb->watchdog_lock);
3489 3521 }
3490 3522
3491 3523 /*
3492 3524 * igb_stop_watchdog_timer - Stop the driver watchdog timer
3493 3525 */
3494 3526 static void
3495 3527 igb_stop_watchdog_timer(igb_t *igb)
3496 3528 {
3497 3529 timeout_id_t tid;
3498 3530
3499 3531 mutex_enter(&igb->watchdog_lock);
3500 3532
3501 3533 igb->watchdog_start = B_FALSE;
3502 3534 tid = igb->watchdog_tid;
3503 3535 igb->watchdog_tid = 0;
3504 3536
3505 3537 mutex_exit(&igb->watchdog_lock);
3506 3538
3507 3539 if (tid != 0)
3508 3540 (void) untimeout(tid);
3509 3541 }
3510 3542
3511 3543 /*
3512 3544 * igb_start_link_timer - Start the link setup timer
3513 3545 */
3514 3546 static void
3515 3547 igb_start_link_timer(struct igb *igb)
3516 3548 {
3517 3549 struct e1000_hw *hw = &igb->hw;
3518 3550 clock_t link_timeout;
3519 3551
3520 3552 if (hw->mac.autoneg)
3521 3553 link_timeout = PHY_AUTO_NEG_LIMIT *
3522 3554 drv_usectohz(100000);
3523 3555 else
3524 3556 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000);
3525 3557
3526 3558 mutex_enter(&igb->link_lock);
3527 3559 if (hw->phy.autoneg_wait_to_complete) {
3528 3560 igb->link_complete = B_TRUE;
3529 3561 } else {
3530 3562 igb->link_complete = B_FALSE;
3531 3563 igb->link_tid = timeout(igb_link_timer, (void *)igb,
3532 3564 link_timeout);
3533 3565 }
3534 3566 mutex_exit(&igb->link_lock);
3535 3567 }
3536 3568
3537 3569 /*
3538 3570 * igb_stop_link_timer - Stop the link setup timer
3539 3571 */
3540 3572 static void
3541 3573 igb_stop_link_timer(struct igb *igb)
3542 3574 {
3543 3575 timeout_id_t tid;
3544 3576
3545 3577 mutex_enter(&igb->link_lock);
3546 3578 igb->link_complete = B_TRUE;
3547 3579 tid = igb->link_tid;
3548 3580 igb->link_tid = 0;
3549 3581 mutex_exit(&igb->link_lock);
3550 3582
3551 3583 if (tid != 0)
3552 3584 (void) untimeout(tid);
3553 3585 }
3554 3586
3555 3587 /*
3556 3588 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts
3557 3589 */
3558 3590 static void
3559 3591 igb_disable_adapter_interrupts(igb_t *igb)
3560 3592 {
3561 3593 struct e1000_hw *hw = &igb->hw;
3562 3594
3563 3595 /*
3564 3596 * Set the IMC register to mask all the interrupts,
3565 3597 * including the tx interrupts.
3566 3598 */
3567 3599 E1000_WRITE_REG(hw, E1000_IMC, ~0);
3568 3600 E1000_WRITE_REG(hw, E1000_IAM, 0);
3569 3601
3570 3602 /*
3571 3603 * Additional disabling for MSI-X
3572 3604 */
3573 3605 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3574 3606 E1000_WRITE_REG(hw, E1000_EIMC, ~0);
3575 3607 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3576 3608 E1000_WRITE_REG(hw, E1000_EIAM, 0);
3577 3609 }
3578 3610
3579 3611 E1000_WRITE_FLUSH(hw);
3580 3612 }
3581 3613
3582 3614 /*
3583 3615 * igb_enable_adapter_interrupts_82580 - Enable NIC interrupts for 82580
3584 3616 */
3585 3617 static void
3586 3618 igb_enable_adapter_interrupts_82580(igb_t *igb)
3587 3619 {
3588 3620 struct e1000_hw *hw = &igb->hw;
3589 3621
3590 3622 /* Clear any pending interrupts */
3591 3623 (void) E1000_READ_REG(hw, E1000_ICR);
3592 3624 igb->ims_mask |= E1000_IMS_DRSTA;
3593 3625
3594 3626 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3595 3627
3596 3628 /* Interrupt enabling for MSI-X */
3597 3629 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3598 3630 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3599 3631 igb->ims_mask = (E1000_IMS_LSC | E1000_IMS_DRSTA);
3600 3632 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
3601 3633 } else { /* Interrupt enabling for MSI and legacy */
3602 3634 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
3603 3635 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
3604 3636 igb->ims_mask |= E1000_IMS_DRSTA;
3605 3637 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
3606 3638 }
3607 3639
3608 3640 /* Disable auto-mask for ICR interrupt bits */
3609 3641 E1000_WRITE_REG(hw, E1000_IAM, 0);
3610 3642
3611 3643 E1000_WRITE_FLUSH(hw);
3612 3644 }
3613 3645
3614 3646 /*
3615 3647 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576
3616 3648 */
3617 3649 static void
3618 3650 igb_enable_adapter_interrupts_82576(igb_t *igb)
3619 3651 {
3620 3652 struct e1000_hw *hw = &igb->hw;
3621 3653
3622 3654 /* Clear any pending interrupts */
3623 3655 (void) E1000_READ_REG(hw, E1000_ICR);
3624 3656
3625 3657 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3626 3658
3627 3659 /* Interrupt enabling for MSI-X */
3628 3660 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3629 3661 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3630 3662 igb->ims_mask = E1000_IMS_LSC;
3631 3663 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3632 3664 } else {
3633 3665 /* Interrupt enabling for MSI and legacy */
3634 3666 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
3635 3667 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
3636 3668 E1000_WRITE_REG(hw, E1000_IMS,
3637 3669 (IMS_ENABLE_MASK | E1000_IMS_TXQE));
3638 3670 }
3639 3671
3640 3672 /* Disable auto-mask for ICR interrupt bits */
3641 3673 E1000_WRITE_REG(hw, E1000_IAM, 0);
3642 3674
3643 3675 E1000_WRITE_FLUSH(hw);
3644 3676 }
3645 3677
3646 3678 /*
3647 3679 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575
3648 3680 */
3649 3681 static void
3650 3682 igb_enable_adapter_interrupts_82575(igb_t *igb)
3651 3683 {
3652 3684 struct e1000_hw *hw = &igb->hw;
3653 3685 uint32_t reg;
3654 3686
3655 3687 /* Clear any pending interrupts */
3656 3688 (void) E1000_READ_REG(hw, E1000_ICR);
3657 3689
3658 3690 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3659 3691 /* Interrupt enabling for MSI-X */
3660 3692 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3661 3693 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3662 3694 igb->ims_mask = E1000_IMS_LSC;
3663 3695 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3664 3696
3665 3697 /* Enable MSI-X PBA support */
3666 3698 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
3667 3699 reg |= E1000_CTRL_EXT_PBA_CLR;
3668 3700
3669 3701 /* Non-selective interrupt clear-on-read */
3670 3702 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */
3671 3703
3672 3704 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
3673 3705 } else {
3674 3706 /* Interrupt enabling for MSI and legacy */
3675 3707 igb->ims_mask = IMS_ENABLE_MASK;
3676 3708 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3677 3709 }
3678 3710
3679 3711 E1000_WRITE_FLUSH(hw);
3680 3712 }
3681 3713
3682 3714 /*
3683 3715 * Loopback Support
3684 3716 */
3685 3717 static lb_property_t lb_normal =
3686 3718 { normal, "normal", IGB_LB_NONE };
3687 3719 static lb_property_t lb_external =
3688 3720 { external, "External", IGB_LB_EXTERNAL };
3689 3721 static lb_property_t lb_phy =
3690 3722 { internal, "PHY", IGB_LB_INTERNAL_PHY };
3691 3723 static lb_property_t lb_serdes =
3692 3724 { internal, "SerDes", IGB_LB_INTERNAL_SERDES };
3693 3725
3694 3726 enum ioc_reply
3695 3727 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp)
3696 3728 {
3697 3729 lb_info_sz_t *lbsp;
3698 3730 lb_property_t *lbpp;
3699 3731 struct e1000_hw *hw;
3700 3732 uint32_t *lbmp;
3701 3733 uint32_t size;
3702 3734 uint32_t value;
3703 3735
3704 3736 hw = &igb->hw;
3705 3737
3706 3738 if (mp->b_cont == NULL)
3707 3739 return (IOC_INVAL);
3708 3740
3709 3741 switch (iocp->ioc_cmd) {
3710 3742 default:
3711 3743 return (IOC_INVAL);
3712 3744
3713 3745 case LB_GET_INFO_SIZE:
3714 3746 size = sizeof (lb_info_sz_t);
3715 3747 if (iocp->ioc_count != size)
3716 3748 return (IOC_INVAL);
3717 3749
3718 3750 value = sizeof (lb_normal);
3719 3751 if (hw->phy.media_type == e1000_media_type_copper)
3720 3752 value += sizeof (lb_phy);
3721 3753 else
3722 3754 value += sizeof (lb_serdes);
3723 3755 value += sizeof (lb_external);
3724 3756
3725 3757 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr;
3726 3758 *lbsp = value;
3727 3759 break;
3728 3760
3729 3761 case LB_GET_INFO:
3730 3762 value = sizeof (lb_normal);
3731 3763 if (hw->phy.media_type == e1000_media_type_copper)
3732 3764 value += sizeof (lb_phy);
3733 3765 else
3734 3766 value += sizeof (lb_serdes);
3735 3767 value += sizeof (lb_external);
3736 3768
3737 3769 size = value;
3738 3770 if (iocp->ioc_count != size)
3739 3771 return (IOC_INVAL);
3740 3772
3741 3773 value = 0;
3742 3774 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr;
3743 3775
3744 3776 lbpp[value++] = lb_normal;
3745 3777 if (hw->phy.media_type == e1000_media_type_copper)
3746 3778 lbpp[value++] = lb_phy;
3747 3779 else
3748 3780 lbpp[value++] = lb_serdes;
3749 3781 lbpp[value++] = lb_external;
3750 3782 break;
3751 3783
3752 3784 case LB_GET_MODE:
3753 3785 size = sizeof (uint32_t);
3754 3786 if (iocp->ioc_count != size)
3755 3787 return (IOC_INVAL);
3756 3788
3757 3789 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3758 3790 *lbmp = igb->loopback_mode;
3759 3791 break;
3760 3792
3761 3793 case LB_SET_MODE:
3762 3794 size = 0;
3763 3795 if (iocp->ioc_count != sizeof (uint32_t))
3764 3796 return (IOC_INVAL);
3765 3797
3766 3798 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3767 3799 if (!igb_set_loopback_mode(igb, *lbmp))
3768 3800 return (IOC_INVAL);
3769 3801 break;
3770 3802 }
3771 3803
3772 3804 iocp->ioc_count = size;
3773 3805 iocp->ioc_error = 0;
3774 3806
3775 3807 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3776 3808 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3777 3809 return (IOC_INVAL);
3778 3810 }
3779 3811
3780 3812 return (IOC_REPLY);
3781 3813 }
3782 3814
3783 3815 /*
3784 3816 * igb_set_loopback_mode - Setup loopback based on the loopback mode
3785 3817 */
3786 3818 static boolean_t
3787 3819 igb_set_loopback_mode(igb_t *igb, uint32_t mode)
3788 3820 {
3789 3821 struct e1000_hw *hw;
3790 3822 int i;
3791 3823
3792 3824 if (mode == igb->loopback_mode)
3793 3825 return (B_TRUE);
3794 3826
3795 3827 hw = &igb->hw;
3796 3828
3797 3829 igb->loopback_mode = mode;
3798 3830
3799 3831 if (mode == IGB_LB_NONE) {
3800 3832 /* Reset the chip */
3801 3833 hw->phy.autoneg_wait_to_complete = B_TRUE;
3802 3834 (void) igb_reset(igb);
3803 3835 hw->phy.autoneg_wait_to_complete = B_FALSE;
3804 3836 return (B_TRUE);
3805 3837 }
3806 3838
3807 3839 mutex_enter(&igb->gen_lock);
3808 3840
3809 3841 switch (mode) {
3810 3842 default:
3811 3843 mutex_exit(&igb->gen_lock);
3812 3844 return (B_FALSE);
3813 3845
3814 3846 case IGB_LB_EXTERNAL:
3815 3847 igb_set_external_loopback(igb);
3816 3848 break;
3817 3849
3818 3850 case IGB_LB_INTERNAL_PHY:
3819 3851 igb_set_internal_phy_loopback(igb);
3820 3852 break;
3821 3853
3822 3854 case IGB_LB_INTERNAL_SERDES:
3823 3855 igb_set_internal_serdes_loopback(igb);
3824 3856 break;
3825 3857 }
3826 3858
3827 3859 mutex_exit(&igb->gen_lock);
3828 3860
3829 3861 /*
3830 3862 * When external loopback is set, wait up to 1000ms to get the link up.
3831 3863 * According to test, 1000ms can work and it's an experimental value.
3832 3864 */
3833 3865 if (mode == IGB_LB_EXTERNAL) {
3834 3866 for (i = 0; i <= 10; i++) {
3835 3867 mutex_enter(&igb->gen_lock);
3836 3868 (void) igb_link_check(igb);
3837 3869 mutex_exit(&igb->gen_lock);
3838 3870
3839 3871 if (igb->link_state == LINK_STATE_UP)
3840 3872 break;
3841 3873
3842 3874 msec_delay(100);
3843 3875 }
3844 3876
3845 3877 if (igb->link_state != LINK_STATE_UP) {
3846 3878 /*
3847 3879 * Does not support external loopback.
3848 3880 * Reset driver to loopback none.
3849 3881 */
3850 3882 igb->loopback_mode = IGB_LB_NONE;
3851 3883
3852 3884 /* Reset the chip */
3853 3885 hw->phy.autoneg_wait_to_complete = B_TRUE;
3854 3886 (void) igb_reset(igb);
3855 3887 hw->phy.autoneg_wait_to_complete = B_FALSE;
3856 3888
3857 3889 IGB_DEBUGLOG_0(igb, "Set external loopback failed, "
3858 3890 "reset to loopback none.");
3859 3891
3860 3892 return (B_FALSE);
3861 3893 }
3862 3894 }
3863 3895
3864 3896 return (B_TRUE);
3865 3897 }
3866 3898
3867 3899 /*
3868 3900 * igb_set_external_loopback - Set the external loopback mode
3869 3901 */
3870 3902 static void
3871 3903 igb_set_external_loopback(igb_t *igb)
3872 3904 {
3873 3905 struct e1000_hw *hw;
3874 3906 uint32_t ctrl_ext;
3875 3907
3876 3908 hw = &igb->hw;
3877 3909
3878 3910 /* Set link mode to PHY (00b) in the Extended Control register */
3879 3911 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3880 3912 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
3881 3913 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3882 3914
3883 3915 (void) e1000_write_phy_reg(hw, 0x0, 0x0140);
3884 3916 (void) e1000_write_phy_reg(hw, 0x9, 0x1a00);
3885 3917 (void) e1000_write_phy_reg(hw, 0x12, 0x1610);
3886 3918 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c);
3887 3919 }
3888 3920
3889 3921 /*
3890 3922 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode
3891 3923 */
3892 3924 static void
3893 3925 igb_set_internal_phy_loopback(igb_t *igb)
3894 3926 {
3895 3927 struct e1000_hw *hw;
3896 3928 uint32_t ctrl_ext;
3897 3929 uint16_t phy_ctrl;
3898 3930 uint16_t phy_pconf;
3899 3931
3900 3932 hw = &igb->hw;
3901 3933
3902 3934 /* Set link mode to PHY (00b) in the Extended Control register */
3903 3935 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3904 3936 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
3905 3937 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3906 3938
3907 3939 /*
3908 3940 * Set PHY control register (0x4140):
3909 3941 * Set full duplex mode
3910 3942 * Set loopback bit
3911 3943 * Clear auto-neg enable bit
3912 3944 * Set PHY speed
3913 3945 */
3914 3946 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK;
3915 3947 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
3916 3948
3917 3949 /* Set the link disable bit in the Port Configuration register */
3918 3950 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf);
3919 3951 phy_pconf |= (uint16_t)1 << 14;
3920 3952 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf);
3921 3953 }
3922 3954
3923 3955 /*
3924 3956 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode
3925 3957 */
3926 3958 static void
3927 3959 igb_set_internal_serdes_loopback(igb_t *igb)
3928 3960 {
3929 3961 struct e1000_hw *hw;
3930 3962 uint32_t ctrl_ext;
3931 3963 uint32_t ctrl;
3932 3964 uint32_t pcs_lctl;
3933 3965 uint32_t connsw;
3934 3966
3935 3967 hw = &igb->hw;
3936 3968
3937 3969 /* Set link mode to SerDes (11b) in the Extended Control register */
3938 3970 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3939 3971 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
3940 3972 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3941 3973
3942 3974 /* Configure the SerDes to loopback */
3943 3975 E1000_WRITE_REG(hw, E1000_SCTL, 0x410);
3944 3976
3945 3977 /* Set Device Control register */
3946 3978 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3947 3979 ctrl |= (E1000_CTRL_FD | /* Force full duplex */
3948 3980 E1000_CTRL_SLU); /* Force link up */
3949 3981 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */
3950 3982 E1000_CTRL_TFCE | /* Disable transmit flow control */
3951 3983 E1000_CTRL_LRST); /* Clear link reset */
3952 3984 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3953 3985
3954 3986 /* Set PCS Link Control register */
3955 3987 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL);
3956 3988 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK |
3957 3989 E1000_PCS_LCTL_FSD |
3958 3990 E1000_PCS_LCTL_FDV_FULL |
3959 3991 E1000_PCS_LCTL_FLV_LINK_UP);
3960 3992 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE;
3961 3993 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl);
3962 3994
3963 3995 /* Set the Copper/Fiber Switch Control - CONNSW register */
3964 3996 connsw = E1000_READ_REG(hw, E1000_CONNSW);
3965 3997 connsw &= ~E1000_CONNSW_ENRGSRC;
3966 3998 E1000_WRITE_REG(hw, E1000_CONNSW, connsw);
3967 3999 }
3968 4000
3969 4001 #pragma inline(igb_intr_rx_work)
3970 4002 /*
3971 4003 * igb_intr_rx_work - rx processing of ISR
3972 4004 */
3973 4005 static void
3974 4006 igb_intr_rx_work(igb_rx_ring_t *rx_ring)
3975 4007 {
3976 4008 mblk_t *mp;
3977 4009
3978 4010 mutex_enter(&rx_ring->rx_lock);
3979 4011 mp = igb_rx(rx_ring, IGB_NO_POLL);
3980 4012 mutex_exit(&rx_ring->rx_lock);
3981 4013
3982 4014 if (mp != NULL)
3983 4015 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp,
3984 4016 rx_ring->ring_gen_num);
3985 4017 }
3986 4018
3987 4019 #pragma inline(igb_intr_tx_work)
3988 4020 /*
3989 4021 * igb_intr_tx_work - tx processing of ISR
3990 4022 */
3991 4023 static void
3992 4024 igb_intr_tx_work(igb_tx_ring_t *tx_ring)
3993 4025 {
3994 4026 igb_t *igb = tx_ring->igb;
3995 4027
3996 4028 /* Recycle the tx descriptors */
3997 4029 tx_ring->tx_recycle(tx_ring);
3998 4030
3999 4031 /* Schedule the re-transmit */
4000 4032 if (tx_ring->reschedule &&
4001 4033 (tx_ring->tbd_free >= igb->tx_resched_thresh)) {
4002 4034 tx_ring->reschedule = B_FALSE;
4003 4035 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle);
4004 4036 IGB_DEBUG_STAT(tx_ring->stat_reschedule);
4005 4037 }
4006 4038 }
4007 4039
4008 4040 #pragma inline(igb_intr_link_work)
4009 4041 /*
4010 4042 * igb_intr_link_work - link-status-change processing of ISR
4011 4043 */
4012 4044 static void
4013 4045 igb_intr_link_work(igb_t *igb)
4014 4046 {
4015 4047 boolean_t link_changed;
4016 4048
4017 4049 igb_stop_watchdog_timer(igb);
4018 4050
4019 4051 mutex_enter(&igb->gen_lock);
4020 4052
4021 4053 /*
4022 4054 * Because we got a link-status-change interrupt, force
4023 4055 * e1000_check_for_link() to look at phy
4024 4056 */
4025 4057 igb->hw.mac.get_link_status = B_TRUE;
4026 4058
4027 4059 /* igb_link_check takes care of link status change */
4028 4060 link_changed = igb_link_check(igb);
4029 4061
4030 4062 /* Get new phy state */
4031 4063 igb_get_phy_state(igb);
4032 4064
4033 4065 mutex_exit(&igb->gen_lock);
4034 4066
4035 4067 if (link_changed)
4036 4068 mac_link_update(igb->mac_hdl, igb->link_state);
4037 4069
4038 4070 igb_start_watchdog_timer(igb);
4039 4071 }
4040 4072
4041 4073 /*
4042 4074 * igb_intr_legacy - Interrupt handler for legacy interrupts
4043 4075 */
4044 4076 static uint_t
4045 4077 igb_intr_legacy(void *arg1, void *arg2)
4046 4078 {
4047 4079 igb_t *igb = (igb_t *)arg1;
4048 4080 igb_tx_ring_t *tx_ring;
4049 4081 uint32_t icr;
4050 4082 mblk_t *mp;
4051 4083 boolean_t tx_reschedule;
4052 4084 boolean_t link_changed;
4053 4085 uint_t result;
4054 4086
4055 4087 _NOTE(ARGUNUSED(arg2));
4056 4088
4057 4089 mutex_enter(&igb->gen_lock);
4058 4090
4059 4091 if (igb->igb_state & IGB_SUSPENDED) {
4060 4092 mutex_exit(&igb->gen_lock);
4061 4093 return (DDI_INTR_UNCLAIMED);
4062 4094 }
4063 4095
4064 4096 mp = NULL;
4065 4097 tx_reschedule = B_FALSE;
4066 4098 link_changed = B_FALSE;
4067 4099 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4068 4100
4069 4101 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4070 4102 mutex_exit(&igb->gen_lock);
4071 4103 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4072 4104 atomic_or_32(&igb->igb_state, IGB_ERROR);
4073 4105 return (DDI_INTR_UNCLAIMED);
4074 4106 }
4075 4107
4076 4108 if (icr & E1000_ICR_INT_ASSERTED) {
4077 4109 /*
4078 4110 * E1000_ICR_INT_ASSERTED bit was set:
4079 4111 * Read(Clear) the ICR, claim this interrupt,
4080 4112 * look for work to do.
4081 4113 */
4082 4114 ASSERT(igb->num_rx_rings == 1);
4083 4115 ASSERT(igb->num_tx_rings == 1);
4084 4116
4085 4117 /* Make sure all interrupt causes cleared */
4086 4118 (void) E1000_READ_REG(&igb->hw, E1000_EICR);
4087 4119
4088 4120 if (icr & E1000_ICR_RXT0) {
4089 4121 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL);
4090 4122 }
4091 4123
4092 4124 if (icr & E1000_ICR_TXDW) {
4093 4125 tx_ring = &igb->tx_rings[0];
4094 4126
4095 4127 /* Recycle the tx descriptors */
4096 4128 tx_ring->tx_recycle(tx_ring);
4097 4129
4098 4130 /* Schedule the re-transmit */
4099 4131 tx_reschedule = (tx_ring->reschedule &&
4100 4132 (tx_ring->tbd_free >= igb->tx_resched_thresh));
4101 4133 }
4102 4134
4103 4135 if (icr & E1000_ICR_LSC) {
4104 4136 /*
4105 4137 * Because we got a link-status-change interrupt, force
4106 4138 * e1000_check_for_link() to look at phy
4107 4139 */
4108 4140 igb->hw.mac.get_link_status = B_TRUE;
4109 4141
4110 4142 /* igb_link_check takes care of link status change */
4111 4143 link_changed = igb_link_check(igb);
4112 4144
4113 4145 /* Get new phy state */
4114 4146 igb_get_phy_state(igb);
4115 4147 }
4116 4148
4117 4149 if (icr & E1000_ICR_DRSTA) {
4118 4150 /* 82580 Full Device Reset needed */
4119 4151 atomic_or_32(&igb->igb_state, IGB_STALL);
4120 4152 }
4121 4153
4122 4154 result = DDI_INTR_CLAIMED;
4123 4155 } else {
4124 4156 /*
4125 4157 * E1000_ICR_INT_ASSERTED bit was not set:
4126 4158 * Don't claim this interrupt.
4127 4159 */
4128 4160 result = DDI_INTR_UNCLAIMED;
4129 4161 }
4130 4162
4131 4163 mutex_exit(&igb->gen_lock);
4132 4164
4133 4165 /*
4134 4166 * Do the following work outside of the gen_lock
4135 4167 */
4136 4168 if (mp != NULL)
4137 4169 mac_rx(igb->mac_hdl, NULL, mp);
4138 4170
4139 4171 if (tx_reschedule) {
4140 4172 tx_ring->reschedule = B_FALSE;
4141 4173 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle);
4142 4174 IGB_DEBUG_STAT(tx_ring->stat_reschedule);
4143 4175 }
4144 4176
4145 4177 if (link_changed)
4146 4178 mac_link_update(igb->mac_hdl, igb->link_state);
4147 4179
4148 4180 return (result);
4149 4181 }
4150 4182
4151 4183 /*
4152 4184 * igb_intr_msi - Interrupt handler for MSI
4153 4185 */
4154 4186 static uint_t
4155 4187 igb_intr_msi(void *arg1, void *arg2)
4156 4188 {
4157 4189 igb_t *igb = (igb_t *)arg1;
4158 4190 uint32_t icr;
4159 4191
4160 4192 _NOTE(ARGUNUSED(arg2));
4161 4193
4162 4194 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4163 4195
4164 4196 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4165 4197 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4166 4198 atomic_or_32(&igb->igb_state, IGB_ERROR);
4167 4199 return (DDI_INTR_CLAIMED);
4168 4200 }
4169 4201
4170 4202 /* Make sure all interrupt causes cleared */
4171 4203 (void) E1000_READ_REG(&igb->hw, E1000_EICR);
4172 4204
4173 4205 /*
4174 4206 * For MSI interrupt, we have only one vector,
4175 4207 * so we have only one rx ring and one tx ring enabled.
4176 4208 */
4177 4209 ASSERT(igb->num_rx_rings == 1);
4178 4210 ASSERT(igb->num_tx_rings == 1);
4179 4211
4180 4212 if (icr & E1000_ICR_RXT0) {
4181 4213 igb_intr_rx_work(&igb->rx_rings[0]);
4182 4214 }
4183 4215
4184 4216 if (icr & E1000_ICR_TXDW) {
4185 4217 igb_intr_tx_work(&igb->tx_rings[0]);
4186 4218 }
4187 4219
4188 4220 if (icr & E1000_ICR_LSC) {
4189 4221 igb_intr_link_work(igb);
4190 4222 }
4191 4223
4192 4224 if (icr & E1000_ICR_DRSTA) {
4193 4225 /* 82580 Full Device Reset needed */
4194 4226 atomic_or_32(&igb->igb_state, IGB_STALL);
4195 4227 }
4196 4228
4197 4229 return (DDI_INTR_CLAIMED);
4198 4230 }
4199 4231
4200 4232 /*
4201 4233 * igb_intr_rx - Interrupt handler for rx
4202 4234 */
4203 4235 static uint_t
4204 4236 igb_intr_rx(void *arg1, void *arg2)
4205 4237 {
4206 4238 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1;
4207 4239
4208 4240 _NOTE(ARGUNUSED(arg2));
4209 4241
4210 4242 /*
4211 4243 * Only used via MSI-X vector so don't check cause bits
4212 4244 * and only clean the given ring.
4213 4245 */
4214 4246 igb_intr_rx_work(rx_ring);
4215 4247
4216 4248 return (DDI_INTR_CLAIMED);
4217 4249 }
4218 4250
4219 4251 /*
4220 4252 * igb_intr_tx - Interrupt handler for tx
4221 4253 */
4222 4254 static uint_t
4223 4255 igb_intr_tx(void *arg1, void *arg2)
4224 4256 {
4225 4257 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1;
4226 4258
4227 4259 _NOTE(ARGUNUSED(arg2));
4228 4260
4229 4261 /*
4230 4262 * Only used via MSI-X vector so don't check cause bits
4231 4263 * and only clean the given ring.
4232 4264 */
4233 4265 igb_intr_tx_work(tx_ring);
4234 4266
4235 4267 return (DDI_INTR_CLAIMED);
4236 4268 }
4237 4269
4238 4270 /*
4239 4271 * igb_intr_tx_other - Interrupt handler for both tx and other
4240 4272 *
4241 4273 */
4242 4274 static uint_t
4243 4275 igb_intr_tx_other(void *arg1, void *arg2)
4244 4276 {
4245 4277 igb_t *igb = (igb_t *)arg1;
4246 4278 uint32_t icr;
4247 4279
4248 4280 _NOTE(ARGUNUSED(arg2));
4249 4281
4250 4282 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4251 4283
4252 4284 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4253 4285 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4254 4286 atomic_or_32(&igb->igb_state, IGB_ERROR);
4255 4287 return (DDI_INTR_CLAIMED);
4256 4288 }
4257 4289
4258 4290 /*
4259 4291 * Look for tx reclaiming work first. Remember, in the
4260 4292 * case of only interrupt sharing, only one tx ring is
4261 4293 * used
4262 4294 */
4263 4295 igb_intr_tx_work(&igb->tx_rings[0]);
4264 4296
4265 4297 /*
4266 4298 * Check for "other" causes.
4267 4299 */
4268 4300 if (icr & E1000_ICR_LSC) {
4269 4301 igb_intr_link_work(igb);
4270 4302 }
4271 4303
4272 4304 /*
4273 4305 * The DOUTSYNC bit indicates a tx packet dropped because
4274 4306 * DMA engine gets "out of sync". There isn't a real fix
4275 4307 * for this. The Intel recommendation is to count the number
4276 4308 * of occurrences so user can detect when it is happening.
4277 4309 * The issue is non-fatal and there's no recovery action
4278 4310 * available.
4279 4311 */
4280 4312 if (icr & E1000_ICR_DOUTSYNC) {
4281 4313 IGB_STAT(igb->dout_sync);
4282 4314 }
4283 4315
4284 4316 if (icr & E1000_ICR_DRSTA) {
4285 4317 /* 82580 Full Device Reset needed */
4286 4318 atomic_or_32(&igb->igb_state, IGB_STALL);
4287 4319 }
4288 4320
4289 4321 return (DDI_INTR_CLAIMED);
4290 4322 }
4291 4323
4292 4324 /*
4293 4325 * igb_alloc_intrs - Allocate interrupts for the driver
4294 4326 *
4295 4327 * Normal sequence is to try MSI-X; if not sucessful, try MSI;
4296 4328 * if not successful, try Legacy.
4297 4329 * igb->intr_force can be used to force sequence to start with
4298 4330 * any of the 3 types.
4299 4331 * If MSI-X is not used, number of tx/rx rings is forced to 1.
4300 4332 */
4301 4333 static int
4302 4334 igb_alloc_intrs(igb_t *igb)
4303 4335 {
4304 4336 dev_info_t *devinfo;
4305 4337 int intr_types;
4306 4338 int rc;
4307 4339
4308 4340 devinfo = igb->dip;
4309 4341
4310 4342 /* Get supported interrupt types */
4311 4343 rc = ddi_intr_get_supported_types(devinfo, &intr_types);
4312 4344
4313 4345 if (rc != DDI_SUCCESS) {
4314 4346 igb_log(igb,
4315 4347 "Get supported interrupt types failed: %d", rc);
4316 4348 return (IGB_FAILURE);
4317 4349 }
4318 4350 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types);
4319 4351
4320 4352 igb->intr_type = 0;
4321 4353
4322 4354 /* Install MSI-X interrupts */
4323 4355 if ((intr_types & DDI_INTR_TYPE_MSIX) &&
4324 4356 (igb->intr_force <= IGB_INTR_MSIX)) {
4325 4357 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX);
4326 4358
4327 4359 if (rc == IGB_SUCCESS)
4328 4360 return (IGB_SUCCESS);
4329 4361
4330 4362 igb_log(igb,
4331 4363 "Allocate MSI-X failed, trying MSI interrupts...");
4332 4364 }
4333 4365
4334 4366 /* MSI-X not used, force rings to 1 */
4335 4367 igb->num_rx_rings = 1;
4336 4368 igb->num_tx_rings = 1;
4337 4369 igb_log(igb,
4338 4370 "MSI-X not used, force rx and tx queue number to 1");
4339 4371
4340 4372 /* Install MSI interrupts */
4341 4373 if ((intr_types & DDI_INTR_TYPE_MSI) &&
4342 4374 (igb->intr_force <= IGB_INTR_MSI)) {
4343 4375 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI);
4344 4376
4345 4377 if (rc == IGB_SUCCESS)
4346 4378 return (IGB_SUCCESS);
4347 4379
4348 4380 igb_log(igb,
4349 4381 "Allocate MSI failed, trying Legacy interrupts...");
4350 4382 }
4351 4383
4352 4384 /* Install legacy interrupts */
4353 4385 if (intr_types & DDI_INTR_TYPE_FIXED) {
4354 4386 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED);
4355 4387
4356 4388 if (rc == IGB_SUCCESS)
4357 4389 return (IGB_SUCCESS);
4358 4390
4359 4391 igb_log(igb,
4360 4392 "Allocate Legacy interrupts failed");
4361 4393 }
4362 4394
4363 4395 /* If none of the 3 types succeeded, return failure */
4364 4396 return (IGB_FAILURE);
4365 4397 }
4366 4398
4367 4399 /*
4368 4400 * igb_alloc_intr_handles - Allocate interrupt handles.
4369 4401 *
4370 4402 * For legacy and MSI, only 1 handle is needed. For MSI-X,
4371 4403 * if fewer than 2 handles are available, return failure.
4372 4404 * Upon success, this sets the number of Rx rings to a number that
4373 4405 * matches the handles available for Rx interrupts.
4374 4406 */
4375 4407 static int
4376 4408 igb_alloc_intr_handles(igb_t *igb, int intr_type)
4377 4409 {
4378 4410 dev_info_t *devinfo;
4379 4411 int orig, request, count, avail, actual;
4380 4412 int diff, minimum;
4381 4413 int rc;
4382 4414
4383 4415 devinfo = igb->dip;
4384 4416
4385 4417 switch (intr_type) {
4386 4418 case DDI_INTR_TYPE_FIXED:
4387 4419 request = 1; /* Request 1 legacy interrupt handle */
4388 4420 minimum = 1;
4389 4421 IGB_DEBUGLOG_0(igb, "interrupt type: legacy");
4390 4422 break;
4391 4423
4392 4424 case DDI_INTR_TYPE_MSI:
4393 4425 request = 1; /* Request 1 MSI interrupt handle */
4394 4426 minimum = 1;
4395 4427 IGB_DEBUGLOG_0(igb, "interrupt type: MSI");
4396 4428 break;
4397 4429
4398 4430 case DDI_INTR_TYPE_MSIX:
4399 4431 /*
4400 4432 * Number of vectors for the adapter is
4401 4433 * # rx rings + # tx rings
4402 4434 * One of tx vectors is for tx & other
4403 4435 */
4404 4436 request = igb->num_rx_rings + igb->num_tx_rings;
4405 4437 orig = request;
4406 4438 minimum = 2;
4407 4439 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X");
4408 4440 break;
4409 4441
4410 4442 default:
4411 4443 igb_log(igb,
4412 4444 "invalid call to igb_alloc_intr_handles(): %d\n",
4413 4445 intr_type);
4414 4446 return (IGB_FAILURE);
4415 4447 }
4416 4448 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d",
4417 4449 request, minimum);
4418 4450
4419 4451 /*
4420 4452 * Get number of supported interrupts
4421 4453 */
4422 4454 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
4423 4455 if ((rc != DDI_SUCCESS) || (count < minimum)) {
4424 4456 igb_log(igb,
4425 4457 "Get supported interrupt number failed. "
4426 4458 "Return: %d, count: %d", rc, count);
4427 4459 return (IGB_FAILURE);
4428 4460 }
4429 4461 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count);
4430 4462
4431 4463 /*
4432 4464 * Get number of available interrupts
4433 4465 */
4434 4466 rc = ddi_intr_get_navail(devinfo, intr_type, &avail);
4435 4467 if ((rc != DDI_SUCCESS) || (avail < minimum)) {
4436 4468 igb_log(igb,
4437 4469 "Get available interrupt number failed. "
4438 4470 "Return: %d, available: %d", rc, avail);
4439 4471 return (IGB_FAILURE);
4440 4472 }
4441 4473 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail);
4442 4474
4443 4475 if (avail < request) {
4444 4476 igb_log(igb, "Request %d handles, %d available",
4445 4477 request, avail);
4446 4478 request = avail;
4447 4479 }
4448 4480
4449 4481 actual = 0;
4450 4482 igb->intr_cnt = 0;
4451 4483
4452 4484 /*
4453 4485 * Allocate an array of interrupt handles
4454 4486 */
4455 4487 igb->intr_size = request * sizeof (ddi_intr_handle_t);
4456 4488 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP);
4457 4489
4458 4490 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0,
4459 4491 request, &actual, DDI_INTR_ALLOC_NORMAL);
4460 4492 if (rc != DDI_SUCCESS) {
4461 4493 igb_log(igb, "Allocate interrupts failed. "
4462 4494 "return: %d, request: %d, actual: %d",
4463 4495 rc, request, actual);
4464 4496 goto alloc_handle_fail;
4465 4497 }
4466 4498 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual);
4467 4499
4468 4500 igb->intr_cnt = actual;
4469 4501
4470 4502 if (actual < minimum) {
4471 4503 igb_log(igb, "Insufficient interrupt handles allocated: %d",
4472 4504 actual);
4473 4505 goto alloc_handle_fail;
4474 4506 }
4475 4507
4476 4508 /*
4477 4509 * For MSI-X, actual might force us to reduce number of tx & rx rings
4478 4510 */
4479 4511 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) {
4480 4512 diff = orig - actual;
4481 4513 if (diff < igb->num_tx_rings) {
4482 4514 igb_log(igb,
4483 4515 "MSI-X vectors force Tx queue number to %d",
4484 4516 igb->num_tx_rings - diff);
4485 4517 igb->num_tx_rings -= diff;
4486 4518 } else {
4487 4519 igb_log(igb,
4488 4520 "MSI-X vectors force Tx queue number to 1");
4489 4521 igb->num_tx_rings = 1;
4490 4522
4491 4523 igb_log(igb,
4492 4524 "MSI-X vectors force Rx queue number to %d",
4493 4525 actual - 1);
4494 4526 igb->num_rx_rings = actual - 1;
4495 4527 }
4496 4528 }
4497 4529
4498 4530 /*
4499 4531 * Get priority for first vector, assume remaining are all the same
4500 4532 */
4501 4533 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri);
4502 4534 if (rc != DDI_SUCCESS) {
4503 4535 igb_log(igb,
4504 4536 "Get interrupt priority failed: %d", rc);
4505 4537 goto alloc_handle_fail;
4506 4538 }
4507 4539
4508 4540 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap);
4509 4541 if (rc != DDI_SUCCESS) {
4510 4542 igb_log(igb,
4511 4543 "Get interrupt cap failed: %d", rc);
4512 4544 goto alloc_handle_fail;
4513 4545 }
4514 4546
4515 4547 igb->intr_type = intr_type;
4516 4548
4517 4549 return (IGB_SUCCESS);
4518 4550
4519 4551 alloc_handle_fail:
4520 4552 igb_rem_intrs(igb);
4521 4553
4522 4554 return (IGB_FAILURE);
4523 4555 }
4524 4556
4525 4557 /*
4526 4558 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type
4527 4559 *
4528 4560 * Before adding the interrupt handlers, the interrupt vectors have
4529 4561 * been allocated, and the rx/tx rings have also been allocated.
4530 4562 */
4531 4563 static int
4532 4564 igb_add_intr_handlers(igb_t *igb)
4533 4565 {
4534 4566 igb_rx_ring_t *rx_ring;
4535 4567 igb_tx_ring_t *tx_ring;
4536 4568 int vector;
4537 4569 int rc;
4538 4570 int i;
4539 4571
4540 4572 vector = 0;
4541 4573
4542 4574 switch (igb->intr_type) {
4543 4575 case DDI_INTR_TYPE_MSIX:
4544 4576 /* Add interrupt handler for tx + other */
4545 4577 tx_ring = &igb->tx_rings[0];
4546 4578 rc = ddi_intr_add_handler(igb->htable[vector],
4547 4579 (ddi_intr_handler_t *)igb_intr_tx_other,
4548 4580 (void *)igb, NULL);
4549 4581
4550 4582 if (rc != DDI_SUCCESS) {
4551 4583 igb_log(igb,
4552 4584 "Add tx/other interrupt handler failed: %d", rc);
4553 4585 return (IGB_FAILURE);
4554 4586 }
4555 4587 tx_ring->intr_vector = vector;
4556 4588 vector++;
4557 4589
4558 4590 /* Add interrupt handler for each rx ring */
4559 4591 for (i = 0; i < igb->num_rx_rings; i++) {
4560 4592 rx_ring = &igb->rx_rings[i];
4561 4593
4562 4594 rc = ddi_intr_add_handler(igb->htable[vector],
4563 4595 (ddi_intr_handler_t *)igb_intr_rx,
4564 4596 (void *)rx_ring, NULL);
4565 4597
4566 4598 if (rc != DDI_SUCCESS) {
4567 4599 igb_log(igb,
4568 4600 "Add rx interrupt handler failed. "
4569 4601 "return: %d, rx ring: %d", rc, i);
4570 4602 for (vector--; vector >= 0; vector--) {
4571 4603 (void) ddi_intr_remove_handler(
4572 4604 igb->htable[vector]);
4573 4605 }
4574 4606 return (IGB_FAILURE);
4575 4607 }
4576 4608
4577 4609 rx_ring->intr_vector = vector;
4578 4610
4579 4611 vector++;
4580 4612 }
4581 4613
4582 4614 /* Add interrupt handler for each tx ring from 2nd ring */
4583 4615 for (i = 1; i < igb->num_tx_rings; i++) {
4584 4616 tx_ring = &igb->tx_rings[i];
4585 4617
4586 4618 rc = ddi_intr_add_handler(igb->htable[vector],
4587 4619 (ddi_intr_handler_t *)igb_intr_tx,
4588 4620 (void *)tx_ring, NULL);
4589 4621
4590 4622 if (rc != DDI_SUCCESS) {
4591 4623 igb_log(igb,
4592 4624 "Add tx interrupt handler failed. "
4593 4625 "return: %d, tx ring: %d", rc, i);
4594 4626 for (vector--; vector >= 0; vector--) {
4595 4627 (void) ddi_intr_remove_handler(
4596 4628 igb->htable[vector]);
4597 4629 }
4598 4630 return (IGB_FAILURE);
4599 4631 }
4600 4632
4601 4633 tx_ring->intr_vector = vector;
4602 4634
4603 4635 vector++;
4604 4636 }
4605 4637
4606 4638 break;
4607 4639
4608 4640 case DDI_INTR_TYPE_MSI:
4609 4641 /* Add interrupt handlers for the only vector */
4610 4642 rc = ddi_intr_add_handler(igb->htable[vector],
4611 4643 (ddi_intr_handler_t *)igb_intr_msi,
4612 4644 (void *)igb, NULL);
4613 4645
4614 4646 if (rc != DDI_SUCCESS) {
4615 4647 igb_log(igb,
4616 4648 "Add MSI interrupt handler failed: %d", rc);
4617 4649 return (IGB_FAILURE);
4618 4650 }
4619 4651
4620 4652 rx_ring = &igb->rx_rings[0];
4621 4653 rx_ring->intr_vector = vector;
4622 4654
4623 4655 vector++;
4624 4656 break;
4625 4657
4626 4658 case DDI_INTR_TYPE_FIXED:
4627 4659 /* Add interrupt handlers for the only vector */
4628 4660 rc = ddi_intr_add_handler(igb->htable[vector],
4629 4661 (ddi_intr_handler_t *)igb_intr_legacy,
4630 4662 (void *)igb, NULL);
4631 4663
4632 4664 if (rc != DDI_SUCCESS) {
4633 4665 igb_log(igb,
4634 4666 "Add legacy interrupt handler failed: %d", rc);
4635 4667 return (IGB_FAILURE);
4636 4668 }
4637 4669
4638 4670 rx_ring = &igb->rx_rings[0];
4639 4671 rx_ring->intr_vector = vector;
4640 4672
4641 4673 vector++;
4642 4674 break;
4643 4675
4644 4676 default:
4645 4677 return (IGB_FAILURE);
4646 4678 }
4647 4679
4648 4680 ASSERT(vector == igb->intr_cnt);
4649 4681
4650 4682 return (IGB_SUCCESS);
4651 4683 }
4652 4684
4653 4685 /*
4654 4686 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts
4655 4687 *
4656 4688 * For each vector enabled on the adapter, Set the MSIXBM register accordingly
4657 4689 */
4658 4690 static void
4659 4691 igb_setup_msix_82575(igb_t *igb)
4660 4692 {
4661 4693 uint32_t eims = 0;
4662 4694 int i, vector;
4663 4695 struct e1000_hw *hw = &igb->hw;
4664 4696
4665 4697 /*
4666 4698 * Set vector for tx ring 0 and other causes.
4667 4699 * NOTE assumption that it is vector 0.
4668 4700 */
4669 4701 vector = 0;
4670 4702
4671 4703 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER;
4672 4704 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask);
4673 4705 vector++;
4674 4706
4675 4707 for (i = 0; i < igb->num_rx_rings; i++) {
4676 4708 /*
4677 4709 * Set vector for each rx ring
4678 4710 */
4679 4711 eims = (E1000_EICR_RX_QUEUE0 << i);
4680 4712 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
4681 4713
4682 4714 /*
4683 4715 * Accumulate bits to enable in
4684 4716 * igb_enable_adapter_interrupts_82575()
4685 4717 */
4686 4718 igb->eims_mask |= eims;
4687 4719
4688 4720 vector++;
4689 4721 }
4690 4722
4691 4723 for (i = 1; i < igb->num_tx_rings; i++) {
4692 4724 /*
4693 4725 * Set vector for each tx ring from 2nd tx ring
4694 4726 */
4695 4727 eims = (E1000_EICR_TX_QUEUE0 << i);
4696 4728 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
4697 4729
4698 4730 /*
4699 4731 * Accumulate bits to enable in
4700 4732 * igb_enable_adapter_interrupts_82575()
4701 4733 */
4702 4734 igb->eims_mask |= eims;
4703 4735
4704 4736 vector++;
4705 4737 }
4706 4738
4707 4739 ASSERT(vector == igb->intr_cnt);
4708 4740
4709 4741 /*
4710 4742 * Disable IAM for ICR interrupt bits
4711 4743 */
4712 4744 E1000_WRITE_REG(hw, E1000_IAM, 0);
4713 4745 E1000_WRITE_FLUSH(hw);
4714 4746 }
4715 4747
4716 4748 /*
4717 4749 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts
4718 4750 *
4719 4751 * 82576 uses a table based method for assigning vectors. Each queue has a
4720 4752 * single entry in the table to which we write a vector number along with a
4721 4753 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors
4722 4754 * take a different position in the 4-byte register depending on whether
4723 4755 * they are numbered above or below 8.
4724 4756 */
4725 4757 static void
4726 4758 igb_setup_msix_82576(igb_t *igb)
4727 4759 {
4728 4760 struct e1000_hw *hw = &igb->hw;
4729 4761 uint32_t ivar, index, vector;
4730 4762 int i;
4731 4763
4732 4764 /* must enable msi-x capability before IVAR settings */
4733 4765 E1000_WRITE_REG(hw, E1000_GPIE,
4734 4766 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR));
4735 4767
4736 4768 /*
4737 4769 * Set vector for tx ring 0 and other causes.
4738 4770 * NOTE assumption that it is vector 0.
4739 4771 * This is also interdependent with installation of interrupt service
4740 4772 * routines in igb_add_intr_handlers().
4741 4773 */
4742 4774
4743 4775 /* assign "other" causes to vector 0 */
4744 4776 vector = 0;
4745 4777 ivar = ((vector | E1000_IVAR_VALID) << 8);
4746 4778 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
4747 4779
4748 4780 /* assign tx ring 0 to vector 0 */
4749 4781 ivar = ((vector | E1000_IVAR_VALID) << 8);
4750 4782 E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
4751 4783
4752 4784 /* prepare to enable tx & other interrupt causes */
4753 4785 igb->eims_mask = (1 << vector);
4754 4786
4755 4787 vector ++;
4756 4788 for (i = 0; i < igb->num_rx_rings; i++) {
4757 4789 /*
4758 4790 * Set vector for each rx ring
4759 4791 */
4760 4792 index = (i & 0x7);
4761 4793 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4762 4794
4763 4795 if (i < 8) {
4764 4796 /* vector goes into low byte of register */
4765 4797 ivar = ivar & 0xFFFFFF00;
4766 4798 ivar |= (vector | E1000_IVAR_VALID);
4767 4799 } else {
4768 4800 /* vector goes into third byte of register */
4769 4801 ivar = ivar & 0xFF00FFFF;
4770 4802 ivar |= ((vector | E1000_IVAR_VALID) << 16);
4771 4803 }
4772 4804 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4773 4805
4774 4806 /* Accumulate interrupt-cause bits to enable */
4775 4807 igb->eims_mask |= (1 << vector);
4776 4808
4777 4809 vector ++;
4778 4810 }
4779 4811
4780 4812 for (i = 1; i < igb->num_tx_rings; i++) {
4781 4813 /*
4782 4814 * Set vector for each tx ring from 2nd tx ring.
4783 4815 * Note assumption that tx vectors numericall follow rx vectors.
4784 4816 */
4785 4817 index = (i & 0x7);
4786 4818 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4787 4819
4788 4820 if (i < 8) {
4789 4821 /* vector goes into second byte of register */
4790 4822 ivar = ivar & 0xFFFF00FF;
4791 4823 ivar |= ((vector | E1000_IVAR_VALID) << 8);
4792 4824 } else {
4793 4825 /* vector goes into fourth byte of register */
4794 4826 ivar = ivar & 0x00FFFFFF;
4795 4827 ivar |= (vector | E1000_IVAR_VALID) << 24;
4796 4828 }
4797 4829 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4798 4830
4799 4831 /* Accumulate interrupt-cause bits to enable */
4800 4832 igb->eims_mask |= (1 << vector);
4801 4833
4802 4834 vector ++;
4803 4835 }
4804 4836
4805 4837 ASSERT(vector == igb->intr_cnt);
4806 4838 }
4807 4839
4808 4840 /*
4809 4841 * igb_setup_msix_82580 - setup 82580 adapter to use MSI-X interrupts
4810 4842 *
4811 4843 * 82580 uses same table approach at 82576 but has fewer entries. Each
4812 4844 * queue has a single entry in the table to which we write a vector number
4813 4845 * along with a "valid" bit. Vectors take a different position in the
4814 4846 * register depending on * whether * they are numbered above or below 4.
4815 4847 */
4816 4848 static void
4817 4849 igb_setup_msix_82580(igb_t *igb)
4818 4850 {
4819 4851 struct e1000_hw *hw = &igb->hw;
4820 4852 uint32_t ivar, index, vector;
4821 4853 int i;
4822 4854
4823 4855 /* must enable msi-x capability before IVAR settings */
4824 4856 E1000_WRITE_REG(hw, E1000_GPIE, (E1000_GPIE_MSIX_MODE |
4825 4857 E1000_GPIE_PBA | E1000_GPIE_NSICR | E1000_GPIE_EIAME));
4826 4858 /*
4827 4859 * Set vector for tx ring 0 and other causes.
4828 4860 * NOTE assumption that it is vector 0.
4829 4861 * This is also interdependent with installation of interrupt service
4830 4862 * routines in igb_add_intr_handlers().
4831 4863 */
4832 4864
4833 4865 /* assign "other" causes to vector 0 */
4834 4866 vector = 0;
4835 4867 ivar = ((vector | E1000_IVAR_VALID) << 8);
4836 4868 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
4837 4869
4838 4870 /* assign tx ring 0 to vector 0 */
4839 4871 ivar = ((vector | E1000_IVAR_VALID) << 8);
4840 4872 E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
4841 4873
4842 4874 /* prepare to enable tx & other interrupt causes */
4843 4875 igb->eims_mask = (1 << vector);
4844 4876
4845 4877 vector ++;
4846 4878
4847 4879 for (i = 0; i < igb->num_rx_rings; i++) {
4848 4880 /*
4849 4881 * Set vector for each rx ring
4850 4882 */
4851 4883 index = (i >> 1);
4852 4884 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4853 4885
4854 4886 if (i & 1) {
4855 4887 /* vector goes into third byte of register */
4856 4888 ivar = ivar & 0xFF00FFFF;
4857 4889 ivar |= ((vector | E1000_IVAR_VALID) << 16);
4858 4890 } else {
4859 4891 /* vector goes into low byte of register */
4860 4892 ivar = ivar & 0xFFFFFF00;
4861 4893 ivar |= (vector | E1000_IVAR_VALID);
4862 4894 }
4863 4895 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4864 4896
4865 4897 /* Accumulate interrupt-cause bits to enable */
4866 4898 igb->eims_mask |= (1 << vector);
4867 4899
4868 4900 vector ++;
4869 4901 }
4870 4902
4871 4903 for (i = 1; i < igb->num_tx_rings; i++) {
4872 4904 /*
4873 4905 * Set vector for each tx ring from 2nd tx ring.
4874 4906 * Note assumption that tx vectors numericall follow rx vectors.
4875 4907 */
4876 4908 index = (i >> 1);
4877 4909 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4878 4910
4879 4911 if (i & 1) {
4880 4912 /* vector goes into high byte of register */
4881 4913 ivar = ivar & 0x00FFFFFF;
4882 4914 ivar |= ((vector | E1000_IVAR_VALID) << 24);
4883 4915 } else {
4884 4916 /* vector goes into second byte of register */
4885 4917 ivar = ivar & 0xFFFF00FF;
4886 4918 ivar |= (vector | E1000_IVAR_VALID) << 8;
4887 4919 }
4888 4920 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4889 4921
4890 4922 /* Accumulate interrupt-cause bits to enable */
4891 4923 igb->eims_mask |= (1 << vector);
4892 4924
4893 4925 vector ++;
4894 4926 }
4895 4927 ASSERT(vector == igb->intr_cnt);
4896 4928 }
4897 4929
4898 4930 /*
4899 4931 * igb_rem_intr_handlers - remove the interrupt handlers
4900 4932 */
4901 4933 static void
4902 4934 igb_rem_intr_handlers(igb_t *igb)
4903 4935 {
4904 4936 int i;
4905 4937 int rc;
4906 4938
4907 4939 for (i = 0; i < igb->intr_cnt; i++) {
4908 4940 rc = ddi_intr_remove_handler(igb->htable[i]);
4909 4941 if (rc != DDI_SUCCESS) {
4910 4942 IGB_DEBUGLOG_1(igb,
4911 4943 "Remove intr handler failed: %d", rc);
4912 4944 }
4913 4945 }
4914 4946 }
4915 4947
4916 4948 /*
4917 4949 * igb_rem_intrs - remove the allocated interrupts
4918 4950 */
4919 4951 static void
4920 4952 igb_rem_intrs(igb_t *igb)
4921 4953 {
4922 4954 int i;
4923 4955 int rc;
4924 4956
4925 4957 for (i = 0; i < igb->intr_cnt; i++) {
4926 4958 rc = ddi_intr_free(igb->htable[i]);
4927 4959 if (rc != DDI_SUCCESS) {
4928 4960 IGB_DEBUGLOG_1(igb,
4929 4961 "Free intr failed: %d", rc);
4930 4962 }
4931 4963 }
4932 4964
4933 4965 kmem_free(igb->htable, igb->intr_size);
4934 4966 igb->htable = NULL;
4935 4967 }
4936 4968
4937 4969 /*
4938 4970 * igb_enable_intrs - enable all the ddi interrupts
4939 4971 */
4940 4972 static int
4941 4973 igb_enable_intrs(igb_t *igb)
4942 4974 {
4943 4975 int i;
4944 4976 int rc;
4945 4977
4946 4978 /* Enable interrupts */
4947 4979 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
4948 4980 /* Call ddi_intr_block_enable() for MSI */
4949 4981 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt);
4950 4982 if (rc != DDI_SUCCESS) {
4951 4983 igb_log(igb,
4952 4984 "Enable block intr failed: %d", rc);
4953 4985 return (IGB_FAILURE);
4954 4986 }
4955 4987 } else {
4956 4988 /* Call ddi_intr_enable() for Legacy/MSI non block enable */
4957 4989 for (i = 0; i < igb->intr_cnt; i++) {
4958 4990 rc = ddi_intr_enable(igb->htable[i]);
4959 4991 if (rc != DDI_SUCCESS) {
4960 4992 igb_log(igb,
4961 4993 "Enable intr failed: %d", rc);
4962 4994 return (IGB_FAILURE);
4963 4995 }
4964 4996 }
4965 4997 }
4966 4998
4967 4999 return (IGB_SUCCESS);
4968 5000 }
4969 5001
4970 5002 /*
4971 5003 * igb_disable_intrs - disable all the ddi interrupts
4972 5004 */
4973 5005 static int
4974 5006 igb_disable_intrs(igb_t *igb)
4975 5007 {
4976 5008 int i;
4977 5009 int rc;
4978 5010
4979 5011 /* Disable all interrupts */
4980 5012 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
4981 5013 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt);
4982 5014 if (rc != DDI_SUCCESS) {
4983 5015 igb_log(igb,
4984 5016 "Disable block intr failed: %d", rc);
4985 5017 return (IGB_FAILURE);
4986 5018 }
4987 5019 } else {
4988 5020 for (i = 0; i < igb->intr_cnt; i++) {
4989 5021 rc = ddi_intr_disable(igb->htable[i]);
4990 5022 if (rc != DDI_SUCCESS) {
4991 5023 igb_log(igb,
4992 5024 "Disable intr failed: %d", rc);
4993 5025 return (IGB_FAILURE);
4994 5026 }
4995 5027 }
4996 5028 }
4997 5029
4998 5030 return (IGB_SUCCESS);
4999 5031 }
5000 5032
5001 5033 /*
5002 5034 * igb_get_phy_state - Get and save the parameters read from PHY registers
5003 5035 */
5004 5036 static void
5005 5037 igb_get_phy_state(igb_t *igb)
5006 5038 {
5007 5039 struct e1000_hw *hw = &igb->hw;
5008 5040 uint16_t phy_ctrl;
5009 5041 uint16_t phy_status;
5010 5042 uint16_t phy_an_adv;
5011 5043 uint16_t phy_an_exp;
5012 5044 uint16_t phy_ext_status;
5013 5045 uint16_t phy_1000t_ctrl;
5014 5046 uint16_t phy_1000t_status;
5015 5047 uint16_t phy_lp_able;
5016 5048
5017 5049 ASSERT(mutex_owned(&igb->gen_lock));
5018 5050
5019 5051 if (hw->phy.media_type == e1000_media_type_copper) {
5020 5052 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
5021 5053 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
5022 5054 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv);
5023 5055 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp);
5024 5056 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status);
5025 5057 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl);
5026 5058 (void) e1000_read_phy_reg(hw,
5027 5059 PHY_1000T_STATUS, &phy_1000t_status);
5028 5060 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able);
5029 5061
5030 5062 igb->param_autoneg_cap =
5031 5063 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0;
5032 5064 igb->param_pause_cap =
5033 5065 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
5034 5066 igb->param_asym_pause_cap =
5035 5067 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
5036 5068 igb->param_1000fdx_cap =
5037 5069 ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
5038 5070 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0;
5039 5071 igb->param_1000hdx_cap =
5040 5072 ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) ||
5041 5073 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0;
5042 5074 igb->param_100t4_cap =
5043 5075 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0;
5044 5076 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) ||
5045 5077 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0;
5046 5078 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) ||
5047 5079 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0;
5048 5080 igb->param_10fdx_cap =
5049 5081 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0;
5050 5082 igb->param_10hdx_cap =
5051 5083 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0;
5052 5084 igb->param_rem_fault =
5053 5085 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0;
5054 5086
5055 5087 igb->param_adv_autoneg_cap = hw->mac.autoneg;
5056 5088 igb->param_adv_pause_cap =
5057 5089 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
5058 5090 igb->param_adv_asym_pause_cap =
5059 5091 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
5060 5092 igb->param_adv_1000hdx_cap =
5061 5093 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0;
5062 5094 igb->param_adv_100t4_cap =
5063 5095 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0;
5064 5096 igb->param_adv_rem_fault =
5065 5097 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0;
5066 5098 if (igb->param_adv_autoneg_cap == 1) {
5067 5099 igb->param_adv_1000fdx_cap =
5068 5100 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0;
5069 5101 igb->param_adv_100fdx_cap =
5070 5102 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0;
5071 5103 igb->param_adv_100hdx_cap =
5072 5104 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0;
5073 5105 igb->param_adv_10fdx_cap =
5074 5106 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0;
5075 5107 igb->param_adv_10hdx_cap =
5076 5108 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0;
5077 5109 }
5078 5110
5079 5111 igb->param_lp_autoneg_cap =
5080 5112 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0;
5081 5113 igb->param_lp_pause_cap =
5082 5114 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0;
5083 5115 igb->param_lp_asym_pause_cap =
5084 5116 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0;
5085 5117 igb->param_lp_1000fdx_cap =
5086 5118 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0;
5087 5119 igb->param_lp_1000hdx_cap =
5088 5120 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0;
5089 5121 igb->param_lp_100t4_cap =
5090 5122 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0;
5091 5123 igb->param_lp_100fdx_cap =
5092 5124 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0;
5093 5125 igb->param_lp_100hdx_cap =
5094 5126 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0;
5095 5127 igb->param_lp_10fdx_cap =
5096 5128 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0;
5097 5129 igb->param_lp_10hdx_cap =
5098 5130 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0;
5099 5131 igb->param_lp_rem_fault =
5100 5132 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0;
5101 5133 } else {
5102 5134 /*
5103 5135 * 1Gig Fiber adapter only offers 1Gig Full Duplex.
5104 5136 */
5105 5137 igb->param_autoneg_cap = 0;
5106 5138 igb->param_pause_cap = 1;
5107 5139 igb->param_asym_pause_cap = 1;
5108 5140 igb->param_1000fdx_cap = 1;
5109 5141 igb->param_1000hdx_cap = 0;
5110 5142 igb->param_100t4_cap = 0;
5111 5143 igb->param_100fdx_cap = 0;
5112 5144 igb->param_100hdx_cap = 0;
5113 5145 igb->param_10fdx_cap = 0;
5114 5146 igb->param_10hdx_cap = 0;
5115 5147
5116 5148 igb->param_adv_autoneg_cap = 0;
5117 5149 igb->param_adv_pause_cap = 1;
5118 5150 igb->param_adv_asym_pause_cap = 1;
5119 5151 igb->param_adv_1000fdx_cap = 1;
5120 5152 igb->param_adv_1000hdx_cap = 0;
5121 5153 igb->param_adv_100t4_cap = 0;
5122 5154 igb->param_adv_100fdx_cap = 0;
5123 5155 igb->param_adv_100hdx_cap = 0;
5124 5156 igb->param_adv_10fdx_cap = 0;
5125 5157 igb->param_adv_10hdx_cap = 0;
5126 5158
5127 5159 igb->param_lp_autoneg_cap = 0;
5128 5160 igb->param_lp_pause_cap = 0;
5129 5161 igb->param_lp_asym_pause_cap = 0;
5130 5162 igb->param_lp_1000fdx_cap = 0;
5131 5163 igb->param_lp_1000hdx_cap = 0;
5132 5164 igb->param_lp_100t4_cap = 0;
5133 5165 igb->param_lp_100fdx_cap = 0;
5134 5166 igb->param_lp_100hdx_cap = 0;
5135 5167 igb->param_lp_10fdx_cap = 0;
5136 5168 igb->param_lp_10hdx_cap = 0;
5137 5169 igb->param_lp_rem_fault = 0;
5138 5170 }
5139 5171 }
5140 5172
5141 5173 /*
5142 5174 * synchronize the adv* and en* parameters.
5143 5175 *
5144 5176 * See comments in <sys/dld.h> for details of the *_en_*
5145 5177 * parameters. The usage of ndd for setting adv parameters will
5146 5178 * synchronize all the en parameters with the e1000g parameters,
5147 5179 * implicitly disabling any settings made via dladm.
5148 5180 */
5149 5181 static void
5150 5182 igb_param_sync(igb_t *igb)
5151 5183 {
5152 5184 igb->param_en_1000fdx_cap = igb->param_adv_1000fdx_cap;
5153 5185 igb->param_en_1000hdx_cap = igb->param_adv_1000hdx_cap;
5154 5186 igb->param_en_100t4_cap = igb->param_adv_100t4_cap;
5155 5187 igb->param_en_100fdx_cap = igb->param_adv_100fdx_cap;
5156 5188 igb->param_en_100hdx_cap = igb->param_adv_100hdx_cap;
5157 5189 igb->param_en_10fdx_cap = igb->param_adv_10fdx_cap;
5158 5190 igb->param_en_10hdx_cap = igb->param_adv_10hdx_cap;
5159 5191 }
5160 5192
5161 5193 /*
5162 5194 * igb_get_driver_control
5163 5195 */
5164 5196 static void
5165 5197 igb_get_driver_control(struct e1000_hw *hw)
5166 5198 {
5167 5199 uint32_t ctrl_ext;
5168 5200
5169 5201 /* Notify firmware that driver is in control of device */
5170 5202 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5171 5203 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD;
5172 5204 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5173 5205 }
5174 5206
5175 5207 /*
5176 5208 * igb_release_driver_control
5177 5209 */
5178 5210 static void
5179 5211 igb_release_driver_control(struct e1000_hw *hw)
5180 5212 {
5181 5213 uint32_t ctrl_ext;
5182 5214
5183 5215 /* Notify firmware that driver is no longer in control of device */
5184 5216 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5185 5217 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD;
5186 5218 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5187 5219 }
5188 5220
5189 5221 /*
5190 5222 * igb_atomic_reserve - Atomic decrease operation
5191 5223 */
5192 5224 int
5193 5225 igb_atomic_reserve(uint32_t *count_p, uint32_t n)
5194 5226 {
5195 5227 uint32_t oldval;
5196 5228 uint32_t newval;
5197 5229
5198 5230 /* ATOMICALLY */
5199 5231 do {
5200 5232 oldval = *count_p;
5201 5233 if (oldval < n)
5202 5234 return (-1);
5203 5235 newval = oldval - n;
5204 5236 } while (atomic_cas_32(count_p, oldval, newval) != oldval);
5205 5237
5206 5238 return (newval);
5207 5239 }
5208 5240
5209 5241 /*
5210 5242 * FMA support
5211 5243 */
5212 5244
5213 5245 int
5214 5246 igb_check_acc_handle(ddi_acc_handle_t handle)
5215 5247 {
5216 5248 ddi_fm_error_t de;
5217 5249
5218 5250 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
5219 5251 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
5220 5252 return (de.fme_status);
5221 5253 }
5222 5254
5223 5255 int
5224 5256 igb_check_dma_handle(ddi_dma_handle_t handle)
5225 5257 {
5226 5258 ddi_fm_error_t de;
5227 5259
5228 5260 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
5229 5261 return (de.fme_status);
5230 5262 }
5231 5263
5232 5264 /*
5233 5265 * The IO fault service error handling callback function
5234 5266 */
5235 5267 /*ARGSUSED*/
5236 5268 static int
5237 5269 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
5238 5270 {
5239 5271 /*
5240 5272 * as the driver can always deal with an error in any dma or
5241 5273 * access handle, we can just return the fme_status value.
5242 5274 */
5243 5275 pci_ereport_post(dip, err, NULL);
5244 5276 return (err->fme_status);
5245 5277 }
5246 5278
5247 5279 static void
5248 5280 igb_fm_init(igb_t *igb)
5249 5281 {
5250 5282 ddi_iblock_cookie_t iblk;
5251 5283 int fma_dma_flag;
5252 5284
5253 5285 /* Only register with IO Fault Services if we have some capability */
5254 5286 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
5255 5287 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
5256 5288 } else {
5257 5289 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
5258 5290 }
5259 5291
5260 5292 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
5261 5293 fma_dma_flag = 1;
5262 5294 } else {
5263 5295 fma_dma_flag = 0;
5264 5296 }
5265 5297
5266 5298 (void) igb_set_fma_flags(fma_dma_flag);
5267 5299
5268 5300 if (igb->fm_capabilities) {
5269 5301
5270 5302 /* Register capabilities with IO Fault Services */
5271 5303 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk);
5272 5304
5273 5305 /*
5274 5306 * Initialize pci ereport capabilities if ereport capable
5275 5307 */
5276 5308 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
5277 5309 DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5278 5310 pci_ereport_setup(igb->dip);
5279 5311
5280 5312 /*
5281 5313 * Register error callback if error callback capable
5282 5314 */
5283 5315 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5284 5316 ddi_fm_handler_register(igb->dip,
5285 5317 igb_fm_error_cb, (void*) igb);
5286 5318 }
5287 5319 }
5288 5320
5289 5321 static void
5290 5322 igb_fm_fini(igb_t *igb)
5291 5323 {
5292 5324 /* Only unregister FMA capabilities if we registered some */
5293 5325 if (igb->fm_capabilities) {
5294 5326
5295 5327 /*
5296 5328 * Release any resources allocated by pci_ereport_setup()
5297 5329 */
5298 5330 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
5299 5331 DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5300 5332 pci_ereport_teardown(igb->dip);
5301 5333
5302 5334 /*
5303 5335 * Un-register error callback if error callback capable
5304 5336 */
5305 5337 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5306 5338 ddi_fm_handler_unregister(igb->dip);
5307 5339
5308 5340 /* Unregister from IO Fault Services */
5309 5341 ddi_fm_fini(igb->dip);
5310 5342 }
5311 5343 }
5312 5344
5313 5345 void
5314 5346 igb_fm_ereport(igb_t *igb, char *detail)
5315 5347 {
5316 5348 uint64_t ena;
5317 5349 char buf[FM_MAX_CLASS];
5318 5350
5319 5351 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
5320 5352 ena = fm_ena_generate(0, FM_ENA_FMT1);
5321 5353 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) {
5322 5354 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP,
5323 5355 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
5324 5356 }
5325 5357 }
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