9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright 2013, Nexenta Systems, Inc. All rights reserved.
29 */
30
31 #include "igb_sw.h"
32
33 int
34 igb_m_stat(void *arg, uint_t stat, uint64_t *val)
35 {
36 igb_t *igb = (igb_t *)arg;
37 struct e1000_hw *hw = &igb->hw;
38 igb_stat_t *igb_ks;
39 uint32_t low_val, high_val;
40
41 igb_ks = (igb_stat_t *)igb->igb_ks->ks_data;
42
43 mutex_enter(&igb->gen_lock);
44
45 if (igb->igb_state & IGB_SUSPENDED) {
46 mutex_exit(&igb->gen_lock);
47 return (ECANCELED);
48 }
49
50 switch (stat) {
51 case MAC_STAT_IFSPEED:
52 *val = igb->link_speed * 1000000ull;
53 break;
54
55 case MAC_STAT_MULTIRCV:
56 igb_ks->mprc.value.ui64 +=
57 E1000_READ_REG(hw, E1000_MPRC);
58 *val = igb_ks->mprc.value.ui64;
59 break;
60
61 case MAC_STAT_BRDCSTRCV:
62 igb_ks->bprc.value.ui64 +=
63 E1000_READ_REG(hw, E1000_BPRC);
64 *val = igb_ks->bprc.value.ui64;
65 break;
66
67 case MAC_STAT_MULTIXMT:
68 igb_ks->mptc.value.ui64 +=
69 E1000_READ_REG(hw, E1000_MPTC);
70 *val = igb_ks->mptc.value.ui64;
71 break;
72
73 case MAC_STAT_BRDCSTXMT:
74 igb_ks->bptc.value.ui64 +=
75 E1000_READ_REG(hw, E1000_BPTC);
76 *val = igb_ks->bptc.value.ui64;
77 break;
78
79 case MAC_STAT_NORCVBUF:
80 igb_ks->rnbc.value.ui64 +=
81 E1000_READ_REG(hw, E1000_RNBC);
82 *val = igb_ks->rnbc.value.ui64;
83 break;
84
85 case MAC_STAT_IERRORS:
86 igb_ks->rxerrc.value.ui64 +=
87 E1000_READ_REG(hw, E1000_RXERRC);
88 igb_ks->algnerrc.value.ui64 +=
89 E1000_READ_REG(hw, E1000_ALGNERRC);
90 igb_ks->rlec.value.ui64 +=
91 E1000_READ_REG(hw, E1000_RLEC);
92 igb_ks->crcerrs.value.ui64 +=
93 E1000_READ_REG(hw, E1000_CRCERRS);
94 igb_ks->cexterr.value.ui64 +=
95 E1000_READ_REG(hw, E1000_CEXTERR);
96 *val = igb_ks->rxerrc.value.ui64 +
97 igb_ks->algnerrc.value.ui64 +
98 igb_ks->rlec.value.ui64 +
99 igb_ks->crcerrs.value.ui64 +
100 igb_ks->cexterr.value.ui64;
101 break;
102
103 case MAC_STAT_NOXMTBUF:
104 *val = 0;
105 break;
106
107 case MAC_STAT_OERRORS:
108 igb_ks->ecol.value.ui64 +=
109 E1000_READ_REG(hw, E1000_ECOL);
110 *val = igb_ks->ecol.value.ui64;
111 break;
112
113 case MAC_STAT_COLLISIONS:
114 igb_ks->colc.value.ui64 +=
115 E1000_READ_REG(hw, E1000_COLC);
116 *val = igb_ks->colc.value.ui64;
117 break;
118
119 case MAC_STAT_RBYTES:
120 /*
121 * The 64-bit register will reset whenever the upper
122 * 32 bits are read. So we need to read the lower
123 * 32 bits first, then read the upper 32 bits.
124 */
125 low_val = E1000_READ_REG(hw, E1000_TORL);
126 high_val = E1000_READ_REG(hw, E1000_TORH);
127 igb_ks->tor.value.ui64 +=
128 (uint64_t)high_val << 32 | (uint64_t)low_val;
129 *val = igb_ks->tor.value.ui64;
130 break;
131
132 case MAC_STAT_IPACKETS:
133 igb_ks->tpr.value.ui64 +=
134 E1000_READ_REG(hw, E1000_TPR);
135 *val = igb_ks->tpr.value.ui64;
136 break;
137
138 case MAC_STAT_OBYTES:
139 /*
140 * The 64-bit register will reset whenever the upper
141 * 32 bits are read. So we need to read the lower
142 * 32 bits first, then read the upper 32 bits.
143 */
144 low_val = E1000_READ_REG(hw, E1000_TOTL);
145 high_val = E1000_READ_REG(hw, E1000_TOTH);
146 igb_ks->tot.value.ui64 +=
147 (uint64_t)high_val << 32 | (uint64_t)low_val;
148 *val = igb_ks->tot.value.ui64;
149 break;
150
151 case MAC_STAT_OPACKETS:
152 igb_ks->tpt.value.ui64 +=
153 E1000_READ_REG(hw, E1000_TPT);
154 *val = igb_ks->tpt.value.ui64;
155 break;
156
157 /* RFC 1643 stats */
158 case ETHER_STAT_ALIGN_ERRORS:
159 igb_ks->algnerrc.value.ui64 +=
160 E1000_READ_REG(hw, E1000_ALGNERRC);
161 *val = igb_ks->algnerrc.value.ui64;
162 break;
163
164 case ETHER_STAT_FCS_ERRORS:
165 igb_ks->crcerrs.value.ui64 +=
166 E1000_READ_REG(hw, E1000_CRCERRS);
167 *val = igb_ks->crcerrs.value.ui64;
168 break;
169
170 case ETHER_STAT_FIRST_COLLISIONS:
171 igb_ks->scc.value.ui64 +=
172 E1000_READ_REG(hw, E1000_SCC);
173 *val = igb_ks->scc.value.ui64;
174 break;
175
176 case ETHER_STAT_MULTI_COLLISIONS:
177 igb_ks->mcc.value.ui64 +=
178 E1000_READ_REG(hw, E1000_MCC);
179 *val = igb_ks->mcc.value.ui64;
180 break;
181
182 case ETHER_STAT_SQE_ERRORS:
183 igb_ks->sec.value.ui64 +=
184 E1000_READ_REG(hw, E1000_SEC);
185 *val = igb_ks->sec.value.ui64;
186 break;
187
188 case ETHER_STAT_DEFER_XMTS:
189 igb_ks->dc.value.ui64 +=
190 E1000_READ_REG(hw, E1000_DC);
191 *val = igb_ks->dc.value.ui64;
192 break;
193
194 case ETHER_STAT_TX_LATE_COLLISIONS:
195 igb_ks->latecol.value.ui64 +=
196 E1000_READ_REG(hw, E1000_LATECOL);
197 *val = igb_ks->latecol.value.ui64;
198 break;
199
200 case ETHER_STAT_EX_COLLISIONS:
201 igb_ks->ecol.value.ui64 +=
202 E1000_READ_REG(hw, E1000_ECOL);
203 *val = igb_ks->ecol.value.ui64;
204 break;
205
206 case ETHER_STAT_MACXMT_ERRORS:
207 igb_ks->ecol.value.ui64 +=
208 E1000_READ_REG(hw, E1000_ECOL);
209 *val = igb_ks->ecol.value.ui64;
210 break;
211
212 case ETHER_STAT_CARRIER_ERRORS:
213 igb_ks->cexterr.value.ui64 +=
214 E1000_READ_REG(hw, E1000_CEXTERR);
215 *val = igb_ks->cexterr.value.ui64;
216 break;
217
218 case ETHER_STAT_TOOLONG_ERRORS:
219 igb_ks->roc.value.ui64 +=
220 E1000_READ_REG(hw, E1000_ROC);
221 *val = igb_ks->roc.value.ui64;
222 break;
223
224 case ETHER_STAT_MACRCV_ERRORS:
225 igb_ks->rxerrc.value.ui64 +=
226 E1000_READ_REG(hw, E1000_RXERRC);
227 *val = igb_ks->rxerrc.value.ui64;
228 break;
229
230 /* MII/GMII stats */
231 case ETHER_STAT_XCVR_ADDR:
232 /* The Internal PHY's MDI address for each MAC is 1 */
233 *val = 1;
234 break;
235
236 case ETHER_STAT_XCVR_ID:
237 *val = hw->phy.id | hw->phy.revision;
238 break;
239
240 case ETHER_STAT_XCVR_INUSE:
241 switch (igb->link_speed) {
242 case SPEED_1000:
243 *val =
244 (hw->phy.media_type == e1000_media_type_copper) ?
245 XCVR_1000T : XCVR_1000X;
246 break;
247 case SPEED_100:
368 break;
369
370 case ETHER_STAT_LINK_ASMPAUSE:
371 *val = igb->param_asym_pause_cap;
372 break;
373
374 case ETHER_STAT_LINK_PAUSE:
375 *val = igb->param_pause_cap;
376 break;
377
378 case ETHER_STAT_LINK_AUTONEG:
379 *val = hw->mac.autoneg;
380 break;
381
382 case ETHER_STAT_LINK_DUPLEX:
383 *val = (igb->link_duplex == FULL_DUPLEX) ?
384 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF;
385 break;
386
387 case ETHER_STAT_TOOSHORT_ERRORS:
388 igb_ks->ruc.value.ui64 +=
389 E1000_READ_REG(hw, E1000_RUC);
390 *val = igb_ks->ruc.value.ui64;
391 break;
392
393 case ETHER_STAT_CAP_REMFAULT:
394 *val = igb->param_rem_fault;
395 break;
396
397 case ETHER_STAT_ADV_REMFAULT:
398 *val = igb->param_adv_rem_fault;
399 break;
400
401 case ETHER_STAT_LP_REMFAULT:
402 *val = igb->param_lp_rem_fault;
403 break;
404
405 case ETHER_STAT_JABBER_ERRORS:
406 igb_ks->rjc.value.ui64 +=
407 E1000_READ_REG(hw, E1000_RJC);
408 *val = igb_ks->rjc.value.ui64;
409 break;
410
411 case ETHER_STAT_CAP_100T4:
412 *val = igb->param_100t4_cap;
413 break;
414
415 case ETHER_STAT_ADV_CAP_100T4:
416 *val = igb->param_adv_100t4_cap;
417 break;
418
419 case ETHER_STAT_LP_CAP_100T4:
420 *val = igb->param_lp_100t4_cap;
421 break;
422
423 default:
424 mutex_exit(&igb->gen_lock);
425 return (ENOTSUP);
426 }
427
428 mutex_exit(&igb->gen_lock);
1376 return (B_FALSE);
1377 }
1378
1379 /* ARGSUSED */
1380 int
1381 igb_set_priv_prop(igb_t *igb, const char *pr_name,
1382 uint_t pr_valsize, const void *pr_val)
1383 {
1384 int err = 0;
1385 long result;
1386 struct e1000_hw *hw = &igb->hw;
1387 int i;
1388
1389 if (strcmp(pr_name, "_eee_support") == 0) {
1390 if (pr_val == NULL)
1391 return (EINVAL);
1392 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1393 switch (result) {
1394 case 0:
1395 case 1:
1396 if (hw->mac.type != e1000_i350) {
1397 /*
1398 * For now, only supported on I350.
1399 * Add new mac.type values (or use < instead)
1400 * as new cards offer up EEE.
1401 */
1402 return (ENXIO);
1403 }
1404 /* Must set this prior to the set call. */
1405 hw->dev_spec._82575.eee_disable = !result;
1406 if (e1000_set_eee_i350(hw) != E1000_SUCCESS)
1407 err = EIO;
1408 break;
1409 default:
1410 err = EINVAL;
1411 /* FALLTHRU */
1412 }
1413 return (err);
1414 }
1415 if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
1416 if (pr_val == NULL) {
1417 err = EINVAL;
1418 return (err);
1419 }
1420 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1421 if (result < MIN_TX_COPY_THRESHOLD ||
1422 result > MAX_TX_COPY_THRESHOLD)
1423 err = EINVAL;
1424 else {
1425 igb->tx_copy_thresh = (uint32_t)result;
1426 }
1427 return (err);
1428 }
1429 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
1522 return (err);
1523 }
1524 return (ENOTSUP);
1525 }
1526
1527 int
1528 igb_get_priv_prop(igb_t *igb, const char *pr_name, uint_t pr_valsize,
1529 void *pr_val)
1530 {
1531 int value;
1532
1533 if (strcmp(pr_name, "_adv_pause_cap") == 0) {
1534 value = igb->param_adv_pause_cap;
1535 } else if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
1536 value = igb->param_adv_asym_pause_cap;
1537 } else if (strcmp(pr_name, "_eee_support") == 0) {
1538 /*
1539 * For now, only supported on I350. Add new mac.type values
1540 * (or use < instead) as new cards offer up EEE.
1541 */
1542 value = (igb->hw.mac.type != e1000_i350) ? 0 :
1543 !(igb->hw.dev_spec._82575.eee_disable);
1544 } else if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
1545 value = igb->tx_copy_thresh;
1546 } else if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
1547 value = igb->tx_recycle_thresh;
1548 } else if (strcmp(pr_name, "_tx_overload_thresh") == 0) {
1549 value = igb->tx_overload_thresh;
1550 } else if (strcmp(pr_name, "_tx_resched_thresh") == 0) {
1551 value = igb->tx_resched_thresh;
1552 } else if (strcmp(pr_name, "_rx_copy_thresh") == 0) {
1553 value = igb->rx_copy_thresh;
1554 } else if (strcmp(pr_name, "_rx_limit_per_intr") == 0) {
1555 value = igb->rx_limit_per_intr;
1556 } else if (strcmp(pr_name, "_intr_throttling") == 0) {
1557 value = igb->intr_throttling[0];
1558 } else {
1559 return (ENOTSUP);
1560 }
1561
1562 (void) snprintf(pr_val, pr_valsize, "%d", value);
1563 return (0);
|
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright 2013, Nexenta Systems, Inc. All rights reserved.
29 * Copyright 2014 Pluribus Networks Inc.
30 */
31
32 #include "igb_sw.h"
33
34 int
35 igb_m_stat(void *arg, uint_t stat, uint64_t *val)
36 {
37 igb_t *igb = (igb_t *)arg;
38 struct e1000_hw *hw = &igb->hw;
39 igb_stat_t *igb_ks;
40 uint32_t low_val, high_val;
41
42 igb_ks = (igb_stat_t *)igb->igb_ks->ks_data;
43
44 mutex_enter(&igb->gen_lock);
45
46 if (igb->igb_state & IGB_SUSPENDED) {
47 mutex_exit(&igb->gen_lock);
48 return (ECANCELED);
49 }
50
51 switch (stat) {
52 case MAC_STAT_IFSPEED:
53 *val = igb->link_speed * 1000000ull;
54 break;
55
56 case MAC_STAT_MULTIRCV:
57 igb->stat_mprc += E1000_READ_REG(hw, E1000_MPRC);
58 *val = igb->stat_mprc;
59 break;
60
61 case MAC_STAT_BRDCSTRCV:
62 igb->stat_bprc += E1000_READ_REG(hw, E1000_BPRC);
63 *val = igb->stat_bprc;
64 break;
65
66 case MAC_STAT_MULTIXMT:
67 igb->stat_mptc += E1000_READ_REG(hw, E1000_MPTC);
68 *val = igb->stat_mptc;
69 break;
70
71 case MAC_STAT_BRDCSTXMT:
72 igb->stat_bptc += E1000_READ_REG(hw, E1000_BPTC);
73 *val = igb->stat_bptc;
74 break;
75
76 case MAC_STAT_NORCVBUF:
77 igb->stat_rnbc += E1000_READ_REG(hw, E1000_RNBC);
78 *val = igb->stat_rnbc;
79 break;
80
81 case MAC_STAT_IERRORS:
82 igb->stat_rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
83 igb->stat_algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
84 igb_ks->rlec.value.ui64 +=
85 E1000_READ_REG(hw, E1000_RLEC);
86 igb->stat_crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
87 igb->stat_cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
88 *val = igb->stat_rxerrc +
89 igb->stat_algnerrc +
90 igb_ks->rlec.value.ui64 +
91 igb->stat_crcerrs +
92 igb->stat_cexterr;
93 break;
94
95 case MAC_STAT_NOXMTBUF:
96 *val = 0;
97 break;
98
99 case MAC_STAT_OERRORS:
100 igb->stat_ecol += E1000_READ_REG(hw, E1000_ECOL);
101 *val = igb->stat_ecol;
102 break;
103
104 case MAC_STAT_COLLISIONS:
105 igb->stat_colc += E1000_READ_REG(hw, E1000_COLC);
106 *val = igb->stat_colc;
107 break;
108
109 case MAC_STAT_RBYTES:
110 /*
111 * The 64-bit register will reset whenever the upper
112 * 32 bits are read. So we need to read the lower
113 * 32 bits first, then read the upper 32 bits.
114 */
115 low_val = E1000_READ_REG(hw, E1000_TORL);
116 high_val = E1000_READ_REG(hw, E1000_TORH);
117 igb->stat_tor += (uint64_t)high_val << 32 | (uint64_t)low_val;
118 *val = igb->stat_tor;
119 break;
120
121 case MAC_STAT_IPACKETS:
122 igb->stat_tpr += E1000_READ_REG(hw, E1000_TPR);
123 *val = igb->stat_tpr;
124 break;
125
126 case MAC_STAT_OBYTES:
127 /*
128 * The 64-bit register will reset whenever the upper
129 * 32 bits are read. So we need to read the lower
130 * 32 bits first, then read the upper 32 bits.
131 */
132 low_val = E1000_READ_REG(hw, E1000_TOTL);
133 high_val = E1000_READ_REG(hw, E1000_TOTH);
134 igb->stat_tot += (uint64_t)high_val << 32 | (uint64_t)low_val;
135 *val = igb->stat_tot;
136 break;
137
138 case MAC_STAT_OPACKETS:
139 igb->stat_tpt += E1000_READ_REG(hw, E1000_TPT);
140 *val = igb->stat_tpt;
141 break;
142
143 /* RFC 1643 stats */
144 case ETHER_STAT_ALIGN_ERRORS:
145 igb->stat_algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
146 *val = igb->stat_algnerrc;
147 break;
148
149 case ETHER_STAT_FCS_ERRORS:
150 igb->stat_crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
151 *val = igb->stat_crcerrs;
152 break;
153
154 case ETHER_STAT_FIRST_COLLISIONS:
155 igb->stat_scc += E1000_READ_REG(hw, E1000_SCC);
156 *val = igb->stat_scc;
157 break;
158
159 case ETHER_STAT_MULTI_COLLISIONS:
160 igb->stat_mcc += E1000_READ_REG(hw, E1000_MCC);
161 *val = igb->stat_mcc;
162 break;
163
164 case ETHER_STAT_SQE_ERRORS:
165 igb->stat_sec += E1000_READ_REG(hw, E1000_SEC);
166 *val = igb->stat_sec;
167 break;
168
169 case ETHER_STAT_DEFER_XMTS:
170 igb->stat_dc += E1000_READ_REG(hw, E1000_DC);
171 *val = igb->stat_dc;
172 break;
173
174 case ETHER_STAT_TX_LATE_COLLISIONS:
175 igb->stat_latecol += E1000_READ_REG(hw, E1000_LATECOL);
176 *val = igb->stat_latecol;
177 break;
178
179 case ETHER_STAT_EX_COLLISIONS:
180 igb->stat_ecol += E1000_READ_REG(hw, E1000_ECOL);
181 *val = igb->stat_ecol;
182 break;
183
184 case ETHER_STAT_MACXMT_ERRORS:
185 igb->stat_ecol += E1000_READ_REG(hw, E1000_ECOL);
186 *val = igb->stat_ecol;
187 break;
188
189 case ETHER_STAT_CARRIER_ERRORS:
190 igb->stat_cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
191 *val = igb->stat_cexterr;
192 break;
193
194 case ETHER_STAT_TOOLONG_ERRORS:
195 igb->stat_roc += E1000_READ_REG(hw, E1000_ROC);
196 *val = igb->stat_roc;
197 break;
198
199 case ETHER_STAT_MACRCV_ERRORS:
200 igb->stat_rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
201 *val = igb->stat_rxerrc;
202 break;
203
204 /* MII/GMII stats */
205 case ETHER_STAT_XCVR_ADDR:
206 /* The Internal PHY's MDI address for each MAC is 1 */
207 *val = 1;
208 break;
209
210 case ETHER_STAT_XCVR_ID:
211 *val = hw->phy.id | hw->phy.revision;
212 break;
213
214 case ETHER_STAT_XCVR_INUSE:
215 switch (igb->link_speed) {
216 case SPEED_1000:
217 *val =
218 (hw->phy.media_type == e1000_media_type_copper) ?
219 XCVR_1000T : XCVR_1000X;
220 break;
221 case SPEED_100:
342 break;
343
344 case ETHER_STAT_LINK_ASMPAUSE:
345 *val = igb->param_asym_pause_cap;
346 break;
347
348 case ETHER_STAT_LINK_PAUSE:
349 *val = igb->param_pause_cap;
350 break;
351
352 case ETHER_STAT_LINK_AUTONEG:
353 *val = hw->mac.autoneg;
354 break;
355
356 case ETHER_STAT_LINK_DUPLEX:
357 *val = (igb->link_duplex == FULL_DUPLEX) ?
358 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF;
359 break;
360
361 case ETHER_STAT_TOOSHORT_ERRORS:
362 igb->stat_ruc += E1000_READ_REG(hw, E1000_RUC);
363 *val = igb->stat_ruc;
364 break;
365
366 case ETHER_STAT_CAP_REMFAULT:
367 *val = igb->param_rem_fault;
368 break;
369
370 case ETHER_STAT_ADV_REMFAULT:
371 *val = igb->param_adv_rem_fault;
372 break;
373
374 case ETHER_STAT_LP_REMFAULT:
375 *val = igb->param_lp_rem_fault;
376 break;
377
378 case ETHER_STAT_JABBER_ERRORS:
379 igb->stat_rjc += E1000_READ_REG(hw, E1000_RJC);
380 *val = igb->stat_rjc;
381 break;
382
383 case ETHER_STAT_CAP_100T4:
384 *val = igb->param_100t4_cap;
385 break;
386
387 case ETHER_STAT_ADV_CAP_100T4:
388 *val = igb->param_adv_100t4_cap;
389 break;
390
391 case ETHER_STAT_LP_CAP_100T4:
392 *val = igb->param_lp_100t4_cap;
393 break;
394
395 default:
396 mutex_exit(&igb->gen_lock);
397 return (ENOTSUP);
398 }
399
400 mutex_exit(&igb->gen_lock);
1348 return (B_FALSE);
1349 }
1350
1351 /* ARGSUSED */
1352 int
1353 igb_set_priv_prop(igb_t *igb, const char *pr_name,
1354 uint_t pr_valsize, const void *pr_val)
1355 {
1356 int err = 0;
1357 long result;
1358 struct e1000_hw *hw = &igb->hw;
1359 int i;
1360
1361 if (strcmp(pr_name, "_eee_support") == 0) {
1362 if (pr_val == NULL)
1363 return (EINVAL);
1364 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1365 switch (result) {
1366 case 0:
1367 case 1:
1368 /*
1369 * For now, only supported on I350/I354.
1370 * Add new mac.type values (or use < instead)
1371 * as new cards offer up EEE.
1372 */
1373 switch (hw->mac.type) {
1374 case e1000_i350:
1375 /* Must set this prior to the set call. */
1376 hw->dev_spec._82575.eee_disable = !result;
1377 if (e1000_set_eee_i350(hw) != E1000_SUCCESS)
1378 err = EIO;
1379 break;
1380 case e1000_i354:
1381 /* Must set this prior to the set call. */
1382 hw->dev_spec._82575.eee_disable = !result;
1383 if (e1000_set_eee_i354(hw) != E1000_SUCCESS)
1384 err = EIO;
1385 break;
1386 default:
1387 return (ENXIO);
1388 }
1389 break;
1390 default:
1391 err = EINVAL;
1392 /* FALLTHRU */
1393 }
1394 return (err);
1395 }
1396 if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
1397 if (pr_val == NULL) {
1398 err = EINVAL;
1399 return (err);
1400 }
1401 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1402 if (result < MIN_TX_COPY_THRESHOLD ||
1403 result > MAX_TX_COPY_THRESHOLD)
1404 err = EINVAL;
1405 else {
1406 igb->tx_copy_thresh = (uint32_t)result;
1407 }
1408 return (err);
1409 }
1410 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
1503 return (err);
1504 }
1505 return (ENOTSUP);
1506 }
1507
1508 int
1509 igb_get_priv_prop(igb_t *igb, const char *pr_name, uint_t pr_valsize,
1510 void *pr_val)
1511 {
1512 int value;
1513
1514 if (strcmp(pr_name, "_adv_pause_cap") == 0) {
1515 value = igb->param_adv_pause_cap;
1516 } else if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
1517 value = igb->param_adv_asym_pause_cap;
1518 } else if (strcmp(pr_name, "_eee_support") == 0) {
1519 /*
1520 * For now, only supported on I350. Add new mac.type values
1521 * (or use < instead) as new cards offer up EEE.
1522 */
1523 switch (igb->hw.mac.type) {
1524 case e1000_i350:
1525 case e1000_i354:
1526 value = !(igb->hw.dev_spec._82575.eee_disable);
1527 break;
1528 default:
1529 value = 0;
1530 }
1531 } else if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
1532 value = igb->tx_copy_thresh;
1533 } else if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
1534 value = igb->tx_recycle_thresh;
1535 } else if (strcmp(pr_name, "_tx_overload_thresh") == 0) {
1536 value = igb->tx_overload_thresh;
1537 } else if (strcmp(pr_name, "_tx_resched_thresh") == 0) {
1538 value = igb->tx_resched_thresh;
1539 } else if (strcmp(pr_name, "_rx_copy_thresh") == 0) {
1540 value = igb->rx_copy_thresh;
1541 } else if (strcmp(pr_name, "_rx_limit_per_intr") == 0) {
1542 value = igb->rx_limit_per_intr;
1543 } else if (strcmp(pr_name, "_intr_throttling") == 0) {
1544 value = igb->intr_throttling[0];
1545 } else {
1546 return (ENOTSUP);
1547 }
1548
1549 (void) snprintf(pr_val, pr_valsize, "%d", value);
1550 return (0);
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