37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 #define E1000_CTRL 0x00000 /* Device Control - RW */
43 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
44 #define E1000_STATUS 0x00008 /* Device Status - RO */
45 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
46 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
47 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
48 #define E1000_FLA 0x0001C /* Flash Access - RW */
49 #define E1000_MDIC 0x00020 /* MDI Control - RW */
50 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
51 #define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */
52 #define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */
53 #define E1000_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */
54 #define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */
55 #define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */
56 #define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */
57 #define E1000_I350_BARCTRL 0x5BFC /* BAR ctrl reg */
58 #define E1000_I350_DTXMXPKTSZ 0x355C /* Maximum sent packet size reg*/
59 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
60 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
61 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
62 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
63 #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */
64 #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
65 #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
66 #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
67 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
68 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
69 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
70 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
71 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
72 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
73 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
74 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
75 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
76 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
81 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
82 #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
83 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
84 #define E1000_PBA_ECC 0x01100 /* PBA ECC Register */
85 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
86 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
87 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
88 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
89 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
90 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
91 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
92 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
93 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
94 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
95 #define E1000_TCTL 0x00400 /* Tx Control - RW */
96 #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
97 #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
98 #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
99 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
100 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
101 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
102 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
103 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
104 #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
105 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
106 #define E1000_PBS 0x01008 /* Packet Buffer Size */
107 #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
108 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
109 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
110 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
111 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
112 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
113 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
114 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
115 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
116 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
117 #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
118 #define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */
119 #define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */
120 #define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */
139 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
140 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
141 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
142 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
143 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
144 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
145 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
146 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
147 /* Split and Replication Rx Control - RW */
148 #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
149 #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
150 #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
151 #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
152 #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
153 #define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */
154 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
155 #define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */
156 #define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */
157 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
158 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
159 #define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */
160 #define E1000_I210_FLMNGCTL 0x12038
161 #define E1000_I210_FLMNGDATA 0x1203C
162 #define E1000_I210_FLMNGCNT 0x12040
163
164 #define E1000_I210_FLSWCTL 0x12048
165 #define E1000_I210_FLSWDATA 0x1204C
166 #define E1000_I210_FLSWCNT 0x12050
167
168 #define E1000_I210_FLA 0x1201C
169
170 #define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n))
171 #define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */
172
173 /* QAV Tx mode control register */
174 #define E1000_I210_TQAVCTRL 0x3570
175
176 /* QAV Tx mode control register bitfields masks */
177 /* QAV enable */
178 #define E1000_TQAVCTRL_MODE (1 << 0)
195 #define E1000_I210_TQAVHC(_n) (0x300C + 0x40 * (_n))
196
197 /* Queues fetch arbitration priority control register */
198 #define E1000_I210_TQAVARBCTRL 0x3574
199 /* Queues priority masks where _n and _p can be 0-3. */
200 #define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * _n))
201 /* QAV Tx mode control registers where _n can be 0 or 1. */
202 #define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n))
203
204 /* QAV Tx mode control register bitfields masks */
205 #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */
206 #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */
207 #define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */
208
209 /* Good transmitted packets counter registers */
210 #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n)))
211
212 /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
213 #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * _n))
214
215 /* Convenience macros
216 *
217 * Note: "_n" is the queue number of the register to be written to.
218 *
219 * Example usage:
220 * E1000_RDBAL_REG(current_rx_queue)
221 */
222 #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
223 (0x0C000 + ((_n) * 0x40)))
224 #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
225 (0x0C004 + ((_n) * 0x40)))
226 #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
227 (0x0C008 + ((_n) * 0x40)))
228 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
229 (0x0C00C + ((_n) * 0x40)))
230 #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
231 (0x0C010 + ((_n) * 0x40)))
232 #define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
233 (0x0C014 + ((_n) * 0x40)))
234 #define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
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37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 #define E1000_CTRL 0x00000 /* Device Control - RW */
43 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
44 #define E1000_STATUS 0x00008 /* Device Status - RO */
45 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
46 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
47 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
48 #define E1000_FLA 0x0001C /* Flash Access - RW */
49 #define E1000_MDIC 0x00020 /* MDI Control - RW */
50 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
51 #define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */
52 #define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */
53 #define E1000_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */
54 #define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */
55 #define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */
56 #define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */
57 #define E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */
58 #define E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */
59 #define E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */
60 #define E1000_PPHY_CTRL 0x5b48 /* PCIe PHY Control */
61 #define E1000_I350_BARCTRL 0x5BFC /* BAR ctrl reg */
62 #define E1000_I350_DTXMXPKTSZ 0x355C /* Maximum sent packet size reg*/
63 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
64 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
65 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
66 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
67 #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */
68 #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
69 #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
70 #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
71 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
72 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
73 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
74 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
75 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
76 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
77 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
78 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
79 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
80 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
85 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
86 #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
87 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
88 #define E1000_PBA_ECC 0x01100 /* PBA ECC Register */
89 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
90 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
91 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
92 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
93 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
94 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
95 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
96 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
97 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
98 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
99 #define E1000_TCTL 0x00400 /* Tx Control - RW */
100 #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
101 #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
102 #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
103 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
104 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
105 #define E1000_LEDMUX 0x08130 /* LED MUX Control */
106 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
107 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
108 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
109 #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
110 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
111 #define E1000_PBS 0x01008 /* Packet Buffer Size */
112 #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
113 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
114 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
115 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
116 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
117 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
118 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
119 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
120 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
121 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
122 #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
123 #define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */
124 #define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */
125 #define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */
144 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
145 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
146 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
147 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
148 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
149 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
150 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
151 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
152 /* Split and Replication Rx Control - RW */
153 #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
154 #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
155 #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
156 #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
157 #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
158 #define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */
159 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
160 #define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */
161 #define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */
162 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
163 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
164 #define E1000_EMIADD 0x10 /* Extended Memory Indirect Address */
165 #define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */
166 #define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */
167 #define E1000_I210_FLMNGCTL 0x12038
168 #define E1000_I210_FLMNGDATA 0x1203C
169 #define E1000_I210_FLMNGCNT 0x12040
170
171 #define E1000_I210_FLSWCTL 0x12048
172 #define E1000_I210_FLSWDATA 0x1204C
173 #define E1000_I210_FLSWCNT 0x12050
174
175 #define E1000_I210_FLA 0x1201C
176
177 #define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n))
178 #define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */
179
180 /* QAV Tx mode control register */
181 #define E1000_I210_TQAVCTRL 0x3570
182
183 /* QAV Tx mode control register bitfields masks */
184 /* QAV enable */
185 #define E1000_TQAVCTRL_MODE (1 << 0)
202 #define E1000_I210_TQAVHC(_n) (0x300C + 0x40 * (_n))
203
204 /* Queues fetch arbitration priority control register */
205 #define E1000_I210_TQAVARBCTRL 0x3574
206 /* Queues priority masks where _n and _p can be 0-3. */
207 #define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * _n))
208 /* QAV Tx mode control registers where _n can be 0 or 1. */
209 #define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n))
210
211 /* QAV Tx mode control register bitfields masks */
212 #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */
213 #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */
214 #define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */
215
216 /* Good transmitted packets counter registers */
217 #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n)))
218
219 /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
220 #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * _n))
221
222 #define E1000_MMDAC 13 /* MMD Access Control */
223 #define E1000_MMDAAD 14 /* MMD Access Address/Data */
224
225 /* Convenience macros
226 *
227 * Note: "_n" is the queue number of the register to be written to.
228 *
229 * Example usage:
230 * E1000_RDBAL_REG(current_rx_queue)
231 */
232 #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
233 (0x0C000 + ((_n) * 0x40)))
234 #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
235 (0x0C004 + ((_n) * 0x40)))
236 #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
237 (0x0C008 + ((_n) * 0x40)))
238 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
239 (0x0C00C + ((_n) * 0x40)))
240 #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
241 (0x0C010 + ((_n) * 0x40)))
242 #define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
243 (0x0C014 + ((_n) * 0x40)))
244 #define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
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