4431 igb support for I354
4616 igb has uninitialized kstats

*** 52,61 ****
--- 52,65 ----
  #define E1000_EEPROM_INIT_CTRL_WORD_2   0x0F /* EEPROM Init Ctrl Word 2 */
  #define E1000_EEPROM_PCIE_CTRL_WORD_2   0x28 /* EEPROM PCIe Ctrl Word 2 */
  #define E1000_BARCTRL                   0x5BBC /* BAR ctrl reg */
  #define E1000_BARCTRL_FLSIZE            0x0700 /* BAR ctrl Flsize */
  #define E1000_BARCTRL_CSRSIZE           0x2000 /* BAR ctrl CSR size */
+ #define E1000_MPHY_ADDR_CTRL            0x0024 /* GbE MPHY Address Control */
+ #define E1000_MPHY_DATA                 0x0E10 /* GBE MPHY Data */
+ #define E1000_MPHY_STAT                 0x0E0C /* GBE MPHY Statistics */
+ #define E1000_PPHY_CTRL                 0x5b48 /* PCIe PHY Control */
  #define E1000_I350_BARCTRL              0x5BFC /* BAR ctrl reg */
  #define E1000_I350_DTXMXPKTSZ           0x355C /* Maximum sent packet size reg*/
  #define E1000_SCTL      0x00024  /* SerDes Control - RW */
  #define E1000_FCAL      0x00028  /* Flow Control Address Low - RW */
  #define E1000_FCAH      0x0002C  /* Flow Control Address High -RW */
*** 96,105 ****
--- 100,110 ----
  #define E1000_TCTL_EXT  0x00404  /* Extended Tx Control - RW */
  #define E1000_TIPG      0x00410  /* Tx Inter-packet gap -RW */
  #define E1000_TBT       0x00448  /* Tx Burst Timer - RW */
  #define E1000_AIT       0x00458  /* Adaptive Interframe Spacing Throttle - RW */
  #define E1000_LEDCTL    0x00E00  /* LED Control - RW */
+ #define E1000_LEDMUX    0x08130 /* LED MUX Control */
  #define E1000_EXTCNF_CTRL       0x00F00  /* Extended Configuration Control */
  #define E1000_EXTCNF_SIZE       0x00F08  /* Extended Configuration Size */
  #define E1000_PHY_CTRL  0x00F10  /* PHY Control Register in CSR */
  #define E1000_POEMB     E1000_PHY_CTRL /* PHY OEM Bits */
  #define E1000_PBA       0x01000  /* Packet Buffer Allocation - RW */
*** 154,163 ****
--- 159,170 ----
  #define E1000_RXPBS     0x02404  /* Rx Packet Buffer Size - RW */
  #define E1000_IRPBS     0x02404 /* Same as RXPBS, renamed for newer Si - RW */
  #define E1000_PBRWAC    0x024E8 /* Rx packet buffer wrap around counter - RO */
  #define E1000_RDTR      0x02820  /* Rx Delay Timer - RW */
  #define E1000_RADV      0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
+ #define E1000_EMIADD    0x10    /* Extended Memory Indirect Address */
+ #define E1000_EMIDATA   0x11    /* Extended Memory Indirect Data */
  #define E1000_SRWR              0x12018  /* Shadow Ram Write Register - RW */
  #define E1000_I210_FLMNGCTL     0x12038
  #define E1000_I210_FLMNGDATA    0x1203C
  #define E1000_I210_FLMNGCNT     0x12040
  
*** 210,219 ****
--- 217,229 ----
  #define E1000_PQGPTC(_n)                (0x010014 + (0x100 * (_n)))
  
  /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
  #define E1000_I210_TXPBS_SIZE(_n, _s)   ((_s) << (6 * _n))
  
+ #define E1000_MMDAC                     13 /* MMD Access Control */
+ #define E1000_MMDAAD                    14 /* MMD Access Address/Data */
+ 
  /* Convenience macros
   *
   * Note: "_n" is the queue number of the register to be written to.
   *
   * Example usage: