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4431 igb support for I354
4616 igb has uninitialized kstats
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--- old/usr/src/uts/common/io/e1000api/e1000_hw.h
+++ new/usr/src/uts/common/io/e1000api/e1000_hw.h
1 1 /******************************************************************************
2 2
3 3 Copyright (c) 2001-2013, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD$*/
34 34
35 35 #ifndef _E1000_HW_H_
36 36 #define _E1000_HW_H_
37 37
38 38 #ifdef __cplusplus
39 39 extern "C" {
40 40 #endif
41 41
42 42 #include "e1000_osdep.h"
43 43 #include "e1000_regs.h"
44 44 #include "e1000_defines.h"
45 45
46 46 struct e1000_hw;
47 47
48 48 #define E1000_DEV_ID_82542 0x1000
49 49 #define E1000_DEV_ID_82543GC_FIBER 0x1001
50 50 #define E1000_DEV_ID_82543GC_COPPER 0x1004
51 51 #define E1000_DEV_ID_82544EI_COPPER 0x1008
52 52 #define E1000_DEV_ID_82544EI_FIBER 0x1009
53 53 #define E1000_DEV_ID_82544GC_COPPER 0x100C
54 54 #define E1000_DEV_ID_82544GC_LOM 0x100D
55 55 #define E1000_DEV_ID_82540EM 0x100E
56 56 #define E1000_DEV_ID_82540EM_LOM 0x1015
57 57 #define E1000_DEV_ID_82540EP_LOM 0x1016
58 58 #define E1000_DEV_ID_82540EP 0x1017
59 59 #define E1000_DEV_ID_82540EP_LP 0x101E
60 60 #define E1000_DEV_ID_82545EM_COPPER 0x100F
61 61 #define E1000_DEV_ID_82545EM_FIBER 0x1011
62 62 #define E1000_DEV_ID_82545GM_COPPER 0x1026
63 63 #define E1000_DEV_ID_82545GM_FIBER 0x1027
64 64 #define E1000_DEV_ID_82545GM_SERDES 0x1028
65 65 #define E1000_DEV_ID_82546EB_COPPER 0x1010
66 66 #define E1000_DEV_ID_82546EB_FIBER 0x1012
67 67 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
68 68 #define E1000_DEV_ID_82546GB_COPPER 0x1079
69 69 #define E1000_DEV_ID_82546GB_FIBER 0x107A
70 70 #define E1000_DEV_ID_82546GB_SERDES 0x107B
71 71 #define E1000_DEV_ID_82546GB_PCIE 0x108A
72 72 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
73 73 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
74 74 #define E1000_DEV_ID_82541EI 0x1013
75 75 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
76 76 #define E1000_DEV_ID_82541ER_LOM 0x1014
77 77 #define E1000_DEV_ID_82541ER 0x1078
78 78 #define E1000_DEV_ID_82541GI 0x1076
79 79 #define E1000_DEV_ID_82541GI_LF 0x107C
80 80 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
81 81 #define E1000_DEV_ID_82547EI 0x1019
82 82 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
83 83 #define E1000_DEV_ID_82547GI 0x1075
84 84 #define E1000_DEV_ID_82571EB_COPPER 0x105E
85 85 #define E1000_DEV_ID_82571EB_FIBER 0x105F
86 86 #define E1000_DEV_ID_82571EB_SERDES 0x1060
87 87 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
88 88 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
89 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
90 90 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
91 91 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
92 92 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
93 93 #define E1000_DEV_ID_82572EI_COPPER 0x107D
94 94 #define E1000_DEV_ID_82572EI_FIBER 0x107E
95 95 #define E1000_DEV_ID_82572EI_SERDES 0x107F
96 96 #define E1000_DEV_ID_82572EI 0x10B9
97 97 #define E1000_DEV_ID_82573E 0x108B
98 98 #define E1000_DEV_ID_82573E_IAMT 0x108C
99 99 #define E1000_DEV_ID_82573L 0x109A
100 100 #define E1000_DEV_ID_82574L 0x10D3
101 101 #define E1000_DEV_ID_82574LA 0x10F6
102 102 #define E1000_DEV_ID_82583V 0x150C
103 103 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
104 104 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
105 105 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
106 106 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
107 107 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
108 108 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
109 109 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
110 110 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
111 111 #define E1000_DEV_ID_ICH8_IFE 0x104C
112 112 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
113 113 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
114 114 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
115 115 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
116 116 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
117 117 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
118 118 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
119 119 #define E1000_DEV_ID_ICH9_BM 0x10E5
120 120 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
121 121 #define E1000_DEV_ID_ICH9_IFE 0x10C0
122 122 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
123 123 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
124 124 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
125 125 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
126 126 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
127 127 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
128 128 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
129 129 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
130 130 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
131 131 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
132 132 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
133 133 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
134 134 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
135 135 #define E1000_DEV_ID_PCH2_LV_V 0x1503
136 136 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
137 137 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
138 138 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
139 139 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
140 140 #define E1000_DEV_ID_82576 0x10C9
141 141 #define E1000_DEV_ID_82576_FIBER 0x10E6
142 142 #define E1000_DEV_ID_82576_SERDES 0x10E7
143 143 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
144 144 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
145 145 #define E1000_DEV_ID_82576_NS 0x150A
146 146 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
147 147 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
148 148 #define E1000_DEV_ID_82576_VF 0x10CA
149 149 #define E1000_DEV_ID_82576_VF_HV 0x152D
150 150 #define E1000_DEV_ID_I350_VF 0x1520
151 151 #define E1000_DEV_ID_I350_VF_HV 0x152F
152 152 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
153 153 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
154 154 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
155 155 #define E1000_DEV_ID_82580_COPPER 0x150E
156 156 #define E1000_DEV_ID_82580_FIBER 0x150F
157 157 #define E1000_DEV_ID_82580_SERDES 0x1510
158 158 #define E1000_DEV_ID_82580_SGMII 0x1511
159 159 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
160 160 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
161 161 #define E1000_DEV_ID_I350_COPPER 0x1521
162 162 #define E1000_DEV_ID_I350_FIBER 0x1522
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163 163 #define E1000_DEV_ID_I350_SERDES 0x1523
164 164 #define E1000_DEV_ID_I350_SGMII 0x1524
165 165 #define E1000_DEV_ID_I350_DA4 0x1546
166 166 #define E1000_DEV_ID_I210_COPPER 0x1533
167 167 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
168 168 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
169 169 #define E1000_DEV_ID_I210_FIBER 0x1536
170 170 #define E1000_DEV_ID_I210_SERDES 0x1537
171 171 #define E1000_DEV_ID_I210_SGMII 0x1538
172 172 #define E1000_DEV_ID_I211_COPPER 0x1539
173 +#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
174 +#define E1000_DEV_ID_I354_SGMII 0x1F41
175 +#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
173 176 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
174 177 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
175 178 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
176 179 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
177 180
178 181 #define E1000_REVISION_0 0
179 182 #define E1000_REVISION_1 1
180 183 #define E1000_REVISION_2 2
181 184 #define E1000_REVISION_3 3
182 185 #define E1000_REVISION_4 4
183 186
184 187 #define E1000_FUNC_0 0
185 188 #define E1000_FUNC_1 1
186 189 #define E1000_FUNC_2 2
187 190 #define E1000_FUNC_3 3
188 191
189 192 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
190 193 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
191 194 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
192 195 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
193 196
194 197 enum e1000_mac_type {
195 198 e1000_undefined = 0,
196 199 e1000_82542,
197 200 e1000_82543,
198 201 e1000_82544,
199 202 e1000_82540,
200 203 e1000_82545,
201 204 e1000_82545_rev_3,
202 205 e1000_82546,
203 206 e1000_82546_rev_3,
204 207 e1000_82541,
205 208 e1000_82541_rev_2,
206 209 e1000_82547,
207 210 e1000_82547_rev_2,
208 211 e1000_82571,
209 212 e1000_82572,
210 213 e1000_82573,
211 214 e1000_82574,
212 215 e1000_82583,
213 216 e1000_80003es2lan,
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214 217 e1000_ich8lan,
215 218 e1000_ich9lan,
216 219 e1000_ich10lan,
217 220 e1000_pchlan,
218 221 e1000_pch2lan,
219 222 e1000_pch_lpt,
220 223 e1000_82575,
221 224 e1000_82576,
222 225 e1000_82580,
223 226 e1000_i350,
227 + e1000_i354,
224 228 e1000_i210,
225 229 e1000_i211,
226 230 e1000_vfadapt,
227 231 e1000_vfadapt_i350,
228 232 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
229 233 };
230 234
231 235 enum e1000_media_type {
232 236 e1000_media_type_unknown = 0,
233 237 e1000_media_type_copper = 1,
234 238 e1000_media_type_fiber = 2,
235 239 e1000_media_type_internal_serdes = 3,
236 240 e1000_num_media_types
237 241 };
238 242
239 243 enum e1000_nvm_type {
240 244 e1000_nvm_unknown = 0,
241 245 e1000_nvm_none,
242 246 e1000_nvm_eeprom_spi,
243 247 e1000_nvm_eeprom_microwire,
244 248 e1000_nvm_flash_hw,
245 249 e1000_nvm_flash_sw
246 250 };
247 251
248 252 enum e1000_nvm_override {
249 253 e1000_nvm_override_none = 0,
250 254 e1000_nvm_override_spi_small,
251 255 e1000_nvm_override_spi_large,
252 256 e1000_nvm_override_microwire_small,
253 257 e1000_nvm_override_microwire_large
254 258 };
255 259
256 260 enum e1000_phy_type {
257 261 e1000_phy_unknown = 0,
258 262 e1000_phy_none,
259 263 e1000_phy_m88,
260 264 e1000_phy_igp,
261 265 e1000_phy_igp_2,
262 266 e1000_phy_gg82563,
263 267 e1000_phy_igp_3,
264 268 e1000_phy_ife,
265 269 e1000_phy_bm,
266 270 e1000_phy_82578,
267 271 e1000_phy_82577,
268 272 e1000_phy_82579,
269 273 e1000_phy_i217,
270 274 e1000_phy_82580,
271 275 e1000_phy_vf,
272 276 e1000_phy_i210,
273 277 };
274 278
275 279 enum e1000_bus_type {
276 280 e1000_bus_type_unknown = 0,
277 281 e1000_bus_type_pci,
278 282 e1000_bus_type_pcix,
279 283 e1000_bus_type_pci_express,
280 284 e1000_bus_type_reserved
281 285 };
282 286
283 287 enum e1000_bus_speed {
284 288 e1000_bus_speed_unknown = 0,
285 289 e1000_bus_speed_33,
286 290 e1000_bus_speed_66,
287 291 e1000_bus_speed_100,
288 292 e1000_bus_speed_120,
289 293 e1000_bus_speed_133,
290 294 e1000_bus_speed_2500,
291 295 e1000_bus_speed_5000,
292 296 e1000_bus_speed_reserved
293 297 };
294 298
295 299 enum e1000_bus_width {
296 300 e1000_bus_width_unknown = 0,
297 301 e1000_bus_width_pcie_x1,
298 302 e1000_bus_width_pcie_x2,
299 303 e1000_bus_width_pcie_x4 = 4,
300 304 e1000_bus_width_pcie_x8 = 8,
301 305 e1000_bus_width_32,
302 306 e1000_bus_width_64,
303 307 e1000_bus_width_reserved
304 308 };
305 309
306 310 enum e1000_1000t_rx_status {
307 311 e1000_1000t_rx_status_not_ok = 0,
308 312 e1000_1000t_rx_status_ok,
309 313 e1000_1000t_rx_status_undefined = 0xFF
310 314 };
311 315
312 316 enum e1000_rev_polarity {
313 317 e1000_rev_polarity_normal = 0,
314 318 e1000_rev_polarity_reversed,
315 319 e1000_rev_polarity_undefined = 0xFF
316 320 };
317 321
318 322 enum e1000_fc_mode {
319 323 e1000_fc_none = 0,
320 324 e1000_fc_rx_pause,
321 325 e1000_fc_tx_pause,
322 326 e1000_fc_full,
323 327 e1000_fc_default = 0xFF
324 328 };
325 329
326 330 enum e1000_ffe_config {
327 331 e1000_ffe_config_enabled = 0,
328 332 e1000_ffe_config_active,
329 333 e1000_ffe_config_blocked
330 334 };
331 335
332 336 enum e1000_dsp_config {
333 337 e1000_dsp_config_disabled = 0,
334 338 e1000_dsp_config_enabled,
335 339 e1000_dsp_config_activated,
336 340 e1000_dsp_config_undefined = 0xFF
337 341 };
338 342
339 343 enum e1000_ms_type {
340 344 e1000_ms_hw_default = 0,
341 345 e1000_ms_force_master,
342 346 e1000_ms_force_slave,
343 347 e1000_ms_auto
344 348 };
345 349
346 350 enum e1000_smart_speed {
347 351 e1000_smart_speed_default = 0,
348 352 e1000_smart_speed_on,
349 353 e1000_smart_speed_off
350 354 };
351 355
352 356 enum e1000_serdes_link_state {
353 357 e1000_serdes_link_down = 0,
354 358 e1000_serdes_link_autoneg_progress,
355 359 e1000_serdes_link_autoneg_complete,
356 360 e1000_serdes_link_forced_up
357 361 };
358 362
359 363 /* Receive Descriptor */
360 364 struct e1000_rx_desc {
361 365 __le64 buffer_addr; /* Address of the descriptor's data buffer */
362 366 __le16 length; /* Length of data DMAed into data buffer */
363 367 __le16 csum; /* Packet checksum */
364 368 u8 status; /* Descriptor status */
365 369 u8 errors; /* Descriptor Errors */
366 370 __le16 special;
367 371 };
368 372
369 373 /* Receive Descriptor - Extended */
370 374 union e1000_rx_desc_extended {
371 375 struct {
372 376 __le64 buffer_addr;
373 377 __le64 reserved;
374 378 } read;
375 379 struct {
376 380 struct {
377 381 __le32 mrq; /* Multiple Rx Queues */
378 382 union {
379 383 __le32 rss; /* RSS Hash */
380 384 struct {
381 385 __le16 ip_id; /* IP id */
382 386 __le16 csum; /* Packet Checksum */
383 387 } csum_ip;
384 388 } hi_dword;
385 389 } lower;
386 390 struct {
387 391 __le32 status_error; /* ext status/error */
388 392 __le16 length;
389 393 __le16 vlan; /* VLAN tag */
390 394 } upper;
391 395 } wb; /* writeback */
392 396 };
393 397
394 398 #define MAX_PS_BUFFERS 4
395 399 /* Receive Descriptor - Packet Split */
396 400 union e1000_rx_desc_packet_split {
397 401 struct {
398 402 /* one buffer for protocol header(s), three data buffers */
399 403 __le64 buffer_addr[MAX_PS_BUFFERS];
400 404 } read;
401 405 struct {
402 406 struct {
403 407 __le32 mrq; /* Multiple Rx Queues */
404 408 union {
405 409 __le32 rss; /* RSS Hash */
406 410 struct {
407 411 __le16 ip_id; /* IP id */
408 412 __le16 csum; /* Packet Checksum */
409 413 } csum_ip;
410 414 } hi_dword;
411 415 } lower;
412 416 struct {
413 417 __le32 status_error; /* ext status/error */
414 418 __le16 length0; /* length of buffer 0 */
415 419 __le16 vlan; /* VLAN tag */
416 420 } middle;
417 421 struct {
418 422 __le16 header_status;
419 423 __le16 length[3]; /* length of buffers 1-3 */
420 424 } upper;
421 425 __le64 reserved;
422 426 } wb; /* writeback */
423 427 };
424 428
425 429 /* Transmit Descriptor */
426 430 struct e1000_tx_desc {
427 431 __le64 buffer_addr; /* Address of the descriptor's data buffer */
428 432 union {
429 433 __le32 data;
430 434 struct {
431 435 __le16 length; /* Data buffer length */
432 436 u8 cso; /* Checksum offset */
433 437 u8 cmd; /* Descriptor control */
434 438 } flags;
435 439 } lower;
436 440 union {
437 441 __le32 data;
438 442 struct {
439 443 u8 status; /* Descriptor status */
440 444 u8 css; /* Checksum start */
441 445 __le16 special;
442 446 } fields;
443 447 } upper;
444 448 };
445 449
446 450 /* Offload Context Descriptor */
447 451 struct e1000_context_desc {
448 452 union {
449 453 __le32 ip_config;
450 454 struct {
451 455 u8 ipcss; /* IP checksum start */
452 456 u8 ipcso; /* IP checksum offset */
453 457 __le16 ipcse; /* IP checksum end */
454 458 } ip_fields;
455 459 } lower_setup;
456 460 union {
457 461 __le32 tcp_config;
458 462 struct {
459 463 u8 tucss; /* TCP checksum start */
460 464 u8 tucso; /* TCP checksum offset */
461 465 __le16 tucse; /* TCP checksum end */
462 466 } tcp_fields;
463 467 } upper_setup;
464 468 __le32 cmd_and_length;
465 469 union {
466 470 __le32 data;
467 471 struct {
468 472 u8 status; /* Descriptor status */
469 473 u8 hdr_len; /* Header length */
470 474 __le16 mss; /* Maximum segment size */
471 475 } fields;
472 476 } tcp_seg_setup;
473 477 };
474 478
475 479 /* Offload data descriptor */
476 480 struct e1000_data_desc {
477 481 __le64 buffer_addr; /* Address of the descriptor's buffer address */
478 482 union {
479 483 __le32 data;
480 484 struct {
481 485 __le16 length; /* Data buffer length */
482 486 u8 typ_len_ext;
483 487 u8 cmd;
484 488 } flags;
485 489 } lower;
486 490 union {
487 491 __le32 data;
488 492 struct {
489 493 u8 status; /* Descriptor status */
490 494 u8 popts; /* Packet Options */
491 495 __le16 special;
492 496 } fields;
493 497 } upper;
494 498 };
495 499
496 500 /* Statistics counters collected by the MAC */
497 501 struct e1000_hw_stats {
498 502 u64 crcerrs;
499 503 u64 algnerrc;
500 504 u64 symerrs;
501 505 u64 rxerrc;
502 506 u64 mpc;
503 507 u64 scc;
504 508 u64 ecol;
505 509 u64 mcc;
506 510 u64 latecol;
507 511 u64 colc;
508 512 u64 dc;
509 513 u64 tncrs;
510 514 u64 sec;
511 515 u64 cexterr;
512 516 u64 rlec;
513 517 u64 xonrxc;
514 518 u64 xontxc;
515 519 u64 xoffrxc;
516 520 u64 xofftxc;
517 521 u64 fcruc;
518 522 u64 prc64;
519 523 u64 prc127;
520 524 u64 prc255;
521 525 u64 prc511;
522 526 u64 prc1023;
523 527 u64 prc1522;
524 528 u64 gprc;
525 529 u64 bprc;
526 530 u64 mprc;
527 531 u64 gptc;
528 532 u64 gorc;
529 533 u64 gotc;
530 534 u64 rnbc;
531 535 u64 ruc;
532 536 u64 rfc;
533 537 u64 roc;
534 538 u64 rjc;
535 539 u64 mgprc;
536 540 u64 mgpdc;
537 541 u64 mgptc;
538 542 u64 tor;
539 543 u64 tot;
540 544 u64 tpr;
541 545 u64 tpt;
542 546 u64 ptc64;
543 547 u64 ptc127;
544 548 u64 ptc255;
545 549 u64 ptc511;
546 550 u64 ptc1023;
547 551 u64 ptc1522;
548 552 u64 mptc;
549 553 u64 bptc;
550 554 u64 tsctc;
551 555 u64 tsctfc;
552 556 u64 iac;
553 557 u64 icrxptc;
554 558 u64 icrxatc;
555 559 u64 ictxptc;
556 560 u64 ictxatc;
557 561 u64 ictxqec;
558 562 u64 ictxqmtc;
559 563 u64 icrxdmtc;
560 564 u64 icrxoc;
561 565 u64 cbtmpc;
562 566 u64 htdpmc;
563 567 u64 cbrdpc;
564 568 u64 cbrmpc;
565 569 u64 rpthc;
566 570 u64 hgptc;
567 571 u64 htcbdpc;
568 572 u64 hgorc;
569 573 u64 hgotc;
570 574 u64 lenerrs;
571 575 u64 scvpc;
572 576 u64 hrmpc;
573 577 u64 doosync;
574 578 u64 o2bgptc;
575 579 u64 o2bspc;
576 580 u64 b2ospc;
577 581 u64 b2ogprc;
578 582 };
579 583
580 584 struct e1000_vf_stats {
581 585 u64 base_gprc;
582 586 u64 base_gptc;
583 587 u64 base_gorc;
584 588 u64 base_gotc;
585 589 u64 base_mprc;
586 590 u64 base_gotlbc;
587 591 u64 base_gptlbc;
588 592 u64 base_gorlbc;
589 593 u64 base_gprlbc;
590 594
591 595 u32 last_gprc;
592 596 u32 last_gptc;
593 597 u32 last_gorc;
594 598 u32 last_gotc;
595 599 u32 last_mprc;
596 600 u32 last_gotlbc;
597 601 u32 last_gptlbc;
598 602 u32 last_gorlbc;
599 603 u32 last_gprlbc;
600 604
601 605 u64 gprc;
602 606 u64 gptc;
603 607 u64 gorc;
604 608 u64 gotc;
605 609 u64 mprc;
606 610 u64 gotlbc;
607 611 u64 gptlbc;
608 612 u64 gorlbc;
609 613 u64 gprlbc;
610 614 };
611 615
612 616 struct e1000_phy_stats {
613 617 u32 idle_errors;
614 618 u32 receive_errors;
615 619 };
616 620
617 621 struct e1000_host_mng_dhcp_cookie {
618 622 u32 signature;
619 623 u8 status;
620 624 u8 reserved0;
621 625 u16 vlan_id;
622 626 u32 reserved1;
623 627 u16 reserved2;
624 628 u8 reserved3;
625 629 u8 checksum;
626 630 };
627 631
628 632 /* Host Interface "Rev 1" */
629 633 struct e1000_host_command_header {
630 634 u8 command_id;
631 635 u8 command_length;
632 636 u8 command_options;
633 637 u8 checksum;
634 638 };
635 639
636 640 #define E1000_HI_MAX_DATA_LENGTH 252
637 641 struct e1000_host_command_info {
638 642 struct e1000_host_command_header command_header;
639 643 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
640 644 };
641 645
642 646 /* Host Interface "Rev 2" */
643 647 struct e1000_host_mng_command_header {
644 648 u8 command_id;
645 649 u8 checksum;
646 650 u16 reserved1;
647 651 u16 reserved2;
648 652 u16 command_length;
649 653 };
650 654
651 655 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
652 656 struct e1000_host_mng_command_info {
653 657 struct e1000_host_mng_command_header command_header;
654 658 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
655 659 };
656 660
657 661 #include "e1000_mac.h"
658 662 #include "e1000_phy.h"
659 663 #include "e1000_nvm.h"
660 664 #include "e1000_manage.h"
661 665 #include "e1000_mbx.h"
662 666
663 667 /* Function pointers for the MAC. */
664 668 struct e1000_mac_operations {
665 669 s32 (*init_params)(struct e1000_hw *);
666 670 s32 (*id_led_init)(struct e1000_hw *);
667 671 s32 (*blink_led)(struct e1000_hw *);
668 672 bool (*check_mng_mode)(struct e1000_hw *);
669 673 s32 (*check_for_link)(struct e1000_hw *);
670 674 s32 (*cleanup_led)(struct e1000_hw *);
671 675 void (*clear_hw_cntrs)(struct e1000_hw *);
672 676 void (*clear_vfta)(struct e1000_hw *);
673 677 s32 (*get_bus_info)(struct e1000_hw *);
674 678 void (*set_lan_id)(struct e1000_hw *);
675 679 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
676 680 s32 (*led_on)(struct e1000_hw *);
677 681 s32 (*led_off)(struct e1000_hw *);
678 682 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
679 683 s32 (*reset_hw)(struct e1000_hw *);
680 684 s32 (*init_hw)(struct e1000_hw *);
681 685 void (*shutdown_serdes)(struct e1000_hw *);
682 686 void (*power_up_serdes)(struct e1000_hw *);
683 687 s32 (*setup_link)(struct e1000_hw *);
684 688 s32 (*setup_physical_interface)(struct e1000_hw *);
685 689 s32 (*setup_led)(struct e1000_hw *);
686 690 void (*write_vfta)(struct e1000_hw *, u32, u32);
687 691 void (*config_collision_dist)(struct e1000_hw *);
688 692 void (*rar_set)(struct e1000_hw *, u8*, u32);
689 693 s32 (*read_mac_addr)(struct e1000_hw *);
690 694 s32 (*validate_mdi_setting)(struct e1000_hw *);
691 695 s32 (*set_obff_timer)(struct e1000_hw *, u32);
692 696 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
693 697 void (*release_swfw_sync)(struct e1000_hw *, u16);
694 698 };
695 699
696 700 /* When to use various PHY register access functions:
697 701 *
698 702 * Func Caller
699 703 * Function Does Does When to use
700 704 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
701 705 * X_reg L,P,A n/a for simple PHY reg accesses
702 706 * X_reg_locked P,A L for multiple accesses of different regs
703 707 * on different pages
704 708 * X_reg_page A L,P for multiple accesses of different regs
705 709 * on the same page
706 710 *
707 711 * Where X=[read|write], L=locking, P=sets page, A=register access
708 712 *
709 713 */
710 714 struct e1000_phy_operations {
711 715 s32 (*init_params)(struct e1000_hw *);
712 716 s32 (*acquire)(struct e1000_hw *);
713 717 s32 (*cfg_on_link_up)(struct e1000_hw *);
714 718 s32 (*check_polarity)(struct e1000_hw *);
715 719 s32 (*check_reset_block)(struct e1000_hw *);
716 720 s32 (*commit)(struct e1000_hw *);
717 721 s32 (*force_speed_duplex)(struct e1000_hw *);
718 722 s32 (*get_cfg_done)(struct e1000_hw *hw);
719 723 s32 (*get_cable_length)(struct e1000_hw *);
720 724 s32 (*get_info)(struct e1000_hw *);
721 725 s32 (*set_page)(struct e1000_hw *, u16);
722 726 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
723 727 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
724 728 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
725 729 void (*release)(struct e1000_hw *);
726 730 s32 (*reset)(struct e1000_hw *);
727 731 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
728 732 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
729 733 s32 (*write_reg)(struct e1000_hw *, u32, u16);
730 734 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
731 735 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
732 736 void (*power_up)(struct e1000_hw *);
733 737 void (*power_down)(struct e1000_hw *);
734 738 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
735 739 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
736 740 };
737 741
738 742 /* Function pointers for the NVM. */
739 743 struct e1000_nvm_operations {
740 744 s32 (*init_params)(struct e1000_hw *);
741 745 s32 (*acquire)(struct e1000_hw *);
742 746 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
743 747 void (*release)(struct e1000_hw *);
744 748 void (*reload)(struct e1000_hw *);
745 749 s32 (*update)(struct e1000_hw *);
746 750 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
747 751 s32 (*validate)(struct e1000_hw *);
748 752 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
749 753 };
750 754
751 755 struct e1000_mac_info {
752 756 struct e1000_mac_operations ops;
753 757 u8 addr[ETH_ADDR_LEN];
754 758 u8 perm_addr[ETH_ADDR_LEN];
755 759
756 760 enum e1000_mac_type type;
757 761
758 762 u32 collision_delta;
759 763 u32 ledctl_default;
760 764 u32 ledctl_mode1;
761 765 u32 ledctl_mode2;
762 766 u32 mc_filter_type;
763 767 u32 tx_packet_delta;
764 768 u32 txcw;
765 769
766 770 u16 current_ifs_val;
767 771 u16 ifs_max_val;
768 772 u16 ifs_min_val;
769 773 u16 ifs_ratio;
770 774 u16 ifs_step_size;
771 775 u16 mta_reg_count;
772 776 u16 uta_reg_count;
773 777
774 778 /* Maximum size of the MTA register table in all supported adapters */
775 779 #define MAX_MTA_REG 128
776 780 u32 mta_shadow[MAX_MTA_REG];
777 781 u16 rar_entry_count;
778 782
779 783 u8 forced_speed_duplex;
780 784
781 785 bool adaptive_ifs;
782 786 bool has_fwsm;
783 787 bool arc_subsystem_valid;
784 788 bool asf_firmware_present;
785 789 bool autoneg;
786 790 bool autoneg_failed;
787 791 bool get_link_status;
788 792 bool in_ifs_mode;
789 793 bool report_tx_early;
790 794 enum e1000_serdes_link_state serdes_link_state;
791 795 bool serdes_has_link;
792 796 bool tx_pkt_filtering;
793 797 u32 max_frame_size;
794 798 };
795 799
796 800 struct e1000_phy_info {
797 801 struct e1000_phy_operations ops;
798 802 enum e1000_phy_type type;
799 803
800 804 enum e1000_1000t_rx_status local_rx;
801 805 enum e1000_1000t_rx_status remote_rx;
802 806 enum e1000_ms_type ms_type;
803 807 enum e1000_ms_type original_ms_type;
804 808 enum e1000_rev_polarity cable_polarity;
805 809 enum e1000_smart_speed smart_speed;
806 810
807 811 u32 addr;
808 812 u32 id;
809 813 u32 reset_delay_us; /* in usec */
810 814 u32 revision;
811 815
812 816 enum e1000_media_type media_type;
813 817
814 818 u16 autoneg_advertised;
815 819 u16 autoneg_mask;
816 820 u16 cable_length;
817 821 u16 max_cable_length;
818 822 u16 min_cable_length;
819 823
820 824 u8 mdix;
821 825
822 826 bool disable_polarity_correction;
823 827 bool is_mdix;
824 828 bool polarity_correction;
825 829 bool speed_downgraded;
826 830 bool autoneg_wait_to_complete;
827 831 };
828 832
829 833 struct e1000_nvm_info {
830 834 struct e1000_nvm_operations ops;
831 835 enum e1000_nvm_type type;
832 836 enum e1000_nvm_override override;
833 837
834 838 u32 flash_bank_size;
835 839 u32 flash_base_addr;
836 840
837 841 u16 word_size;
838 842 u16 delay_usec;
839 843 u16 address_bits;
840 844 u16 opcode_bits;
841 845 u16 page_size;
842 846 };
843 847
844 848 struct e1000_bus_info {
845 849 enum e1000_bus_type type;
846 850 enum e1000_bus_speed speed;
847 851 enum e1000_bus_width width;
848 852
849 853 u16 func;
850 854 u16 pci_cmd_word;
851 855 };
852 856
853 857 struct e1000_fc_info {
854 858 u32 high_water; /* Flow control high-water mark */
855 859 u32 low_water; /* Flow control low-water mark */
856 860 u16 pause_time; /* Flow control pause timer */
857 861 u16 refresh_time; /* Flow control refresh timer */
858 862 bool send_xon; /* Flow control send XON */
859 863 bool strict_ieee; /* Strict IEEE mode */
860 864 enum e1000_fc_mode current_mode; /* FC mode in effect */
861 865 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
862 866 };
863 867
864 868 struct e1000_mbx_operations {
865 869 s32 (*init_params)(struct e1000_hw *hw);
866 870 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
867 871 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
868 872 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
869 873 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
870 874 s32 (*check_for_msg)(struct e1000_hw *, u16);
871 875 s32 (*check_for_ack)(struct e1000_hw *, u16);
872 876 s32 (*check_for_rst)(struct e1000_hw *, u16);
873 877 };
874 878
875 879 struct e1000_mbx_stats {
876 880 u32 msgs_tx;
877 881 u32 msgs_rx;
878 882
879 883 u32 acks;
880 884 u32 reqs;
881 885 u32 rsts;
882 886 };
883 887
884 888 struct e1000_mbx_info {
885 889 struct e1000_mbx_operations ops;
886 890 struct e1000_mbx_stats stats;
887 891 u32 timeout;
888 892 u32 usec_delay;
889 893 u16 size;
890 894 };
891 895
892 896 struct e1000_dev_spec_82541 {
893 897 enum e1000_dsp_config dsp_config;
894 898 enum e1000_ffe_config ffe_config;
895 899 u32 tx_fifo_head;
896 900 u32 tx_fifo_start;
897 901 u32 tx_fifo_size;
898 902 u16 dsp_reset_counter;
899 903 u16 spd_default;
900 904 bool phy_init_script;
901 905 bool ttl_workaround;
902 906 };
903 907
904 908 struct e1000_dev_spec_82542 {
905 909 bool dma_fairness;
906 910 };
907 911
908 912 struct e1000_dev_spec_82543 {
909 913 u32 tbi_compatibility;
910 914 bool dma_fairness;
911 915 bool init_phy_disabled;
912 916 };
913 917
914 918 struct e1000_dev_spec_82571 {
915 919 bool laa_is_present;
916 920 u32 smb_counter;
917 921 E1000_MUTEX swflag_mutex;
918 922 };
919 923
920 924 struct e1000_dev_spec_80003es2lan {
921 925 bool mdic_wa_enable;
922 926 };
923 927
924 928 struct e1000_shadow_ram {
925 929 u16 value;
926 930 bool modified;
927 931 };
928 932
929 933 #define E1000_SHADOW_RAM_WORDS 2048
930 934
931 935 struct e1000_dev_spec_ich8lan {
932 936 bool kmrn_lock_loss_workaround_enabled;
933 937 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
934 938 E1000_MUTEX nvm_mutex;
935 939 E1000_MUTEX swflag_mutex;
936 940 bool nvm_k1_enabled;
937 941 bool eee_disable;
938 942 u16 eee_lp_ability;
939 943 };
940 944
941 945 struct e1000_dev_spec_82575 {
942 946 bool sgmii_active;
943 947 bool global_device_reset;
944 948 bool eee_disable;
945 949 bool module_plugged;
946 950 bool clear_semaphore_once;
947 951 u32 mtu;
948 952 struct sfp_e1000_flags eth_flags;
949 953 };
950 954
951 955 struct e1000_dev_spec_vf {
952 956 u32 vf_number;
953 957 u32 v2p_mailbox;
954 958 };
955 959
956 960 struct e1000_hw {
957 961 void *back;
958 962
959 963 u8 *hw_addr;
960 964 u8 *flash_address;
961 965 unsigned long io_base;
962 966
963 967 struct e1000_mac_info mac;
964 968 struct e1000_fc_info fc;
965 969 struct e1000_phy_info phy;
966 970 struct e1000_nvm_info nvm;
967 971 struct e1000_bus_info bus;
968 972 struct e1000_mbx_info mbx;
969 973 struct e1000_host_mng_dhcp_cookie mng_cookie;
970 974
971 975 union {
972 976 struct e1000_dev_spec_82541 _82541;
973 977 struct e1000_dev_spec_82542 _82542;
974 978 struct e1000_dev_spec_82543 _82543;
975 979 struct e1000_dev_spec_82571 _82571;
976 980 struct e1000_dev_spec_80003es2lan _80003es2lan;
977 981 struct e1000_dev_spec_ich8lan ich8lan;
978 982 struct e1000_dev_spec_82575 _82575;
979 983 struct e1000_dev_spec_vf vf;
980 984 } dev_spec;
981 985
982 986 u16 device_id;
983 987 u16 subsystem_vendor_id;
984 988 u16 subsystem_device_id;
985 989 u16 vendor_id;
986 990
987 991 u8 revision_id;
988 992 };
989 993
990 994 #include "e1000_82541.h"
991 995 #include "e1000_82543.h"
992 996 #include "e1000_82571.h"
993 997 #include "e1000_80003es2lan.h"
994 998 #include "e1000_ich8lan.h"
995 999 #include "e1000_82575.h"
996 1000 #include "e1000_i210.h"
997 1001
998 1002 /* These functions must be implemented by drivers */
999 1003 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1000 1004 void e1000_pci_set_mwi(struct e1000_hw *hw);
1001 1005 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1002 1006 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1003 1007 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1004 1008 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1005 1009
1006 1010 #ifdef __cplusplus
1007 1011 }
1008 1012 #endif
1009 1013
1010 1014 #endif /* _E1000_HW_H_ */
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