Print this page
4431 igb support for I354
4616 igb has uninitialized kstats
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/e1000api/e1000_defines.h
+++ new/usr/src/uts/common/io/e1000api/e1000_defines.h
1 1 /******************************************************************************
2 2
3 3 Copyright (c) 2001-2013, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD$*/
34 34
35 35 #ifndef _E1000_DEFINES_H_
36 36 #define _E1000_DEFINES_H_
37 37
38 38 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
39 39 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
40 40 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
41 41
42 42 /* Definitions for power management and wakeup registers */
43 43 /* Wake Up Control */
44 44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46 46 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
47 47
48 48 /* Wake Up Filter Control */
49 49 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
50 50 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
51 51 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
52 52 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
53 53 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
54 54 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
55 55 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
56 56 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
57 57
58 58 /* Wake Up Status */
59 59 #define E1000_WUS_LNKC E1000_WUFC_LNKC
60 60 #define E1000_WUS_MAG E1000_WUFC_MAG
61 61 #define E1000_WUS_EX E1000_WUFC_EX
62 62 #define E1000_WUS_MC E1000_WUFC_MC
63 63 #define E1000_WUS_BC E1000_WUFC_BC
64 64
65 65 /* Extended Device Control */
66 66 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */
67 67 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
68 68 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
69 69 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
70 70 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
71 71 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
72 72 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
73 73 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
74 74 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
75 75 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
76 76 /* Physical Func Reset Done Indication */
77 77 #define E1000_CTRL_EXT_PFRSTD 0x00004000
78 78 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
79 79 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
80 80 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
81 81 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
82 82 /* Offset of the link mode field in Ctrl Ext register */
83 83 #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22
84 84 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
85 85 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
86 86 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
87 87 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
88 88 #define E1000_CTRL_EXT_EIAME 0x01000000
89 89 #define E1000_CTRL_EXT_IRCA 0x00000001
90 90 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
91 91 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
92 92 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
93 93 #define E1000_CTRL_EXT_LSECCK 0x00001000
94 94 #define E1000_CTRL_EXT_PHYPDEN 0x00100000
95 95 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
96 96 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
97 97 #define E1000_I2CCMD_OPCODE_READ 0x08000000
98 98 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
99 99 #define E1000_I2CCMD_READY 0x20000000
100 100 #define E1000_I2CCMD_ERROR 0x80000000
101 101 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
102 102 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
103 103 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
104 104 #define E1000_I2CCMD_PHY_TIMEOUT 200
105 105 #define E1000_IVAR_VALID 0x80
106 106 #define E1000_GPIE_NSICR 0x00000001
107 107 #define E1000_GPIE_MSIX_MODE 0x00000010
108 108 #define E1000_GPIE_EIAME 0x40000000
109 109 #define E1000_GPIE_PBA 0x80000000
110 110
111 111 /* Receive Descriptor bit definitions */
112 112 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
113 113 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
114 114 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
115 115 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
116 116 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
117 117 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
118 118 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
119 119 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
120 120 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
121 121 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
122 122 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
123 123 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
124 124 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
125 125 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
126 126 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
127 127 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
128 128 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
129 129 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
130 130 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
131 131
132 132 #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */
133 133 #define E1000_RXDEXT_STATERR_LB 0x00040000
134 134 #define E1000_RXDEXT_STATERR_CE 0x01000000
135 135 #define E1000_RXDEXT_STATERR_SE 0x02000000
136 136 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
137 137 #define E1000_RXDEXT_STATERR_CXE 0x10000000
138 138 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
139 139 #define E1000_RXDEXT_STATERR_IPE 0x40000000
140 140 #define E1000_RXDEXT_STATERR_RXE 0x80000000
141 141
142 142 /* mask to determine if packets should be dropped due to frame errors */
143 143 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
144 144 E1000_RXD_ERR_CE | \
145 145 E1000_RXD_ERR_SE | \
146 146 E1000_RXD_ERR_SEQ | \
147 147 E1000_RXD_ERR_CXE | \
148 148 E1000_RXD_ERR_RXE)
149 149
150 150 /* Same mask, but for extended and packet split descriptors */
151 151 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
152 152 E1000_RXDEXT_STATERR_CE | \
153 153 E1000_RXDEXT_STATERR_SE | \
154 154 E1000_RXDEXT_STATERR_SEQ | \
155 155 E1000_RXDEXT_STATERR_CXE | \
156 156 E1000_RXDEXT_STATERR_RXE)
157 157
158 158 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
159 159 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
160 160 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
161 161 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
162 162 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
163 163 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
164 164
165 165 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
166 166
167 167 /* Management Control */
168 168 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
169 169 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
170 170 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
171 171 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
172 172 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
173 173 /* Enable MAC address filtering */
174 174 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
175 175 /* Enable MNG packets to host memory */
176 176 #define E1000_MANC_EN_MNG2HOST 0x00200000
177 177
178 178 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
179 179 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
180 180 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
181 181 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
182 182
183 183 /* Receive Control */
184 184 #define E1000_RCTL_RST 0x00000001 /* Software reset */
185 185 #define E1000_RCTL_EN 0x00000002 /* enable */
186 186 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
187 187 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
188 188 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
189 189 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
190 190 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
191 191 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
192 192 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
193 193 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
194 194 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
195 195 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
196 196 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
197 197 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
198 198 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
199 199 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
200 200 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
201 201 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
202 202 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
203 203 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
204 204 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
205 205 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
206 206 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
207 207 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
208 208 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
209 209 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
210 210 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
211 211 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
212 212 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
213 213 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
214 214
215 215 /* Use byte values for the following shift parameters
216 216 * Usage:
217 217 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
218 218 * E1000_PSRCTL_BSIZE0_MASK) |
219 219 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
220 220 * E1000_PSRCTL_BSIZE1_MASK) |
221 221 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
222 222 * E1000_PSRCTL_BSIZE2_MASK) |
223 223 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
224 224 * E1000_PSRCTL_BSIZE3_MASK))
225 225 * where value0 = [128..16256], default=256
226 226 * value1 = [1024..64512], default=4096
227 227 * value2 = [0..64512], default=4096
228 228 * value3 = [0..64512], default=0
229 229 */
230 230
231 231 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
232 232 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
233 233 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
234 234 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
235 235
236 236 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
237 237 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
238 238 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
239 239 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
240 240
241 241 /* SWFW_SYNC Definitions */
242 242 #define E1000_SWFW_EEP_SM 0x01
243 243 #define E1000_SWFW_PHY0_SM 0x02
244 244 #define E1000_SWFW_PHY1_SM 0x04
245 245 #define E1000_SWFW_CSR_SM 0x08
246 246 #define E1000_SWFW_PHY2_SM 0x20
247 247 #define E1000_SWFW_PHY3_SM 0x40
248 248 #define E1000_SWFW_SW_MNG_SM 0x400
249 249
250 250 /* Device Control */
251 251 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
252 252 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
253 253 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
254 254 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
255 255 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
256 256 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
257 257 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
258 258 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
259 259 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
260 260 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
261 261 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
262 262 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
263 263 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
264 264 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
265 265 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
266 266 #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
267 267 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
268 268 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
269 269 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
270 270 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
271 271 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
272 272 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
273 273 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
274 274 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
275 275 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
276 276 #define E1000_CTRL_RST 0x04000000 /* Global reset */
277 277 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
278 278 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
279 279 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
|
↓ open down ↓ |
279 lines elided |
↑ open up ↑ |
280 280 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
281 281 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
282 282
283 283 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
284 284 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
285 285 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
286 286 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
287 287
288 288 #define E1000_CONNSW_ENRGSRC 0x4
289 289 #define E1000_CONNSW_PHYSD 0x400
290 +#define E1000_CONNSW_PHY_PDN 0x800
290 291 #define E1000_CONNSW_SERDESD 0x200
292 +#define E1000_CONNSW_AUTOSENSE_CONF 0x2
293 +#define E1000_CONNSW_AUTOSENSE_EN 0x1
291 294 #define E1000_PCS_CFG_PCS_EN 8
292 295 #define E1000_PCS_LCTL_FLV_LINK_UP 1
293 296 #define E1000_PCS_LCTL_FSV_10 0
294 297 #define E1000_PCS_LCTL_FSV_100 2
295 298 #define E1000_PCS_LCTL_FSV_1000 4
296 299 #define E1000_PCS_LCTL_FDV_FULL 8
297 300 #define E1000_PCS_LCTL_FSD 0x10
298 301 #define E1000_PCS_LCTL_FORCE_LINK 0x20
299 302 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
300 303 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
301 304 #define E1000_PCS_LCTL_AN_RESTART 0x20000
302 305 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
303 306 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
304 307
305 308 #define E1000_PCS_LSTS_LINK_OK 1
306 309 #define E1000_PCS_LSTS_SPEED_100 2
307 310 #define E1000_PCS_LSTS_SPEED_1000 4
308 311 #define E1000_PCS_LSTS_DUPLEX_FULL 8
309 312 #define E1000_PCS_LSTS_SYNK_OK 0x10
310 313 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
311 314
312 315 /* Device Status */
313 316 #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
314 317 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
315 318 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
316 319 #define E1000_STATUS_FUNC_SHIFT 2
317 320 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
|
↓ open down ↓ |
17 lines elided |
↑ open up ↑ |
318 321 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
319 322 #define E1000_STATUS_SPEED_MASK 0x000000C0
320 323 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
321 324 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
322 325 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
323 326 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */
324 327 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
325 328 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
326 329 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
327 330 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
331 +#define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */
332 +#define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */
328 333 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
329 334 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
330 335
331 336 /* Constants used to interpret the masked PCI-X bus speed. */
332 337 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
333 338 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
334 339 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
335 340
336 341 #define SPEED_10 10
337 342 #define SPEED_100 100
338 343 #define SPEED_1000 1000
344 +#define SPEED_2500 2500
339 345 #define HALF_DUPLEX 1
340 346 #define FULL_DUPLEX 2
341 347
342 348 #define PHY_FORCE_TIME 20
343 349
344 350 #define ADVERTISE_10_HALF 0x0001
345 351 #define ADVERTISE_10_FULL 0x0002
346 352 #define ADVERTISE_100_HALF 0x0004
347 353 #define ADVERTISE_100_FULL 0x0008
348 354 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
349 355 #define ADVERTISE_1000_FULL 0x0020
350 356
351 357 /* 1000/H is not supported, nor spec-compliant. */
352 358 #define E1000_ALL_SPEED_DUPLEX ( \
353 359 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
354 360 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
355 361 #define E1000_ALL_NOT_GIG ( \
356 362 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
357 363 ADVERTISE_100_FULL)
358 364 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
359 365 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
360 366 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
361 367
362 368 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
363 369
364 370 /* LED Control */
365 371 #define E1000_PHY_LED0_MODE_MASK 0x00000007
366 372 #define E1000_PHY_LED0_IVRT 0x00000008
367 373 #define E1000_PHY_LED0_MASK 0x0000001F
368 374
369 375 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
370 376 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
371 377 #define E1000_LEDCTL_LED0_IVRT 0x00000040
372 378 #define E1000_LEDCTL_LED0_BLINK 0x00000080
373 379
374 380 #define E1000_LEDCTL_MODE_LINK_UP 0x2
375 381 #define E1000_LEDCTL_MODE_LED_ON 0xE
376 382 #define E1000_LEDCTL_MODE_LED_OFF 0xF
377 383
378 384 /* Transmit Descriptor bit definitions */
379 385 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
380 386 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
381 387 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
382 388 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
383 389 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
384 390 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
385 391 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
386 392 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
387 393 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
388 394 #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
389 395 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
390 396 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
391 397 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
392 398 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
393 399 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
394 400 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
395 401 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
396 402 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
397 403 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
398 404 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
399 405 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
400 406
401 407 /* Transmit Control */
402 408 #define E1000_TCTL_EN 0x00000002 /* enable Tx */
403 409 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
404 410 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
405 411 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
406 412 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
407 413 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
408 414
409 415 /* Transmit Arbitration Count */
410 416 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
411 417
412 418 /* SerDes Control */
413 419 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
414 420 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
415 421
416 422 /* Receive Checksum Control */
417 423 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
418 424 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
419 425 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
420 426 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
421 427 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
422 428
423 429 /* Header split receive */
424 430 #define E1000_RFCTL_NFSW_DIS 0x00000040
425 431 #define E1000_RFCTL_NFSR_DIS 0x00000080
426 432 #define E1000_RFCTL_ACK_DIS 0x00001000
427 433 #define E1000_RFCTL_EXTEN 0x00008000
428 434 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
429 435 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
430 436 #define E1000_RFCTL_LEF 0x00040000
431 437
432 438 /* Collision related configuration parameters */
433 439 #define E1000_COLLISION_THRESHOLD 15
434 440 #define E1000_CT_SHIFT 4
435 441 #define E1000_COLLISION_DISTANCE 63
436 442 #define E1000_COLD_SHIFT 12
437 443
438 444 /* Default values for the transmit IPG register */
439 445 #define DEFAULT_82542_TIPG_IPGT 10
440 446 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
441 447 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
442 448
443 449 #define E1000_TIPG_IPGT_MASK 0x000003FF
444 450
445 451 #define DEFAULT_82542_TIPG_IPGR1 2
446 452 #define DEFAULT_82543_TIPG_IPGR1 8
447 453 #define E1000_TIPG_IPGR1_SHIFT 10
448 454
449 455 #define DEFAULT_82542_TIPG_IPGR2 10
450 456 #define DEFAULT_82543_TIPG_IPGR2 6
451 457 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
452 458 #define E1000_TIPG_IPGR2_SHIFT 20
453 459
454 460 /* Ethertype field values */
455 461 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
456 462
457 463 #define ETHERNET_FCS_SIZE 4
458 464 #define MAX_JUMBO_FRAME_SIZE 0x3F00
459 465
460 466 /* Extended Configuration Control and Size */
461 467 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
462 468 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
463 469 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
464 470 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
465 471 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
466 472 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
467 473 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
468 474 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
469 475 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
470 476
471 477 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
472 478 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
473 479 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
474 480 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
475 481
476 482 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
477 483
478 484 /* Low Power IDLE Control */
479 485 #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */
480 486
481 487 /* PBA constants */
482 488 #define E1000_PBA_8K 0x0008 /* 8KB */
483 489 #define E1000_PBA_10K 0x000A /* 10KB */
484 490 #define E1000_PBA_12K 0x000C /* 12KB */
485 491 #define E1000_PBA_14K 0x000E /* 14KB */
486 492 #define E1000_PBA_16K 0x0010 /* 16KB */
487 493 #define E1000_PBA_18K 0x0012
488 494 #define E1000_PBA_20K 0x0014
489 495 #define E1000_PBA_22K 0x0016
490 496 #define E1000_PBA_24K 0x0018
491 497 #define E1000_PBA_26K 0x001A
492 498 #define E1000_PBA_30K 0x001E
493 499 #define E1000_PBA_32K 0x0020
494 500 #define E1000_PBA_34K 0x0022
495 501 #define E1000_PBA_35K 0x0023
496 502 #define E1000_PBA_38K 0x0026
497 503 #define E1000_PBA_40K 0x0028
498 504 #define E1000_PBA_48K 0x0030 /* 48KB */
499 505 #define E1000_PBA_64K 0x0040 /* 64KB */
500 506
501 507 #define E1000_PBA_RXA_MASK 0xFFFF
502 508
503 509 #define E1000_PBS_16K E1000_PBA_16K
504 510
505 511 /* Uncorrectable/correctable ECC Error counts and enable bits */
506 512 #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
507 513 #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
508 514 #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
509 515 #define E1000_PBECCSTS_ECC_ENABLE 0x00010000
510 516
511 517 #define IFS_MAX 80
512 518 #define IFS_MIN 40
513 519 #define IFS_RATIO 4
514 520 #define IFS_STEP 10
515 521 #define MIN_NUM_XMITS 1000
516 522
517 523 /* SW Semaphore Register */
518 524 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
519 525 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
520 526 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
521 527
522 528 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
523 529
524 530 /* Interrupt Cause Read */
525 531 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
526 532 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
527 533 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
528 534 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
529 535 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
530 536 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */
531 537 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
532 538 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
533 539 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
534 540 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
535 541 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
536 542 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
537 543 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
538 544 #define E1000_ICR_TXD_LOW 0x00008000
539 545 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
540 546 #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
541 547 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
542 548 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
543 549 /* If this bit asserted, the driver should claim the interrupt */
544 550 #define E1000_ICR_INT_ASSERTED 0x80000000
545 551 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
546 552 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
547 553 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
548 554 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
549 555 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
550 556 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
551 557 #define E1000_ICR_FER 0x00400000 /* Fatal Error */
552 558
553 559 #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/
554 560 #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */
555 561
556 562 #define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */
557 563 #define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */
558 564
559 565 /* PBA ECC Register */
560 566 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
561 567 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
562 568 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
563 569 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
564 570 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
565 571
566 572 /* Extended Interrupt Cause Read */
567 573 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
568 574 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
569 575 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
570 576 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
571 577 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
572 578 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
573 579 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
574 580 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
575 581 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
576 582 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
577 583 /* TCP Timer */
578 584 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
579 585 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
580 586 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
581 587 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
582 588
583 589 /* This defines the bits that are set in the Interrupt Mask
584 590 * Set/Read Register. Each bit is documented below:
585 591 * o RXT0 = Receiver Timer Interrupt (ring 0)
586 592 * o TXDW = Transmit Descriptor Written Back
587 593 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
588 594 * o RXSEQ = Receive Sequence Error
589 595 * o LSC = Link Status Change
590 596 */
591 597 #define IMS_ENABLE_MASK ( \
592 598 E1000_IMS_RXT0 | \
593 599 E1000_IMS_TXDW | \
594 600 E1000_IMS_RXDMT0 | \
595 601 E1000_IMS_RXSEQ | \
596 602 E1000_IMS_LSC)
597 603
598 604 /* Interrupt Mask Set */
599 605 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
600 606 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
601 607 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
602 608 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
603 609 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
604 610 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
605 611 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
606 612 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
607 613 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
608 614 #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */
609 615 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */
610 616 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
611 617 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
612 618 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
613 619 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
614 620 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
615 621 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
616 622 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
617 623 #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */
618 624
619 625 #define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
620 626 #define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */
621 627 /* Extended Interrupt Mask Set */
622 628 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
623 629 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
624 630 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
625 631 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
626 632 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
627 633 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
628 634 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
629 635 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
630 636 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
631 637 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
632 638
633 639 /* Interrupt Cause Set */
634 640 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
635 641 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
636 642 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
637 643
638 644 /* Extended Interrupt Cause Set */
639 645 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
640 646 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
641 647 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
642 648 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
|
↓ open down ↓ |
294 lines elided |
↑ open up ↑ |
643 649 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
644 650 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
645 651 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
646 652 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
647 653 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
648 654 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
649 655
650 656 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF
651 657 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
652 658 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
659 +#define E1000_EITR_INTERVAL 0x00007FFC
653 660
654 661 /* Transmit Descriptor Control */
655 662 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
656 663 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
657 664 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
658 665 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
659 666 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
660 667 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
661 668 /* Enable the counting of descriptors still to be processed. */
662 669 #define E1000_TXDCTL_COUNT_DESC 0x00400000
663 670
664 671 /* Flow Control Constants */
665 672 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
666 673 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
667 674 #define FLOW_CONTROL_TYPE 0x8808
668 675
669 676 /* 802.1q VLAN Packet Size */
670 677 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
671 678 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
672 679
673 680 /* Receive Address
674 681 * Number of high/low register pairs in the RAR. The RAR (Receive Address
675 682 * Registers) holds the directed and multicast addresses that we monitor.
676 683 * Technically, we have 16 spots. However, we reserve one of these spots
677 684 * (RAR[15]) for our directed address used by controllers with
678 685 * manageability enabled, allowing us room for 15 multicast addresses.
679 686 */
680 687 #define E1000_RAR_ENTRIES 15
681 688 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
682 689 #define E1000_RAL_MAC_ADDR_LEN 4
683 690 #define E1000_RAH_MAC_ADDR_LEN 2
684 691 #define E1000_RAH_QUEUE_MASK_82575 0x000C0000
685 692 #define E1000_RAH_POOL_1 0x00040000
686 693
687 694 /* Error Codes */
688 695 #define E1000_SUCCESS 0
689 696 #define E1000_ERR_NVM 1
690 697 #define E1000_ERR_PHY 2
691 698 #define E1000_ERR_CONFIG 3
692 699 #define E1000_ERR_PARAM 4
693 700 #define E1000_ERR_MAC_INIT 5
694 701 #define E1000_ERR_PHY_TYPE 6
695 702 #define E1000_ERR_RESET 9
696 703 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
697 704 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
698 705 #define E1000_BLK_PHY_RESET 12
699 706 #define E1000_ERR_SWFW_SYNC 13
700 707 #define E1000_NOT_IMPLEMENTED 14
701 708 #define E1000_ERR_MBX 15
702 709 #define E1000_ERR_INVALID_ARGUMENT 16
703 710 #define E1000_ERR_NO_SPACE 17
704 711 #define E1000_ERR_NVM_PBA_SECTION 18
705 712 #define E1000_ERR_I2C 19
706 713 #define E1000_ERR_INVM_VALUE_NOT_FOUND 20
707 714
708 715 /* Loop limit on how long we wait for auto-negotiation to complete */
709 716 #define FIBER_LINK_UP_LIMIT 50
710 717 #define COPPER_LINK_UP_LIMIT 10
711 718 #define PHY_AUTO_NEG_LIMIT 45
712 719 #define PHY_FORCE_LIMIT 20
713 720 /* Number of 100 microseconds we wait for PCI Express master disable */
714 721 #define MASTER_DISABLE_TIMEOUT 800
715 722 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
716 723 #define PHY_CFG_TIMEOUT 100
717 724 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
718 725 #define MDIO_OWNERSHIP_TIMEOUT 10
719 726 /* Number of milliseconds for NVM auto read done after MAC reset. */
720 727 #define AUTO_READ_DONE_TIMEOUT 10
721 728
722 729 /* Flow Control */
723 730 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
724 731 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
725 732 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
726 733
727 734 /* Transmit Configuration Word */
728 735 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
729 736 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
730 737 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
731 738 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
732 739 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
733 740
734 741 /* Receive Configuration Word */
735 742 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
736 743 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
737 744 #define E1000_RXCW_C 0x20000000 /* Receive config */
738 745 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
739 746
740 747 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
741 748 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
742 749
743 750 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
744 751 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
745 752 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
746 753 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
747 754 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
748 755 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08
749 756 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
750 757 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
751 758 #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
752 759
753 760 #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
754 761 #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
755 762
756 763 #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
757 764 #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
758 765
759 766 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
760 767 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
761 768 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
762 769 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
763 770 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
764 771 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
765 772
766 773 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
767 774 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
768 775 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
769 776 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
770 777 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
771 778 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
772 779 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
773 780 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
774 781 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
775 782 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
776 783 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
777 784
778 785 #define E1000_TIMINCA_16NS_SHIFT 24
779 786 #define E1000_TIMINCA_INCPERIOD_SHIFT 24
780 787 #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
781 788
782 789 #define E1000_TSICR_TXTS 0x00000002
783 790 #define E1000_TSIM_TXTS 0x00000002
784 791 /* TUPLE Filtering Configuration */
785 792 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
786 793 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
787 794 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
788 795 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
789 796 #define E1000_TTQF_PROTOCOL_TCP 0x0
790 797 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
791 798 #define E1000_TTQF_PROTOCOL_UDP 0x1
792 799 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
793 800 #define E1000_TTQF_PROTOCOL_SCTP 0x2
794 801 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
795 802 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
796 803 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
797 804 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
798 805 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
799 806 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
800 807 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
801 808 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
802 809
803 810 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
804 811 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
805 812 #define E1000_MDICNFG_PHY_MASK 0x03E00000
806 813 #define E1000_MDICNFG_PHY_SHIFT 21
807 814
808 815 #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
809 816 #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
810 817 #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
811 818 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
812 819 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */
813 820
|
↓ open down ↓ |
151 lines elided |
↑ open up ↑ |
814 821 /* I350 EEE defines */
815 822 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
816 823 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
817 824 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
818 825 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
819 826 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
820 827 /* EEE status */
821 828 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
822 829 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
823 830 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
831 +#define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
832 +#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
833 +#define E1000_M88E1543_EEE_CTRL_1 0x0
834 +#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
835 +#define E1000_EEE_ADV_DEV_I354 7
836 +#define E1000_EEE_ADV_ADDR_I354 60
837 +#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
838 +#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
839 +#define E1000_PCS_STATUS_DEV_I354 3
840 +#define E1000_PCS_STATUS_ADDR_I354 1
841 +#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
842 +#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
843 +
824 844 #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
825 845 /* PCI Express Control */
826 846 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
827 847 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
828 848 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
829 849 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
830 850 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
831 851 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
832 852 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
833 853 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
834 854 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
835 855 #define E1000_GCR_CAP_VER2 0x00040000
836 856
857 +
837 858 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
838 859 E1000_GCR_RXDSCW_NO_SNOOP | \
839 860 E1000_GCR_RXDSCR_NO_SNOOP | \
840 861 E1000_GCR_TXD_NO_SNOOP | \
841 862 E1000_GCR_TXDSCW_NO_SNOOP | \
842 863 E1000_GCR_TXDSCR_NO_SNOOP)
843 864
865 +#define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
866 +
844 867 /* mPHY address control and data registers */
845 868 #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */
846 869 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
847 870 #define E1000_MPHY_DATA 0x0E10 /* Data Register */
848 871
849 872 /* AFE CSR Offset for PCS CLK */
850 873 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004
851 874 /* Override for near end digital loopback. */
852 875 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
853 876
854 877 /* PHY Control Register */
855 878 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
856 879 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
857 880 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
858 881 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
859 882 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
860 883 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
861 884 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
862 885 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
863 886 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
864 887 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
865 888 #define MII_CR_SPEED_1000 0x0040
866 889 #define MII_CR_SPEED_100 0x2000
867 890 #define MII_CR_SPEED_10 0x0000
868 891
869 892 /* PHY Status Register */
870 893 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
871 894 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
872 895 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
873 896 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
874 897 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
875 898 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
876 899 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
877 900 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
878 901 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
879 902 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
880 903 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
881 904 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
882 905 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
883 906 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
884 907 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
885 908
886 909 /* Autoneg Advertisement Register */
887 910 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
888 911 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
889 912 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
890 913 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
891 914 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
892 915 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
893 916 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
894 917 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
895 918 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
896 919 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
897 920
898 921 /* Link Partner Ability Register (Base Page) */
899 922 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
900 923 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
901 924 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
902 925 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
903 926 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
904 927 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
905 928 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
906 929 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
907 930 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */
908 931 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
909 932 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
910 933
911 934 /* Autoneg Expansion Register */
912 935 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
913 936 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
914 937 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
915 938 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
916 939 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
917 940
918 941 /* 1000BASE-T Control Register */
919 942 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
920 943 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
921 944 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
922 945 /* 1=Repeater/switch device port 0=DTE device */
923 946 #define CR_1000T_REPEATER_DTE 0x0400
924 947 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
925 948 #define CR_1000T_MS_VALUE 0x0800
926 949 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
927 950 #define CR_1000T_MS_ENABLE 0x1000
928 951 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
929 952 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
930 953 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
931 954 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
932 955 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
933 956
934 957 /* 1000BASE-T Status Register */
935 958 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */
936 959 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
937 960 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
938 961 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
939 962 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
940 963 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
941 964 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
942 965 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
943 966
944 967 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
945 968
946 969 /* PHY 1000 MII Register/Bit Definitions */
947 970 /* PHY Registers defined by IEEE */
948 971 #define PHY_CONTROL 0x00 /* Control Register */
949 972 #define PHY_STATUS 0x01 /* Status Register */
950 973 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
951 974 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
952 975 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
953 976 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
954 977 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
955 978 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
956 979 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
957 980 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
958 981 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
959 982 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
960 983
961 984 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
962 985
963 986 /* NVM Control */
964 987 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
965 988 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
966 989 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
967 990 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
968 991 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
969 992 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
970 993 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
971 994 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
972 995 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
973 996 #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */
974 997 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
975 998 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
976 999 /* NVM Addressing bits based on type 0=small, 1=large */
977 1000 #define E1000_EECD_ADDR_BITS 0x00000400
978 1001 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
979 1002 #ifndef E1000_NVM_GRANT_ATTEMPTS
980 1003 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
981 1004 #endif
982 1005 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
983 1006 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
984 1007 #define E1000_EECD_SIZE_EX_SHIFT 11
985 1008 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
986 1009 #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
987 1010 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
988 1011 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
989 1012 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
990 1013 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */
991 1014 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
992 1015 #define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */
993 1016 #define E1000_FLUDONE_ATTEMPTS 20000
994 1017 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
995 1018 #define E1000_I210_FIFO_SEL_RX 0x00
996 1019 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
997 1020 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
998 1021 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
999 1022 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
1000 1023
1001 1024 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */
1002 1025 /* Secure FLASH mode requires removing MSb */
1003 1026 #define E1000_I210_FW_PTR_MASK 0x7FFF
1004 1027 /* Firmware code revision field word offset*/
1005 1028 #define E1000_I210_FW_VER_OFFSET 328
1006 1029
1007 1030 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
1008 1031 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1009 1032 #define E1000_NVM_RW_REG_START 1 /* Start operation */
1010 1033 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1011 1034 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1012 1035 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1013 1036 #define E1000_FLASH_UPDATES 2000
1014 1037
1015 1038 /* NVM Word Offsets */
1016 1039 #define NVM_COMPAT 0x0003
1017 1040 #define NVM_ID_LED_SETTINGS 0x0004
1018 1041 #define NVM_VERSION 0x0005
1019 1042 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1020 1043 #define NVM_PHY_CLASS_WORD 0x0007
1021 1044 #define E1000_I210_NVM_FW_MODULE_PTR 0x0010
1022 1045 #define E1000_I350_NVM_FW_MODULE_PTR 0x0051
1023 1046 #define NVM_FUTURE_INIT_WORD1 0x0019
1024 1047 #define NVM_MAC_ADDR 0x0000
1025 1048 #define NVM_SUB_DEV_ID 0x000B
1026 1049 #define NVM_SUB_VEN_ID 0x000C
1027 1050 #define NVM_DEV_ID 0x000D
1028 1051 #define NVM_VEN_ID 0x000E
1029 1052 #define NVM_INIT_CTRL_2 0x000F
1030 1053 #define NVM_INIT_CTRL_4 0x0013
1031 1054 #define NVM_LED_1_CFG 0x001C
1032 1055 #define NVM_LED_0_2_CFG 0x001F
1033 1056
1034 1057 #define NVM_COMPAT_VALID_CSUM 0x0001
1035 1058 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
1036 1059
1037 1060 #define NVM_INIT_CONTROL2_REG 0x000F
1038 1061 #define NVM_INIT_CONTROL3_PORT_B 0x0014
1039 1062 #define NVM_INIT_3GIO_3 0x001A
1040 1063 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1041 1064 #define NVM_INIT_CONTROL3_PORT_A 0x0024
1042 1065 #define NVM_CFG 0x0012
1043 1066 #define NVM_ALT_MAC_ADDR_PTR 0x0037
1044 1067 #define NVM_CHECKSUM_REG 0x003F
1045 1068 #define NVM_COMPATIBILITY_REG_3 0x0003
1046 1069 #define NVM_COMPATIBILITY_BIT_MASK 0x8000
1047 1070
1048 1071 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1049 1072 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
1050 1073 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
1051 1074 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
1052 1075
1053 1076 #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0)
1054 1077
1055 1078 /* Mask bits for fields in Word 0x24 of the NVM */
1056 1079 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
1057 1080 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */
1058 1081 /* Offset of Link Mode bits for 82575/82576 */
1059 1082 #define NVM_WORD24_LNK_MODE_OFFSET 8
1060 1083 /* Offset of Link Mode bits for 82580 up */
1061 1084 #define NVM_WORD24_82580_LNK_MODE_OFFSET 4
1062 1085
1063 1086
1064 1087 /* Mask bits for fields in Word 0x0f of the NVM */
1065 1088 #define NVM_WORD0F_PAUSE_MASK 0x3000
1066 1089 #define NVM_WORD0F_PAUSE 0x1000
1067 1090 #define NVM_WORD0F_ASM_DIR 0x2000
1068 1091 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1069 1092
1070 1093 /* Mask bits for fields in Word 0x1a of the NVM */
1071 1094 #define NVM_WORD1A_ASPM_MASK 0x000C
1072 1095
1073 1096 /* Mask bits for fields in Word 0x03 of the EEPROM */
1074 1097 #define NVM_COMPAT_LOM 0x0800
1075 1098
1076 1099 /* length of string needed to store PBA number */
1077 1100 #define E1000_PBANUM_LENGTH 11
1078 1101
1079 1102 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1080 1103 #define NVM_SUM 0xBABA
1081 1104
1082 1105 /* OEM NVM Offsets */
1083 1106 #define NVM_OEM_OFFSET_0 6
1084 1107 #define NVM_OEM_OFFSET_1 7
1085 1108
1086 1109 /* PBA (printed board assembly) number words */
1087 1110 #define NVM_PBA_OFFSET_0 8
1088 1111 #define NVM_PBA_OFFSET_1 9
1089 1112 #define NVM_PBA_PTR_GUARD 0xFAFA
1090 1113 #define NVM_RESERVED_WORD 0xFFFF
1091 1114 #define NVM_PHY_CLASS_A 0x8000
1092 1115 #define NVM_SERDES_AMPLITUDE_MASK 0x000F
1093 1116 #define NVM_SIZE_MASK 0x1C00
1094 1117 #define NVM_SIZE_SHIFT 10
1095 1118 #define NVM_WORD_SIZE_BASE_SHIFT 6
1096 1119 #define NVM_SWDPIO_EXT_SHIFT 4
1097 1120
1098 1121 /* NVM Commands - Microwire */
1099 1122 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
1100 1123 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
1101 1124 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
1102 1125 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1103 1126 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
1104 1127
1105 1128 /* NVM Commands - SPI */
1106 1129 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1107 1130 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1108 1131 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1109 1132 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1110 1133 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1111 1134 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1112 1135
1113 1136 /* SPI NVM Status Register */
1114 1137 #define NVM_STATUS_RDY_SPI 0x01
1115 1138
1116 1139 /* Word definitions for ID LED Settings */
1117 1140 #define ID_LED_RESERVED_0000 0x0000
1118 1141 #define ID_LED_RESERVED_FFFF 0xFFFF
1119 1142 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1120 1143 (ID_LED_OFF1_OFF2 << 8) | \
1121 1144 (ID_LED_DEF1_DEF2 << 4) | \
1122 1145 (ID_LED_DEF1_DEF2))
1123 1146 #define ID_LED_DEF1_DEF2 0x1
1124 1147 #define ID_LED_DEF1_ON2 0x2
1125 1148 #define ID_LED_DEF1_OFF2 0x3
1126 1149 #define ID_LED_ON1_DEF2 0x4
1127 1150 #define ID_LED_ON1_ON2 0x5
1128 1151 #define ID_LED_ON1_OFF2 0x6
1129 1152 #define ID_LED_OFF1_DEF2 0x7
1130 1153 #define ID_LED_OFF1_ON2 0x8
1131 1154 #define ID_LED_OFF1_OFF2 0x9
1132 1155
1133 1156 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1134 1157 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1135 1158 #define IGP_LED3_MODE 0x07000000
1136 1159
1137 1160 /* PCI/PCI-X/PCI-EX Config space */
1138 1161 #define PCIX_COMMAND_REGISTER 0xE6
1139 1162 #define PCIX_STATUS_REGISTER_LO 0xE8
1140 1163 #define PCIX_STATUS_REGISTER_HI 0xEA
1141 1164 #define PCI_HEADER_TYPE_REGISTER 0x0E
1142 1165 #define PCIE_LINK_STATUS 0x12
1143 1166 #define PCIE_DEVICE_CONTROL2 0x28
1144 1167
1145 1168 #define PCIX_COMMAND_MMRBC_MASK 0x000C
1146 1169 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
1147 1170 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1148 1171 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1149 1172 #define PCIX_STATUS_HI_MMRBC_4K 0x3
1150 1173 #define PCIX_STATUS_HI_MMRBC_2K 0x2
1151 1174 #define PCIX_STATUS_LO_FUNC_MASK 0x7
1152 1175 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
1153 1176 #define PCIE_LINK_WIDTH_MASK 0x3F0
1154 1177 #define PCIE_LINK_WIDTH_SHIFT 4
1155 1178 #define PCIE_LINK_SPEED_MASK 0x0F
1156 1179 #define PCIE_LINK_SPEED_2500 0x01
1157 1180 #define PCIE_LINK_SPEED_5000 0x02
1158 1181 #define PCIE_DEVICE_CONTROL2_16ms 0x0005
1159 1182
1160 1183 #ifndef ETH_ADDR_LEN
1161 1184 #define ETH_ADDR_LEN 6
1162 1185 #endif
1163 1186
1164 1187 #define PHY_REVISION_MASK 0xFFFFFFF0
1165 1188 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1166 1189 #define MAX_PHY_MULTI_PAGE_REG 0xF
|
↓ open down ↓ |
313 lines elided |
↑ open up ↑ |
1167 1190
1168 1191 /* Bit definitions for valid PHY IDs.
1169 1192 * I = Integrated
1170 1193 * E = External
1171 1194 */
1172 1195 #define M88E1000_E_PHY_ID 0x01410C50
1173 1196 #define M88E1000_I_PHY_ID 0x01410C30
1174 1197 #define M88E1011_I_PHY_ID 0x01410C20
1175 1198 #define IGP01E1000_I_PHY_ID 0x02A80380
1176 1199 #define M88E1111_I_PHY_ID 0x01410CC0
1200 +#define M88E1543_E_PHY_ID 0x01410EA0
1201 +#define M88E1512_E_PHY_ID 0x01410DD0
1177 1202 #define M88E1112_E_PHY_ID 0x01410C90
1178 1203 #define I347AT4_E_PHY_ID 0x01410DC0
1179 1204 #define M88E1340M_E_PHY_ID 0x01410DF0
1180 1205 #define GG82563_E_PHY_ID 0x01410CA0
1181 1206 #define IGP03E1000_E_PHY_ID 0x02A80390
1182 1207 #define IFE_E_PHY_ID 0x02A80330
1183 1208 #define IFE_PLUS_E_PHY_ID 0x02A80320
1184 1209 #define IFE_C_E_PHY_ID 0x02A80310
1185 1210 #define BME1000_E_PHY_ID 0x01410CB0
1186 1211 #define BME1000_E_PHY_ID_R2 0x01410CB1
1187 1212 #define I82577_E_PHY_ID 0x01540050
1188 1213 #define I82578_E_PHY_ID 0x004DD040
1189 1214 #define I82579_E_PHY_ID 0x01540090
1190 1215 #define I217_E_PHY_ID 0x015400A0
1191 1216 #define I82580_I_PHY_ID 0x015403A0
1192 1217 #define I350_I_PHY_ID 0x015403B0
1193 1218 #define I210_I_PHY_ID 0x01410C00
1194 1219 #define IGP04E1000_E_PHY_ID 0x02A80391
1195 1220 #define M88_VENDOR 0x0141
1196 1221
1197 1222 /* M88E1000 Specific Registers */
1198 1223 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
1199 1224 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */
1200 1225 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */
1201 1226 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1202 1227
1203 1228 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1204 1229 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */
1205 1230 #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */
1206 1231 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1207 1232 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1208 1233
1209 1234 /* M88E1000 PHY Specific Control Register */
1210 1235 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1211 1236 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */
1212 1237 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1213 1238 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1214 1239 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1215 1240 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
1216 1241 /* Auto crossover enabled all speeds */
1217 1242 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
1218 1243 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1219 1244
1220 1245 /* M88E1000 PHY Specific Status Register */
1221 1246 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1222 1247 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1223 1248 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1224 1249 /* 0 = <50M
1225 1250 * 1 = 50-80M
1226 1251 * 2 = 80-110M
1227 1252 * 3 = 110-140M
1228 1253 * 4 = >140M
1229 1254 */
1230 1255 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
1231 1256 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1232 1257 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1233 1258 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1234 1259 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1235 1260 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1236 1261 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1237 1262
1238 1263 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1239 1264
1240 1265 /* Number of times we will attempt to autonegotiate before downshifting if we
1241 1266 * are the master
1242 1267 */
1243 1268 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1244 1269 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1245 1270 /* Number of times we will attempt to autonegotiate before downshifting if we
1246 1271 * are the slave
1247 1272 */
1248 1273 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1249 1274 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1250 1275 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1251 1276
1252 1277 /* Intel I347AT4 Registers */
1253 1278 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
1254 1279 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1255 1280 #define I347AT4_PAGE_SELECT 0x16
1256 1281
1257 1282 /* I347AT4 Extended PHY Specific Control Register */
1258 1283
1259 1284 /* Number of times we will attempt to autonegotiate before downshifting if we
1260 1285 * are the master
1261 1286 */
1262 1287 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
1263 1288 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
1264 1289 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
1265 1290 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
1266 1291 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
1267 1292 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
1268 1293 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
1269 1294 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
1270 1295 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
1271 1296 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
1272 1297
1273 1298 /* I347AT4 PHY Cable Diagnostics Control */
1274 1299 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1275 1300
1276 1301 /* M88E1112 only registers */
1277 1302 #define M88E1112_VCT_DSP_DISTANCE 0x001A
1278 1303
1279 1304 /* M88EC018 Rev 2 specific DownShift settings */
1280 1305 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1281 1306 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1282 1307
1283 1308 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
1284 1309 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
1285 1310
1286 1311 /* BME1000 PHY Specific Control Register */
1287 1312 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
1288 1313
1289 1314 /* Bits...
1290 1315 * 15-5: page
1291 1316 * 4-0: register offset
1292 1317 */
1293 1318 #define GG82563_PAGE_SHIFT 5
1294 1319 #define GG82563_REG(page, reg) \
1295 1320 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1296 1321 #define GG82563_MIN_ALT_REG 30
1297 1322
1298 1323 /* GG82563 Specific Registers */
1299 1324 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1300 1325 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1301 1326 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1302 1327 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1303 1328
1304 1329 /* MAC Specific Control Register */
1305 1330 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1306 1331
1307 1332 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
1308 1333
1309 1334 /* Page 193 - Port Control Registers */
1310 1335 /* Kumeran Mode Control */
1311 1336 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
1312 1337 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
1313 1338
1314 1339 /* Page 194 - KMRN Registers */
1315 1340 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */
1316 1341
1317 1342 /* MDI Control */
1318 1343 #define E1000_MDIC_REG_MASK 0x001F0000
1319 1344 #define E1000_MDIC_REG_SHIFT 16
1320 1345 #define E1000_MDIC_PHY_MASK 0x03E00000
1321 1346 #define E1000_MDIC_PHY_SHIFT 21
1322 1347 #define E1000_MDIC_OP_WRITE 0x04000000
1323 1348 #define E1000_MDIC_OP_READ 0x08000000
1324 1349 #define E1000_MDIC_READY 0x10000000
1325 1350 #define E1000_MDIC_ERROR 0x40000000
1326 1351 #define E1000_MDIC_DEST 0x80000000
1327 1352
1328 1353 /* SerDes Control */
1329 1354 #define E1000_GEN_CTL_READY 0x80000000
1330 1355 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1331 1356 #define E1000_GEN_POLL_TIMEOUT 640
1332 1357
1333 1358 /* LinkSec register fields */
1334 1359 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1335 1360 #define E1000_LSECTXCAP_SUM_SHIFT 16
1336 1361 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1337 1362 #define E1000_LSECRXCAP_SUM_SHIFT 16
1338 1363
1339 1364 #define E1000_LSECTXCTRL_EN_MASK 0x00000003
1340 1365 #define E1000_LSECTXCTRL_DISABLE 0x0
1341 1366 #define E1000_LSECTXCTRL_AUTH 0x1
1342 1367 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1343 1368 #define E1000_LSECTXCTRL_AISCI 0x00000020
1344 1369 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1345 1370 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1346 1371
1347 1372 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1348 1373 #define E1000_LSECRXCTRL_EN_SHIFT 2
1349 1374 #define E1000_LSECRXCTRL_DISABLE 0x0
1350 1375 #define E1000_LSECRXCTRL_CHECK 0x1
1351 1376 #define E1000_LSECRXCTRL_STRICT 0x2
1352 1377 #define E1000_LSECRXCTRL_DROP 0x3
1353 1378 #define E1000_LSECRXCTRL_PLSH 0x00000040
1354 1379 #define E1000_LSECRXCTRL_RP 0x00000080
1355 1380 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1356 1381
1357 1382 /* Tx Rate-Scheduler Config fields */
1358 1383 #define E1000_RTTBCNRC_RS_ENA 0x80000000
1359 1384 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1360 1385 #define E1000_RTTBCNRC_RF_INT_SHIFT 14
1361 1386 #define E1000_RTTBCNRC_RF_INT_MASK \
1362 1387 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1363 1388
1364 1389 /* DMA Coalescing register fields */
1365 1390 /* DMA Coalescing Watchdog Timer */
1366 1391 #define E1000_DMACR_DMACWT_MASK 0x00003FFF
1367 1392 /* DMA Coalescing Rx Threshold */
1368 1393 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000
1369 1394 #define E1000_DMACR_DMACTHR_SHIFT 16
1370 1395 /* Lx when no PCIe transactions */
1371 1396 #define E1000_DMACR_DMAC_LX_MASK 0x30000000
1372 1397 #define E1000_DMACR_DMAC_LX_SHIFT 28
1373 1398 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1374 1399 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1375 1400 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
1376 1401
1377 1402 /* DMA Coalescing Transmit Threshold */
1378 1403 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
1379 1404
1380 1405 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
1381 1406
1382 1407 /* Rx Traffic Rate Threshold */
1383 1408 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
1384 1409 /* Rx packet rate in current window */
1385 1410 #define E1000_DMCRTRH_LRPRCW 0x80000000
1386 1411
1387 1412 /* DMA Coal Rx Traffic Current Count */
1388 1413 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
1389 1414
1390 1415 /* Flow ctrl Rx Threshold High val */
1391 1416 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
1392 1417 #define E1000_FCRTC_RTH_COAL_SHIFT 4
1393 1418 /* Lx power decision based on DMA coal */
1394 1419 #define E1000_PCIEMISC_LX_DECISION 0x00000080
1395 1420
1396 1421 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1397 1422 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1398 1423 #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
1399 1424 #define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */
1400 1425 #define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */
1401 1426
1402 1427 /* Proxy Filter Control */
1403 1428 #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1404 1429 #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */
1405 1430 #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */
1406 1431 #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1407 1432 #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */
1408 1433 #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1409 1434 #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
1410 1435 #define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */
1411 1436 #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */
1412 1437 /* Proxy Status */
1413 1438 #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
1414 1439
1415 1440 /* Firmware Status */
1416 1441 #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */
1417 1442 /* VF Control */
1418 1443 #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */
1419 1444
1420 1445 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */
1421 1446 /* Lan ID bit field offset in status register */
1422 1447 #define E1000_STATUS_LAN_ID_OFFSET 2
1423 1448 #define E1000_VFTA_ENTRIES 128
1424 1449 #endif /* _E1000_DEFINES_H_ */
|
↓ open down ↓ |
238 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX