4431 igb support for I354
4616 igb has uninitialized kstats

@@ -285,11 +285,14 @@
 #define E1000_CTRL_MDC_DIR              E1000_CTRL_SWDPIO3
 #define E1000_CTRL_MDC                  E1000_CTRL_SWDPIN3
 
 #define E1000_CONNSW_ENRGSRC            0x4
 #define E1000_CONNSW_PHYSD              0x400
+#define E1000_CONNSW_PHY_PDN            0x800
 #define E1000_CONNSW_SERDESD            0x200
+#define E1000_CONNSW_AUTOSENSE_CONF     0x2
+#define E1000_CONNSW_AUTOSENSE_EN       0x1
 #define E1000_PCS_CFG_PCS_EN            8
 #define E1000_PCS_LCTL_FLV_LINK_UP      1
 #define E1000_PCS_LCTL_FSV_10           0
 #define E1000_PCS_LCTL_FSV_100          2
 #define E1000_PCS_LCTL_FSV_1000         4

@@ -323,10 +326,12 @@
 #define E1000_STATUS_LAN_INIT_DONE      0x00000200 /* Lan Init Compltn by NVM */
 #define E1000_STATUS_PHYRA              0x00000400 /* PHY Reset Asserted */
 #define E1000_STATUS_GIO_MASTER_ENABLE  0x00080000 /* Master request status */
 #define E1000_STATUS_PCI66              0x00000800 /* In 66Mhz slot */
 #define E1000_STATUS_BUS64              0x00001000 /* In 64 bit slot */
+#define E1000_STATUS_2P5_SKU            0x00001000 /* Val of 2.5GBE SKU strap */
+#define E1000_STATUS_2P5_SKU_OVER       0x00002000 /* Val of 2.5GBE SKU Over */
 #define E1000_STATUS_PCIX_MODE          0x00002000 /* PCI-X mode */
 #define E1000_STATUS_PCIX_SPEED         0x0000C000 /* PCI-X bus speed */
 
 /* Constants used to interpret the masked PCI-X bus speed. */
 #define E1000_STATUS_PCIX_SPEED_66      0x00000000 /* PCI-X bus spd 50-66MHz */

@@ -334,10 +339,11 @@
 #define E1000_STATUS_PCIX_SPEED_133     0x00008000 /* PCI-X bus spd 100-133MHz*/
 
 #define SPEED_10        10
 #define SPEED_100       100
 #define SPEED_1000      1000
+#define SPEED_2500      2500
 #define HALF_DUPLEX     1
 #define FULL_DUPLEX     2
 
 #define PHY_FORCE_TIME  20
 

@@ -648,10 +654,11 @@
 #define E1000_EICS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
 
 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF
 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
 #define E1000_EITR_CNT_IGNR     0x80000000 /* Don't reset counters on write */
+#define E1000_EITR_INTERVAL     0x00007FFC
 
 /* Transmit Descriptor Control */
 #define E1000_TXDCTL_PTHRESH    0x0000003F /* TXDCTL Prefetch Threshold */
 #define E1000_TXDCTL_HTHRESH    0x00003F00 /* TXDCTL Host Threshold */
 #define E1000_TXDCTL_WTHRESH    0x003F0000 /* TXDCTL Writeback Threshold */

@@ -819,10 +826,23 @@
 #define E1000_EEER_LPI_FC               0x00040000 /* EEER Ena on Flow Cntrl */
 /* EEE status */
 #define E1000_EEER_EEE_NEG              0x20000000 /* EEE capability nego */
 #define E1000_EEER_RX_LPI_STATUS        0x40000000 /* Rx in LPI state */
 #define E1000_EEER_TX_LPI_STATUS        0x80000000 /* Tx in LPI state */
+#define E1000_EEE_LP_ADV_ADDR_I350      0x040F     /* EEE LP Advertisement */
+#define E1000_M88E1543_PAGE_ADDR        0x16       /* Page Offset Register */
+#define E1000_M88E1543_EEE_CTRL_1       0x0
+#define E1000_M88E1543_EEE_CTRL_1_MS    0x0001     /* EEE Master/Slave */
+#define E1000_EEE_ADV_DEV_I354          7
+#define E1000_EEE_ADV_ADDR_I354         60
+#define E1000_EEE_ADV_100_SUPPORTED     (1 << 1)   /* 100BaseTx EEE Supported */
+#define E1000_EEE_ADV_1000_SUPPORTED    (1 << 2)   /* 1000BaseT EEE Supported */
+#define E1000_PCS_STATUS_DEV_I354       3
+#define E1000_PCS_STATUS_ADDR_I354      1
+#define E1000_PCS_STATUS_RX_LPI_RCVD    0x0400
+#define E1000_PCS_STATUS_TX_LPI_RCVD    0x0800
+
 #define E1000_EEE_SU_LPI_CLK_STP        0x00800000 /* EEE LPI Clock Stop */
 /* PCI Express Control */
 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
 #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004

@@ -832,17 +852,20 @@
 #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
 #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
 #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
 #define E1000_GCR_CAP_VER2              0x00040000
 
+
 #define PCIE_NO_SNOOP_ALL       (E1000_GCR_RXD_NO_SNOOP | \
                                  E1000_GCR_RXDSCW_NO_SNOOP | \
                                  E1000_GCR_RXDSCR_NO_SNOOP | \
                                  E1000_GCR_TXD_NO_SNOOP    | \
                                  E1000_GCR_TXDSCW_NO_SNOOP | \
                                  E1000_GCR_TXDSCR_NO_SNOOP)
 
+#define E1000_MMDAC_FUNC_DATA   0x4000 /* Data, no post increment */
+
 /* mPHY address control and data registers */
 #define E1000_MPHY_ADDR_CTL             0x0024 /* Address Control Reg */
 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
 #define E1000_MPHY_DATA                 0x0E10 /* Data Register */
 

@@ -1172,10 +1195,12 @@
 #define M88E1000_E_PHY_ID       0x01410C50
 #define M88E1000_I_PHY_ID       0x01410C30
 #define M88E1011_I_PHY_ID       0x01410C20
 #define IGP01E1000_I_PHY_ID     0x02A80380
 #define M88E1111_I_PHY_ID       0x01410CC0
+#define M88E1543_E_PHY_ID       0x01410EA0
+#define M88E1512_E_PHY_ID       0x01410DD0
 #define M88E1112_E_PHY_ID       0x01410C90
 #define I347AT4_E_PHY_ID        0x01410DC0
 #define M88E1340M_E_PHY_ID      0x01410DF0
 #define GG82563_E_PHY_ID        0x01410CA0
 #define IGP03E1000_E_PHY_ID     0x02A80390