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4431 igb support for I354
4616 igb has uninitialized kstats


 270 #define E1000_CTRL_ADVD3WUC     0x00100000 /* D3 WUC */
 271 #define E1000_CTRL_EN_PHY_PWR_MGMT      0x00200000 /* PHY PM enable */
 272 #define E1000_CTRL_SWDPIN3      0x00200000 /* SWDPIN 3 value */
 273 #define E1000_CTRL_SWDPIO0      0x00400000 /* SWDPIN 0 Input or output */
 274 #define E1000_CTRL_SWDPIO2      0x01000000 /* SWDPIN 2 input or output */
 275 #define E1000_CTRL_SWDPIO3      0x02000000 /* SWDPIN 3 input or output */
 276 #define E1000_CTRL_RST          0x04000000 /* Global reset */
 277 #define E1000_CTRL_RFCE         0x08000000 /* Receive Flow Control enable */
 278 #define E1000_CTRL_TFCE         0x10000000 /* Transmit flow control enable */
 279 #define E1000_CTRL_VME          0x40000000 /* IEEE VLAN mode enable */
 280 #define E1000_CTRL_PHY_RST      0x80000000 /* PHY Reset */
 281 #define E1000_CTRL_I2C_ENA      0x02000000 /* I2C enable */
 282 
 283 #define E1000_CTRL_MDIO_DIR             E1000_CTRL_SWDPIO2
 284 #define E1000_CTRL_MDIO                 E1000_CTRL_SWDPIN2
 285 #define E1000_CTRL_MDC_DIR              E1000_CTRL_SWDPIO3
 286 #define E1000_CTRL_MDC                  E1000_CTRL_SWDPIN3
 287 
 288 #define E1000_CONNSW_ENRGSRC            0x4
 289 #define E1000_CONNSW_PHYSD              0x400

 290 #define E1000_CONNSW_SERDESD            0x200


 291 #define E1000_PCS_CFG_PCS_EN            8
 292 #define E1000_PCS_LCTL_FLV_LINK_UP      1
 293 #define E1000_PCS_LCTL_FSV_10           0
 294 #define E1000_PCS_LCTL_FSV_100          2
 295 #define E1000_PCS_LCTL_FSV_1000         4
 296 #define E1000_PCS_LCTL_FDV_FULL         8
 297 #define E1000_PCS_LCTL_FSD              0x10
 298 #define E1000_PCS_LCTL_FORCE_LINK       0x20
 299 #define E1000_PCS_LCTL_FORCE_FCTRL      0x80
 300 #define E1000_PCS_LCTL_AN_ENABLE        0x10000
 301 #define E1000_PCS_LCTL_AN_RESTART       0x20000
 302 #define E1000_PCS_LCTL_AN_TIMEOUT       0x40000
 303 #define E1000_ENABLE_SERDES_LOOPBACK    0x0410
 304 
 305 #define E1000_PCS_LSTS_LINK_OK          1
 306 #define E1000_PCS_LSTS_SPEED_100        2
 307 #define E1000_PCS_LSTS_SPEED_1000       4
 308 #define E1000_PCS_LSTS_DUPLEX_FULL      8
 309 #define E1000_PCS_LSTS_SYNK_OK          0x10
 310 #define E1000_PCS_LSTS_AN_COMPLETE      0x10000
 311 
 312 /* Device Status */
 313 #define E1000_STATUS_FD                 0x00000001 /* Duplex 0=half 1=full */
 314 #define E1000_STATUS_LU                 0x00000002 /* Link up.0=no,1=link */
 315 #define E1000_STATUS_FUNC_MASK          0x0000000C /* PCI Function Mask */
 316 #define E1000_STATUS_FUNC_SHIFT         2
 317 #define E1000_STATUS_FUNC_1             0x00000004 /* Function 1 */
 318 #define E1000_STATUS_TXOFF              0x00000010 /* transmission paused */
 319 #define E1000_STATUS_SPEED_MASK 0x000000C0
 320 #define E1000_STATUS_SPEED_10           0x00000000 /* Speed 10Mb/s */
 321 #define E1000_STATUS_SPEED_100          0x00000040 /* Speed 100Mb/s */
 322 #define E1000_STATUS_SPEED_1000         0x00000080 /* Speed 1000Mb/s */
 323 #define E1000_STATUS_LAN_INIT_DONE      0x00000200 /* Lan Init Compltn by NVM */
 324 #define E1000_STATUS_PHYRA              0x00000400 /* PHY Reset Asserted */
 325 #define E1000_STATUS_GIO_MASTER_ENABLE  0x00080000 /* Master request status */
 326 #define E1000_STATUS_PCI66              0x00000800 /* In 66Mhz slot */
 327 #define E1000_STATUS_BUS64              0x00001000 /* In 64 bit slot */


 328 #define E1000_STATUS_PCIX_MODE          0x00002000 /* PCI-X mode */
 329 #define E1000_STATUS_PCIX_SPEED         0x0000C000 /* PCI-X bus speed */
 330 
 331 /* Constants used to interpret the masked PCI-X bus speed. */
 332 #define E1000_STATUS_PCIX_SPEED_66      0x00000000 /* PCI-X bus spd 50-66MHz */
 333 #define E1000_STATUS_PCIX_SPEED_100     0x00004000 /* PCI-X bus spd 66-100MHz */
 334 #define E1000_STATUS_PCIX_SPEED_133     0x00008000 /* PCI-X bus spd 100-133MHz*/
 335 
 336 #define SPEED_10        10
 337 #define SPEED_100       100
 338 #define SPEED_1000      1000

 339 #define HALF_DUPLEX     1
 340 #define FULL_DUPLEX     2
 341 
 342 #define PHY_FORCE_TIME  20
 343 
 344 #define ADVERTISE_10_HALF               0x0001
 345 #define ADVERTISE_10_FULL               0x0002
 346 #define ADVERTISE_100_HALF              0x0004
 347 #define ADVERTISE_100_FULL              0x0008
 348 #define ADVERTISE_1000_HALF             0x0010 /* Not used, just FYI */
 349 #define ADVERTISE_1000_FULL             0x0020
 350 
 351 /* 1000/H is not supported, nor spec-compliant. */
 352 #define E1000_ALL_SPEED_DUPLEX  ( \
 353         ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
 354         ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
 355 #define E1000_ALL_NOT_GIG       ( \
 356         ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
 357         ADVERTISE_100_FULL)
 358 #define E1000_ALL_100_SPEED     (ADVERTISE_100_HALF | ADVERTISE_100_FULL)


 633 /* Interrupt Cause Set */
 634 #define E1000_ICS_LSC           E1000_ICR_LSC       /* Link Status Change */
 635 #define E1000_ICS_RXSEQ         E1000_ICR_RXSEQ     /* Rx sequence error */
 636 #define E1000_ICS_RXDMT0        E1000_ICR_RXDMT0    /* Rx desc min. threshold */
 637 
 638 /* Extended Interrupt Cause Set */
 639 #define E1000_EICS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
 640 #define E1000_EICS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
 641 #define E1000_EICS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
 642 #define E1000_EICS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
 643 #define E1000_EICS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
 644 #define E1000_EICS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
 645 #define E1000_EICS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
 646 #define E1000_EICS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
 647 #define E1000_EICS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
 648 #define E1000_EICS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
 649 
 650 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF
 651 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
 652 #define E1000_EITR_CNT_IGNR     0x80000000 /* Don't reset counters on write */

 653 
 654 /* Transmit Descriptor Control */
 655 #define E1000_TXDCTL_PTHRESH    0x0000003F /* TXDCTL Prefetch Threshold */
 656 #define E1000_TXDCTL_HTHRESH    0x00003F00 /* TXDCTL Host Threshold */
 657 #define E1000_TXDCTL_WTHRESH    0x003F0000 /* TXDCTL Writeback Threshold */
 658 #define E1000_TXDCTL_GRAN       0x01000000 /* TXDCTL Granularity */
 659 #define E1000_TXDCTL_FULL_TX_DESC_WB    0x01010000 /* GRAN=1, WTHRESH=1 */
 660 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
 661 /* Enable the counting of descriptors still to be processed. */
 662 #define E1000_TXDCTL_COUNT_DESC 0x00400000
 663 
 664 /* Flow Control Constants */
 665 #define FLOW_CONTROL_ADDRESS_LOW        0x00C28001
 666 #define FLOW_CONTROL_ADDRESS_HIGH       0x00000100
 667 #define FLOW_CONTROL_TYPE               0x8808
 668 
 669 /* 802.1q VLAN Packet Size */
 670 #define VLAN_TAG_SIZE                   4    /* 802.3ac tag (not DMA'd) */
 671 #define E1000_VLAN_FILTER_TBL_SIZE      128  /* VLAN Filter Table (4096 bits) */
 672 


 804 #define E1000_MDICNFG_COM_MDIO          0x40000000 /* MDI shared w/ lan 0 */
 805 #define E1000_MDICNFG_PHY_MASK          0x03E00000
 806 #define E1000_MDICNFG_PHY_SHIFT         21
 807 
 808 #define E1000_THSTAT_LOW_EVENT          0x20000000 /* Low thermal threshold */
 809 #define E1000_THSTAT_MID_EVENT          0x00200000 /* Mid thermal threshold */
 810 #define E1000_THSTAT_HIGH_EVENT         0x00002000 /* High thermal threshold */
 811 #define E1000_THSTAT_PWR_DOWN           0x00000001 /* Power Down Event */
 812 #define E1000_THSTAT_LINK_THROTTLE      0x00000002 /* Link Spd Throttle Event */
 813 
 814 /* I350 EEE defines */
 815 #define E1000_IPCNFG_EEE_1G_AN          0x00000008 /* IPCNFG EEE Ena 1G AN */
 816 #define E1000_IPCNFG_EEE_100M_AN        0x00000004 /* IPCNFG EEE Ena 100M AN */
 817 #define E1000_EEER_TX_LPI_EN            0x00010000 /* EEER Tx LPI Enable */
 818 #define E1000_EEER_RX_LPI_EN            0x00020000 /* EEER Rx LPI Enable */
 819 #define E1000_EEER_LPI_FC               0x00040000 /* EEER Ena on Flow Cntrl */
 820 /* EEE status */
 821 #define E1000_EEER_EEE_NEG              0x20000000 /* EEE capability nego */
 822 #define E1000_EEER_RX_LPI_STATUS        0x40000000 /* Rx in LPI state */
 823 #define E1000_EEER_TX_LPI_STATUS        0x80000000 /* Tx in LPI state */













 824 #define E1000_EEE_SU_LPI_CLK_STP        0x00800000 /* EEE LPI Clock Stop */
 825 /* PCI Express Control */
 826 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
 827 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
 828 #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
 829 #define E1000_GCR_TXD_NO_SNOOP          0x00000008
 830 #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
 831 #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
 832 #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
 833 #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
 834 #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
 835 #define E1000_GCR_CAP_VER2              0x00040000
 836 

 837 #define PCIE_NO_SNOOP_ALL       (E1000_GCR_RXD_NO_SNOOP | \
 838                                  E1000_GCR_RXDSCW_NO_SNOOP | \
 839                                  E1000_GCR_RXDSCR_NO_SNOOP | \
 840                                  E1000_GCR_TXD_NO_SNOOP    | \
 841                                  E1000_GCR_TXDSCW_NO_SNOOP | \
 842                                  E1000_GCR_TXDSCR_NO_SNOOP)
 843 


 844 /* mPHY address control and data registers */
 845 #define E1000_MPHY_ADDR_CTL             0x0024 /* Address Control Reg */
 846 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
 847 #define E1000_MPHY_DATA                 0x0E10 /* Data Register */
 848 
 849 /* AFE CSR Offset for PCS CLK */
 850 #define E1000_MPHY_PCS_CLK_REG_OFFSET   0x0004
 851 /* Override for near end digital loopback. */
 852 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN       0x10
 853 
 854 /* PHY Control Register */
 855 #define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
 856 #define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
 857 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 858 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
 859 #define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
 860 #define MII_CR_POWER_DOWN       0x0800  /* Power down */
 861 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
 862 #define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
 863 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */


1157 #define PCIE_LINK_SPEED_5000            0x02
1158 #define PCIE_DEVICE_CONTROL2_16ms       0x0005
1159 
1160 #ifndef ETH_ADDR_LEN
1161 #define ETH_ADDR_LEN                    6
1162 #endif
1163 
1164 #define PHY_REVISION_MASK               0xFFFFFFF0
1165 #define MAX_PHY_REG_ADDRESS             0x1F  /* 5 bit address bus (0-0x1F) */
1166 #define MAX_PHY_MULTI_PAGE_REG          0xF
1167 
1168 /* Bit definitions for valid PHY IDs.
1169  * I = Integrated
1170  * E = External
1171  */
1172 #define M88E1000_E_PHY_ID       0x01410C50
1173 #define M88E1000_I_PHY_ID       0x01410C30
1174 #define M88E1011_I_PHY_ID       0x01410C20
1175 #define IGP01E1000_I_PHY_ID     0x02A80380
1176 #define M88E1111_I_PHY_ID       0x01410CC0


1177 #define M88E1112_E_PHY_ID       0x01410C90
1178 #define I347AT4_E_PHY_ID        0x01410DC0
1179 #define M88E1340M_E_PHY_ID      0x01410DF0
1180 #define GG82563_E_PHY_ID        0x01410CA0
1181 #define IGP03E1000_E_PHY_ID     0x02A80390
1182 #define IFE_E_PHY_ID            0x02A80330
1183 #define IFE_PLUS_E_PHY_ID       0x02A80320
1184 #define IFE_C_E_PHY_ID          0x02A80310
1185 #define BME1000_E_PHY_ID        0x01410CB0
1186 #define BME1000_E_PHY_ID_R2     0x01410CB1
1187 #define I82577_E_PHY_ID         0x01540050
1188 #define I82578_E_PHY_ID         0x004DD040
1189 #define I82579_E_PHY_ID         0x01540090
1190 #define I217_E_PHY_ID           0x015400A0
1191 #define I82580_I_PHY_ID         0x015403A0
1192 #define I350_I_PHY_ID           0x015403B0
1193 #define I210_I_PHY_ID           0x01410C00
1194 #define IGP04E1000_E_PHY_ID     0x02A80391
1195 #define M88_VENDOR              0x0141
1196 




 270 #define E1000_CTRL_ADVD3WUC     0x00100000 /* D3 WUC */
 271 #define E1000_CTRL_EN_PHY_PWR_MGMT      0x00200000 /* PHY PM enable */
 272 #define E1000_CTRL_SWDPIN3      0x00200000 /* SWDPIN 3 value */
 273 #define E1000_CTRL_SWDPIO0      0x00400000 /* SWDPIN 0 Input or output */
 274 #define E1000_CTRL_SWDPIO2      0x01000000 /* SWDPIN 2 input or output */
 275 #define E1000_CTRL_SWDPIO3      0x02000000 /* SWDPIN 3 input or output */
 276 #define E1000_CTRL_RST          0x04000000 /* Global reset */
 277 #define E1000_CTRL_RFCE         0x08000000 /* Receive Flow Control enable */
 278 #define E1000_CTRL_TFCE         0x10000000 /* Transmit flow control enable */
 279 #define E1000_CTRL_VME          0x40000000 /* IEEE VLAN mode enable */
 280 #define E1000_CTRL_PHY_RST      0x80000000 /* PHY Reset */
 281 #define E1000_CTRL_I2C_ENA      0x02000000 /* I2C enable */
 282 
 283 #define E1000_CTRL_MDIO_DIR             E1000_CTRL_SWDPIO2
 284 #define E1000_CTRL_MDIO                 E1000_CTRL_SWDPIN2
 285 #define E1000_CTRL_MDC_DIR              E1000_CTRL_SWDPIO3
 286 #define E1000_CTRL_MDC                  E1000_CTRL_SWDPIN3
 287 
 288 #define E1000_CONNSW_ENRGSRC            0x4
 289 #define E1000_CONNSW_PHYSD              0x400
 290 #define E1000_CONNSW_PHY_PDN            0x800
 291 #define E1000_CONNSW_SERDESD            0x200
 292 #define E1000_CONNSW_AUTOSENSE_CONF     0x2
 293 #define E1000_CONNSW_AUTOSENSE_EN       0x1
 294 #define E1000_PCS_CFG_PCS_EN            8
 295 #define E1000_PCS_LCTL_FLV_LINK_UP      1
 296 #define E1000_PCS_LCTL_FSV_10           0
 297 #define E1000_PCS_LCTL_FSV_100          2
 298 #define E1000_PCS_LCTL_FSV_1000         4
 299 #define E1000_PCS_LCTL_FDV_FULL         8
 300 #define E1000_PCS_LCTL_FSD              0x10
 301 #define E1000_PCS_LCTL_FORCE_LINK       0x20
 302 #define E1000_PCS_LCTL_FORCE_FCTRL      0x80
 303 #define E1000_PCS_LCTL_AN_ENABLE        0x10000
 304 #define E1000_PCS_LCTL_AN_RESTART       0x20000
 305 #define E1000_PCS_LCTL_AN_TIMEOUT       0x40000
 306 #define E1000_ENABLE_SERDES_LOOPBACK    0x0410
 307 
 308 #define E1000_PCS_LSTS_LINK_OK          1
 309 #define E1000_PCS_LSTS_SPEED_100        2
 310 #define E1000_PCS_LSTS_SPEED_1000       4
 311 #define E1000_PCS_LSTS_DUPLEX_FULL      8
 312 #define E1000_PCS_LSTS_SYNK_OK          0x10
 313 #define E1000_PCS_LSTS_AN_COMPLETE      0x10000
 314 
 315 /* Device Status */
 316 #define E1000_STATUS_FD                 0x00000001 /* Duplex 0=half 1=full */
 317 #define E1000_STATUS_LU                 0x00000002 /* Link up.0=no,1=link */
 318 #define E1000_STATUS_FUNC_MASK          0x0000000C /* PCI Function Mask */
 319 #define E1000_STATUS_FUNC_SHIFT         2
 320 #define E1000_STATUS_FUNC_1             0x00000004 /* Function 1 */
 321 #define E1000_STATUS_TXOFF              0x00000010 /* transmission paused */
 322 #define E1000_STATUS_SPEED_MASK 0x000000C0
 323 #define E1000_STATUS_SPEED_10           0x00000000 /* Speed 10Mb/s */
 324 #define E1000_STATUS_SPEED_100          0x00000040 /* Speed 100Mb/s */
 325 #define E1000_STATUS_SPEED_1000         0x00000080 /* Speed 1000Mb/s */
 326 #define E1000_STATUS_LAN_INIT_DONE      0x00000200 /* Lan Init Compltn by NVM */
 327 #define E1000_STATUS_PHYRA              0x00000400 /* PHY Reset Asserted */
 328 #define E1000_STATUS_GIO_MASTER_ENABLE  0x00080000 /* Master request status */
 329 #define E1000_STATUS_PCI66              0x00000800 /* In 66Mhz slot */
 330 #define E1000_STATUS_BUS64              0x00001000 /* In 64 bit slot */
 331 #define E1000_STATUS_2P5_SKU            0x00001000 /* Val of 2.5GBE SKU strap */
 332 #define E1000_STATUS_2P5_SKU_OVER       0x00002000 /* Val of 2.5GBE SKU Over */
 333 #define E1000_STATUS_PCIX_MODE          0x00002000 /* PCI-X mode */
 334 #define E1000_STATUS_PCIX_SPEED         0x0000C000 /* PCI-X bus speed */
 335 
 336 /* Constants used to interpret the masked PCI-X bus speed. */
 337 #define E1000_STATUS_PCIX_SPEED_66      0x00000000 /* PCI-X bus spd 50-66MHz */
 338 #define E1000_STATUS_PCIX_SPEED_100     0x00004000 /* PCI-X bus spd 66-100MHz */
 339 #define E1000_STATUS_PCIX_SPEED_133     0x00008000 /* PCI-X bus spd 100-133MHz*/
 340 
 341 #define SPEED_10        10
 342 #define SPEED_100       100
 343 #define SPEED_1000      1000
 344 #define SPEED_2500      2500
 345 #define HALF_DUPLEX     1
 346 #define FULL_DUPLEX     2
 347 
 348 #define PHY_FORCE_TIME  20
 349 
 350 #define ADVERTISE_10_HALF               0x0001
 351 #define ADVERTISE_10_FULL               0x0002
 352 #define ADVERTISE_100_HALF              0x0004
 353 #define ADVERTISE_100_FULL              0x0008
 354 #define ADVERTISE_1000_HALF             0x0010 /* Not used, just FYI */
 355 #define ADVERTISE_1000_FULL             0x0020
 356 
 357 /* 1000/H is not supported, nor spec-compliant. */
 358 #define E1000_ALL_SPEED_DUPLEX  ( \
 359         ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
 360         ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
 361 #define E1000_ALL_NOT_GIG       ( \
 362         ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
 363         ADVERTISE_100_FULL)
 364 #define E1000_ALL_100_SPEED     (ADVERTISE_100_HALF | ADVERTISE_100_FULL)


 639 /* Interrupt Cause Set */
 640 #define E1000_ICS_LSC           E1000_ICR_LSC       /* Link Status Change */
 641 #define E1000_ICS_RXSEQ         E1000_ICR_RXSEQ     /* Rx sequence error */
 642 #define E1000_ICS_RXDMT0        E1000_ICR_RXDMT0    /* Rx desc min. threshold */
 643 
 644 /* Extended Interrupt Cause Set */
 645 #define E1000_EICS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
 646 #define E1000_EICS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
 647 #define E1000_EICS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
 648 #define E1000_EICS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
 649 #define E1000_EICS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
 650 #define E1000_EICS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
 651 #define E1000_EICS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
 652 #define E1000_EICS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
 653 #define E1000_EICS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
 654 #define E1000_EICS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
 655 
 656 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF
 657 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
 658 #define E1000_EITR_CNT_IGNR     0x80000000 /* Don't reset counters on write */
 659 #define E1000_EITR_INTERVAL     0x00007FFC
 660 
 661 /* Transmit Descriptor Control */
 662 #define E1000_TXDCTL_PTHRESH    0x0000003F /* TXDCTL Prefetch Threshold */
 663 #define E1000_TXDCTL_HTHRESH    0x00003F00 /* TXDCTL Host Threshold */
 664 #define E1000_TXDCTL_WTHRESH    0x003F0000 /* TXDCTL Writeback Threshold */
 665 #define E1000_TXDCTL_GRAN       0x01000000 /* TXDCTL Granularity */
 666 #define E1000_TXDCTL_FULL_TX_DESC_WB    0x01010000 /* GRAN=1, WTHRESH=1 */
 667 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
 668 /* Enable the counting of descriptors still to be processed. */
 669 #define E1000_TXDCTL_COUNT_DESC 0x00400000
 670 
 671 /* Flow Control Constants */
 672 #define FLOW_CONTROL_ADDRESS_LOW        0x00C28001
 673 #define FLOW_CONTROL_ADDRESS_HIGH       0x00000100
 674 #define FLOW_CONTROL_TYPE               0x8808
 675 
 676 /* 802.1q VLAN Packet Size */
 677 #define VLAN_TAG_SIZE                   4    /* 802.3ac tag (not DMA'd) */
 678 #define E1000_VLAN_FILTER_TBL_SIZE      128  /* VLAN Filter Table (4096 bits) */
 679 


 811 #define E1000_MDICNFG_COM_MDIO          0x40000000 /* MDI shared w/ lan 0 */
 812 #define E1000_MDICNFG_PHY_MASK          0x03E00000
 813 #define E1000_MDICNFG_PHY_SHIFT         21
 814 
 815 #define E1000_THSTAT_LOW_EVENT          0x20000000 /* Low thermal threshold */
 816 #define E1000_THSTAT_MID_EVENT          0x00200000 /* Mid thermal threshold */
 817 #define E1000_THSTAT_HIGH_EVENT         0x00002000 /* High thermal threshold */
 818 #define E1000_THSTAT_PWR_DOWN           0x00000001 /* Power Down Event */
 819 #define E1000_THSTAT_LINK_THROTTLE      0x00000002 /* Link Spd Throttle Event */
 820 
 821 /* I350 EEE defines */
 822 #define E1000_IPCNFG_EEE_1G_AN          0x00000008 /* IPCNFG EEE Ena 1G AN */
 823 #define E1000_IPCNFG_EEE_100M_AN        0x00000004 /* IPCNFG EEE Ena 100M AN */
 824 #define E1000_EEER_TX_LPI_EN            0x00010000 /* EEER Tx LPI Enable */
 825 #define E1000_EEER_RX_LPI_EN            0x00020000 /* EEER Rx LPI Enable */
 826 #define E1000_EEER_LPI_FC               0x00040000 /* EEER Ena on Flow Cntrl */
 827 /* EEE status */
 828 #define E1000_EEER_EEE_NEG              0x20000000 /* EEE capability nego */
 829 #define E1000_EEER_RX_LPI_STATUS        0x40000000 /* Rx in LPI state */
 830 #define E1000_EEER_TX_LPI_STATUS        0x80000000 /* Tx in LPI state */
 831 #define E1000_EEE_LP_ADV_ADDR_I350      0x040F     /* EEE LP Advertisement */
 832 #define E1000_M88E1543_PAGE_ADDR        0x16       /* Page Offset Register */
 833 #define E1000_M88E1543_EEE_CTRL_1       0x0
 834 #define E1000_M88E1543_EEE_CTRL_1_MS    0x0001     /* EEE Master/Slave */
 835 #define E1000_EEE_ADV_DEV_I354          7
 836 #define E1000_EEE_ADV_ADDR_I354         60
 837 #define E1000_EEE_ADV_100_SUPPORTED     (1 << 1)   /* 100BaseTx EEE Supported */
 838 #define E1000_EEE_ADV_1000_SUPPORTED    (1 << 2)   /* 1000BaseT EEE Supported */
 839 #define E1000_PCS_STATUS_DEV_I354       3
 840 #define E1000_PCS_STATUS_ADDR_I354      1
 841 #define E1000_PCS_STATUS_RX_LPI_RCVD    0x0400
 842 #define E1000_PCS_STATUS_TX_LPI_RCVD    0x0800
 843 
 844 #define E1000_EEE_SU_LPI_CLK_STP        0x00800000 /* EEE LPI Clock Stop */
 845 /* PCI Express Control */
 846 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
 847 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
 848 #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
 849 #define E1000_GCR_TXD_NO_SNOOP          0x00000008
 850 #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
 851 #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
 852 #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
 853 #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
 854 #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
 855 #define E1000_GCR_CAP_VER2              0x00040000
 856 
 857 
 858 #define PCIE_NO_SNOOP_ALL       (E1000_GCR_RXD_NO_SNOOP | \
 859                                  E1000_GCR_RXDSCW_NO_SNOOP | \
 860                                  E1000_GCR_RXDSCR_NO_SNOOP | \
 861                                  E1000_GCR_TXD_NO_SNOOP    | \
 862                                  E1000_GCR_TXDSCW_NO_SNOOP | \
 863                                  E1000_GCR_TXDSCR_NO_SNOOP)
 864 
 865 #define E1000_MMDAC_FUNC_DATA   0x4000 /* Data, no post increment */
 866 
 867 /* mPHY address control and data registers */
 868 #define E1000_MPHY_ADDR_CTL             0x0024 /* Address Control Reg */
 869 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
 870 #define E1000_MPHY_DATA                 0x0E10 /* Data Register */
 871 
 872 /* AFE CSR Offset for PCS CLK */
 873 #define E1000_MPHY_PCS_CLK_REG_OFFSET   0x0004
 874 /* Override for near end digital loopback. */
 875 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN       0x10
 876 
 877 /* PHY Control Register */
 878 #define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
 879 #define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
 880 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 881 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
 882 #define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
 883 #define MII_CR_POWER_DOWN       0x0800  /* Power down */
 884 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
 885 #define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
 886 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */


1180 #define PCIE_LINK_SPEED_5000            0x02
1181 #define PCIE_DEVICE_CONTROL2_16ms       0x0005
1182 
1183 #ifndef ETH_ADDR_LEN
1184 #define ETH_ADDR_LEN                    6
1185 #endif
1186 
1187 #define PHY_REVISION_MASK               0xFFFFFFF0
1188 #define MAX_PHY_REG_ADDRESS             0x1F  /* 5 bit address bus (0-0x1F) */
1189 #define MAX_PHY_MULTI_PAGE_REG          0xF
1190 
1191 /* Bit definitions for valid PHY IDs.
1192  * I = Integrated
1193  * E = External
1194  */
1195 #define M88E1000_E_PHY_ID       0x01410C50
1196 #define M88E1000_I_PHY_ID       0x01410C30
1197 #define M88E1011_I_PHY_ID       0x01410C20
1198 #define IGP01E1000_I_PHY_ID     0x02A80380
1199 #define M88E1111_I_PHY_ID       0x01410CC0
1200 #define M88E1543_E_PHY_ID       0x01410EA0
1201 #define M88E1512_E_PHY_ID       0x01410DD0
1202 #define M88E1112_E_PHY_ID       0x01410C90
1203 #define I347AT4_E_PHY_ID        0x01410DC0
1204 #define M88E1340M_E_PHY_ID      0x01410DF0
1205 #define GG82563_E_PHY_ID        0x01410CA0
1206 #define IGP03E1000_E_PHY_ID     0x02A80390
1207 #define IFE_E_PHY_ID            0x02A80330
1208 #define IFE_PLUS_E_PHY_ID       0x02A80320
1209 #define IFE_C_E_PHY_ID          0x02A80310
1210 #define BME1000_E_PHY_ID        0x01410CB0
1211 #define BME1000_E_PHY_ID_R2     0x01410CB1
1212 #define I82577_E_PHY_ID         0x01540050
1213 #define I82578_E_PHY_ID         0x004DD040
1214 #define I82579_E_PHY_ID         0x01540090
1215 #define I217_E_PHY_ID           0x015400A0
1216 #define I82580_I_PHY_ID         0x015403A0
1217 #define I350_I_PHY_ID           0x015403B0
1218 #define I210_I_PHY_ID           0x01410C00
1219 #define IGP04E1000_E_PHY_ID     0x02A80391
1220 #define M88_VENDOR              0x0141
1221