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4431 igb support for I354
4616 igb has uninitialized kstats
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--- old/usr/src/uts/common/io/e1000api/e1000_82575.c
+++ new/usr/src/uts/common/io/e1000api/e1000_82575.c
1 1 /******************************************************************************
2 2
3 3 Copyright (c) 2001-2013, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD$*/
34 34
35 35 /*
36 36 * 82575EB Gigabit Network Connection
37 37 * 82575EB Gigabit Backplane Connection
38 38 * 82575GB Gigabit Network Connection
39 39 * 82576 Gigabit Network Connection
40 40 * 82576 Quad Port Gigabit Mezzanine Adapter
41 41 * 82580 Gigabit Network Connection
42 42 * I350 Gigabit Network Connection
43 43 */
44 44
45 45 #include "e1000_api.h"
46 46 #include "e1000_i210.h"
47 47
48 48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49 49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50 50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
51 51 static void e1000_release_phy_82575(struct e1000_hw *hw);
52 52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
53 53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
54 54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
55 55 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 56 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
57 57 u16 *duplex);
58 58 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
59 59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
60 60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
61 61 u16 *data);
62 62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
63 63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64 64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
65 65 u32 offset, u16 *data);
66 66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
67 67 u32 offset, u16 data);
68 68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
69 69 bool active);
70 70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
71 71 bool active);
72 72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
73 73 bool active);
74 74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75 75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76 76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77 77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78 78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79 79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
80 80 u32 offset, u16 data);
81 81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82 82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
83 83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
84 84 u16 *speed, u16 *duplex);
85 85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
86 86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
87 87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
88 88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
89 89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
90 90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
91 91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
92 92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
93 93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
94 94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
95 95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
96 96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
97 97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
98 98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
99 99 u16 offset);
100 100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
101 101 u16 offset);
102 102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
103 103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
104 104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
105 105 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
106 106
107 107 static void e1000_i2c_start(struct e1000_hw *hw);
108 108 static void e1000_i2c_stop(struct e1000_hw *hw);
109 109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
110 110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
111 111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
112 112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
113 113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
114 114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
116 116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
117 117 static bool e1000_get_i2c_data(u32 *i2cctl);
118 118
119 119 static const u16 e1000_82580_rxpbs_table[] = {
120 120 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
121 121 #define E1000_82580_RXPBS_TABLE_SIZE \
122 122 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
123 123
124 124
125 125 /**
126 126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
127 127 * @hw: pointer to the HW structure
128 128 *
129 129 * Called to determine if the I2C pins are being used for I2C or as an
130 130 * external MDIO interface since the two options are mutually exclusive.
131 131 **/
132 132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
133 133 {
134 134 u32 reg = 0;
135 135 bool ext_mdio = FALSE;
136 136
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137 137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
138 138
139 139 switch (hw->mac.type) {
140 140 case e1000_82575:
141 141 case e1000_82576:
142 142 reg = E1000_READ_REG(hw, E1000_MDIC);
143 143 ext_mdio = !!(reg & E1000_MDIC_DEST);
144 144 break;
145 145 case e1000_82580:
146 146 case e1000_i350:
147 + case e1000_i354:
147 148 case e1000_i210:
148 149 case e1000_i211:
149 150 reg = E1000_READ_REG(hw, E1000_MDICNFG);
150 151 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
151 152 break;
152 153 default:
153 154 break;
154 155 }
155 156 return ext_mdio;
156 157 }
157 158
158 159 /**
159 160 * e1000_init_phy_params_82575 - Init PHY func ptrs.
160 161 * @hw: pointer to the HW structure
161 162 **/
162 163 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
163 164 {
164 165 struct e1000_phy_info *phy = &hw->phy;
165 166 s32 ret_val = E1000_SUCCESS;
166 167 u32 ctrl_ext;
167 168
168 169 DEBUGFUNC("e1000_init_phy_params_82575");
169 170
170 171 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
171 172 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
172 173
173 174 if (hw->phy.media_type != e1000_media_type_copper) {
174 175 phy->type = e1000_phy_none;
175 176 goto out;
176 177 }
177 178
178 179 phy->ops.power_up = e1000_power_up_phy_copper;
179 180 phy->ops.power_down = e1000_power_down_phy_copper_82575;
180 181
181 182 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
182 183 phy->reset_delay_us = 100;
183 184
184 185 phy->ops.acquire = e1000_acquire_phy_82575;
185 186 phy->ops.check_reset_block = e1000_check_reset_block_generic;
186 187 phy->ops.commit = e1000_phy_sw_reset_generic;
187 188 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
188 189 phy->ops.release = e1000_release_phy_82575;
189 190
190 191 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
191 192
192 193 if (e1000_sgmii_active_82575(hw)) {
193 194 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
194 195 ctrl_ext |= E1000_CTRL_I2C_ENA;
195 196 } else {
196 197 phy->ops.reset = e1000_phy_hw_reset_generic;
197 198 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
198 199 }
199 200
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200 201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
201 202 e1000_reset_mdicnfg_82580(hw);
202 203
203 204 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
204 205 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
205 206 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
206 207 } else {
207 208 switch (hw->mac.type) {
208 209 case e1000_82580:
209 210 case e1000_i350:
211 + case e1000_i354:
210 212 phy->ops.read_reg = e1000_read_phy_reg_82580;
211 213 phy->ops.write_reg = e1000_write_phy_reg_82580;
212 214 break;
213 215 case e1000_i210:
214 216 case e1000_i211:
215 217 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
216 218 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
217 219 break;
218 220 default:
219 221 phy->ops.read_reg = e1000_read_phy_reg_igp;
220 222 phy->ops.write_reg = e1000_write_phy_reg_igp;
221 223 }
222 224 }
223 225
224 226 /* Set phy->phy_addr and phy->id. */
225 227 ret_val = e1000_get_phy_id_82575(hw);
226 228
227 229 /* Verify phy id and set remaining function pointers */
228 230 switch (phy->id) {
231 + case M88E1543_E_PHY_ID:
232 + case M88E1512_E_PHY_ID:
229 233 case I347AT4_E_PHY_ID:
230 234 case M88E1112_E_PHY_ID:
231 235 case M88E1340M_E_PHY_ID:
232 236 case M88E1111_I_PHY_ID:
233 237 phy->type = e1000_phy_m88;
234 238 phy->ops.check_polarity = e1000_check_polarity_m88;
235 239 phy->ops.get_info = e1000_get_phy_info_m88;
236 - if (phy->id == I347AT4_E_PHY_ID ||
237 - phy->id == M88E1112_E_PHY_ID ||
238 - phy->id == M88E1340M_E_PHY_ID)
240 + switch (phy->id) {
241 + case I347AT4_E_PHY_ID:
242 + case M88E1112_E_PHY_ID:
243 + case M88E1340M_E_PHY_ID:
244 + case M88E1543_E_PHY_ID:
245 + case M88E1512_E_PHY_ID:
239 246 phy->ops.get_cable_length =
240 247 e1000_get_cable_length_m88_gen2;
241 - else
248 + default:
242 249 phy->ops.get_cable_length = e1000_get_cable_length_m88;
250 + }
243 251 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
244 252 break;
245 253 case IGP03E1000_E_PHY_ID:
246 254 case IGP04E1000_E_PHY_ID:
247 255 phy->type = e1000_phy_igp_3;
248 256 phy->ops.check_polarity = e1000_check_polarity_igp;
249 257 phy->ops.get_info = e1000_get_phy_info_igp;
250 258 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
251 259 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
252 260 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
253 261 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
254 262 break;
255 263 case I82580_I_PHY_ID:
256 264 case I350_I_PHY_ID:
257 265 phy->type = e1000_phy_82580;
258 266 phy->ops.check_polarity = e1000_check_polarity_82577;
259 267 phy->ops.force_speed_duplex =
260 268 e1000_phy_force_speed_duplex_82577;
261 269 phy->ops.get_cable_length = e1000_get_cable_length_82577;
262 270 phy->ops.get_info = e1000_get_phy_info_82577;
263 271 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
264 272 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
265 273 break;
266 274 case I210_I_PHY_ID:
267 275 phy->type = e1000_phy_i210;
268 276 phy->ops.check_polarity = e1000_check_polarity_m88;
269 277 phy->ops.get_info = e1000_get_phy_info_m88;
270 278 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
271 279 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
272 280 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
273 281 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
274 282 break;
275 283 default:
276 284 ret_val = -E1000_ERR_PHY;
277 285 goto out;
278 286 }
279 287
280 288 out:
281 289 return ret_val;
282 290 }
283 291
284 292 /**
285 293 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
286 294 * @hw: pointer to the HW structure
287 295 **/
288 296 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
289 297 {
290 298 struct e1000_nvm_info *nvm = &hw->nvm;
291 299 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
292 300 u16 size;
293 301
294 302 DEBUGFUNC("e1000_init_nvm_params_82575");
295 303
296 304 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
297 305 E1000_EECD_SIZE_EX_SHIFT);
298 306 /*
299 307 * Added to a constant, "size" becomes the left-shift value
300 308 * for setting word_size.
301 309 */
302 310 size += NVM_WORD_SIZE_BASE_SHIFT;
303 311
304 312 /* Just in case size is out of range, cap it to the largest
305 313 * EEPROM size supported
306 314 */
307 315 if (size > 15)
308 316 size = 15;
309 317
310 318 nvm->word_size = 1 << size;
311 319 if (hw->mac.type < e1000_i210) {
312 320 nvm->opcode_bits = 8;
313 321 nvm->delay_usec = 1;
314 322
315 323 switch (nvm->override) {
316 324 case e1000_nvm_override_spi_large:
317 325 nvm->page_size = 32;
318 326 nvm->address_bits = 16;
319 327 break;
320 328 case e1000_nvm_override_spi_small:
321 329 nvm->page_size = 8;
322 330 nvm->address_bits = 8;
323 331 break;
324 332 default:
325 333 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
326 334 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
327 335 16 : 8;
328 336 break;
329 337 }
330 338 if (nvm->word_size == (1 << 15))
331 339 nvm->page_size = 128;
332 340
333 341 nvm->type = e1000_nvm_eeprom_spi;
334 342 } else {
335 343 nvm->type = e1000_nvm_flash_hw;
336 344 }
337 345
338 346 /* Function Pointers */
339 347 nvm->ops.acquire = e1000_acquire_nvm_82575;
340 348 nvm->ops.release = e1000_release_nvm_82575;
341 349 if (nvm->word_size < (1 << 15))
342 350 nvm->ops.read = e1000_read_nvm_eerd;
343 351 else
344 352 nvm->ops.read = e1000_read_nvm_spi;
345 353
346 354 nvm->ops.write = e1000_write_nvm_spi;
347 355 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
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348 356 nvm->ops.update = e1000_update_nvm_checksum_generic;
349 357 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
350 358
351 359 /* override generic family function pointers for specific descendants */
352 360 switch (hw->mac.type) {
353 361 case e1000_82580:
354 362 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
355 363 nvm->ops.update = e1000_update_nvm_checksum_82580;
356 364 break;
357 365 case e1000_i350:
366 + case e1000_i354:
358 367 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
359 368 nvm->ops.update = e1000_update_nvm_checksum_i350;
360 369 break;
361 370 default:
362 371 break;
363 372 }
364 373
365 374 return E1000_SUCCESS;
366 375 }
367 376
368 377 /**
369 378 * e1000_init_mac_params_82575 - Init MAC func ptrs.
370 379 * @hw: pointer to the HW structure
371 380 **/
372 381 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
373 382 {
374 383 struct e1000_mac_info *mac = &hw->mac;
375 384 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
376 385
377 386 DEBUGFUNC("e1000_init_mac_params_82575");
378 387
379 388 /* Derives media type */
380 389 e1000_get_media_type_82575(hw);
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381 390 /* Set mta register count */
382 391 mac->mta_reg_count = 128;
383 392 /* Set uta register count */
384 393 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
385 394 /* Set rar entry count */
386 395 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
387 396 if (mac->type == e1000_82576)
388 397 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
389 398 if (mac->type == e1000_82580)
390 399 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
391 - if (mac->type == e1000_i350)
400 + if (mac->type == e1000_i350 || mac->type == e1000_i354)
392 401 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
393 402
394 - /* Enable EEE default settings for EEE supported devices */
403 + /* Disable EEE default settings for EEE supported devices */
395 404 if (mac->type >= e1000_i350)
396 405 dev_spec->eee_disable = TRUE;
397 406
398 407 /* Allow a single clear of the SW semaphore on I210 and newer */
399 408 if (mac->type >= e1000_i210)
400 409 dev_spec->clear_semaphore_once = TRUE;
401 410
402 411 /* Set if part includes ASF firmware */
403 412 mac->asf_firmware_present = TRUE;
404 413 /* FWSM register */
405 414 mac->has_fwsm = TRUE;
406 415 /* ARC supported; valid only if manageability features are enabled. */
407 416 mac->arc_subsystem_valid =
408 417 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
409 418
410 419 /* Function pointers */
411 420
412 421 /* bus type/speed/width */
413 422 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
414 423 /* reset */
415 424 if (mac->type >= e1000_82580)
416 425 mac->ops.reset_hw = e1000_reset_hw_82580;
417 426 else
418 427 mac->ops.reset_hw = e1000_reset_hw_82575;
419 428 /* hw initialization */
420 429 mac->ops.init_hw = e1000_init_hw_82575;
421 430 /* link setup */
422 431 mac->ops.setup_link = e1000_setup_link_generic;
423 432 /* physical interface link setup */
424 433 mac->ops.setup_physical_interface =
425 434 (hw->phy.media_type == e1000_media_type_copper)
426 435 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
427 436 /* physical interface shutdown */
428 437 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
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429 438 /* physical interface power up */
430 439 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
431 440 /* check for link */
432 441 mac->ops.check_for_link = e1000_check_for_link_82575;
433 442 /* read mac address */
434 443 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
435 444 /* configure collision distance */
436 445 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
437 446 /* multicast address update */
438 447 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
439 - if (mac->type == e1000_i350) {
448 + if (mac->type == e1000_i350 || mac->type == e1000_i354) {
440 449 /* writing VFTA */
441 450 mac->ops.write_vfta = e1000_write_vfta_i350;
442 451 /* clearing VFTA */
443 452 mac->ops.clear_vfta = e1000_clear_vfta_i350;
444 453 } else {
445 454 /* writing VFTA */
446 455 mac->ops.write_vfta = e1000_write_vfta_generic;
447 456 /* clearing VFTA */
448 457 mac->ops.clear_vfta = e1000_clear_vfta_generic;
449 458 }
450 459 if (hw->mac.type >= e1000_82580)
451 460 mac->ops.validate_mdi_setting =
452 461 e1000_validate_mdi_setting_crossover_generic;
453 462 /* ID LED init */
454 463 mac->ops.id_led_init = e1000_id_led_init_generic;
455 464 /* blink LED */
456 465 mac->ops.blink_led = e1000_blink_led_generic;
457 466 /* setup LED */
458 467 mac->ops.setup_led = e1000_setup_led_generic;
459 468 /* cleanup LED */
460 469 mac->ops.cleanup_led = e1000_cleanup_led_generic;
461 470 /* turn on/off LED */
462 471 mac->ops.led_on = e1000_led_on_generic;
463 472 mac->ops.led_off = e1000_led_off_generic;
464 473 /* clear hardware counters */
465 474 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
466 475 /* link info */
467 476 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
468 477 /* acquire SW_FW sync */
469 478 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
470 479 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
471 480 if (mac->type >= e1000_i210) {
472 481 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
473 482 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
474 483 }
475 484
476 485 /* set lan id for port to determine which phy lock to use */
477 486 hw->mac.ops.set_lan_id(hw);
478 487
479 488 return E1000_SUCCESS;
480 489 }
481 490
482 491 /**
483 492 * e1000_init_function_pointers_82575 - Init func ptrs.
484 493 * @hw: pointer to the HW structure
485 494 *
486 495 * Called to initialize all function pointers and parameters.
487 496 **/
488 497 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
489 498 {
490 499 DEBUGFUNC("e1000_init_function_pointers_82575");
491 500
492 501 hw->mac.ops.init_params = e1000_init_mac_params_82575;
493 502 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
494 503 hw->phy.ops.init_params = e1000_init_phy_params_82575;
495 504 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
496 505 }
497 506
498 507 /**
499 508 * e1000_acquire_phy_82575 - Acquire rights to access PHY
500 509 * @hw: pointer to the HW structure
501 510 *
502 511 * Acquire access rights to the correct PHY.
503 512 **/
504 513 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
505 514 {
506 515 u16 mask = E1000_SWFW_PHY0_SM;
507 516
508 517 DEBUGFUNC("e1000_acquire_phy_82575");
509 518
510 519 if (hw->bus.func == E1000_FUNC_1)
511 520 mask = E1000_SWFW_PHY1_SM;
512 521 else if (hw->bus.func == E1000_FUNC_2)
513 522 mask = E1000_SWFW_PHY2_SM;
514 523 else if (hw->bus.func == E1000_FUNC_3)
515 524 mask = E1000_SWFW_PHY3_SM;
516 525
517 526 return hw->mac.ops.acquire_swfw_sync(hw, mask);
518 527 }
519 528
520 529 /**
521 530 * e1000_release_phy_82575 - Release rights to access PHY
522 531 * @hw: pointer to the HW structure
523 532 *
524 533 * A wrapper to release access rights to the correct PHY.
525 534 **/
526 535 static void e1000_release_phy_82575(struct e1000_hw *hw)
527 536 {
528 537 u16 mask = E1000_SWFW_PHY0_SM;
529 538
530 539 DEBUGFUNC("e1000_release_phy_82575");
531 540
532 541 if (hw->bus.func == E1000_FUNC_1)
533 542 mask = E1000_SWFW_PHY1_SM;
534 543 else if (hw->bus.func == E1000_FUNC_2)
535 544 mask = E1000_SWFW_PHY2_SM;
536 545 else if (hw->bus.func == E1000_FUNC_3)
537 546 mask = E1000_SWFW_PHY3_SM;
538 547
539 548 hw->mac.ops.release_swfw_sync(hw, mask);
540 549 }
541 550
542 551 /**
543 552 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
544 553 * @hw: pointer to the HW structure
545 554 * @offset: register offset to be read
546 555 * @data: pointer to the read data
547 556 *
548 557 * Reads the PHY register at offset using the serial gigabit media independent
549 558 * interface and stores the retrieved information in data.
550 559 **/
551 560 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
552 561 u16 *data)
553 562 {
554 563 s32 ret_val = -E1000_ERR_PARAM;
555 564
556 565 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
557 566
558 567 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
559 568 DEBUGOUT1("PHY Address %u is out of range\n", offset);
560 569 goto out;
561 570 }
562 571
563 572 ret_val = hw->phy.ops.acquire(hw);
564 573 if (ret_val)
565 574 goto out;
566 575
567 576 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
568 577
569 578 hw->phy.ops.release(hw);
570 579
571 580 out:
572 581 return ret_val;
573 582 }
574 583
575 584 /**
576 585 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
577 586 * @hw: pointer to the HW structure
578 587 * @offset: register offset to write to
579 588 * @data: data to write at register offset
580 589 *
581 590 * Writes the data to PHY register at the offset using the serial gigabit
582 591 * media independent interface.
583 592 **/
584 593 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
585 594 u16 data)
586 595 {
587 596 s32 ret_val = -E1000_ERR_PARAM;
588 597
589 598 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
590 599
591 600 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
592 601 DEBUGOUT1("PHY Address %d is out of range\n", offset);
593 602 goto out;
594 603 }
595 604
596 605 ret_val = hw->phy.ops.acquire(hw);
597 606 if (ret_val)
598 607 goto out;
599 608
600 609 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
601 610
602 611 hw->phy.ops.release(hw);
603 612
604 613 out:
605 614 return ret_val;
606 615 }
607 616
608 617 /**
609 618 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
610 619 * @hw: pointer to the HW structure
611 620 *
612 621 * Retrieves the PHY address and ID for both PHY's which do and do not use
613 622 * sgmi interface.
614 623 **/
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615 624 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
616 625 {
617 626 struct e1000_phy_info *phy = &hw->phy;
618 627 s32 ret_val = E1000_SUCCESS;
619 628 u16 phy_id;
620 629 u32 ctrl_ext;
621 630 u32 mdic;
622 631
623 632 DEBUGFUNC("e1000_get_phy_id_82575");
624 633
634 + /* some i354 devices need an extra read for phy id */
635 + if (hw->mac.type == e1000_i354)
636 + e1000_get_phy_id(hw);
637 +
625 638 /*
626 639 * For SGMII PHYs, we try the list of possible addresses until
627 640 * we find one that works. For non-SGMII PHYs
628 641 * (e.g. integrated copper PHYs), an address of 1 should
629 642 * work. The result of this function should mean phy->phy_addr
630 643 * and phy->id are set correctly.
631 644 */
632 645 if (!e1000_sgmii_active_82575(hw)) {
633 646 phy->addr = 1;
634 647 ret_val = e1000_get_phy_id(hw);
635 648 goto out;
636 649 }
637 650
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638 651 if (e1000_sgmii_uses_mdio_82575(hw)) {
639 652 switch (hw->mac.type) {
640 653 case e1000_82575:
641 654 case e1000_82576:
642 655 mdic = E1000_READ_REG(hw, E1000_MDIC);
643 656 mdic &= E1000_MDIC_PHY_MASK;
644 657 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
645 658 break;
646 659 case e1000_82580:
647 660 case e1000_i350:
661 + case e1000_i354:
648 662 case e1000_i210:
649 663 case e1000_i211:
650 664 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
651 665 mdic &= E1000_MDICNFG_PHY_MASK;
652 666 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
653 667 break;
654 668 default:
655 669 ret_val = -E1000_ERR_PHY;
656 670 goto out;
657 671 break;
658 672 }
659 673 ret_val = e1000_get_phy_id(hw);
660 674 goto out;
661 675 }
662 676
663 677 /* Power on sgmii phy if it is disabled */
664 678 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
665 679 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
666 680 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
667 681 E1000_WRITE_FLUSH(hw);
668 682 msec_delay(300);
669 683
670 684 /*
671 685 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
672 686 * Therefore, we need to test 1-7
673 687 */
674 688 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
675 689 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
676 690 if (ret_val == E1000_SUCCESS) {
677 691 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
678 692 phy_id, phy->addr);
679 693 /*
680 694 * At the time of this writing, The M88 part is
681 695 * the only supported SGMII PHY product.
682 696 */
683 697 if (phy_id == M88_VENDOR)
684 698 break;
685 699 } else {
686 700 DEBUGOUT1("PHY address %u was unreadable\n",
687 701 phy->addr);
688 702 }
689 703 }
690 704
691 705 /* A valid PHY type couldn't be found. */
692 706 if (phy->addr == 8) {
693 707 phy->addr = 0;
694 708 ret_val = -E1000_ERR_PHY;
695 709 } else {
696 710 ret_val = e1000_get_phy_id(hw);
697 711 }
698 712
699 713 /* restore previous sfp cage power state */
700 714 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
701 715
702 716 out:
703 717 return ret_val;
704 718 }
705 719
706 720 /**
707 721 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
708 722 * @hw: pointer to the HW structure
709 723 *
710 724 * Resets the PHY using the serial gigabit media independent interface.
711 725 **/
712 726 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
713 727 {
714 728 s32 ret_val = E1000_SUCCESS;
715 729
716 730 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
717 731
718 732 /*
719 733 * This isn't a TRUE "hard" reset, but is the only reset
720 734 * available to us at this time.
721 735 */
722 736
723 737 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
724 738
725 739 if (!(hw->phy.ops.write_reg))
726 740 goto out;
727 741
728 742 /*
729 743 * SFP documentation requires the following to configure the SPF module
730 744 * to work on SGMII. No further documentation is given.
731 745 */
732 746 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
733 747 if (ret_val)
734 748 goto out;
735 749
736 750 ret_val = hw->phy.ops.commit(hw);
737 751
738 752 out:
739 753 return ret_val;
740 754 }
741 755
742 756 /**
743 757 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
744 758 * @hw: pointer to the HW structure
745 759 * @active: TRUE to enable LPLU, FALSE to disable
746 760 *
747 761 * Sets the LPLU D0 state according to the active flag. When
748 762 * activating LPLU this function also disables smart speed
749 763 * and vice versa. LPLU will not be activated unless the
750 764 * device autonegotiation advertisement meets standards of
751 765 * either 10 or 10/100 or 10/100/1000 at all duplexes.
752 766 * This is a function pointer entry point only called by
753 767 * PHY setup routines.
754 768 **/
755 769 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
756 770 {
757 771 struct e1000_phy_info *phy = &hw->phy;
758 772 s32 ret_val = E1000_SUCCESS;
759 773 u16 data;
760 774
761 775 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
762 776
763 777 if (!(hw->phy.ops.read_reg))
764 778 goto out;
765 779
766 780 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
767 781 if (ret_val)
768 782 goto out;
769 783
770 784 if (active) {
771 785 data |= IGP02E1000_PM_D0_LPLU;
772 786 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
773 787 data);
774 788 if (ret_val)
775 789 goto out;
776 790
777 791 /* When LPLU is enabled, we should disable SmartSpeed */
778 792 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
779 793 &data);
780 794 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
781 795 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
782 796 data);
783 797 if (ret_val)
784 798 goto out;
785 799 } else {
786 800 data &= ~IGP02E1000_PM_D0_LPLU;
787 801 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
788 802 data);
789 803 /*
790 804 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
791 805 * during Dx states where the power conservation is most
792 806 * important. During driver activity we should enable
793 807 * SmartSpeed, so performance is maintained.
794 808 */
795 809 if (phy->smart_speed == e1000_smart_speed_on) {
796 810 ret_val = phy->ops.read_reg(hw,
797 811 IGP01E1000_PHY_PORT_CONFIG,
798 812 &data);
799 813 if (ret_val)
800 814 goto out;
801 815
802 816 data |= IGP01E1000_PSCFR_SMART_SPEED;
803 817 ret_val = phy->ops.write_reg(hw,
804 818 IGP01E1000_PHY_PORT_CONFIG,
805 819 data);
806 820 if (ret_val)
807 821 goto out;
808 822 } else if (phy->smart_speed == e1000_smart_speed_off) {
809 823 ret_val = phy->ops.read_reg(hw,
810 824 IGP01E1000_PHY_PORT_CONFIG,
811 825 &data);
812 826 if (ret_val)
813 827 goto out;
814 828
815 829 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
816 830 ret_val = phy->ops.write_reg(hw,
817 831 IGP01E1000_PHY_PORT_CONFIG,
818 832 data);
819 833 if (ret_val)
820 834 goto out;
821 835 }
822 836 }
823 837
824 838 out:
825 839 return ret_val;
826 840 }
827 841
828 842 /**
829 843 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
830 844 * @hw: pointer to the HW structure
831 845 * @active: TRUE to enable LPLU, FALSE to disable
832 846 *
833 847 * Sets the LPLU D0 state according to the active flag. When
834 848 * activating LPLU this function also disables smart speed
835 849 * and vice versa. LPLU will not be activated unless the
836 850 * device autonegotiation advertisement meets standards of
837 851 * either 10 or 10/100 or 10/100/1000 at all duplexes.
838 852 * This is a function pointer entry point only called by
839 853 * PHY setup routines.
840 854 **/
841 855 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
842 856 {
843 857 struct e1000_phy_info *phy = &hw->phy;
844 858 s32 ret_val = E1000_SUCCESS;
845 859 u32 data;
846 860
847 861 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
848 862
849 863 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
850 864
851 865 if (active) {
852 866 data |= E1000_82580_PM_D0_LPLU;
853 867
854 868 /* When LPLU is enabled, we should disable SmartSpeed */
855 869 data &= ~E1000_82580_PM_SPD;
856 870 } else {
857 871 data &= ~E1000_82580_PM_D0_LPLU;
858 872
859 873 /*
860 874 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
861 875 * during Dx states where the power conservation is most
862 876 * important. During driver activity we should enable
863 877 * SmartSpeed, so performance is maintained.
864 878 */
865 879 if (phy->smart_speed == e1000_smart_speed_on)
866 880 data |= E1000_82580_PM_SPD;
867 881 else if (phy->smart_speed == e1000_smart_speed_off)
868 882 data &= ~E1000_82580_PM_SPD;
869 883 }
870 884
871 885 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
872 886 return ret_val;
873 887 }
874 888
875 889 /**
876 890 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
877 891 * @hw: pointer to the HW structure
878 892 * @active: boolean used to enable/disable lplu
879 893 *
880 894 * Success returns 0, Failure returns 1
881 895 *
882 896 * The low power link up (lplu) state is set to the power management level D3
883 897 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
884 898 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
885 899 * is used during Dx states where the power conservation is most important.
886 900 * During driver activity, SmartSpeed should be enabled so performance is
887 901 * maintained.
888 902 **/
889 903 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
890 904 {
891 905 struct e1000_phy_info *phy = &hw->phy;
892 906 s32 ret_val = E1000_SUCCESS;
893 907 u32 data;
894 908
895 909 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
896 910
897 911 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
898 912
899 913 if (!active) {
900 914 data &= ~E1000_82580_PM_D3_LPLU;
901 915 /*
902 916 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
903 917 * during Dx states where the power conservation is most
904 918 * important. During driver activity we should enable
905 919 * SmartSpeed, so performance is maintained.
906 920 */
907 921 if (phy->smart_speed == e1000_smart_speed_on)
908 922 data |= E1000_82580_PM_SPD;
909 923 else if (phy->smart_speed == e1000_smart_speed_off)
910 924 data &= ~E1000_82580_PM_SPD;
911 925 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
912 926 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
913 927 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
914 928 data |= E1000_82580_PM_D3_LPLU;
915 929 /* When LPLU is enabled, we should disable SmartSpeed */
916 930 data &= ~E1000_82580_PM_SPD;
917 931 }
918 932
919 933 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
920 934 return ret_val;
921 935 }
922 936
923 937 /**
924 938 * e1000_acquire_nvm_82575 - Request for access to EEPROM
925 939 * @hw: pointer to the HW structure
926 940 *
927 941 * Acquire the necessary semaphores for exclusive access to the EEPROM.
928 942 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
929 943 * Return successful if access grant bit set, else clear the request for
930 944 * EEPROM access and return -E1000_ERR_NVM (-1).
931 945 **/
932 946 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
933 947 {
934 948 s32 ret_val;
935 949
936 950 DEBUGFUNC("e1000_acquire_nvm_82575");
937 951
938 952 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
939 953 if (ret_val)
940 954 goto out;
941 955
942 956 /*
943 957 * Check if there is some access
944 958 * error this access may hook on
945 959 */
946 960 if (hw->mac.type == e1000_i350) {
947 961 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
948 962 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
949 963 E1000_EECD_TIMEOUT)) {
950 964 /* Clear all access error flags */
951 965 E1000_WRITE_REG(hw, E1000_EECD, eecd |
952 966 E1000_EECD_ERROR_CLR);
953 967 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
954 968 }
955 969 }
956 970 if (hw->mac.type == e1000_82580) {
957 971 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
958 972 if (eecd & E1000_EECD_BLOCKED) {
959 973 /* Clear access error flag */
960 974 E1000_WRITE_REG(hw, E1000_EECD, eecd |
961 975 E1000_EECD_BLOCKED);
962 976 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
963 977 }
964 978 }
965 979
966 980
967 981 ret_val = e1000_acquire_nvm_generic(hw);
968 982 if (ret_val)
969 983 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
970 984
971 985 out:
972 986 return ret_val;
973 987 }
974 988
975 989 /**
976 990 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
977 991 * @hw: pointer to the HW structure
978 992 *
979 993 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
980 994 * then release the semaphores acquired.
981 995 **/
982 996 static void e1000_release_nvm_82575(struct e1000_hw *hw)
983 997 {
984 998 DEBUGFUNC("e1000_release_nvm_82575");
985 999
986 1000 e1000_release_nvm_generic(hw);
987 1001
988 1002 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
989 1003 }
990 1004
991 1005 /**
992 1006 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
993 1007 * @hw: pointer to the HW structure
994 1008 * @mask: specifies which semaphore to acquire
995 1009 *
996 1010 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
997 1011 * will also specify which port we're acquiring the lock for.
998 1012 **/
999 1013 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1000 1014 {
1001 1015 u32 swfw_sync;
1002 1016 u32 swmask = mask;
1003 1017 u32 fwmask = mask << 16;
1004 1018 s32 ret_val = E1000_SUCCESS;
1005 1019 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1006 1020
1007 1021 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1008 1022
1009 1023 while (i < timeout) {
1010 1024 if (e1000_get_hw_semaphore_generic(hw)) {
1011 1025 ret_val = -E1000_ERR_SWFW_SYNC;
1012 1026 goto out;
1013 1027 }
1014 1028
1015 1029 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1016 1030 if (!(swfw_sync & (fwmask | swmask)))
1017 1031 break;
1018 1032
1019 1033 /*
1020 1034 * Firmware currently using resource (fwmask)
1021 1035 * or other software thread using resource (swmask)
1022 1036 */
1023 1037 e1000_put_hw_semaphore_generic(hw);
1024 1038 msec_delay_irq(5);
1025 1039 i++;
1026 1040 }
1027 1041
1028 1042 if (i == timeout) {
1029 1043 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1030 1044 ret_val = -E1000_ERR_SWFW_SYNC;
1031 1045 goto out;
1032 1046 }
1033 1047
1034 1048 swfw_sync |= swmask;
1035 1049 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1036 1050
1037 1051 e1000_put_hw_semaphore_generic(hw);
1038 1052
1039 1053 out:
1040 1054 return ret_val;
1041 1055 }
1042 1056
1043 1057 /**
1044 1058 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1045 1059 * @hw: pointer to the HW structure
1046 1060 * @mask: specifies which semaphore to acquire
1047 1061 *
1048 1062 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1049 1063 * will also specify which port we're releasing the lock for.
1050 1064 **/
1051 1065 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1052 1066 {
1053 1067 u32 swfw_sync;
1054 1068
1055 1069 DEBUGFUNC("e1000_release_swfw_sync_82575");
1056 1070
1057 1071 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1058 1072 ; /* Empty */
1059 1073
1060 1074 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1061 1075 swfw_sync &= ~mask;
1062 1076 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1063 1077
1064 1078 e1000_put_hw_semaphore_generic(hw);
1065 1079 }
1066 1080
1067 1081 /**
1068 1082 * e1000_get_cfg_done_82575 - Read config done bit
1069 1083 * @hw: pointer to the HW structure
1070 1084 *
1071 1085 * Read the management control register for the config done bit for
1072 1086 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1073 1087 * to read the config done bit, so an error is *ONLY* logged and returns
1074 1088 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1075 1089 * would not be able to be reset or change link.
1076 1090 **/
1077 1091 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1078 1092 {
1079 1093 s32 timeout = PHY_CFG_TIMEOUT;
1080 1094 s32 ret_val = E1000_SUCCESS;
1081 1095 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1082 1096
1083 1097 DEBUGFUNC("e1000_get_cfg_done_82575");
1084 1098
1085 1099 if (hw->bus.func == E1000_FUNC_1)
1086 1100 mask = E1000_NVM_CFG_DONE_PORT_1;
1087 1101 else if (hw->bus.func == E1000_FUNC_2)
1088 1102 mask = E1000_NVM_CFG_DONE_PORT_2;
1089 1103 else if (hw->bus.func == E1000_FUNC_3)
1090 1104 mask = E1000_NVM_CFG_DONE_PORT_3;
1091 1105 while (timeout) {
1092 1106 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1093 1107 break;
1094 1108 msec_delay(1);
1095 1109 timeout--;
1096 1110 }
1097 1111 if (!timeout)
1098 1112 DEBUGOUT("MNG configuration cycle has not completed.\n");
1099 1113
1100 1114 /* If EEPROM is not marked present, init the PHY manually */
1101 1115 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1102 1116 (hw->phy.type == e1000_phy_igp_3))
1103 1117 e1000_phy_init_script_igp3(hw);
1104 1118
1105 1119 return ret_val;
1106 1120 }
1107 1121
1108 1122 /**
1109 1123 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1110 1124 * @hw: pointer to the HW structure
1111 1125 * @speed: stores the current speed
1112 1126 * @duplex: stores the current duplex
1113 1127 *
1114 1128 * This is a wrapper function, if using the serial gigabit media independent
1115 1129 * interface, use PCS to retrieve the link speed and duplex information.
1116 1130 * Otherwise, use the generic function to get the link speed and duplex info.
1117 1131 **/
1118 1132 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1119 1133 u16 *duplex)
1120 1134 {
1121 1135 s32 ret_val;
1122 1136
1123 1137 DEBUGFUNC("e1000_get_link_up_info_82575");
1124 1138
1125 1139 if (hw->phy.media_type != e1000_media_type_copper)
1126 1140 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1127 1141 duplex);
1128 1142 else
1129 1143 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1130 1144 duplex);
1131 1145
1132 1146 return ret_val;
1133 1147 }
1134 1148
1135 1149 /**
1136 1150 * e1000_check_for_link_82575 - Check for link
1137 1151 * @hw: pointer to the HW structure
1138 1152 *
1139 1153 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1140 1154 * use the generic interface for determining link.
1141 1155 **/
1142 1156 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1143 1157 {
1144 1158 s32 ret_val;
1145 1159 u16 speed, duplex;
1146 1160
1147 1161 DEBUGFUNC("e1000_check_for_link_82575");
1148 1162
1149 1163 if (hw->phy.media_type != e1000_media_type_copper) {
1150 1164 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1151 1165 &duplex);
1152 1166 /*
1153 1167 * Use this flag to determine if link needs to be checked or
1154 1168 * not. If we have link clear the flag so that we do not
1155 1169 * continue to check for link.
1156 1170 */
1157 1171 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1158 1172
1159 1173 /*
1160 1174 * Configure Flow Control now that Auto-Neg has completed.
1161 1175 * First, we need to restore the desired flow control
1162 1176 * settings because we may have had to re-autoneg with a
1163 1177 * different link partner.
1164 1178 */
1165 1179 ret_val = e1000_config_fc_after_link_up_generic(hw);
1166 1180 if (ret_val)
1167 1181 DEBUGOUT("Error configuring flow control\n");
1168 1182 } else {
1169 1183 ret_val = e1000_check_for_copper_link_generic(hw);
1170 1184 }
1171 1185
1172 1186 return ret_val;
1173 1187 }
1174 1188
1175 1189 /**
1176 1190 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1177 1191 * @hw: pointer to the HW structure
1178 1192 **/
1179 1193 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1180 1194 {
1181 1195 u32 reg;
1182 1196
1183 1197 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1184 1198
1185 1199 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1186 1200 !e1000_sgmii_active_82575(hw))
1187 1201 return;
1188 1202
1189 1203 /* Enable PCS to turn on link */
1190 1204 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1191 1205 reg |= E1000_PCS_CFG_PCS_EN;
1192 1206 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1193 1207
1194 1208 /* Power up the laser */
1195 1209 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1196 1210 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1197 1211 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1198 1212
1199 1213 /* flush the write to verify completion */
1200 1214 E1000_WRITE_FLUSH(hw);
1201 1215 msec_delay(1);
1202 1216 }
1203 1217
1204 1218 /**
1205 1219 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1206 1220 * @hw: pointer to the HW structure
1207 1221 * @speed: stores the current speed
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1208 1222 * @duplex: stores the current duplex
1209 1223 *
1210 1224 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1211 1225 * duplex, then store the values in the pointers provided.
1212 1226 **/
1213 1227 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1214 1228 u16 *speed, u16 *duplex)
1215 1229 {
1216 1230 struct e1000_mac_info *mac = &hw->mac;
1217 1231 u32 pcs;
1232 + u32 status;
1218 1233
1219 1234 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1220 1235
1221 1236 /*
1222 1237 * Read the PCS Status register for link state. For non-copper mode,
1223 1238 * the status register is not accurate. The PCS status register is
1224 1239 * used instead.
1225 1240 */
1226 1241 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1227 1242
1228 1243 /*
1229 1244 * The link up bit determines when link is up on autoneg.
1230 1245 */
1231 1246 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1232 1247 mac->serdes_has_link = TRUE;
1233 1248
1234 1249 /* Detect and store PCS speed */
1235 1250 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1236 1251 *speed = SPEED_1000;
1237 1252 else if (pcs & E1000_PCS_LSTS_SPEED_100)
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1238 1253 *speed = SPEED_100;
1239 1254 else
1240 1255 *speed = SPEED_10;
1241 1256
1242 1257 /* Detect and store PCS duplex */
1243 1258 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1244 1259 *duplex = FULL_DUPLEX;
1245 1260 else
1246 1261 *duplex = HALF_DUPLEX;
1247 1262
1263 + /* Check if it is an I354 2.5Gb backplane connection. */
1264 + if (mac->type == e1000_i354) {
1265 + status = E1000_READ_REG(hw, E1000_STATUS);
1266 + if ((status & E1000_STATUS_2P5_SKU) &&
1267 + !(status & E1000_STATUS_2P5_SKU_OVER)) {
1268 + *speed = SPEED_2500;
1269 + *duplex = FULL_DUPLEX;
1270 + DEBUGOUT("2500 Mbs, ");
1271 + DEBUGOUT("Full Duplex\n");
1272 + }
1273 + }
1274 +
1248 1275 } else {
1249 1276 mac->serdes_has_link = FALSE;
1250 1277 *speed = 0;
1251 1278 *duplex = 0;
1252 1279 }
1253 1280
1254 1281 return E1000_SUCCESS;
1255 1282 }
1256 1283
1257 1284 /**
1258 1285 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1259 1286 * @hw: pointer to the HW structure
1260 1287 *
1261 1288 * In the case of serdes shut down sfp and PCS on driver unload
1262 1289 * when management pass thru is not enabled.
1263 1290 **/
1264 1291 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1265 1292 {
1266 1293 u32 reg;
1267 1294
1268 1295 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1269 1296
1270 1297 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1271 1298 !e1000_sgmii_active_82575(hw))
1272 1299 return;
1273 1300
1274 1301 if (!e1000_enable_mng_pass_thru(hw)) {
1275 1302 /* Disable PCS to turn off link */
1276 1303 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1277 1304 reg &= ~E1000_PCS_CFG_PCS_EN;
1278 1305 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1279 1306
1280 1307 /* shutdown the laser */
1281 1308 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1282 1309 reg |= E1000_CTRL_EXT_SDP3_DATA;
1283 1310 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1284 1311
1285 1312 /* flush the write to verify completion */
1286 1313 E1000_WRITE_FLUSH(hw);
1287 1314 msec_delay(1);
1288 1315 }
1289 1316
1290 1317 return;
1291 1318 }
1292 1319
1293 1320 /**
1294 1321 * e1000_reset_hw_82575 - Reset hardware
1295 1322 * @hw: pointer to the HW structure
1296 1323 *
1297 1324 * This resets the hardware into a known state.
1298 1325 **/
1299 1326 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1300 1327 {
1301 1328 u32 ctrl;
1302 1329 s32 ret_val;
1303 1330
1304 1331 DEBUGFUNC("e1000_reset_hw_82575");
1305 1332
1306 1333 /*
1307 1334 * Prevent the PCI-E bus from sticking if there is no TLP connection
1308 1335 * on the last TLP read/write transaction when MAC is reset.
1309 1336 */
1310 1337 ret_val = e1000_disable_pcie_master_generic(hw);
1311 1338 if (ret_val)
1312 1339 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1313 1340
1314 1341 /* set the completion timeout for interface */
1315 1342 ret_val = e1000_set_pcie_completion_timeout(hw);
1316 1343 if (ret_val)
1317 1344 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1318 1345
1319 1346 DEBUGOUT("Masking off all interrupts\n");
1320 1347 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1321 1348
1322 1349 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1323 1350 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1324 1351 E1000_WRITE_FLUSH(hw);
1325 1352
1326 1353 msec_delay(10);
1327 1354
1328 1355 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1329 1356
1330 1357 DEBUGOUT("Issuing a global reset to MAC\n");
1331 1358 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1332 1359
1333 1360 ret_val = e1000_get_auto_rd_done_generic(hw);
1334 1361 if (ret_val) {
1335 1362 /*
1336 1363 * When auto config read does not complete, do not
1337 1364 * return with an error. This can happen in situations
1338 1365 * where there is no eeprom and prevents getting link.
1339 1366 */
1340 1367 DEBUGOUT("Auto Read Done did not complete\n");
1341 1368 }
1342 1369
1343 1370 /* If EEPROM is not present, run manual init scripts */
1344 1371 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1345 1372 e1000_reset_init_script_82575(hw);
1346 1373
1347 1374 /* Clear any pending interrupt events. */
1348 1375 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1349 1376 E1000_READ_REG(hw, E1000_ICR);
1350 1377
1351 1378 /* Install any alternate MAC address into RAR0 */
1352 1379 ret_val = e1000_check_alt_mac_addr_generic(hw);
1353 1380
1354 1381 return ret_val;
1355 1382 }
1356 1383
1357 1384 /**
1358 1385 * e1000_init_hw_82575 - Initialize hardware
1359 1386 * @hw: pointer to the HW structure
1360 1387 *
1361 1388 * This inits the hardware readying it for operation.
1362 1389 **/
1363 1390 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1364 1391 {
1365 1392 struct e1000_mac_info *mac = &hw->mac;
1366 1393 s32 ret_val;
1367 1394 u16 i, rar_count = mac->rar_entry_count;
1368 1395
1369 1396 DEBUGFUNC("e1000_init_hw_82575");
1370 1397
1371 1398 /* Initialize identification LED */
1372 1399 ret_val = mac->ops.id_led_init(hw);
1373 1400 if (ret_val) {
1374 1401 DEBUGOUT("Error initializing identification LED\n");
1375 1402 /* This is not fatal and we should not stop init due to this */
1376 1403 }
1377 1404
1378 1405 /* Disabling VLAN filtering */
1379 1406 DEBUGOUT("Initializing the IEEE VLAN\n");
1380 1407 mac->ops.clear_vfta(hw);
1381 1408
1382 1409 /* Setup the receive address */
1383 1410 e1000_init_rx_addrs_generic(hw, rar_count);
1384 1411
1385 1412 /* Zero out the Multicast HASH table */
1386 1413 DEBUGOUT("Zeroing the MTA\n");
1387 1414 for (i = 0; i < mac->mta_reg_count; i++)
1388 1415 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1389 1416
1390 1417 /* Zero out the Unicast HASH table */
1391 1418 DEBUGOUT("Zeroing the UTA\n");
1392 1419 for (i = 0; i < mac->uta_reg_count; i++)
1393 1420 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1394 1421
1395 1422 /* Setup link and flow control */
1396 1423 ret_val = mac->ops.setup_link(hw);
1397 1424
1398 1425 /* Set the default MTU size */
1399 1426 hw->dev_spec._82575.mtu = 1500;
1400 1427
1401 1428 /*
1402 1429 * Clear all of the statistics registers (clear on read). It is
1403 1430 * important that we do this after we have tried to establish link
1404 1431 * because the symbol error count will increment wildly if there
1405 1432 * is no link.
1406 1433 */
1407 1434 e1000_clear_hw_cntrs_82575(hw);
1408 1435
1409 1436 return ret_val;
1410 1437 }
1411 1438
1412 1439 /**
1413 1440 * e1000_setup_copper_link_82575 - Configure copper link settings
1414 1441 * @hw: pointer to the HW structure
1415 1442 *
1416 1443 * Configures the link for auto-neg or forced speed and duplex. Then we check
1417 1444 * for link, once link is established calls to configure collision distance
1418 1445 * and flow control are called.
1419 1446 **/
1420 1447 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1421 1448 {
1422 1449 u32 ctrl;
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1423 1450 s32 ret_val;
1424 1451 u32 phpm_reg;
1425 1452
1426 1453 DEBUGFUNC("e1000_setup_copper_link_82575");
1427 1454
1428 1455 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1429 1456 ctrl |= E1000_CTRL_SLU;
1430 1457 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1431 1458 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1432 1459
1433 - /* Clear Go Link Disconnect bit */
1434 - if (hw->mac.type >= e1000_82580) {
1460 + /* Clear Go Link Disconnect bit on supported devices */
1461 + switch (hw->mac.type) {
1462 + case e1000_82580:
1463 + case e1000_i350:
1464 + case e1000_i210:
1465 + case e1000_i211:
1435 1466 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1436 1467 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1437 1468 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1469 + break;
1470 + default:
1471 + break;
1438 1472 }
1439 1473
1440 1474 ret_val = e1000_setup_serdes_link_82575(hw);
1441 1475 if (ret_val)
1442 1476 goto out;
1443 1477
1444 1478 if (e1000_sgmii_active_82575(hw)) {
1445 1479 /* allow time for SFP cage time to power up phy */
1446 1480 msec_delay(300);
1447 1481
1448 1482 ret_val = hw->phy.ops.reset(hw);
1449 1483 if (ret_val) {
1450 1484 DEBUGOUT("Error resetting the PHY.\n");
1451 1485 goto out;
1452 1486 }
1453 1487 }
1454 1488 switch (hw->phy.type) {
1455 1489 case e1000_phy_i210:
1456 1490 case e1000_phy_m88:
1457 1491 switch (hw->phy.id) {
1458 1492 case I347AT4_E_PHY_ID:
1459 1493 case M88E1112_E_PHY_ID:
1460 1494 case M88E1340M_E_PHY_ID:
1461 1495 case I210_I_PHY_ID:
1462 1496 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1463 1497 break;
1464 1498 default:
1465 1499 ret_val = e1000_copper_link_setup_m88(hw);
1466 1500 break;
1467 1501 }
1468 1502 break;
1469 1503 case e1000_phy_igp_3:
1470 1504 ret_val = e1000_copper_link_setup_igp(hw);
1471 1505 break;
1472 1506 case e1000_phy_82580:
1473 1507 ret_val = e1000_copper_link_setup_82577(hw);
1474 1508 break;
1475 1509 default:
1476 1510 ret_val = -E1000_ERR_PHY;
1477 1511 break;
1478 1512 }
1479 1513
1480 1514 if (ret_val)
1481 1515 goto out;
1482 1516
1483 1517 ret_val = e1000_setup_copper_link_generic(hw);
1484 1518 out:
1485 1519 return ret_val;
1486 1520 }
1487 1521
1488 1522 /**
1489 1523 * e1000_setup_serdes_link_82575 - Setup link for serdes
1490 1524 * @hw: pointer to the HW structure
1491 1525 *
1492 1526 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1493 1527 * used on copper connections where the serialized gigabit media independent
1494 1528 * interface (sgmii), or serdes fiber is being used. Configures the link
1495 1529 * for auto-negotiation or forces speed/duplex.
1496 1530 **/
1497 1531 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1498 1532 {
1499 1533 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1500 1534 bool pcs_autoneg;
1501 1535 s32 ret_val = E1000_SUCCESS;
1502 1536 u16 data;
1503 1537
1504 1538 DEBUGFUNC("e1000_setup_serdes_link_82575");
1505 1539
1506 1540 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1507 1541 !e1000_sgmii_active_82575(hw))
1508 1542 return ret_val;
1509 1543
1510 1544 /*
1511 1545 * On the 82575, SerDes loopback mode persists until it is
1512 1546 * explicitly turned off or a power cycle is performed. A read to
1513 1547 * the register does not indicate its status. Therefore, we ensure
1514 1548 * loopback mode is disabled during initialization.
1515 1549 */
1516 1550 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1517 1551
1518 1552 /* power on the sfp cage if present */
1519 1553 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1520 1554 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1521 1555 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1522 1556
1523 1557 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1524 1558 ctrl_reg |= E1000_CTRL_SLU;
1525 1559
1526 1560 /* set both sw defined pins on 82575/82576*/
1527 1561 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1528 1562 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1529 1563
1530 1564 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1531 1565
1532 1566 /* default pcs_autoneg to the same setting as mac autoneg */
1533 1567 pcs_autoneg = hw->mac.autoneg;
1534 1568
1535 1569 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1536 1570 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1537 1571 /* sgmii mode lets the phy handle forcing speed/duplex */
1538 1572 pcs_autoneg = TRUE;
1539 1573 /* autoneg time out should be disabled for SGMII mode */
1540 1574 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1541 1575 break;
1542 1576 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1543 1577 /* disable PCS autoneg and support parallel detect only */
1544 1578 pcs_autoneg = FALSE;
1545 1579 /* fall through to default case */
1546 1580 default:
1547 1581 if (hw->mac.type == e1000_82575 ||
1548 1582 hw->mac.type == e1000_82576) {
1549 1583 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1550 1584 if (ret_val) {
1551 1585 DEBUGOUT("NVM Read Error\n");
1552 1586 return ret_val;
1553 1587 }
1554 1588
1555 1589 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1556 1590 pcs_autoneg = FALSE;
1557 1591 }
1558 1592
1559 1593 /*
1560 1594 * non-SGMII modes only supports a speed of 1000/Full for the
1561 1595 * link so it is best to just force the MAC and let the pcs
1562 1596 * link either autoneg or be forced to 1000/Full
1563 1597 */
1564 1598 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1565 1599 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1566 1600
1567 1601 /* set speed of 1000/Full if speed/duplex is forced */
1568 1602 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1569 1603 break;
1570 1604 }
1571 1605
1572 1606 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1573 1607
1574 1608 /*
1575 1609 * New SerDes mode allows for forcing speed or autonegotiating speed
1576 1610 * at 1gb. Autoneg should be default set by most drivers. This is the
1577 1611 * mode that will be compatible with older link partners and switches.
1578 1612 * However, both are supported by the hardware and some drivers/tools.
1579 1613 */
1580 1614 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1581 1615 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1582 1616
1583 1617 if (pcs_autoneg) {
1584 1618 /* Set PCS register for autoneg */
1585 1619 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1586 1620 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1587 1621
1588 1622 /* Disable force flow control for autoneg */
1589 1623 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1590 1624
1591 1625 /* Configure flow control advertisement for autoneg */
1592 1626 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1593 1627 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1594 1628
1595 1629 switch (hw->fc.requested_mode) {
1596 1630 case e1000_fc_full:
1597 1631 case e1000_fc_rx_pause:
1598 1632 anadv_reg |= E1000_TXCW_ASM_DIR;
1599 1633 anadv_reg |= E1000_TXCW_PAUSE;
1600 1634 break;
1601 1635 case e1000_fc_tx_pause:
1602 1636 anadv_reg |= E1000_TXCW_ASM_DIR;
1603 1637 break;
1604 1638 default:
1605 1639 break;
1606 1640 }
1607 1641
1608 1642 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1609 1643
1610 1644 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1611 1645 } else {
1612 1646 /* Set PCS register for forced link */
1613 1647 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1614 1648
1615 1649 /* Force flow control for forced link */
1616 1650 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1617 1651
1618 1652 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1619 1653 }
1620 1654
1621 1655 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1622 1656
1623 1657 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1624 1658 e1000_force_mac_fc_generic(hw);
1625 1659
1626 1660 return ret_val;
1627 1661 }
1628 1662
1629 1663 /**
1630 1664 * e1000_get_media_type_82575 - derives current media type.
1631 1665 * @hw: pointer to the HW structure
1632 1666 *
1633 1667 * The media type is chosen reflecting few settings.
1634 1668 * The following are taken into account:
1635 1669 * - link mode set in the current port Init Control Word #3
1636 1670 * - current link mode settings in CSR register
1637 1671 * - MDIO vs. I2C PHY control interface chosen
1638 1672 * - SFP module media type
1639 1673 **/
1640 1674 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1641 1675 {
1642 1676 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1643 1677 s32 ret_val = E1000_SUCCESS;
1644 1678 u32 ctrl_ext = 0;
1645 1679 u32 link_mode = 0;
1646 1680
1647 1681 /* Set internal phy as default */
1648 1682 dev_spec->sgmii_active = FALSE;
1649 1683 dev_spec->module_plugged = FALSE;
1650 1684
1651 1685 /* Get CSR setting */
1652 1686 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1653 1687
1654 1688 /* extract link mode setting */
1655 1689 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1656 1690
1657 1691 switch (link_mode) {
1658 1692 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1659 1693 hw->phy.media_type = e1000_media_type_internal_serdes;
1660 1694 break;
1661 1695 case E1000_CTRL_EXT_LINK_MODE_GMII:
1662 1696 hw->phy.media_type = e1000_media_type_copper;
1663 1697 break;
1664 1698 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1665 1699 /* Get phy control interface type set (MDIO vs. I2C)*/
1666 1700 if (e1000_sgmii_uses_mdio_82575(hw)) {
1667 1701 hw->phy.media_type = e1000_media_type_copper;
1668 1702 dev_spec->sgmii_active = TRUE;
1669 1703 break;
1670 1704 }
1671 1705 /* fall through for I2C based SGMII */
1672 1706 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1673 1707 /* read media type from SFP EEPROM */
1674 1708 ret_val = e1000_set_sfp_media_type_82575(hw);
1675 1709 if ((ret_val != E1000_SUCCESS) ||
1676 1710 (hw->phy.media_type == e1000_media_type_unknown)) {
1677 1711 /*
1678 1712 * If media type was not identified then return media
1679 1713 * type defined by the CTRL_EXT settings.
1680 1714 */
1681 1715 hw->phy.media_type = e1000_media_type_internal_serdes;
1682 1716
1683 1717 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1684 1718 hw->phy.media_type = e1000_media_type_copper;
1685 1719 dev_spec->sgmii_active = TRUE;
1686 1720 }
1687 1721
1688 1722 break;
1689 1723 }
1690 1724
1691 1725 /* do not change link mode for 100BaseFX */
1692 1726 if (dev_spec->eth_flags.e100_base_fx)
1693 1727 break;
1694 1728
1695 1729 /* change current link mode setting */
1696 1730 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1697 1731
1698 1732 if (hw->phy.media_type == e1000_media_type_copper)
1699 1733 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1700 1734 else
1701 1735 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1702 1736
1703 1737 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1704 1738
1705 1739 break;
1706 1740 }
1707 1741
1708 1742 return ret_val;
1709 1743 }
1710 1744
1711 1745 /**
1712 1746 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1713 1747 * @hw: pointer to the HW structure
1714 1748 *
1715 1749 * The media type is chosen based on SFP module.
1716 1750 * compatibility flags retrieved from SFP ID EEPROM.
1717 1751 **/
1718 1752 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1719 1753 {
1720 1754 s32 ret_val = E1000_ERR_CONFIG;
1721 1755 u32 ctrl_ext = 0;
1722 1756 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1723 1757 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1724 1758 u8 tranceiver_type = 0;
1725 1759 s32 timeout = 3;
1726 1760
1727 1761 /* Turn I2C interface ON and power on sfp cage */
1728 1762 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1729 1763 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1730 1764 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1731 1765
1732 1766 E1000_WRITE_FLUSH(hw);
1733 1767
1734 1768 /* Read SFP module data */
1735 1769 while (timeout) {
1736 1770 ret_val = e1000_read_sfp_data_byte(hw,
1737 1771 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1738 1772 &tranceiver_type);
1739 1773 if (ret_val == E1000_SUCCESS)
1740 1774 break;
1741 1775 msec_delay(100);
1742 1776 timeout--;
1743 1777 }
1744 1778 if (ret_val != E1000_SUCCESS)
1745 1779 goto out;
1746 1780
1747 1781 ret_val = e1000_read_sfp_data_byte(hw,
1748 1782 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1749 1783 (u8 *)eth_flags);
1750 1784 if (ret_val != E1000_SUCCESS)
1751 1785 goto out;
1752 1786
1753 1787 /* Check if there is some SFP module plugged and powered */
1754 1788 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1755 1789 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1756 1790 dev_spec->module_plugged = TRUE;
1757 1791 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1758 1792 hw->phy.media_type = e1000_media_type_internal_serdes;
1759 1793 } else if (eth_flags->e100_base_fx) {
1760 1794 dev_spec->sgmii_active = TRUE;
1761 1795 hw->phy.media_type = e1000_media_type_internal_serdes;
1762 1796 } else if (eth_flags->e1000_base_t) {
1763 1797 dev_spec->sgmii_active = TRUE;
1764 1798 hw->phy.media_type = e1000_media_type_copper;
1765 1799 } else {
1766 1800 hw->phy.media_type = e1000_media_type_unknown;
1767 1801 DEBUGOUT("PHY module has not been recognized\n");
1768 1802 goto out;
1769 1803 }
1770 1804 } else {
1771 1805 hw->phy.media_type = e1000_media_type_unknown;
1772 1806 }
1773 1807 ret_val = E1000_SUCCESS;
1774 1808 out:
1775 1809 /* Restore I2C interface setting */
1776 1810 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1777 1811 return ret_val;
1778 1812 }
1779 1813
1780 1814 /**
1781 1815 * e1000_valid_led_default_82575 - Verify a valid default LED config
1782 1816 * @hw: pointer to the HW structure
1783 1817 * @data: pointer to the NVM (EEPROM)
1784 1818 *
1785 1819 * Read the EEPROM for the current default LED configuration. If the
1786 1820 * LED configuration is not valid, set to a valid LED configuration.
1787 1821 **/
1788 1822 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1789 1823 {
1790 1824 s32 ret_val;
1791 1825
1792 1826 DEBUGFUNC("e1000_valid_led_default_82575");
1793 1827
1794 1828 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1795 1829 if (ret_val) {
1796 1830 DEBUGOUT("NVM Read Error\n");
1797 1831 goto out;
1798 1832 }
1799 1833
1800 1834 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1801 1835 switch (hw->phy.media_type) {
1802 1836 case e1000_media_type_internal_serdes:
1803 1837 *data = ID_LED_DEFAULT_82575_SERDES;
1804 1838 break;
1805 1839 case e1000_media_type_copper:
1806 1840 default:
1807 1841 *data = ID_LED_DEFAULT;
1808 1842 break;
1809 1843 }
1810 1844 }
1811 1845 out:
1812 1846 return ret_val;
1813 1847 }
1814 1848
1815 1849 /**
1816 1850 * e1000_sgmii_active_82575 - Return sgmii state
1817 1851 * @hw: pointer to the HW structure
1818 1852 *
1819 1853 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1820 1854 * which can be enabled for use in the embedded applications. Simply
1821 1855 * return the current state of the sgmii interface.
1822 1856 **/
1823 1857 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1824 1858 {
1825 1859 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1826 1860 return dev_spec->sgmii_active;
1827 1861 }
1828 1862
1829 1863 /**
1830 1864 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1831 1865 * @hw: pointer to the HW structure
1832 1866 *
1833 1867 * Inits recommended HW defaults after a reset when there is no EEPROM
1834 1868 * detected. This is only for the 82575.
1835 1869 **/
1836 1870 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1837 1871 {
1838 1872 DEBUGFUNC("e1000_reset_init_script_82575");
1839 1873
1840 1874 if (hw->mac.type == e1000_82575) {
1841 1875 DEBUGOUT("Running reset init script for 82575\n");
1842 1876 /* SerDes configuration via SERDESCTRL */
1843 1877 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1844 1878 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1845 1879 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1846 1880 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1847 1881
1848 1882 /* CCM configuration via CCMCTL register */
1849 1883 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1850 1884 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1851 1885
1852 1886 /* PCIe lanes configuration */
1853 1887 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1854 1888 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1855 1889 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1856 1890 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1857 1891
1858 1892 /* PCIe PLL Configuration */
1859 1893 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1860 1894 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1861 1895 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1862 1896 }
1863 1897
1864 1898 return E1000_SUCCESS;
1865 1899 }
1866 1900
1867 1901 /**
1868 1902 * e1000_read_mac_addr_82575 - Read device MAC address
1869 1903 * @hw: pointer to the HW structure
1870 1904 **/
1871 1905 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1872 1906 {
1873 1907 s32 ret_val = E1000_SUCCESS;
1874 1908
1875 1909 DEBUGFUNC("e1000_read_mac_addr_82575");
1876 1910
1877 1911 /*
1878 1912 * If there's an alternate MAC address place it in RAR0
1879 1913 * so that it will override the Si installed default perm
1880 1914 * address.
1881 1915 */
1882 1916 ret_val = e1000_check_alt_mac_addr_generic(hw);
1883 1917 if (ret_val)
1884 1918 goto out;
1885 1919
1886 1920 ret_val = e1000_read_mac_addr_generic(hw);
1887 1921
1888 1922 out:
1889 1923 return ret_val;
1890 1924 }
1891 1925
1892 1926 /**
1893 1927 * e1000_config_collision_dist_82575 - Configure collision distance
1894 1928 * @hw: pointer to the HW structure
1895 1929 *
1896 1930 * Configures the collision distance to the default value and is used
1897 1931 * during link setup.
1898 1932 **/
1899 1933 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1900 1934 {
1901 1935 u32 tctl_ext;
1902 1936
1903 1937 DEBUGFUNC("e1000_config_collision_dist_82575");
1904 1938
1905 1939 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1906 1940
1907 1941 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1908 1942 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1909 1943
1910 1944 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1911 1945 E1000_WRITE_FLUSH(hw);
1912 1946 }
1913 1947
1914 1948 /**
1915 1949 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1916 1950 * @hw: pointer to the HW structure
1917 1951 *
1918 1952 * In the case of a PHY power down to save power, or to turn off link during a
1919 1953 * driver unload, or wake on lan is not enabled, remove the link.
1920 1954 **/
1921 1955 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1922 1956 {
1923 1957 struct e1000_phy_info *phy = &hw->phy;
1924 1958
1925 1959 if (!(phy->ops.check_reset_block))
1926 1960 return;
1927 1961
1928 1962 /* If the management interface is not enabled, then power down */
1929 1963 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1930 1964 e1000_power_down_phy_copper(hw);
1931 1965
1932 1966 return;
1933 1967 }
1934 1968
1935 1969 /**
1936 1970 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1937 1971 * @hw: pointer to the HW structure
1938 1972 *
1939 1973 * Clears the hardware counters by reading the counter registers.
1940 1974 **/
1941 1975 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1942 1976 {
1943 1977 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1944 1978
1945 1979 e1000_clear_hw_cntrs_base_generic(hw);
1946 1980
1947 1981 E1000_READ_REG(hw, E1000_PRC64);
1948 1982 E1000_READ_REG(hw, E1000_PRC127);
1949 1983 E1000_READ_REG(hw, E1000_PRC255);
1950 1984 E1000_READ_REG(hw, E1000_PRC511);
1951 1985 E1000_READ_REG(hw, E1000_PRC1023);
1952 1986 E1000_READ_REG(hw, E1000_PRC1522);
1953 1987 E1000_READ_REG(hw, E1000_PTC64);
1954 1988 E1000_READ_REG(hw, E1000_PTC127);
1955 1989 E1000_READ_REG(hw, E1000_PTC255);
1956 1990 E1000_READ_REG(hw, E1000_PTC511);
1957 1991 E1000_READ_REG(hw, E1000_PTC1023);
1958 1992 E1000_READ_REG(hw, E1000_PTC1522);
1959 1993
1960 1994 E1000_READ_REG(hw, E1000_ALGNERRC);
1961 1995 E1000_READ_REG(hw, E1000_RXERRC);
1962 1996 E1000_READ_REG(hw, E1000_TNCRS);
1963 1997 E1000_READ_REG(hw, E1000_CEXTERR);
1964 1998 E1000_READ_REG(hw, E1000_TSCTC);
1965 1999 E1000_READ_REG(hw, E1000_TSCTFC);
1966 2000
1967 2001 E1000_READ_REG(hw, E1000_MGTPRC);
1968 2002 E1000_READ_REG(hw, E1000_MGTPDC);
1969 2003 E1000_READ_REG(hw, E1000_MGTPTC);
1970 2004
1971 2005 E1000_READ_REG(hw, E1000_IAC);
1972 2006 E1000_READ_REG(hw, E1000_ICRXOC);
1973 2007
1974 2008 E1000_READ_REG(hw, E1000_ICRXPTC);
1975 2009 E1000_READ_REG(hw, E1000_ICRXATC);
1976 2010 E1000_READ_REG(hw, E1000_ICTXPTC);
1977 2011 E1000_READ_REG(hw, E1000_ICTXATC);
1978 2012 E1000_READ_REG(hw, E1000_ICTXQEC);
1979 2013 E1000_READ_REG(hw, E1000_ICTXQMTC);
1980 2014 E1000_READ_REG(hw, E1000_ICRXDMTC);
1981 2015
1982 2016 E1000_READ_REG(hw, E1000_CBTMPC);
1983 2017 E1000_READ_REG(hw, E1000_HTDPMC);
1984 2018 E1000_READ_REG(hw, E1000_CBRMPC);
1985 2019 E1000_READ_REG(hw, E1000_RPTHC);
1986 2020 E1000_READ_REG(hw, E1000_HGPTC);
1987 2021 E1000_READ_REG(hw, E1000_HTCBDPC);
1988 2022 E1000_READ_REG(hw, E1000_HGORCL);
1989 2023 E1000_READ_REG(hw, E1000_HGORCH);
1990 2024 E1000_READ_REG(hw, E1000_HGOTCL);
1991 2025 E1000_READ_REG(hw, E1000_HGOTCH);
1992 2026 E1000_READ_REG(hw, E1000_LENERRS);
1993 2027
1994 2028 /* This register should not be read in copper configurations */
1995 2029 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1996 2030 e1000_sgmii_active_82575(hw))
1997 2031 E1000_READ_REG(hw, E1000_SCVPC);
1998 2032 }
1999 2033
2000 2034 /**
2001 2035 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2002 2036 * @hw: pointer to the HW structure
2003 2037 *
2004 2038 * After rx enable if managability is enabled then there is likely some
2005 2039 * bad data at the start of the fifo and possibly in the DMA fifo. This
2006 2040 * function clears the fifos and flushes any packets that came in as rx was
2007 2041 * being enabled.
2008 2042 **/
2009 2043 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2010 2044 {
2011 2045 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2012 2046 int i, ms_wait;
2013 2047
2014 2048 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2015 2049 if (hw->mac.type != e1000_82575 ||
2016 2050 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2017 2051 return;
2018 2052
2019 2053 /* Disable all Rx queues */
2020 2054 for (i = 0; i < 4; i++) {
2021 2055 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2022 2056 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2023 2057 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2024 2058 }
2025 2059 /* Poll all queues to verify they have shut down */
2026 2060 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2027 2061 msec_delay(1);
2028 2062 rx_enabled = 0;
2029 2063 for (i = 0; i < 4; i++)
2030 2064 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2031 2065 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2032 2066 break;
2033 2067 }
2034 2068
2035 2069 if (ms_wait == 10)
2036 2070 DEBUGOUT("Queue disable timed out after 10ms\n");
2037 2071
2038 2072 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2039 2073 * incoming packets are rejected. Set enable and wait 2ms so that
2040 2074 * any packet that was coming in as RCTL.EN was set is flushed
2041 2075 */
2042 2076 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2043 2077 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2044 2078
2045 2079 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2046 2080 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2047 2081
2048 2082 rctl = E1000_READ_REG(hw, E1000_RCTL);
2049 2083 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2050 2084 temp_rctl |= E1000_RCTL_LPE;
2051 2085
2052 2086 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2053 2087 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2054 2088 E1000_WRITE_FLUSH(hw);
2055 2089 msec_delay(2);
2056 2090
2057 2091 /* Enable Rx queues that were previously enabled and restore our
2058 2092 * previous state
2059 2093 */
2060 2094 for (i = 0; i < 4; i++)
2061 2095 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2062 2096 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2063 2097 E1000_WRITE_FLUSH(hw);
2064 2098
2065 2099 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2066 2100 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2067 2101
2068 2102 /* Flush receive errors generated by workaround */
2069 2103 E1000_READ_REG(hw, E1000_ROC);
2070 2104 E1000_READ_REG(hw, E1000_RNBC);
2071 2105 E1000_READ_REG(hw, E1000_MPC);
2072 2106 }
2073 2107
2074 2108 /**
2075 2109 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2076 2110 * @hw: pointer to the HW structure
2077 2111 *
2078 2112 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2079 2113 * however the hardware default for these parts is 500us to 1ms which is less
2080 2114 * than the 10ms recommended by the pci-e spec. To address this we need to
2081 2115 * increase the value to either 10ms to 200ms for capability version 1 config,
2082 2116 * or 16ms to 55ms for version 2.
2083 2117 **/
2084 2118 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2085 2119 {
2086 2120 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2087 2121 s32 ret_val = E1000_SUCCESS;
2088 2122 u16 pcie_devctl2;
2089 2123
2090 2124 /* only take action if timeout value is defaulted to 0 */
2091 2125 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2092 2126 goto out;
2093 2127
2094 2128 /*
2095 2129 * if capababilities version is type 1 we can write the
2096 2130 * timeout of 10ms to 200ms through the GCR register
2097 2131 */
2098 2132 if (!(gcr & E1000_GCR_CAP_VER2)) {
2099 2133 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2100 2134 goto out;
2101 2135 }
2102 2136
2103 2137 /*
2104 2138 * for version 2 capabilities we need to write the config space
2105 2139 * directly in order to set the completion timeout value for
2106 2140 * 16ms to 55ms
2107 2141 */
2108 2142 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2109 2143 &pcie_devctl2);
2110 2144 if (ret_val)
2111 2145 goto out;
2112 2146
2113 2147 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2114 2148
2115 2149 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2116 2150 &pcie_devctl2);
2117 2151 out:
2118 2152 /* disable completion timeout resend */
2119 2153 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2120 2154
2121 2155 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2122 2156 return ret_val;
2123 2157 }
2124 2158
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2125 2159 /**
2126 2160 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2127 2161 * @hw: pointer to the hardware struct
2128 2162 * @enable: state to enter, either enabled or disabled
2129 2163 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2130 2164 *
2131 2165 * enables/disables L2 switch anti-spoofing functionality.
2132 2166 **/
2133 2167 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2134 2168 {
2135 - u32 dtxswc;
2169 + u32 reg_val, reg_offset;
2136 2170
2137 2171 switch (hw->mac.type) {
2138 2172 case e1000_82576:
2139 - dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2140 - if (enable) {
2141 - dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2142 - E1000_DTXSWC_VLAN_SPOOF_MASK);
2143 - /* The PF can spoof - it has to in order to
2144 - * support emulation mode NICs */
2145 - dtxswc ^= (1 << pf | 1 << (pf +
2146 - E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2147 - } else {
2148 - dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2149 - E1000_DTXSWC_VLAN_SPOOF_MASK);
2150 - }
2151 - E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2173 + reg_offset = E1000_DTXSWC;
2152 2174 break;
2153 2175 case e1000_i350:
2154 - dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2155 - if (enable) {
2156 - dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2157 - E1000_DTXSWC_VLAN_SPOOF_MASK);
2158 - /* The PF can spoof - it has to in order to
2159 - * support emulation mode NICs
2160 - */
2161 - dtxswc ^= (1 << pf | 1 << (pf +
2162 - E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2163 - } else {
2164 - dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2165 - E1000_DTXSWC_VLAN_SPOOF_MASK);
2166 - }
2167 - E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2168 - default:
2176 + case e1000_i354:
2177 + reg_offset = E1000_TXSWC;
2169 2178 break;
2179 + default:
2180 + return;
2170 2181 }
2182 + reg_val = E1000_READ_REG(hw, reg_offset);
2183 + if (enable) {
2184 + reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2185 + E1000_DTXSWC_VLAN_SPOOF_MASK);
2186 + /* The PF can spoof - it has to in order to
2187 + * support emulation mode NICs
2188 + */
2189 + reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2190 + } else {
2191 + reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2192 + E1000_DTXSWC_VLAN_SPOOF_MASK);
2193 + }
2194 + E1000_WRITE_REG(hw, reg_offset, reg_val);
2171 2195 }
2172 2196
2173 2197 /**
2174 2198 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2175 2199 * @hw: pointer to the hardware struct
2176 2200 * @enable: state to enter, either enabled or disabled
2177 2201 *
2178 2202 * enables/disables L2 switch loopback functionality.
2179 2203 **/
2180 2204 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2181 2205 {
2182 2206 u32 dtxswc;
2183 2207
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2184 2208 switch (hw->mac.type) {
2185 2209 case e1000_82576:
2186 2210 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2187 2211 if (enable)
2188 2212 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2189 2213 else
2190 2214 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2191 2215 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2192 2216 break;
2193 2217 case e1000_i350:
2218 + case e1000_i354:
2194 2219 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2195 2220 if (enable)
2196 2221 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2197 2222 else
2198 2223 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2199 2224 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2200 2225 break;
2201 2226 default:
2202 2227 /* Currently no other hardware supports loopback */
2203 2228 break;
2204 2229 }
2205 2230
2206 2231
2207 2232 }
2208 2233
2209 2234 /**
2210 2235 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2211 2236 * @hw: pointer to the hardware struct
2212 2237 * @enable: state to enter, either enabled or disabled
2213 2238 *
2214 2239 * enables/disables replication of packets across multiple pools.
2215 2240 **/
2216 2241 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2217 2242 {
2218 2243 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2219 2244
2220 2245 if (enable)
2221 2246 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2222 2247 else
2223 2248 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2224 2249
2225 2250 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2226 2251 }
2227 2252
2228 2253 /**
2229 2254 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2230 2255 * @hw: pointer to the HW structure
2231 2256 * @offset: register offset to be read
2232 2257 * @data: pointer to the read data
2233 2258 *
2234 2259 * Reads the MDI control register in the PHY at offset and stores the
2235 2260 * information read to data.
2236 2261 **/
2237 2262 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2238 2263 {
2239 2264 s32 ret_val;
2240 2265
2241 2266 DEBUGFUNC("e1000_read_phy_reg_82580");
2242 2267
2243 2268 ret_val = hw->phy.ops.acquire(hw);
2244 2269 if (ret_val)
2245 2270 goto out;
2246 2271
2247 2272 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2248 2273
2249 2274 hw->phy.ops.release(hw);
2250 2275
2251 2276 out:
2252 2277 return ret_val;
2253 2278 }
2254 2279
2255 2280 /**
2256 2281 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2257 2282 * @hw: pointer to the HW structure
2258 2283 * @offset: register offset to write to
2259 2284 * @data: data to write to register at offset
2260 2285 *
2261 2286 * Writes data to MDI control register in the PHY at offset.
2262 2287 **/
2263 2288 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2264 2289 {
2265 2290 s32 ret_val;
2266 2291
2267 2292 DEBUGFUNC("e1000_write_phy_reg_82580");
2268 2293
2269 2294 ret_val = hw->phy.ops.acquire(hw);
2270 2295 if (ret_val)
2271 2296 goto out;
2272 2297
2273 2298 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2274 2299
2275 2300 hw->phy.ops.release(hw);
2276 2301
2277 2302 out:
2278 2303 return ret_val;
2279 2304 }
2280 2305
2281 2306 /**
2282 2307 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2283 2308 * @hw: pointer to the HW structure
2284 2309 *
2285 2310 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2286 2311 * the values found in the EEPROM. This addresses an issue in which these
2287 2312 * bits are not restored from EEPROM after reset.
2288 2313 **/
2289 2314 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2290 2315 {
2291 2316 s32 ret_val = E1000_SUCCESS;
2292 2317 u32 mdicnfg;
2293 2318 u16 nvm_data = 0;
2294 2319
2295 2320 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2296 2321
2297 2322 if (hw->mac.type != e1000_82580)
2298 2323 goto out;
2299 2324 if (!e1000_sgmii_active_82575(hw))
2300 2325 goto out;
2301 2326
2302 2327 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2303 2328 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2304 2329 &nvm_data);
2305 2330 if (ret_val) {
2306 2331 DEBUGOUT("NVM Read Error\n");
2307 2332 goto out;
2308 2333 }
2309 2334
2310 2335 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2311 2336 if (nvm_data & NVM_WORD24_EXT_MDIO)
2312 2337 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2313 2338 if (nvm_data & NVM_WORD24_COM_MDIO)
2314 2339 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2315 2340 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2316 2341 out:
2317 2342 return ret_val;
2318 2343 }
2319 2344
2320 2345 /**
2321 2346 * e1000_reset_hw_82580 - Reset hardware
2322 2347 * @hw: pointer to the HW structure
2323 2348 *
2324 2349 * This resets function or entire device (all ports, etc.)
2325 2350 * to a known state.
2326 2351 **/
2327 2352 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2328 2353 {
2329 2354 s32 ret_val = E1000_SUCCESS;
2330 2355 /* BH SW mailbox bit in SW_FW_SYNC */
2331 2356 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2332 2357 u32 ctrl;
2333 2358 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2334 2359
2335 2360 DEBUGFUNC("e1000_reset_hw_82580");
2336 2361
2337 2362 hw->dev_spec._82575.global_device_reset = FALSE;
2338 2363
2339 2364 /* 82580 does not reliably do global_device_reset due to hw errata */
2340 2365 if (hw->mac.type == e1000_82580)
2341 2366 global_device_reset = FALSE;
2342 2367
2343 2368 /* Get current control state. */
2344 2369 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2345 2370
2346 2371 /*
2347 2372 * Prevent the PCI-E bus from sticking if there is no TLP connection
2348 2373 * on the last TLP read/write transaction when MAC is reset.
2349 2374 */
2350 2375 ret_val = e1000_disable_pcie_master_generic(hw);
2351 2376 if (ret_val)
2352 2377 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2353 2378
2354 2379 DEBUGOUT("Masking off all interrupts\n");
2355 2380 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2356 2381 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2357 2382 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2358 2383 E1000_WRITE_FLUSH(hw);
2359 2384
2360 2385 msec_delay(10);
2361 2386
2362 2387 /* Determine whether or not a global dev reset is requested */
2363 2388 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2364 2389 swmbsw_mask))
2365 2390 global_device_reset = FALSE;
2366 2391
2367 2392 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2368 2393 E1000_STAT_DEV_RST_SET))
2369 2394 ctrl |= E1000_CTRL_DEV_RST;
2370 2395 else
2371 2396 ctrl |= E1000_CTRL_RST;
2372 2397
2373 2398 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2374 2399 E1000_WRITE_FLUSH(hw);
2375 2400
2376 2401 /* Add delay to insure DEV_RST has time to complete */
2377 2402 if (global_device_reset)
2378 2403 msec_delay(5);
2379 2404
2380 2405 ret_val = e1000_get_auto_rd_done_generic(hw);
2381 2406 if (ret_val) {
2382 2407 /*
2383 2408 * When auto config read does not complete, do not
2384 2409 * return with an error. This can happen in situations
2385 2410 * where there is no eeprom and prevents getting link.
2386 2411 */
2387 2412 DEBUGOUT("Auto Read Done did not complete\n");
2388 2413 }
2389 2414
2390 2415 /* If EEPROM is not present, run manual init scripts */
2391 2416 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
2392 2417 e1000_reset_init_script_82575(hw);
2393 2418
2394 2419 /* clear global device reset status bit */
2395 2420 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2396 2421
2397 2422 /* Clear any pending interrupt events. */
2398 2423 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2399 2424 E1000_READ_REG(hw, E1000_ICR);
2400 2425
2401 2426 ret_val = e1000_reset_mdicnfg_82580(hw);
2402 2427 if (ret_val)
2403 2428 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2404 2429
2405 2430 /* Install any alternate MAC address into RAR0 */
2406 2431 ret_val = e1000_check_alt_mac_addr_generic(hw);
2407 2432
2408 2433 /* Release semaphore */
2409 2434 if (global_device_reset)
2410 2435 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2411 2436
2412 2437 return ret_val;
2413 2438 }
2414 2439
2415 2440 /**
2416 2441 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2417 2442 * @data: data received by reading RXPBS register
2418 2443 *
2419 2444 * The 82580 uses a table based approach for packet buffer allocation sizes.
2420 2445 * This function converts the retrieved value into the correct table value
2421 2446 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2422 2447 * 0x0 36 72 144 1 2 4 8 16
2423 2448 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2424 2449 */
2425 2450 u16 e1000_rxpbs_adjust_82580(u32 data)
2426 2451 {
2427 2452 u16 ret_val = 0;
2428 2453
2429 2454 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2430 2455 ret_val = e1000_82580_rxpbs_table[data];
2431 2456
2432 2457 return ret_val;
2433 2458 }
2434 2459
2435 2460 /**
2436 2461 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2437 2462 * checksum
2438 2463 * @hw: pointer to the HW structure
2439 2464 * @offset: offset in words of the checksum protected region
2440 2465 *
2441 2466 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2442 2467 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2443 2468 **/
2444 2469 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2445 2470 {
2446 2471 s32 ret_val = E1000_SUCCESS;
2447 2472 u16 checksum = 0;
2448 2473 u16 i, nvm_data;
2449 2474
2450 2475 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2451 2476
2452 2477 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2453 2478 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2454 2479 if (ret_val) {
2455 2480 DEBUGOUT("NVM Read Error\n");
2456 2481 goto out;
2457 2482 }
2458 2483 checksum += nvm_data;
2459 2484 }
2460 2485
2461 2486 if (checksum != (u16) NVM_SUM) {
2462 2487 DEBUGOUT("NVM Checksum Invalid\n");
2463 2488 ret_val = -E1000_ERR_NVM;
2464 2489 goto out;
2465 2490 }
2466 2491
2467 2492 out:
2468 2493 return ret_val;
2469 2494 }
2470 2495
2471 2496 /**
2472 2497 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2473 2498 * checksum
2474 2499 * @hw: pointer to the HW structure
2475 2500 * @offset: offset in words of the checksum protected region
2476 2501 *
2477 2502 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2478 2503 * up to the checksum. Then calculates the EEPROM checksum and writes the
2479 2504 * value to the EEPROM.
2480 2505 **/
2481 2506 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2482 2507 {
2483 2508 s32 ret_val;
2484 2509 u16 checksum = 0;
2485 2510 u16 i, nvm_data;
2486 2511
2487 2512 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2488 2513
2489 2514 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2490 2515 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2491 2516 if (ret_val) {
2492 2517 DEBUGOUT("NVM Read Error while updating checksum.\n");
2493 2518 goto out;
2494 2519 }
2495 2520 checksum += nvm_data;
2496 2521 }
2497 2522 checksum = (u16) NVM_SUM - checksum;
2498 2523 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2499 2524 &checksum);
2500 2525 if (ret_val)
2501 2526 DEBUGOUT("NVM Write Error while updating checksum.\n");
2502 2527
2503 2528 out:
2504 2529 return ret_val;
2505 2530 }
2506 2531
2507 2532 /**
2508 2533 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2509 2534 * @hw: pointer to the HW structure
2510 2535 *
2511 2536 * Calculates the EEPROM section checksum by reading/adding each word of
2512 2537 * the EEPROM and then verifies that the sum of the EEPROM is
2513 2538 * equal to 0xBABA.
2514 2539 **/
2515 2540 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2516 2541 {
2517 2542 s32 ret_val = E1000_SUCCESS;
2518 2543 u16 eeprom_regions_count = 1;
2519 2544 u16 j, nvm_data;
2520 2545 u16 nvm_offset;
2521 2546
2522 2547 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2523 2548
2524 2549 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2525 2550 if (ret_val) {
2526 2551 DEBUGOUT("NVM Read Error\n");
2527 2552 goto out;
2528 2553 }
2529 2554
2530 2555 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2531 2556 /* if chekcsums compatibility bit is set validate checksums
2532 2557 * for all 4 ports. */
2533 2558 eeprom_regions_count = 4;
2534 2559 }
2535 2560
2536 2561 for (j = 0; j < eeprom_regions_count; j++) {
2537 2562 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2538 2563 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2539 2564 nvm_offset);
2540 2565 if (ret_val != E1000_SUCCESS)
2541 2566 goto out;
2542 2567 }
2543 2568
2544 2569 out:
2545 2570 return ret_val;
2546 2571 }
2547 2572
2548 2573 /**
2549 2574 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2550 2575 * @hw: pointer to the HW structure
2551 2576 *
2552 2577 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2553 2578 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2554 2579 * checksum and writes the value to the EEPROM.
2555 2580 **/
2556 2581 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2557 2582 {
2558 2583 s32 ret_val;
2559 2584 u16 j, nvm_data;
2560 2585 u16 nvm_offset;
2561 2586
2562 2587 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2563 2588
2564 2589 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2565 2590 if (ret_val) {
2566 2591 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2567 2592 goto out;
2568 2593 }
2569 2594
2570 2595 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2571 2596 /* set compatibility bit to validate checksums appropriately */
2572 2597 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2573 2598 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2574 2599 &nvm_data);
2575 2600 if (ret_val) {
2576 2601 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2577 2602 goto out;
2578 2603 }
2579 2604 }
2580 2605
2581 2606 for (j = 0; j < 4; j++) {
2582 2607 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2583 2608 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2584 2609 if (ret_val)
2585 2610 goto out;
2586 2611 }
2587 2612
2588 2613 out:
2589 2614 return ret_val;
2590 2615 }
2591 2616
2592 2617 /**
2593 2618 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2594 2619 * @hw: pointer to the HW structure
2595 2620 *
2596 2621 * Calculates the EEPROM section checksum by reading/adding each word of
2597 2622 * the EEPROM and then verifies that the sum of the EEPROM is
2598 2623 * equal to 0xBABA.
2599 2624 **/
2600 2625 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2601 2626 {
2602 2627 s32 ret_val = E1000_SUCCESS;
2603 2628 u16 j;
2604 2629 u16 nvm_offset;
2605 2630
2606 2631 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2607 2632
2608 2633 for (j = 0; j < 4; j++) {
2609 2634 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2610 2635 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2611 2636 nvm_offset);
2612 2637 if (ret_val != E1000_SUCCESS)
2613 2638 goto out;
2614 2639 }
2615 2640
2616 2641 out:
2617 2642 return ret_val;
2618 2643 }
2619 2644
2620 2645 /**
2621 2646 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2622 2647 * @hw: pointer to the HW structure
2623 2648 *
2624 2649 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2625 2650 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2626 2651 * checksum and writes the value to the EEPROM.
2627 2652 **/
2628 2653 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2629 2654 {
2630 2655 s32 ret_val = E1000_SUCCESS;
2631 2656 u16 j;
2632 2657 u16 nvm_offset;
2633 2658
2634 2659 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2635 2660
2636 2661 for (j = 0; j < 4; j++) {
2637 2662 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2638 2663 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2639 2664 if (ret_val != E1000_SUCCESS)
2640 2665 goto out;
2641 2666 }
2642 2667
2643 2668 out:
2644 2669 return ret_val;
2645 2670 }
2646 2671
2647 2672 /**
2648 2673 * e1000_set_eee_i350 - Enable/disable EEE support
2649 2674 * @hw: pointer to the HW structure
2650 2675 *
2651 2676 * Enable/disable EEE based on setting in dev_spec structure.
2652 2677 *
2653 2678 **/
2654 2679 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2655 2680 {
2656 2681 s32 ret_val = E1000_SUCCESS;
2657 2682 u32 ipcnfg, eeer;
2658 2683
2659 2684 DEBUGFUNC("e1000_set_eee_i350");
2660 2685
2661 2686 if ((hw->mac.type < e1000_i350) ||
2662 2687 (hw->phy.media_type != e1000_media_type_copper))
2663 2688 goto out;
2664 2689 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2665 2690 eeer = E1000_READ_REG(hw, E1000_EEER);
2666 2691
2667 2692 /* enable or disable per user setting */
2668 2693 if (!(hw->dev_spec._82575.eee_disable)) {
2669 2694 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2670 2695
2671 2696 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2672 2697 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2673 2698 E1000_EEER_LPI_FC);
2674 2699
2675 2700 /* This bit should not be set in normal operation. */
2676 2701 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2677 2702 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2678 2703 } else {
2679 2704 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2680 2705 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
|
↓ open down ↓ |
477 lines elided |
↑ open up ↑ |
2681 2706 E1000_EEER_LPI_FC);
2682 2707 }
2683 2708 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2684 2709 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2685 2710 E1000_READ_REG(hw, E1000_IPCNFG);
2686 2711 E1000_READ_REG(hw, E1000_EEER);
2687 2712 out:
2688 2713
2689 2714 return ret_val;
2690 2715 }
2716 +
2717 +/**
2718 + * e1000_set_eee_i354 - Enable/disable EEE support
2719 + * @hw: pointer to the HW structure
2720 + *
2721 + * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2722 + *
2723 + **/
2724 +s32 e1000_set_eee_i354(struct e1000_hw *hw)
2725 +{
2726 + struct e1000_phy_info *phy = &hw->phy;
2727 + s32 ret_val = E1000_SUCCESS;
2728 + u16 phy_data;
2729 +
2730 + DEBUGFUNC("e1000_set_eee_i354");
2731 +
2732 + if ((hw->phy.media_type != e1000_media_type_copper) ||
2733 + ((phy->id != M88E1543_E_PHY_ID) &&
2734 + (phy->id != M88E1512_E_PHY_ID)))
2735 + goto out;
2736 +
2737 + if (!hw->dev_spec._82575.eee_disable) {
2738 + /* Switch to PHY page 18. */
2739 + ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2740 + if (ret_val)
2741 + goto out;
2742 +
2743 + ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2744 + &phy_data);
2745 + if (ret_val)
2746 + goto out;
2747 +
2748 + phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2749 + ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2750 + phy_data);
2751 + if (ret_val)
2752 + goto out;
2753 +
2754 + /* Return the PHY to page 0. */
2755 + ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2756 + if (ret_val)
2757 + goto out;
2758 +
2759 + /* Turn on EEE advertisement. */
2760 + ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2761 + E1000_EEE_ADV_DEV_I354,
2762 + &phy_data);
2763 + if (ret_val)
2764 + goto out;
2765 +
2766 + phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2767 + E1000_EEE_ADV_1000_SUPPORTED;
2768 + ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2769 + E1000_EEE_ADV_DEV_I354,
2770 + phy_data);
2771 + } else {
2772 + /* Turn off EEE advertisement. */
2773 + ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2774 + E1000_EEE_ADV_DEV_I354,
2775 + &phy_data);
2776 + if (ret_val)
2777 + goto out;
2778 +
2779 + phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2780 + E1000_EEE_ADV_1000_SUPPORTED);
2781 + ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2782 + E1000_EEE_ADV_DEV_I354,
2783 + phy_data);
2784 + }
2785 +
2786 +out:
2787 + return ret_val;
2788 +}
2789 +
2790 +/**
2791 + * e1000_get_eee_status_i354 - Get EEE status
2792 + * @hw: pointer to the HW structure
2793 + * @status: EEE status
2794 + *
2795 + * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2796 + * been received.
2797 + **/
2798 +s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2799 +{
2800 + struct e1000_phy_info *phy = &hw->phy;
2801 + s32 ret_val = E1000_SUCCESS;
2802 + u16 phy_data;
2803 +
2804 + DEBUGFUNC("e1000_get_eee_status_i354");
2805 +
2806 + /* Check if EEE is supported on this device. */
2807 + if ((hw->phy.media_type != e1000_media_type_copper) ||
2808 + ((phy->id != M88E1543_E_PHY_ID) &&
2809 + (phy->id != M88E1512_E_PHY_ID)))
2810 + goto out;
2811 +
2812 + ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2813 + E1000_PCS_STATUS_DEV_I354,
2814 + &phy_data);
2815 + if (ret_val)
2816 + goto out;
2817 +
2818 + *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2819 + E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE;
2820 +
2821 +out:
2822 + return ret_val;
2823 +}
2691 2824
2692 2825 /* Due to a hw errata, if the host tries to configure the VFTA register
2693 2826 * while performing queries from the BMC or DMA, then the VFTA in some
2694 2827 * cases won't be written.
2695 2828 */
2696 2829
2697 2830 /**
2698 2831 * e1000_clear_vfta_i350 - Clear VLAN filter table
2699 2832 * @hw: pointer to the HW structure
2700 2833 *
2701 2834 * Clears the register array which contains the VLAN filter table by
2702 2835 * setting all the values to 0.
2703 2836 **/
2704 2837 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2705 2838 {
2706 2839 u32 offset;
2707 2840 int i;
2708 2841
2709 2842 DEBUGFUNC("e1000_clear_vfta_350");
2710 2843
2711 2844 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2712 2845 for (i = 0; i < 10; i++)
2713 2846 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2714 2847
2715 2848 E1000_WRITE_FLUSH(hw);
2716 2849 }
2717 2850 }
2718 2851
2719 2852 /**
2720 2853 * e1000_write_vfta_i350 - Write value to VLAN filter table
2721 2854 * @hw: pointer to the HW structure
2722 2855 * @offset: register offset in VLAN filter table
2723 2856 * @value: register value written to VLAN filter table
2724 2857 *
2725 2858 * Writes value at the given offset in the register array which stores
2726 2859 * the VLAN filter table.
2727 2860 **/
2728 2861 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2729 2862 {
2730 2863 int i;
2731 2864
2732 2865 DEBUGFUNC("e1000_write_vfta_350");
2733 2866
2734 2867 for (i = 0; i < 10; i++)
2735 2868 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2736 2869
2737 2870 E1000_WRITE_FLUSH(hw);
2738 2871 }
2739 2872
2740 2873
2741 2874 /**
2742 2875 * e1000_set_i2c_bb - Enable I2C bit-bang
2743 2876 * @hw: pointer to the HW structure
2744 2877 *
2745 2878 * Enable I2C bit-bang interface
2746 2879 *
2747 2880 **/
2748 2881 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2749 2882 {
2750 2883 s32 ret_val = E1000_SUCCESS;
2751 2884 u32 ctrl_ext, i2cparams;
2752 2885
2753 2886 DEBUGFUNC("e1000_set_i2c_bb");
2754 2887
2755 2888 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2756 2889 ctrl_ext |= E1000_CTRL_I2C_ENA;
2757 2890 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2758 2891 E1000_WRITE_FLUSH(hw);
2759 2892
2760 2893 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
2761 2894 i2cparams |= E1000_I2CBB_EN;
2762 2895 i2cparams |= E1000_I2C_DATA_OE_N;
2763 2896 i2cparams |= E1000_I2C_CLK_OE_N;
2764 2897 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
2765 2898 E1000_WRITE_FLUSH(hw);
2766 2899
2767 2900 return ret_val;
2768 2901 }
2769 2902
2770 2903 /**
2771 2904 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2772 2905 * @hw: pointer to hardware structure
2773 2906 * @byte_offset: byte offset to read
2774 2907 * @dev_addr: device address
2775 2908 * @data: value read
2776 2909 *
2777 2910 * Performs byte read operation over I2C interface at
2778 2911 * a specified device address.
2779 2912 **/
2780 2913 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2781 2914 u8 dev_addr, u8 *data)
2782 2915 {
2783 2916 s32 status = E1000_SUCCESS;
2784 2917 u32 max_retry = 10;
2785 2918 u32 retry = 1;
2786 2919 u16 swfw_mask = 0;
2787 2920
2788 2921 bool nack = TRUE;
2789 2922
2790 2923 DEBUGFUNC("e1000_read_i2c_byte_generic");
2791 2924
2792 2925 swfw_mask = E1000_SWFW_PHY0_SM;
2793 2926
2794 2927 do {
2795 2928 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
2796 2929 != E1000_SUCCESS) {
2797 2930 status = E1000_ERR_SWFW_SYNC;
2798 2931 goto read_byte_out;
2799 2932 }
2800 2933
2801 2934 e1000_i2c_start(hw);
2802 2935
2803 2936 /* Device Address and write indication */
2804 2937 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2805 2938 if (status != E1000_SUCCESS)
2806 2939 goto fail;
2807 2940
2808 2941 status = e1000_get_i2c_ack(hw);
2809 2942 if (status != E1000_SUCCESS)
2810 2943 goto fail;
2811 2944
2812 2945 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2813 2946 if (status != E1000_SUCCESS)
2814 2947 goto fail;
2815 2948
2816 2949 status = e1000_get_i2c_ack(hw);
2817 2950 if (status != E1000_SUCCESS)
2818 2951 goto fail;
2819 2952
2820 2953 e1000_i2c_start(hw);
2821 2954
2822 2955 /* Device Address and read indication */
2823 2956 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2824 2957 if (status != E1000_SUCCESS)
2825 2958 goto fail;
2826 2959
2827 2960 status = e1000_get_i2c_ack(hw);
2828 2961 if (status != E1000_SUCCESS)
2829 2962 goto fail;
2830 2963
2831 2964 status = e1000_clock_in_i2c_byte(hw, data);
2832 2965 if (status != E1000_SUCCESS)
2833 2966 goto fail;
2834 2967
2835 2968 status = e1000_clock_out_i2c_bit(hw, nack);
2836 2969 if (status != E1000_SUCCESS)
2837 2970 goto fail;
2838 2971
2839 2972 e1000_i2c_stop(hw);
2840 2973 break;
2841 2974
2842 2975 fail:
2843 2976 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2844 2977 msec_delay(100);
2845 2978 e1000_i2c_bus_clear(hw);
2846 2979 retry++;
2847 2980 if (retry < max_retry)
2848 2981 DEBUGOUT("I2C byte read error - Retrying.\n");
2849 2982 else
2850 2983 DEBUGOUT("I2C byte read error.\n");
2851 2984
2852 2985 } while (retry < max_retry);
2853 2986
2854 2987 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2855 2988
2856 2989 read_byte_out:
2857 2990
2858 2991 return status;
2859 2992 }
2860 2993
2861 2994 /**
2862 2995 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
2863 2996 * @hw: pointer to hardware structure
2864 2997 * @byte_offset: byte offset to write
2865 2998 * @dev_addr: device address
2866 2999 * @data: value to write
2867 3000 *
2868 3001 * Performs byte write operation over I2C interface at
2869 3002 * a specified device address.
2870 3003 **/
2871 3004 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2872 3005 u8 dev_addr, u8 data)
2873 3006 {
2874 3007 s32 status = E1000_SUCCESS;
2875 3008 u32 max_retry = 1;
2876 3009 u32 retry = 0;
2877 3010 u16 swfw_mask = 0;
2878 3011
2879 3012 DEBUGFUNC("e1000_write_i2c_byte_generic");
2880 3013
2881 3014 swfw_mask = E1000_SWFW_PHY0_SM;
2882 3015
2883 3016 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
2884 3017 status = E1000_ERR_SWFW_SYNC;
2885 3018 goto write_byte_out;
2886 3019 }
2887 3020
2888 3021 do {
2889 3022 e1000_i2c_start(hw);
2890 3023
2891 3024 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2892 3025 if (status != E1000_SUCCESS)
2893 3026 goto fail;
2894 3027
2895 3028 status = e1000_get_i2c_ack(hw);
2896 3029 if (status != E1000_SUCCESS)
2897 3030 goto fail;
2898 3031
2899 3032 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2900 3033 if (status != E1000_SUCCESS)
2901 3034 goto fail;
2902 3035
2903 3036 status = e1000_get_i2c_ack(hw);
2904 3037 if (status != E1000_SUCCESS)
2905 3038 goto fail;
2906 3039
2907 3040 status = e1000_clock_out_i2c_byte(hw, data);
2908 3041 if (status != E1000_SUCCESS)
2909 3042 goto fail;
2910 3043
2911 3044 status = e1000_get_i2c_ack(hw);
2912 3045 if (status != E1000_SUCCESS)
2913 3046 goto fail;
2914 3047
2915 3048 e1000_i2c_stop(hw);
2916 3049 break;
2917 3050
2918 3051 fail:
2919 3052 e1000_i2c_bus_clear(hw);
2920 3053 retry++;
2921 3054 if (retry < max_retry)
2922 3055 DEBUGOUT("I2C byte write error - Retrying.\n");
2923 3056 else
2924 3057 DEBUGOUT("I2C byte write error.\n");
2925 3058 } while (retry < max_retry);
2926 3059
2927 3060 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2928 3061
2929 3062 write_byte_out:
2930 3063
2931 3064 return status;
2932 3065 }
2933 3066
2934 3067 /**
2935 3068 * e1000_i2c_start - Sets I2C start condition
2936 3069 * @hw: pointer to hardware structure
2937 3070 *
2938 3071 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2939 3072 **/
2940 3073 static void e1000_i2c_start(struct e1000_hw *hw)
2941 3074 {
2942 3075 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2943 3076
2944 3077 DEBUGFUNC("e1000_i2c_start");
2945 3078
2946 3079 /* Start condition must begin with data and clock high */
2947 3080 e1000_set_i2c_data(hw, &i2cctl, 1);
2948 3081 e1000_raise_i2c_clk(hw, &i2cctl);
2949 3082
2950 3083 /* Setup time for start condition (4.7us) */
2951 3084 usec_delay(E1000_I2C_T_SU_STA);
2952 3085
2953 3086 e1000_set_i2c_data(hw, &i2cctl, 0);
2954 3087
2955 3088 /* Hold time for start condition (4us) */
2956 3089 usec_delay(E1000_I2C_T_HD_STA);
2957 3090
2958 3091 e1000_lower_i2c_clk(hw, &i2cctl);
2959 3092
2960 3093 /* Minimum low period of clock is 4.7 us */
2961 3094 usec_delay(E1000_I2C_T_LOW);
2962 3095
2963 3096 }
2964 3097
2965 3098 /**
2966 3099 * e1000_i2c_stop - Sets I2C stop condition
2967 3100 * @hw: pointer to hardware structure
2968 3101 *
2969 3102 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2970 3103 **/
2971 3104 static void e1000_i2c_stop(struct e1000_hw *hw)
2972 3105 {
2973 3106 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2974 3107
2975 3108 DEBUGFUNC("e1000_i2c_stop");
2976 3109
2977 3110 /* Stop condition must begin with data low and clock high */
2978 3111 e1000_set_i2c_data(hw, &i2cctl, 0);
2979 3112 e1000_raise_i2c_clk(hw, &i2cctl);
2980 3113
2981 3114 /* Setup time for stop condition (4us) */
2982 3115 usec_delay(E1000_I2C_T_SU_STO);
2983 3116
2984 3117 e1000_set_i2c_data(hw, &i2cctl, 1);
2985 3118
2986 3119 /* bus free time between stop and start (4.7us)*/
2987 3120 usec_delay(E1000_I2C_T_BUF);
2988 3121 }
2989 3122
2990 3123 /**
2991 3124 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
2992 3125 * @hw: pointer to hardware structure
2993 3126 * @data: data byte to clock in
2994 3127 *
2995 3128 * Clocks in one byte data via I2C data/clock
2996 3129 **/
2997 3130 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
2998 3131 {
2999 3132 s32 i;
3000 3133 bool bit = 0;
3001 3134
3002 3135 DEBUGFUNC("e1000_clock_in_i2c_byte");
3003 3136
3004 3137 *data = 0;
3005 3138 for (i = 7; i >= 0; i--) {
3006 3139 e1000_clock_in_i2c_bit(hw, &bit);
3007 3140 *data |= bit << i;
3008 3141 }
3009 3142
3010 3143 return E1000_SUCCESS;
3011 3144 }
3012 3145
3013 3146 /**
3014 3147 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3015 3148 * @hw: pointer to hardware structure
3016 3149 * @data: data byte clocked out
3017 3150 *
3018 3151 * Clocks out one byte data via I2C data/clock
3019 3152 **/
3020 3153 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3021 3154 {
3022 3155 s32 status = E1000_SUCCESS;
3023 3156 s32 i;
3024 3157 u32 i2cctl;
3025 3158 bool bit = 0;
3026 3159
3027 3160 DEBUGFUNC("e1000_clock_out_i2c_byte");
3028 3161
3029 3162 for (i = 7; i >= 0; i--) {
3030 3163 bit = (data >> i) & 0x1;
3031 3164 status = e1000_clock_out_i2c_bit(hw, bit);
3032 3165
3033 3166 if (status != E1000_SUCCESS)
3034 3167 break;
3035 3168 }
3036 3169
3037 3170 /* Release SDA line (set high) */
3038 3171 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3039 3172
3040 3173 i2cctl |= E1000_I2C_DATA_OE_N;
3041 3174 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3042 3175 E1000_WRITE_FLUSH(hw);
3043 3176
3044 3177 return status;
3045 3178 }
3046 3179
3047 3180 /**
3048 3181 * e1000_get_i2c_ack - Polls for I2C ACK
3049 3182 * @hw: pointer to hardware structure
3050 3183 *
3051 3184 * Clocks in/out one bit via I2C data/clock
3052 3185 **/
3053 3186 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3054 3187 {
3055 3188 s32 status = E1000_SUCCESS;
3056 3189 u32 i = 0;
3057 3190 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3058 3191 u32 timeout = 10;
3059 3192 bool ack = TRUE;
3060 3193
3061 3194 DEBUGFUNC("e1000_get_i2c_ack");
3062 3195
3063 3196 e1000_raise_i2c_clk(hw, &i2cctl);
3064 3197
3065 3198 /* Minimum high period of clock is 4us */
3066 3199 usec_delay(E1000_I2C_T_HIGH);
3067 3200
3068 3201 /* Wait until SCL returns high */
3069 3202 for (i = 0; i < timeout; i++) {
3070 3203 usec_delay(1);
3071 3204 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3072 3205 if (i2cctl & E1000_I2C_CLK_IN)
3073 3206 break;
3074 3207 }
3075 3208 if (!(i2cctl & E1000_I2C_CLK_IN))
3076 3209 return E1000_ERR_I2C;
3077 3210
3078 3211 ack = e1000_get_i2c_data(&i2cctl);
3079 3212 if (ack) {
3080 3213 DEBUGOUT("I2C ack was not received.\n");
3081 3214 status = E1000_ERR_I2C;
3082 3215 }
3083 3216
3084 3217 e1000_lower_i2c_clk(hw, &i2cctl);
3085 3218
3086 3219 /* Minimum low period of clock is 4.7 us */
3087 3220 usec_delay(E1000_I2C_T_LOW);
3088 3221
3089 3222 return status;
3090 3223 }
3091 3224
3092 3225 /**
3093 3226 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3094 3227 * @hw: pointer to hardware structure
3095 3228 * @data: read data value
3096 3229 *
3097 3230 * Clocks in one bit via I2C data/clock
3098 3231 **/
3099 3232 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3100 3233 {
3101 3234 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3102 3235
3103 3236 DEBUGFUNC("e1000_clock_in_i2c_bit");
3104 3237
3105 3238 e1000_raise_i2c_clk(hw, &i2cctl);
3106 3239
3107 3240 /* Minimum high period of clock is 4us */
3108 3241 usec_delay(E1000_I2C_T_HIGH);
3109 3242
3110 3243 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3111 3244 *data = e1000_get_i2c_data(&i2cctl);
3112 3245
3113 3246 e1000_lower_i2c_clk(hw, &i2cctl);
3114 3247
3115 3248 /* Minimum low period of clock is 4.7 us */
3116 3249 usec_delay(E1000_I2C_T_LOW);
3117 3250
3118 3251 return E1000_SUCCESS;
3119 3252 }
3120 3253
3121 3254 /**
3122 3255 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3123 3256 * @hw: pointer to hardware structure
3124 3257 * @data: data value to write
3125 3258 *
3126 3259 * Clocks out one bit via I2C data/clock
3127 3260 **/
3128 3261 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3129 3262 {
3130 3263 s32 status;
3131 3264 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3132 3265
3133 3266 DEBUGFUNC("e1000_clock_out_i2c_bit");
3134 3267
3135 3268 status = e1000_set_i2c_data(hw, &i2cctl, data);
3136 3269 if (status == E1000_SUCCESS) {
3137 3270 e1000_raise_i2c_clk(hw, &i2cctl);
3138 3271
3139 3272 /* Minimum high period of clock is 4us */
3140 3273 usec_delay(E1000_I2C_T_HIGH);
3141 3274
3142 3275 e1000_lower_i2c_clk(hw, &i2cctl);
3143 3276
3144 3277 /* Minimum low period of clock is 4.7 us.
3145 3278 * This also takes care of the data hold time.
3146 3279 */
3147 3280 usec_delay(E1000_I2C_T_LOW);
3148 3281 } else {
3149 3282 status = E1000_ERR_I2C;
3150 3283 DEBUGOUT1("I2C data was not set to %X\n", data);
3151 3284 }
3152 3285
3153 3286 return status;
3154 3287 }
3155 3288 /**
3156 3289 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3157 3290 * @hw: pointer to hardware structure
3158 3291 * @i2cctl: Current value of I2CCTL register
3159 3292 *
3160 3293 * Raises the I2C clock line '0'->'1'
3161 3294 **/
3162 3295 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3163 3296 {
3164 3297 DEBUGFUNC("e1000_raise_i2c_clk");
3165 3298
3166 3299 *i2cctl |= E1000_I2C_CLK_OUT;
3167 3300 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3168 3301 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3169 3302 E1000_WRITE_FLUSH(hw);
3170 3303
3171 3304 /* SCL rise time (1000ns) */
3172 3305 usec_delay(E1000_I2C_T_RISE);
3173 3306 }
3174 3307
3175 3308 /**
3176 3309 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3177 3310 * @hw: pointer to hardware structure
3178 3311 * @i2cctl: Current value of I2CCTL register
3179 3312 *
3180 3313 * Lowers the I2C clock line '1'->'0'
3181 3314 **/
3182 3315 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3183 3316 {
3184 3317
3185 3318 DEBUGFUNC("e1000_lower_i2c_clk");
3186 3319
3187 3320 *i2cctl &= ~E1000_I2C_CLK_OUT;
3188 3321 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3189 3322 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3190 3323 E1000_WRITE_FLUSH(hw);
3191 3324
3192 3325 /* SCL fall time (300ns) */
3193 3326 usec_delay(E1000_I2C_T_FALL);
3194 3327 }
3195 3328
3196 3329 /**
3197 3330 * e1000_set_i2c_data - Sets the I2C data bit
3198 3331 * @hw: pointer to hardware structure
3199 3332 * @i2cctl: Current value of I2CCTL register
3200 3333 * @data: I2C data value (0 or 1) to set
3201 3334 *
3202 3335 * Sets the I2C data bit
3203 3336 **/
3204 3337 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3205 3338 {
3206 3339 s32 status = E1000_SUCCESS;
3207 3340
3208 3341 DEBUGFUNC("e1000_set_i2c_data");
3209 3342
3210 3343 if (data)
3211 3344 *i2cctl |= E1000_I2C_DATA_OUT;
3212 3345 else
3213 3346 *i2cctl &= ~E1000_I2C_DATA_OUT;
3214 3347
3215 3348 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3216 3349 *i2cctl |= E1000_I2C_CLK_OE_N;
3217 3350 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3218 3351 E1000_WRITE_FLUSH(hw);
3219 3352
3220 3353 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3221 3354 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3222 3355
3223 3356 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3224 3357 if (data != e1000_get_i2c_data(i2cctl)) {
3225 3358 status = E1000_ERR_I2C;
3226 3359 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3227 3360 }
3228 3361
3229 3362 return status;
3230 3363 }
3231 3364
3232 3365 /**
3233 3366 * e1000_get_i2c_data - Reads the I2C SDA data bit
3234 3367 * @hw: pointer to hardware structure
3235 3368 * @i2cctl: Current value of I2CCTL register
3236 3369 *
3237 3370 * Returns the I2C data bit value
3238 3371 **/
3239 3372 static bool e1000_get_i2c_data(u32 *i2cctl)
3240 3373 {
3241 3374 bool data;
3242 3375
3243 3376 DEBUGFUNC("e1000_get_i2c_data");
3244 3377
3245 3378 if (*i2cctl & E1000_I2C_DATA_IN)
3246 3379 data = 1;
3247 3380 else
3248 3381 data = 0;
3249 3382
3250 3383 return data;
3251 3384 }
3252 3385
3253 3386 /**
3254 3387 * e1000_i2c_bus_clear - Clears the I2C bus
3255 3388 * @hw: pointer to hardware structure
3256 3389 *
3257 3390 * Clears the I2C bus by sending nine clock pulses.
3258 3391 * Used when data line is stuck low.
3259 3392 **/
3260 3393 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3261 3394 {
3262 3395 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3263 3396 u32 i;
3264 3397
3265 3398 DEBUGFUNC("e1000_i2c_bus_clear");
3266 3399
3267 3400 e1000_i2c_start(hw);
3268 3401
3269 3402 e1000_set_i2c_data(hw, &i2cctl, 1);
3270 3403
3271 3404 for (i = 0; i < 9; i++) {
3272 3405 e1000_raise_i2c_clk(hw, &i2cctl);
3273 3406
3274 3407 /* Min high period of clock is 4us */
3275 3408 usec_delay(E1000_I2C_T_HIGH);
3276 3409
3277 3410 e1000_lower_i2c_clk(hw, &i2cctl);
3278 3411
3279 3412 /* Min low period of clock is 4.7us*/
3280 3413 usec_delay(E1000_I2C_T_LOW);
3281 3414 }
3282 3415
3283 3416 e1000_i2c_start(hw);
3284 3417
3285 3418 /* Put the i2c bus back to default state */
3286 3419 e1000_i2c_stop(hw);
3287 3420 }
3288 3421
3289 3422
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