127 * @hw: pointer to the HW structure
128 *
129 * Called to determine if the I2C pins are being used for I2C or as an
130 * external MDIO interface since the two options are mutually exclusive.
131 **/
132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
133 {
134 u32 reg = 0;
135 bool ext_mdio = FALSE;
136
137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
138
139 switch (hw->mac.type) {
140 case e1000_82575:
141 case e1000_82576:
142 reg = E1000_READ_REG(hw, E1000_MDIC);
143 ext_mdio = !!(reg & E1000_MDIC_DEST);
144 break;
145 case e1000_82580:
146 case e1000_i350:
147 case e1000_i210:
148 case e1000_i211:
149 reg = E1000_READ_REG(hw, E1000_MDICNFG);
150 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
151 break;
152 default:
153 break;
154 }
155 return ext_mdio;
156 }
157
158 /**
159 * e1000_init_phy_params_82575 - Init PHY func ptrs.
160 * @hw: pointer to the HW structure
161 **/
162 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
163 {
164 struct e1000_phy_info *phy = &hw->phy;
165 s32 ret_val = E1000_SUCCESS;
166 u32 ctrl_ext;
190 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
191
192 if (e1000_sgmii_active_82575(hw)) {
193 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
194 ctrl_ext |= E1000_CTRL_I2C_ENA;
195 } else {
196 phy->ops.reset = e1000_phy_hw_reset_generic;
197 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
198 }
199
200 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
201 e1000_reset_mdicnfg_82580(hw);
202
203 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
204 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
205 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
206 } else {
207 switch (hw->mac.type) {
208 case e1000_82580:
209 case e1000_i350:
210 phy->ops.read_reg = e1000_read_phy_reg_82580;
211 phy->ops.write_reg = e1000_write_phy_reg_82580;
212 break;
213 case e1000_i210:
214 case e1000_i211:
215 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
216 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
217 break;
218 default:
219 phy->ops.read_reg = e1000_read_phy_reg_igp;
220 phy->ops.write_reg = e1000_write_phy_reg_igp;
221 }
222 }
223
224 /* Set phy->phy_addr and phy->id. */
225 ret_val = e1000_get_phy_id_82575(hw);
226
227 /* Verify phy id and set remaining function pointers */
228 switch (phy->id) {
229 case I347AT4_E_PHY_ID:
230 case M88E1112_E_PHY_ID:
231 case M88E1340M_E_PHY_ID:
232 case M88E1111_I_PHY_ID:
233 phy->type = e1000_phy_m88;
234 phy->ops.check_polarity = e1000_check_polarity_m88;
235 phy->ops.get_info = e1000_get_phy_info_m88;
236 if (phy->id == I347AT4_E_PHY_ID ||
237 phy->id == M88E1112_E_PHY_ID ||
238 phy->id == M88E1340M_E_PHY_ID)
239 phy->ops.get_cable_length =
240 e1000_get_cable_length_m88_gen2;
241 else
242 phy->ops.get_cable_length = e1000_get_cable_length_m88;
243 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
244 break;
245 case IGP03E1000_E_PHY_ID:
246 case IGP04E1000_E_PHY_ID:
247 phy->type = e1000_phy_igp_3;
248 phy->ops.check_polarity = e1000_check_polarity_igp;
249 phy->ops.get_info = e1000_get_phy_info_igp;
250 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
251 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
252 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
253 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
254 break;
255 case I82580_I_PHY_ID:
256 case I350_I_PHY_ID:
257 phy->type = e1000_phy_82580;
258 phy->ops.check_polarity = e1000_check_polarity_82577;
259 phy->ops.force_speed_duplex =
260 e1000_phy_force_speed_duplex_82577;
261 phy->ops.get_cable_length = e1000_get_cable_length_82577;
262 phy->ops.get_info = e1000_get_phy_info_82577;
338 /* Function Pointers */
339 nvm->ops.acquire = e1000_acquire_nvm_82575;
340 nvm->ops.release = e1000_release_nvm_82575;
341 if (nvm->word_size < (1 << 15))
342 nvm->ops.read = e1000_read_nvm_eerd;
343 else
344 nvm->ops.read = e1000_read_nvm_spi;
345
346 nvm->ops.write = e1000_write_nvm_spi;
347 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
348 nvm->ops.update = e1000_update_nvm_checksum_generic;
349 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
350
351 /* override generic family function pointers for specific descendants */
352 switch (hw->mac.type) {
353 case e1000_82580:
354 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
355 nvm->ops.update = e1000_update_nvm_checksum_82580;
356 break;
357 case e1000_i350:
358 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
359 nvm->ops.update = e1000_update_nvm_checksum_i350;
360 break;
361 default:
362 break;
363 }
364
365 return E1000_SUCCESS;
366 }
367
368 /**
369 * e1000_init_mac_params_82575 - Init MAC func ptrs.
370 * @hw: pointer to the HW structure
371 **/
372 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
373 {
374 struct e1000_mac_info *mac = &hw->mac;
375 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
376
377 DEBUGFUNC("e1000_init_mac_params_82575");
378
379 /* Derives media type */
380 e1000_get_media_type_82575(hw);
381 /* Set mta register count */
382 mac->mta_reg_count = 128;
383 /* Set uta register count */
384 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
385 /* Set rar entry count */
386 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
387 if (mac->type == e1000_82576)
388 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
389 if (mac->type == e1000_82580)
390 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
391 if (mac->type == e1000_i350)
392 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
393
394 /* Enable EEE default settings for EEE supported devices */
395 if (mac->type >= e1000_i350)
396 dev_spec->eee_disable = TRUE;
397
398 /* Allow a single clear of the SW semaphore on I210 and newer */
399 if (mac->type >= e1000_i210)
400 dev_spec->clear_semaphore_once = TRUE;
401
402 /* Set if part includes ASF firmware */
403 mac->asf_firmware_present = TRUE;
404 /* FWSM register */
405 mac->has_fwsm = TRUE;
406 /* ARC supported; valid only if manageability features are enabled. */
407 mac->arc_subsystem_valid =
408 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
409
410 /* Function pointers */
411
412 /* bus type/speed/width */
413 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
414 /* reset */
419 /* hw initialization */
420 mac->ops.init_hw = e1000_init_hw_82575;
421 /* link setup */
422 mac->ops.setup_link = e1000_setup_link_generic;
423 /* physical interface link setup */
424 mac->ops.setup_physical_interface =
425 (hw->phy.media_type == e1000_media_type_copper)
426 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
427 /* physical interface shutdown */
428 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
429 /* physical interface power up */
430 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
431 /* check for link */
432 mac->ops.check_for_link = e1000_check_for_link_82575;
433 /* read mac address */
434 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
435 /* configure collision distance */
436 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
437 /* multicast address update */
438 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
439 if (mac->type == e1000_i350) {
440 /* writing VFTA */
441 mac->ops.write_vfta = e1000_write_vfta_i350;
442 /* clearing VFTA */
443 mac->ops.clear_vfta = e1000_clear_vfta_i350;
444 } else {
445 /* writing VFTA */
446 mac->ops.write_vfta = e1000_write_vfta_generic;
447 /* clearing VFTA */
448 mac->ops.clear_vfta = e1000_clear_vfta_generic;
449 }
450 if (hw->mac.type >= e1000_82580)
451 mac->ops.validate_mdi_setting =
452 e1000_validate_mdi_setting_crossover_generic;
453 /* ID LED init */
454 mac->ops.id_led_init = e1000_id_led_init_generic;
455 /* blink LED */
456 mac->ops.blink_led = e1000_blink_led_generic;
457 /* setup LED */
458 mac->ops.setup_led = e1000_setup_led_generic;
459 /* cleanup LED */
605 return ret_val;
606 }
607
608 /**
609 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
610 * @hw: pointer to the HW structure
611 *
612 * Retrieves the PHY address and ID for both PHY's which do and do not use
613 * sgmi interface.
614 **/
615 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
616 {
617 struct e1000_phy_info *phy = &hw->phy;
618 s32 ret_val = E1000_SUCCESS;
619 u16 phy_id;
620 u32 ctrl_ext;
621 u32 mdic;
622
623 DEBUGFUNC("e1000_get_phy_id_82575");
624
625 /*
626 * For SGMII PHYs, we try the list of possible addresses until
627 * we find one that works. For non-SGMII PHYs
628 * (e.g. integrated copper PHYs), an address of 1 should
629 * work. The result of this function should mean phy->phy_addr
630 * and phy->id are set correctly.
631 */
632 if (!e1000_sgmii_active_82575(hw)) {
633 phy->addr = 1;
634 ret_val = e1000_get_phy_id(hw);
635 goto out;
636 }
637
638 if (e1000_sgmii_uses_mdio_82575(hw)) {
639 switch (hw->mac.type) {
640 case e1000_82575:
641 case e1000_82576:
642 mdic = E1000_READ_REG(hw, E1000_MDIC);
643 mdic &= E1000_MDIC_PHY_MASK;
644 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
645 break;
646 case e1000_82580:
647 case e1000_i350:
648 case e1000_i210:
649 case e1000_i211:
650 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
651 mdic &= E1000_MDICNFG_PHY_MASK;
652 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
653 break;
654 default:
655 ret_val = -E1000_ERR_PHY;
656 goto out;
657 break;
658 }
659 ret_val = e1000_get_phy_id(hw);
660 goto out;
661 }
662
663 /* Power on sgmii phy if it is disabled */
664 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
665 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
666 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
667 E1000_WRITE_FLUSH(hw);
1198
1199 /* flush the write to verify completion */
1200 E1000_WRITE_FLUSH(hw);
1201 msec_delay(1);
1202 }
1203
1204 /**
1205 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1206 * @hw: pointer to the HW structure
1207 * @speed: stores the current speed
1208 * @duplex: stores the current duplex
1209 *
1210 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1211 * duplex, then store the values in the pointers provided.
1212 **/
1213 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1214 u16 *speed, u16 *duplex)
1215 {
1216 struct e1000_mac_info *mac = &hw->mac;
1217 u32 pcs;
1218
1219 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1220
1221 /*
1222 * Read the PCS Status register for link state. For non-copper mode,
1223 * the status register is not accurate. The PCS status register is
1224 * used instead.
1225 */
1226 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1227
1228 /*
1229 * The link up bit determines when link is up on autoneg.
1230 */
1231 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1232 mac->serdes_has_link = TRUE;
1233
1234 /* Detect and store PCS speed */
1235 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1236 *speed = SPEED_1000;
1237 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1238 *speed = SPEED_100;
1239 else
1240 *speed = SPEED_10;
1241
1242 /* Detect and store PCS duplex */
1243 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1244 *duplex = FULL_DUPLEX;
1245 else
1246 *duplex = HALF_DUPLEX;
1247
1248 } else {
1249 mac->serdes_has_link = FALSE;
1250 *speed = 0;
1251 *duplex = 0;
1252 }
1253
1254 return E1000_SUCCESS;
1255 }
1256
1257 /**
1258 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1259 * @hw: pointer to the HW structure
1260 *
1261 * In the case of serdes shut down sfp and PCS on driver unload
1262 * when management pass thru is not enabled.
1263 **/
1264 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1265 {
1266 u32 reg;
1267
1413 * e1000_setup_copper_link_82575 - Configure copper link settings
1414 * @hw: pointer to the HW structure
1415 *
1416 * Configures the link for auto-neg or forced speed and duplex. Then we check
1417 * for link, once link is established calls to configure collision distance
1418 * and flow control are called.
1419 **/
1420 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1421 {
1422 u32 ctrl;
1423 s32 ret_val;
1424 u32 phpm_reg;
1425
1426 DEBUGFUNC("e1000_setup_copper_link_82575");
1427
1428 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1429 ctrl |= E1000_CTRL_SLU;
1430 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1431 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1432
1433 /* Clear Go Link Disconnect bit */
1434 if (hw->mac.type >= e1000_82580) {
1435 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1436 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1437 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1438 }
1439
1440 ret_val = e1000_setup_serdes_link_82575(hw);
1441 if (ret_val)
1442 goto out;
1443
1444 if (e1000_sgmii_active_82575(hw)) {
1445 /* allow time for SFP cage time to power up phy */
1446 msec_delay(300);
1447
1448 ret_val = hw->phy.ops.reset(hw);
1449 if (ret_val) {
1450 DEBUGOUT("Error resetting the PHY.\n");
1451 goto out;
1452 }
1453 }
1454 switch (hw->phy.type) {
1455 case e1000_phy_i210:
1456 case e1000_phy_m88:
1457 switch (hw->phy.id) {
2115 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2116 &pcie_devctl2);
2117 out:
2118 /* disable completion timeout resend */
2119 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2120
2121 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2122 return ret_val;
2123 }
2124
2125 /**
2126 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2127 * @hw: pointer to the hardware struct
2128 * @enable: state to enter, either enabled or disabled
2129 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2130 *
2131 * enables/disables L2 switch anti-spoofing functionality.
2132 **/
2133 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2134 {
2135 u32 dtxswc;
2136
2137 switch (hw->mac.type) {
2138 case e1000_82576:
2139 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2140 if (enable) {
2141 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2142 E1000_DTXSWC_VLAN_SPOOF_MASK);
2143 /* The PF can spoof - it has to in order to
2144 * support emulation mode NICs */
2145 dtxswc ^= (1 << pf | 1 << (pf +
2146 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2147 } else {
2148 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2149 E1000_DTXSWC_VLAN_SPOOF_MASK);
2150 }
2151 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2152 break;
2153 case e1000_i350:
2154 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2155 if (enable) {
2156 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2157 E1000_DTXSWC_VLAN_SPOOF_MASK);
2158 /* The PF can spoof - it has to in order to
2159 * support emulation mode NICs
2160 */
2161 dtxswc ^= (1 << pf | 1 << (pf +
2162 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2163 } else {
2164 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2165 E1000_DTXSWC_VLAN_SPOOF_MASK);
2166 }
2167 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2168 default:
2169 break;
2170 }
2171 }
2172
2173 /**
2174 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2175 * @hw: pointer to the hardware struct
2176 * @enable: state to enter, either enabled or disabled
2177 *
2178 * enables/disables L2 switch loopback functionality.
2179 **/
2180 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2181 {
2182 u32 dtxswc;
2183
2184 switch (hw->mac.type) {
2185 case e1000_82576:
2186 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2187 if (enable)
2188 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2189 else
2190 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2191 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2192 break;
2193 case e1000_i350:
2194 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2195 if (enable)
2196 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2197 else
2198 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2199 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2200 break;
2201 default:
2202 /* Currently no other hardware supports loopback */
2203 break;
2204 }
2205
2206
2207 }
2208
2209 /**
2210 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2211 * @hw: pointer to the hardware struct
2212 * @enable: state to enter, either enabled or disabled
2213 *
2671 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2672 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2673 E1000_EEER_LPI_FC);
2674
2675 /* This bit should not be set in normal operation. */
2676 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2677 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2678 } else {
2679 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2680 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2681 E1000_EEER_LPI_FC);
2682 }
2683 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2684 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2685 E1000_READ_REG(hw, E1000_IPCNFG);
2686 E1000_READ_REG(hw, E1000_EEER);
2687 out:
2688
2689 return ret_val;
2690 }
2691
2692 /* Due to a hw errata, if the host tries to configure the VFTA register
2693 * while performing queries from the BMC or DMA, then the VFTA in some
2694 * cases won't be written.
2695 */
2696
2697 /**
2698 * e1000_clear_vfta_i350 - Clear VLAN filter table
2699 * @hw: pointer to the HW structure
2700 *
2701 * Clears the register array which contains the VLAN filter table by
2702 * setting all the values to 0.
2703 **/
2704 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2705 {
2706 u32 offset;
2707 int i;
2708
2709 DEBUGFUNC("e1000_clear_vfta_350");
2710
|
127 * @hw: pointer to the HW structure
128 *
129 * Called to determine if the I2C pins are being used for I2C or as an
130 * external MDIO interface since the two options are mutually exclusive.
131 **/
132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
133 {
134 u32 reg = 0;
135 bool ext_mdio = FALSE;
136
137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
138
139 switch (hw->mac.type) {
140 case e1000_82575:
141 case e1000_82576:
142 reg = E1000_READ_REG(hw, E1000_MDIC);
143 ext_mdio = !!(reg & E1000_MDIC_DEST);
144 break;
145 case e1000_82580:
146 case e1000_i350:
147 case e1000_i354:
148 case e1000_i210:
149 case e1000_i211:
150 reg = E1000_READ_REG(hw, E1000_MDICNFG);
151 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
152 break;
153 default:
154 break;
155 }
156 return ext_mdio;
157 }
158
159 /**
160 * e1000_init_phy_params_82575 - Init PHY func ptrs.
161 * @hw: pointer to the HW structure
162 **/
163 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
164 {
165 struct e1000_phy_info *phy = &hw->phy;
166 s32 ret_val = E1000_SUCCESS;
167 u32 ctrl_ext;
191 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
192
193 if (e1000_sgmii_active_82575(hw)) {
194 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
195 ctrl_ext |= E1000_CTRL_I2C_ENA;
196 } else {
197 phy->ops.reset = e1000_phy_hw_reset_generic;
198 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
199 }
200
201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
202 e1000_reset_mdicnfg_82580(hw);
203
204 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
205 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
206 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
207 } else {
208 switch (hw->mac.type) {
209 case e1000_82580:
210 case e1000_i350:
211 case e1000_i354:
212 phy->ops.read_reg = e1000_read_phy_reg_82580;
213 phy->ops.write_reg = e1000_write_phy_reg_82580;
214 break;
215 case e1000_i210:
216 case e1000_i211:
217 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
218 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
219 break;
220 default:
221 phy->ops.read_reg = e1000_read_phy_reg_igp;
222 phy->ops.write_reg = e1000_write_phy_reg_igp;
223 }
224 }
225
226 /* Set phy->phy_addr and phy->id. */
227 ret_val = e1000_get_phy_id_82575(hw);
228
229 /* Verify phy id and set remaining function pointers */
230 switch (phy->id) {
231 case M88E1543_E_PHY_ID:
232 case M88E1512_E_PHY_ID:
233 case I347AT4_E_PHY_ID:
234 case M88E1112_E_PHY_ID:
235 case M88E1340M_E_PHY_ID:
236 case M88E1111_I_PHY_ID:
237 phy->type = e1000_phy_m88;
238 phy->ops.check_polarity = e1000_check_polarity_m88;
239 phy->ops.get_info = e1000_get_phy_info_m88;
240 switch (phy->id) {
241 case I347AT4_E_PHY_ID:
242 case M88E1112_E_PHY_ID:
243 case M88E1340M_E_PHY_ID:
244 case M88E1543_E_PHY_ID:
245 case M88E1512_E_PHY_ID:
246 phy->ops.get_cable_length =
247 e1000_get_cable_length_m88_gen2;
248 default:
249 phy->ops.get_cable_length = e1000_get_cable_length_m88;
250 }
251 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
252 break;
253 case IGP03E1000_E_PHY_ID:
254 case IGP04E1000_E_PHY_ID:
255 phy->type = e1000_phy_igp_3;
256 phy->ops.check_polarity = e1000_check_polarity_igp;
257 phy->ops.get_info = e1000_get_phy_info_igp;
258 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
259 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
260 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
261 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
262 break;
263 case I82580_I_PHY_ID:
264 case I350_I_PHY_ID:
265 phy->type = e1000_phy_82580;
266 phy->ops.check_polarity = e1000_check_polarity_82577;
267 phy->ops.force_speed_duplex =
268 e1000_phy_force_speed_duplex_82577;
269 phy->ops.get_cable_length = e1000_get_cable_length_82577;
270 phy->ops.get_info = e1000_get_phy_info_82577;
346 /* Function Pointers */
347 nvm->ops.acquire = e1000_acquire_nvm_82575;
348 nvm->ops.release = e1000_release_nvm_82575;
349 if (nvm->word_size < (1 << 15))
350 nvm->ops.read = e1000_read_nvm_eerd;
351 else
352 nvm->ops.read = e1000_read_nvm_spi;
353
354 nvm->ops.write = e1000_write_nvm_spi;
355 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
356 nvm->ops.update = e1000_update_nvm_checksum_generic;
357 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
358
359 /* override generic family function pointers for specific descendants */
360 switch (hw->mac.type) {
361 case e1000_82580:
362 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
363 nvm->ops.update = e1000_update_nvm_checksum_82580;
364 break;
365 case e1000_i350:
366 case e1000_i354:
367 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
368 nvm->ops.update = e1000_update_nvm_checksum_i350;
369 break;
370 default:
371 break;
372 }
373
374 return E1000_SUCCESS;
375 }
376
377 /**
378 * e1000_init_mac_params_82575 - Init MAC func ptrs.
379 * @hw: pointer to the HW structure
380 **/
381 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
382 {
383 struct e1000_mac_info *mac = &hw->mac;
384 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
385
386 DEBUGFUNC("e1000_init_mac_params_82575");
387
388 /* Derives media type */
389 e1000_get_media_type_82575(hw);
390 /* Set mta register count */
391 mac->mta_reg_count = 128;
392 /* Set uta register count */
393 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
394 /* Set rar entry count */
395 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
396 if (mac->type == e1000_82576)
397 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
398 if (mac->type == e1000_82580)
399 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
400 if (mac->type == e1000_i350 || mac->type == e1000_i354)
401 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
402
403 /* Disable EEE default settings for EEE supported devices */
404 if (mac->type >= e1000_i350)
405 dev_spec->eee_disable = TRUE;
406
407 /* Allow a single clear of the SW semaphore on I210 and newer */
408 if (mac->type >= e1000_i210)
409 dev_spec->clear_semaphore_once = TRUE;
410
411 /* Set if part includes ASF firmware */
412 mac->asf_firmware_present = TRUE;
413 /* FWSM register */
414 mac->has_fwsm = TRUE;
415 /* ARC supported; valid only if manageability features are enabled. */
416 mac->arc_subsystem_valid =
417 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
418
419 /* Function pointers */
420
421 /* bus type/speed/width */
422 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
423 /* reset */
428 /* hw initialization */
429 mac->ops.init_hw = e1000_init_hw_82575;
430 /* link setup */
431 mac->ops.setup_link = e1000_setup_link_generic;
432 /* physical interface link setup */
433 mac->ops.setup_physical_interface =
434 (hw->phy.media_type == e1000_media_type_copper)
435 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
436 /* physical interface shutdown */
437 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
438 /* physical interface power up */
439 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
440 /* check for link */
441 mac->ops.check_for_link = e1000_check_for_link_82575;
442 /* read mac address */
443 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
444 /* configure collision distance */
445 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
446 /* multicast address update */
447 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
448 if (mac->type == e1000_i350 || mac->type == e1000_i354) {
449 /* writing VFTA */
450 mac->ops.write_vfta = e1000_write_vfta_i350;
451 /* clearing VFTA */
452 mac->ops.clear_vfta = e1000_clear_vfta_i350;
453 } else {
454 /* writing VFTA */
455 mac->ops.write_vfta = e1000_write_vfta_generic;
456 /* clearing VFTA */
457 mac->ops.clear_vfta = e1000_clear_vfta_generic;
458 }
459 if (hw->mac.type >= e1000_82580)
460 mac->ops.validate_mdi_setting =
461 e1000_validate_mdi_setting_crossover_generic;
462 /* ID LED init */
463 mac->ops.id_led_init = e1000_id_led_init_generic;
464 /* blink LED */
465 mac->ops.blink_led = e1000_blink_led_generic;
466 /* setup LED */
467 mac->ops.setup_led = e1000_setup_led_generic;
468 /* cleanup LED */
614 return ret_val;
615 }
616
617 /**
618 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
619 * @hw: pointer to the HW structure
620 *
621 * Retrieves the PHY address and ID for both PHY's which do and do not use
622 * sgmi interface.
623 **/
624 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
625 {
626 struct e1000_phy_info *phy = &hw->phy;
627 s32 ret_val = E1000_SUCCESS;
628 u16 phy_id;
629 u32 ctrl_ext;
630 u32 mdic;
631
632 DEBUGFUNC("e1000_get_phy_id_82575");
633
634 /* some i354 devices need an extra read for phy id */
635 if (hw->mac.type == e1000_i354)
636 e1000_get_phy_id(hw);
637
638 /*
639 * For SGMII PHYs, we try the list of possible addresses until
640 * we find one that works. For non-SGMII PHYs
641 * (e.g. integrated copper PHYs), an address of 1 should
642 * work. The result of this function should mean phy->phy_addr
643 * and phy->id are set correctly.
644 */
645 if (!e1000_sgmii_active_82575(hw)) {
646 phy->addr = 1;
647 ret_val = e1000_get_phy_id(hw);
648 goto out;
649 }
650
651 if (e1000_sgmii_uses_mdio_82575(hw)) {
652 switch (hw->mac.type) {
653 case e1000_82575:
654 case e1000_82576:
655 mdic = E1000_READ_REG(hw, E1000_MDIC);
656 mdic &= E1000_MDIC_PHY_MASK;
657 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
658 break;
659 case e1000_82580:
660 case e1000_i350:
661 case e1000_i354:
662 case e1000_i210:
663 case e1000_i211:
664 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
665 mdic &= E1000_MDICNFG_PHY_MASK;
666 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
667 break;
668 default:
669 ret_val = -E1000_ERR_PHY;
670 goto out;
671 break;
672 }
673 ret_val = e1000_get_phy_id(hw);
674 goto out;
675 }
676
677 /* Power on sgmii phy if it is disabled */
678 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
679 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
680 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
681 E1000_WRITE_FLUSH(hw);
1212
1213 /* flush the write to verify completion */
1214 E1000_WRITE_FLUSH(hw);
1215 msec_delay(1);
1216 }
1217
1218 /**
1219 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1220 * @hw: pointer to the HW structure
1221 * @speed: stores the current speed
1222 * @duplex: stores the current duplex
1223 *
1224 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1225 * duplex, then store the values in the pointers provided.
1226 **/
1227 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1228 u16 *speed, u16 *duplex)
1229 {
1230 struct e1000_mac_info *mac = &hw->mac;
1231 u32 pcs;
1232 u32 status;
1233
1234 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1235
1236 /*
1237 * Read the PCS Status register for link state. For non-copper mode,
1238 * the status register is not accurate. The PCS status register is
1239 * used instead.
1240 */
1241 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1242
1243 /*
1244 * The link up bit determines when link is up on autoneg.
1245 */
1246 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1247 mac->serdes_has_link = TRUE;
1248
1249 /* Detect and store PCS speed */
1250 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1251 *speed = SPEED_1000;
1252 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1253 *speed = SPEED_100;
1254 else
1255 *speed = SPEED_10;
1256
1257 /* Detect and store PCS duplex */
1258 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1259 *duplex = FULL_DUPLEX;
1260 else
1261 *duplex = HALF_DUPLEX;
1262
1263 /* Check if it is an I354 2.5Gb backplane connection. */
1264 if (mac->type == e1000_i354) {
1265 status = E1000_READ_REG(hw, E1000_STATUS);
1266 if ((status & E1000_STATUS_2P5_SKU) &&
1267 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1268 *speed = SPEED_2500;
1269 *duplex = FULL_DUPLEX;
1270 DEBUGOUT("2500 Mbs, ");
1271 DEBUGOUT("Full Duplex\n");
1272 }
1273 }
1274
1275 } else {
1276 mac->serdes_has_link = FALSE;
1277 *speed = 0;
1278 *duplex = 0;
1279 }
1280
1281 return E1000_SUCCESS;
1282 }
1283
1284 /**
1285 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1286 * @hw: pointer to the HW structure
1287 *
1288 * In the case of serdes shut down sfp and PCS on driver unload
1289 * when management pass thru is not enabled.
1290 **/
1291 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1292 {
1293 u32 reg;
1294
1440 * e1000_setup_copper_link_82575 - Configure copper link settings
1441 * @hw: pointer to the HW structure
1442 *
1443 * Configures the link for auto-neg or forced speed and duplex. Then we check
1444 * for link, once link is established calls to configure collision distance
1445 * and flow control are called.
1446 **/
1447 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1448 {
1449 u32 ctrl;
1450 s32 ret_val;
1451 u32 phpm_reg;
1452
1453 DEBUGFUNC("e1000_setup_copper_link_82575");
1454
1455 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1456 ctrl |= E1000_CTRL_SLU;
1457 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1458 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1459
1460 /* Clear Go Link Disconnect bit on supported devices */
1461 switch (hw->mac.type) {
1462 case e1000_82580:
1463 case e1000_i350:
1464 case e1000_i210:
1465 case e1000_i211:
1466 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1467 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1468 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1469 break;
1470 default:
1471 break;
1472 }
1473
1474 ret_val = e1000_setup_serdes_link_82575(hw);
1475 if (ret_val)
1476 goto out;
1477
1478 if (e1000_sgmii_active_82575(hw)) {
1479 /* allow time for SFP cage time to power up phy */
1480 msec_delay(300);
1481
1482 ret_val = hw->phy.ops.reset(hw);
1483 if (ret_val) {
1484 DEBUGOUT("Error resetting the PHY.\n");
1485 goto out;
1486 }
1487 }
1488 switch (hw->phy.type) {
1489 case e1000_phy_i210:
1490 case e1000_phy_m88:
1491 switch (hw->phy.id) {
2149 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2150 &pcie_devctl2);
2151 out:
2152 /* disable completion timeout resend */
2153 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2154
2155 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2156 return ret_val;
2157 }
2158
2159 /**
2160 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2161 * @hw: pointer to the hardware struct
2162 * @enable: state to enter, either enabled or disabled
2163 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2164 *
2165 * enables/disables L2 switch anti-spoofing functionality.
2166 **/
2167 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2168 {
2169 u32 reg_val, reg_offset;
2170
2171 switch (hw->mac.type) {
2172 case e1000_82576:
2173 reg_offset = E1000_DTXSWC;
2174 break;
2175 case e1000_i350:
2176 case e1000_i354:
2177 reg_offset = E1000_TXSWC;
2178 break;
2179 default:
2180 return;
2181 }
2182 reg_val = E1000_READ_REG(hw, reg_offset);
2183 if (enable) {
2184 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2185 E1000_DTXSWC_VLAN_SPOOF_MASK);
2186 /* The PF can spoof - it has to in order to
2187 * support emulation mode NICs
2188 */
2189 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2190 } else {
2191 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2192 E1000_DTXSWC_VLAN_SPOOF_MASK);
2193 }
2194 E1000_WRITE_REG(hw, reg_offset, reg_val);
2195 }
2196
2197 /**
2198 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2199 * @hw: pointer to the hardware struct
2200 * @enable: state to enter, either enabled or disabled
2201 *
2202 * enables/disables L2 switch loopback functionality.
2203 **/
2204 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2205 {
2206 u32 dtxswc;
2207
2208 switch (hw->mac.type) {
2209 case e1000_82576:
2210 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2211 if (enable)
2212 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2213 else
2214 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2215 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2216 break;
2217 case e1000_i350:
2218 case e1000_i354:
2219 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2220 if (enable)
2221 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2222 else
2223 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2224 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2225 break;
2226 default:
2227 /* Currently no other hardware supports loopback */
2228 break;
2229 }
2230
2231
2232 }
2233
2234 /**
2235 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2236 * @hw: pointer to the hardware struct
2237 * @enable: state to enter, either enabled or disabled
2238 *
2696 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2697 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2698 E1000_EEER_LPI_FC);
2699
2700 /* This bit should not be set in normal operation. */
2701 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2702 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2703 } else {
2704 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2705 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2706 E1000_EEER_LPI_FC);
2707 }
2708 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2709 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2710 E1000_READ_REG(hw, E1000_IPCNFG);
2711 E1000_READ_REG(hw, E1000_EEER);
2712 out:
2713
2714 return ret_val;
2715 }
2716
2717 /**
2718 * e1000_set_eee_i354 - Enable/disable EEE support
2719 * @hw: pointer to the HW structure
2720 *
2721 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2722 *
2723 **/
2724 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2725 {
2726 struct e1000_phy_info *phy = &hw->phy;
2727 s32 ret_val = E1000_SUCCESS;
2728 u16 phy_data;
2729
2730 DEBUGFUNC("e1000_set_eee_i354");
2731
2732 if ((hw->phy.media_type != e1000_media_type_copper) ||
2733 ((phy->id != M88E1543_E_PHY_ID) &&
2734 (phy->id != M88E1512_E_PHY_ID)))
2735 goto out;
2736
2737 if (!hw->dev_spec._82575.eee_disable) {
2738 /* Switch to PHY page 18. */
2739 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2740 if (ret_val)
2741 goto out;
2742
2743 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2744 &phy_data);
2745 if (ret_val)
2746 goto out;
2747
2748 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2749 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2750 phy_data);
2751 if (ret_val)
2752 goto out;
2753
2754 /* Return the PHY to page 0. */
2755 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2756 if (ret_val)
2757 goto out;
2758
2759 /* Turn on EEE advertisement. */
2760 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2761 E1000_EEE_ADV_DEV_I354,
2762 &phy_data);
2763 if (ret_val)
2764 goto out;
2765
2766 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2767 E1000_EEE_ADV_1000_SUPPORTED;
2768 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2769 E1000_EEE_ADV_DEV_I354,
2770 phy_data);
2771 } else {
2772 /* Turn off EEE advertisement. */
2773 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2774 E1000_EEE_ADV_DEV_I354,
2775 &phy_data);
2776 if (ret_val)
2777 goto out;
2778
2779 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2780 E1000_EEE_ADV_1000_SUPPORTED);
2781 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2782 E1000_EEE_ADV_DEV_I354,
2783 phy_data);
2784 }
2785
2786 out:
2787 return ret_val;
2788 }
2789
2790 /**
2791 * e1000_get_eee_status_i354 - Get EEE status
2792 * @hw: pointer to the HW structure
2793 * @status: EEE status
2794 *
2795 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2796 * been received.
2797 **/
2798 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2799 {
2800 struct e1000_phy_info *phy = &hw->phy;
2801 s32 ret_val = E1000_SUCCESS;
2802 u16 phy_data;
2803
2804 DEBUGFUNC("e1000_get_eee_status_i354");
2805
2806 /* Check if EEE is supported on this device. */
2807 if ((hw->phy.media_type != e1000_media_type_copper) ||
2808 ((phy->id != M88E1543_E_PHY_ID) &&
2809 (phy->id != M88E1512_E_PHY_ID)))
2810 goto out;
2811
2812 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2813 E1000_PCS_STATUS_DEV_I354,
2814 &phy_data);
2815 if (ret_val)
2816 goto out;
2817
2818 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2819 E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE;
2820
2821 out:
2822 return ret_val;
2823 }
2824
2825 /* Due to a hw errata, if the host tries to configure the VFTA register
2826 * while performing queries from the BMC or DMA, then the VFTA in some
2827 * cases won't be written.
2828 */
2829
2830 /**
2831 * e1000_clear_vfta_i350 - Clear VLAN filter table
2832 * @hw: pointer to the HW structure
2833 *
2834 * Clears the register array which contains the VLAN filter table by
2835 * setting all the values to 0.
2836 **/
2837 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2838 {
2839 u32 offset;
2840 int i;
2841
2842 DEBUGFUNC("e1000_clear_vfta_350");
2843
|