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--- old/usr/src/lib/libm/common/m9x/fex_handler.h
+++ new/usr/src/lib/libm/common/m9x/fex_handler.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
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20 20 */
21 21
22 22 /*
23 23 * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
27 27 * Use is subject to license terms.
28 28 */
29 29
30 -/* #include <sys/isa_defs.h> */
31 -
32 30 /* the following enums must match the bit positions in fenv.h */
33 31 enum fex_exception {
34 32 fex_inexact = 0,
35 33 fex_division = 1,
36 34 fex_underflow = 2,
37 35 fex_overflow = 3,
38 36 fex_inv_zdz = 4,
39 37 fex_inv_idi = 5,
40 38 fex_inv_isi = 6,
41 39 fex_inv_zmi = 7,
42 40 fex_inv_sqrt = 8,
43 41 fex_inv_snan = 9,
44 42 fex_inv_int = 10,
45 43 fex_inv_cmp = 11
46 44 };
47 45
48 46
49 47 /* auxiliary functions in __fex_hdlr.c */
50 48 extern struct fex_handler_data *__fex_get_thr_handlers(void);
51 49 extern void __fex_update_te(void);
52 50
53 51 /* auxiliary functions in __fex_sym.c */
54 52 extern void __fex_sym_init(void);
55 53 extern char *__fex_sym(char *, char **);
56 54
57 55 /* auxiliary functions in fex_log.c */
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58 56 extern void __fex_mklog(ucontext_t *, char *, int, enum fex_exception,
59 57 int, void *);
60 58
61 59 /* system-dependent auxiliary functions */
62 60 extern enum fex_exception __fex_get_invalid_type(siginfo_t *, ucontext_t *);
63 61 extern void __fex_get_op(siginfo_t *, ucontext_t *, fex_info_t *);
64 62 extern void __fex_st_result(siginfo_t *, ucontext_t *, fex_info_t *);
65 63
66 64 /* inline templates and macros for accessing fp state */
67 65 extern void __fenv_getfsr(unsigned long *);
68 -extern void __fenv_setfsr(unsigned const long *);
66 +extern void __fenv_setfsr(const unsigned long *);
69 67
70 68 #if defined(__sparc)
71 69
72 70 #define __fenv_get_rd(X) ((X>>30)&0x3)
73 71 #define __fenv_set_rd(X,Y) X=(X&~0xc0000000ul)|((Y)<<30)
74 72
75 73 #define __fenv_get_te(X) ((X>>23)&0x1f)
76 74 #define __fenv_set_te(X,Y) X=(X&~0x0f800000ul)|((Y)<<23)
77 75
78 76 #define __fenv_get_ex(X) ((X>>5)&0x1f)
79 77 #define __fenv_set_ex(X,Y) X=(X&~0x000003e0ul)|((Y)<<5)
80 78
81 79 #elif defined(__x86)
82 80
83 81 extern void __fenv_getcwsw(unsigned int *);
84 82 extern void __fenv_setcwsw(const unsigned int *);
85 83
86 84 extern void __fenv_getmxcsr(unsigned int *);
87 85 extern void __fenv_setmxcsr(const unsigned int *);
88 86
89 87 #define __fenv_get_rd(X) ((X>>26)&3)
90 88 #define __fenv_set_rd(X,Y) X=(X&~0x0c000000)|((Y)<<26)
91 89
92 90 #define __fenv_get_rp(X) ((X>>24)&3)
93 91 #define __fenv_set_rp(X,Y) X=(X&~0x03000000)|((Y)<<24)
94 92
95 93 #define __fenv_get_te(X) ((X>>16)&0x3d)
96 94 #define __fenv_set_te(X,Y) X=(X&~0x003d0000)|((Y)<<16)
97 95
98 96 #define __fenv_get_ex(X) (X&0x3d)
99 97 #define __fenv_set_ex(X,Y) X=(X&~0x0000003d)|(Y)
100 98
101 99 /*
102 100 * These macros define some useful distinctions between various
103 101 * SSE instructions. In some cases, distinctions are made for
104 102 * the purpose of simplifying the decoding of instructions, while
105 103 * in other cases, they are made for the purpose of simplying the
106 104 * emulation. Note that these values serve as bit flags within
107 105 * the enum values in sseinst_t.
108 106 */
109 107 #define DOUBLE 0x100
110 108 #define SIMD 0x080
111 109 #define INTREG 0x040
112 110
113 111 typedef union {
114 112 double d[2];
115 113 long long l[2];
116 114 float f[4];
117 115 int i[4];
118 116 } sseoperand_t;
119 117
120 118 /* structure to hold a decoded SSE instruction */
121 119 typedef struct {
122 120 enum {
123 121 /* single precision scalar instructions */
124 122 cmpss = 0,
125 123 minss = 1,
126 124 maxss = 2,
127 125 addss = 3,
128 126 subss = 4,
129 127 mulss = 5,
130 128 divss = 6,
131 129 sqrtss = 7,
132 130 ucomiss = 16,
133 131 comiss = 17,
134 132 cvtss2sd = 32,
135 133 cvtsi2ss = INTREG + 0,
136 134 cvttss2si = INTREG + 1,
137 135 cvtss2si = INTREG + 2,
138 136 cvtsi2ssq = INTREG + 8,
139 137 cvttss2siq = INTREG + 9,
140 138 cvtss2siq = INTREG + 10,
141 139
142 140 /* single precision SIMD instructions */
143 141 cmpps = SIMD + 0,
144 142 minps = SIMD + 1,
145 143 maxps = SIMD + 2,
146 144 addps = SIMD + 3,
147 145 subps = SIMD + 4,
148 146 mulps = SIMD + 5,
149 147 divps = SIMD + 6,
150 148 sqrtps = SIMD + 7,
151 149 cvtps2pd = SIMD + 32,
152 150 cvtdq2ps = SIMD + 34,
153 151 cvttps2dq = SIMD + 35,
154 152 cvtps2dq = SIMD + 36,
155 153 cvtpi2ps = SIMD + INTREG + 0,
156 154 cvttps2pi = SIMD + INTREG + 1,
157 155 cvtps2pi = SIMD + INTREG + 2,
158 156
159 157 /* double precision scalar instructions */
160 158 cmpsd = DOUBLE + 0,
161 159 minsd = DOUBLE + 1,
162 160 maxsd = DOUBLE + 2,
163 161 addsd = DOUBLE + 3,
164 162 subsd = DOUBLE + 4,
165 163 mulsd = DOUBLE + 5,
166 164 divsd = DOUBLE + 6,
167 165 sqrtsd = DOUBLE + 7,
168 166 ucomisd = DOUBLE + 16,
169 167 comisd = DOUBLE + 17,
170 168 cvtsd2ss = DOUBLE + 32,
171 169 cvtsi2sd = DOUBLE + INTREG + 0,
172 170 cvttsd2si = DOUBLE + INTREG + 1,
173 171 cvtsd2si = DOUBLE + INTREG + 2,
174 172 cvtsi2sdq = DOUBLE + INTREG + 8,
175 173 cvttsd2siq = DOUBLE + INTREG + 9,
176 174 cvtsd2siq = DOUBLE + INTREG + 10,
177 175
178 176 /* double precision SIMD instructions */
179 177 cmppd = DOUBLE + SIMD + 0,
180 178 minpd = DOUBLE + SIMD + 1,
181 179 maxpd = DOUBLE + SIMD + 2,
182 180 addpd = DOUBLE + SIMD + 3,
183 181 subpd = DOUBLE + SIMD + 4,
184 182 mulpd = DOUBLE + SIMD + 5,
185 183 divpd = DOUBLE + SIMD + 6,
186 184 sqrtpd = DOUBLE + SIMD + 7,
187 185 cvtpd2ps = DOUBLE + SIMD + 32,
188 186 cvtdq2pd = DOUBLE + SIMD + 34,
189 187 cvttpd2dq = DOUBLE + SIMD + 35,
190 188 cvtpd2dq = DOUBLE + SIMD + 36,
191 189 cvtpi2pd = DOUBLE + SIMD + INTREG + 0,
192 190 cvttpd2pi = DOUBLE + SIMD + INTREG + 1,
193 191 cvtpd2pi = DOUBLE + SIMD + INTREG + 2,
194 192 } op;
195 193 int imm;
196 194 sseoperand_t *op1, *op2;
197 195 } sseinst_t;
198 196
199 197 /* x86-specific auxiliary functions */
200 198 extern int *__fex_accrued(void);
201 199 extern void __fex_get_x86_exc(siginfo_t *, ucontext_t *);
202 200 extern int __fex_parse_sse(ucontext_t *, sseinst_t *);
203 201 extern enum fex_exception __fex_get_sse_op(ucontext_t *, sseinst_t *,
204 202 fex_info_t *);
205 203 extern void __fex_get_simd_op(ucontext_t *, sseinst_t *,
206 204 enum fex_exception *, fex_info_t *);
207 205 extern void __fex_st_sse_result(ucontext_t *, sseinst_t *,
208 206 enum fex_exception, fex_info_t *);
209 207 extern void __fex_st_simd_result(ucontext_t *, sseinst_t *,
210 208 enum fex_exception *, fex_info_t *);
211 209
212 210 #else
213 211 #error Unknown architecture
214 212 #endif
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