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*** 241,251 ****
r = ((rex & 1) << 3) | (modrm & 7);
inst->op2 = (sseoperand_t *)&uap->uc_mcontext.fpregs.
fp_reg_set.fpchip_state.xmm[r];
}
} else if ((modrm & 0xc7) == 0x05) {
! #if defined(__amd64)
/* address of next instruction + offset */
r = i + 4;
if (inst->op == cmpss || inst->op == cmpps ||
inst->op == cmpsd || inst->op == cmppd)
r++;
--- 241,251 ----
r = ((rex & 1) << 3) | (modrm & 7);
inst->op2 = (sseoperand_t *)&uap->uc_mcontext.fpregs.
fp_reg_set.fpchip_state.xmm[r];
}
} else if ((modrm & 0xc7) == 0x05) {
! #ifdef __amd64
/* address of next instruction + offset */
r = i + 4;
if (inst->op == cmpss || inst->op == cmpps ||
inst->op == cmpsd || inst->op == cmppd)
r++;
*** 260,270 ****
if ((modrm & 7) == 4) {
/* parse sib byte */
sib = ip[i++];
if ((sib & 7) == 5 && (modrm >> 6) == 0) {
/* start with absolute address */
! addr = (char *)(uintptr_t)(ip + i);
i += 4;
} else {
/* start with base */
r = ((rex & 1) << 3) | (sib & 7);
addr = (char *)uap->uc_mcontext.gregs[regno(r)];
--- 260,270 ----
if ((modrm & 7) == 4) {
/* parse sib byte */
sib = ip[i++];
if ((sib & 7) == 5 && (modrm >> 6) == 0) {
/* start with absolute address */
! addr = (char *)(uintptr_t)(*(int *)(ip + i));
i += 4;
} else {
/* start with base */
r = ((rex & 1) << 3) | (sib & 7);
addr = (char *)uap->uc_mcontext.gregs[regno(r)];
*** 368,377 ****
--- 368,379 ----
case cvtss2siq:
case cvtsd2siq:
case cvttss2siq:
case cvttsd2siq:
return fex_inv_int;
+ default:
+ break;
}
/* check op1 for signaling nan */
t1 = ((int)inst->op & DOUBLE)? my_fp_class(&inst->op1->d[0]) :
my_fp_classf(&inst->op1->f[0]);
*** 409,418 ****
--- 411,422 ----
case divsd:
if (t1 == fp_zero && t2 == fp_zero)
return fex_inv_zdz;
if (t1 == fp_infinity && t2 == fp_infinity)
return fex_inv_idi;
+ default:
+ break;
}
return (enum fex_exception)-1;
}
*** 636,645 ****
--- 640,651 ----
case comisd:
info->op = fex_cmp;
info->res.type = fex_nodata;
sse_comisd(&info->op1.val.d, &info->op2.val.d);
break;
+ default:
+ break;
}
} else {
if (inst->op == cvtsi2ss) {
info->op1.type = fex_int;
info->op1.val.i = inst->op2->i[0];
*** 789,798 ****
--- 795,806 ----
case comiss:
info->op = fex_cmp;
info->res.type = fex_nodata;
sse_comiss(&info->op1.val.f, &info->op2.val.f);
break;
+ default:
+ break;
}
}
__fenv_getmxcsr(&mxcsr);
info->flags = mxcsr & 0x3d;
__fenv_setmxcsr(&oldmxcsr);
*** 1081,1090 ****
--- 1089,1100 ----
for (i = 0; i < 2; i++) {
dummy.op1 = (sseoperand_t *)&inst->op1->f[i];
dummy.op2 = (sseoperand_t *)&inst->op2->d[i];
e[i] = __fex_get_sse_op(uap, &dummy, &info[i]);
}
+ default:
+ break;
}
}
/*
* Store the result value from *info in the destination of the scalar
*** 1096,1109 ****
*/
void
__fex_st_sse_result(ucontext_t *uap, sseinst_t *inst, enum fex_exception e,
fex_info_t *info)
{
! int i;
! long long l;
! float f, fscl;
! double d, dscl;
/* for compares that write eflags, just set the flags
to indicate "unordered" */
if (inst->op == ucomiss || inst->op == comiss ||
inst->op == ucomisd || inst->op == comisd) {
--- 1106,1119 ----
*/
void
__fex_st_sse_result(ucontext_t *uap, sseinst_t *inst, enum fex_exception e,
fex_info_t *info)
{
! int i = 0;
! long long l = 0L;;
! float f = 0.0, fscl;
! double d = 0.0L, dscl;
/* for compares that write eflags, just set the flags
to indicate "unordered" */
if (inst->op == ucomiss || inst->op == comiss ||
inst->op == ucomisd || inst->op == comisd) {
*** 1226,1235 ****
--- 1236,1248 ----
break;
case fex_ldouble:
i = info->res.val.q;
break;
+
+ default:
+ break;
}
inst->op1->i[0] = i;
} else if (inst->op == cmpsd || inst->op == cvttss2siq ||
inst->op == cvtss2siq || inst->op == cvttsd2siq ||
inst->op == cvtsd2siq) {
*** 1251,1260 ****
--- 1264,1276 ----
break;
case fex_ldouble:
l = info->res.val.q;
break;
+
+ default:
+ break;
}
inst->op1->l[0] = l;
} else if ((((int)inst->op & DOUBLE) && inst->op != cvtsd2ss) ||
inst->op == cvtss2sd) {
switch (info->res.type) {
*** 1275,1284 ****
--- 1291,1303 ----
break;
case fex_ldouble:
d = info->res.val.q;
break;
+
+ default:
+ break;
}
inst->op1->d[0] = d;
} else {
switch (info->res.type) {
case fex_int:
*** 1298,1307 ****
--- 1317,1329 ----
break;
case fex_ldouble:
f = info->res.val.q;
break;
+
+ default:
+ break;
}
inst->op1->f[0] = f;
}
}
*** 1576,1582 ****
--- 1598,1608 ----
dummy.op2 = (sseoperand_t *)&inst->op2->d[i];
__fex_st_sse_result(uap, &dummy, e[i], &info[i]);
}
/* zero the high 64 bits of the destination */
inst->op1->l[1] = 0ll;
+
+ default:
+ break;
}
}
+