199 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
200 #define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */
201 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
202 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
203 #define E1000_RAL(_i) (((_i) <= 15) ? \
204 (0x05400 + ((_i) * 8)) : \
205 (0x054E0 + ((_i - 16) * 8)))
206 #define E1000_RAH(_i) (((_i) <= 15) ? \
207 (0x05404 + ((_i) * 8)) : \
208 (0x054E4 + ((_i - 16) * 8)))
209 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
210 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
211 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
212 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
213 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
214 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
215 #define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */
216 /* Packet Buffer DWORD (_n) */
217 #define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n)))
218 #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
219 /* Same as TXPBS, renamed for newer adpaters - RW */
220 #define E1000_ITPBS 0x03404
221 #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
222 #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
223 #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
224 #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
225 #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
226 #define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */
227 #define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */
228 #define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */
229 #define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */
230 #define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */
231 #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */
232 #define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
233 #define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
234 #define E1000_DTXMXSZRQ 0x03540 /* DMA Tx Max Total Allow Size Requests - RW */
235 #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
236 #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
237 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
238 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
239 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
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199 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
200 #define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */
201 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
202 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
203 #define E1000_RAL(_i) (((_i) <= 15) ? \
204 (0x05400 + ((_i) * 8)) : \
205 (0x054E0 + ((_i - 16) * 8)))
206 #define E1000_RAH(_i) (((_i) <= 15) ? \
207 (0x05404 + ((_i) * 8)) : \
208 (0x054E4 + ((_i - 16) * 8)))
209 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
210 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
211 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
212 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
213 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
214 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
215 #define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */
216 /* Packet Buffer DWORD (_n) */
217 #define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n)))
218 #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
219 /* Same as TXPBS, renamed for newer adapters - RW */
220 #define E1000_ITPBS 0x03404
221 #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
222 #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
223 #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
224 #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
225 #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
226 #define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */
227 #define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */
228 #define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */
229 #define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */
230 #define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */
231 #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */
232 #define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
233 #define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
234 #define E1000_DTXMXSZRQ 0x03540 /* DMA Tx Max Total Allow Size Requests - RW */
235 #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
236 #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
237 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
238 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
239 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
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