3217 cfgadm should spell "adaptors" correctly
Reviewed by: Alexander Eremin <alexander.r.eremin@gmail.com>
Reviewed by: David Hoeppner <0xffea@gmail.com>
Reviewed by: Gary Mills <gary_mills@fastmail.fm>
Reviewed by: Eric Schrock <Eric.Schrock@delphix.com>

          --- old/usr/src/uts/common/io/1394/adapters/hci1394_extern.c
          +++ new/usr/src/uts/common/io/1394/adapters/hci1394_extern.c

   1    1  /*
   2    2   * CDDL HEADER START
   3    3   *
   4    4   * The contents of this file are subject to the terms of the
   5    5   * Common Development and Distribution License, Version 1.0 only
   6    6   * (the "License").  You may not use this file except in compliance
   7    7   * with the License.
   8    8   *
   9    9   * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10   10   * or http://www.opensolaris.org/os/licensing.
  11   11   * See the License for the specific language governing permissions
  12   12   * and limitations under the License.
  13   13   *
  14   14   * When distributing Covered Code, include this CDDL HEADER in each
  15   15   * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16   16   * If applicable, add the following below this CDDL HEADER, with the

  17   17   * fields enclosed by brackets "[]" replaced with your own identifying
  18   18   * information: Portions Copyright [yyyy] [name of copyright owner]
  19   19   *
  20   20   * CDDL HEADER END
  21   21   */
  22   22  /*
  23   23   * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
  24   24   * All rights reserved.
  25   25   */
  26   26  
  27      -#pragma ident   "%Z%%M% %I%     %E% SMI"
  28      -
  29   27  /*
  30   28   * hci1394_extern.c
  31   29   *    Central location for externs.  There are two exceptions to this,
  32   30   *    hci1394_statep (located in hci1394.c) and hci1394_evts (located in
  33   31   *    hci1394_s1394if.c).
  34   32   */
  35   33  
  36   34  #include <sys/conf.h>
  37   35  #include <sys/ddi.h>
  38   36  #include <sys/modctl.h>

  39   37  #include <sys/stat.h>
  40   38  
  41   39  #include <sys/1394/h1394.h>
  42   40  
  43   41  #include <sys/1394/adapters/hci1394.h>
  44   42  

  45   43  
  46   44  
  47   45  /*
  48   46   * The 1394 bus ticks are in 125uS increments.  split_timeout is represented in
  49   47   * 1394 bus ticks.  800 bus ticks is 100mS.
  50   48   */
  51   49  uint32_t hci1394_split_timeout = 800;
  52   50  
  53   51  
  54   52  /*
  55      - * 1394 address map for OpenHCI adpaters.
       53 + * 1394 address map for OpenHCI adapters.
  56   54   *
  57   55   * This is what is reported to the services layer.  The hci1394 driver does not
  58   56   * modify the HW to reflect this.  This should reflect what the OpenHCI 1.0 HW
  59   57   * is set to.  The comments below give the actual address ranges where the
  60   58   * actual structure has the format of - start address, size, type.
  61   59   *
  62   60   * physical =>          0x0000000000000000 - 0x00000000FFFFFFFF
  63   61   * posted write =>      0x0000000100000000 - 0x0000FFFEFFFFFFFF
  64   62   * normal =>            0x0000FFFF00000000 - 0x0000FFFFEFFFFFFF
  65   63   * csr =>               0x0000FFFFF0000000 - 0x0000FFFFFFFFFFFF

  66   64   */
  67   65  h1394_addr_map_t hci1394_addr_map[HCI1394_ADDR_MAP_SIZE] = {
  68   66          {0x0000000000000000, 0x0000000100000000, H1394_ADDR_PHYSICAL},
  69   67          {0x0000000100000000, 0x0000FFFE00000000, H1394_ADDR_POSTED_WRITE},
  70   68          {0x0000FFFF00000000, 0x00000000F0000000, H1394_ADDR_NORMAL},
  71   69          {0x0000FFFFF0000000, 0x0000000010000000, H1394_ADDR_CSR}
  72   70  };
  73   71  
  74   72  
  75   73  /* Max number of uS to wait for phy reads & writes to finish */
  76   74  uint_t hci1394_phy_delay_uS = 10;
  77   75  
  78   76  /*
  79   77   * Time to wait for PHY to SCLK to be stable. There does not seem to be standard
  80   78   * time for how long wait for the PHY to come up. The problem is that the PHY
  81   79   * provides a clock to the link layer and if that is not stable, we could get a
  82   80   * PCI timeout error when reading/writing a phy register (and maybe an OpenHCI
  83   81   * register?)  This used to be set to 10mS which works for just about every
  84   82   * adapter we tested on.  We got a new TI adapter which would crash the system
  85   83   * once in a while if nothing (1394 device) was plugged into the adapter?
  86   84   * Changing this delay to 50mS made that problem go away.
  87   85   *
  88   86   * NOTE: Do not this delay unless you know what your doing!!!!
  89   87   */
  90   88  uint_t hci1394_phy_stabilization_delay_uS = 50000;

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