1 /******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "ixgbe_x550.h"
36 #include "ixgbe_x540.h"
37 #include "ixgbe_type.h"
38 #include "ixgbe_api.h"
39 #include "ixgbe_common.h"
40 #include "ixgbe_phy.h"
41
42 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
43
44 /**
45 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
46 * @hw: pointer to hardware structure
47 *
48 * Initialize the function pointers and assign the MAC type for X550.
49 * Does not touch the hardware.
50 **/
51 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
52 {
53 struct ixgbe_mac_info *mac = &hw->mac;
54 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55 s32 ret_val;
56
57 DEBUGFUNC("ixgbe_init_ops_X550");
58
59 ret_val = ixgbe_init_ops_X540(hw);
60 mac->ops.dmac_config = ixgbe_dmac_config_X550;
61 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
62 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
63 mac->ops.setup_eee = ixgbe_setup_eee_X550;
64 mac->ops.set_source_address_pruning =
65 ixgbe_set_source_address_pruning_X550;
66 mac->ops.set_ethertype_anti_spoofing =
67 ixgbe_set_ethertype_anti_spoofing_X550;
68
69 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
70 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
71 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
72 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
73 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
74 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
75 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
76 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
77 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
78
79 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
80 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
81 mac->ops.mdd_event = ixgbe_mdd_event_X550;
82 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
83 mac->ops.disable_rx = ixgbe_disable_rx_x550;
84 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
85 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
86 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
87 }
88 return ret_val;
89 }
90
91 /**
92 * ixgbe_read_cs4227 - Read CS4227 register
93 * @hw: pointer to hardware structure
94 * @reg: register number to write
95 * @value: pointer to receive value read
96 *
97 * Returns status code
98 **/
99 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
100 {
101 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
102 }
103
104 /**
105 * ixgbe_write_cs4227 - Write CS4227 register
106 * @hw: pointer to hardware structure
107 * @reg: register number to write
108 * @value: value to write to register
109 *
110 * Returns status code
111 **/
112 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
113 {
114 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
115 }
116
117 /**
118 * ixgbe_read_pe - Read register from port expander
119 * @hw: pointer to hardware structure
120 * @reg: register number to read
121 * @value: pointer to receive read value
122 *
123 * Returns status code
124 **/
125 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
126 {
127 s32 status;
128
129 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
130 if (status != IXGBE_SUCCESS)
131 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
132 "port expander access failed with %d\n", status);
133 return status;
134 }
135
136 /**
137 * ixgbe_write_pe - Write register to port expander
138 * @hw: pointer to hardware structure
139 * @reg: register number to write
140 * @value: value to write
141 *
142 * Returns status code
143 **/
144 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
145 {
146 s32 status;
147
148 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
149 if (status != IXGBE_SUCCESS)
150 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
151 "port expander access failed with %d\n", status);
152 return status;
153 }
154
155 /**
156 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
157 * @hw: pointer to hardware structure
158 *
159 * This function assumes that the caller has acquired the proper semaphore.
160 * Returns error code
161 **/
162 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
163 {
164 s32 status;
165 u32 retry;
166 u16 value;
167 u8 reg;
168
169 /* Trigger hard reset. */
170 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
171 if (status != IXGBE_SUCCESS)
172 return status;
173 reg |= IXGBE_PE_BIT1;
174 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
175 if (status != IXGBE_SUCCESS)
176 return status;
177
178 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
179 if (status != IXGBE_SUCCESS)
180 return status;
181 reg &= ~IXGBE_PE_BIT1;
182 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
183 if (status != IXGBE_SUCCESS)
184 return status;
185
186 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
187 if (status != IXGBE_SUCCESS)
188 return status;
189 reg &= ~IXGBE_PE_BIT1;
190 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
191 if (status != IXGBE_SUCCESS)
192 return status;
193
194 usec_delay(IXGBE_CS4227_RESET_HOLD);
195
196 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
197 if (status != IXGBE_SUCCESS)
198 return status;
199 reg |= IXGBE_PE_BIT1;
200 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
201 if (status != IXGBE_SUCCESS)
202 return status;
203
204 /* Wait for the reset to complete. */
205 msec_delay(IXGBE_CS4227_RESET_DELAY);
206 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
207 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
208 &value);
209 if (status == IXGBE_SUCCESS &&
210 value == IXGBE_CS4227_EEPROM_LOAD_OK)
211 break;
212 msec_delay(IXGBE_CS4227_CHECK_DELAY);
213 }
214 if (retry == IXGBE_CS4227_RETRIES) {
215 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
216 "CS4227 reset did not complete.");
217 return IXGBE_ERR_PHY;
218 }
219
220 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
221 if (status != IXGBE_SUCCESS ||
222 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
223 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
224 "CS4227 EEPROM did not load successfully.");
225 return IXGBE_ERR_PHY;
226 }
227
228 return IXGBE_SUCCESS;
229 }
230
231 /**
232 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
233 * @hw: pointer to hardware structure
234 **/
235 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
236 {
237 s32 status = IXGBE_SUCCESS;
238 u32 swfw_mask = hw->phy.phy_semaphore_mask;
239 u16 value = 0;
240 u8 retry;
241
242 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
243 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
244 if (status != IXGBE_SUCCESS) {
245 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
246 "semaphore failed with %d", status);
247 msec_delay(IXGBE_CS4227_CHECK_DELAY);
248 continue;
249 }
250
251 /* Get status of reset flow. */
252 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
253
254 if (status == IXGBE_SUCCESS &&
255 value == IXGBE_CS4227_RESET_COMPLETE)
256 goto out;
257
258 if (status != IXGBE_SUCCESS ||
259 value != IXGBE_CS4227_RESET_PENDING)
260 break;
261
262 /* Reset is pending. Wait and check again. */
263 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
264 msec_delay(IXGBE_CS4227_CHECK_DELAY);
265 }
266
267 /* If still pending, assume other instance failed. */
268 if (retry == IXGBE_CS4227_RETRIES) {
269 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
270 if (status != IXGBE_SUCCESS) {
271 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
272 "semaphore failed with %d", status);
273 return;
274 }
275 }
276
277 /* Reset the CS4227. */
278 status = ixgbe_reset_cs4227(hw);
279 if (status != IXGBE_SUCCESS) {
280 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
281 "CS4227 reset failed: %d", status);
282 goto out;
283 }
284
285 /* Reset takes so long, temporarily release semaphore in case the
286 * other driver instance is waiting for the reset indication.
287 */
288 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
289 IXGBE_CS4227_RESET_PENDING);
290 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
291 msec_delay(10);
292 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
293 if (status != IXGBE_SUCCESS) {
294 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
295 "semaphore failed with %d", status);
296 return;
297 }
298
299 /* Record completion for next time. */
300 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
301 IXGBE_CS4227_RESET_COMPLETE);
302
303 out:
304 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
305 msec_delay(hw->eeprom.semaphore_delay);
306 }
307
308 /**
309 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
310 * @hw: pointer to hardware structure
311 **/
312 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
313 {
314 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
315
316 if (hw->bus.lan_id) {
317 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
318 esdp |= IXGBE_ESDP_SDP1_DIR;
319 }
320 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
321 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
322 IXGBE_WRITE_FLUSH(hw);
323 }
324
325 /**
326 * ixgbe_identify_phy_x550em - Get PHY type based on device id
327 * @hw: pointer to hardware structure
328 *
329 * Returns error code
330 */
331 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
332 {
333 switch (hw->device_id) {
334 case IXGBE_DEV_ID_X550EM_X_SFP:
335 /* set up for CS4227 usage */
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
337 ixgbe_setup_mux_ctl(hw);
338 ixgbe_check_cs4227(hw);
339
340 return ixgbe_identify_module_generic(hw);
341 break;
342 case IXGBE_DEV_ID_X550EM_X_KX4:
343 hw->phy.type = ixgbe_phy_x550em_kx4;
344 break;
345 case IXGBE_DEV_ID_X550EM_X_KR:
346 hw->phy.type = ixgbe_phy_x550em_kr;
347 break;
348 case IXGBE_DEV_ID_X550EM_X_1G_T:
349 case IXGBE_DEV_ID_X550EM_X_10G_T:
350 return ixgbe_identify_phy_generic(hw);
351 default:
352 break;
353 }
354 return IXGBE_SUCCESS;
355 }
356
357 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
358 u32 device_type, u16 *phy_data)
359 {
360 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
361 return IXGBE_NOT_IMPLEMENTED;
362 }
363
364 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
365 u32 device_type, u16 phy_data)
366 {
367 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
368 return IXGBE_NOT_IMPLEMENTED;
369 }
370
371 /**
372 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
373 * @hw: pointer to hardware structure
374 *
375 * Initialize the function pointers and for MAC type X550EM.
376 * Does not touch the hardware.
377 **/
378 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
379 {
380 struct ixgbe_mac_info *mac = &hw->mac;
381 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
382 struct ixgbe_phy_info *phy = &hw->phy;
383 s32 ret_val;
384
385 DEBUGFUNC("ixgbe_init_ops_X550EM");
386
387 /* Similar to X550 so start there. */
388 ret_val = ixgbe_init_ops_X550(hw);
389
390 /* Since this function eventually calls
391 * ixgbe_init_ops_540 by design, we are setting
392 * the pointers to NULL explicitly here to overwrite
393 * the values being set in the x540 function.
394 */
395
396 /* FCOE not supported in x550EM */
397 mac->ops.get_san_mac_addr = NULL;
398 mac->ops.set_san_mac_addr = NULL;
399 mac->ops.get_wwn_prefix = NULL;
400 mac->ops.get_fcoe_boot_status = NULL;
401
402 /* IPsec not supported in x550EM */
403 mac->ops.disable_sec_rx_path = NULL;
404 mac->ops.enable_sec_rx_path = NULL;
405
406 /* AUTOC register is not present in x550EM. */
407 mac->ops.prot_autoc_read = NULL;
408 mac->ops.prot_autoc_write = NULL;
409
410 /* X550EM bus type is internal*/
411 hw->bus.type = ixgbe_bus_type_internal;
412 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
413
414 if (hw->mac.type == ixgbe_mac_X550EM_x) {
415 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
416 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
417 }
418
419 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
420 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
421 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
422 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
423 mac->ops.get_supported_physical_layer =
424 ixgbe_get_supported_physical_layer_X550em;
425
426 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
427 mac->ops.setup_fc = ixgbe_setup_fc_generic;
428 else
429 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
430
431 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
432 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
433
434 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
435 mac->ops.setup_eee = NULL;
436
437 /* PHY */
438 phy->ops.init = ixgbe_init_phy_ops_X550em;
439 phy->ops.identify = ixgbe_identify_phy_x550em;
440 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
441 phy->ops.set_phy_power = NULL;
442
443
444 /* EEPROM */
445 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
446 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
447 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
448 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
449 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
450 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
451 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
452 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
453
454 return ret_val;
455 }
456
457 /**
458 * ixgbe_dmac_config_X550
459 * @hw: pointer to hardware structure
460 *
461 * Configure DMA coalescing. If enabling dmac, dmac is activated.
462 * When disabling dmac, dmac enable dmac bit is cleared.
463 **/
464 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
465 {
466 u32 reg, high_pri_tc;
467
468 DEBUGFUNC("ixgbe_dmac_config_X550");
469
470 /* Disable DMA coalescing before configuring */
471 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
472 reg &= ~IXGBE_DMACR_DMAC_EN;
473 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
474
475 /* Disable DMA Coalescing if the watchdog timer is 0 */
476 if (!hw->mac.dmac_config.watchdog_timer)
477 goto out;
478
479 ixgbe_dmac_config_tcs_X550(hw);
480
481 /* Configure DMA Coalescing Control Register */
482 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
483
484 /* Set the watchdog timer in units of 40.96 usec */
485 reg &= ~IXGBE_DMACR_DMACWT_MASK;
486 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
487
488 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
489 /* If fcoe is enabled, set high priority traffic class */
490 if (hw->mac.dmac_config.fcoe_en) {
491 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
492 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
493 IXGBE_DMACR_HIGH_PRI_TC_MASK);
494 }
495 reg |= IXGBE_DMACR_EN_MNG_IND;
496
497 /* Enable DMA coalescing after configuration */
498 reg |= IXGBE_DMACR_DMAC_EN;
499 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
500
501 out:
502 return IXGBE_SUCCESS;
503 }
504
505 /**
506 * ixgbe_dmac_config_tcs_X550
507 * @hw: pointer to hardware structure
508 *
509 * Configure DMA coalescing threshold per TC. The dmac enable bit must
510 * be cleared before configuring.
511 **/
512 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
513 {
514 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
515
516 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
517
518 /* Configure DMA coalescing enabled */
519 switch (hw->mac.dmac_config.link_speed) {
520 case IXGBE_LINK_SPEED_100_FULL:
521 pb_headroom = IXGBE_DMACRXT_100M;
522 break;
523 case IXGBE_LINK_SPEED_1GB_FULL:
524 pb_headroom = IXGBE_DMACRXT_1G;
525 break;
526 default:
527 pb_headroom = IXGBE_DMACRXT_10G;
528 break;
529 }
530
531 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
532 IXGBE_MHADD_MFS_SHIFT) / 1024);
533
534 /* Set the per Rx packet buffer receive threshold */
535 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
536 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
537 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
538
539 if (tc < hw->mac.dmac_config.num_tcs) {
540 /* Get Rx PB size */
541 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
542 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
543 IXGBE_RXPBSIZE_SHIFT;
544
545 /* Calculate receive buffer threshold in kilobytes */
546 if (rx_pb_size > pb_headroom)
547 rx_pb_size = rx_pb_size - pb_headroom;
548 else
549 rx_pb_size = 0;
550
551 /* Minimum of MFS shall be set for DMCTH */
552 reg |= (rx_pb_size > maxframe_size_kb) ?
553 rx_pb_size : maxframe_size_kb;
554 }
555 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
556 }
557 return IXGBE_SUCCESS;
558 }
559
560 /**
561 * ixgbe_dmac_update_tcs_X550
562 * @hw: pointer to hardware structure
563 *
564 * Disables dmac, updates per TC settings, and then enables dmac.
565 **/
566 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
567 {
568 u32 reg;
569
570 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
571
572 /* Disable DMA coalescing before configuring */
573 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
574 reg &= ~IXGBE_DMACR_DMAC_EN;
575 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
576
577 ixgbe_dmac_config_tcs_X550(hw);
578
579 /* Enable DMA coalescing after configuration */
580 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
581 reg |= IXGBE_DMACR_DMAC_EN;
582 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
583
584 return IXGBE_SUCCESS;
585 }
586
587 /**
588 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
589 * @hw: pointer to hardware structure
590 *
591 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
592 * ixgbe_hw struct in order to set up EEPROM access.
593 **/
594 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
595 {
596 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
597 u32 eec;
598 u16 eeprom_size;
599
600 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
601
602 if (eeprom->type == ixgbe_eeprom_uninitialized) {
603 eeprom->semaphore_delay = 10;
604 eeprom->type = ixgbe_flash;
605
606 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
607 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
608 IXGBE_EEC_SIZE_SHIFT);
609 eeprom->word_size = 1 << (eeprom_size +
610 IXGBE_EEPROM_WORD_SIZE_SHIFT);
611
612 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
613 eeprom->type, eeprom->word_size);
614 }
615
616 return IXGBE_SUCCESS;
617 }
618
619 /**
620 * ixgbe_setup_eee_X550 - Enable/disable EEE support
621 * @hw: pointer to the HW structure
622 * @enable_eee: boolean flag to enable EEE
623 *
624 * Enable/disable EEE based on enable_eee flag.
625 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
626 * are modified.
627 *
628 **/
629 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
630 {
631 u32 eeer;
632 u16 autoneg_eee_reg;
633 u32 link_reg;
634 s32 status;
635 u32 fuse;
636
637 DEBUGFUNC("ixgbe_setup_eee_X550");
638
639 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
640 /* Enable or disable EEE per flag */
641 if (enable_eee) {
642 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
643
644 if (hw->mac.type == ixgbe_mac_X550) {
645 /* Advertise EEE capability */
646 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
647 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
648
649 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
650 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
651 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
652
653 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
654 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
655 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
656 /* Not supported on first revision. */
657 fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
658 if (!(fuse & IXGBE_FUSES0_REV1))
659 return IXGBE_SUCCESS;
660
661 status = ixgbe_read_iosf_sb_reg_x550(hw,
662 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
663 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
664 if (status != IXGBE_SUCCESS)
665 return status;
666
667 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
668 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
669
670 /* Don't advertise FEC capability when EEE enabled. */
671 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
672
673 status = ixgbe_write_iosf_sb_reg_x550(hw,
674 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
675 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
676 if (status != IXGBE_SUCCESS)
677 return status;
678 }
679 } else {
680 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
681
682 if (hw->mac.type == ixgbe_mac_X550) {
683 /* Disable advertised EEE capability */
684 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
685 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
686
687 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
688 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
689 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
690
691 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
692 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
693 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
694 status = ixgbe_read_iosf_sb_reg_x550(hw,
695 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
696 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
697 if (status != IXGBE_SUCCESS)
698 return status;
699
700 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
701 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
702
703 /* Advertise FEC capability when EEE is disabled. */
704 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
705
706 status = ixgbe_write_iosf_sb_reg_x550(hw,
707 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
708 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
709 if (status != IXGBE_SUCCESS)
710 return status;
711 }
712 }
713 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
714
715 return IXGBE_SUCCESS;
716 }
717
718 /**
719 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
720 * @hw: pointer to hardware structure
721 * @enable: enable or disable source address pruning
722 * @pool: Rx pool to set source address pruning for
723 **/
724 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
725 unsigned int pool)
726 {
727 u64 pfflp;
728
729 /* max rx pool is 63 */
730 if (pool > 63)
731 return;
732
733 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
734 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
735
736 if (enable)
737 pfflp |= (1ULL << pool);
738 else
739 pfflp &= ~(1ULL << pool);
740
741 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
742 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
743 }
744
745 /**
746 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
747 * @hw: pointer to hardware structure
748 * @enable: enable or disable switch for Ethertype anti-spoofing
749 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
750 *
751 **/
752 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
753 bool enable, int vf)
754 {
755 int vf_target_reg = vf >> 3;
756 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
757 u32 pfvfspoof;
758
759 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
760
761 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
762 if (enable)
763 pfvfspoof |= (1 << vf_target_shift);
764 else
765 pfvfspoof &= ~(1 << vf_target_shift);
766
767 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
768 }
769
770 /**
771 * ixgbe_iosf_wait - Wait for IOSF command completion
772 * @hw: pointer to hardware structure
773 * @ctrl: pointer to location to receive final IOSF control value
774 *
775 * Returns failing status on timeout
776 *
777 * Note: ctrl can be NULL if the IOSF control register value is not needed
778 **/
779 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
780 {
781 u32 i, command = 0;
782
783 /* Check every 10 usec to see if the address cycle completed.
784 * The SB IOSF BUSY bit will clear when the operation is
785 * complete
786 */
787 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
788 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
789 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
790 break;
791 usec_delay(10);
792 }
793 if (ctrl)
794 *ctrl = command;
795 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
796 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
797 return IXGBE_ERR_PHY;
798 }
799
800 return IXGBE_SUCCESS;
801 }
802
803 /**
804 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
805 * device
806 * @hw: pointer to hardware structure
807 * @reg_addr: 32 bit PHY register to write
808 * @device_type: 3 bit device type
809 * @data: Data to write to the register
810 **/
811 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
812 u32 device_type, u32 data)
813 {
814 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
815 u32 command, error;
816 s32 ret;
817
818 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
819 if (ret != IXGBE_SUCCESS)
820 return ret;
821
822 ret = ixgbe_iosf_wait(hw, NULL);
823 if (ret != IXGBE_SUCCESS)
824 goto out;
825
826 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
827 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
828
829 /* Write IOSF control register */
830 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
831
832 /* Write IOSF data register */
833 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
834
835 ret = ixgbe_iosf_wait(hw, &command);
836
837 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
838 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
839 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
840 ERROR_REPORT2(IXGBE_ERROR_POLLING,
841 "Failed to write, error %x\n", error);
842 ret = IXGBE_ERR_PHY;
843 }
844
845 out:
846 ixgbe_release_swfw_semaphore(hw, gssr);
847 return ret;
848 }
849
850 /**
851 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
852 * device
853 * @hw: pointer to hardware structure
854 * @reg_addr: 32 bit PHY register to write
855 * @device_type: 3 bit device type
856 * @phy_data: Pointer to read data from the register
857 **/
858 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
859 u32 device_type, u32 *data)
860 {
861 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
862 u32 command, error;
863 s32 ret;
864
865 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
866 if (ret != IXGBE_SUCCESS)
867 return ret;
868
869 ret = ixgbe_iosf_wait(hw, NULL);
870 if (ret != IXGBE_SUCCESS)
871 goto out;
872
873 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
874 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
875
876 /* Write IOSF control register */
877 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
878
879 ret = ixgbe_iosf_wait(hw, &command);
880
881 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
882 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
883 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
884 ERROR_REPORT2(IXGBE_ERROR_POLLING,
885 "Failed to read, error %x\n", error);
886 ret = IXGBE_ERR_PHY;
887 }
888
889 if (ret == IXGBE_SUCCESS)
890 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
891
892 out:
893 ixgbe_release_swfw_semaphore(hw, gssr);
894 return ret;
895 }
896
897 /**
898 * ixgbe_disable_mdd_X550
899 * @hw: pointer to hardware structure
900 *
901 * Disable malicious driver detection
902 **/
903 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
904 {
905 u32 reg;
906
907 DEBUGFUNC("ixgbe_disable_mdd_X550");
908
909 /* Disable MDD for TX DMA and interrupt */
910 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
911 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
912 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
913
914 /* Disable MDD for RX and interrupt */
915 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
916 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
917 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
918 }
919
920 /**
921 * ixgbe_enable_mdd_X550
922 * @hw: pointer to hardware structure
923 *
924 * Enable malicious driver detection
925 **/
926 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
927 {
928 u32 reg;
929
930 DEBUGFUNC("ixgbe_enable_mdd_X550");
931
932 /* Enable MDD for TX DMA and interrupt */
933 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
934 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
935 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
936
937 /* Enable MDD for RX and interrupt */
938 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
939 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
940 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
941 }
942
943 /**
944 * ixgbe_restore_mdd_vf_X550
945 * @hw: pointer to hardware structure
946 * @vf: vf index
947 *
948 * Restore VF that was disabled during malicious driver detection event
949 **/
950 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
951 {
952 u32 idx, reg, num_qs, start_q, bitmask;
953
954 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
955
956 /* Map VF to queues */
957 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
958 switch (reg & IXGBE_MRQC_MRQE_MASK) {
959 case IXGBE_MRQC_VMDQRT8TCEN:
960 num_qs = 8; /* 16 VFs / pools */
961 bitmask = 0x000000FF;
962 break;
963 case IXGBE_MRQC_VMDQRSS32EN:
964 case IXGBE_MRQC_VMDQRT4TCEN:
965 num_qs = 4; /* 32 VFs / pools */
966 bitmask = 0x0000000F;
967 break;
968 default: /* 64 VFs / pools */
969 num_qs = 2;
970 bitmask = 0x00000003;
971 break;
972 }
973 start_q = vf * num_qs;
974
975 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
976 idx = start_q / 32;
977 reg = 0;
978 reg |= (bitmask << (start_q % 32));
979 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
980 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
981 }
982
983 /**
984 * ixgbe_mdd_event_X550
985 * @hw: pointer to hardware structure
986 * @vf_bitmap: vf bitmap of malicious vfs
987 *
988 * Handle malicious driver detection event.
989 **/
990 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
991 {
992 u32 wqbr;
993 u32 i, j, reg, q, shift, vf, idx;
994
995 DEBUGFUNC("ixgbe_mdd_event_X550");
996
997 /* figure out pool size for mapping to vf's */
998 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
999 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1000 case IXGBE_MRQC_VMDQRT8TCEN:
1001 shift = 3; /* 16 VFs / pools */
1002 break;
1003 case IXGBE_MRQC_VMDQRSS32EN:
1004 case IXGBE_MRQC_VMDQRT4TCEN:
1005 shift = 2; /* 32 VFs / pools */
1006 break;
1007 default:
1008 shift = 1; /* 64 VFs / pools */
1009 break;
1010 }
1011
1012 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1013 for (i = 0; i < 4; i++) {
1014 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1015 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1016
1017 if (!wqbr)
1018 continue;
1019
1020 /* Get malicious queue */
1021 for (j = 0; j < 32 && wqbr; j++) {
1022
1023 if (!(wqbr & (1 << j)))
1024 continue;
1025
1026 /* Get queue from bitmask */
1027 q = j + (i * 32);
1028
1029 /* Map queue to vf */
1030 vf = (q >> shift);
1031
1032 /* Set vf bit in vf_bitmap */
1033 idx = vf / 32;
1034 vf_bitmap[idx] |= (1 << (vf % 32));
1035 wqbr &= ~(1 << j);
1036 }
1037 }
1038 }
1039
1040 /**
1041 * ixgbe_get_media_type_X550em - Get media type
1042 * @hw: pointer to hardware structure
1043 *
1044 * Returns the media type (fiber, copper, backplane)
1045 */
1046 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1047 {
1048 enum ixgbe_media_type media_type;
1049
1050 DEBUGFUNC("ixgbe_get_media_type_X550em");
1051
1052 /* Detect if there is a copper PHY attached. */
1053 switch (hw->device_id) {
1054 case IXGBE_DEV_ID_X550EM_X_KR:
1055 case IXGBE_DEV_ID_X550EM_X_KX4:
1056 media_type = ixgbe_media_type_backplane;
1057 break;
1058 case IXGBE_DEV_ID_X550EM_X_SFP:
1059 media_type = ixgbe_media_type_fiber;
1060 break;
1061 case IXGBE_DEV_ID_X550EM_X_1G_T:
1062 case IXGBE_DEV_ID_X550EM_X_10G_T:
1063 media_type = ixgbe_media_type_copper;
1064 break;
1065 default:
1066 media_type = ixgbe_media_type_unknown;
1067 break;
1068 }
1069 return media_type;
1070 }
1071
1072 /**
1073 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1074 * @hw: pointer to hardware structure
1075 * @linear: TRUE if SFP module is linear
1076 */
1077 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1078 {
1079 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1080
1081 switch (hw->phy.sfp_type) {
1082 case ixgbe_sfp_type_not_present:
1083 return IXGBE_ERR_SFP_NOT_PRESENT;
1084 case ixgbe_sfp_type_da_cu_core0:
1085 case ixgbe_sfp_type_da_cu_core1:
1086 *linear = TRUE;
1087 break;
1088 case ixgbe_sfp_type_srlr_core0:
1089 case ixgbe_sfp_type_srlr_core1:
1090 case ixgbe_sfp_type_da_act_lmt_core0:
1091 case ixgbe_sfp_type_da_act_lmt_core1:
1092 case ixgbe_sfp_type_1g_sx_core0:
1093 case ixgbe_sfp_type_1g_sx_core1:
1094 case ixgbe_sfp_type_1g_lx_core0:
1095 case ixgbe_sfp_type_1g_lx_core1:
1096 *linear = FALSE;
1097 break;
1098 case ixgbe_sfp_type_unknown:
1099 case ixgbe_sfp_type_1g_cu_core0:
1100 case ixgbe_sfp_type_1g_cu_core1:
1101 default:
1102 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1103 }
1104
1105 return IXGBE_SUCCESS;
1106 }
1107
1108 /**
1109 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1110 * @hw: pointer to hardware structure
1111 *
1112 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1113 **/
1114 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1115 {
1116 s32 status;
1117 bool linear;
1118
1119 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1120
1121 status = ixgbe_identify_module_generic(hw);
1122
1123 if (status != IXGBE_SUCCESS)
1124 return status;
1125
1126 /* Check if SFP module is supported */
1127 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1128
1129 return status;
1130 }
1131
1132 /**
1133 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1134 * @hw: pointer to hardware structure
1135 */
1136 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1137 {
1138 s32 status;
1139 bool linear;
1140
1141 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1142
1143 /* Check if SFP module is supported */
1144 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1145
1146 if (status != IXGBE_SUCCESS)
1147 return status;
1148
1149 ixgbe_init_mac_link_ops_X550em(hw);
1150 hw->phy.ops.reset = NULL;
1151
1152 return IXGBE_SUCCESS;
1153 }
1154
1155 /**
1156 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1157 * @hw: pointer to hardware structure
1158 */
1159 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1160 {
1161 struct ixgbe_mac_info *mac = &hw->mac;
1162
1163 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1164
1165 switch (hw->mac.ops.get_media_type(hw)) {
1166 case ixgbe_media_type_fiber:
1167 /* CS4227 does not support autoneg, so disable the laser control
1168 * functions for SFP+ fiber
1169 */
1170 mac->ops.disable_tx_laser = NULL;
1171 mac->ops.enable_tx_laser = NULL;
1172 mac->ops.flap_tx_laser = NULL;
1173 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1174 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1175 mac->ops.set_rate_select_speed =
1176 ixgbe_set_soft_rate_select_speed;
1177 break;
1178 case ixgbe_media_type_copper:
1179 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1180 mac->ops.check_link = ixgbe_check_link_t_X550em;
1181 break;
1182 default:
1183 break;
1184 }
1185 }
1186
1187 /**
1188 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1189 * @hw: pointer to hardware structure
1190 * @speed: pointer to link speed
1191 * @autoneg: TRUE when autoneg or autotry is enabled
1192 */
1193 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1194 ixgbe_link_speed *speed,
1195 bool *autoneg)
1196 {
1197 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1198
1199 /* SFP */
1200 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1201
1202 /* CS4227 SFP must not enable auto-negotiation */
1203 *autoneg = FALSE;
1204
1205 /* Check if 1G SFP module. */
1206 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1207 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1208 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1209 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1210 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1211 return IXGBE_SUCCESS;
1212 }
1213
1214 /* Link capabilities are based on SFP */
1215 if (hw->phy.multispeed_fiber)
1216 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1217 IXGBE_LINK_SPEED_1GB_FULL;
1218 else
1219 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1220 } else {
1221 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1222 IXGBE_LINK_SPEED_1GB_FULL;
1223 *autoneg = TRUE;
1224 }
1225
1226 return IXGBE_SUCCESS;
1227 }
1228
1229 /**
1230 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1231 * @hw: pointer to hardware structure
1232 * @lsc: pointer to boolean flag which indicates whether external Base T
1233 * PHY interrupt is lsc
1234 *
1235 * Determime if external Base T PHY interrupt cause is high temperature
1236 * failure alarm or link status change.
1237 *
1238 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1239 * failure alarm, else return PHY access status.
1240 */
1241 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1242 {
1243 u32 status;
1244 u16 reg;
1245
1246 *lsc = FALSE;
1247
1248 /* Vendor alarm triggered */
1249 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1250 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1251 ®);
1252
1253 if (status != IXGBE_SUCCESS ||
1254 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1255 return status;
1256
1257 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1258 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1259 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1260 ®);
1261
1262 if (status != IXGBE_SUCCESS ||
1263 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1264 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1265 return status;
1266
1267 /* High temperature failure alarm triggered */
1268 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1269 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1270 ®);
1271
1272 if (status != IXGBE_SUCCESS)
1273 return status;
1274
1275 /* If high temperature failure, then return over temp error and exit */
1276 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1277 /* power down the PHY in case the PHY FW didn't already */
1278 ixgbe_set_copper_phy_power(hw, FALSE);
1279 return IXGBE_ERR_OVERTEMP;
1280 }
1281
1282 /* Vendor alarm 2 triggered */
1283 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1284 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1285
1286 if (status != IXGBE_SUCCESS ||
1287 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1288 return status;
1289
1290 /* link connect/disconnect event occurred */
1291 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1292 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1293
1294 if (status != IXGBE_SUCCESS)
1295 return status;
1296
1297 /* Indicate LSC */
1298 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1299 *lsc = TRUE;
1300
1301 return IXGBE_SUCCESS;
1302 }
1303
1304 /**
1305 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1306 * @hw: pointer to hardware structure
1307 *
1308 * Enable link status change and temperature failure alarm for the external
1309 * Base T PHY
1310 *
1311 * Returns PHY access status
1312 */
1313 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1314 {
1315 u32 status;
1316 u16 reg;
1317 bool lsc;
1318
1319 /* Clear interrupt flags */
1320 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1321
1322 /* Enable link status change alarm */
1323 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1324 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1325
1326 if (status != IXGBE_SUCCESS)
1327 return status;
1328
1329 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1330
1331 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1332 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1333
1334 if (status != IXGBE_SUCCESS)
1335 return status;
1336
1337 /* Enables high temperature failure alarm */
1338 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1339 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1340 ®);
1341
1342 if (status != IXGBE_SUCCESS)
1343 return status;
1344
1345 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1346
1347 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1348 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1349 reg);
1350
1351 if (status != IXGBE_SUCCESS)
1352 return status;
1353
1354 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1355 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1356 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1357 ®);
1358
1359 if (status != IXGBE_SUCCESS)
1360 return status;
1361
1362 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1363 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1364
1365 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1366 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1367 reg);
1368
1369 if (status != IXGBE_SUCCESS)
1370 return status;
1371
1372 /* Enable chip-wide vendor alarm */
1373 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1374 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1375 ®);
1376
1377 if (status != IXGBE_SUCCESS)
1378 return status;
1379
1380 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1381
1382 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1383 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1384 reg);
1385
1386 return status;
1387 }
1388
1389 /**
1390 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1391 * @hw: pointer to hardware structure
1392 * @speed: link speed
1393 *
1394 * Configures the integrated KR PHY.
1395 **/
1396 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1397 ixgbe_link_speed speed)
1398 {
1399 s32 status;
1400 u32 reg_val;
1401
1402 status = ixgbe_read_iosf_sb_reg_x550(hw,
1403 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1404 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1405 if (status)
1406 return status;
1407
1408 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1409 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1410 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1411
1412 /* Advertise 10G support. */
1413 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1414 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1415
1416 /* Advertise 1G support. */
1417 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1418 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1419
1420 /* Restart auto-negotiation. */
1421 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1422 status = ixgbe_write_iosf_sb_reg_x550(hw,
1423 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1424 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1425
1426 return status;
1427 }
1428
1429 /**
1430 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1431 * @hw: pointer to hardware structure
1432 *
1433 * Initialize any function pointers that were not able to be
1434 * set during init_shared_code because the PHY/SFP type was
1435 * not known. Perform the SFP init if necessary.
1436 */
1437 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1438 {
1439 struct ixgbe_phy_info *phy = &hw->phy;
1440 ixgbe_link_speed speed;
1441 s32 ret_val;
1442
1443 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1444
1445 hw->mac.ops.set_lan_id(hw);
1446
1447 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1448 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1449 ixgbe_setup_mux_ctl(hw);
1450
1451 /* Save NW management interface connected on board. This is used
1452 * to determine internal PHY mode.
1453 */
1454 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1455 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1456 speed = IXGBE_LINK_SPEED_10GB_FULL |
1457 IXGBE_LINK_SPEED_1GB_FULL;
1458 }
1459 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1460 }
1461
1462 /* Identify the PHY or SFP module */
1463 ret_val = phy->ops.identify(hw);
1464 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1465 return ret_val;
1466
1467 /* Setup function pointers based on detected hardware */
1468 ixgbe_init_mac_link_ops_X550em(hw);
1469 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1470 phy->ops.reset = NULL;
1471
1472 /* Set functions pointers based on phy type */
1473 switch (hw->phy.type) {
1474 case ixgbe_phy_x550em_kx4:
1475 phy->ops.setup_link = NULL;
1476 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1477 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1478 break;
1479 case ixgbe_phy_x550em_kr:
1480 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1481 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1482 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1483 break;
1484 case ixgbe_phy_x550em_ext_t:
1485 /* Save NW management interface connected on board. This is used
1486 * to determine internal PHY mode
1487 */
1488 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1489
1490 /* If internal link mode is XFI, then setup iXFI internal link,
1491 * else setup KR now.
1492 */
1493 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1494 phy->ops.setup_internal_link =
1495 ixgbe_setup_internal_phy_t_x550em;
1496 } else {
1497 speed = IXGBE_LINK_SPEED_10GB_FULL |
1498 IXGBE_LINK_SPEED_1GB_FULL;
1499 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1500 }
1501
1502 /* setup SW LPLU only for first revision */
1503 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1504 IXGBE_FUSES0_GROUP(0))))
1505 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1506
1507 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1508 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1509 break;
1510 default:
1511 break;
1512 }
1513 return ret_val;
1514 }
1515
1516 /**
1517 * ixgbe_reset_hw_X550em - Perform hardware reset
1518 * @hw: pointer to hardware structure
1519 *
1520 * Resets the hardware by resetting the transmit and receive units, masks
1521 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1522 * reset.
1523 */
1524 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1525 {
1526 ixgbe_link_speed link_speed;
1527 s32 status;
1528 u32 ctrl = 0;
1529 u32 i;
1530 u32 hlreg0;
1531 bool link_up = FALSE;
1532
1533 DEBUGFUNC("ixgbe_reset_hw_X550em");
1534
1535 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1536 status = hw->mac.ops.stop_adapter(hw);
1537 if (status != IXGBE_SUCCESS)
1538 return status;
1539
1540 /* flush pending Tx transactions */
1541 ixgbe_clear_tx_pending(hw);
1542
1543 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1544 /* Config MDIO clock speed before the first MDIO PHY access */
1545 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1546 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1547 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1548 }
1549
1550 /* PHY ops must be identified and initialized prior to reset */
1551 status = hw->phy.ops.init(hw);
1552
1553 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1554 return status;
1555
1556 /* start the external PHY */
1557 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1558 status = ixgbe_init_ext_t_x550em(hw);
1559 if (status)
1560 return status;
1561 }
1562
1563 /* Setup SFP module if there is one present. */
1564 if (hw->phy.sfp_setup_needed) {
1565 status = hw->mac.ops.setup_sfp(hw);
1566 hw->phy.sfp_setup_needed = FALSE;
1567 }
1568
1569 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1570 return status;
1571
1572 /* Reset PHY */
1573 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1574 hw->phy.ops.reset(hw);
1575
1576 mac_reset_top:
1577 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1578 * If link reset is used when link is up, it might reset the PHY when
1579 * mng is using it. If link is down or the flag to force full link
1580 * reset is set, then perform link reset.
1581 */
1582 ctrl = IXGBE_CTRL_LNK_RST;
1583 if (!hw->force_full_reset) {
1584 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1585 if (link_up)
1586 ctrl = IXGBE_CTRL_RST;
1587 }
1588
1589 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1590 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1591 IXGBE_WRITE_FLUSH(hw);
1592
1593 /* Poll for reset bit to self-clear meaning reset is complete */
1594 for (i = 0; i < 10; i++) {
1595 usec_delay(1);
1596 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1597 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1598 break;
1599 }
1600
1601 if (ctrl & IXGBE_CTRL_RST_MASK) {
1602 status = IXGBE_ERR_RESET_FAILED;
1603 DEBUGOUT("Reset polling failed to complete.\n");
1604 }
1605
1606 msec_delay(50);
1607
1608 /* Double resets are required for recovery from certain error
1609 * conditions. Between resets, it is necessary to stall to
1610 * allow time for any pending HW events to complete.
1611 */
1612 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1613 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1614 goto mac_reset_top;
1615 }
1616
1617 /* Store the permanent mac address */
1618 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1619
1620 /* Store MAC address from RAR0, clear receive address registers, and
1621 * clear the multicast table. Also reset num_rar_entries to 128,
1622 * since we modify this value when programming the SAN MAC address.
1623 */
1624 hw->mac.num_rar_entries = 128;
1625 hw->mac.ops.init_rx_addrs(hw);
1626
1627 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1628 ixgbe_setup_mux_ctl(hw);
1629
1630 return status;
1631 }
1632
1633 /**
1634 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1635 * @hw: pointer to hardware structure
1636 */
1637 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1638 {
1639 u32 status;
1640 u16 reg;
1641
1642 status = hw->phy.ops.read_reg(hw,
1643 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1644 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1645 ®);
1646
1647 if (status != IXGBE_SUCCESS)
1648 return status;
1649
1650 /* If PHY FW reset completed bit is set then this is the first
1651 * SW instance after a power on so the PHY FW must be un-stalled.
1652 */
1653 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1654 status = hw->phy.ops.read_reg(hw,
1655 IXGBE_MDIO_GLOBAL_RES_PR_10,
1656 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1657 ®);
1658
1659 if (status != IXGBE_SUCCESS)
1660 return status;
1661
1662 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1663
1664 status = hw->phy.ops.write_reg(hw,
1665 IXGBE_MDIO_GLOBAL_RES_PR_10,
1666 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1667 reg);
1668
1669 if (status != IXGBE_SUCCESS)
1670 return status;
1671 }
1672
1673 return status;
1674 }
1675
1676 /**
1677 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1678 * @hw: pointer to hardware structure
1679 *
1680 * Configures the integrated KR PHY.
1681 **/
1682 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1683 {
1684 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1685 }
1686
1687 /**
1688 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1689 * @hw: pointer to hardware structure
1690 *
1691 * Configure the external PHY and the integrated KR PHY for SFP support.
1692 **/
1693 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1694 ixgbe_link_speed speed,
1695 bool autoneg_wait_to_complete)
1696 {
1697 s32 ret_val;
1698 u16 reg_slice, reg_val;
1699 bool setup_linear = FALSE;
1700 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1701
1702 /* Check if SFP module is supported and linear */
1703 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1704
1705 /* If no SFP module present, then return success. Return success since
1706 * there is no reason to configure CS4227 and SFP not present error is
1707 * not excepted in the setup MAC link flow.
1708 */
1709 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1710 return IXGBE_SUCCESS;
1711
1712 if (ret_val != IXGBE_SUCCESS)
1713 return ret_val;
1714
1715 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1716 /* Configure CS4227 LINE side to 10G SR. */
1717 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1718 (hw->bus.lan_id << 12);
1719 reg_val = IXGBE_CS4227_SPEED_10G;
1720 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1721 reg_val);
1722
1723 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1724 (hw->bus.lan_id << 12);
1725 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1726 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1727 reg_val);
1728
1729 /* Configure CS4227 for HOST connection rate then type. */
1730 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1731 (hw->bus.lan_id << 12);
1732 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1733 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1734 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1735 reg_val);
1736
1737 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1738 (hw->bus.lan_id << 12);
1739 if (setup_linear)
1740 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1741 else
1742 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1743 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1744 reg_val);
1745
1746 /* Setup XFI internal link. */
1747 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1748 } else {
1749 /* Configure internal PHY for KR/KX. */
1750 ixgbe_setup_kr_speed_x550em(hw, speed);
1751
1752 /* Configure CS4227 LINE side to proper mode. */
1753 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1754 (hw->bus.lan_id << 12);
1755 if (setup_linear)
1756 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1757 else
1758 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1759 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1760 reg_val);
1761 }
1762 return ret_val;
1763 }
1764
1765 /**
1766 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1767 * @hw: pointer to hardware structure
1768 * @speed: the link speed to force
1769 *
1770 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1771 * internal and external PHY at a specific speed, without autonegotiation.
1772 **/
1773 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1774 {
1775 s32 status;
1776 u32 reg_val;
1777
1778 /* Disable AN and force speed to 10G Serial. */
1779 status = ixgbe_read_iosf_sb_reg_x550(hw,
1780 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1781 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1782 if (status != IXGBE_SUCCESS)
1783 return status;
1784
1785 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1786 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1787
1788 /* Select forced link speed for internal PHY. */
1789 switch (*speed) {
1790 case IXGBE_LINK_SPEED_10GB_FULL:
1791 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1792 break;
1793 case IXGBE_LINK_SPEED_1GB_FULL:
1794 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1795 break;
1796 default:
1797 /* Other link speeds are not supported by internal KR PHY. */
1798 return IXGBE_ERR_LINK_SETUP;
1799 }
1800
1801 status = ixgbe_write_iosf_sb_reg_x550(hw,
1802 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1803 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1804 if (status != IXGBE_SUCCESS)
1805 return status;
1806
1807 /* Disable training protocol FSM. */
1808 status = ixgbe_read_iosf_sb_reg_x550(hw,
1809 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1810 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1811 if (status != IXGBE_SUCCESS)
1812 return status;
1813 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1814 status = ixgbe_write_iosf_sb_reg_x550(hw,
1815 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1816 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1817 if (status != IXGBE_SUCCESS)
1818 return status;
1819
1820 /* Disable Flex from training TXFFE. */
1821 status = ixgbe_read_iosf_sb_reg_x550(hw,
1822 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1823 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1824 if (status != IXGBE_SUCCESS)
1825 return status;
1826 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1827 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1828 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1829 status = ixgbe_write_iosf_sb_reg_x550(hw,
1830 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1831 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1832 if (status != IXGBE_SUCCESS)
1833 return status;
1834 status = ixgbe_read_iosf_sb_reg_x550(hw,
1835 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1836 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1837 if (status != IXGBE_SUCCESS)
1838 return status;
1839 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1840 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1841 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1842 status = ixgbe_write_iosf_sb_reg_x550(hw,
1843 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1844 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1845 if (status != IXGBE_SUCCESS)
1846 return status;
1847
1848 /* Enable override for coefficients. */
1849 status = ixgbe_read_iosf_sb_reg_x550(hw,
1850 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1851 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1852 if (status != IXGBE_SUCCESS)
1853 return status;
1854 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1855 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1856 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1857 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1858 status = ixgbe_write_iosf_sb_reg_x550(hw,
1859 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1860 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1861 if (status != IXGBE_SUCCESS)
1862 return status;
1863
1864 /* Toggle port SW reset by AN reset. */
1865 status = ixgbe_read_iosf_sb_reg_x550(hw,
1866 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1867 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1868 if (status != IXGBE_SUCCESS)
1869 return status;
1870 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1871 status = ixgbe_write_iosf_sb_reg_x550(hw,
1872 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1873 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1874
1875 return status;
1876 }
1877
1878 /**
1879 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1880 * @hw: address of hardware structure
1881 * @link_up: address of boolean to indicate link status
1882 *
1883 * Returns error code if unable to get link status.
1884 */
1885 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1886 {
1887 u32 ret;
1888 u16 autoneg_status;
1889
1890 *link_up = FALSE;
1891
1892 /* read this twice back to back to indicate current status */
1893 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1894 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1895 &autoneg_status);
1896 if (ret != IXGBE_SUCCESS)
1897 return ret;
1898
1899 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1900 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1901 &autoneg_status);
1902 if (ret != IXGBE_SUCCESS)
1903 return ret;
1904
1905 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1906
1907 return IXGBE_SUCCESS;
1908 }
1909
1910 /**
1911 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1912 * @hw: point to hardware structure
1913 *
1914 * Configures the link between the integrated KR PHY and the external X557 PHY
1915 * The driver will call this function when it gets a link status change
1916 * interrupt from the X557 PHY. This function configures the link speed
1917 * between the PHYs to match the link speed of the BASE-T link.
1918 *
1919 * A return of a non-zero value indicates an error, and the base driver should
1920 * not report link up.
1921 */
1922 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1923 {
1924 ixgbe_link_speed force_speed;
1925 bool link_up;
1926 u32 status;
1927 u16 speed;
1928
1929 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1930 return IXGBE_ERR_CONFIG;
1931
1932 /* If link is not up, then there is no setup necessary so return */
1933 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1934 if (status != IXGBE_SUCCESS)
1935 return status;
1936
1937 if (!link_up)
1938 return IXGBE_SUCCESS;
1939
1940 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1941 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1942 &speed);
1943 if (status != IXGBE_SUCCESS)
1944 return status;
1945
1946 /* If link is not still up, then no setup is necessary so return */
1947 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1948 if (status != IXGBE_SUCCESS)
1949 return status;
1950 if (!link_up)
1951 return IXGBE_SUCCESS;
1952
1953 /* clear everything but the speed and duplex bits */
1954 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1955
1956 switch (speed) {
1957 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1958 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1959 break;
1960 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1961 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1962 break;
1963 default:
1964 /* Internal PHY does not support anything else */
1965 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1966 }
1967
1968 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1969 }
1970
1971 /**
1972 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1973 * @hw: pointer to hardware structure
1974 *
1975 * Configures the integrated KR PHY to use internal loopback mode.
1976 **/
1977 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1978 {
1979 s32 status;
1980 u32 reg_val;
1981
1982 /* Disable AN and force speed to 10G Serial. */
1983 status = ixgbe_read_iosf_sb_reg_x550(hw,
1984 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1985 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1986 if (status != IXGBE_SUCCESS)
1987 return status;
1988 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1989 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1990 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1991 status = ixgbe_write_iosf_sb_reg_x550(hw,
1992 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1993 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1994 if (status != IXGBE_SUCCESS)
1995 return status;
1996
1997 /* Set near-end loopback clocks. */
1998 status = ixgbe_read_iosf_sb_reg_x550(hw,
1999 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2000 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2001 if (status != IXGBE_SUCCESS)
2002 return status;
2003 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2004 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2005 status = ixgbe_write_iosf_sb_reg_x550(hw,
2006 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2007 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2008 if (status != IXGBE_SUCCESS)
2009 return status;
2010
2011 /* Set loopback enable. */
2012 status = ixgbe_read_iosf_sb_reg_x550(hw,
2013 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2014 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2015 if (status != IXGBE_SUCCESS)
2016 return status;
2017 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2018 status = ixgbe_write_iosf_sb_reg_x550(hw,
2019 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2020 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2021 if (status != IXGBE_SUCCESS)
2022 return status;
2023
2024 /* Training bypass. */
2025 status = ixgbe_read_iosf_sb_reg_x550(hw,
2026 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2027 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2028 if (status != IXGBE_SUCCESS)
2029 return status;
2030 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2031 status = ixgbe_write_iosf_sb_reg_x550(hw,
2032 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2033 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2034
2035 return status;
2036 }
2037
2038 /**
2039 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2040 * assuming that the semaphore is already obtained.
2041 * @hw: pointer to hardware structure
2042 * @offset: offset of word in the EEPROM to read
2043 * @data: word read from the EEPROM
2044 *
2045 * Reads a 16 bit word from the EEPROM using the hostif.
2046 **/
2047 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2048 u16 *data)
2049 {
2050 s32 status;
2051 struct ixgbe_hic_read_shadow_ram buffer;
2052
2053 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2054 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2055 buffer.hdr.req.buf_lenh = 0;
2056 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2057 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2058
2059 /* convert offset from words to bytes */
2060 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2061 /* one word */
2062 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2063
2064 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2065 sizeof(buffer),
2066 IXGBE_HI_COMMAND_TIMEOUT, FALSE);
2067
2068 if (status)
2069 return status;
2070
2071 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2072 FW_NVM_DATA_OFFSET);
2073
2074 return 0;
2075 }
2076
2077 /**
2078 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2079 * @hw: pointer to hardware structure
2080 * @offset: offset of word in the EEPROM to read
2081 * @data: word read from the EEPROM
2082 *
2083 * Reads a 16 bit word from the EEPROM using the hostif.
2084 **/
2085 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2086 u16 *data)
2087 {
2088 s32 status = IXGBE_SUCCESS;
2089
2090 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2091
2092 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2093 IXGBE_SUCCESS) {
2094 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2095 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2096 } else {
2097 status = IXGBE_ERR_SWFW_SYNC;
2098 }
2099
2100 return status;
2101 }
2102
2103 /**
2104 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2105 * @hw: pointer to hardware structure
2106 * @offset: offset of word in the EEPROM to read
2107 * @words: number of words
2108 * @data: word(s) read from the EEPROM
2109 *
2110 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2111 **/
2112 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2113 u16 offset, u16 words, u16 *data)
2114 {
2115 struct ixgbe_hic_read_shadow_ram buffer;
2116 u32 current_word = 0;
2117 u16 words_to_read;
2118 s32 status;
2119 u32 i;
2120
2121 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2122
2123 /* Take semaphore for the entire operation. */
2124 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2125 if (status) {
2126 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2127 return status;
2128 }
2129 while (words) {
2130 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2131 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2132 else
2133 words_to_read = words;
2134
2135 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2136 buffer.hdr.req.buf_lenh = 0;
2137 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2138 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2139
2140 /* convert offset from words to bytes */
2141 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2142 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2143
2144 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2145 sizeof(buffer),
2146 IXGBE_HI_COMMAND_TIMEOUT,
2147 FALSE);
2148
2149 if (status) {
2150 DEBUGOUT("Host interface command failed\n");
2151 goto out;
2152 }
2153
2154 for (i = 0; i < words_to_read; i++) {
2155 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2156 2 * i;
2157 u32 value = IXGBE_READ_REG(hw, reg);
2158
2159 data[current_word] = (u16)(value & 0xffff);
2160 current_word++;
2161 i++;
2162 if (i < words_to_read) {
2163 value >>= 16;
2164 data[current_word] = (u16)(value & 0xffff);
2165 current_word++;
2166 }
2167 }
2168 words -= words_to_read;
2169 }
2170
2171 out:
2172 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2173 return status;
2174 }
2175
2176 /**
2177 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2178 * @hw: pointer to hardware structure
2179 * @offset: offset of word in the EEPROM to write
2180 * @data: word write to the EEPROM
2181 *
2182 * Write a 16 bit word to the EEPROM using the hostif.
2183 **/
2184 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2185 u16 data)
2186 {
2187 s32 status;
2188 struct ixgbe_hic_write_shadow_ram buffer;
2189
2190 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2191
2192 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2193 buffer.hdr.req.buf_lenh = 0;
2194 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2195 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2196
2197 /* one word */
2198 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2199 buffer.data = data;
2200 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2201
2202 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2203 sizeof(buffer),
2204 IXGBE_HI_COMMAND_TIMEOUT, FALSE);
2205
2206 return status;
2207 }
2208
2209 /**
2210 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2211 * @hw: pointer to hardware structure
2212 * @offset: offset of word in the EEPROM to write
2213 * @data: word write to the EEPROM
2214 *
2215 * Write a 16 bit word to the EEPROM using the hostif.
2216 **/
2217 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2218 u16 data)
2219 {
2220 s32 status = IXGBE_SUCCESS;
2221
2222 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2223
2224 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2225 IXGBE_SUCCESS) {
2226 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2227 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2228 } else {
2229 DEBUGOUT("write ee hostif failed to get semaphore");
2230 status = IXGBE_ERR_SWFW_SYNC;
2231 }
2232
2233 return status;
2234 }
2235
2236 /**
2237 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2238 * @hw: pointer to hardware structure
2239 * @offset: offset of word in the EEPROM to write
2240 * @words: number of words
2241 * @data: word(s) write to the EEPROM
2242 *
2243 * Write a 16 bit word(s) to the EEPROM using the hostif.
2244 **/
2245 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2246 u16 offset, u16 words, u16 *data)
2247 {
2248 s32 status = IXGBE_SUCCESS;
2249 u32 i = 0;
2250
2251 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2252
2253 /* Take semaphore for the entire operation. */
2254 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2255 if (status != IXGBE_SUCCESS) {
2256 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2257 goto out;
2258 }
2259
2260 for (i = 0; i < words; i++) {
2261 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2262 data[i]);
2263
2264 if (status != IXGBE_SUCCESS) {
2265 DEBUGOUT("Eeprom buffered write failed\n");
2266 break;
2267 }
2268 }
2269
2270 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2271 out:
2272
2273 return status;
2274 }
2275
2276 /**
2277 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2278 * @hw: pointer to hardware structure
2279 * @ptr: pointer offset in eeprom
2280 * @size: size of section pointed by ptr, if 0 first word will be used as size
2281 * @csum: address of checksum to update
2282 *
2283 * Returns error status for any failure
2284 */
2285 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2286 u16 size, u16 *csum, u16 *buffer,
2287 u32 buffer_size)
2288 {
2289 u16 buf[256];
2290 s32 status;
2291 u16 length, bufsz, i, start;
2292 u16 *local_buffer;
2293
2294 bufsz = sizeof(buf) / sizeof(buf[0]);
2295
2296 /* Read a chunk at the pointer location */
2297 if (!buffer) {
2298 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2299 if (status) {
2300 DEBUGOUT("Failed to read EEPROM image\n");
2301 return status;
2302 }
2303 local_buffer = buf;
2304 } else {
2305 if (buffer_size < ptr)
2306 return IXGBE_ERR_PARAM;
2307 local_buffer = &buffer[ptr];
2308 }
2309
2310 if (size) {
2311 start = 0;
2312 length = size;
2313 } else {
2314 start = 1;
2315 length = local_buffer[0];
2316
2317 /* Skip pointer section if length is invalid. */
2318 if (length == 0xFFFF || length == 0 ||
2319 (ptr + length) >= hw->eeprom.word_size)
2320 return IXGBE_SUCCESS;
2321 }
2322
2323 if (buffer && ((u32)start + (u32)length > buffer_size))
2324 return IXGBE_ERR_PARAM;
2325
2326 for (i = start; length; i++, length--) {
2327 if (i == bufsz && !buffer) {
2328 ptr += bufsz;
2329 i = 0;
2330 if (length < bufsz)
2331 bufsz = length;
2332
2333 /* Read a chunk at the pointer location */
2334 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2335 bufsz, buf);
2336 if (status) {
2337 DEBUGOUT("Failed to read EEPROM image\n");
2338 return status;
2339 }
2340 }
2341 *csum += local_buffer[i];
2342 }
2343 return IXGBE_SUCCESS;
2344 }
2345
2346 /**
2347 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2348 * @hw: pointer to hardware structure
2349 * @buffer: pointer to buffer containing calculated checksum
2350 * @buffer_size: size of buffer
2351 *
2352 * Returns a negative error code on error, or the 16-bit checksum
2353 **/
2354 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2355 {
2356 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2357 u16 *local_buffer;
2358 s32 status;
2359 u16 checksum = 0;
2360 u16 pointer, i, size;
2361
2362 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2363
2364 hw->eeprom.ops.init_params(hw);
2365
2366 if (!buffer) {
2367 /* Read pointer area */
2368 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2369 IXGBE_EEPROM_LAST_WORD + 1,
2370 eeprom_ptrs);
2371 if (status) {
2372 DEBUGOUT("Failed to read EEPROM image\n");
2373 return status;
2374 }
2375 local_buffer = eeprom_ptrs;
2376 } else {
2377 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2378 return IXGBE_ERR_PARAM;
2379 local_buffer = buffer;
2380 }
2381
2382 /*
2383 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2384 * checksum word itself
2385 */
2386 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2387 if (i != IXGBE_EEPROM_CHECKSUM)
2388 checksum += local_buffer[i];
2389
2390 /*
2391 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2392 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2393 */
2394 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2395 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2396 continue;
2397
2398 pointer = local_buffer[i];
2399
2400 /* Skip pointer section if the pointer is invalid. */
2401 if (pointer == 0xFFFF || pointer == 0 ||
2402 pointer >= hw->eeprom.word_size)
2403 continue;
2404
2405 switch (i) {
2406 case IXGBE_PCIE_GENERAL_PTR:
2407 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2408 break;
2409 case IXGBE_PCIE_CONFIG0_PTR:
2410 case IXGBE_PCIE_CONFIG1_PTR:
2411 size = IXGBE_PCIE_CONFIG_SIZE;
2412 break;
2413 default:
2414 size = 0;
2415 break;
2416 }
2417
2418 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2419 buffer, buffer_size);
2420 if (status)
2421 return status;
2422 }
2423
2424 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2425
2426 return (s32)checksum;
2427 }
2428
2429 /**
2430 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2431 * @hw: pointer to hardware structure
2432 *
2433 * Returns a negative error code on error, or the 16-bit checksum
2434 **/
2435 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2436 {
2437 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2438 }
2439
2440 /**
2441 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2442 * @hw: pointer to hardware structure
2443 * @checksum_val: calculated checksum
2444 *
2445 * Performs checksum calculation and validates the EEPROM checksum. If the
2446 * caller does not need checksum_val, the value can be NULL.
2447 **/
2448 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2449 {
2450 s32 status;
2451 u16 checksum;
2452 u16 read_checksum = 0;
2453
2454 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2455
2456 /* Read the first word from the EEPROM. If this times out or fails, do
2457 * not continue or we could be in for a very long wait while every
2458 * EEPROM read fails
2459 */
2460 status = hw->eeprom.ops.read(hw, 0, &checksum);
2461 if (status) {
2462 DEBUGOUT("EEPROM read failed\n");
2463 return status;
2464 }
2465
2466 status = hw->eeprom.ops.calc_checksum(hw);
2467 if (status < 0)
2468 return status;
2469
2470 checksum = (u16)(status & 0xffff);
2471
2472 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2473 &read_checksum);
2474 if (status)
2475 return status;
2476
2477 /* Verify read checksum from EEPROM is the same as
2478 * calculated checksum
2479 */
2480 if (read_checksum != checksum) {
2481 status = IXGBE_ERR_EEPROM_CHECKSUM;
2482 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2483 "Invalid EEPROM checksum");
2484 }
2485
2486 /* If the user cares, return the calculated checksum */
2487 if (checksum_val)
2488 *checksum_val = checksum;
2489
2490 return status;
2491 }
2492
2493 /**
2494 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2495 * @hw: pointer to hardware structure
2496 *
2497 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2498 * checksum and updates the EEPROM and instructs the hardware to update
2499 * the flash.
2500 **/
2501 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2502 {
2503 s32 status;
2504 u16 checksum = 0;
2505
2506 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2507
2508 /* Read the first word from the EEPROM. If this times out or fails, do
2509 * not continue or we could be in for a very long wait while every
2510 * EEPROM read fails
2511 */
2512 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2513 if (status) {
2514 DEBUGOUT("EEPROM read failed\n");
2515 return status;
2516 }
2517
2518 status = ixgbe_calc_eeprom_checksum_X550(hw);
2519 if (status < 0)
2520 return status;
2521
2522 checksum = (u16)(status & 0xffff);
2523
2524 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2525 checksum);
2526 if (status)
2527 return status;
2528
2529 status = ixgbe_update_flash_X550(hw);
2530
2531 return status;
2532 }
2533
2534 /**
2535 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2536 * @hw: pointer to hardware structure
2537 *
2538 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2539 **/
2540 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2541 {
2542 s32 status = IXGBE_SUCCESS;
2543 union ixgbe_hic_hdr2 buffer;
2544
2545 DEBUGFUNC("ixgbe_update_flash_X550");
2546
2547 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2548 buffer.req.buf_lenh = 0;
2549 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2550 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2551
2552 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2553 sizeof(buffer),
2554 IXGBE_HI_COMMAND_TIMEOUT, FALSE);
2555
2556 return status;
2557 }
2558
2559 /**
2560 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2561 * @hw: pointer to hardware structure
2562 *
2563 * Determines physical layer capabilities of the current configuration.
2564 **/
2565 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2566 {
2567 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2568 u16 ext_ability = 0;
2569
2570 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2571
2572 hw->phy.ops.identify(hw);
2573
2574 switch (hw->phy.type) {
2575 case ixgbe_phy_x550em_kr:
2576 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2577 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2578 break;
2579 case ixgbe_phy_x550em_kx4:
2580 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2581 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2582 break;
2583 case ixgbe_phy_x550em_ext_t:
2584 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2585 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2586 &ext_ability);
2587 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2588 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2589 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2590 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2591 break;
2592 default:
2593 break;
2594 }
2595
2596 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2597 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2598
2599 return physical_layer;
2600 }
2601
2602 /**
2603 * ixgbe_get_bus_info_x550em - Set PCI bus info
2604 * @hw: pointer to hardware structure
2605 *
2606 * Sets bus link width and speed to unknown because X550em is
2607 * not a PCI device.
2608 **/
2609 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2610 {
2611
2612 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2613
2614 hw->bus.width = ixgbe_bus_width_unknown;
2615 hw->bus.speed = ixgbe_bus_speed_unknown;
2616
2617 hw->mac.ops.set_lan_id(hw);
2618
2619 return IXGBE_SUCCESS;
2620 }
2621
2622 /**
2623 * ixgbe_disable_rx_x550 - Disable RX unit
2624 *
2625 * Enables the Rx DMA unit for x550
2626 **/
2627 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2628 {
2629 u32 rxctrl, pfdtxgswc;
2630 s32 status;
2631 struct ixgbe_hic_disable_rxen fw_cmd;
2632
2633 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2634
2635 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2636 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2637 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2638 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2639 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2640 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2641 hw->mac.set_lben = TRUE;
2642 } else {
2643 hw->mac.set_lben = FALSE;
2644 }
2645
2646 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2647 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2648 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2649 fw_cmd.port_number = (u8)hw->bus.lan_id;
2650
2651 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2652 sizeof(struct ixgbe_hic_disable_rxen),
2653 IXGBE_HI_COMMAND_TIMEOUT, TRUE);
2654
2655 /* If we fail - disable RX using register write */
2656 if (status) {
2657 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2658 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2659 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2660 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2661 }
2662 }
2663 }
2664 }
2665
2666 /**
2667 * ixgbe_enter_lplu_x550em - Transition to low power states
2668 * @hw: pointer to hardware structure
2669 *
2670 * Configures Low Power Link Up on transition to low power states
2671 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2672 * X557 PHY immediately prior to entering LPLU.
2673 **/
2674 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2675 {
2676 u16 an_10g_cntl_reg, autoneg_reg, speed;
2677 s32 status;
2678 ixgbe_link_speed lcd_speed;
2679 u32 save_autoneg;
2680 bool link_up;
2681
2682 /* SW LPLU not required on later HW revisions. */
2683 if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2684 return IXGBE_SUCCESS;
2685
2686 /* If blocked by MNG FW, then don't restart AN */
2687 if (ixgbe_check_reset_blocked(hw))
2688 return IXGBE_SUCCESS;
2689
2690 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2691 if (status != IXGBE_SUCCESS)
2692 return status;
2693
2694 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2695
2696 if (status != IXGBE_SUCCESS)
2697 return status;
2698
2699 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2700 * disabled, then force link down by entering low power mode.
2701 */
2702 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2703 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2704 return ixgbe_set_copper_phy_power(hw, FALSE);
2705
2706 /* Determine LCD */
2707 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2708
2709 if (status != IXGBE_SUCCESS)
2710 return status;
2711
2712 /* If no valid LCD link speed, then force link down and exit. */
2713 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2714 return ixgbe_set_copper_phy_power(hw, FALSE);
2715
2716 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2717 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2718 &speed);
2719
2720 if (status != IXGBE_SUCCESS)
2721 return status;
2722
2723 /* If no link now, speed is invalid so take link down */
2724 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2725 if (status != IXGBE_SUCCESS)
2726 return ixgbe_set_copper_phy_power(hw, FALSE);
2727
2728 /* clear everything but the speed bits */
2729 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2730
2731 /* If current speed is already LCD, then exit. */
2732 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2733 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2734 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2735 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2736 return status;
2737
2738 /* Clear AN completed indication */
2739 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2740 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2741 &autoneg_reg);
2742
2743 if (status != IXGBE_SUCCESS)
2744 return status;
2745
2746 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2747 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2748 &an_10g_cntl_reg);
2749
2750 if (status != IXGBE_SUCCESS)
2751 return status;
2752
2753 status = hw->phy.ops.read_reg(hw,
2754 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2756 &autoneg_reg);
2757
2758 if (status != IXGBE_SUCCESS)
2759 return status;
2760
2761 save_autoneg = hw->phy.autoneg_advertised;
2762
2763 /* Setup link at least common link speed */
2764 status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE);
2765
2766 /* restore autoneg from before setting lplu speed */
2767 hw->phy.autoneg_advertised = save_autoneg;
2768
2769 return status;
2770 }
2771
2772 /**
2773 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2774 * @hw: pointer to hardware structure
2775 * @lcd_speed: pointer to lowest common link speed
2776 *
2777 * Determine lowest common link speed with link partner.
2778 **/
2779 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2780 {
2781 u16 an_lp_status;
2782 s32 status;
2783 u16 word = hw->eeprom.ctrl_word_3;
2784
2785 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2786
2787 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2788 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2789 &an_lp_status);
2790
2791 if (status != IXGBE_SUCCESS)
2792 return status;
2793
2794 /* If link partner advertised 1G, return 1G */
2795 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2796 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2797 return status;
2798 }
2799
2800 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2801 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2802 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2803 return status;
2804
2805 /* Link partner not capable of lower speeds, return 10G */
2806 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2807 return status;
2808 }
2809
2810 /**
2811 * ixgbe_setup_fc_X550em - Set up flow control
2812 * @hw: pointer to hardware structure
2813 *
2814 * Called at init time to set up flow control.
2815 **/
2816 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2817 {
2818 s32 ret_val = IXGBE_SUCCESS;
2819 u32 pause, asm_dir, reg_val;
2820
2821 DEBUGFUNC("ixgbe_setup_fc_X550em");
2822
2823 /* Validate the requested mode */
2824 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2825 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2826 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2827 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2828 goto out;
2829 }
2830
2831 /* 10gig parts do not have a word in the EEPROM to determine the
2832 * default flow control setting, so we explicitly set it to full.
2833 */
2834 if (hw->fc.requested_mode == ixgbe_fc_default)
2835 hw->fc.requested_mode = ixgbe_fc_full;
2836
2837 /* Determine PAUSE and ASM_DIR bits. */
2838 switch (hw->fc.requested_mode) {
2839 case ixgbe_fc_none:
2840 pause = 0;
2841 asm_dir = 0;
2842 break;
2843 case ixgbe_fc_tx_pause:
2844 pause = 0;
2845 asm_dir = 1;
2846 break;
2847 case ixgbe_fc_rx_pause:
2848 /* Rx Flow control is enabled and Tx Flow control is
2849 * disabled by software override. Since there really
2850 * isn't a way to advertise that we are capable of RX
2851 * Pause ONLY, we will advertise that we support both
2852 * symmetric and asymmetric Rx PAUSE, as such we fall
2853 * through to the fc_full statement. Later, we will
2854 * disable the adapter's ability to send PAUSE frames.
2855 */
2856 case ixgbe_fc_full:
2857 pause = 1;
2858 asm_dir = 1;
2859 break;
2860 default:
2861 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2862 "Flow control param set incorrectly\n");
2863 ret_val = IXGBE_ERR_CONFIG;
2864 goto out;
2865 }
2866
2867 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2868 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2869 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2870 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2871 if (ret_val != IXGBE_SUCCESS)
2872 goto out;
2873 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2874 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2875 if (pause)
2876 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2877 if (asm_dir)
2878 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2879 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2880 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2881 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2882
2883 /* This device does not fully support AN. */
2884 hw->fc.disable_fc_autoneg = TRUE;
2885 }
2886
2887 out:
2888 return ret_val;
2889 }
2890
2891 /**
2892 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2893 * @hw: pointer to hardware structure
2894 * @state: set mux if 1, clear if 0
2895 */
2896 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2897 {
2898 u32 esdp;
2899
2900 if (!hw->bus.lan_id)
2901 return;
2902 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2903 if (state)
2904 esdp |= IXGBE_ESDP_SDP1;
2905 else
2906 esdp &= ~IXGBE_ESDP_SDP1;
2907 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2908 IXGBE_WRITE_FLUSH(hw);
2909 }
2910
2911 /**
2912 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2913 * @hw: pointer to hardware structure
2914 * @mask: Mask to specify which semaphore to acquire
2915 *
2916 * Acquires the SWFW semaphore and sets the I2C MUX
2917 **/
2918 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2919 {
2920 s32 status;
2921
2922 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2923
2924 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2925 if (status)
2926 return status;
2927
2928 if (mask & IXGBE_GSSR_I2C_MASK)
2929 ixgbe_set_mux(hw, 1);
2930
2931 return IXGBE_SUCCESS;
2932 }
2933
2934 /**
2935 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2936 * @hw: pointer to hardware structure
2937 * @mask: Mask to specify which semaphore to release
2938 *
2939 * Releases the SWFW semaphore and sets the I2C MUX
2940 **/
2941 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2942 {
2943 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2944
2945 if (mask & IXGBE_GSSR_I2C_MASK)
2946 ixgbe_set_mux(hw, 0);
2947
2948 ixgbe_release_swfw_sync_X540(hw, mask);
2949 }
2950
2951 /**
2952 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2953 * @hw: pointer to hardware structure
2954 *
2955 * Handle external Base T PHY interrupt. If high temperature
2956 * failure alarm then return error, else if link status change
2957 * then setup internal/external PHY link
2958 *
2959 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2960 * failure alarm, else return PHY access status.
2961 */
2962 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2963 {
2964 bool lsc;
2965 u32 status;
2966
2967 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2968
2969 if (status != IXGBE_SUCCESS)
2970 return status;
2971
2972 if (lsc)
2973 return ixgbe_setup_internal_phy(hw);
2974
2975 return IXGBE_SUCCESS;
2976 }
2977
2978 /**
2979 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2980 * @hw: pointer to hardware structure
2981 * @speed: new link speed
2982 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
2983 *
2984 * Setup internal/external PHY link speed based on link speed, then set
2985 * external PHY auto advertised link speed.
2986 *
2987 * Returns error status for any failure
2988 **/
2989 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2990 ixgbe_link_speed speed,
2991 bool autoneg_wait_to_complete)
2992 {
2993 s32 status;
2994 ixgbe_link_speed force_speed;
2995
2996 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2997
2998 /* Setup internal/external PHY link speed to iXFI (10G), unless
2999 * only 1G is auto advertised then setup KX link.
3000 */
3001 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3002 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3003 else
3004 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3005
3006 /* If internal link mode is XFI, then setup XFI internal link. */
3007 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3008 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3009
3010 if (status != IXGBE_SUCCESS)
3011 return status;
3012 }
3013
3014 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3015 }
3016
3017 /**
3018 * ixgbe_check_link_t_X550em - Determine link and speed status
3019 * @hw: pointer to hardware structure
3020 * @speed: pointer to link speed
3021 * @link_up: TRUE when link is up
3022 * @link_up_wait_to_complete: bool used to wait for link up or not
3023 *
3024 * Check that both the MAC and X557 external PHY have link.
3025 **/
3026 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3027 bool *link_up, bool link_up_wait_to_complete)
3028 {
3029 u32 status;
3030 u16 autoneg_status;
3031
3032 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3033 return IXGBE_ERR_CONFIG;
3034
3035 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3036 link_up_wait_to_complete);
3037
3038 /* If check link fails or MAC link is not up, then return */
3039 if (status != IXGBE_SUCCESS || !(*link_up))
3040 return status;
3041
3042 /* MAC link is up, so check external PHY link.
3043 * Read this twice back to back to indicate current status.
3044 */
3045 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3046 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3047 &autoneg_status);
3048
3049 if (status != IXGBE_SUCCESS)
3050 return status;
3051
3052 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3053 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3054 &autoneg_status);
3055
3056 if (status != IXGBE_SUCCESS)
3057 return status;
3058
3059 /* If external PHY link is not up, then indicate link not up */
3060 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3061 *link_up = FALSE;
3062
3063 return IXGBE_SUCCESS;
3064 }
3065
3066 /**
3067 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3068 * @hw: pointer to hardware structure
3069 **/
3070 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3071 {
3072 s32 status;
3073
3074 status = ixgbe_reset_phy_generic(hw);
3075
3076 if (status != IXGBE_SUCCESS)
3077 return status;
3078
3079 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3080 return ixgbe_enable_lasi_ext_t_x550em(hw);
3081 }
3082
3083 /**
3084 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3085 * @hw: pointer to hardware structure
3086 * @led_idx: led number to turn on
3087 **/
3088 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3089 {
3090 u16 phy_data;
3091
3092 DEBUGFUNC("ixgbe_led_on_t_X550em");
3093
3094 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3095 return IXGBE_ERR_PARAM;
3096
3097 /* To turn on the LED, set mode to ON. */
3098 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3099 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3100 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3101 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3102 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3103
3104 return IXGBE_SUCCESS;
3105 }
3106
3107 /**
3108 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3109 * @hw: pointer to hardware structure
3110 * @led_idx: led number to turn off
3111 **/
3112 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3113 {
3114 u16 phy_data;
3115
3116 DEBUGFUNC("ixgbe_led_off_t_X550em");
3117
3118 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3119 return IXGBE_ERR_PARAM;
3120
3121 /* To turn on the LED, set mode to ON. */
3122 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3123 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3124 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3125 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3126 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3127
3128 return IXGBE_SUCCESS;
3129 }
3130