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6064 ixgbe needs X550 support
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_x540.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_x540.c
1 1 /******************************************************************************
2 2
3 - Copyright (c) 2001-2012, Intel Corporation
3 + Copyright (c) 2001-2015, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 -/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_x540.c,v 1.2 2012/07/05 20:51:44 jfv Exp $*/
33 +/*$FreeBSD$*/
34 34
35 35 #include "ixgbe_x540.h"
36 36 #include "ixgbe_type.h"
37 37 #include "ixgbe_api.h"
38 38 #include "ixgbe_common.h"
39 39 #include "ixgbe_phy.h"
40 40
41 -static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
41 +#define IXGBE_X540_MAX_TX_QUEUES 128
42 +#define IXGBE_X540_MAX_RX_QUEUES 128
43 +#define IXGBE_X540_RAR_ENTRIES 128
44 +#define IXGBE_X540_MC_TBL_SIZE 128
45 +#define IXGBE_X540_VFT_TBL_SIZE 128
46 +#define IXGBE_X540_RX_PB_SIZE 384
47 +
42 48 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
43 49 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
44 50 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
45 51
46 52 /**
47 53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
48 54 * @hw: pointer to hardware structure
49 55 *
50 56 * Initialize the function pointers and assign the MAC type for X540.
51 57 * Does not touch the hardware.
52 58 **/
53 59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
54 60 {
55 61 struct ixgbe_mac_info *mac = &hw->mac;
56 62 struct ixgbe_phy_info *phy = &hw->phy;
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57 63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 64 s32 ret_val;
59 65
60 66 DEBUGFUNC("ixgbe_init_ops_X540");
61 67
62 68 ret_val = ixgbe_init_phy_ops_generic(hw);
63 69 ret_val = ixgbe_init_ops_generic(hw);
64 70
65 71
66 72 /* EEPROM */
67 - eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
68 - eeprom->ops.read = &ixgbe_read_eerd_X540;
69 - eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
70 - eeprom->ops.write = &ixgbe_write_eewr_X540;
71 - eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
72 - eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
73 - eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
74 - eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
73 + eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
74 + eeprom->ops.read = ixgbe_read_eerd_X540;
75 + eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
76 + eeprom->ops.write = ixgbe_write_eewr_X540;
77 + eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
78 + eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
79 + eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
80 + eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
75 81
76 82 /* PHY */
77 - phy->ops.init = &ixgbe_init_phy_ops_generic;
83 + phy->ops.init = ixgbe_init_phy_ops_generic;
78 84 phy->ops.reset = NULL;
85 + if (!ixgbe_mng_present(hw))
86 + phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
79 87
80 88 /* MAC */
81 - mac->ops.reset_hw = &ixgbe_reset_hw_X540;
82 - mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
83 - mac->ops.get_media_type = &ixgbe_get_media_type_X540;
89 + mac->ops.reset_hw = ixgbe_reset_hw_X540;
90 + mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
91 + mac->ops.get_media_type = ixgbe_get_media_type_X540;
84 92 mac->ops.get_supported_physical_layer =
85 - &ixgbe_get_supported_physical_layer_X540;
93 + ixgbe_get_supported_physical_layer_X540;
86 94 mac->ops.read_analog_reg8 = NULL;
87 95 mac->ops.write_analog_reg8 = NULL;
88 - mac->ops.start_hw = &ixgbe_start_hw_X540;
89 - mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
90 - mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
91 - mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
92 - mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
93 - mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
94 - mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
95 - mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
96 - mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
97 - mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
96 + mac->ops.start_hw = ixgbe_start_hw_X540;
97 + mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
98 + mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
99 + mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
100 + mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
101 + mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
102 + mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
103 + mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
104 + mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
105 + mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
98 106
99 107 /* RAR, Multicast, VLAN */
100 - mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
101 - mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
102 - mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
103 - mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
108 + mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
109 + mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
110 + mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
111 + mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
104 112 mac->rar_highwater = 1;
105 - mac->ops.set_vfta = &ixgbe_set_vfta_generic;
106 - mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
107 - mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
108 - mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
109 - mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
110 - mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
113 + mac->ops.set_vfta = ixgbe_set_vfta_generic;
114 + mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
115 + mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
116 + mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
117 + mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
118 + mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
111 119
112 120 /* Link */
113 121 mac->ops.get_link_capabilities =
114 - &ixgbe_get_copper_link_capabilities_generic;
115 - mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
116 - mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
117 - mac->ops.check_link = &ixgbe_check_mac_link_generic;
122 + ixgbe_get_copper_link_capabilities_generic;
123 + mac->ops.setup_link = ixgbe_setup_mac_link_X540;
124 + mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
125 + mac->ops.check_link = ixgbe_check_mac_link_generic;
118 126
119 - mac->mcft_size = 128;
120 - mac->vft_size = 128;
121 - mac->num_rar_entries = 128;
122 - mac->rx_pb_size = 384;
123 - mac->max_tx_queues = 128;
124 - mac->max_rx_queues = 128;
127 +
128 + mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
129 + mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
130 + mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
131 + mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
132 + mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
133 + mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
125 134 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
126 135
127 136 /*
128 137 * FWSM register
129 138 * ARC supported; valid only if manageability features are
130 139 * enabled.
131 140 */
132 - mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
133 - IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
141 + mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
142 + & IXGBE_FWSM_MODE_MASK);
134 143
135 144 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
136 145
137 146 /* LEDs */
138 147 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
139 148 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
140 149
141 150 /* Manageability interface */
142 - mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
151 + mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
143 152
153 + mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
154 +
144 155 return ret_val;
145 156 }
146 157
147 158 /**
148 159 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
149 160 * @hw: pointer to hardware structure
150 161 * @speed: pointer to link speed
151 162 * @autoneg: TRUE when autoneg or autotry is enabled
152 163 *
153 164 * Determines the link capabilities by reading the AUTOC register.
154 165 **/
155 166 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
156 167 ixgbe_link_speed *speed,
157 168 bool *autoneg)
158 169 {
159 - return ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
170 + ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
171 +
172 + return IXGBE_SUCCESS;
160 173 }
161 174
162 175 /**
163 176 * ixgbe_get_media_type_X540 - Get media type
164 177 * @hw: pointer to hardware structure
165 178 *
166 179 * Returns the media type (fiber, copper, backplane)
167 180 **/
168 181 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
169 182 {
170 183 UNREFERENCED_1PARAMETER(hw);
171 184 return ixgbe_media_type_copper;
172 185 }
173 186
174 187 /**
175 188 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
176 189 * @hw: pointer to hardware structure
177 190 * @speed: new link speed
178 - * @autoneg: TRUE if autonegotiation enabled
179 191 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
180 192 **/
181 193 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
182 - ixgbe_link_speed speed, bool autoneg,
194 + ixgbe_link_speed speed,
183 195 bool autoneg_wait_to_complete)
184 196 {
185 197 DEBUGFUNC("ixgbe_setup_mac_link_X540");
186 - return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
187 - autoneg_wait_to_complete);
198 + return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
188 199 }
189 200
190 201 /**
191 202 * ixgbe_reset_hw_X540 - Perform hardware reset
192 203 * @hw: pointer to hardware structure
193 204 *
194 205 * Resets the hardware by resetting the transmit and receive units, masks
195 206 * and clears all interrupts, and perform a reset.
196 207 **/
197 208 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
198 209 {
199 210 s32 status;
200 211 u32 ctrl, i;
201 212
202 213 DEBUGFUNC("ixgbe_reset_hw_X540");
203 214
204 215 /* Call adapter stop to disable tx/rx and clear interrupts */
205 216 status = hw->mac.ops.stop_adapter(hw);
206 217 if (status != IXGBE_SUCCESS)
207 218 goto reset_hw_out;
208 219
209 220 /* flush pending Tx transactions */
210 221 ixgbe_clear_tx_pending(hw);
211 222
212 223 mac_reset_top:
213 224 ctrl = IXGBE_CTRL_RST;
214 225 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
215 226 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
216 227 IXGBE_WRITE_FLUSH(hw);
217 228
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218 229 /* Poll for reset bit to self-clear indicating reset is complete */
219 230 for (i = 0; i < 10; i++) {
220 231 usec_delay(1);
221 232 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
222 233 if (!(ctrl & IXGBE_CTRL_RST_MASK))
223 234 break;
224 235 }
225 236
226 237 if (ctrl & IXGBE_CTRL_RST_MASK) {
227 238 status = IXGBE_ERR_RESET_FAILED;
228 - DEBUGOUT("Reset polling failed to complete.\n");
239 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
240 + "Reset polling failed to complete.\n");
229 241 }
230 242 msec_delay(100);
231 243
232 244 /*
233 245 * Double resets are required for recovery from certain error
234 246 * conditions. Between resets, it is necessary to stall to allow time
235 247 * for any pending HW events to complete.
236 248 */
237 249 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
238 250 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
239 251 goto mac_reset_top;
240 252 }
241 253
242 254 /* Set the Rx packet buffer size. */
243 255 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
244 256
245 257 /* Store the permanent mac address */
246 258 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
247 259
248 260 /*
249 261 * Store MAC address from RAR0, clear receive address registers, and
250 262 * clear the multicast table. Also reset num_rar_entries to 128,
251 263 * since we modify this value when programming the SAN MAC address.
252 264 */
253 265 hw->mac.num_rar_entries = 128;
254 266 hw->mac.ops.init_rx_addrs(hw);
255 267
256 268 /* Store the permanent SAN mac address */
257 269 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
258 270
259 271 /* Add the SAN MAC address to the RAR only if it's a valid address */
260 272 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
261 273 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
262 274 hw->mac.san_addr, 0, IXGBE_RAH_AV);
263 275
264 276 /* Save the SAN MAC RAR index */
265 277 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
266 278
267 279 /* Reserve the last RAR for the SAN MAC address */
268 280 hw->mac.num_rar_entries--;
269 281 }
270 282
271 283 /* Store the alternative WWNN/WWPN prefix */
272 284 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
273 285 &hw->mac.wwpn_prefix);
274 286
275 287 reset_hw_out:
276 288 return status;
277 289 }
278 290
279 291 /**
280 292 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
281 293 * @hw: pointer to hardware structure
282 294 *
283 295 * Starts the hardware using the generic start_hw function
284 296 * and the generation start_hw function.
285 297 * Then performs revision-specific operations, if any.
286 298 **/
287 299 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
288 300 {
289 301 s32 ret_val = IXGBE_SUCCESS;
290 302
291 303 DEBUGFUNC("ixgbe_start_hw_X540");
292 304
293 305 ret_val = ixgbe_start_hw_generic(hw);
294 306 if (ret_val != IXGBE_SUCCESS)
295 307 goto out;
296 308
297 309 ret_val = ixgbe_start_hw_gen2(hw);
298 310
299 311 out:
300 312 return ret_val;
301 313 }
302 314
303 315 /**
304 316 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
305 317 * @hw: pointer to hardware structure
306 318 *
307 319 * Determines physical layer capabilities of the current configuration.
308 320 **/
309 321 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
310 322 {
311 323 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
312 324 u16 ext_ability = 0;
313 325
314 326 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
315 327
316 328 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
317 329 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
318 330 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
319 331 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
320 332 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
321 333 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
322 334 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
323 335 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
324 336
325 337 return physical_layer;
326 338 }
327 339
328 340 /**
329 341 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
330 342 * @hw: pointer to hardware structure
331 343 *
332 344 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
333 345 * ixgbe_hw struct in order to set up EEPROM access.
334 346 **/
335 347 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
336 348 {
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337 349 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
338 350 u32 eec;
339 351 u16 eeprom_size;
340 352
341 353 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
342 354
343 355 if (eeprom->type == ixgbe_eeprom_uninitialized) {
344 356 eeprom->semaphore_delay = 10;
345 357 eeprom->type = ixgbe_flash;
346 358
347 - eec = IXGBE_READ_REG(hw, IXGBE_EEC);
359 + eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
348 360 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
349 361 IXGBE_EEC_SIZE_SHIFT);
350 362 eeprom->word_size = 1 << (eeprom_size +
351 363 IXGBE_EEPROM_WORD_SIZE_SHIFT);
352 364
353 365 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
354 366 eeprom->type, eeprom->word_size);
355 367 }
356 368
357 369 return IXGBE_SUCCESS;
358 370 }
359 371
360 372 /**
361 373 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
362 374 * @hw: pointer to hardware structure
363 375 * @offset: offset of word in the EEPROM to read
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364 376 * @data: word read from the EEPROM
365 377 *
366 378 * Reads a 16 bit word from the EEPROM using the EERD register.
367 379 **/
368 380 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
369 381 {
370 382 s32 status = IXGBE_SUCCESS;
371 383
372 384 DEBUGFUNC("ixgbe_read_eerd_X540");
373 385 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
374 - IXGBE_SUCCESS)
386 + IXGBE_SUCCESS) {
375 387 status = ixgbe_read_eerd_generic(hw, offset, data);
376 - else
388 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
389 + } else {
377 390 status = IXGBE_ERR_SWFW_SYNC;
391 + }
378 392
379 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
380 393 return status;
381 394 }
382 395
383 396 /**
384 397 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
385 398 * @hw: pointer to hardware structure
386 399 * @offset: offset of word in the EEPROM to read
387 400 * @words: number of words
388 401 * @data: word(s) read from the EEPROM
389 402 *
390 403 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
391 404 **/
392 405 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
393 406 u16 offset, u16 words, u16 *data)
394 407 {
395 408 s32 status = IXGBE_SUCCESS;
396 409
397 410 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
398 411 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
399 - IXGBE_SUCCESS)
412 + IXGBE_SUCCESS) {
400 413 status = ixgbe_read_eerd_buffer_generic(hw, offset,
401 414 words, data);
402 - else
415 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
416 + } else {
403 417 status = IXGBE_ERR_SWFW_SYNC;
418 + }
404 419
405 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
406 420 return status;
407 421 }
408 422
409 423 /**
410 424 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
411 425 * @hw: pointer to hardware structure
412 426 * @offset: offset of word in the EEPROM to write
413 427 * @data: word write to the EEPROM
414 428 *
415 429 * Write a 16 bit word to the EEPROM using the EEWR register.
416 430 **/
417 431 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
418 432 {
419 433 s32 status = IXGBE_SUCCESS;
420 434
421 435 DEBUGFUNC("ixgbe_write_eewr_X540");
422 436 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
423 - IXGBE_SUCCESS)
437 + IXGBE_SUCCESS) {
424 438 status = ixgbe_write_eewr_generic(hw, offset, data);
425 - else
439 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
440 + } else {
426 441 status = IXGBE_ERR_SWFW_SYNC;
442 + }
427 443
428 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
429 444 return status;
430 445 }
431 446
432 447 /**
433 448 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
434 449 * @hw: pointer to hardware structure
435 450 * @offset: offset of word in the EEPROM to write
436 451 * @words: number of words
437 452 * @data: word(s) write to the EEPROM
438 453 *
439 454 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
440 455 **/
441 456 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
442 457 u16 offset, u16 words, u16 *data)
443 458 {
444 459 s32 status = IXGBE_SUCCESS;
445 460
446 461 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
447 462 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
448 - IXGBE_SUCCESS)
463 + IXGBE_SUCCESS) {
449 464 status = ixgbe_write_eewr_buffer_generic(hw, offset,
450 465 words, data);
451 - else
466 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
467 + } else {
452 468 status = IXGBE_ERR_SWFW_SYNC;
469 + }
453 470
454 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
455 471 return status;
456 472 }
457 473
458 474 /**
459 475 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
460 476 *
461 477 * This function does not use synchronization for EERD and EEWR. It can
462 478 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
463 479 *
464 480 * @hw: pointer to hardware structure
481 + *
482 + * Returns a negative error code on error, or the 16-bit checksum
465 483 **/
466 -u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
484 +s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
467 485 {
468 - u16 i;
469 - u16 j;
486 + u16 i, j;
470 487 u16 checksum = 0;
471 488 u16 length = 0;
472 489 u16 pointer = 0;
473 490 u16 word = 0;
491 + u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
492 + u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
474 493
475 - /*
476 - * Do not use hw->eeprom.ops.read because we do not want to take
494 + /* Do not use hw->eeprom.ops.read because we do not want to take
477 495 * the synchronization semaphores here. Instead use
478 496 * ixgbe_read_eerd_generic
479 497 */
480 498
481 499 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
482 500
483 501 /* Include 0x0-0x3F in the checksum */
484 - for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
485 - if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
502 + for (i = 0; i <= checksum_last_word; i++) {
503 + if (ixgbe_read_eerd_generic(hw, i, &word)) {
486 504 DEBUGOUT("EEPROM read failed\n");
487 - break;
505 + return IXGBE_ERR_EEPROM;
488 506 }
489 - checksum += word;
507 + if (i != IXGBE_EEPROM_CHECKSUM)
508 + checksum += word;
490 509 }
491 510
492 - /*
493 - * Include all data from pointers 0x3, 0x6-0xE. This excludes the
511 + /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
494 512 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
495 513 */
496 - for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
514 + for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
497 515 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
498 516 continue;
499 517
500 - if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
518 + if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
501 519 DEBUGOUT("EEPROM read failed\n");
502 - break;
520 + return IXGBE_ERR_EEPROM;
503 521 }
504 522
505 523 /* Skip pointer section if the pointer is invalid. */
506 524 if (pointer == 0xFFFF || pointer == 0 ||
507 525 pointer >= hw->eeprom.word_size)
508 526 continue;
509 527
510 - if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
511 - IXGBE_SUCCESS) {
528 + if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
512 529 DEBUGOUT("EEPROM read failed\n");
513 - break;
530 + return IXGBE_ERR_EEPROM;
514 531 }
515 532
516 533 /* Skip pointer section if length is invalid. */
517 534 if (length == 0xFFFF || length == 0 ||
518 535 (pointer + length) >= hw->eeprom.word_size)
519 536 continue;
520 537
521 - for (j = pointer+1; j <= pointer+length; j++) {
522 - if (ixgbe_read_eerd_generic(hw, j, &word) !=
523 - IXGBE_SUCCESS) {
538 + for (j = pointer + 1; j <= pointer + length; j++) {
539 + if (ixgbe_read_eerd_generic(hw, j, &word)) {
524 540 DEBUGOUT("EEPROM read failed\n");
525 - break;
541 + return IXGBE_ERR_EEPROM;
526 542 }
527 543 checksum += word;
528 544 }
529 545 }
530 546
531 547 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
532 548
533 - return checksum;
549 + return (s32)checksum;
534 550 }
535 551
536 552 /**
537 553 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
538 554 * @hw: pointer to hardware structure
539 555 * @checksum_val: calculated checksum
540 556 *
541 557 * Performs checksum calculation and validates the EEPROM checksum. If the
542 558 * caller does not need checksum_val, the value can be NULL.
543 559 **/
544 560 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
545 561 u16 *checksum_val)
546 562 {
547 563 s32 status;
548 564 u16 checksum;
549 565 u16 read_checksum = 0;
550 566
551 567 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
552 568
553 - /*
554 - * Read the first word from the EEPROM. If this times out or fails, do
569 + /* Read the first word from the EEPROM. If this times out or fails, do
555 570 * not continue or we could be in for a very long wait while every
556 571 * EEPROM read fails
557 572 */
558 573 status = hw->eeprom.ops.read(hw, 0, &checksum);
559 -
560 - if (status != IXGBE_SUCCESS) {
574 + if (status) {
561 575 DEBUGOUT("EEPROM read failed\n");
562 - goto out;
576 + return status;
563 577 }
564 578
565 - if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
566 - IXGBE_SUCCESS) {
567 - checksum = hw->eeprom.ops.calc_checksum(hw);
579 + if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
580 + return IXGBE_ERR_SWFW_SYNC;
568 581
569 - /*
570 - * Do not use hw->eeprom.ops.read because we do not want to take
571 - * the synchronization semaphores twice here.
572 - */
573 - status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
574 - &read_checksum);
582 + status = hw->eeprom.ops.calc_checksum(hw);
583 + if (status < 0)
584 + goto out;
575 585
576 - if (status == IXGBE_SUCCESS) {
577 - /*
578 - * Verify read checksum from EEPROM is the same as
579 - * calculated checksum
580 - */
581 - if (read_checksum != checksum)
582 - status = IXGBE_ERR_EEPROM_CHECKSUM;
586 + checksum = (u16)(status & 0xffff);
583 587
584 - /* If the user cares, return the calculated checksum */
585 - if (checksum_val)
586 - *checksum_val = checksum;
587 - }
588 - } else {
589 - status = IXGBE_ERR_SWFW_SYNC;
588 + /* Do not use hw->eeprom.ops.read because we do not want to take
589 + * the synchronization semaphores twice here.
590 + */
591 + status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
592 + &read_checksum);
593 + if (status)
594 + goto out;
595 +
596 + /* Verify read checksum from EEPROM is the same as
597 + * calculated checksum
598 + */
599 + if (read_checksum != checksum) {
600 + ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
601 + "Invalid EEPROM checksum");
602 + status = IXGBE_ERR_EEPROM_CHECKSUM;
590 603 }
591 604
592 - hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
605 + /* If the user cares, return the calculated checksum */
606 + if (checksum_val)
607 + *checksum_val = checksum;
608 +
593 609 out:
610 + hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
611 +
594 612 return status;
595 613 }
596 614
597 615 /**
598 616 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
599 617 * @hw: pointer to hardware structure
600 618 *
601 619 * After writing EEPROM to shadow RAM using EEWR register, software calculates
602 620 * checksum and updates the EEPROM and instructs the hardware to update
603 621 * the flash.
604 622 **/
605 623 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
606 624 {
607 625 s32 status;
608 626 u16 checksum;
609 627
610 628 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
611 629
612 - /*
613 - * Read the first word from the EEPROM. If this times out or fails, do
630 + /* Read the first word from the EEPROM. If this times out or fails, do
614 631 * not continue or we could be in for a very long wait while every
615 632 * EEPROM read fails
616 633 */
617 634 status = hw->eeprom.ops.read(hw, 0, &checksum);
618 -
619 - if (status != IXGBE_SUCCESS)
635 + if (status) {
620 636 DEBUGOUT("EEPROM read failed\n");
637 + return status;
638 + }
621 639
622 - if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
623 - IXGBE_SUCCESS) {
624 - checksum = hw->eeprom.ops.calc_checksum(hw);
640 + if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
641 + return IXGBE_ERR_SWFW_SYNC;
625 642
626 - /*
627 - * Do not use hw->eeprom.ops.write because we do not want to
628 - * take the synchronization semaphores twice here.
629 - */
630 - status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
631 - checksum);
643 + status = hw->eeprom.ops.calc_checksum(hw);
644 + if (status < 0)
645 + goto out;
632 646
633 - if (status == IXGBE_SUCCESS)
634 - status = ixgbe_update_flash_X540(hw);
635 - else
636 - status = IXGBE_ERR_SWFW_SYNC;
637 - }
647 + checksum = (u16)(status & 0xffff);
638 648
649 + /* Do not use hw->eeprom.ops.write because we do not want to
650 + * take the synchronization semaphores twice here.
651 + */
652 + status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
653 + if (status)
654 + goto out;
655 +
656 + status = ixgbe_update_flash_X540(hw);
657 +
658 +out:
639 659 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
640 660
641 661 return status;
642 662 }
643 663
644 664 /**
645 665 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
646 666 * @hw: pointer to hardware structure
647 667 *
648 668 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
649 669 * EEPROM from shadow RAM to the flash device.
650 670 **/
651 -static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
671 +s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
652 672 {
653 673 u32 flup;
654 - s32 status = IXGBE_ERR_EEPROM;
674 + s32 status;
655 675
656 676 DEBUGFUNC("ixgbe_update_flash_X540");
657 677
658 678 status = ixgbe_poll_flash_update_done_X540(hw);
659 679 if (status == IXGBE_ERR_EEPROM) {
660 680 DEBUGOUT("Flash update time out\n");
661 681 goto out;
662 682 }
663 683
664 - flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
665 - IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
684 + flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
685 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
666 686
667 687 status = ixgbe_poll_flash_update_done_X540(hw);
668 688 if (status == IXGBE_SUCCESS)
669 689 DEBUGOUT("Flash update complete\n");
670 690 else
671 691 DEBUGOUT("Flash update time out\n");
672 692
673 - if (hw->revision_id == 0) {
674 - flup = IXGBE_READ_REG(hw, IXGBE_EEC);
693 + if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
694 + flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
675 695
676 696 if (flup & IXGBE_EEC_SEC1VAL) {
677 697 flup |= IXGBE_EEC_FLUP;
678 - IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
698 + IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
679 699 }
680 700
681 701 status = ixgbe_poll_flash_update_done_X540(hw);
682 702 if (status == IXGBE_SUCCESS)
683 703 DEBUGOUT("Flash update complete\n");
684 704 else
685 705 DEBUGOUT("Flash update time out\n");
686 706 }
687 707 out:
688 708 return status;
689 709 }
690 710
691 711 /**
692 712 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
693 713 * @hw: pointer to hardware structure
694 714 *
695 715 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
696 716 * flash update is done.
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697 717 **/
698 718 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
699 719 {
700 720 u32 i;
701 721 u32 reg;
702 722 s32 status = IXGBE_ERR_EEPROM;
703 723
704 724 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
705 725
706 726 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
707 - reg = IXGBE_READ_REG(hw, IXGBE_EEC);
727 + reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
708 728 if (reg & IXGBE_EEC_FLUDONE) {
709 729 status = IXGBE_SUCCESS;
710 730 break;
711 731 }
712 - usec_delay(5);
732 + msec_delay(5);
713 733 }
734 +
735 + if (i == IXGBE_FLUDONE_ATTEMPTS)
736 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
737 + "Flash update status polling timed out");
738 +
714 739 return status;
715 740 }
716 741
717 742 /**
718 743 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
719 744 * @hw: pointer to hardware structure
720 745 * @mask: Mask to specify which semaphore to acquire
721 746 *
722 747 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
723 748 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
724 749 **/
725 -s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
750 +s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
726 751 {
727 - u32 swfw_sync;
728 - u32 swmask = mask;
729 - u32 fwmask = mask << 5;
730 - u32 hwmask = 0;
752 + u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
753 + u32 fwmask = swmask << 5;
754 + u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
731 755 u32 timeout = 200;
756 + u32 hwmask = 0;
757 + u32 swfw_sync;
732 758 u32 i;
733 - s32 ret_val = IXGBE_SUCCESS;
734 759
735 760 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
736 761
737 - if (swmask == IXGBE_GSSR_EEP_SM)
738 - hwmask = IXGBE_GSSR_FLASH_SM;
762 + if (swmask & IXGBE_GSSR_EEP_SM)
763 + hwmask |= IXGBE_GSSR_FLASH_SM;
739 764
740 765 /* SW only mask doesn't have FW bit pair */
741 - if (swmask == IXGBE_GSSR_SW_MNG_SM)
742 - fwmask = 0;
766 + if (mask & IXGBE_GSSR_SW_MNG_SM)
767 + swmask |= IXGBE_GSSR_SW_MNG_SM;
743 768
769 + swmask |= swi2c_mask;
770 + fwmask |= swi2c_mask << 2;
744 771 for (i = 0; i < timeout; i++) {
745 - /*
746 - * SW NVM semaphore bit is used for access to all
772 + /* SW NVM semaphore bit is used for access to all
747 773 * SW_FW_SYNC bits (not just NVM)
748 774 */
749 - if (ixgbe_get_swfw_sync_semaphore(hw)) {
750 - ret_val = IXGBE_ERR_SWFW_SYNC;
751 - goto out;
752 - }
775 + if (ixgbe_get_swfw_sync_semaphore(hw))
776 + return IXGBE_ERR_SWFW_SYNC;
753 777
754 - swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
778 + swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
755 779 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
756 780 swfw_sync |= swmask;
757 - IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
781 + IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
782 + swfw_sync);
758 783 ixgbe_release_swfw_sync_semaphore(hw);
759 784 msec_delay(5);
760 - goto out;
761 - } else {
762 - /*
763 - * Firmware currently using resource (fwmask), hardware
764 - * currently using resource (hwmask), or other software
765 - * thread currently using resource (swmask)
766 - */
767 - ixgbe_release_swfw_sync_semaphore(hw);
768 - msec_delay(5);
785 + return IXGBE_SUCCESS;
769 786 }
787 + /* Firmware currently using resource (fwmask), hardware
788 + * currently using resource (hwmask), or other software
789 + * thread currently using resource (swmask)
790 + */
791 + ixgbe_release_swfw_sync_semaphore(hw);
792 + msec_delay(5);
770 793 }
771 794
772 795 /* Failed to get SW only semaphore */
773 796 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
774 - ret_val = IXGBE_ERR_SWFW_SYNC;
775 - goto out;
797 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
798 + "Failed to get SW only semaphore");
799 + return IXGBE_ERR_SWFW_SYNC;
776 800 }
777 801
778 802 /* If the resource is not released by the FW/HW the SW can assume that
779 - * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
803 + * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
780 804 * of the requested resource(s) while ignoring the corresponding FW/HW
781 805 * bits in the SW_FW_SYNC register.
782 806 */
783 - swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
807 + if (ixgbe_get_swfw_sync_semaphore(hw))
808 + return IXGBE_ERR_SWFW_SYNC;
809 + swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
784 810 if (swfw_sync & (fwmask | hwmask)) {
785 - if (ixgbe_get_swfw_sync_semaphore(hw)) {
786 - ret_val = IXGBE_ERR_SWFW_SYNC;
787 - goto out;
788 - }
789 -
790 811 swfw_sync |= swmask;
791 - IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
812 + IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
792 813 ixgbe_release_swfw_sync_semaphore(hw);
793 814 msec_delay(5);
815 + return IXGBE_SUCCESS;
794 816 }
817 + /* If the resource is not released by other SW the SW can assume that
818 + * the other SW malfunctions. In that case the SW should clear all SW
819 + * flags that it does not own and then repeat the whole process once
820 + * again.
821 + */
822 + if (swfw_sync & swmask) {
823 + u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
824 + IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
795 825
796 -out:
797 - return ret_val;
826 + if (swi2c_mask)
827 + rmask |= IXGBE_GSSR_I2C_MASK;
828 + ixgbe_release_swfw_sync_X540(hw, rmask);
829 + ixgbe_release_swfw_sync_semaphore(hw);
830 + return IXGBE_ERR_SWFW_SYNC;
831 + }
832 + ixgbe_release_swfw_sync_semaphore(hw);
833 +
834 + return IXGBE_ERR_SWFW_SYNC;
798 835 }
799 836
800 837 /**
801 838 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
802 839 * @hw: pointer to hardware structure
803 840 * @mask: Mask to specify which semaphore to release
804 841 *
805 842 * Releases the SWFW semaphore through the SW_FW_SYNC register
806 843 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
807 844 **/
808 -void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
845 +void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
809 846 {
847 + u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
810 848 u32 swfw_sync;
811 - u32 swmask = mask;
812 849
813 850 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
814 851
815 - (void) ixgbe_get_swfw_sync_semaphore(hw);
852 + if (mask & IXGBE_GSSR_I2C_MASK)
853 + swmask |= mask & IXGBE_GSSR_I2C_MASK;
854 + ixgbe_get_swfw_sync_semaphore(hw);
816 855
817 - swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
856 + swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
818 857 swfw_sync &= ~swmask;
819 - IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
858 + IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
820 859
821 860 ixgbe_release_swfw_sync_semaphore(hw);
822 861 msec_delay(5);
823 862 }
824 863
825 864 /**
826 - * ixgbe_get_nvm_semaphore - Get hardware semaphore
865 + * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
827 866 * @hw: pointer to hardware structure
828 867 *
829 868 * Sets the hardware semaphores so SW/FW can gain control of shared resources
830 869 **/
831 870 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
832 871 {
833 872 s32 status = IXGBE_ERR_EEPROM;
834 873 u32 timeout = 2000;
835 874 u32 i;
836 875 u32 swsm;
837 876
838 877 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
839 878
840 879 /* Get SMBI software semaphore between device drivers first */
841 880 for (i = 0; i < timeout; i++) {
842 881 /*
843 882 * If the SMBI bit is 0 when we read it, then the bit will be
844 883 * set and we have the semaphore
845 884 */
846 - swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
885 + swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
847 886 if (!(swsm & IXGBE_SWSM_SMBI)) {
848 887 status = IXGBE_SUCCESS;
849 888 break;
850 889 }
851 890 usec_delay(50);
852 891 }
853 892
854 893 /* Now get the semaphore between SW/FW through the REGSMP bit */
855 894 if (status == IXGBE_SUCCESS) {
856 895 for (i = 0; i < timeout; i++) {
857 - swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
896 + swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
858 897 if (!(swsm & IXGBE_SWFW_REGSMP))
859 898 break;
860 899
861 900 usec_delay(50);
862 901 }
863 902
864 903 /*
865 904 * Release semaphores and return error if SW NVM semaphore
866 905 * was not granted because we don't have access to the EEPROM
867 906 */
868 907 if (i >= timeout) {
869 - DEBUGOUT("REGSMP Software NVM semaphore not "
870 - "granted.\n");
908 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
909 + "REGSMP Software NVM semaphore not granted.\n");
871 910 ixgbe_release_swfw_sync_semaphore(hw);
872 911 status = IXGBE_ERR_EEPROM;
873 912 }
874 913 } else {
875 - DEBUGOUT("Software semaphore SMBI between device drivers "
876 - "not granted.\n");
914 + ERROR_REPORT1(IXGBE_ERROR_POLLING,
915 + "Software semaphore SMBI between device drivers "
916 + "not granted.\n");
877 917 }
878 918
879 919 return status;
880 920 }
881 921
882 922 /**
883 - * ixgbe_release_nvm_semaphore - Release hardware semaphore
923 + * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
884 924 * @hw: pointer to hardware structure
885 925 *
886 926 * This function clears hardware semaphore bits.
887 927 **/
888 928 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
889 929 {
890 930 u32 swsm;
891 931
892 932 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
893 933
894 934 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
895 935
896 - swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
897 - swsm &= ~IXGBE_SWSM_SMBI;
898 - IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
899 -
900 - swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
936 + swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
901 937 swsm &= ~IXGBE_SWFW_REGSMP;
902 - IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
938 + IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
903 939
940 + swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
941 + swsm &= ~IXGBE_SWSM_SMBI;
942 + IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
943 +
904 944 IXGBE_WRITE_FLUSH(hw);
905 945 }
906 946
907 947 /**
908 948 * ixgbe_blink_led_start_X540 - Blink LED based on index.
909 949 * @hw: pointer to hardware structure
910 950 * @index: led number to blink
911 951 *
912 952 * Devices that implement the version 2 interface:
913 953 * X540
914 954 **/
915 955 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
916 956 {
917 957 u32 macc_reg;
918 958 u32 ledctl_reg;
919 959 ixgbe_link_speed speed;
920 960 bool link_up;
921 961
922 962 DEBUGFUNC("ixgbe_blink_led_start_X540");
923 963
924 964 /*
925 965 * Link should be up in order for the blink bit in the LED control
926 966 * register to work. Force link and speed in the MAC if link is down.
927 967 * This will be reversed when we stop the blinking.
928 968 */
929 969 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
930 970 if (link_up == FALSE) {
931 971 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
932 972 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
933 973 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
934 974 }
935 975 /* Set the LED to LINK_UP + BLINK. */
936 976 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
937 977 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
938 978 ledctl_reg |= IXGBE_LED_BLINK(index);
939 979 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
940 980 IXGBE_WRITE_FLUSH(hw);
941 981
942 982 return IXGBE_SUCCESS;
943 983 }
944 984
945 985 /**
946 986 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
947 987 * @hw: pointer to hardware structure
948 988 * @index: led number to stop blinking
949 989 *
950 990 * Devices that implement the version 2 interface:
951 991 * X540
952 992 **/
953 993 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
954 994 {
955 995 u32 macc_reg;
956 996 u32 ledctl_reg;
957 997
958 998 DEBUGFUNC("ixgbe_blink_led_stop_X540");
959 999
960 1000 /* Restore the LED to its default value. */
961 1001 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
962 1002 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
963 1003 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
964 1004 ledctl_reg &= ~IXGBE_LED_BLINK(index);
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965 1005 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
966 1006
967 1007 /* Unforce link and speed in the MAC. */
968 1008 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
969 1009 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
970 1010 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
971 1011 IXGBE_WRITE_FLUSH(hw);
972 1012
973 1013 return IXGBE_SUCCESS;
974 1014 }
975 -
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