1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_x540.c,v 1.2 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
42 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
43 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
44 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
45
46 /**
47 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
49 *
50 * Initialize the function pointers and assign the MAC type for X540.
51 * Does not touch the hardware.
52 **/
53 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
54 {
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_phy_info *phy = &hw->phy;
57 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 s32 ret_val;
59
60 DEBUGFUNC("ixgbe_init_ops_X540");
61
62 ret_val = ixgbe_init_phy_ops_generic(hw);
63 ret_val = ixgbe_init_ops_generic(hw);
64
65
66 /* EEPROM */
67 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
68 eeprom->ops.read = &ixgbe_read_eerd_X540;
69 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
70 eeprom->ops.write = &ixgbe_write_eewr_X540;
71 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
72 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
73 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
74 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
75
76 /* PHY */
77 phy->ops.init = &ixgbe_init_phy_ops_generic;
78 phy->ops.reset = NULL;
79
80 /* MAC */
81 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
82 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
83 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
84 mac->ops.get_supported_physical_layer =
85 &ixgbe_get_supported_physical_layer_X540;
86 mac->ops.read_analog_reg8 = NULL;
87 mac->ops.write_analog_reg8 = NULL;
88 mac->ops.start_hw = &ixgbe_start_hw_X540;
89 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
90 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
91 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
92 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
93 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
94 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
95 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
96 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
97 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
98
99 /* RAR, Multicast, VLAN */
100 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
101 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
102 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
103 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
104 mac->rar_highwater = 1;
105 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
106 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
107 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
108 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
109 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
110 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
111
112 /* Link */
113 mac->ops.get_link_capabilities =
114 &ixgbe_get_copper_link_capabilities_generic;
115 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
116 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
117 mac->ops.check_link = &ixgbe_check_mac_link_generic;
118
119 mac->mcft_size = 128;
120 mac->vft_size = 128;
121 mac->num_rar_entries = 128;
122 mac->rx_pb_size = 384;
123 mac->max_tx_queues = 128;
124 mac->max_rx_queues = 128;
125 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
126
127 /*
128 * FWSM register
129 * ARC supported; valid only if manageability features are
130 * enabled.
131 */
132 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
133 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
134
135 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
136
137 /* LEDs */
138 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
139 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
140
141 /* Manageability interface */
142 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
143
144 return ret_val;
145 }
146
147 /**
148 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
149 * @hw: pointer to hardware structure
150 * @speed: pointer to link speed
151 * @autoneg: TRUE when autoneg or autotry is enabled
152 *
153 * Determines the link capabilities by reading the AUTOC register.
154 **/
155 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
156 ixgbe_link_speed *speed,
157 bool *autoneg)
158 {
159 return ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
160 }
161
162 /**
163 * ixgbe_get_media_type_X540 - Get media type
164 * @hw: pointer to hardware structure
165 *
166 * Returns the media type (fiber, copper, backplane)
167 **/
168 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
169 {
170 UNREFERENCED_1PARAMETER(hw);
171 return ixgbe_media_type_copper;
172 }
173
174 /**
175 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
176 * @hw: pointer to hardware structure
177 * @speed: new link speed
178 * @autoneg: TRUE if autonegotiation enabled
179 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
180 **/
181 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
182 ixgbe_link_speed speed, bool autoneg,
183 bool autoneg_wait_to_complete)
184 {
185 DEBUGFUNC("ixgbe_setup_mac_link_X540");
186 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
187 autoneg_wait_to_complete);
188 }
189
190 /**
191 * ixgbe_reset_hw_X540 - Perform hardware reset
192 * @hw: pointer to hardware structure
193 *
194 * Resets the hardware by resetting the transmit and receive units, masks
195 * and clears all interrupts, and perform a reset.
196 **/
197 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
198 {
199 s32 status;
200 u32 ctrl, i;
201
202 DEBUGFUNC("ixgbe_reset_hw_X540");
203
204 /* Call adapter stop to disable tx/rx and clear interrupts */
205 status = hw->mac.ops.stop_adapter(hw);
206 if (status != IXGBE_SUCCESS)
207 goto reset_hw_out;
208
209 /* flush pending Tx transactions */
210 ixgbe_clear_tx_pending(hw);
211
212 mac_reset_top:
213 ctrl = IXGBE_CTRL_RST;
214 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
215 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
216 IXGBE_WRITE_FLUSH(hw);
217
218 /* Poll for reset bit to self-clear indicating reset is complete */
219 for (i = 0; i < 10; i++) {
220 usec_delay(1);
221 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
222 if (!(ctrl & IXGBE_CTRL_RST_MASK))
223 break;
224 }
225
226 if (ctrl & IXGBE_CTRL_RST_MASK) {
227 status = IXGBE_ERR_RESET_FAILED;
228 DEBUGOUT("Reset polling failed to complete.\n");
229 }
230 msec_delay(100);
231
232 /*
233 * Double resets are required for recovery from certain error
234 * conditions. Between resets, it is necessary to stall to allow time
235 * for any pending HW events to complete.
236 */
237 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
238 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
239 goto mac_reset_top;
240 }
241
242 /* Set the Rx packet buffer size. */
243 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
244
245 /* Store the permanent mac address */
246 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
247
248 /*
249 * Store MAC address from RAR0, clear receive address registers, and
250 * clear the multicast table. Also reset num_rar_entries to 128,
251 * since we modify this value when programming the SAN MAC address.
252 */
253 hw->mac.num_rar_entries = 128;
254 hw->mac.ops.init_rx_addrs(hw);
255
256 /* Store the permanent SAN mac address */
257 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
258
259 /* Add the SAN MAC address to the RAR only if it's a valid address */
260 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
261 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
262 hw->mac.san_addr, 0, IXGBE_RAH_AV);
263
264 /* Save the SAN MAC RAR index */
265 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
266
267 /* Reserve the last RAR for the SAN MAC address */
268 hw->mac.num_rar_entries--;
269 }
270
271 /* Store the alternative WWNN/WWPN prefix */
272 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
273 &hw->mac.wwpn_prefix);
274
275 reset_hw_out:
276 return status;
277 }
278
279 /**
280 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
281 * @hw: pointer to hardware structure
282 *
283 * Starts the hardware using the generic start_hw function
284 * and the generation start_hw function.
285 * Then performs revision-specific operations, if any.
286 **/
287 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
288 {
289 s32 ret_val = IXGBE_SUCCESS;
290
291 DEBUGFUNC("ixgbe_start_hw_X540");
292
293 ret_val = ixgbe_start_hw_generic(hw);
294 if (ret_val != IXGBE_SUCCESS)
295 goto out;
296
297 ret_val = ixgbe_start_hw_gen2(hw);
298
299 out:
300 return ret_val;
301 }
302
303 /**
304 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
305 * @hw: pointer to hardware structure
306 *
307 * Determines physical layer capabilities of the current configuration.
308 **/
309 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
310 {
311 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
312 u16 ext_ability = 0;
313
314 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
315
316 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
317 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
318 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
319 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
320 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
321 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
322 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
323 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
324
325 return physical_layer;
326 }
327
328 /**
329 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
330 * @hw: pointer to hardware structure
331 *
332 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
333 * ixgbe_hw struct in order to set up EEPROM access.
334 **/
335 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
336 {
337 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
338 u32 eec;
339 u16 eeprom_size;
340
341 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
342
343 if (eeprom->type == ixgbe_eeprom_uninitialized) {
344 eeprom->semaphore_delay = 10;
345 eeprom->type = ixgbe_flash;
346
347 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
348 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
349 IXGBE_EEC_SIZE_SHIFT);
350 eeprom->word_size = 1 << (eeprom_size +
351 IXGBE_EEPROM_WORD_SIZE_SHIFT);
352
353 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
354 eeprom->type, eeprom->word_size);
355 }
356
357 return IXGBE_SUCCESS;
358 }
359
360 /**
361 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
362 * @hw: pointer to hardware structure
363 * @offset: offset of word in the EEPROM to read
364 * @data: word read from the EEPROM
365 *
366 * Reads a 16 bit word from the EEPROM using the EERD register.
367 **/
368 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
369 {
370 s32 status = IXGBE_SUCCESS;
371
372 DEBUGFUNC("ixgbe_read_eerd_X540");
373 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
374 IXGBE_SUCCESS)
375 status = ixgbe_read_eerd_generic(hw, offset, data);
376 else
377 status = IXGBE_ERR_SWFW_SYNC;
378
379 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
380 return status;
381 }
382
383 /**
384 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
385 * @hw: pointer to hardware structure
386 * @offset: offset of word in the EEPROM to read
387 * @words: number of words
388 * @data: word(s) read from the EEPROM
389 *
390 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
391 **/
392 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
393 u16 offset, u16 words, u16 *data)
394 {
395 s32 status = IXGBE_SUCCESS;
396
397 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
398 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
399 IXGBE_SUCCESS)
400 status = ixgbe_read_eerd_buffer_generic(hw, offset,
401 words, data);
402 else
403 status = IXGBE_ERR_SWFW_SYNC;
404
405 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
406 return status;
407 }
408
409 /**
410 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
411 * @hw: pointer to hardware structure
412 * @offset: offset of word in the EEPROM to write
413 * @data: word write to the EEPROM
414 *
415 * Write a 16 bit word to the EEPROM using the EEWR register.
416 **/
417 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
418 {
419 s32 status = IXGBE_SUCCESS;
420
421 DEBUGFUNC("ixgbe_write_eewr_X540");
422 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
423 IXGBE_SUCCESS)
424 status = ixgbe_write_eewr_generic(hw, offset, data);
425 else
426 status = IXGBE_ERR_SWFW_SYNC;
427
428 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
429 return status;
430 }
431
432 /**
433 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
434 * @hw: pointer to hardware structure
435 * @offset: offset of word in the EEPROM to write
436 * @words: number of words
437 * @data: word(s) write to the EEPROM
438 *
439 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
440 **/
441 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
442 u16 offset, u16 words, u16 *data)
443 {
444 s32 status = IXGBE_SUCCESS;
445
446 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
447 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
448 IXGBE_SUCCESS)
449 status = ixgbe_write_eewr_buffer_generic(hw, offset,
450 words, data);
451 else
452 status = IXGBE_ERR_SWFW_SYNC;
453
454 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
455 return status;
456 }
457
458 /**
459 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
460 *
461 * This function does not use synchronization for EERD and EEWR. It can
462 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
463 *
464 * @hw: pointer to hardware structure
465 **/
466 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
467 {
468 u16 i;
469 u16 j;
470 u16 checksum = 0;
471 u16 length = 0;
472 u16 pointer = 0;
473 u16 word = 0;
474
475 /*
476 * Do not use hw->eeprom.ops.read because we do not want to take
477 * the synchronization semaphores here. Instead use
478 * ixgbe_read_eerd_generic
479 */
480
481 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
482
483 /* Include 0x0-0x3F in the checksum */
484 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
485 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
486 DEBUGOUT("EEPROM read failed\n");
487 break;
488 }
489 checksum += word;
490 }
491
492 /*
493 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
494 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
495 */
496 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
497 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
498 continue;
499
500 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
501 DEBUGOUT("EEPROM read failed\n");
502 break;
503 }
504
505 /* Skip pointer section if the pointer is invalid. */
506 if (pointer == 0xFFFF || pointer == 0 ||
507 pointer >= hw->eeprom.word_size)
508 continue;
509
510 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
511 IXGBE_SUCCESS) {
512 DEBUGOUT("EEPROM read failed\n");
513 break;
514 }
515
516 /* Skip pointer section if length is invalid. */
517 if (length == 0xFFFF || length == 0 ||
518 (pointer + length) >= hw->eeprom.word_size)
519 continue;
520
521 for (j = pointer+1; j <= pointer+length; j++) {
522 if (ixgbe_read_eerd_generic(hw, j, &word) !=
523 IXGBE_SUCCESS) {
524 DEBUGOUT("EEPROM read failed\n");
525 break;
526 }
527 checksum += word;
528 }
529 }
530
531 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
532
533 return checksum;
534 }
535
536 /**
537 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
538 * @hw: pointer to hardware structure
539 * @checksum_val: calculated checksum
540 *
541 * Performs checksum calculation and validates the EEPROM checksum. If the
542 * caller does not need checksum_val, the value can be NULL.
543 **/
544 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
545 u16 *checksum_val)
546 {
547 s32 status;
548 u16 checksum;
549 u16 read_checksum = 0;
550
551 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
552
553 /*
554 * Read the first word from the EEPROM. If this times out or fails, do
555 * not continue or we could be in for a very long wait while every
556 * EEPROM read fails
557 */
558 status = hw->eeprom.ops.read(hw, 0, &checksum);
559
560 if (status != IXGBE_SUCCESS) {
561 DEBUGOUT("EEPROM read failed\n");
562 goto out;
563 }
564
565 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
566 IXGBE_SUCCESS) {
567 checksum = hw->eeprom.ops.calc_checksum(hw);
568
569 /*
570 * Do not use hw->eeprom.ops.read because we do not want to take
571 * the synchronization semaphores twice here.
572 */
573 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
574 &read_checksum);
575
576 if (status == IXGBE_SUCCESS) {
577 /*
578 * Verify read checksum from EEPROM is the same as
579 * calculated checksum
580 */
581 if (read_checksum != checksum)
582 status = IXGBE_ERR_EEPROM_CHECKSUM;
583
584 /* If the user cares, return the calculated checksum */
585 if (checksum_val)
586 *checksum_val = checksum;
587 }
588 } else {
589 status = IXGBE_ERR_SWFW_SYNC;
590 }
591
592 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
593 out:
594 return status;
595 }
596
597 /**
598 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
599 * @hw: pointer to hardware structure
600 *
601 * After writing EEPROM to shadow RAM using EEWR register, software calculates
602 * checksum and updates the EEPROM and instructs the hardware to update
603 * the flash.
604 **/
605 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
606 {
607 s32 status;
608 u16 checksum;
609
610 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
611
612 /*
613 * Read the first word from the EEPROM. If this times out or fails, do
614 * not continue or we could be in for a very long wait while every
615 * EEPROM read fails
616 */
617 status = hw->eeprom.ops.read(hw, 0, &checksum);
618
619 if (status != IXGBE_SUCCESS)
620 DEBUGOUT("EEPROM read failed\n");
621
622 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
623 IXGBE_SUCCESS) {
624 checksum = hw->eeprom.ops.calc_checksum(hw);
625
626 /*
627 * Do not use hw->eeprom.ops.write because we do not want to
628 * take the synchronization semaphores twice here.
629 */
630 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
631 checksum);
632
633 if (status == IXGBE_SUCCESS)
634 status = ixgbe_update_flash_X540(hw);
635 else
636 status = IXGBE_ERR_SWFW_SYNC;
637 }
638
639 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
640
641 return status;
642 }
643
644 /**
645 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
646 * @hw: pointer to hardware structure
647 *
648 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
649 * EEPROM from shadow RAM to the flash device.
650 **/
651 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
652 {
653 u32 flup;
654 s32 status = IXGBE_ERR_EEPROM;
655
656 DEBUGFUNC("ixgbe_update_flash_X540");
657
658 status = ixgbe_poll_flash_update_done_X540(hw);
659 if (status == IXGBE_ERR_EEPROM) {
660 DEBUGOUT("Flash update time out\n");
661 goto out;
662 }
663
664 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
665 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
666
667 status = ixgbe_poll_flash_update_done_X540(hw);
668 if (status == IXGBE_SUCCESS)
669 DEBUGOUT("Flash update complete\n");
670 else
671 DEBUGOUT("Flash update time out\n");
672
673 if (hw->revision_id == 0) {
674 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
675
676 if (flup & IXGBE_EEC_SEC1VAL) {
677 flup |= IXGBE_EEC_FLUP;
678 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
679 }
680
681 status = ixgbe_poll_flash_update_done_X540(hw);
682 if (status == IXGBE_SUCCESS)
683 DEBUGOUT("Flash update complete\n");
684 else
685 DEBUGOUT("Flash update time out\n");
686 }
687 out:
688 return status;
689 }
690
691 /**
692 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
693 * @hw: pointer to hardware structure
694 *
695 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
696 * flash update is done.
697 **/
698 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
699 {
700 u32 i;
701 u32 reg;
702 s32 status = IXGBE_ERR_EEPROM;
703
704 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
705
706 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
707 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
708 if (reg & IXGBE_EEC_FLUDONE) {
709 status = IXGBE_SUCCESS;
710 break;
711 }
712 usec_delay(5);
713 }
714 return status;
715 }
716
717 /**
718 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
719 * @hw: pointer to hardware structure
720 * @mask: Mask to specify which semaphore to acquire
721 *
722 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
723 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
724 **/
725 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
726 {
727 u32 swfw_sync;
728 u32 swmask = mask;
729 u32 fwmask = mask << 5;
730 u32 hwmask = 0;
731 u32 timeout = 200;
732 u32 i;
733 s32 ret_val = IXGBE_SUCCESS;
734
735 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
736
737 if (swmask == IXGBE_GSSR_EEP_SM)
738 hwmask = IXGBE_GSSR_FLASH_SM;
739
740 /* SW only mask doesn't have FW bit pair */
741 if (swmask == IXGBE_GSSR_SW_MNG_SM)
742 fwmask = 0;
743
744 for (i = 0; i < timeout; i++) {
745 /*
746 * SW NVM semaphore bit is used for access to all
747 * SW_FW_SYNC bits (not just NVM)
748 */
749 if (ixgbe_get_swfw_sync_semaphore(hw)) {
750 ret_val = IXGBE_ERR_SWFW_SYNC;
751 goto out;
752 }
753
754 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
755 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
756 swfw_sync |= swmask;
757 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
758 ixgbe_release_swfw_sync_semaphore(hw);
759 msec_delay(5);
760 goto out;
761 } else {
762 /*
763 * Firmware currently using resource (fwmask), hardware
764 * currently using resource (hwmask), or other software
765 * thread currently using resource (swmask)
766 */
767 ixgbe_release_swfw_sync_semaphore(hw);
768 msec_delay(5);
769 }
770 }
771
772 /* Failed to get SW only semaphore */
773 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
774 ret_val = IXGBE_ERR_SWFW_SYNC;
775 goto out;
776 }
777
778 /* If the resource is not released by the FW/HW the SW can assume that
779 * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
780 * of the requested resource(s) while ignoring the corresponding FW/HW
781 * bits in the SW_FW_SYNC register.
782 */
783 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
784 if (swfw_sync & (fwmask | hwmask)) {
785 if (ixgbe_get_swfw_sync_semaphore(hw)) {
786 ret_val = IXGBE_ERR_SWFW_SYNC;
787 goto out;
788 }
789
790 swfw_sync |= swmask;
791 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
792 ixgbe_release_swfw_sync_semaphore(hw);
793 msec_delay(5);
794 }
795
796 out:
797 return ret_val;
798 }
799
800 /**
801 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
802 * @hw: pointer to hardware structure
803 * @mask: Mask to specify which semaphore to release
804 *
805 * Releases the SWFW semaphore through the SW_FW_SYNC register
806 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
807 **/
808 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
809 {
810 u32 swfw_sync;
811 u32 swmask = mask;
812
813 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
814
815 (void) ixgbe_get_swfw_sync_semaphore(hw);
816
817 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
818 swfw_sync &= ~swmask;
819 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
820
821 ixgbe_release_swfw_sync_semaphore(hw);
822 msec_delay(5);
823 }
824
825 /**
826 * ixgbe_get_nvm_semaphore - Get hardware semaphore
827 * @hw: pointer to hardware structure
828 *
829 * Sets the hardware semaphores so SW/FW can gain control of shared resources
830 **/
831 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
832 {
833 s32 status = IXGBE_ERR_EEPROM;
834 u32 timeout = 2000;
835 u32 i;
836 u32 swsm;
837
838 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
839
840 /* Get SMBI software semaphore between device drivers first */
841 for (i = 0; i < timeout; i++) {
842 /*
843 * If the SMBI bit is 0 when we read it, then the bit will be
844 * set and we have the semaphore
845 */
846 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
847 if (!(swsm & IXGBE_SWSM_SMBI)) {
848 status = IXGBE_SUCCESS;
849 break;
850 }
851 usec_delay(50);
852 }
853
854 /* Now get the semaphore between SW/FW through the REGSMP bit */
855 if (status == IXGBE_SUCCESS) {
856 for (i = 0; i < timeout; i++) {
857 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
858 if (!(swsm & IXGBE_SWFW_REGSMP))
859 break;
860
861 usec_delay(50);
862 }
863
864 /*
865 * Release semaphores and return error if SW NVM semaphore
866 * was not granted because we don't have access to the EEPROM
867 */
868 if (i >= timeout) {
869 DEBUGOUT("REGSMP Software NVM semaphore not "
870 "granted.\n");
871 ixgbe_release_swfw_sync_semaphore(hw);
872 status = IXGBE_ERR_EEPROM;
873 }
874 } else {
875 DEBUGOUT("Software semaphore SMBI between device drivers "
876 "not granted.\n");
877 }
878
879 return status;
880 }
881
882 /**
883 * ixgbe_release_nvm_semaphore - Release hardware semaphore
884 * @hw: pointer to hardware structure
885 *
886 * This function clears hardware semaphore bits.
887 **/
888 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
889 {
890 u32 swsm;
891
892 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
893
894 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
895
896 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
897 swsm &= ~IXGBE_SWSM_SMBI;
898 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
899
900 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
901 swsm &= ~IXGBE_SWFW_REGSMP;
902 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
903
904 IXGBE_WRITE_FLUSH(hw);
905 }
906
907 /**
908 * ixgbe_blink_led_start_X540 - Blink LED based on index.
909 * @hw: pointer to hardware structure
910 * @index: led number to blink
911 *
912 * Devices that implement the version 2 interface:
913 * X540
914 **/
915 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
916 {
917 u32 macc_reg;
918 u32 ledctl_reg;
919 ixgbe_link_speed speed;
920 bool link_up;
921
922 DEBUGFUNC("ixgbe_blink_led_start_X540");
923
924 /*
925 * Link should be up in order for the blink bit in the LED control
926 * register to work. Force link and speed in the MAC if link is down.
927 * This will be reversed when we stop the blinking.
928 */
929 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
930 if (link_up == FALSE) {
931 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
932 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
933 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
934 }
935 /* Set the LED to LINK_UP + BLINK. */
936 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
937 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
938 ledctl_reg |= IXGBE_LED_BLINK(index);
939 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
940 IXGBE_WRITE_FLUSH(hw);
941
942 return IXGBE_SUCCESS;
943 }
944
945 /**
946 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
947 * @hw: pointer to hardware structure
948 * @index: led number to stop blinking
949 *
950 * Devices that implement the version 2 interface:
951 * X540
952 **/
953 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
954 {
955 u32 macc_reg;
956 u32 ledctl_reg;
957
958 DEBUGFUNC("ixgbe_blink_led_stop_X540");
959
960 /* Restore the LED to its default value. */
961 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
962 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
963 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
964 ledctl_reg &= ~IXGBE_LED_BLINK(index);
965 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
966
967 /* Unforce link and speed in the MAC. */
968 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
969 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
970 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
971 IXGBE_WRITE_FLUSH(hw);
972
973 return IXGBE_SUCCESS;
974 }
975