Print this page
6064 ixgbe needs X550 support
   1 /******************************************************************************
   2 
   3   Copyright (c) 2001-2012, Intel Corporation 
   4   All rights reserved.
   5   
   6   Redistribution and use in source and binary forms, with or without 
   7   modification, are permitted provided that the following conditions are met:
   8   
   9    1. Redistributions of source code must retain the above copyright notice, 
  10       this list of conditions and the following disclaimer.
  11   
  12    2. Redistributions in binary form must reproduce the above copyright 
  13       notice, this list of conditions and the following disclaimer in the 
  14       documentation and/or other materials provided with the distribution.
  15   
  16    3. Neither the name of the Intel Corporation nor the names of its 
  17       contributors may be used to endorse or promote products derived from 
  18       this software without specific prior written permission.
  19   
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31 
  32 ******************************************************************************/
  33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_type.h,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
  34 
  35 #ifndef _IXGBE_TYPE_H_
  36 #define _IXGBE_TYPE_H_
  37 






































  38 #include "ixgbe_osdep.h"
  39 


  40 
  41 /* Vendor ID */
  42 #define IXGBE_INTEL_VENDOR_ID                   0x8086
  43 
  44 /* Device IDs */
  45 #define IXGBE_DEV_ID_82598                      0x10B6
  46 #define IXGBE_DEV_ID_82598_BX                   0x1508
  47 #define IXGBE_DEV_ID_82598AF_DUAL_PORT          0x10C6
  48 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT        0x10C7
  49 #define IXGBE_DEV_ID_82598AT                    0x10C8
  50 #define IXGBE_DEV_ID_82598AT2                   0x150B
  51 #define IXGBE_DEV_ID_82598EB_SFP_LOM            0x10DB
  52 #define IXGBE_DEV_ID_82598EB_CX4                0x10DD
  53 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT        0x10EC
  54 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT         0x10F1
  55 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
  56 #define IXGBE_DEV_ID_82598EB_XF_LR              0x10F4
  57 #define IXGBE_DEV_ID_82599_KX4                  0x10F7
  58 #define IXGBE_DEV_ID_82599_KX4_MEZZ             0x1514
  59 #define IXGBE_DEV_ID_82599_KR                   0x1517
  60 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE      0x10F8
  61 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ       0x000C
  62 #define IXGBE_DEV_ID_82599_CX4                  0x10F9
  63 #define IXGBE_DEV_ID_82599_SFP                  0x10FB
  64 #define IXGBE_SUBDEV_ID_82599_SFP               0x11A9


  65 #define IXGBE_SUBDEV_ID_82599_560FLR            0x17D0







  66 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152A
  67 #define IXGBE_DEV_ID_82599_SFP_FCOE             0x1529
  68 #define IXGBE_DEV_ID_82599_SFP_EM               0x1507
  69 #define IXGBE_DEV_ID_82599_SFP_SF2              0x154D


  70 #define IXGBE_DEV_ID_82599EN_SFP                0x1557

  71 #define IXGBE_DEV_ID_82599_XAUI_LOM             0x10FC
  72 #define IXGBE_DEV_ID_82599_T3_LOM               0x151C
  73 #define IXGBE_DEV_ID_82599_VF                   0x10ED
  74 #define IXGBE_DEV_ID_X540_VF                    0x1515

  75 #define IXGBE_DEV_ID_X540T                      0x1528



  76 #define IXGBE_DEV_ID_X540T1                     0x1560











  77 




  78 /* General Registers */
  79 #define IXGBE_CTRL              0x00000
  80 #define IXGBE_STATUS            0x00008
  81 #define IXGBE_CTRL_EXT          0x00018
  82 #define IXGBE_ESDP              0x00020
  83 #define IXGBE_EODSDP            0x00028
  84 #define IXGBE_I2CCTL            0x00028





  85 #define IXGBE_PHY_GPIO          0x00028
  86 #define IXGBE_MAC_GPIO          0x00030
  87 #define IXGBE_PHYINT_STATUS0    0x00100
  88 #define IXGBE_PHYINT_STATUS1    0x00104
  89 #define IXGBE_PHYINT_STATUS2    0x00108
  90 #define IXGBE_LEDCTL            0x00200
  91 #define IXGBE_FRTIMER           0x00048
  92 #define IXGBE_TCPTIMER          0x0004C
  93 #define IXGBE_CORESPARE         0x00600
  94 #define IXGBE_EXVET             0x05078
  95 
  96 /* NVM Registers */
  97 #define IXGBE_EEC       0x10010





  98 #define IXGBE_EERD      0x10014
  99 #define IXGBE_EEWR      0x10018

 100 #define IXGBE_FLA       0x1001C





 101 #define IXGBE_EEMNGCTL  0x10110
 102 #define IXGBE_EEMNGDATA 0x10114
 103 #define IXGBE_FLMNGCTL  0x10118
 104 #define IXGBE_FLMNGDATA 0x1011C
 105 #define IXGBE_FLMNGCNT  0x10120
 106 #define IXGBE_FLOP      0x1013C

 107 #define IXGBE_GRC       0x10200





 108 #define IXGBE_SRAMREL   0x10210





 109 #define IXGBE_PHYDBG    0x10218
 110 
 111 /* General Receive Control */
 112 #define IXGBE_GRC_MNG   0x00000001 /* Manageability Enable */
 113 #define IXGBE_GRC_APME  0x00000002 /* APM enabled in EEPROM */
 114 
 115 #define IXGBE_VPDDIAG0  0x10204
 116 #define IXGBE_VPDDIAG1  0x10208
 117 
 118 /* I2CCTL Bit Masks */
 119 #define IXGBE_I2C_CLK_IN        0x00000001





 120 #define IXGBE_I2C_CLK_OUT       0x00000002





 121 #define IXGBE_I2C_DATA_IN       0x00000004





 122 #define IXGBE_I2C_DATA_OUT      0x00000008























 123 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT      500
 124 
 125 
 126 /* Interrupt Registers */
 127 #define IXGBE_EICR              0x00800
 128 #define IXGBE_EICS              0x00808
 129 #define IXGBE_EIMS              0x00880
 130 #define IXGBE_EIMC              0x00888
 131 #define IXGBE_EIAC              0x00810
 132 #define IXGBE_EIAM              0x00890
 133 #define IXGBE_EICS_EX(_i)       (0x00A90 + (_i) * 4)
 134 #define IXGBE_EIMS_EX(_i)       (0x00AA0 + (_i) * 4)
 135 #define IXGBE_EIMC_EX(_i)       (0x00AB0 + (_i) * 4)
 136 #define IXGBE_EIAM_EX(_i)       (0x00AD0 + (_i) * 4)
 137 /* 82599 EITR is only 12 bits, with the lower 3 always zero */
 138 /*
 139  * 82598 EITR is 16 bits but set the limits based on the max
 140  * supported by all ixgbe hardware
 141  */
 142 #define IXGBE_MAX_INT_RATE      488281


 192 #define IXGBE_STARCTRL  0x03024
 193 /*
 194  * Split and Replication Receive Control Registers
 195  * 00-15 : 0x02100 + n*4
 196  * 16-64 : 0x01014 + n*0x40
 197  * 64-127: 0x0D014 + (n-64)*0x40
 198  */
 199 #define IXGBE_SRRCTL(_i)        (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
 200                                  (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
 201                                  (0x0D014 + (((_i) - 64) * 0x40))))
 202 /*
 203  * Rx DCA Control Register:
 204  * 00-15 : 0x02200 + n*4
 205  * 16-64 : 0x0100C + n*0x40
 206  * 64-127: 0x0D00C + (n-64)*0x40
 207  */
 208 #define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
 209                                  (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
 210                                  (0x0D00C + (((_i) - 64) * 0x40))))
 211 #define IXGBE_RDRXCTL           0x02F00
 212 #define IXGBE_RDRXCTL_RSC_PUSH  0x80
 213 /* 8 of these 0x03C00 - 0x03C1C */
 214 #define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
 215 #define IXGBE_RXCTRL            0x03000
 216 #define IXGBE_DROPEN            0x03D04
 217 #define IXGBE_RXPBSIZE_SHIFT    10

 218 
 219 /* Receive Registers */
 220 #define IXGBE_RXCSUM            0x05000
 221 #define IXGBE_RFCTL             0x05008
 222 #define IXGBE_DRECCCTL          0x02F08
 223 #define IXGBE_DRECCCTL_DISABLE  0
 224 #define IXGBE_DRECCCTL2         0x02F8C
 225 
 226 /* Multicast Table Array - 128 entries */
 227 #define IXGBE_MTA(_i)           (0x05200 + ((_i) * 4))
 228 #define IXGBE_RAL(_i)           (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
 229                                  (0x0A200 + ((_i) * 8)))
 230 #define IXGBE_RAH(_i)           (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
 231                                  (0x0A204 + ((_i) * 8)))
 232 #define IXGBE_MPSAR_LO(_i)      (0x0A600 + ((_i) * 8))
 233 #define IXGBE_MPSAR_HI(_i)      (0x0A604 + ((_i) * 8))
 234 /* Packet split receive type */
 235 #define IXGBE_PSRTYPE(_i)       (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
 236                                  (0x0EA00 + ((_i) * 4)))
 237 /* array of 4096 1-bit vlan filters */
 238 #define IXGBE_VFTA(_i)          (0x0A000 + ((_i) * 4))
 239 /*array of 4096 4-bit vlan vmdq indices */
 240 #define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
 241 #define IXGBE_FCTRL             0x05080
 242 #define IXGBE_VLNCTRL           0x05088
 243 #define IXGBE_MCSTCTRL          0x05090
 244 #define IXGBE_MRQC              0x05818
 245 #define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
 246 #define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
 247 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
 248 #define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
 249 #define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
 250 #define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
 251 #define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
 252 #define IXGBE_RQTC      0x0EC70
 253 #define IXGBE_MTQC      0x08120
 254 #define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
 255 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
 256 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */


 257 #define IXGBE_VT_CTL            0x051B0
 258 #define IXGBE_PFMAILBOX(_i)     (0x04B00 + (4 * (_i))) /* 64 total */
 259 /* 64 Mailboxes, 16 DW each */
 260 #define IXGBE_PFMBMEM(_i)       (0x13000 + (64 * (_i)))
 261 #define IXGBE_PFMBICR(_i)       (0x00710 + (4 * (_i))) /* 4 total */
 262 #define IXGBE_PFMBIMR(_i)       (0x00720 + (4 * (_i))) /* 4 total */
 263 #define IXGBE_VFRE(_i)          (0x051E0 + ((_i) * 4))
 264 #define IXGBE_VFTE(_i)          (0x08110 + ((_i) * 4))
 265 #define IXGBE_VMECM(_i)         (0x08790 + ((_i) * 4))
 266 #define IXGBE_QDE               0x2F04
 267 #define IXGBE_VMTXSW(_i)        (0x05180 + ((_i) * 4)) /* 2 total */
 268 #define IXGBE_VMOLR(_i)         (0x0F000 + ((_i) * 4)) /* 64 total */
 269 #define IXGBE_UTA(_i)           (0x0F400 + ((_i) * 4))
 270 #define IXGBE_MRCTL(_i)         (0x0F600 + ((_i) * 4))
 271 #define IXGBE_VMRVLAN(_i)       (0x0F610 + ((_i) * 4))
 272 #define IXGBE_VMRVM(_i)         (0x0F630 + ((_i) * 4))






 273 #define IXGBE_L34T_IMIR(_i)     (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
 274 #define IXGBE_RXFECCERR0        0x051B8
 275 #define IXGBE_LLITHRESH         0x0EC90
 276 #define IXGBE_IMIR(_i)          (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
 277 #define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
 278 #define IXGBE_IMIRVP            0x05AC0
 279 #define IXGBE_VMD_CTL           0x0581C
 280 #define IXGBE_RETA(_i)          (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */

 281 #define IXGBE_RSSRK(_i)         (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 282 








 283 /* Flow Director registers */
 284 #define IXGBE_FDIRCTRL  0x0EE00
 285 #define IXGBE_FDIRHKEY  0x0EE68
 286 #define IXGBE_FDIRSKEY  0x0EE6C
 287 #define IXGBE_FDIRDIP4M 0x0EE3C
 288 #define IXGBE_FDIRSIP4M 0x0EE40
 289 #define IXGBE_FDIRTCPM  0x0EE44
 290 #define IXGBE_FDIRUDPM  0x0EE48

 291 #define IXGBE_FDIRIP6M  0x0EE74
 292 #define IXGBE_FDIRM     0x0EE70
 293 
 294 /* Flow Director Stats registers */
 295 #define IXGBE_FDIRFREE  0x0EE38
 296 #define IXGBE_FDIRLEN   0x0EE4C
 297 #define IXGBE_FDIRUSTAT 0x0EE50
 298 #define IXGBE_FDIRFSTAT 0x0EE54
 299 #define IXGBE_FDIRMATCH 0x0EE58
 300 #define IXGBE_FDIRMISS  0x0EE5C
 301 
 302 /* Flow Director Programming registers */
 303 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
 304 #define IXGBE_FDIRIPSA  0x0EE18
 305 #define IXGBE_FDIRIPDA  0x0EE1C
 306 #define IXGBE_FDIRPORT  0x0EE20
 307 #define IXGBE_FDIRVLAN  0x0EE24
 308 #define IXGBE_FDIRHASH  0x0EE28
 309 #define IXGBE_FDIRCMD   0x0EE2C
 310 


 314 #define IXGBE_TDLEN(_i)         (0x06008 + ((_i) * 0x40))
 315 #define IXGBE_TDH(_i)           (0x06010 + ((_i) * 0x40))
 316 #define IXGBE_TDT(_i)           (0x06018 + ((_i) * 0x40))
 317 #define IXGBE_TXDCTL(_i)        (0x06028 + ((_i) * 0x40))
 318 #define IXGBE_TDWBAL(_i)        (0x06038 + ((_i) * 0x40))
 319 #define IXGBE_TDWBAH(_i)        (0x0603C + ((_i) * 0x40))
 320 #define IXGBE_DTXCTL            0x07E00
 321 
 322 #define IXGBE_DMATXCTL          0x04A80
 323 #define IXGBE_PFVFSPOOF(_i)     (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
 324 #define IXGBE_PFDTXGSWC         0x08220
 325 #define IXGBE_DTXMXSZRQ         0x08100
 326 #define IXGBE_DTXTCPFLGL        0x04A88
 327 #define IXGBE_DTXTCPFLGH        0x04A8C
 328 #define IXGBE_LBDRPEN           0x0CA00
 329 #define IXGBE_TXPBTHRESH(_i)    (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
 330 
 331 #define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
 332 #define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
 333 #define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */


 334 #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 335 
 336 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
 337 
 338 /* Anti-spoofing defines */
 339 #define IXGBE_SPOOF_MACAS_MASK          0xFF
 340 #define IXGBE_SPOOF_VLANAS_MASK         0xFF00
 341 #define IXGBE_SPOOF_VLANAS_SHIFT        8


 342 #define IXGBE_PFVFSPOOF_REG_COUNT       8
 343 /* 16 of these (0-15) */
 344 #define IXGBE_DCA_TXCTRL(_i)            (0x07200 + ((_i) * 4))
 345 /* Tx DCA Control register : 128 of these (0-127) */
 346 #define IXGBE_DCA_TXCTRL_82599(_i)      (0x0600C + ((_i) * 0x40))
 347 #define IXGBE_TIPG                      0x0CB00
 348 #define IXGBE_TXPBSIZE(_i)              (0x0CC00 + ((_i) * 4)) /* 8 of these */
 349 #define IXGBE_MNGTXMAP                  0x0CD10
 350 #define IXGBE_TIPG_FIBER_DEFAULT        3
 351 #define IXGBE_TXPBSIZE_SHIFT            10
 352 
 353 /* Wake up registers */
 354 #define IXGBE_WUC       0x05800
 355 #define IXGBE_WUFC      0x05808
 356 #define IXGBE_WUS       0x05810
 357 #define IXGBE_IPAV      0x05838
 358 #define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
 359 #define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
 360 
 361 #define IXGBE_WUPL      0x05900
 362 #define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
 363 #define IXGBE_FHFT(_n)  (0x09000 + (_n * 0x100)) /* Flex host filter table */




 364 /* Ext Flexible Host Filter Table */
 365 #define IXGBE_FHFT_EXT(_n)      (0x09800 + (_n * 0x100))

 366 

 367 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4





 368 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
 369 
 370 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
 371 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX          128
 372 #define IXGBE_FHFT_LENGTH_OFFSET                0xFC  /* Length byte in FHFT */
 373 #define IXGBE_FHFT_LENGTH_MASK                  0x0FF /* Length in lower byte */
 374 
 375 /* Definitions for power management and wakeup registers */
 376 /* Wake Up Control */
 377 #define IXGBE_WUC_PME_EN        0x00000002 /* PME Enable */
 378 #define IXGBE_WUC_PME_STATUS    0x00000004 /* PME Status */
 379 #define IXGBE_WUC_WKEN          0x00000010 /* Enable PE_WAKE_N pin assertion  */
 380 
 381 /* Wake Up Filter Control */
 382 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
 383 #define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
 384 #define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
 385 #define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
 386 #define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
 387 #define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
 388 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
 389 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 390 #define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
 391 
 392 #define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
 393 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
 394 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
 395 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
 396 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
 397 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
 398 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
 399 #define IXGBE_WUFC_FLX_FILTERS  0x000F0000 /* Mask for 4 flex filters */



 400 /* Mask for Ext. flex filters */
 401 #define IXGBE_WUFC_EXT_FLX_FILTERS      0x00300000
 402 #define IXGBE_WUFC_ALL_FILTERS  0x003F00FF /* Mask for all wakeup filters */


 403 #define IXGBE_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
 404 
 405 /* Wake Up Status */
 406 #define IXGBE_WUS_LNKC          IXGBE_WUFC_LNKC
 407 #define IXGBE_WUS_MAG           IXGBE_WUFC_MAG
 408 #define IXGBE_WUS_EX            IXGBE_WUFC_EX
 409 #define IXGBE_WUS_MC            IXGBE_WUFC_MC
 410 #define IXGBE_WUS_BC            IXGBE_WUFC_BC
 411 #define IXGBE_WUS_ARP           IXGBE_WUFC_ARP
 412 #define IXGBE_WUS_IPV4          IXGBE_WUFC_IPV4
 413 #define IXGBE_WUS_IPV6          IXGBE_WUFC_IPV6
 414 #define IXGBE_WUS_MNG           IXGBE_WUFC_MNG
 415 #define IXGBE_WUS_FLX0          IXGBE_WUFC_FLX0
 416 #define IXGBE_WUS_FLX1          IXGBE_WUFC_FLX1
 417 #define IXGBE_WUS_FLX2          IXGBE_WUFC_FLX2
 418 #define IXGBE_WUS_FLX3          IXGBE_WUFC_FLX3
 419 #define IXGBE_WUS_FLX4          IXGBE_WUFC_FLX4
 420 #define IXGBE_WUS_FLX5          IXGBE_WUFC_FLX5
 421 #define IXGBE_WUS_FLX_FILTERS   IXGBE_WUFC_FLX_FILTERS








 422 
 423 /* Wake Up Packet Length */








 424 #define IXGBE_WUPL_LENGTH_MASK  0xFFFF
 425 
 426 /* DCB registers */
 427 #define IXGBE_DCB_MAX_TRAFFIC_CLASS     8
 428 #define IXGBE_RMCS              0x03D00
 429 #define IXGBE_DPMCS             0x07F40
 430 #define IXGBE_PDPMCS            0x0CD00
 431 #define IXGBE_RUPPBMR           0x050A0
 432 #define IXGBE_RT2CR(_i)         (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
 433 #define IXGBE_RT2SR(_i)         (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
 434 #define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
 435 #define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
 436 #define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 437 #define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 438 









 439 











































 440 /* Security Control Registers */
 441 #define IXGBE_SECTXCTRL         0x08800
 442 #define IXGBE_SECTXSTAT         0x08804
 443 #define IXGBE_SECTXBUFFAF       0x08808
 444 #define IXGBE_SECTXMINIFG       0x08810
 445 #define IXGBE_SECRXCTRL         0x08D00
 446 #define IXGBE_SECRXSTAT         0x08D04
 447 
 448 /* Security Bit Fields and Masks */
 449 #define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
 450 #define IXGBE_SECTXCTRL_TX_DIS          0x00000002
 451 #define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
 452 
 453 #define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
 454 #define IXGBE_SECTXSTAT_ECC_TXERR       0x00000002
 455 
 456 #define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
 457 #define IXGBE_SECRXCTRL_RX_DIS          0x00000002
 458 
 459 #define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001


 557 #define IXGBE_RTTBCNRC                  0x04984
 558 #define IXGBE_RTTBCNRC_RS_ENA           0x80000000
 559 #define IXGBE_RTTBCNRC_RF_DEC_MASK      0x00003FFF
 560 #define IXGBE_RTTBCNRC_RF_INT_SHIFT     14
 561 #define IXGBE_RTTBCNRC_RF_INT_MASK \
 562         (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
 563 #define IXGBE_RTTBCNRM  0x04980
 564 
 565 /* BCN (for DCB) Registers */
 566 #define IXGBE_RTTBCNRS  0x04988
 567 #define IXGBE_RTTBCNCR  0x08B00
 568 #define IXGBE_RTTBCNACH 0x08B04
 569 #define IXGBE_RTTBCNACL 0x08B08
 570 #define IXGBE_RTTBCNTG  0x04A90
 571 #define IXGBE_RTTBCNIDX 0x08B0C
 572 #define IXGBE_RTTBCNCP  0x08B10
 573 #define IXGBE_RTFRTIMER 0x08B14
 574 #define IXGBE_RTTBCNRTT 0x05150
 575 #define IXGBE_RTTBCNRD  0x0498C
 576 

 577 /* FCoE DMA Context Registers */


 578 #define IXGBE_FCPTRL            0x02410 /* FC User Desc. PTR Low */
 579 #define IXGBE_FCPTRH            0x02414 /* FC USer Desc. PTR High */
 580 #define IXGBE_FCBUFF            0x02418 /* FC Buffer Control */
 581 #define IXGBE_FCDMARW           0x02420 /* FC Receive DMA RW */
 582 #define IXGBE_FCINVST0          0x03FC0 /* FC Invalid DMA Context Status Reg 0*/
 583 #define IXGBE_FCINVST(_i)       (IXGBE_FCINVST0 + ((_i) * 4))
 584 #define IXGBE_FCBUFF_VALID      (1 << 0)   /* DMA Context Valid */
 585 #define IXGBE_FCBUFF_BUFFSIZE   (3 << 3)   /* User Buffer Size */
 586 #define IXGBE_FCBUFF_WRCONTX    (1 << 7)   /* 0: Initiator, 1: Target */
 587 #define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
 588 #define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
 589 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT     3
 590 #define IXGBE_FCBUFF_BUFFCNT_SHIFT      8
 591 #define IXGBE_FCBUFF_OFFSET_SHIFT       16
 592 #define IXGBE_FCDMARW_WE                (1 << 14)   /* Write enable */
 593 #define IXGBE_FCDMARW_RE                (1 << 15)   /* Read enable */
 594 #define IXGBE_FCDMARW_FCOESEL           0x000001ff  /* FC X_ID: 11 bits */
 595 #define IXGBE_FCDMARW_LASTSIZE          0xffff0000  /* Last User Buffer Size */
 596 #define IXGBE_FCDMARW_LASTSIZE_SHIFT    16
 597 /* FCoE SOF/EOF */
 598 #define IXGBE_TEOFF             0x04A94 /* Tx FC EOF */
 599 #define IXGBE_TSOFF             0x04A98 /* Tx FC SOF */
 600 #define IXGBE_REOFF             0x05158 /* Rx FC EOF */
 601 #define IXGBE_RSOFF             0x051F8 /* Rx FC SOF */
 602 /* FCoE Filter Context Registers */






 603 #define IXGBE_FCFLT             0x05108 /* FC FLT Context */
 604 #define IXGBE_FCFLTRW           0x05110 /* FC Filter RW Control */
 605 #define IXGBE_FCPARAM           0x051d8 /* FC Offset Parameter */
 606 #define IXGBE_FCFLT_VALID       (1 << 0)   /* Filter Context Valid */
 607 #define IXGBE_FCFLT_FIRST       (1 << 1)   /* Filter First */
 608 #define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
 609 #define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
 610 #define IXGBE_FCFLTRW_RVALDT    (1 << 13)  /* Fast Re-Validation */
 611 #define IXGBE_FCFLTRW_WE        (1 << 14)  /* Write Enable */
 612 #define IXGBE_FCFLTRW_RE        (1 << 15)  /* Read Enable */
 613 /* FCoE Receive Control */
 614 #define IXGBE_FCRXCTRL          0x05100 /* FC Receive Control */
 615 #define IXGBE_FCRXCTRL_FCOELLI  (1 << 0)   /* Low latency interrupt */
 616 #define IXGBE_FCRXCTRL_SAVBAD   (1 << 1)   /* Save Bad Frames */
 617 #define IXGBE_FCRXCTRL_FRSTRDH  (1 << 2)   /* EN 1st Read Header */
 618 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)   /* EN Last Header in Seq */
 619 #define IXGBE_FCRXCTRL_ALLH     (1 << 4)   /* EN All Headers */
 620 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)   /* EN 1st Seq. Header */
 621 #define IXGBE_FCRXCTRL_ICRC     (1 << 6)   /* Ignore Bad FC CRC */
 622 #define IXGBE_FCRXCTRL_FCCRCBO  (1 << 7)   /* FC CRC Byte Ordering */
 623 #define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
 624 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT    8
 625 /* FCoE Redirection */
 626 #define IXGBE_FCRECTL           0x0ED00 /* FC Redirection Control */
 627 #define IXGBE_FCRETA0           0x0ED10 /* FC Redirection Table 0 */
 628 #define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
 629 #define IXGBE_FCRECTL_ENA       0x1 /* FCoE Redir Table Enable */
 630 #define IXGBE_FCRETASEL_ENA     0x2 /* FCoE FCRETASEL bit */
 631 #define IXGBE_FCRETA_SIZE       8 /* Max entries in FCRETA */
 632 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */




 633 
 634 /* Stats registers */
 635 #define IXGBE_CRCERRS   0x04000
 636 #define IXGBE_ILLERRC   0x04004
 637 #define IXGBE_ERRBC     0x04008
 638 #define IXGBE_MSPDC     0x04010
 639 #define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
 640 #define IXGBE_MLFC      0x04034
 641 #define IXGBE_MRFC      0x04038
 642 #define IXGBE_RLEC      0x04040
 643 #define IXGBE_LXONTXC   0x03F60
 644 #define IXGBE_LXONRXC   0x0CF60
 645 #define IXGBE_LXOFFTXC  0x03F68
 646 #define IXGBE_LXOFFRXC  0x0CF68
 647 #define IXGBE_LXONRXCNT         0x041A4
 648 #define IXGBE_LXOFFRXCNT        0x041A8
 649 #define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
 650 #define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
 651 #define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
 652 #define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/


 711 #define IXGBE_FCOEDWRC          0x0242C /* Number of FCoE DWords Received */
 712 #define IXGBE_FCOEPTC           0x08784 /* Number of FCoE Packets Transmitted */
 713 #define IXGBE_FCOEDWTC          0x08788 /* Number of FCoE DWords Transmitted */
 714 #define IXGBE_FCCRC_CNT_MASK    0x0000FFFF /* CRC_CNT: bit 0 - 15 */
 715 #define IXGBE_FCLAST_CNT_MASK   0x0000FFFF /* Last_CNT: bit 0 - 15 */
 716 #define IXGBE_O2BGPTC           0x041C4
 717 #define IXGBE_O2BSPC            0x087B0
 718 #define IXGBE_B2OSPC            0x041C0
 719 #define IXGBE_B2OGPRC           0x02F90
 720 #define IXGBE_BUPRC             0x04180
 721 #define IXGBE_BMPRC             0x04184
 722 #define IXGBE_BBPRC             0x04188
 723 #define IXGBE_BUPTC             0x0418C
 724 #define IXGBE_BMPTC             0x04190
 725 #define IXGBE_BBPTC             0x04194
 726 #define IXGBE_BCRCERRS          0x04198
 727 #define IXGBE_BXONRXC           0x0419C
 728 #define IXGBE_BXOFFRXC          0x041E0
 729 #define IXGBE_BXONTXC           0x041E4
 730 #define IXGBE_BXOFFTXC          0x041E8
 731 #define IXGBE_PCRC8ECL          0x0E810
 732 #define IXGBE_PCRC8ECH          0x0E811
 733 #define IXGBE_PCRC8ECH_MASK     0x1F
 734 #define IXGBE_LDPCECL           0x0E820
 735 #define IXGBE_LDPCECH           0x0E821
 736 
 737 /* Management */
 738 #define IXGBE_MAVTV(_i)         (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
 739 #define IXGBE_MFUTP(_i)         (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
 740 #define IXGBE_MANC              0x05820
 741 #define IXGBE_MFVAL             0x05824
 742 #define IXGBE_MANC2H            0x05860
 743 #define IXGBE_MDEF(_i)          (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
 744 #define IXGBE_MIPAF             0x058B0
 745 #define IXGBE_MMAL(_i)          (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
 746 #define IXGBE_MMAH(_i)          (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
 747 #define IXGBE_FTFT              0x09400 /* 0x9400-0x97FC */
 748 #define IXGBE_METF(_i)          (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
 749 #define IXGBE_MDEF_EXT(_i)      (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
 750 #define IXGBE_LSWFW             0x15014
 751 #define IXGBE_BMCIP(_i)         (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
 752 #define IXGBE_BMCIPVAL          0x05060
 753 #define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
 754 #define IXGBE_BMCIP_IPADDR_VALID        0x00000002
 755 
 756 /* Management Bit Fields and Masks */


 757 #define IXGBE_MANC_EN_BMC2OS    0x10000000 /* Ena BMC2OS and OS2BMC traffic */
 758 #define IXGBE_MANC_EN_BMC2OS_SHIFT      28
 759 
 760 /* Firmware Semaphore Register */
 761 #define IXGBE_FWSM_MODE_MASK    0xE


 762 
 763 /* ARC Subsystem registers */
 764 #define IXGBE_HICR              0x15F00
 765 #define IXGBE_FWSTS             0x15F0C
 766 #define IXGBE_HSMC0R            0x15F04
 767 #define IXGBE_HSMC1R            0x15F08
 768 #define IXGBE_SWSR              0x15F10
 769 #define IXGBE_HFDR              0x15FE8
 770 #define IXGBE_FLEX_MNG          0x15800 /* 0x15800 - 0x15EFC */
 771 
 772 #define IXGBE_HICR_EN           0x01  /* Enable bit - RO */
 773 /* Driver sets this bit when done to put command in RAM */
 774 #define IXGBE_HICR_C            0x02
 775 #define IXGBE_HICR_SV           0x04  /* Status Validity */
 776 #define IXGBE_HICR_FW_RESET_ENABLE      0x40
 777 #define IXGBE_HICR_FW_RESET     0x80
 778 
 779 /* PCI-E registers */
 780 #define IXGBE_GCR               0x11000
 781 #define IXGBE_GTV               0x11004
 782 #define IXGBE_FUNCTAG           0x11008
 783 #define IXGBE_GLT               0x1100C
 784 #define IXGBE_PCIEPIPEADR       0x11004
 785 #define IXGBE_PCIEPIPEDAT       0x11008
 786 #define IXGBE_GSCL_1            0x11010
 787 #define IXGBE_GSCL_2            0x11014
 788 #define IXGBE_GSCL_3            0x11018
 789 #define IXGBE_GSCL_4            0x1101C
 790 #define IXGBE_GSCN_0            0x11020
 791 #define IXGBE_GSCN_1            0x11024
 792 #define IXGBE_GSCN_2            0x11028
 793 #define IXGBE_GSCN_3            0x1102C
 794 #define IXGBE_FACTPS            0x10150





 795 #define IXGBE_PCIEANACTL        0x11040
 796 #define IXGBE_SWSM              0x10140





 797 #define IXGBE_FWSM              0x10148











 798 #define IXGBE_GSSR              0x10160
 799 #define IXGBE_MREVID            0x11064
 800 #define IXGBE_DCA_ID            0x11070
 801 #define IXGBE_DCA_CTRL          0x11074
 802 #define IXGBE_SWFW_SYNC         IXGBE_GSSR
 803 
 804 /* PCI-E registers 82599-Specific */
 805 #define IXGBE_GCR_EXT           0x11050
 806 #define IXGBE_GSCL_5_82599      0x11030
 807 #define IXGBE_GSCL_6_82599      0x11034
 808 #define IXGBE_GSCL_7_82599      0x11038
 809 #define IXGBE_GSCL_8_82599      0x1103C
 810 #define IXGBE_PHYADR_82599      0x11040
 811 #define IXGBE_PHYDAT_82599      0x11044
 812 #define IXGBE_PHYCTL_82599      0x11048
 813 #define IXGBE_PBACLR_82599      0x11068
 814 #define IXGBE_CIAA_82599        0x11088
 815 #define IXGBE_CIAD_82599        0x1108C










 816 #define IXGBE_PICAUSE           0x110B0
 817 #define IXGBE_PIENA             0x110B8
 818 #define IXGBE_CDQ_MBR_82599     0x110B4
 819 #define IXGBE_PCIESPARE         0x110BC
 820 #define IXGBE_MISC_REG_82599    0x110F0
 821 #define IXGBE_ECC_CTRL_0_82599  0x11100
 822 #define IXGBE_ECC_CTRL_1_82599  0x11104
 823 #define IXGBE_ECC_STATUS_82599  0x110E0
 824 #define IXGBE_BAR_CTRL_82599    0x110F4
 825 
 826 /* PCI Express Control */
 827 #define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
 828 #define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
 829 #define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
 830 #define IXGBE_GCR_CAP_VER2              0x00040000
 831 
 832 #define IXGBE_GCR_EXT_MSIX_EN           0x80000000
 833 #define IXGBE_GCR_EXT_BUFFERS_CLEAR     0x40000000
 834 #define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
 835 #define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
 836 #define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
 837 #define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
 838                                          IXGBE_GCR_EXT_VT_MODE_64)
 839 #define IXGBE_GCR_EXT_VT_MODE_MASK      0x00000003
 840 /* Time Sync Registers */
 841 #define IXGBE_TSYNCRXCTL        0x05188 /* Rx Time Sync Control register - RW */
 842 #define IXGBE_TSYNCTXCTL        0x08C00 /* Tx Time Sync Control register - RW */
 843 #define IXGBE_RXSTMPL   0x051E8 /* Rx timestamp Low - RO */
 844 #define IXGBE_RXSTMPH   0x051A4 /* Rx timestamp High - RO */
 845 #define IXGBE_RXSATRL   0x051A0 /* Rx timestamp attribute low - RO */
 846 #define IXGBE_RXSATRH   0x051A8 /* Rx timestamp attribute high - RO */
 847 #define IXGBE_RXMTRL    0x05120 /* RX message type register low - RW */
 848 #define IXGBE_TXSTMPL   0x08C04 /* Tx timestamp value Low - RO */
 849 #define IXGBE_TXSTMPH   0x08C08 /* Tx timestamp value High - RO */
 850 #define IXGBE_SYSTIML   0x08C0C /* System time register Low - RO */
 851 #define IXGBE_SYSTIMH   0x08C10 /* System time register High - RO */

 852 #define IXGBE_TIMINCA   0x08C14 /* Increment attributes register - RW */
 853 #define IXGBE_TIMADJL   0x08C18 /* Time Adjustment Offset register Low - RW */
 854 #define IXGBE_TIMADJH   0x08C1C /* Time Adjustment Offset register High - RW */
 855 #define IXGBE_TSAUXC    0x08C20 /* TimeSync Auxiliary Control register - RW */
 856 #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
 857 #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
 858 #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
 859 #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
 860 #define IXGBE_CLKTIML   0x08C34 /* Clock Out Time Register Low - RW */
 861 #define IXGBE_CLKTIMH   0x08C38 /* Clock Out Time Register High - RW */
 862 #define IXGBE_FREQOUT0  0x08C34 /* Frequency Out 0 Control register - RW */
 863 #define IXGBE_FREQOUT1  0x08C38 /* Frequency Out 1 Control register - RW */
 864 #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
 865 #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
 866 #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
 867 #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */



 868 
 869 /* Diagnostic Registers */
 870 #define IXGBE_RDSTATCTL         0x02C20
 871 #define IXGBE_RDSTAT(_i)        (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
 872 #define IXGBE_RDHMPN            0x02F08
 873 #define IXGBE_RIC_DW(_i)        (0x02F10 + ((_i) * 4))
 874 #define IXGBE_RDPROBE           0x02F20
 875 #define IXGBE_RDMAM             0x02F30
 876 #define IXGBE_RDMAD             0x02F34
 877 #define IXGBE_TDSTATCTL         0x07C20
 878 #define IXGBE_TDSTAT(_i)        (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
 879 #define IXGBE_TDHMPN            0x07F08
 880 #define IXGBE_TDHMPN2           0x082FC
 881 #define IXGBE_TXDESCIC          0x082CC
 882 #define IXGBE_TIC_DW(_i)        (0x07F10 + ((_i) * 4))
 883 #define IXGBE_TIC_DW2(_i)       (0x082B0 + ((_i) * 4))
 884 #define IXGBE_TDPROBE           0x07F20
 885 #define IXGBE_TXBUFCTRL         0x0C600
 886 #define IXGBE_TXBUFDATA0        0x0C610
 887 #define IXGBE_TXBUFDATA1        0x0C614
 888 #define IXGBE_TXBUFDATA2        0x0C618
 889 #define IXGBE_TXBUFDATA3        0x0C61C
 890 #define IXGBE_RXBUFCTRL         0x03600
 891 #define IXGBE_RXBUFDATA0        0x03610
 892 #define IXGBE_RXBUFDATA1        0x03614
 893 #define IXGBE_RXBUFDATA2        0x03618
 894 #define IXGBE_RXBUFDATA3        0x0361C
 895 #define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
 896 #define IXGBE_RFVAL             0x050A4
 897 #define IXGBE_MDFTC1            0x042B8
 898 #define IXGBE_MDFTC2            0x042C0


 997 
 998 #define IXGBE_RXDSTATCTRL       0x02F40
 999 
1000 /* Copper Pond 2 link timeout */
1001 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1002 
1003 /* Omer CORECTL */
1004 #define IXGBE_CORECTL                   0x014F00
1005 /* BARCTRL */
1006 #define IXGBE_BARCTRL                   0x110F4
1007 #define IXGBE_BARCTRL_FLSIZE            0x0700
1008 #define IXGBE_BARCTRL_FLSIZE_SHIFT      8
1009 #define IXGBE_BARCTRL_CSRSIZE           0x2000
1010 
1011 /* RSCCTL Bit Masks */
1012 #define IXGBE_RSCCTL_RSCEN      0x01
1013 #define IXGBE_RSCCTL_MAXDESC_1  0x00
1014 #define IXGBE_RSCCTL_MAXDESC_4  0x04
1015 #define IXGBE_RSCCTL_MAXDESC_8  0x08
1016 #define IXGBE_RSCCTL_MAXDESC_16 0x0C

1017 
1018 /* RSCDBU Bit Masks */
1019 #define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
1020 #define IXGBE_RSCDBU_RSCACKDIS          0x00000080
1021 
1022 /* RDRXCTL Bit Masks */
1023 #define IXGBE_RDRXCTL_RDMTS_1_2         0x00000000 /* Rx Desc Min THLD Size */
1024 #define IXGBE_RDRXCTL_CRCSTRIP          0x00000002 /* CRC Strip */

1025 #define IXGBE_RDRXCTL_MVMEN             0x00000020

1026 #define IXGBE_RDRXCTL_DMAIDONE          0x00000008 /* DMA init cycle done */

1027 #define IXGBE_RDRXCTL_AGGDIS            0x00010000 /* Aggregation disable */
1028 #define IXGBE_RDRXCTL_RSCFRSTSIZE       0x003E0000 /* RSC First packet size */
1029 #define IXGBE_RDRXCTL_RSCLLIDIS         0x00800000 /* Disabl RSC compl on LLI */
1030 #define IXGBE_RDRXCTL_RSCACKC           0x02000000 /* must set 1 when RSC ena */
1031 #define IXGBE_RDRXCTL_FCOE_WRFIX        0x04000000 /* must set 1 when RSC ena */


1032 
1033 /* RQTC Bit Masks and Shifts */
1034 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1035 #define IXGBE_RQTC_TC0_MASK     (0x7 << 0)
1036 #define IXGBE_RQTC_TC1_MASK     (0x7 << 4)
1037 #define IXGBE_RQTC_TC2_MASK     (0x7 << 8)
1038 #define IXGBE_RQTC_TC3_MASK     (0x7 << 12)
1039 #define IXGBE_RQTC_TC4_MASK     (0x7 << 16)
1040 #define IXGBE_RQTC_TC5_MASK     (0x7 << 20)
1041 #define IXGBE_RQTC_TC6_MASK     (0x7 << 24)
1042 #define IXGBE_RQTC_TC7_MASK     (0x7 << 28)
1043 
1044 /* PSRTYPE.RQPL Bit masks and shift */
1045 #define IXGBE_PSRTYPE_RQPL_MASK         0x7
1046 #define IXGBE_PSRTYPE_RQPL_SHIFT        29
1047 
1048 /* CTRL Bit Masks */
1049 #define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */
1050 #define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
1051 #define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
1052 #define IXGBE_CTRL_RST_MASK     (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1053 
1054 /* FACTPS */

1055 #define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
1056 
1057 /* MHADD Bit Masks */
1058 #define IXGBE_MHADD_MFS_MASK    0xFFFF0000
1059 #define IXGBE_MHADD_MFS_SHIFT   16
1060 
1061 /* Extended Device Control */
1062 #define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
1063 #define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
1064 #define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
1065 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1066 
1067 /* Direct Cache Access (DCA) definitions */
1068 #define IXGBE_DCA_CTRL_DCA_ENABLE       0x00000000 /* DCA Enable */
1069 #define IXGBE_DCA_CTRL_DCA_DISABLE      0x00000001 /* DCA Disable */
1070 
1071 #define IXGBE_DCA_CTRL_DCA_MODE_CB1     0x00 /* DCA Mode CB1 */
1072 #define IXGBE_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */
1073 
1074 #define IXGBE_DCA_RXCTRL_CPUID_MASK     0x0000001F /* Rx CPUID Mask */


1134 
1135 /* Device Type definitions for new protocol MDIO commands */
1136 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE             0x1
1137 #define IXGBE_MDIO_PCS_DEV_TYPE                 0x3
1138 #define IXGBE_MDIO_PHY_XS_DEV_TYPE              0x4
1139 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE            0x7
1140 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE   0x1E   /* Device 30 */
1141 #define IXGBE_TWINAX_DEV                        1
1142 
1143 #define IXGBE_MDIO_COMMAND_TIMEOUT      100 /* PHY Timeout for 1 GB mode */
1144 
1145 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL            0x0 /* VS1 Ctrl Reg */
1146 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS             0x1 /* VS1 Status Reg */
1147 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS        0x0008 /* 1 = Link Up */
1148 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS       0x0010 /* 0-10G, 1-1G */
1149 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED          0x0018
1150 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED           0x0010
1151 
1152 #define IXGBE_MDIO_AUTO_NEG_CONTROL     0x0 /* AUTO_NEG Control Reg */
1153 #define IXGBE_MDIO_AUTO_NEG_STATUS      0x1 /* AUTO_NEG Status Reg */




1154 #define IXGBE_MDIO_AUTO_NEG_ADVT        0x10 /* AUTO_NEG Advt Reg */
1155 #define IXGBE_MDIO_AUTO_NEG_LP          0x13 /* AUTO_NEG LP Status Reg */




1156 #define IXGBE_MDIO_PHY_XS_CONTROL       0x0 /* PHY_XS Control Reg */
1157 #define IXGBE_MDIO_PHY_XS_RESET         0x8000 /* PHY_XS Reset */
1158 #define IXGBE_MDIO_PHY_ID_HIGH          0x2 /* PHY ID High Reg*/
1159 #define IXGBE_MDIO_PHY_ID_LOW           0x3 /* PHY ID Low Reg*/
1160 #define IXGBE_MDIO_PHY_SPEED_ABILITY    0x4 /* Speed Ability Reg */
1161 #define IXGBE_MDIO_PHY_SPEED_10G        0x0001 /* 10G capable */
1162 #define IXGBE_MDIO_PHY_SPEED_1G         0x0010 /* 1G capable */
1163 #define IXGBE_MDIO_PHY_SPEED_100M       0x0020 /* 100M capable */
1164 #define IXGBE_MDIO_PHY_EXT_ABILITY      0xB /* Ext Ability Reg */
1165 #define IXGBE_MDIO_PHY_10GBASET_ABILITY         0x0004 /* 10GBaseT capable */
1166 #define IXGBE_MDIO_PHY_1000BASET_ABILITY        0x0020 /* 1000BaseT capable */
1167 #define IXGBE_MDIO_PHY_100BASETX_ABILITY        0x0080 /* 100BaseTX capable */
1168 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE       0x0800 /* Set low power mode */




1169 
















1170 #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
1171 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1172 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1173 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */




1174 






1175 /* MII clause 22/28 definitions */
1176 #define IXGBE_MDIO_PHY_LOW_POWER_MODE   0x0800
1177 


















1178 #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG    0x20   /* 10G Control Reg */
1179 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1180 #define IXGBE_MII_AUTONEG_XNP_TX_REG            0x17   /* 1G XNP Transmit */
1181 #define IXGBE_MII_AUTONEG_ADVERTISE_REG         0x10   /* 100M Advertisement */
1182 #define IXGBE_MII_10GBASE_T_ADVERTISE           0x1000 /* full duplex, bit:12*/
1183 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX     0x4000 /* full duplex, bit:14*/
1184 #define IXGBE_MII_1GBASE_T_ADVERTISE            0x8000 /* full duplex, bit:15*/


1185 #define IXGBE_MII_100BASE_T_ADVERTISE           0x0100 /* full duplex, bit:8 */
1186 #define IXGBE_MII_100BASE_T_ADVERTISE_HALF      0x0080 /* half duplex, bit:7 */
1187 #define IXGBE_MII_RESTART                       0x200
1188 #define IXGBE_MII_AUTONEG_COMPLETE              0x20
1189 #define IXGBE_MII_AUTONEG_LINK_UP               0x04
1190 #define IXGBE_MII_AUTONEG_REG                   0x0
1191 
1192 #define IXGBE_PHY_REVISION_MASK         0xFFFFFFF0
1193 #define IXGBE_MAX_PHY_ADDR              32
1194 
1195 /* PHY IDs*/
1196 #define TN1010_PHY_ID   0x00A19410
1197 #define TNX_FW_REV      0xB
1198 #define X540_PHY_ID     0x01540200




1199 #define AQ_FW_REV       0x20
1200 #define QT2022_PHY_ID   0x0043A400
1201 #define ATH_PHY_ID      0x03429050
1202 
1203 /* PHY Types */
1204 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1205 
1206 /* Special PHY Init Routine */
1207 #define IXGBE_PHY_INIT_OFFSET_NL        0x002B
1208 #define IXGBE_PHY_INIT_END_NL           0xFFFF
1209 #define IXGBE_CONTROL_MASK_NL           0xF000
1210 #define IXGBE_DATA_MASK_NL              0x0FFF
1211 #define IXGBE_CONTROL_SHIFT_NL          12
1212 #define IXGBE_DELAY_NL                  0
1213 #define IXGBE_DATA_NL                   1
1214 #define IXGBE_CONTROL_NL                0x000F
1215 #define IXGBE_CONTROL_EOL_NL            0x0FFF
1216 #define IXGBE_CONTROL_SOL_NL            0x0000
1217 
1218 /* General purpose Interrupt Enable */
1219 #define IXGBE_SDP0_GPIEN        0x00000001 /* SDP0 */
1220 #define IXGBE_SDP1_GPIEN        0x00000002 /* SDP1 */
1221 #define IXGBE_SDP2_GPIEN        0x00000004 /* SDP2 */













1222 #define IXGBE_GPIE_MSIX_MODE    0x00000010 /* MSI-X mode */
1223 #define IXGBE_GPIE_OCD          0x00000020 /* Other Clear Disable */
1224 #define IXGBE_GPIE_EIMEN        0x00000040 /* Immediate Interrupt Enable */
1225 #define IXGBE_GPIE_EIAME        0x40000000
1226 #define IXGBE_GPIE_PBA_SUPPORT  0x80000000
1227 #define IXGBE_GPIE_RSC_DELAY_SHIFT      11
1228 #define IXGBE_GPIE_VTMODE_MASK  0x0000C000 /* VT Mode Mask */
1229 #define IXGBE_GPIE_VTMODE_16    0x00004000 /* 16 VFs 8 queues per VF */
1230 #define IXGBE_GPIE_VTMODE_32    0x00008000 /* 32 VFs 4 queues per VF */
1231 #define IXGBE_GPIE_VTMODE_64    0x0000C000 /* 64 VFs 2 queues per VF */
1232 
1233 /* Packet Buffer Initialization */
1234 #define IXGBE_MAX_PACKET_BUFFERS        8
1235 
1236 #define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
1237 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
1238 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
1239 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
1240 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
1241 #define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */


1379 #define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
1380 #define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
1381 
1382 /* Interrupt register bitmasks */
1383 
1384 /* Extended Interrupt Cause Read */
1385 #define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
1386 #define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
1387 #define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
1388 #define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
1389 #define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
1390 #define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
1391 #define IXGBE_EICR_LINKSEC      0x00200000 /* PN Threshold */
1392 #define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
1393 #define IXGBE_EICR_TS           0x00800000 /* Thermal Sensor Event */
1394 #define IXGBE_EICR_TIMESYNC     0x01000000 /* Timesync Event */
1395 #define IXGBE_EICR_GPI_SDP0     0x01000000 /* Gen Purpose Interrupt on SDP0 */
1396 #define IXGBE_EICR_GPI_SDP1     0x02000000 /* Gen Purpose Interrupt on SDP1 */
1397 #define IXGBE_EICR_GPI_SDP2     0x04000000 /* Gen Purpose Interrupt on SDP2 */
1398 #define IXGBE_EICR_ECC          0x10000000 /* ECC Error */













1399 #define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
1400 #define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
1401 #define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
1402 #define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
1403 
1404 /* Extended Interrupt Cause Set */
1405 #define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1406 #define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1407 #define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
1408 #define IXGBE_EICS_PCI          IXGBE_EICR_PCI /* PCI Exception */
1409 #define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1410 #define IXGBE_EICS_LSC          IXGBE_EICR_LSC /* Link Status Change */
1411 #define IXGBE_EICS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1412 #define IXGBE_EICS_TIMESYNC     IXGBE_EICR_TIMESYNC /* Timesync Event */
1413 #define IXGBE_EICS_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1414 #define IXGBE_EICS_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1415 #define IXGBE_EICS_GPI_SDP2     IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1416 #define IXGBE_EICS_ECC          IXGBE_EICR_ECC /* ECC Error */



1417 #define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1418 #define IXGBE_EICS_DHER         IXGBE_EICR_DHER /* Desc Handler Error */
1419 #define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1420 #define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1421 
1422 /* Extended Interrupt Mask Set */
1423 #define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1424 #define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR /* FDir Exception */
1425 #define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1426 #define IXGBE_EIMS_PCI          IXGBE_EICR_PCI /* PCI Exception */
1427 #define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1428 #define IXGBE_EIMS_LSC          IXGBE_EICR_LSC /* Link Status Change */
1429 #define IXGBE_EIMS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1430 #define IXGBE_EIMS_TS           IXGBE_EICR_TS /* Thermal Sensor Event */
1431 #define IXGBE_EIMS_TIMESYNC     IXGBE_EICR_TIMESYNC /* Timesync Event */
1432 #define IXGBE_EIMS_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1433 #define IXGBE_EIMS_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1434 #define IXGBE_EIMS_GPI_SDP2     IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1435 #define IXGBE_EIMS_ECC          IXGBE_EICR_ECC /* ECC Error */



1436 #define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1437 #define IXGBE_EIMS_DHER         IXGBE_EICR_DHER /* Descr Handler Error */
1438 #define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1439 #define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1440 
1441 /* Extended Interrupt Mask Clear */
1442 #define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1443 #define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR /* FDir Exception */
1444 #define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1445 #define IXGBE_EIMC_PCI          IXGBE_EICR_PCI /* PCI Exception */
1446 #define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1447 #define IXGBE_EIMC_LSC          IXGBE_EICR_LSC /* Link Status Change */
1448 #define IXGBE_EIMC_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1449 #define IXGBE_EIMC_TIMESYNC     IXGBE_EICR_TIMESYNC /* Timesync Event */
1450 #define IXGBE_EIMC_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1451 #define IXGBE_EIMC_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1452 #define IXGBE_EIMC_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
1453 #define IXGBE_EIMC_ECC          IXGBE_EICR_ECC /* ECC Error */



1454 #define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1455 #define IXGBE_EIMC_DHER         IXGBE_EICR_DHER /* Desc Handler Err */
1456 #define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1457 #define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1458 
1459 #define IXGBE_EIMS_ENABLE_MASK ( \
1460                                 IXGBE_EIMS_RTX_QUEUE    | \
1461                                 IXGBE_EIMS_LSC          | \
1462                                 IXGBE_EIMS_TCP_TIMER    | \
1463                                 IXGBE_EIMS_OTHER)
1464 
1465 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1466 #define IXGBE_IMIR_PORT_IM_EN   0x00010000  /* TCP port enable */
1467 #define IXGBE_IMIR_PORT_BP      0x00020000  /* TCP port check bypass */
1468 #define IXGBE_IMIREXT_SIZE_BP   0x00001000  /* Packet size bypass */
1469 #define IXGBE_IMIREXT_CTRL_URG  0x00002000  /* Check URG bit in header */
1470 #define IXGBE_IMIREXT_CTRL_ACK  0x00004000  /* Check ACK bit in header */
1471 #define IXGBE_IMIREXT_CTRL_PSH  0x00008000  /* Check PSH bit in header */
1472 #define IXGBE_IMIREXT_CTRL_RST  0x00010000  /* Check RST bit in header */
1473 #define IXGBE_IMIREXT_CTRL_SYN  0x00020000  /* Check SYN bit in header */


1512 /* Interrupt Vector Allocation Registers */
1513 #define IXGBE_IVAR_REG_NUM              25
1514 #define IXGBE_IVAR_REG_NUM_82599        64
1515 #define IXGBE_IVAR_TXRX_ENTRY           96
1516 #define IXGBE_IVAR_RX_ENTRY             64
1517 #define IXGBE_IVAR_RX_QUEUE(_i)         (0 + (_i))
1518 #define IXGBE_IVAR_TX_QUEUE(_i)         (64 + (_i))
1519 #define IXGBE_IVAR_TX_ENTRY             32
1520 
1521 #define IXGBE_IVAR_TCP_TIMER_INDEX      96 /* 0 based index */
1522 #define IXGBE_IVAR_OTHER_CAUSES_INDEX   97 /* 0 based index */
1523 
1524 #define IXGBE_MSIX_VECTOR(_i)           (0 + (_i))
1525 
1526 #define IXGBE_IVAR_ALLOC_VAL            0x80 /* Interrupt Allocation valid */
1527 
1528 /* ETYPE Queue Filter/Select Bit Masks */
1529 #define IXGBE_MAX_ETQF_FILTERS          8
1530 #define IXGBE_ETQF_FCOE                 0x08000000 /* bit 27 */
1531 #define IXGBE_ETQF_BCN                  0x10000000 /* bit 28 */

1532 #define IXGBE_ETQF_1588                 0x40000000 /* bit 30 */
1533 #define IXGBE_ETQF_FILTER_EN            0x80000000 /* bit 31 */
1534 #define IXGBE_ETQF_POOL_ENABLE          (1 << 26) /* bit 26 */
1535 #define IXGBE_ETQF_POOL_SHIFT           20
1536 
1537 #define IXGBE_ETQS_RX_QUEUE             0x007F0000 /* bits 22:16 */
1538 #define IXGBE_ETQS_RX_QUEUE_SHIFT       16
1539 #define IXGBE_ETQS_LLI                  0x20000000 /* bit 29 */
1540 #define IXGBE_ETQS_QUEUE_EN             0x80000000 /* bit 31 */
1541 
1542 /*
1543  * ETQF filter list: one static filter per filter consumer. This is
1544  *                 to avoid filter collisions later. Add new filters
1545  *                 here!!
1546  *
1547  * Current filters:
1548  *      EAPOL 802.1x (0x888e): Filter 0
1549  *      FCoE (0x8906):   Filter 2
1550  *      1588 (0x88f7):   Filter 3
1551  *      FIP  (0x8914):   Filter 4



1552  */
1553 #define IXGBE_ETQF_FILTER_EAPOL         0
1554 #define IXGBE_ETQF_FILTER_FCOE          2
1555 #define IXGBE_ETQF_FILTER_1588          3
1556 #define IXGBE_ETQF_FILTER_FIP           4



1557 /* VLAN Control Bit Masks */
1558 #define IXGBE_VLNCTRL_VET               0x0000FFFF  /* bits 0-15 */
1559 #define IXGBE_VLNCTRL_CFI               0x10000000  /* bit 28 */
1560 #define IXGBE_VLNCTRL_CFIEN             0x20000000  /* bit 29 */
1561 #define IXGBE_VLNCTRL_VFE               0x40000000  /* bit 30 */
1562 #define IXGBE_VLNCTRL_VME               0x80000000  /* bit 31 */
1563 
1564 /* VLAN pool filtering masks */
1565 #define IXGBE_VLVF_VIEN                 0x80000000  /* filter is valid */
1566 #define IXGBE_VLVF_ENTRIES              64
1567 #define IXGBE_VLVF_VLANID_MASK          0x00000FFF
1568 /* Per VF Port VLAN insertion rules */
1569 #define IXGBE_VMVIR_VLANA_DEFAULT       0x40000000 /* Always use default VLAN */
1570 #define IXGBE_VMVIR_VLANA_NEVER         0x80000000 /* Never insert VLAN tag */
1571 
1572 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE   0x8100  /* 802.1q protocol */
1573 
1574 /* STATUS Bit Masks */
1575 #define IXGBE_STATUS_LAN_ID             0x0000000C /* LAN ID */
1576 #define IXGBE_STATUS_LAN_ID_SHIFT       2 /* LAN ID Shift*/
1577 #define IXGBE_STATUS_GIO                0x00080000 /* GIO Master Ena Status */
1578 
1579 #define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
1580 #define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
1581 
1582 /* ESDP Bit Masks */
1583 #define IXGBE_ESDP_SDP0         0x00000001 /* SDP0 Data Value */
1584 #define IXGBE_ESDP_SDP1         0x00000002 /* SDP1 Data Value */
1585 #define IXGBE_ESDP_SDP2         0x00000004 /* SDP2 Data Value */
1586 #define IXGBE_ESDP_SDP3         0x00000008 /* SDP3 Data Value */
1587 #define IXGBE_ESDP_SDP4         0x00000010 /* SDP4 Data Value */
1588 #define IXGBE_ESDP_SDP5         0x00000020 /* SDP5 Data Value */
1589 #define IXGBE_ESDP_SDP6         0x00000040 /* SDP6 Data Value */
1590 #define IXGBE_ESDP_SDP7         0x00000080 /* SDP7 Data Value */
1591 #define IXGBE_ESDP_SDP0_DIR     0x00000100 /* SDP0 IO direction */
1592 #define IXGBE_ESDP_SDP1_DIR     0x00000200 /* SDP1 IO direction */

1593 #define IXGBE_ESDP_SDP3_DIR     0x00000800 /* SDP3 IO direction */
1594 #define IXGBE_ESDP_SDP4_DIR     0x00001000 /* SDP4 IO direction */
1595 #define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
1596 #define IXGBE_ESDP_SDP6_DIR     0x00004000 /* SDP6 IO direction */
1597 #define IXGBE_ESDP_SDP7_DIR     0x00008000 /* SDP7 IO direction */
1598 #define IXGBE_ESDP_SDP0_NATIVE  0x00010000 /* SDP0 IO mode */
1599 #define IXGBE_ESDP_SDP1_NATIVE  0x00020000 /* SDP1 IO mode */
1600 
1601 
1602 /* LEDCTL Bit Masks */
1603 #define IXGBE_LED_IVRT_BASE             0x00000040
1604 #define IXGBE_LED_BLINK_BASE            0x00000080
1605 #define IXGBE_LED_MODE_MASK_BASE        0x0000000F
1606 #define IXGBE_LED_OFFSET(_base, _i)     (_base << (8 * (_i)))
1607 #define IXGBE_LED_MODE_SHIFT(_i)        (8*(_i))
1608 #define IXGBE_LED_IVRT(_i)      IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1609 #define IXGBE_LED_BLINK(_i)     IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1610 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)



1611 
1612 /* LED modes */
1613 #define IXGBE_LED_LINK_UP       0x0
1614 #define IXGBE_LED_LINK_10G      0x1
1615 #define IXGBE_LED_MAC           0x2
1616 #define IXGBE_LED_FILTER        0x3
1617 #define IXGBE_LED_LINK_ACTIVE   0x4
1618 #define IXGBE_LED_LINK_1G       0x5
1619 #define IXGBE_LED_ON            0xE
1620 #define IXGBE_LED_OFF           0xF
1621 
1622 /* AUTOC Bit Masks */
1623 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1624 #define IXGBE_AUTOC_KX4_SUPP    0x80000000
1625 #define IXGBE_AUTOC_KX_SUPP     0x40000000
1626 #define IXGBE_AUTOC_PAUSE       0x30000000
1627 #define IXGBE_AUTOC_ASM_PAUSE   0x20000000
1628 #define IXGBE_AUTOC_SYM_PAUSE   0x10000000
1629 #define IXGBE_AUTOC_RF          0x08000000
1630 #define IXGBE_AUTOC_PD_TMR      0x06000000


1651 #define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1652 
1653 #define IXGBE_AUTOC_1G_PMA_PMD_MASK     0x00000200
1654 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT    9
1655 #define IXGBE_AUTOC_10G_PMA_PMD_MASK    0x00000180
1656 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT   7
1657 #define IXGBE_AUTOC_10G_XAUI    (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1658 #define IXGBE_AUTOC_10G_KX4     (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1659 #define IXGBE_AUTOC_10G_CX4     (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1660 #define IXGBE_AUTOC_1G_BX       (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1661 #define IXGBE_AUTOC_1G_KX       (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1662 #define IXGBE_AUTOC_1G_SFI      (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1663 #define IXGBE_AUTOC_1G_KX_BX    (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1664 
1665 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1666 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK    0x00030000
1667 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT   16
1668 #define IXGBE_AUTOC2_10G_KR     (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1669 #define IXGBE_AUTOC2_10G_XFI    (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1670 #define IXGBE_AUTOC2_10G_SFI    (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)


1671 
1672 #define IXGBE_MACC_FLU          0x00000001
1673 #define IXGBE_MACC_FSV_10G      0x00030000
1674 #define IXGBE_MACC_FS           0x00040000
1675 #define IXGBE_MAC_RX2TX_LPBK    0x00000002
1676 



1677 /* LINKS Bit Masks */
1678 #define IXGBE_LINKS_KX_AN_COMP  0x80000000
1679 #define IXGBE_LINKS_UP          0x40000000
1680 #define IXGBE_LINKS_SPEED       0x20000000
1681 #define IXGBE_LINKS_MODE        0x18000000
1682 #define IXGBE_LINKS_RX_MODE     0x06000000
1683 #define IXGBE_LINKS_TX_MODE     0x01800000
1684 #define IXGBE_LINKS_XGXS_EN     0x00400000
1685 #define IXGBE_LINKS_SGMII_EN    0x02000000
1686 #define IXGBE_LINKS_PCS_1G_EN   0x00200000
1687 #define IXGBE_LINKS_1G_AN_EN    0x00100000
1688 #define IXGBE_LINKS_KX_AN_IDLE  0x00080000
1689 #define IXGBE_LINKS_1G_SYNC     0x00040000
1690 #define IXGBE_LINKS_10G_ALIGN   0x00020000
1691 #define IXGBE_LINKS_10G_LANE_SYNC       0x00017000
1692 #define IXGBE_LINKS_TL_FAULT            0x00001000
1693 #define IXGBE_LINKS_SIGNAL              0x00000F00
1694 

1695 #define IXGBE_LINKS_SPEED_82599         0x30000000
1696 #define IXGBE_LINKS_SPEED_10G_82599     0x30000000
1697 #define IXGBE_LINKS_SPEED_1G_82599      0x20000000
1698 #define IXGBE_LINKS_SPEED_100_82599     0x10000000
1699 #define IXGBE_LINK_UP_TIME              90 /* 9.0 Seconds */
1700 #define IXGBE_AUTO_NEG_TIME             45 /* 4.5 Seconds */
1701 
1702 #define IXGBE_LINKS2_AN_SUPPORTED       0x00000040
1703 
1704 /* PCS1GLSTA Bit Masks */
1705 #define IXGBE_PCS1GLSTA_LINK_OK         1
1706 #define IXGBE_PCS1GLSTA_SYNK_OK         0x10
1707 #define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
1708 #define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
1709 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
1710 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1711 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
1712 
1713 #define IXGBE_PCS1GANA_SYM_PAUSE        0x80
1714 #define IXGBE_PCS1GANA_ASM_PAUSE        0x100


1722 #define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
1723 
1724 /* ANLP1 Bit Masks */
1725 #define IXGBE_ANLP1_PAUSE               0x0C00
1726 #define IXGBE_ANLP1_SYM_PAUSE           0x0400
1727 #define IXGBE_ANLP1_ASM_PAUSE           0x0800
1728 #define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
1729 
1730 /* SW Semaphore Register bitmasks */
1731 #define IXGBE_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
1732 #define IXGBE_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
1733 #define IXGBE_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
1734 #define IXGBE_SWFW_REGSMP       0x80000000 /* Register Semaphore bit 31 */
1735 
1736 /* SW_FW_SYNC/GSSR definitions */
1737 #define IXGBE_GSSR_EEP_SM       0x0001
1738 #define IXGBE_GSSR_PHY0_SM      0x0002
1739 #define IXGBE_GSSR_PHY1_SM      0x0004
1740 #define IXGBE_GSSR_MAC_CSR_SM   0x0008
1741 #define IXGBE_GSSR_FLASH_SM     0x0010

1742 #define IXGBE_GSSR_SW_MNG_SM    0x0400



1743 
1744 /* FW Status register bitmask */
1745 #define IXGBE_FWSTS_FWRI        0x00000200 /* Firmware Reset Indication */
1746 
1747 /* EEC Register */
1748 #define IXGBE_EEC_SK            0x00000001 /* EEPROM Clock */
1749 #define IXGBE_EEC_CS            0x00000002 /* EEPROM Chip Select */
1750 #define IXGBE_EEC_DI            0x00000004 /* EEPROM Data In */
1751 #define IXGBE_EEC_DO            0x00000008 /* EEPROM Data Out */
1752 #define IXGBE_EEC_FWE_MASK      0x00000030 /* FLASH Write Enable */
1753 #define IXGBE_EEC_FWE_DIS       0x00000010 /* Disable FLASH writes */
1754 #define IXGBE_EEC_FWE_EN        0x00000020 /* Enable FLASH writes */
1755 #define IXGBE_EEC_FWE_SHIFT     4
1756 #define IXGBE_EEC_REQ           0x00000040 /* EEPROM Access Request */
1757 #define IXGBE_EEC_GNT           0x00000080 /* EEPROM Access Grant */
1758 #define IXGBE_EEC_PRES          0x00000100 /* EEPROM Present */
1759 #define IXGBE_EEC_ARD           0x00000200 /* EEPROM Auto Read Done */
1760 #define IXGBE_EEC_FLUP          0x00800000 /* Flash update command */
1761 #define IXGBE_EEC_SEC1VAL       0x02000000 /* Sector 1 Valid */
1762 #define IXGBE_EEC_FLUDONE       0x04000000 /* Flash update done */
1763 /* EEPROM Addressing bits based on type (0-small, 1-large) */
1764 #define IXGBE_EEC_ADDR_SIZE     0x00000400
1765 #define IXGBE_EEC_SIZE          0x00007800 /* EEPROM Size */
1766 #define IXGBE_EERD_MAX_ADDR     0x00003FFF /* EERD alows 14 bits for addr. */
1767 
1768 #define IXGBE_EEC_SIZE_SHIFT            11
1769 #define IXGBE_EEPROM_WORD_SIZE_SHIFT    6
1770 #define IXGBE_EEPROM_OPCODE_BITS        8
1771 



1772 /* Part Number String Length */
1773 #define IXGBE_PBANUM_LENGTH     11
1774 
1775 /* Checksum and EEPROM pointers */
1776 #define IXGBE_PBANUM_PTR_GUARD  0xFAFA
1777 #define IXGBE_EEPROM_CHECKSUM   0x3F
1778 #define IXGBE_EEPROM_SUM        0xBABA
1779 #define IXGBE_PCIE_ANALOG_PTR   0x03
1780 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
1781 #define IXGBE_PHY_PTR           0x04
1782 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
1783 #define IXGBE_OPTION_ROM_PTR    0x05
1784 #define IXGBE_PCIE_GENERAL_PTR  0x06
1785 #define IXGBE_PCIE_CONFIG0_PTR  0x07
1786 #define IXGBE_PCIE_CONFIG1_PTR  0x08
1787 #define IXGBE_CORE0_PTR         0x09
1788 #define IXGBE_CORE1_PTR         0x0A
1789 #define IXGBE_MAC0_PTR          0x0B
1790 #define IXGBE_MAC1_PTR          0x0C
1791 #define IXGBE_CSR0_CONFIG_PTR   0x0D
1792 #define IXGBE_CSR1_CONFIG_PTR   0x0E





1793 #define IXGBE_FW_PTR            0x0F
1794 #define IXGBE_PBANUM0_PTR       0x15
1795 #define IXGBE_PBANUM1_PTR       0x16
1796 #define IXGBE_ALT_MAC_ADDR_PTR  0x37
1797 #define IXGBE_FREE_SPACE_PTR    0X3E
1798 
1799 #define IXGBE_SAN_MAC_ADDR_PTR          0x28
1800 #define IXGBE_DEVICE_CAPS               0x2C
1801 #define IXGBE_SERIAL_NUMBER_MAC_ADDR    0x11
1802 #define IXGBE_PCIE_MSIX_82599_CAPS      0x72
1803 #define IXGBE_MAX_MSIX_VECTORS_82599    0x40
1804 #define IXGBE_PCIE_MSIX_82598_CAPS      0x62
1805 #define IXGBE_MAX_MSIX_VECTORS_82598    0x13
1806 
1807 /* MSI-X capability fields masks */
1808 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
1809 
1810 /* Legacy EEPROM word offsets */
1811 #define IXGBE_ISCSI_BOOT_CAPS           0x0033
1812 #define IXGBE_ISCSI_SETUP_PORT_0        0x0030


1818 #define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
1819 #define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
1820 #define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
1821 #define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
1822 /* EEPROM reset Write Enable latch */
1823 #define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
1824 #define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
1825 #define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
1826 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
1827 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI        0xD8  /* EEPROM ERASE 64KB */
1828 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI        0xDB  /* EEPROM ERASE 256B */
1829 
1830 /* EEPROM Read Register */
1831 #define IXGBE_EEPROM_RW_REG_DATA        16 /* data offset in EEPROM read reg */
1832 #define IXGBE_EEPROM_RW_REG_DONE        2 /* Offset to READ done bit */
1833 #define IXGBE_EEPROM_RW_REG_START       1 /* First bit to start operation */
1834 #define IXGBE_EEPROM_RW_ADDR_SHIFT      2 /* Shift to the address bits */
1835 #define IXGBE_NVM_POLL_WRITE            1 /* Flag for polling for wr complete */
1836 #define IXGBE_NVM_POLL_READ             0 /* Flag for polling for rd complete */
1837 





1838 #define IXGBE_ETH_LENGTH_OF_ADDRESS     6
1839 
1840 #define IXGBE_EEPROM_PAGE_SIZE_MAX      128
1841 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT        512 /* words rd in burst */
1842 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT        256 /* words wr in burst */


1843 
1844 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1845 #define IXGBE_EEPROM_GRANT_ATTEMPTS     1000 /* EEPROM attempts to gain grant */
1846 #endif
1847 
1848 /* Number of 5 microseconds we wait for EERD read and
1849  * EERW write to complete */
1850 #define IXGBE_EERD_EEWR_ATTEMPTS        100000
1851 
1852 /* # attempts we wait for flush update to complete */
1853 #define IXGBE_FLUDONE_ATTEMPTS          20000
1854 
1855 #define IXGBE_PCIE_CTRL2                0x5   /* PCIe Control 2 Offset */
1856 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE   0x8   /* Dummy Function Enable */
1857 #define IXGBE_PCIE_CTRL2_LAN_DISABLE    0x2   /* LAN PCI Disable */
1858 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1   /* LAN Disable Select */
1859 
1860 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET         0x0
1861 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET         0x3
1862 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP         0x1
1863 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS         0x2
1864 #define IXGBE_FW_LESM_PARAMETERS_PTR            0x2
1865 #define IXGBE_FW_LESM_STATE_1                   0x1
1866 #define IXGBE_FW_LESM_STATE_ENABLED             0x8000 /* LESM Enable bit */
1867 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
1868 #define IXGBE_FW_PATCH_VERSION_4                0x7
1869 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR             0x33 /* iSCSI/FCOE block */
1870 #define IXGBE_FCOE_IBA_CAPS_FCOE                0x20 /* FCOE flags */
1871 #define IXGBE_ISCSI_FCOE_BLK_PTR                0x17 /* iSCSI/FCOE block */
1872 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET           0x0 /* FCOE flags */
1873 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE           0x1 /* FCOE flags enable bit */
1874 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR          0x27 /* Alt. SAN MAC block */
1875 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET      0x0 /* Alt SAN MAC capability */
1876 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET     0x1 /* Alt SAN MAC 0 offset */
1877 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET     0x4 /* Alt SAN MAC 1 offset */
1878 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET      0x7 /* Alt WWNN prefix offset */
1879 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET      0x8 /* Alt WWPN prefix offset */
1880 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC      0x0 /* Alt SAN MAC exists */
1881 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN      0x1 /* Alt WWN base exists */
1882 












1883 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1   0x4 /* WoL supported on ports 0 & 1 */
1884 #define IXGBE_DEVICE_CAPS_WOL_PORT0     0x8 /* WoL supported on port 0 */
1885 #define IXGBE_DEVICE_CAPS_WOL_MASK      0xC /* Mask for WoL capabilities */
1886 
1887 /* PCI Bus Info */
1888 #define IXGBE_PCI_DEVICE_STATUS         0xAA
1889 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING     0x0020
1890 #define IXGBE_PCI_LINK_STATUS           0xB2
1891 #define IXGBE_PCI_DEVICE_CONTROL2       0xC8
1892 #define IXGBE_PCI_LINK_WIDTH            0x3F0
1893 #define IXGBE_PCI_LINK_WIDTH_1          0x10
1894 #define IXGBE_PCI_LINK_WIDTH_2          0x20
1895 #define IXGBE_PCI_LINK_WIDTH_4          0x40
1896 #define IXGBE_PCI_LINK_WIDTH_8          0x80
1897 #define IXGBE_PCI_LINK_SPEED            0xF
1898 #define IXGBE_PCI_LINK_SPEED_2500       0x1
1899 #define IXGBE_PCI_LINK_SPEED_5000       0x2
1900 #define IXGBE_PCI_LINK_SPEED_8000       0x3
1901 #define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
1902 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1903 #define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
1904 











1905 /* Number of 100 microseconds we wait for PCI Express master disable */
1906 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT        800
1907 
1908 /* Check whether address is multicast. This is little-endian specific check.*/
1909 #define IXGBE_IS_MULTICAST(Address) \
1910                 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
1911 
1912 /* Check whether an address is broadcast. */
1913 #define IXGBE_IS_BROADCAST(Address) \
1914                 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1915                 (((u8 *)(Address))[1] == ((u8)0xff)))
1916 
1917 /* RAH */
1918 #define IXGBE_RAH_VIND_MASK     0x003C0000
1919 #define IXGBE_RAH_VIND_SHIFT    18
1920 #define IXGBE_RAH_AV            0x80000000
1921 #define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
1922 
1923 /* Header split receive */
1924 #define IXGBE_RFCTL_ISCSI_DIS           0x00000001
1925 #define IXGBE_RFCTL_ISCSI_DWC_MASK      0x0000003E
1926 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT     1
1927 #define IXGBE_RFCTL_RSC_DIS             0x00000010
1928 #define IXGBE_RFCTL_NFSW_DIS            0x00000040
1929 #define IXGBE_RFCTL_NFSR_DIS            0x00000080
1930 #define IXGBE_RFCTL_NFS_VER_MASK        0x00000300
1931 #define IXGBE_RFCTL_NFS_VER_SHIFT       8
1932 #define IXGBE_RFCTL_NFS_VER_2           0
1933 #define IXGBE_RFCTL_NFS_VER_3           1
1934 #define IXGBE_RFCTL_NFS_VER_4           2
1935 #define IXGBE_RFCTL_IPV6_DIS            0x00000400
1936 #define IXGBE_RFCTL_IPV6_XSUM_DIS       0x00000800
1937 #define IXGBE_RFCTL_IPFRSP_DIS          0x00004000
1938 #define IXGBE_RFCTL_IPV6_EX_DIS         0x00010000
1939 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
1940 
1941 /* Transmit Config masks */
1942 #define IXGBE_TXDCTL_ENABLE             0x02000000 /* Ena specific Tx Queue */
1943 #define IXGBE_TXDCTL_SWFLSH             0x04000000 /* Tx Desc. wr-bk flushing */
1944 #define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
1945 /* Enable short packet padding to 64 bytes */
1946 #define IXGBE_TX_PAD_ENABLE             0x00000400
1947 #define IXGBE_JUMBO_FRAME_ENABLE        0x00000004  /* Allow jumbo frames */
1948 /* This allows for 16K packets + 4k for vlan */
1949 #define IXGBE_MAX_FRAME_SZ              0x40040000
1950 
1951 #define IXGBE_TDWBAL_HEAD_WB_ENABLE     0x1 /* Tx head write-back enable */
1952 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE   0x2 /* Tx seq# write-back enable */
1953 
1954 /* Receive Config masks */
1955 #define IXGBE_RXCTRL_RXEN               0x00000001 /* Enable Receiver */
1956 #define IXGBE_RXCTRL_DMBYPS             0x00000002 /* Desc Monitor Bypass */
1957 #define IXGBE_RXDCTL_ENABLE             0x02000000 /* Ena specific Rx Queue */
1958 #define IXGBE_RXDCTL_SWFLSH             0x04000000 /* Rx Desc wr-bk flushing */
1959 #define IXGBE_RXDCTL_RLPMLMASK          0x00003FFF /* X540 supported only */
1960 #define IXGBE_RXDCTL_RLPML_EN           0x00008000
1961 #define IXGBE_RXDCTL_VME                0x40000000 /* VLAN mode enable */
1962 
1963 #define IXGBE_TSAUXC_EN_CLK             0x00000004
1964 #define IXGBE_TSAUXC_SYNCLK             0x00000008
1965 #define IXGBE_TSAUXC_SDP0_INT           0x00000040




1966 




1967 #define IXGBE_TSYNCTXCTL_VALID          0x00000001 /* Tx timestamp valid */
1968 #define IXGBE_TSYNCTXCTL_ENABLED        0x00000010 /* Tx timestamping enabled */
1969 
1970 #define IXGBE_TSYNCRXCTL_VALID          0x00000001 /* Rx timestamp valid */
1971 #define IXGBE_TSYNCRXCTL_TYPE_MASK      0x0000000E /* Rx type mask */
1972 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2     0x00
1973 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1     0x02
1974 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2  0x04

1975 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2  0x0A
1976 #define IXGBE_TSYNCRXCTL_ENABLED        0x00000010 /* Rx Timestamping enabled */


1977 








1978 #define IXGBE_RXMTRL_V1_CTRLT_MASK      0x000000FF
1979 #define IXGBE_RXMTRL_V1_SYNC_MSG        0x00
1980 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG   0x01
1981 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG    0x02
1982 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG  0x03
1983 #define IXGBE_RXMTRL_V1_MGMT_MSG        0x04
1984 
1985 #define IXGBE_RXMTRL_V2_MSGID_MASK      0x0000FF00
1986 #define IXGBE_RXMTRL_V2_SYNC_MSG        0x0000
1987 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG   0x0100
1988 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG  0x0200
1989 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
1990 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG    0x0800
1991 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG  0x0900
1992 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
1993 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG    0x0B00
1994 #define IXGBE_RXMTRL_V2_SIGNALLING_MSG  0x0C00
1995 #define IXGBE_RXMTRL_V2_MGMT_MSG        0x0D00
1996 
1997 #define IXGBE_FCTRL_SBP         0x00000002 /* Store Bad Packet */


2015 #define IXGBE_MRQC_MRQE_MASK    0xF /* Bits 3:0 */
2016 #define IXGBE_MRQC_RT8TCEN      0x00000002 /* 8 TC no RSS */
2017 #define IXGBE_MRQC_RT4TCEN      0x00000003 /* 4 TC no RSS */
2018 #define IXGBE_MRQC_RTRSS8TCEN   0x00000004 /* 8 TC w/ RSS */
2019 #define IXGBE_MRQC_RTRSS4TCEN   0x00000005 /* 4 TC w/ RSS */
2020 #define IXGBE_MRQC_VMDQEN       0x00000008 /* VMDq2 64 pools no RSS */
2021 #define IXGBE_MRQC_VMDQRSS32EN  0x0000000A /* VMDq2 32 pools w/ RSS */
2022 #define IXGBE_MRQC_VMDQRSS64EN  0x0000000B /* VMDq2 64 pools w/ RSS */
2023 #define IXGBE_MRQC_VMDQRT8TCEN  0x0000000C /* VMDq2/RT 16 pool 8 TC */
2024 #define IXGBE_MRQC_VMDQRT4TCEN  0x0000000D /* VMDq2/RT 32 pool 4 TC */
2025 #define IXGBE_MRQC_RSS_FIELD_MASK       0xFFFF0000
2026 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP   0x00010000
2027 #define IXGBE_MRQC_RSS_FIELD_IPV4       0x00020000
2028 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2029 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX    0x00080000
2030 #define IXGBE_MRQC_RSS_FIELD_IPV6       0x00100000
2031 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP   0x00200000
2032 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP   0x00400000
2033 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP   0x00800000
2034 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000

2035 #define IXGBE_MRQC_L3L4TXSWEN           0x00008000
2036 
2037 /* Queue Drop Enable */
2038 #define IXGBE_QDE_ENABLE        0x00000001

2039 #define IXGBE_QDE_IDX_MASK      0x00007F00
2040 #define IXGBE_QDE_IDX_SHIFT     8
2041 #define IXGBE_QDE_WRITE         0x00010000
2042 #define IXGBE_QDE_READ          0x00020000
2043 
2044 #define IXGBE_TXD_POPTS_IXSM    0x01 /* Insert IP checksum */
2045 #define IXGBE_TXD_POPTS_TXSM    0x02 /* Insert TCP/UDP checksum */
2046 #define IXGBE_TXD_CMD_EOP       0x01000000 /* End of Packet */
2047 #define IXGBE_TXD_CMD_IFCS      0x02000000 /* Insert FCS (Ethernet CRC) */
2048 #define IXGBE_TXD_CMD_IC        0x04000000 /* Insert Checksum */
2049 #define IXGBE_TXD_CMD_RS        0x08000000 /* Report Status */
2050 #define IXGBE_TXD_CMD_DEXT      0x20000000 /* Desc extension (0 = legacy) */
2051 #define IXGBE_TXD_CMD_VLE       0x40000000 /* Add VLAN tag */
2052 #define IXGBE_TXD_STAT_DD       0x00000001 /* Descriptor Done */
2053 
2054 #define IXGBE_RXDADV_IPSEC_STATUS_SECP          0x00020000
2055 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2056 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
2057 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED    0x18000000
2058 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000


2060 #define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
2061 #define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
2062 #define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
2063 #define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
2064 #define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
2065 #define IXGBE_MTQC_4TC_4TQ      0x8 /* 4 TC if RT_ENA and VT_ENA */
2066 #define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2067 
2068 /* Receive Descriptor bit definitions */
2069 #define IXGBE_RXD_STAT_DD       0x01 /* Descriptor Done */
2070 #define IXGBE_RXD_STAT_EOP      0x02 /* End of Packet */
2071 #define IXGBE_RXD_STAT_FLM      0x04 /* FDir Match */
2072 #define IXGBE_RXD_STAT_VP       0x08 /* IEEE VLAN Packet */
2073 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
2074 #define IXGBE_RXDADV_NEXTP_SHIFT        0x00000004
2075 #define IXGBE_RXD_STAT_UDPCS    0x10 /* UDP xsum calculated */
2076 #define IXGBE_RXD_STAT_L4CS     0x20 /* L4 xsum calculated */
2077 #define IXGBE_RXD_STAT_IPCS     0x40 /* IP xsum calculated */
2078 #define IXGBE_RXD_STAT_PIF      0x80 /* passed in-exact filter */
2079 #define IXGBE_RXD_STAT_CRCV     0x100 /* Speculative CRC Valid */

2080 #define IXGBE_RXD_STAT_VEXT     0x200 /* 1st VLAN found */
2081 #define IXGBE_RXD_STAT_UDPV     0x400 /* Valid UDP checksum */
2082 #define IXGBE_RXD_STAT_DYNINT   0x800 /* Pkt caused INT via DYNINT */
2083 #define IXGBE_RXD_STAT_LLINT    0x800 /* Pkt caused Low Latency Interrupt */

2084 #define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
2085 #define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
2086 #define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
2087 #define IXGBE_RXD_STAT_ACK      0x8000 /* ACK Packet indication */
2088 #define IXGBE_RXD_ERR_CE        0x01 /* CRC Error */
2089 #define IXGBE_RXD_ERR_LE        0x02 /* Length Error */
2090 #define IXGBE_RXD_ERR_PE        0x08 /* Packet Error */
2091 #define IXGBE_RXD_ERR_OSE       0x10 /* Oversize Error */
2092 #define IXGBE_RXD_ERR_USE       0x20 /* Undersize Error */
2093 #define IXGBE_RXD_ERR_TCPE      0x40 /* TCP/UDP Checksum Error */
2094 #define IXGBE_RXD_ERR_IPE       0x80 /* IP Checksum Error */
2095 #define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
2096 #define IXGBE_RXDADV_ERR_SHIFT          20 /* RDESC.ERRORS shift */

2097 #define IXGBE_RXDADV_ERR_RXE            0x20000000 /* Any MAC Error */
2098 #define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCoEFe/IPE */
2099 #define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
2100 #define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
2101 #define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
2102 #define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
2103 #define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
2104 #define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
2105 #define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
2106 #define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
2107 #define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
2108 #define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
2109 #define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
2110 #define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
2111 #define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
2112 #define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
2113 #define IXGBE_RXD_PRI_SHIFT     13
2114 #define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
2115 #define IXGBE_RXD_CFI_SHIFT     12
2116 
2117 #define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
2118 #define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
2119 #define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
2120 #define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
2121 #define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
2122 #define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
2123 #define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
2124 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2125 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
2126 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2127 #define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
2128 #define IXGBE_RXDADV_STAT_TS            0x00010000 /* IEEE1588 Time Stamp */

2129 
2130 /* PSRTYPE bit definitions */
2131 #define IXGBE_PSRTYPE_TCPHDR    0x00000010
2132 #define IXGBE_PSRTYPE_UDPHDR    0x00000020
2133 #define IXGBE_PSRTYPE_IPV4HDR   0x00000100
2134 #define IXGBE_PSRTYPE_IPV6HDR   0x00000200
2135 #define IXGBE_PSRTYPE_L2HDR     0x00001000
2136 
2137 /* SRRCTL bit definitions */
2138 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10 /* so many KBs */




2139 #define IXGBE_SRRCTL_RDMTS_SHIFT        22
2140 #define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
2141 #define IXGBE_SRRCTL_DROP_EN            0x10000000
2142 #define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
2143 #define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
2144 #define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
2145 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2146 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2147 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2148 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2149 #define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
2150 
2151 #define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
2152 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2153 
2154 #define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
2155 #define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
2156 #define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
2157 #define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
2158 #define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000


2166 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
2167 #define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
2168 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
2169 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
2170 #define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
2171 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2172 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
2173 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
2174 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2175 
2176 /* RSS Packet Types as indicated in the receive descriptor. */
2177 #define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
2178 #define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
2179 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
2180 #define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
2181 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
2182 #define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
2183 #define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
2184 #define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
2185 #define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */


2186 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
2187 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
2188 #define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
2189 #define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
2190 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
2191 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
2192 
2193 /* Security Processing bit Indication */
2194 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP         0x00020000
2195 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
2196 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
2197 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
2198 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
2199 
2200 /* Masks to determine if packets should be dropped due to frame errors */
2201 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2202                                 IXGBE_RXD_ERR_CE | \
2203                                 IXGBE_RXD_ERR_LE | \
2204                                 IXGBE_RXD_ERR_PE | \
2205                                 IXGBE_RXD_ERR_OSE | \


2216 
2217 /* Multicast bit mask */
2218 #define IXGBE_MCSTCTRL_MFE      0x4
2219 
2220 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2221 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE        8
2222 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE        8
2223 #define IXGBE_REQ_TX_BUFFER_GRANULARITY         1024
2224 
2225 /* Vlan-specific macros */
2226 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
2227 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK  0xE000 /* Priority in upper 3 bits */
2228 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
2229 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2230 
2231 /* SR-IOV specific macros */
2232 #define IXGBE_MBVFICR_INDEX(vf_number)  (vf_number >> 4)
2233 #define IXGBE_MBVFICR(_i)               (0x00710 + ((_i) * 4))
2234 #define IXGBE_VFLRE(_i)                 (((_i & 1) ? 0x001C0 : 0x00600))
2235 #define IXGBE_VFLREC(_i)                 (0x00700 + ((_i) * 4))




















































2236 










2237 /* Little Endian defines */
2238 #ifndef __le16
2239 #define __le16  u16
2240 #endif
2241 #ifndef __le32
2242 #define __le32  u32
2243 #endif
2244 #ifndef __le64
2245 #define __le64  u64
2246 
2247 #endif
2248 #ifndef __be16
2249 /* Big Endian defines */
2250 #define __be16  u16
2251 #define __be32  u32
2252 #define __be64  u64
2253 
2254 #endif
2255 enum ixgbe_fdir_pballoc_type {
2256         IXGBE_FDIR_PBALLOC_NONE = 0,
2257         IXGBE_FDIR_PBALLOC_64K  = 1,
2258         IXGBE_FDIR_PBALLOC_128K = 2,
2259         IXGBE_FDIR_PBALLOC_256K = 3,
2260 };
2261 
2262 /* Flow Director register values */
2263 #define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
2264 #define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
2265 #define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
2266 #define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
2267 #define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
2268 #define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
2269 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
2270 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8

2271 #define IXGBE_FDIRCTRL_FLEX_SHIFT               16




2272 #define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000

2273 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
2274 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
2275 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
2276 
2277 #define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
2278 #define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
2279 #define IXGBE_FDIRIP6M_DIPM_SHIFT               16
2280 #define IXGBE_FDIRM_VLANID                      0x00000001
2281 #define IXGBE_FDIRM_VLANP                       0x00000002
2282 #define IXGBE_FDIRM_POOL                        0x00000004
2283 #define IXGBE_FDIRM_L4P                         0x00000008
2284 #define IXGBE_FDIRM_FLEX                        0x00000010
2285 #define IXGBE_FDIRM_DIPv6                       0x00000020

2286 






2287 #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
2288 #define IXGBE_FDIRFREE_FREE_SHIFT               0
2289 #define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
2290 #define IXGBE_FDIRFREE_COLL_SHIFT               16
2291 #define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
2292 #define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
2293 #define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
2294 #define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
2295 #define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
2296 #define IXGBE_FDIRUSTAT_ADD_SHIFT               0
2297 #define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
2298 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
2299 #define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
2300 #define IXGBE_FDIRFSTAT_FADD_SHIFT              0
2301 #define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
2302 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
2303 #define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
2304 #define IXGBE_FDIRVLAN_FLEX_SHIFT               16
2305 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
2306 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
2307 
2308 #define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
2309 #define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
2310 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
2311 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
2312 #define IXGBE_FDIRCMD_FILTER_VALID              0x00000004
2313 #define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
2314 #define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
2315 #define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
2316 #define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
2317 #define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
2318 #define IXGBE_FDIRCMD_IPV6                      0x00000080
2319 #define IXGBE_FDIRCMD_CLEARHT                   0x00000100
2320 #define IXGBE_FDIRCMD_DROP                      0x00000200
2321 #define IXGBE_FDIRCMD_INT                       0x00000400
2322 #define IXGBE_FDIRCMD_LAST                      0x00000800
2323 #define IXGBE_FDIRCMD_COLLISION                 0x00001000
2324 #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
2325 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
2326 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16

2327 #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
2328 #define IXGBE_FDIR_INIT_DONE_POLL               10
2329 #define IXGBE_FDIRCMD_CMD_POLL                  10
2330 
2331 #define IXGBE_FDIR_DROP_QUEUE                   127
2332 
2333 #define IXGBE_STATUS_OVERHEATING_BIT            20 /* STATUS overtemp bit num */
2334 
2335 /* Manageablility Host Interface defines */
2336 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH  1792 /* Num of bytes in range */
2337 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
2338 #define IXGBE_HI_COMMAND_TIMEOUT        500 /* Process HI command limit */




2339 
2340 /* CEM Support */
2341 #define FW_CEM_HDR_LEN                  0x4
2342 #define FW_CEM_CMD_DRIVER_INFO          0xDD
2343 #define FW_CEM_CMD_DRIVER_INFO_LEN      0x5
2344 #define FW_CEM_CMD_RESERVED             0X0
2345 #define FW_CEM_UNUSED_VER               0x0
2346 #define FW_CEM_MAX_RETRIES              3
2347 #define FW_CEM_RESP_STATUS_SUCCESS      0x1
















2348 
2349 /* Host Interface Command Structures */
2350 
2351 struct ixgbe_hic_hdr {
2352         u8 cmd;
2353         u8 buf_len;
2354         union {
2355                 u8 cmd_resv;
2356                 u8 ret_status;
2357         } cmd_or_resp;
2358         u8 checksum;
2359 };
2360 



















2361 struct ixgbe_hic_drv_info {
2362         struct ixgbe_hic_hdr hdr;
2363         u8 port_num;
2364         u8 ver_sub;
2365         u8 ver_build;
2366         u8 ver_min;
2367         u8 ver_maj;
2368         u8 pad; /* end spacing to ensure length is mult. of dword */
2369         u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2370 };
2371 










































2372 /* Transmit Descriptor - Legacy */
2373 struct ixgbe_legacy_tx_desc {
2374         u64 buffer_addr; /* Address of the descriptor's data buffer */
2375         union {
2376                 __le32 data;
2377                 struct {
2378                         __le16 length; /* Data buffer length */
2379                         u8 cso; /* Checksum offset */
2380                         u8 cmd; /* Descriptor control */
2381                 } flags;
2382         } lower;
2383         union {
2384                 __le32 data;
2385                 struct {
2386                         u8 status; /* Descriptor status */
2387                         u8 css; /* Checksum start */
2388                         __le16 vlan;
2389                 } fields;
2390         } upper;
2391 };


2493 #define IXGBE_ADVTXD_TUCMD_L4T_UDP      0x00000000 /* L4 Packet TYPE of UDP */
2494 #define IXGBE_ADVTXD_TUCMD_L4T_TCP      0x00000800 /* L4 Packet TYPE of TCP */
2495 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP     0x00001000 /* L4 Packet TYPE of SCTP */
2496 #define IXGBE_ADVTXD_TUCMD_MKRREQ       0x00002000 /* req Markers and CRC */
2497 #define IXGBE_ADVTXD_POPTS_IPSEC        0x00000400 /* IPSec offload request */
2498 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2499 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2500 #define IXGBE_ADVTXT_TUCMD_FCOE         0x00008000 /* FCoE Frame Type */
2501 #define IXGBE_ADVTXD_FCOEF_EOF_MASK     (0x3 << 10) /* FC EOF index */
2502 #define IXGBE_ADVTXD_FCOEF_SOF          ((1 << 2) << 10) /* FC SOF index */
2503 #define IXGBE_ADVTXD_FCOEF_PARINC       ((1 << 3) << 10) /* Rel_Off in F_CTL */
2504 #define IXGBE_ADVTXD_FCOEF_ORIE         ((1 << 4) << 10) /* Orientation End */
2505 #define IXGBE_ADVTXD_FCOEF_ORIS         ((1 << 5) << 10) /* Orientation Start */
2506 #define IXGBE_ADVTXD_FCOEF_EOF_N        (0x0 << 10) /* 00: EOFn */
2507 #define IXGBE_ADVTXD_FCOEF_EOF_T        (0x1 << 10) /* 01: EOFt */
2508 #define IXGBE_ADVTXD_FCOEF_EOF_NI       (0x2 << 10) /* 10: EOFni */
2509 #define IXGBE_ADVTXD_FCOEF_EOF_A        (0x3 << 10) /* 11: EOFa */
2510 #define IXGBE_ADVTXD_L4LEN_SHIFT        8  /* Adv ctxt L4LEN shift */
2511 #define IXGBE_ADVTXD_MSS_SHIFT          16  /* Adv ctxt MSS shift */
2512 






2513 /* Autonegotiation advertised speeds */
2514 typedef u32 ixgbe_autoneg_advertised;
2515 /* Link speed */
2516 typedef u32 ixgbe_link_speed;
2517 #define IXGBE_LINK_SPEED_UNKNOWN        0
2518 #define IXGBE_LINK_SPEED_100_FULL       0x0008
2519 #define IXGBE_LINK_SPEED_1GB_FULL       0x0020


2520 #define IXGBE_LINK_SPEED_10GB_FULL      0x0080
2521 #define IXGBE_LINK_SPEED_82598_AUTONEG  (IXGBE_LINK_SPEED_1GB_FULL | \
2522                                          IXGBE_LINK_SPEED_10GB_FULL)
2523 #define IXGBE_LINK_SPEED_82599_AUTONEG  (IXGBE_LINK_SPEED_100_FULL | \
2524                                          IXGBE_LINK_SPEED_1GB_FULL | \
2525                                          IXGBE_LINK_SPEED_10GB_FULL)
2526 
2527 
2528 /* Physical layer type */
2529 typedef u32 ixgbe_physical_layer;
2530 #define IXGBE_PHYSICAL_LAYER_UNKNOWN            0
2531 #define IXGBE_PHYSICAL_LAYER_10GBASE_T          0x0001
2532 #define IXGBE_PHYSICAL_LAYER_1000BASE_T         0x0002
2533 #define IXGBE_PHYSICAL_LAYER_100BASE_TX         0x0004
2534 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU        0x0008
2535 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR         0x0010
2536 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM        0x0020
2537 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR         0x0040
2538 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4        0x0080
2539 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4        0x0100
2540 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX        0x0200
2541 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX        0x0400
2542 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR         0x0800
2543 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI       0x1000
2544 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA      0x2000
2545 #define IXGBE_PHYSICAL_LAYER_1000BASE_SX        0x4000
2546 
2547 /* Flow Control Data Sheet defined values


2600                          2 * IXGBE_B2BT(_max_frame_tc))
2601 
2602 /* Calculate low threshold delay values */
2603 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
2604                         (2 * IXGBE_B2BT(_max_frame_tc) + \
2605                         (36 * IXGBE_PCI_DELAY / 25) + 1)
2606 #define IXGBE_LOW_DV(_max_frame_tc) \
2607                         (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
2608 
2609 /* Software ATR hash keys */
2610 #define IXGBE_ATR_BUCKET_HASH_KEY       0x3DAD14E2
2611 #define IXGBE_ATR_SIGNATURE_HASH_KEY    0x174D3614
2612 
2613 /* Software ATR input stream values and masks */
2614 #define IXGBE_ATR_HASH_MASK             0x7fff
2615 #define IXGBE_ATR_L4TYPE_MASK           0x3
2616 #define IXGBE_ATR_L4TYPE_UDP            0x1
2617 #define IXGBE_ATR_L4TYPE_TCP            0x2
2618 #define IXGBE_ATR_L4TYPE_SCTP           0x3
2619 #define IXGBE_ATR_L4TYPE_IPV6_MASK      0x4

2620 enum ixgbe_atr_flow_type {
2621         IXGBE_ATR_FLOW_TYPE_IPV4        = 0x0,
2622         IXGBE_ATR_FLOW_TYPE_UDPV4       = 0x1,
2623         IXGBE_ATR_FLOW_TYPE_TCPV4       = 0x2,
2624         IXGBE_ATR_FLOW_TYPE_SCTPV4      = 0x3,
2625         IXGBE_ATR_FLOW_TYPE_IPV6        = 0x4,
2626         IXGBE_ATR_FLOW_TYPE_UDPV6       = 0x5,
2627         IXGBE_ATR_FLOW_TYPE_TCPV6       = 0x6,
2628         IXGBE_ATR_FLOW_TYPE_SCTPV6      = 0x7,








2629 };
2630 
2631 /* Flow Director ATR input struct. */
2632 union ixgbe_atr_input {
2633         /*
2634          * Byte layout in order, all values with MSB first:
2635          *
2636          * vm_pool      - 1 byte
2637          * flow_type    - 1 byte
2638          * vlan_id      - 2 bytes
2639          * src_ip       - 16 bytes



2640          * dst_ip       - 16 bytes
2641          * src_port     - 2 bytes
2642          * dst_port     - 2 bytes
2643          * flex_bytes   - 2 bytes
2644          * bkt_hash     - 2 bytes
2645          */
2646         struct {
2647                 u8 vm_pool;
2648                 u8 flow_type;
2649                 __be16 vlan_id;
2650                 __be32 dst_ip[4];
2651                 __be32 src_ip[4];



2652                 __be16 src_port;
2653                 __be16 dst_port;
2654                 __be16 flex_bytes;
2655                 __be16 bkt_hash;
2656         } formatted;
2657         __be32 dword_stream[11];
2658 };
2659 
2660 /* Flow Director compressed ATR hash input struct */
2661 union ixgbe_atr_hash_dword {
2662         struct {
2663                 u8 vm_pool;
2664                 u8 flow_type;
2665                 __be16 vlan_id;
2666         } formatted;
2667         __be32 ip;
2668         struct {
2669                 __be16 src;
2670                 __be16 dst;
2671         } port;
2672         __be16 flex_bytes;
2673         __be32 dword;
2674 };
2675 
2676 































2677 /*
2678  * Unavailable: The FCoE Boot Option ROM is not present in the flash.
2679  * Disabled: Present; boot order is not set for any targets on the port.
2680  * Enabled: Present; boot order is set for at least one target on the port.
2681  */
2682 enum ixgbe_fcoe_boot_status {
2683         ixgbe_fcoe_bootstatus_disabled = 0,
2684         ixgbe_fcoe_bootstatus_enabled = 1,
2685         ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
2686 };
2687 
2688 enum ixgbe_eeprom_type {
2689         ixgbe_eeprom_uninitialized = 0,
2690         ixgbe_eeprom_spi,
2691         ixgbe_flash,
2692         ixgbe_eeprom_none /* No NVM support */
2693 };
2694 
2695 enum ixgbe_mac_type {
2696         ixgbe_mac_unknown = 0,
2697         ixgbe_mac_82598EB,
2698         ixgbe_mac_82599EB,
2699         ixgbe_mac_82599_vf,
2700         ixgbe_mac_X540,
2701         ixgbe_mac_X540_vf,




2702         ixgbe_num_macs
2703 };
2704 
2705 enum ixgbe_phy_type {
2706         ixgbe_phy_unknown = 0,
2707         ixgbe_phy_none,
2708         ixgbe_phy_tn,
2709         ixgbe_phy_aq,



2710         ixgbe_phy_cu_unknown,
2711         ixgbe_phy_qt,
2712         ixgbe_phy_xaui,
2713         ixgbe_phy_nl,
2714         ixgbe_phy_sfp_passive_tyco,
2715         ixgbe_phy_sfp_passive_unknown,
2716         ixgbe_phy_sfp_active_unknown,
2717         ixgbe_phy_sfp_avago,
2718         ixgbe_phy_sfp_ftl,
2719         ixgbe_phy_sfp_ftl_active,
2720         ixgbe_phy_sfp_unknown,
2721         ixgbe_phy_sfp_intel,




2722         ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
2723         ixgbe_phy_generic
2724 };
2725 
2726 /*
2727  * SFP+ module type IDs:
2728  *
2729  * ID   Module Type
2730  * =============
2731  * 0    SFP_DA_CU
2732  * 1    SFP_SR
2733  * 2    SFP_LR
2734  * 3    SFP_DA_CU_CORE0 - 82599-specific
2735  * 4    SFP_DA_CU_CORE1 - 82599-specific
2736  * 5    SFP_SR/LR_CORE0 - 82599-specific
2737  * 6    SFP_SR/LR_CORE1 - 82599-specific
2738  */
2739 enum ixgbe_sfp_type {
2740         ixgbe_sfp_type_da_cu = 0,
2741         ixgbe_sfp_type_sr = 1,
2742         ixgbe_sfp_type_lr = 2,
2743         ixgbe_sfp_type_da_cu_core0 = 3,
2744         ixgbe_sfp_type_da_cu_core1 = 4,
2745         ixgbe_sfp_type_srlr_core0 = 5,
2746         ixgbe_sfp_type_srlr_core1 = 6,
2747         ixgbe_sfp_type_da_act_lmt_core0 = 7,
2748         ixgbe_sfp_type_da_act_lmt_core1 = 8,
2749         ixgbe_sfp_type_1g_cu_core0 = 9,
2750         ixgbe_sfp_type_1g_cu_core1 = 10,
2751         ixgbe_sfp_type_1g_sx_core0 = 11,
2752         ixgbe_sfp_type_1g_sx_core1 = 12,
2753         ixgbe_sfp_type_1g_lx_core0 = 13,
2754         ixgbe_sfp_type_1g_lx_core1 = 14,
2755         ixgbe_sfp_type_not_present = 0xFFFE,
2756         ixgbe_sfp_type_unknown = 0xFFFF
2757 };
2758 
2759 enum ixgbe_media_type {
2760         ixgbe_media_type_unknown = 0,
2761         ixgbe_media_type_fiber,


2762         ixgbe_media_type_copper,
2763         ixgbe_media_type_backplane,
2764         ixgbe_media_type_cx4,
2765         ixgbe_media_type_virtual
2766 };
2767 
2768 /* Flow Control Settings */
2769 enum ixgbe_fc_mode {
2770         ixgbe_fc_none = 0,
2771         ixgbe_fc_rx_pause,
2772         ixgbe_fc_tx_pause,
2773         ixgbe_fc_full,
2774         ixgbe_fc_default
2775 };
2776 
2777 /* Smart Speed Settings */
2778 #define IXGBE_SMARTSPEED_MAX_RETRIES    3
2779 enum ixgbe_smart_speed {
2780         ixgbe_smart_speed_auto = 0,
2781         ixgbe_smart_speed_on,
2782         ixgbe_smart_speed_off
2783 };
2784 
2785 /* PCI bus types */
2786 enum ixgbe_bus_type {
2787         ixgbe_bus_type_unknown = 0,
2788         ixgbe_bus_type_pci,
2789         ixgbe_bus_type_pcix,
2790         ixgbe_bus_type_pci_express,

2791         ixgbe_bus_type_reserved
2792 };
2793 
2794 /* PCI bus speeds */
2795 enum ixgbe_bus_speed {
2796         ixgbe_bus_speed_unknown = 0,
2797         ixgbe_bus_speed_33      = 33,
2798         ixgbe_bus_speed_66      = 66,
2799         ixgbe_bus_speed_100     = 100,
2800         ixgbe_bus_speed_120     = 120,
2801         ixgbe_bus_speed_133     = 133,
2802         ixgbe_bus_speed_2500    = 2500,
2803         ixgbe_bus_speed_5000    = 5000,
2804         ixgbe_bus_speed_8000    = 8000,
2805         ixgbe_bus_speed_reserved
2806 };
2807 
2808 /* PCI bus widths */
2809 enum ixgbe_bus_width {
2810         ixgbe_bus_width_unknown = 0,


2927         u64 o2bgptc;
2928         u64 o2bspc;
2929 };
2930 
2931 /* forward declaration */
2932 struct ixgbe_hw;
2933 
2934 /* iterator type for walking multicast address lists */
2935 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2936                                   u32 *vmdq);
2937 
2938 /* Function pointer table */
2939 struct ixgbe_eeprom_operations {
2940         s32 (*init_params)(struct ixgbe_hw *);
2941         s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2942         s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2943         s32 (*write)(struct ixgbe_hw *, u16, u16);
2944         s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2945         s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2946         s32 (*update_checksum)(struct ixgbe_hw *);
2947         u16 (*calc_checksum)(struct ixgbe_hw *);
2948 };
2949 
2950 struct ixgbe_mac_operations {
2951         s32 (*init_hw)(struct ixgbe_hw *);
2952         s32 (*reset_hw)(struct ixgbe_hw *);
2953         s32 (*start_hw)(struct ixgbe_hw *);
2954         s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
2955         void (*enable_relaxed_ordering)(struct ixgbe_hw *);
2956         enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2957         u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2958         s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2959         s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
2960         s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
2961         s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2962         s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
2963         s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
2964         s32 (*stop_adapter)(struct ixgbe_hw *);
2965         s32 (*get_bus_info)(struct ixgbe_hw *);
2966         void (*set_lan_id)(struct ixgbe_hw *);
2967         s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2968         s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2969         s32 (*setup_sfp)(struct ixgbe_hw *);
2970         s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2971         s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
2972         s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
2973         s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2974         void (*release_swfw_sync)(struct ixgbe_hw *, u16);


2975 
2976         /* Link */
2977         void (*disable_tx_laser)(struct ixgbe_hw *);
2978         void (*enable_tx_laser)(struct ixgbe_hw *);
2979         void (*flap_tx_laser)(struct ixgbe_hw *);
2980         s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);

2981         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2982         s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2983                                      bool *);

2984 
2985         /* Packet Buffer manipulation */
2986         void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
2987 
2988         /* LED */
2989         s32 (*led_on)(struct ixgbe_hw *, u32);
2990         s32 (*led_off)(struct ixgbe_hw *, u32);
2991         s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2992         s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2993 
2994         /* RAR, Multicast, VLAN */
2995         s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2996         s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
2997         s32 (*clear_rar)(struct ixgbe_hw *, u32);
2998         s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
2999         s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3000         s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3001         s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3002         s32 (*init_rx_addrs)(struct ixgbe_hw *);
3003         s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3004                                    ixgbe_mc_addr_itr);
3005         s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3006                                    ixgbe_mc_addr_itr, bool clear);
3007         s32 (*enable_mc)(struct ixgbe_hw *);
3008         s32 (*disable_mc)(struct ixgbe_hw *);
3009         s32 (*clear_vfta)(struct ixgbe_hw *);
3010         s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
3011         s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);
3012         s32 (*init_uta_tables)(struct ixgbe_hw *);
3013         void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3014         void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3015 
3016         /* Flow Control */
3017         s32 (*fc_enable)(struct ixgbe_hw *);

3018 
3019         /* Manageability interface */
3020         s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
















3021 };
3022 
3023 struct ixgbe_phy_operations {
3024         s32 (*identify)(struct ixgbe_hw *);
3025         s32 (*identify_sfp)(struct ixgbe_hw *);
3026         s32 (*init)(struct ixgbe_hw *);
3027         s32 (*reset)(struct ixgbe_hw *);
3028         s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3029         s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);


3030         s32 (*setup_link)(struct ixgbe_hw *);
3031         s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
3032                                 bool);
3033         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3034         s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3035         s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3036         s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);

3037         s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3038         s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3039         void (*i2c_bus_clear)(struct ixgbe_hw *);


3040         s32 (*check_overtemp)(struct ixgbe_hw *);











3041 };
3042 
3043 struct ixgbe_eeprom_info {
3044         struct ixgbe_eeprom_operations ops;
3045         enum ixgbe_eeprom_type type;
3046         u32 semaphore_delay;
3047         u16 word_size;
3048         u16 address_bits;
3049         u16 word_page_size;

3050 };
3051 
3052 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED       0x01
3053 struct ixgbe_mac_info {
3054         struct ixgbe_mac_operations ops;
3055         enum ixgbe_mac_type type;
3056         u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3057         u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3058         u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3059         /* prefix for World Wide Node Name (WWNN) */
3060         u16 wwnn_prefix;
3061         /* prefix for World Wide Port Name (WWPN) */
3062         u16 wwpn_prefix;
3063 #define IXGBE_MAX_MTA                   128
3064         u32 mta_shadow[IXGBE_MAX_MTA];
3065         s32 mc_filter_type;
3066         u32 mcft_size;
3067         u32 vft_size;
3068         u32 num_rar_entries;
3069         u32 rar_highwater;
3070         u32 rx_pb_size;
3071         u32 max_tx_queues;
3072         u32 max_rx_queues;
3073         u32 orig_autoc;
3074         u8  san_mac_rar_index;

3075         u32 orig_autoc2;
3076         u16 max_msix_vectors;
3077         bool arc_subsystem_valid;
3078         bool orig_link_settings_stored;
3079         bool autotry_restart;
3080         u8 flags;



3081 };
3082 
3083 struct ixgbe_phy_info {
3084         struct ixgbe_phy_operations ops;
3085         enum ixgbe_phy_type type;
3086         u32 addr;
3087         u32 id;
3088         enum ixgbe_sfp_type sfp_type;
3089         bool sfp_setup_needed;
3090         u32 revision;
3091         enum ixgbe_media_type media_type;

3092         bool reset_disable;
3093         ixgbe_autoneg_advertised autoneg_advertised;

3094         enum ixgbe_smart_speed smart_speed;
3095         bool smart_speed_active;
3096         bool multispeed_fiber;
3097         bool reset_if_overtemp;


3098 };
3099 
3100 #include "ixgbe_mbx.h"
3101 
3102 struct ixgbe_mbx_operations {
3103         void (*init_params)(struct ixgbe_hw *hw);
3104         s32  (*read)(struct ixgbe_hw *, u32 *, u16,  u16);
3105         s32  (*write)(struct ixgbe_hw *, u32 *, u16, u16);
3106         s32  (*read_posted)(struct ixgbe_hw *, u32 *, u16,  u16);
3107         s32  (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3108         s32  (*check_for_msg)(struct ixgbe_hw *, u16);
3109         s32  (*check_for_ack)(struct ixgbe_hw *, u16);
3110         s32  (*check_for_rst)(struct ixgbe_hw *, u16);
3111 };
3112 
3113 struct ixgbe_mbx_stats {
3114         u32 msgs_tx;
3115         u32 msgs_rx;
3116 
3117         u32 acks;
3118         u32 reqs;
3119         u32 rsts;
3120 };
3121 
3122 struct ixgbe_mbx_info {
3123         struct ixgbe_mbx_operations ops;
3124         struct ixgbe_mbx_stats stats;
3125         u32 timeout;
3126         u32 usec_delay;
3127         u32 v2p_mailbox;
3128         u16 size;
3129 };
3130 
3131 struct ixgbe_hw {
3132         u8 *hw_addr;
3133         void *back;
3134         struct ixgbe_mac_info mac;
3135         struct ixgbe_addr_filter_info addr_ctrl;
3136         struct ixgbe_fc_info fc;
3137         struct ixgbe_phy_info phy;
3138         struct ixgbe_eeprom_info eeprom;
3139         struct ixgbe_bus_info bus;
3140         struct ixgbe_mbx_info mbx;

3141         u16 device_id;
3142         u16 vendor_id;
3143         u16 subsystem_device_id;
3144         u16 subsystem_vendor_id;
3145         u8 revision_id;
3146         bool adapter_stopped;

3147         bool force_full_reset;
3148         bool allow_unsupported_sfp;

3149 };
3150 
3151 #define ixgbe_call_func(hw, func, params, error) \
3152                 (func != NULL) ? func params : error
3153 
3154 
3155 /* Error Codes */
3156 #define IXGBE_SUCCESS                           0
3157 #define IXGBE_ERR_EEPROM                        -1
3158 #define IXGBE_ERR_EEPROM_CHECKSUM               -2
3159 #define IXGBE_ERR_PHY                           -3
3160 #define IXGBE_ERR_CONFIG                        -4
3161 #define IXGBE_ERR_PARAM                         -5
3162 #define IXGBE_ERR_MAC_TYPE                      -6
3163 #define IXGBE_ERR_UNKNOWN_PHY                   -7
3164 #define IXGBE_ERR_LINK_SETUP                    -8
3165 #define IXGBE_ERR_ADAPTER_STOPPED               -9
3166 #define IXGBE_ERR_INVALID_MAC_ADDR              -10
3167 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11
3168 #define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12


3170 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14
3171 #define IXGBE_ERR_RESET_FAILED                  -15
3172 #define IXGBE_ERR_SWFW_SYNC                     -16
3173 #define IXGBE_ERR_PHY_ADDR_INVALID              -17
3174 #define IXGBE_ERR_I2C                           -18
3175 #define IXGBE_ERR_SFP_NOT_SUPPORTED             -19
3176 #define IXGBE_ERR_SFP_NOT_PRESENT               -20
3177 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT       -21
3178 #define IXGBE_ERR_NO_SAN_ADDR_PTR               -22
3179 #define IXGBE_ERR_FDIR_REINIT_FAILED            -23
3180 #define IXGBE_ERR_EEPROM_VERSION                -24
3181 #define IXGBE_ERR_NO_SPACE                      -25
3182 #define IXGBE_ERR_OVERTEMP                      -26
3183 #define IXGBE_ERR_FC_NOT_NEGOTIATED             -27
3184 #define IXGBE_ERR_FC_NOT_SUPPORTED              -28
3185 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
3186 #define IXGBE_ERR_PBA_SECTION                   -31
3187 #define IXGBE_ERR_INVALID_ARGUMENT              -32
3188 #define IXGBE_ERR_HOST_INTERFACE_COMMAND        -33
3189 #define IXGBE_ERR_OUT_OF_MEM                    -34



3190 
3191 #define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
3192 
3193 


































































3194 #endif /* _IXGBE_TYPE_H_ */
   1 /******************************************************************************
   2 
   3   Copyright (c) 2001-2015, Intel Corporation 
   4   All rights reserved.
   5   
   6   Redistribution and use in source and binary forms, with or without 
   7   modification, are permitted provided that the following conditions are met:
   8   
   9    1. Redistributions of source code must retain the above copyright notice, 
  10       this list of conditions and the following disclaimer.
  11   
  12    2. Redistributions in binary form must reproduce the above copyright 
  13       notice, this list of conditions and the following disclaimer in the 
  14       documentation and/or other materials provided with the distribution.
  15   
  16    3. Neither the name of the Intel Corporation nor the names of its 
  17       contributors may be used to endorse or promote products derived from 
  18       this software without specific prior written permission.
  19   
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31 
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34 
  35 #ifndef _IXGBE_TYPE_H_
  36 #define _IXGBE_TYPE_H_
  37 
  38 /*
  39  * The following is a brief description of the error categories used by the
  40  * ERROR_REPORT* macros.
  41  *
  42  * - IXGBE_ERROR_INVALID_STATE
  43  * This category is for errors which represent a serious failure state that is
  44  * unexpected, and could be potentially harmful to device operation. It should
  45  * not be used for errors relating to issues that can be worked around or
  46  * ignored.
  47  *
  48  * - IXGBE_ERROR_POLLING
  49  * This category is for errors related to polling/timeout issues and should be
  50  * used in any case where the timeout occured, or a failure to obtain a lock, or
  51  * failure to receive data within the time limit.
  52  *
  53  * - IXGBE_ERROR_CAUTION
  54  * This category should be used for reporting issues that may be the cause of
  55  * other errors, such as temperature warnings. It should indicate an event which
  56  * could be serious, but hasn't necessarily caused problems yet.
  57  *
  58  * - IXGBE_ERROR_SOFTWARE
  59  * This category is intended for errors due to software state preventing
  60  * something. The category is not intended for errors due to bad arguments, or
  61  * due to unsupported features. It should be used when a state occurs which
  62  * prevents action but is not a serious issue.
  63  *
  64  * - IXGBE_ERROR_ARGUMENT
  65  * This category is for when a bad or invalid argument is passed. It should be
  66  * used whenever a function is called and error checking has detected the
  67  * argument is wrong or incorrect.
  68  *
  69  * - IXGBE_ERROR_UNSUPPORTED
  70  * This category is for errors which are due to unsupported circumstances or
  71  * configuration issues. It should not be used when the issue is due to an
  72  * invalid argument, but for when something has occurred that is unsupported
  73  * (Ex: Flow control autonegotiation or an unsupported SFP+ module.)
  74  */
  75 
  76 #include "ixgbe_osdep.h"
  77 
  78 /* Override this by setting IOMEM in your ixgbe_osdep.h header */
  79 #define IOMEM
  80 
  81 /* Vendor ID */
  82 #define IXGBE_INTEL_VENDOR_ID                   0x8086
  83 
  84 /* Device IDs */
  85 #define IXGBE_DEV_ID_82598                      0x10B6
  86 #define IXGBE_DEV_ID_82598_BX                   0x1508
  87 #define IXGBE_DEV_ID_82598AF_DUAL_PORT          0x10C6
  88 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT        0x10C7
  89 #define IXGBE_DEV_ID_82598AT                    0x10C8
  90 #define IXGBE_DEV_ID_82598AT2                   0x150B
  91 #define IXGBE_DEV_ID_82598EB_SFP_LOM            0x10DB
  92 #define IXGBE_DEV_ID_82598EB_CX4                0x10DD
  93 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT        0x10EC
  94 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT         0x10F1
  95 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
  96 #define IXGBE_DEV_ID_82598EB_XF_LR              0x10F4
  97 #define IXGBE_DEV_ID_82599_KX4                  0x10F7
  98 #define IXGBE_DEV_ID_82599_KX4_MEZZ             0x1514
  99 #define IXGBE_DEV_ID_82599_KR                   0x1517
 100 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE      0x10F8
 101 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ       0x000C
 102 #define IXGBE_DEV_ID_82599_CX4                  0x10F9
 103 #define IXGBE_DEV_ID_82599_SFP                  0x10FB
 104 #define IXGBE_SUBDEV_ID_82599_SFP               0x11A9
 105 #define IXGBE_SUBDEV_ID_82599_SFP_WOL0          0x1071
 106 #define IXGBE_SUBDEV_ID_82599_RNDC              0x1F72
 107 #define IXGBE_SUBDEV_ID_82599_560FLR            0x17D0
 108 #define IXGBE_SUBDEV_ID_82599_ECNA_DP           0x0470
 109 #define IXGBE_SUBDEV_ID_82599_SP_560FLR         0x211B
 110 #define IXGBE_SUBDEV_ID_82599_LOM_SFP           0x8976
 111 #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6         0x2159
 112 #define IXGBE_SUBDEV_ID_82599_SFP_1OCP          0x000D
 113 #define IXGBE_SUBDEV_ID_82599_SFP_2OCP          0x0008
 114 #define IXGBE_SUBDEV_ID_82599_SFP_LOM           0x06EE
 115 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152A
 116 #define IXGBE_DEV_ID_82599_SFP_FCOE             0x1529
 117 #define IXGBE_DEV_ID_82599_SFP_EM               0x1507
 118 #define IXGBE_DEV_ID_82599_SFP_SF2              0x154D
 119 #define IXGBE_DEV_ID_82599_SFP_SF_QP            0x154A
 120 #define IXGBE_DEV_ID_82599_QSFP_SF_QP           0x1558
 121 #define IXGBE_DEV_ID_82599EN_SFP                0x1557
 122 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1        0x0001
 123 #define IXGBE_DEV_ID_82599_XAUI_LOM             0x10FC
 124 #define IXGBE_DEV_ID_82599_T3_LOM               0x151C
 125 #define IXGBE_DEV_ID_82599_VF                   0x10ED
 126 #define IXGBE_DEV_ID_82599_VF_HV                0x152E
 127 #define IXGBE_DEV_ID_82599_BYPASS               0x155D
 128 #define IXGBE_DEV_ID_X540T                      0x1528
 129 #define IXGBE_DEV_ID_X540_VF                    0x1515
 130 #define IXGBE_DEV_ID_X540_VF_HV                 0x1530
 131 #define IXGBE_DEV_ID_X540_BYPASS                0x155C
 132 #define IXGBE_DEV_ID_X540T1                     0x1560
 133 #define IXGBE_DEV_ID_X550T                      0x1563
 134 #define IXGBE_DEV_ID_X550T1                     0x15D1
 135 #define IXGBE_DEV_ID_X550EM_X_KX4               0x15AA
 136 #define IXGBE_DEV_ID_X550EM_X_KR                0x15AB
 137 #define IXGBE_DEV_ID_X550EM_X_SFP               0x15AC
 138 #define IXGBE_DEV_ID_X550EM_X_10G_T             0x15AD
 139 #define IXGBE_DEV_ID_X550EM_X_1G_T              0x15AE
 140 #define IXGBE_DEV_ID_X550_VF_HV                 0x1564
 141 #define IXGBE_DEV_ID_X550_VF                    0x1565
 142 #define IXGBE_DEV_ID_X550EM_X_VF                0x15A8
 143 #define IXGBE_DEV_ID_X550EM_X_VF_HV             0x15A9
 144 
 145 #define IXGBE_CAT(r,m) IXGBE_##r##m
 146 
 147 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
 148 
 149 /* General Registers */
 150 #define IXGBE_CTRL              0x00000
 151 #define IXGBE_STATUS            0x00008
 152 #define IXGBE_CTRL_EXT          0x00018
 153 #define IXGBE_ESDP              0x00020
 154 #define IXGBE_EODSDP            0x00028
 155 #define IXGBE_I2CCTL_82599      0x00028
 156 #define IXGBE_I2CCTL            IXGBE_I2CCTL_82599
 157 #define IXGBE_I2CCTL_X540       IXGBE_I2CCTL_82599
 158 #define IXGBE_I2CCTL_X550       0x15F5C
 159 #define IXGBE_I2CCTL_X550EM_x   IXGBE_I2CCTL_X550
 160 #define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
 161 #define IXGBE_PHY_GPIO          0x00028
 162 #define IXGBE_MAC_GPIO          0x00030
 163 #define IXGBE_PHYINT_STATUS0    0x00100
 164 #define IXGBE_PHYINT_STATUS1    0x00104
 165 #define IXGBE_PHYINT_STATUS2    0x00108
 166 #define IXGBE_LEDCTL            0x00200
 167 #define IXGBE_FRTIMER           0x00048
 168 #define IXGBE_TCPTIMER          0x0004C
 169 #define IXGBE_CORESPARE         0x00600
 170 #define IXGBE_EXVET             0x05078
 171 
 172 /* NVM Registers */
 173 #define IXGBE_EEC               0x10010
 174 #define IXGBE_EEC_X540          IXGBE_EEC
 175 #define IXGBE_EEC_X550          IXGBE_EEC
 176 #define IXGBE_EEC_X550EM_x      IXGBE_EEC
 177 #define IXGBE_EEC_BY_MAC(_hw)   IXGBE_EEC
 178 
 179 #define IXGBE_EERD              0x10014
 180 #define IXGBE_EEWR              0x10018
 181 
 182 #define IXGBE_FLA               0x1001C
 183 #define IXGBE_FLA_X540          IXGBE_FLA
 184 #define IXGBE_FLA_X550          IXGBE_FLA
 185 #define IXGBE_FLA_X550EM_x      IXGBE_FLA
 186 #define IXGBE_FLA_BY_MAC(_hw)   IXGBE_FLA
 187 
 188 #define IXGBE_EEMNGCTL  0x10110
 189 #define IXGBE_EEMNGDATA 0x10114
 190 #define IXGBE_FLMNGCTL  0x10118
 191 #define IXGBE_FLMNGDATA 0x1011C
 192 #define IXGBE_FLMNGCNT  0x10120
 193 #define IXGBE_FLOP      0x1013C
 194 
 195 #define IXGBE_GRC               0x10200
 196 #define IXGBE_GRC_X540          IXGBE_GRC
 197 #define IXGBE_GRC_X550          IXGBE_GRC
 198 #define IXGBE_GRC_X550EM_x      IXGBE_GRC
 199 #define IXGBE_GRC_BY_MAC(_hw)   IXGBE_GRC
 200 
 201 #define IXGBE_SRAMREL           0x10210
 202 #define IXGBE_SRAMREL_X540      IXGBE_SRAMREL
 203 #define IXGBE_SRAMREL_X550      IXGBE_SRAMREL
 204 #define IXGBE_SRAMREL_X550EM_x  IXGBE_SRAMREL
 205 #define IXGBE_SRAMREL_BY_MAC(_hw)       IXGBE_SRAMREL
 206 
 207 #define IXGBE_PHYDBG    0x10218
 208 
 209 /* General Receive Control */
 210 #define IXGBE_GRC_MNG   0x00000001 /* Manageability Enable */
 211 #define IXGBE_GRC_APME  0x00000002 /* APM enabled in EEPROM */
 212 
 213 #define IXGBE_VPDDIAG0  0x10204
 214 #define IXGBE_VPDDIAG1  0x10208
 215 
 216 /* I2CCTL Bit Masks */
 217 #define IXGBE_I2C_CLK_IN                0x00000001
 218 #define IXGBE_I2C_CLK_IN_X540           IXGBE_I2C_CLK_IN
 219 #define IXGBE_I2C_CLK_IN_X550           0x00004000
 220 #define IXGBE_I2C_CLK_IN_X550EM_x       IXGBE_I2C_CLK_IN_X550
 221 #define IXGBE_I2C_CLK_IN_BY_MAC(_hw)    IXGBE_BY_MAC((_hw), I2C_CLK_IN)
 222 
 223 #define IXGBE_I2C_CLK_OUT               0x00000002
 224 #define IXGBE_I2C_CLK_OUT_X540          IXGBE_I2C_CLK_OUT
 225 #define IXGBE_I2C_CLK_OUT_X550          0x00000200
 226 #define IXGBE_I2C_CLK_OUT_X550EM_x      IXGBE_I2C_CLK_OUT_X550
 227 #define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)   IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
 228 
 229 #define IXGBE_I2C_DATA_IN               0x00000004
 230 #define IXGBE_I2C_DATA_IN_X540          IXGBE_I2C_DATA_IN
 231 #define IXGBE_I2C_DATA_IN_X550          0x00001000
 232 #define IXGBE_I2C_DATA_IN_X550EM_x      IXGBE_I2C_DATA_IN_X550
 233 #define IXGBE_I2C_DATA_IN_BY_MAC(_hw)   IXGBE_BY_MAC((_hw), I2C_DATA_IN)
 234 
 235 #define IXGBE_I2C_DATA_OUT              0x00000008
 236 #define IXGBE_I2C_DATA_OUT_X540         IXGBE_I2C_DATA_OUT
 237 #define IXGBE_I2C_DATA_OUT_X550         0x00000400
 238 #define IXGBE_I2C_DATA_OUT_X550EM_x     IXGBE_I2C_DATA_OUT_X550
 239 #define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)  IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
 240 
 241 #define IXGBE_I2C_DATA_OE_N_EN          0
 242 #define IXGBE_I2C_DATA_OE_N_EN_X540     IXGBE_I2C_DATA_OE_N_EN
 243 #define IXGBE_I2C_DATA_OE_N_EN_X550     0x00000800
 244 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550
 245 #define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
 246 
 247 #define IXGBE_I2C_BB_EN                 0
 248 #define IXGBE_I2C_BB_EN_X540            IXGBE_I2C_BB_EN
 249 #define IXGBE_I2C_BB_EN_X550            0x00000100
 250 #define IXGBE_I2C_BB_EN_X550EM_x        IXGBE_I2C_BB_EN_X550
 251 
 252 #define IXGBE_I2C_BB_EN_BY_MAC(_hw)     IXGBE_BY_MAC((_hw), I2C_BB_EN)
 253 
 254 #define IXGBE_I2C_CLK_OE_N_EN           0
 255 #define IXGBE_I2C_CLK_OE_N_EN_X540      IXGBE_I2C_CLK_OE_N_EN
 256 #define IXGBE_I2C_CLK_OE_N_EN_X550      0x00002000
 257 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x  IXGBE_I2C_CLK_OE_N_EN_X550
 258 #define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
 259 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT      500
 260 
 261 
 262 /* Interrupt Registers */
 263 #define IXGBE_EICR              0x00800
 264 #define IXGBE_EICS              0x00808
 265 #define IXGBE_EIMS              0x00880
 266 #define IXGBE_EIMC              0x00888
 267 #define IXGBE_EIAC              0x00810
 268 #define IXGBE_EIAM              0x00890
 269 #define IXGBE_EICS_EX(_i)       (0x00A90 + (_i) * 4)
 270 #define IXGBE_EIMS_EX(_i)       (0x00AA0 + (_i) * 4)
 271 #define IXGBE_EIMC_EX(_i)       (0x00AB0 + (_i) * 4)
 272 #define IXGBE_EIAM_EX(_i)       (0x00AD0 + (_i) * 4)
 273 /* 82599 EITR is only 12 bits, with the lower 3 always zero */
 274 /*
 275  * 82598 EITR is 16 bits but set the limits based on the max
 276  * supported by all ixgbe hardware
 277  */
 278 #define IXGBE_MAX_INT_RATE      488281


 328 #define IXGBE_STARCTRL  0x03024
 329 /*
 330  * Split and Replication Receive Control Registers
 331  * 00-15 : 0x02100 + n*4
 332  * 16-64 : 0x01014 + n*0x40
 333  * 64-127: 0x0D014 + (n-64)*0x40
 334  */
 335 #define IXGBE_SRRCTL(_i)        (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
 336                                  (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
 337                                  (0x0D014 + (((_i) - 64) * 0x40))))
 338 /*
 339  * Rx DCA Control Register:
 340  * 00-15 : 0x02200 + n*4
 341  * 16-64 : 0x0100C + n*0x40
 342  * 64-127: 0x0D00C + (n-64)*0x40
 343  */
 344 #define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
 345                                  (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
 346                                  (0x0D00C + (((_i) - 64) * 0x40))))
 347 #define IXGBE_RDRXCTL           0x02F00

 348 /* 8 of these 0x03C00 - 0x03C1C */
 349 #define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
 350 #define IXGBE_RXCTRL            0x03000
 351 #define IXGBE_DROPEN            0x03D04
 352 #define IXGBE_RXPBSIZE_SHIFT    10
 353 #define IXGBE_RXPBSIZE_MASK     0x000FFC00
 354 
 355 /* Receive Registers */
 356 #define IXGBE_RXCSUM            0x05000
 357 #define IXGBE_RFCTL             0x05008
 358 #define IXGBE_DRECCCTL          0x02F08
 359 #define IXGBE_DRECCCTL_DISABLE  0
 360 #define IXGBE_DRECCCTL2         0x02F8C
 361 
 362 /* Multicast Table Array - 128 entries */
 363 #define IXGBE_MTA(_i)           (0x05200 + ((_i) * 4))
 364 #define IXGBE_RAL(_i)           (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
 365                                  (0x0A200 + ((_i) * 8)))
 366 #define IXGBE_RAH(_i)           (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
 367                                  (0x0A204 + ((_i) * 8)))
 368 #define IXGBE_MPSAR_LO(_i)      (0x0A600 + ((_i) * 8))
 369 #define IXGBE_MPSAR_HI(_i)      (0x0A604 + ((_i) * 8))
 370 /* Packet split receive type */
 371 #define IXGBE_PSRTYPE(_i)       (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
 372                                  (0x0EA00 + ((_i) * 4)))
 373 /* array of 4096 1-bit vlan filters */
 374 #define IXGBE_VFTA(_i)          (0x0A000 + ((_i) * 4))
 375 /*array of 4096 4-bit vlan vmdq indices */
 376 #define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
 377 #define IXGBE_FCTRL             0x05080
 378 #define IXGBE_VLNCTRL           0x05088
 379 #define IXGBE_MCSTCTRL          0x05090
 380 #define IXGBE_MRQC              0x05818
 381 #define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
 382 #define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
 383 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
 384 #define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
 385 #define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
 386 #define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
 387 #define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
 388 #define IXGBE_RQTC      0x0EC70
 389 #define IXGBE_MTQC      0x08120
 390 #define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
 391 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
 392 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
 393 #define IXGBE_PFFLPL            0x050B0
 394 #define IXGBE_PFFLPH            0x050B4
 395 #define IXGBE_VT_CTL            0x051B0
 396 #define IXGBE_PFMAILBOX(_i)     (0x04B00 + (4 * (_i))) /* 64 total */
 397 /* 64 Mailboxes, 16 DW each */
 398 #define IXGBE_PFMBMEM(_i)       (0x13000 + (64 * (_i)))
 399 #define IXGBE_PFMBICR(_i)       (0x00710 + (4 * (_i))) /* 4 total */
 400 #define IXGBE_PFMBIMR(_i)       (0x00720 + (4 * (_i))) /* 4 total */
 401 #define IXGBE_VFRE(_i)          (0x051E0 + ((_i) * 4))
 402 #define IXGBE_VFTE(_i)          (0x08110 + ((_i) * 4))
 403 #define IXGBE_VMECM(_i)         (0x08790 + ((_i) * 4))
 404 #define IXGBE_QDE               0x2F04
 405 #define IXGBE_VMTXSW(_i)        (0x05180 + ((_i) * 4)) /* 2 total */
 406 #define IXGBE_VMOLR(_i)         (0x0F000 + ((_i) * 4)) /* 64 total */
 407 #define IXGBE_UTA(_i)           (0x0F400 + ((_i) * 4))
 408 #define IXGBE_MRCTL(_i)         (0x0F600 + ((_i) * 4))
 409 #define IXGBE_VMRVLAN(_i)       (0x0F610 + ((_i) * 4))
 410 #define IXGBE_VMRVM(_i)         (0x0F630 + ((_i) * 4))
 411 #define IXGBE_LVMMC_RX          0x2FA8
 412 #define IXGBE_LVMMC_TX          0x8108
 413 #define IXGBE_LMVM_RX           0x2FA4
 414 #define IXGBE_LMVM_TX           0x8124
 415 #define IXGBE_WQBR_RX(_i)       (0x2FB0 + ((_i) * 4)) /* 4 total */
 416 #define IXGBE_WQBR_TX(_i)       (0x8130 + ((_i) * 4)) /* 4 total */
 417 #define IXGBE_L34T_IMIR(_i)     (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
 418 #define IXGBE_RXFECCERR0        0x051B8
 419 #define IXGBE_LLITHRESH         0x0EC90
 420 #define IXGBE_IMIR(_i)          (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
 421 #define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
 422 #define IXGBE_IMIRVP            0x05AC0
 423 #define IXGBE_VMD_CTL           0x0581C
 424 #define IXGBE_RETA(_i)          (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
 425 #define IXGBE_ERETA(_i)         (0x0EE80 + ((_i) * 4))  /* 96 of these (0-95) */
 426 #define IXGBE_RSSRK(_i)         (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 427 
 428 /* Registers for setting up RSS on X550 with SRIOV
 429  * _p - pool number (0..63)
 430  * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
 431  */
 432 #define IXGBE_PFVFMRQC(_p)      (0x03400 + ((_p) * 4))
 433 #define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40))
 434 #define IXGBE_PFVFRETA(_i, _p)  (0x019000 + ((_i) * 4) + ((_p) * 0x40))
 435 
 436 /* Flow Director registers */
 437 #define IXGBE_FDIRCTRL  0x0EE00
 438 #define IXGBE_FDIRHKEY  0x0EE68
 439 #define IXGBE_FDIRSKEY  0x0EE6C
 440 #define IXGBE_FDIRDIP4M 0x0EE3C
 441 #define IXGBE_FDIRSIP4M 0x0EE40
 442 #define IXGBE_FDIRTCPM  0x0EE44
 443 #define IXGBE_FDIRUDPM  0x0EE48
 444 #define IXGBE_FDIRSCTPM 0x0EE78
 445 #define IXGBE_FDIRIP6M  0x0EE74
 446 #define IXGBE_FDIRM     0x0EE70
 447 
 448 /* Flow Director Stats registers */
 449 #define IXGBE_FDIRFREE  0x0EE38
 450 #define IXGBE_FDIRLEN   0x0EE4C
 451 #define IXGBE_FDIRUSTAT 0x0EE50
 452 #define IXGBE_FDIRFSTAT 0x0EE54
 453 #define IXGBE_FDIRMATCH 0x0EE58
 454 #define IXGBE_FDIRMISS  0x0EE5C
 455 
 456 /* Flow Director Programming registers */
 457 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
 458 #define IXGBE_FDIRIPSA  0x0EE18
 459 #define IXGBE_FDIRIPDA  0x0EE1C
 460 #define IXGBE_FDIRPORT  0x0EE20
 461 #define IXGBE_FDIRVLAN  0x0EE24
 462 #define IXGBE_FDIRHASH  0x0EE28
 463 #define IXGBE_FDIRCMD   0x0EE2C
 464 


 468 #define IXGBE_TDLEN(_i)         (0x06008 + ((_i) * 0x40))
 469 #define IXGBE_TDH(_i)           (0x06010 + ((_i) * 0x40))
 470 #define IXGBE_TDT(_i)           (0x06018 + ((_i) * 0x40))
 471 #define IXGBE_TXDCTL(_i)        (0x06028 + ((_i) * 0x40))
 472 #define IXGBE_TDWBAL(_i)        (0x06038 + ((_i) * 0x40))
 473 #define IXGBE_TDWBAH(_i)        (0x0603C + ((_i) * 0x40))
 474 #define IXGBE_DTXCTL            0x07E00
 475 
 476 #define IXGBE_DMATXCTL          0x04A80
 477 #define IXGBE_PFVFSPOOF(_i)     (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
 478 #define IXGBE_PFDTXGSWC         0x08220
 479 #define IXGBE_DTXMXSZRQ         0x08100
 480 #define IXGBE_DTXTCPFLGL        0x04A88
 481 #define IXGBE_DTXTCPFLGH        0x04A8C
 482 #define IXGBE_LBDRPEN           0x0CA00
 483 #define IXGBE_TXPBTHRESH(_i)    (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
 484 
 485 #define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
 486 #define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
 487 #define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
 488 #define IXGBE_DMATXCTL_MDP_EN   0x20 /* Bit 5 */
 489 #define IXGBE_DMATXCTL_MBINTEN  0x40 /* Bit 6 */
 490 #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 491 
 492 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
 493 
 494 /* Anti-spoofing defines */
 495 #define IXGBE_SPOOF_MACAS_MASK          0xFF
 496 #define IXGBE_SPOOF_VLANAS_MASK         0xFF00
 497 #define IXGBE_SPOOF_VLANAS_SHIFT        8
 498 #define IXGBE_SPOOF_ETHERTYPEAS         0xFF000000
 499 #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT   16
 500 #define IXGBE_PFVFSPOOF_REG_COUNT       8
 501 /* 16 of these (0-15) */
 502 #define IXGBE_DCA_TXCTRL(_i)            (0x07200 + ((_i) * 4))
 503 /* Tx DCA Control register : 128 of these (0-127) */
 504 #define IXGBE_DCA_TXCTRL_82599(_i)      (0x0600C + ((_i) * 0x40))
 505 #define IXGBE_TIPG                      0x0CB00
 506 #define IXGBE_TXPBSIZE(_i)              (0x0CC00 + ((_i) * 4)) /* 8 of these */
 507 #define IXGBE_MNGTXMAP                  0x0CD10
 508 #define IXGBE_TIPG_FIBER_DEFAULT        3
 509 #define IXGBE_TXPBSIZE_SHIFT            10
 510 
 511 /* Wake up registers */
 512 #define IXGBE_WUC       0x05800
 513 #define IXGBE_WUFC      0x05808
 514 #define IXGBE_WUS       0x05810
 515 #define IXGBE_IPAV      0x05838
 516 #define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
 517 #define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
 518 
 519 #define IXGBE_WUPL      0x05900
 520 #define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
 521 #define IXGBE_PROXYS    0x05F60 /* Proxying Status Register */
 522 #define IXGBE_PROXYFC   0x05F64 /* Proxying Filter Control Register */
 523 #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */
 524 
 525 #define IXGBE_FHFT(_n)  (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
 526 /* Ext Flexible Host Filter Table */
 527 #define IXGBE_FHFT_EXT(_n)      (0x09800 + ((_n) * 0x100))
 528 #define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100))
 529 
 530 /* Four Flexible Filters are supported */
 531 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4
 532 
 533 /* Six Flexible Filters are supported */
 534 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6       6
 535 /* Eight Flexible Filters are supported */
 536 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8       8
 537 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
 538 
 539 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
 540 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX          128
 541 #define IXGBE_FHFT_LENGTH_OFFSET                0xFC  /* Length byte in FHFT */
 542 #define IXGBE_FHFT_LENGTH_MASK                  0x0FF /* Length in lower byte */
 543 
 544 /* Definitions for power management and wakeup registers */
 545 /* Wake Up Control */
 546 #define IXGBE_WUC_PME_EN        0x00000002 /* PME Enable */
 547 #define IXGBE_WUC_PME_STATUS    0x00000004 /* PME Status */
 548 #define IXGBE_WUC_WKEN          0x00000010 /* Enable PE_WAKE_N pin assertion  */
 549 
 550 /* Wake Up Filter Control */
 551 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
 552 #define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
 553 #define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
 554 #define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
 555 #define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
 556 #define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
 557 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
 558 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 559 #define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
 560 
 561 #define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
 562 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
 563 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
 564 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
 565 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
 566 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
 567 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
 568 #define IXGBE_WUFC_FLX_FILTERS          0x000F0000 /* Mask for 4 flex filters */
 569 #define IXGBE_WUFC_FLX_FILTERS_6        0x003F0000 /* Mask for 6 flex filters */
 570 #define IXGBE_WUFC_FLX_FILTERS_8        0x00FF0000 /* Mask for 8 flex filters */
 571 #define IXGBE_WUFC_FW_RST_WK    0x80000000 /* Ena wake on FW reset assertion */
 572 /* Mask for Ext. flex filters */
 573 #define IXGBE_WUFC_EXT_FLX_FILTERS      0x00300000
 574 #define IXGBE_WUFC_ALL_FILTERS          0x000F00FF /* Mask all 4 flex filters */
 575 #define IXGBE_WUFC_ALL_FILTERS_6        0x003F00FF /* Mask all 6 flex filters */
 576 #define IXGBE_WUFC_ALL_FILTERS_8        0x00FF00FF /* Mask all 8 flex filters */
 577 #define IXGBE_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
 578 
 579 /* Wake Up Status */
 580 #define IXGBE_WUS_LNKC          IXGBE_WUFC_LNKC
 581 #define IXGBE_WUS_MAG           IXGBE_WUFC_MAG
 582 #define IXGBE_WUS_EX            IXGBE_WUFC_EX
 583 #define IXGBE_WUS_MC            IXGBE_WUFC_MC
 584 #define IXGBE_WUS_BC            IXGBE_WUFC_BC
 585 #define IXGBE_WUS_ARP           IXGBE_WUFC_ARP
 586 #define IXGBE_WUS_IPV4          IXGBE_WUFC_IPV4
 587 #define IXGBE_WUS_IPV6          IXGBE_WUFC_IPV6
 588 #define IXGBE_WUS_MNG           IXGBE_WUFC_MNG
 589 #define IXGBE_WUS_FLX0          IXGBE_WUFC_FLX0
 590 #define IXGBE_WUS_FLX1          IXGBE_WUFC_FLX1
 591 #define IXGBE_WUS_FLX2          IXGBE_WUFC_FLX2
 592 #define IXGBE_WUS_FLX3          IXGBE_WUFC_FLX3
 593 #define IXGBE_WUS_FLX4          IXGBE_WUFC_FLX4
 594 #define IXGBE_WUS_FLX5          IXGBE_WUFC_FLX5
 595 #define IXGBE_WUS_FLX_FILTERS   IXGBE_WUFC_FLX_FILTERS
 596 #define IXGBE_WUS_FW_RST_WK     IXGBE_WUFC_FW_RST_WK
 597 /* Proxy Status */
 598 #define IXGBE_PROXYS_EX         0x00000004 /* Exact packet received */
 599 #define IXGBE_PROXYS_ARP_DIR    0x00000020 /* ARP w/filter match received */
 600 #define IXGBE_PROXYS_NS         0x00000200 /* IPV6 NS received */
 601 #define IXGBE_PROXYS_NS_DIR     0x00000400 /* IPV6 NS w/DA match received */
 602 #define IXGBE_PROXYS_ARP        0x00000800 /* ARP request packet received */
 603 #define IXGBE_PROXYS_MLD        0x00001000 /* IPv6 MLD packet received */
 604 
 605 /* Proxying Filter Control */
 606 #define IXGBE_PROXYFC_ENABLE    0x00000001 /* Port Proxying Enable */
 607 #define IXGBE_PROXYFC_EX        0x00000004 /* Directed Exact Proxy Enable */
 608 #define IXGBE_PROXYFC_ARP_DIR   0x00000020 /* Directed ARP Proxy Enable */
 609 #define IXGBE_PROXYFC_NS        0x00000200 /* IPv6 Neighbor Solicitation */
 610 #define IXGBE_PROXYFC_ARP       0x00000800 /* ARP Request Proxy Enable */
 611 #define IXGBE_PROXYFC_MLD       0x00000800 /* IPv6 MLD Proxy Enable */
 612 #define IXGBE_PROXYFC_NO_TCO    0x00008000 /* Ignore TCO packets */
 613 
 614 #define IXGBE_WUPL_LENGTH_MASK  0xFFFF
 615 
 616 /* DCB registers */
 617 #define IXGBE_DCB_MAX_TRAFFIC_CLASS     8
 618 #define IXGBE_RMCS              0x03D00
 619 #define IXGBE_DPMCS             0x07F40
 620 #define IXGBE_PDPMCS            0x0CD00
 621 #define IXGBE_RUPPBMR           0x050A0
 622 #define IXGBE_RT2CR(_i)         (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
 623 #define IXGBE_RT2SR(_i)         (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
 624 #define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
 625 #define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
 626 #define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 627 #define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 628 
 629 /* Power Management */
 630 /* DMA Coalescing configuration */
 631 struct ixgbe_dmac_config {
 632         u16     watchdog_timer; /* usec units */
 633         bool    fcoe_en;
 634         u32     link_speed;
 635         u8      fcoe_tc;
 636         u8      num_tcs;
 637 };
 638 
 639 /*
 640  * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed.
 641  * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 ==
 642  * 87500 bytes [85KB]
 643  */
 644 #define IXGBE_DMACRXT_10G               0x55
 645 #define IXGBE_DMACRXT_1G                0x09
 646 #define IXGBE_DMACRXT_100M              0x01
 647 
 648 /* DMA Coalescing registers */
 649 #define IXGBE_DMCMNGTH                  0x15F20 /* Management Threshold */
 650 #define IXGBE_DMACR                     0x02400 /* Control register */
 651 #define IXGBE_DMCTH(_i)                 (0x03300 + ((_i) * 4)) /* 8 of these */
 652 #define IXGBE_DMCTLX                    0x02404 /* Time to Lx request */
 653 /* DMA Coalescing register fields */
 654 #define IXGBE_DMCMNGTH_DMCMNGTH_MASK    0x000FFFF0 /* Mng Threshold mask */
 655 #define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT   4 /* Management Threshold shift */
 656 #define IXGBE_DMACR_DMACWT_MASK         0x0000FFFF /* Watchdog Timer mask */
 657 #define IXGBE_DMACR_HIGH_PRI_TC_MASK    0x00FF0000
 658 #define IXGBE_DMACR_HIGH_PRI_TC_SHIFT   16
 659 #define IXGBE_DMACR_EN_MNG_IND          0x10000000 /* Enable Mng Indications */
 660 #define IXGBE_DMACR_LX_COAL_IND         0x40000000 /* Lx Coalescing indicate */
 661 #define IXGBE_DMACR_DMAC_EN             0x80000000 /* DMA Coalescing Enable */
 662 #define IXGBE_DMCTH_DMACRXT_MASK        0x000001FF /* Receive Threshold mask */
 663 #define IXGBE_DMCTLX_TTLX_MASK          0x00000FFF /* Time to Lx request mask */
 664 
 665 /* EEE registers */
 666 #define IXGBE_EEER                      0x043A0 /* EEE register */
 667 #define IXGBE_EEE_STAT                  0x04398 /* EEE Status */
 668 #define IXGBE_EEE_SU                    0x04380 /* EEE Set up */
 669 #define IXGBE_EEE_SU_TEEE_DLY_SHIFT     26
 670 #define IXGBE_TLPIC                     0x041F4 /* EEE Tx LPI count */
 671 #define IXGBE_RLPIC                     0x041F8 /* EEE Rx LPI count */
 672 
 673 /* EEE register fields */
 674 #define IXGBE_EEER_TX_LPI_EN            0x00010000 /* Enable EEE LPI TX path */
 675 #define IXGBE_EEER_RX_LPI_EN            0x00020000 /* Enable EEE LPI RX path */
 676 #define IXGBE_EEE_STAT_NEG              0x20000000 /* EEE support neg on link */
 677 #define IXGBE_EEE_RX_LPI_STATUS         0x40000000 /* RX Link in LPI status */
 678 #define IXGBE_EEE_TX_LPI_STATUS         0x80000000 /* TX Link in LPI status */
 679 
 680 
 681 
 682 /* Security Control Registers */
 683 #define IXGBE_SECTXCTRL         0x08800
 684 #define IXGBE_SECTXSTAT         0x08804
 685 #define IXGBE_SECTXBUFFAF       0x08808
 686 #define IXGBE_SECTXMINIFG       0x08810
 687 #define IXGBE_SECRXCTRL         0x08D00
 688 #define IXGBE_SECRXSTAT         0x08D04
 689 
 690 /* Security Bit Fields and Masks */
 691 #define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
 692 #define IXGBE_SECTXCTRL_TX_DIS          0x00000002
 693 #define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
 694 
 695 #define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
 696 #define IXGBE_SECTXSTAT_ECC_TXERR       0x00000002
 697 
 698 #define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
 699 #define IXGBE_SECRXCTRL_RX_DIS          0x00000002
 700 
 701 #define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001


 799 #define IXGBE_RTTBCNRC                  0x04984
 800 #define IXGBE_RTTBCNRC_RS_ENA           0x80000000
 801 #define IXGBE_RTTBCNRC_RF_DEC_MASK      0x00003FFF
 802 #define IXGBE_RTTBCNRC_RF_INT_SHIFT     14
 803 #define IXGBE_RTTBCNRC_RF_INT_MASK \
 804         (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
 805 #define IXGBE_RTTBCNRM  0x04980
 806 
 807 /* BCN (for DCB) Registers */
 808 #define IXGBE_RTTBCNRS  0x04988
 809 #define IXGBE_RTTBCNCR  0x08B00
 810 #define IXGBE_RTTBCNACH 0x08B04
 811 #define IXGBE_RTTBCNACL 0x08B08
 812 #define IXGBE_RTTBCNTG  0x04A90
 813 #define IXGBE_RTTBCNIDX 0x08B0C
 814 #define IXGBE_RTTBCNCP  0x08B10
 815 #define IXGBE_RTFRTIMER 0x08B14
 816 #define IXGBE_RTTBCNRTT 0x05150
 817 #define IXGBE_RTTBCNRD  0x0498C
 818 
 819 
 820 /* FCoE DMA Context Registers */
 821 /* FCoE Direct DMA Context */
 822 #define IXGBE_FCDDC(_i, _j)     (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
 823 #define IXGBE_FCPTRL            0x02410 /* FC User Desc. PTR Low */
 824 #define IXGBE_FCPTRH            0x02414 /* FC USer Desc. PTR High */
 825 #define IXGBE_FCBUFF            0x02418 /* FC Buffer Control */
 826 #define IXGBE_FCDMARW           0x02420 /* FC Receive DMA RW */


 827 #define IXGBE_FCBUFF_VALID      (1 << 0)   /* DMA Context Valid */
 828 #define IXGBE_FCBUFF_BUFFSIZE   (3 << 3)   /* User Buffer Size */
 829 #define IXGBE_FCBUFF_WRCONTX    (1 << 7)   /* 0: Initiator, 1: Target */
 830 #define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
 831 #define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
 832 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT     3
 833 #define IXGBE_FCBUFF_BUFFCNT_SHIFT      8
 834 #define IXGBE_FCBUFF_OFFSET_SHIFT       16
 835 #define IXGBE_FCDMARW_WE                (1 << 14)   /* Write enable */
 836 #define IXGBE_FCDMARW_RE                (1 << 15)   /* Read enable */
 837 #define IXGBE_FCDMARW_FCOESEL           0x000001ff  /* FC X_ID: 11 bits */
 838 #define IXGBE_FCDMARW_LASTSIZE          0xffff0000  /* Last User Buffer Size */
 839 #define IXGBE_FCDMARW_LASTSIZE_SHIFT    16
 840 /* FCoE SOF/EOF */
 841 #define IXGBE_TEOFF             0x04A94 /* Tx FC EOF */
 842 #define IXGBE_TSOFF             0x04A98 /* Tx FC SOF */
 843 #define IXGBE_REOFF             0x05158 /* Rx FC EOF */
 844 #define IXGBE_RSOFF             0x051F8 /* Rx FC SOF */
 845 /* FCoE Filter Context Registers */
 846 #define IXGBE_FCD_ID            0x05114 /* FCoE D_ID */
 847 #define IXGBE_FCSMAC            0x0510C /* FCoE Source MAC */
 848 #define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT   16
 849 /* FCoE Direct Filter Context */
 850 #define IXGBE_FCDFC(_i, _j)     (0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
 851 #define IXGBE_FCDFCD(_i)        (0x30000 + ((_i) * 0x4))
 852 #define IXGBE_FCFLT             0x05108 /* FC FLT Context */
 853 #define IXGBE_FCFLTRW           0x05110 /* FC Filter RW Control */
 854 #define IXGBE_FCPARAM           0x051d8 /* FC Offset Parameter */
 855 #define IXGBE_FCFLT_VALID       (1 << 0)   /* Filter Context Valid */
 856 #define IXGBE_FCFLT_FIRST       (1 << 1)   /* Filter First */
 857 #define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
 858 #define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
 859 #define IXGBE_FCFLTRW_RVALDT    (1 << 13)  /* Fast Re-Validation */
 860 #define IXGBE_FCFLTRW_WE        (1 << 14)  /* Write Enable */
 861 #define IXGBE_FCFLTRW_RE        (1 << 15)  /* Read Enable */
 862 /* FCoE Receive Control */
 863 #define IXGBE_FCRXCTRL          0x05100 /* FC Receive Control */
 864 #define IXGBE_FCRXCTRL_FCOELLI  (1 << 0)   /* Low latency interrupt */
 865 #define IXGBE_FCRXCTRL_SAVBAD   (1 << 1)   /* Save Bad Frames */
 866 #define IXGBE_FCRXCTRL_FRSTRDH  (1 << 2)   /* EN 1st Read Header */
 867 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)   /* EN Last Header in Seq */
 868 #define IXGBE_FCRXCTRL_ALLH     (1 << 4)   /* EN All Headers */
 869 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)   /* EN 1st Seq. Header */
 870 #define IXGBE_FCRXCTRL_ICRC     (1 << 6)   /* Ignore Bad FC CRC */
 871 #define IXGBE_FCRXCTRL_FCCRCBO  (1 << 7)   /* FC CRC Byte Ordering */
 872 #define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
 873 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT    8
 874 /* FCoE Redirection */
 875 #define IXGBE_FCRECTL           0x0ED00 /* FC Redirection Control */
 876 #define IXGBE_FCRETA0           0x0ED10 /* FC Redirection Table 0 */
 877 #define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
 878 #define IXGBE_FCRECTL_ENA       0x1 /* FCoE Redir Table Enable */
 879 #define IXGBE_FCRETASEL_ENA     0x2 /* FCoE FCRETASEL bit */
 880 #define IXGBE_FCRETA_SIZE       8 /* Max entries in FCRETA */
 881 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
 882 #define IXGBE_FCRETA_SIZE_X550  32 /* Max entries in FCRETA */
 883 /* Higher 7 bits for the queue index */
 884 #define IXGBE_FCRETA_ENTRY_HIGH_MASK    0x007F0000
 885 #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT   16
 886 
 887 /* Stats registers */
 888 #define IXGBE_CRCERRS   0x04000
 889 #define IXGBE_ILLERRC   0x04004
 890 #define IXGBE_ERRBC     0x04008
 891 #define IXGBE_MSPDC     0x04010
 892 #define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
 893 #define IXGBE_MLFC      0x04034
 894 #define IXGBE_MRFC      0x04038
 895 #define IXGBE_RLEC      0x04040
 896 #define IXGBE_LXONTXC   0x03F60
 897 #define IXGBE_LXONRXC   0x0CF60
 898 #define IXGBE_LXOFFTXC  0x03F68
 899 #define IXGBE_LXOFFRXC  0x0CF68
 900 #define IXGBE_LXONRXCNT         0x041A4
 901 #define IXGBE_LXOFFRXCNT        0x041A8
 902 #define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
 903 #define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
 904 #define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
 905 #define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/


 964 #define IXGBE_FCOEDWRC          0x0242C /* Number of FCoE DWords Received */
 965 #define IXGBE_FCOEPTC           0x08784 /* Number of FCoE Packets Transmitted */
 966 #define IXGBE_FCOEDWTC          0x08788 /* Number of FCoE DWords Transmitted */
 967 #define IXGBE_FCCRC_CNT_MASK    0x0000FFFF /* CRC_CNT: bit 0 - 15 */
 968 #define IXGBE_FCLAST_CNT_MASK   0x0000FFFF /* Last_CNT: bit 0 - 15 */
 969 #define IXGBE_O2BGPTC           0x041C4
 970 #define IXGBE_O2BSPC            0x087B0
 971 #define IXGBE_B2OSPC            0x041C0
 972 #define IXGBE_B2OGPRC           0x02F90
 973 #define IXGBE_BUPRC             0x04180
 974 #define IXGBE_BMPRC             0x04184
 975 #define IXGBE_BBPRC             0x04188
 976 #define IXGBE_BUPTC             0x0418C
 977 #define IXGBE_BMPTC             0x04190
 978 #define IXGBE_BBPTC             0x04194
 979 #define IXGBE_BCRCERRS          0x04198
 980 #define IXGBE_BXONRXC           0x0419C
 981 #define IXGBE_BXOFFRXC          0x041E0
 982 #define IXGBE_BXONTXC           0x041E4
 983 #define IXGBE_BXOFFTXC          0x041E8





 984 
 985 /* Management */
 986 #define IXGBE_MAVTV(_i)         (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
 987 #define IXGBE_MFUTP(_i)         (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
 988 #define IXGBE_MANC              0x05820
 989 #define IXGBE_MFVAL             0x05824
 990 #define IXGBE_MANC2H            0x05860
 991 #define IXGBE_MDEF(_i)          (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
 992 #define IXGBE_MIPAF             0x058B0
 993 #define IXGBE_MMAL(_i)          (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
 994 #define IXGBE_MMAH(_i)          (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
 995 #define IXGBE_FTFT              0x09400 /* 0x9400-0x97FC */
 996 #define IXGBE_METF(_i)          (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
 997 #define IXGBE_MDEF_EXT(_i)      (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
 998 #define IXGBE_LSWFW             0x15014
 999 #define IXGBE_BMCIP(_i)         (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
1000 #define IXGBE_BMCIPVAL          0x05060
1001 #define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
1002 #define IXGBE_BMCIP_IPADDR_VALID        0x00000002
1003 
1004 /* Management Bit Fields and Masks */
1005 #define IXGBE_MANC_MPROXYE      0x40000000 /* Management Proxy Enable */
1006 #define IXGBE_MANC_RCV_TCO_EN   0x00020000 /* Rcv TCO packet enable */
1007 #define IXGBE_MANC_EN_BMC2OS    0x10000000 /* Ena BMC2OS and OS2BMC traffic */
1008 #define IXGBE_MANC_EN_BMC2OS_SHIFT      28
1009 
1010 /* Firmware Semaphore Register */
1011 #define IXGBE_FWSM_MODE_MASK    0xE
1012 #define IXGBE_FWSM_TS_ENABLED   0x1
1013 #define IXGBE_FWSM_FW_MODE_PT   0x4
1014 
1015 /* ARC Subsystem registers */
1016 #define IXGBE_HICR              0x15F00
1017 #define IXGBE_FWSTS             0x15F0C
1018 #define IXGBE_HSMC0R            0x15F04
1019 #define IXGBE_HSMC1R            0x15F08
1020 #define IXGBE_SWSR              0x15F10
1021 #define IXGBE_HFDR              0x15FE8
1022 #define IXGBE_FLEX_MNG          0x15800 /* 0x15800 - 0x15EFC */
1023 
1024 #define IXGBE_HICR_EN           0x01  /* Enable bit - RO */
1025 /* Driver sets this bit when done to put command in RAM */
1026 #define IXGBE_HICR_C            0x02
1027 #define IXGBE_HICR_SV           0x04  /* Status Validity */
1028 #define IXGBE_HICR_FW_RESET_ENABLE      0x40
1029 #define IXGBE_HICR_FW_RESET     0x80
1030 
1031 /* PCI-E registers */
1032 #define IXGBE_GCR               0x11000
1033 #define IXGBE_GTV               0x11004
1034 #define IXGBE_FUNCTAG           0x11008
1035 #define IXGBE_GLT               0x1100C
1036 #define IXGBE_PCIEPIPEADR       0x11004
1037 #define IXGBE_PCIEPIPEDAT       0x11008
1038 #define IXGBE_GSCL_1            0x11010
1039 #define IXGBE_GSCL_2            0x11014
1040 #define IXGBE_GSCL_3            0x11018
1041 #define IXGBE_GSCL_4            0x1101C
1042 #define IXGBE_GSCN_0            0x11020
1043 #define IXGBE_GSCN_1            0x11024
1044 #define IXGBE_GSCN_2            0x11028
1045 #define IXGBE_GSCN_3            0x1102C
1046 #define IXGBE_FACTPS            0x10150
1047 #define IXGBE_FACTPS_X540       IXGBE_FACTPS
1048 #define IXGBE_FACTPS_X550       IXGBE_FACTPS
1049 #define IXGBE_FACTPS_X550EM_x   IXGBE_FACTPS
1050 #define IXGBE_FACTPS_BY_MAC(_hw)        IXGBE_FACTPS
1051 
1052 #define IXGBE_PCIEANACTL        0x11040
1053 #define IXGBE_SWSM              0x10140
1054 #define IXGBE_SWSM_X540         IXGBE_SWSM
1055 #define IXGBE_SWSM_X550         IXGBE_SWSM
1056 #define IXGBE_SWSM_X550EM_x     IXGBE_SWSM
1057 #define IXGBE_SWSM_BY_MAC(_hw)  IXGBE_SWSM
1058 
1059 #define IXGBE_FWSM              0x10148
1060 #define IXGBE_FWSM_X540         IXGBE_FWSM
1061 #define IXGBE_FWSM_X550         IXGBE_FWSM
1062 #define IXGBE_FWSM_X550EM_x     IXGBE_FWSM
1063 #define IXGBE_FWSM_BY_MAC(_hw)  IXGBE_FWSM
1064 
1065 #define IXGBE_SWFW_SYNC         IXGBE_GSSR
1066 #define IXGBE_SWFW_SYNC_X540    IXGBE_SWFW_SYNC
1067 #define IXGBE_SWFW_SYNC_X550    IXGBE_SWFW_SYNC
1068 #define IXGBE_SWFW_SYNC_X550EM_x        IXGBE_SWFW_SYNC
1069 #define IXGBE_SWFW_SYNC_BY_MAC(_hw)     IXGBE_SWFW_SYNC
1070 
1071 #define IXGBE_GSSR              0x10160
1072 #define IXGBE_MREVID            0x11064
1073 #define IXGBE_DCA_ID            0x11070
1074 #define IXGBE_DCA_CTRL          0x11074

1075 
1076 /* PCI-E registers 82599-Specific */
1077 #define IXGBE_GCR_EXT           0x11050
1078 #define IXGBE_GSCL_5_82599      0x11030
1079 #define IXGBE_GSCL_6_82599      0x11034
1080 #define IXGBE_GSCL_7_82599      0x11038
1081 #define IXGBE_GSCL_8_82599      0x1103C
1082 #define IXGBE_PHYADR_82599      0x11040
1083 #define IXGBE_PHYDAT_82599      0x11044
1084 #define IXGBE_PHYCTL_82599      0x11048
1085 #define IXGBE_PBACLR_82599      0x11068
1086 #define IXGBE_CIAA              0x11088
1087 #define IXGBE_CIAD              0x1108C
1088 #define IXGBE_CIAA_82599        IXGBE_CIAA
1089 #define IXGBE_CIAD_82599        IXGBE_CIAD
1090 #define IXGBE_CIAA_X540         IXGBE_CIAA
1091 #define IXGBE_CIAD_X540         IXGBE_CIAD
1092 #define IXGBE_CIAA_X550         0x11508
1093 #define IXGBE_CIAD_X550         0x11510
1094 #define IXGBE_CIAA_X550EM_x     IXGBE_CIAA_X550
1095 #define IXGBE_CIAD_X550EM_x     IXGBE_CIAD_X550
1096 #define IXGBE_CIAA_BY_MAC(_hw)  IXGBE_BY_MAC((_hw), CIAA)
1097 #define IXGBE_CIAD_BY_MAC(_hw)  IXGBE_BY_MAC((_hw), CIAD)
1098 #define IXGBE_PICAUSE           0x110B0
1099 #define IXGBE_PIENA             0x110B8
1100 #define IXGBE_CDQ_MBR_82599     0x110B4
1101 #define IXGBE_PCIESPARE         0x110BC
1102 #define IXGBE_MISC_REG_82599    0x110F0
1103 #define IXGBE_ECC_CTRL_0_82599  0x11100
1104 #define IXGBE_ECC_CTRL_1_82599  0x11104
1105 #define IXGBE_ECC_STATUS_82599  0x110E0
1106 #define IXGBE_BAR_CTRL_82599    0x110F4
1107 
1108 /* PCI Express Control */
1109 #define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
1110 #define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
1111 #define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
1112 #define IXGBE_GCR_CAP_VER2              0x00040000
1113 
1114 #define IXGBE_GCR_EXT_MSIX_EN           0x80000000
1115 #define IXGBE_GCR_EXT_BUFFERS_CLEAR     0x40000000
1116 #define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
1117 #define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
1118 #define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
1119 #define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
1120                                          IXGBE_GCR_EXT_VT_MODE_64)
1121 #define IXGBE_GCR_EXT_VT_MODE_MASK      0x00000003
1122 /* Time Sync Registers */
1123 #define IXGBE_TSYNCRXCTL        0x05188 /* Rx Time Sync Control register - RW */
1124 #define IXGBE_TSYNCTXCTL        0x08C00 /* Tx Time Sync Control register - RW */
1125 #define IXGBE_RXSTMPL   0x051E8 /* Rx timestamp Low - RO */
1126 #define IXGBE_RXSTMPH   0x051A4 /* Rx timestamp High - RO */
1127 #define IXGBE_RXSATRL   0x051A0 /* Rx timestamp attribute low - RO */
1128 #define IXGBE_RXSATRH   0x051A8 /* Rx timestamp attribute high - RO */
1129 #define IXGBE_RXMTRL    0x05120 /* RX message type register low - RW */
1130 #define IXGBE_TXSTMPL   0x08C04 /* Tx timestamp value Low - RO */
1131 #define IXGBE_TXSTMPH   0x08C08 /* Tx timestamp value High - RO */
1132 #define IXGBE_SYSTIML   0x08C0C /* System time register Low - RO */
1133 #define IXGBE_SYSTIMH   0x08C10 /* System time register High - RO */
1134 #define IXGBE_SYSTIMR   0x08C58 /* System time register Residue - RO */
1135 #define IXGBE_TIMINCA   0x08C14 /* Increment attributes register - RW */
1136 #define IXGBE_TIMADJL   0x08C18 /* Time Adjustment Offset register Low - RW */
1137 #define IXGBE_TIMADJH   0x08C1C /* Time Adjustment Offset register High - RW */
1138 #define IXGBE_TSAUXC    0x08C20 /* TimeSync Auxiliary Control register - RW */
1139 #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
1140 #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
1141 #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
1142 #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
1143 #define IXGBE_CLKTIML   0x08C34 /* Clock Out Time Register Low - RW */
1144 #define IXGBE_CLKTIMH   0x08C38 /* Clock Out Time Register High - RW */
1145 #define IXGBE_FREQOUT0  0x08C34 /* Frequency Out 0 Control register - RW */
1146 #define IXGBE_FREQOUT1  0x08C38 /* Frequency Out 1 Control register - RW */
1147 #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
1148 #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
1149 #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
1150 #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
1151 #define IXGBE_TSIM      0x08C68 /* TimeSync Interrupt Mask Register - RW */
1152 #define IXGBE_TSICR     0x08C60 /* TimeSync Interrupt Cause Register - WO */
1153 #define IXGBE_TSSDP     0x0003C /* TimeSync SDP Configuration Register - RW */
1154 
1155 /* Diagnostic Registers */
1156 #define IXGBE_RDSTATCTL         0x02C20
1157 #define IXGBE_RDSTAT(_i)        (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
1158 #define IXGBE_RDHMPN            0x02F08
1159 #define IXGBE_RIC_DW(_i)        (0x02F10 + ((_i) * 4))
1160 #define IXGBE_RDPROBE           0x02F20
1161 #define IXGBE_RDMAM             0x02F30
1162 #define IXGBE_RDMAD             0x02F34


1163 #define IXGBE_TDHMPN            0x07F08
1164 #define IXGBE_TDHMPN2           0x082FC
1165 #define IXGBE_TXDESCIC          0x082CC
1166 #define IXGBE_TIC_DW(_i)        (0x07F10 + ((_i) * 4))
1167 #define IXGBE_TIC_DW2(_i)       (0x082B0 + ((_i) * 4))
1168 #define IXGBE_TDPROBE           0x07F20
1169 #define IXGBE_TXBUFCTRL         0x0C600
1170 #define IXGBE_TXBUFDATA0        0x0C610
1171 #define IXGBE_TXBUFDATA1        0x0C614
1172 #define IXGBE_TXBUFDATA2        0x0C618
1173 #define IXGBE_TXBUFDATA3        0x0C61C
1174 #define IXGBE_RXBUFCTRL         0x03600
1175 #define IXGBE_RXBUFDATA0        0x03610
1176 #define IXGBE_RXBUFDATA1        0x03614
1177 #define IXGBE_RXBUFDATA2        0x03618
1178 #define IXGBE_RXBUFDATA3        0x0361C
1179 #define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
1180 #define IXGBE_RFVAL             0x050A4
1181 #define IXGBE_MDFTC1            0x042B8
1182 #define IXGBE_MDFTC2            0x042C0


1281 
1282 #define IXGBE_RXDSTATCTRL       0x02F40
1283 
1284 /* Copper Pond 2 link timeout */
1285 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1286 
1287 /* Omer CORECTL */
1288 #define IXGBE_CORECTL                   0x014F00
1289 /* BARCTRL */
1290 #define IXGBE_BARCTRL                   0x110F4
1291 #define IXGBE_BARCTRL_FLSIZE            0x0700
1292 #define IXGBE_BARCTRL_FLSIZE_SHIFT      8
1293 #define IXGBE_BARCTRL_CSRSIZE           0x2000
1294 
1295 /* RSCCTL Bit Masks */
1296 #define IXGBE_RSCCTL_RSCEN      0x01
1297 #define IXGBE_RSCCTL_MAXDESC_1  0x00
1298 #define IXGBE_RSCCTL_MAXDESC_4  0x04
1299 #define IXGBE_RSCCTL_MAXDESC_8  0x08
1300 #define IXGBE_RSCCTL_MAXDESC_16 0x0C
1301 #define IXGBE_RSCCTL_TS_DIS     0x02
1302 
1303 /* RSCDBU Bit Masks */
1304 #define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
1305 #define IXGBE_RSCDBU_RSCACKDIS          0x00000080
1306 
1307 /* RDRXCTL Bit Masks */
1308 #define IXGBE_RDRXCTL_RDMTS_1_2         0x00000000 /* Rx Desc Min THLD Size */
1309 #define IXGBE_RDRXCTL_CRCSTRIP          0x00000002 /* CRC Strip */
1310 #define IXGBE_RDRXCTL_PSP               0x00000004 /* Pad Small Packet */
1311 #define IXGBE_RDRXCTL_MVMEN             0x00000020
1312 #define IXGBE_RDRXCTL_RSC_PUSH_DIS      0x00000020
1313 #define IXGBE_RDRXCTL_DMAIDONE          0x00000008 /* DMA init cycle done */
1314 #define IXGBE_RDRXCTL_RSC_PUSH          0x00000080
1315 #define IXGBE_RDRXCTL_AGGDIS            0x00010000 /* Aggregation disable */
1316 #define IXGBE_RDRXCTL_RSCFRSTSIZE       0x003E0000 /* RSC First packet size */
1317 #define IXGBE_RDRXCTL_RSCLLIDIS         0x00800000 /* Disable RSC compl on LLI*/
1318 #define IXGBE_RDRXCTL_RSCACKC           0x02000000 /* must set 1 when RSC ena */
1319 #define IXGBE_RDRXCTL_FCOE_WRFIX        0x04000000 /* must set 1 when RSC ena */
1320 #define IXGBE_RDRXCTL_MBINTEN           0x10000000
1321 #define IXGBE_RDRXCTL_MDP_EN            0x20000000
1322 
1323 /* RQTC Bit Masks and Shifts */
1324 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1325 #define IXGBE_RQTC_TC0_MASK     (0x7 << 0)
1326 #define IXGBE_RQTC_TC1_MASK     (0x7 << 4)
1327 #define IXGBE_RQTC_TC2_MASK     (0x7 << 8)
1328 #define IXGBE_RQTC_TC3_MASK     (0x7 << 12)
1329 #define IXGBE_RQTC_TC4_MASK     (0x7 << 16)
1330 #define IXGBE_RQTC_TC5_MASK     (0x7 << 20)
1331 #define IXGBE_RQTC_TC6_MASK     (0x7 << 24)
1332 #define IXGBE_RQTC_TC7_MASK     (0x7 << 28)
1333 
1334 /* PSRTYPE.RQPL Bit masks and shift */
1335 #define IXGBE_PSRTYPE_RQPL_MASK         0x7
1336 #define IXGBE_PSRTYPE_RQPL_SHIFT        29
1337 
1338 /* CTRL Bit Masks */
1339 #define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */
1340 #define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
1341 #define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
1342 #define IXGBE_CTRL_RST_MASK     (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1343 
1344 /* FACTPS */
1345 #define IXGBE_FACTPS_MNGCG      0x20000000 /* Manageblility Clock Gated */
1346 #define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
1347 
1348 /* MHADD Bit Masks */
1349 #define IXGBE_MHADD_MFS_MASK    0xFFFF0000
1350 #define IXGBE_MHADD_MFS_SHIFT   16
1351 
1352 /* Extended Device Control */
1353 #define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
1354 #define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
1355 #define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
1356 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1357 
1358 /* Direct Cache Access (DCA) definitions */
1359 #define IXGBE_DCA_CTRL_DCA_ENABLE       0x00000000 /* DCA Enable */
1360 #define IXGBE_DCA_CTRL_DCA_DISABLE      0x00000001 /* DCA Disable */
1361 
1362 #define IXGBE_DCA_CTRL_DCA_MODE_CB1     0x00 /* DCA Mode CB1 */
1363 #define IXGBE_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */
1364 
1365 #define IXGBE_DCA_RXCTRL_CPUID_MASK     0x0000001F /* Rx CPUID Mask */


1425 
1426 /* Device Type definitions for new protocol MDIO commands */
1427 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE             0x1
1428 #define IXGBE_MDIO_PCS_DEV_TYPE                 0x3
1429 #define IXGBE_MDIO_PHY_XS_DEV_TYPE              0x4
1430 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE            0x7
1431 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE   0x1E   /* Device 30 */
1432 #define IXGBE_TWINAX_DEV                        1
1433 
1434 #define IXGBE_MDIO_COMMAND_TIMEOUT      100 /* PHY Timeout for 1 GB mode */
1435 
1436 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL            0x0 /* VS1 Ctrl Reg */
1437 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS             0x1 /* VS1 Status Reg */
1438 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS        0x0008 /* 1 = Link Up */
1439 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS       0x0010 /* 0-10G, 1-1G */
1440 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED          0x0018
1441 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED           0x0010
1442 
1443 #define IXGBE_MDIO_AUTO_NEG_CONTROL     0x0 /* AUTO_NEG Control Reg */
1444 #define IXGBE_MDIO_AUTO_NEG_STATUS      0x1 /* AUTO_NEG Status Reg */
1445 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */
1446 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */
1447 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */
1448 #define IXGBE_MDIO_AUTO_NEG_VEN_LSC     0x1 /* AUTO_NEG Vendor Tx LSC */
1449 #define IXGBE_MDIO_AUTO_NEG_ADVT        0x10 /* AUTO_NEG Advt Reg */
1450 #define IXGBE_MDIO_AUTO_NEG_LP          0x13 /* AUTO_NEG LP Status Reg */
1451 #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT    0x3C /* AUTO_NEG EEE Advt Reg */
1452 #define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT 0x8  /* AUTO NEG EEE 10GBaseT Advt */
1453 #define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4  /* AUTO NEG EEE 1000BaseT Advt */
1454 #define IXGBE_AUTO_NEG_100BASE_EEE_ADVT 0x2  /* AUTO NEG EEE 100BaseT Advt */
1455 #define IXGBE_MDIO_PHY_XS_CONTROL       0x0 /* PHY_XS Control Reg */
1456 #define IXGBE_MDIO_PHY_XS_RESET         0x8000 /* PHY_XS Reset */
1457 #define IXGBE_MDIO_PHY_ID_HIGH          0x2 /* PHY ID High Reg*/
1458 #define IXGBE_MDIO_PHY_ID_LOW           0x3 /* PHY ID Low Reg*/
1459 #define IXGBE_MDIO_PHY_SPEED_ABILITY    0x4 /* Speed Ability Reg */
1460 #define IXGBE_MDIO_PHY_SPEED_10G        0x0001 /* 10G capable */
1461 #define IXGBE_MDIO_PHY_SPEED_1G         0x0010 /* 1G capable */
1462 #define IXGBE_MDIO_PHY_SPEED_100M       0x0020 /* 100M capable */
1463 #define IXGBE_MDIO_PHY_EXT_ABILITY      0xB /* Ext Ability Reg */
1464 #define IXGBE_MDIO_PHY_10GBASET_ABILITY         0x0004 /* 10GBaseT capable */
1465 #define IXGBE_MDIO_PHY_1000BASET_ABILITY        0x0020 /* 1000BaseT capable */
1466 #define IXGBE_MDIO_PHY_100BASETX_ABILITY        0x0080 /* 100BaseTX capable */
1467 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE       0x0800 /* Set low power mode */
1468 #define IXGBE_AUTO_NEG_LP_STATUS        0xE820 /* AUTO NEG Rx LP Status Reg */
1469 #define IXGBE_AUTO_NEG_LP_1000BASE_CAP  0x8000 /* AUTO NEG Rx LP 1000BaseT Cap */
1470 #define IXGBE_AUTO_NEG_LP_10GBASE_CAP   0x0800 /* AUTO NEG Rx LP 10GBaseT Cap */
1471 #define IXGBE_AUTO_NEG_10GBASET_STAT    0x0021 /* AUTO NEG 10G BaseT Stat */
1472 
1473 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3           0xCC02 /* Vendor Alarms 3 Reg */
1474 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK  0x3 /* PHY Reset Complete Mask */
1475 #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
1476 #define IXGBE_MDIO_POWER_UP_STALL               0x8000 /* Power Up Stall */
1477 #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK     0xFF00 /* int std mask */
1478 #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG     0xFC00 /* chip std int flag */
1479 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK     0xFF01 /* int chip-wide mask */
1480 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG     0xFC01 /* int chip-wide mask */
1481 #define IXGBE_MDIO_GLOBAL_ALARM_1               0xCC00 /* Global alarm 1 */
1482 #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL     0x4000 /* high temp failure */
1483 #define IXGBE_MDIO_GLOBAL_INT_MASK              0xD400 /* Global int mask */
1484 #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN     0x1000 /* autoneg vendor alarm int enable */
1485 #define IXGBE_MDIO_GLOBAL_ALARM_1_INT           0x4 /* int in Global alarm 1 */
1486 #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN        0x1 /* vendor alarm int enable */
1487 #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT          0x200 /* vendor alarm2 int mask */
1488 #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN        0x4000 /* int high temp enable */
1489 #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
1490 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1491 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1492 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1493 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */
1494 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN   0x1 /* PHY TX Vendor LASI enable */
1495 #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
1496 #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */
1497 
1498 #define IXGBE_PCRC8ECL          0x0E810 /* PCR CRC-8 Error Count Lo */
1499 #define IXGBE_PCRC8ECH          0x0E811 /* PCR CRC-8 Error Count Hi */
1500 #define IXGBE_PCRC8ECH_MASK     0x1F
1501 #define IXGBE_LDPCECL           0x0E820 /* PCR Uncorrected Error Count Lo */
1502 #define IXGBE_LDPCECH           0x0E821 /* PCR Uncorrected Error Count Hi */
1503 
1504 /* MII clause 22/28 definitions */
1505 #define IXGBE_MDIO_PHY_LOW_POWER_MODE   0x0800
1506 
1507 #define IXGBE_MDIO_XENPAK_LASI_STATUS           0x9005 /* XENPAK LASI Status register*/
1508 #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM     0x1 /* Link Status Alarm change */
1509 
1510 #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS         0x4 /* Indicates if link is up */
1511 
1512 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK  0x7 /* Speed/Duplex Mask */
1513 #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK         0x6 /* Speed Mask */
1514 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF      0x0 /* 10Mb/s Half Duplex */
1515 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL      0x1 /* 10Mb/s Full Duplex */
1516 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF     0x2 /* 100Mb/s Half Duplex */
1517 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL     0x3 /* 100Mb/s Full Duplex */
1518 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF      0x4 /* 1Gb/s Half Duplex */
1519 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL      0x5 /* 1Gb/s Full Duplex */
1520 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF     0x6 /* 10Gb/s Half Duplex */
1521 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL     0x7 /* 10Gb/s Full Duplex */
1522 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB           0x4 /* 1Gb/s */
1523 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB          0x6 /* 10Gb/s */
1524 
1525 #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG    0x20   /* 10G Control Reg */
1526 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1527 #define IXGBE_MII_AUTONEG_XNP_TX_REG            0x17   /* 1G XNP Transmit */
1528 #define IXGBE_MII_AUTONEG_ADVERTISE_REG         0x10   /* 100M Advertisement */
1529 #define IXGBE_MII_10GBASE_T_ADVERTISE           0x1000 /* full duplex, bit:12*/
1530 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX     0x4000 /* full duplex, bit:14*/
1531 #define IXGBE_MII_1GBASE_T_ADVERTISE            0x8000 /* full duplex, bit:15*/
1532 #define IXGBE_MII_2_5GBASE_T_ADVERTISE          0x0400
1533 #define IXGBE_MII_5GBASE_T_ADVERTISE            0x0800
1534 #define IXGBE_MII_100BASE_T_ADVERTISE           0x0100 /* full duplex, bit:8 */
1535 #define IXGBE_MII_100BASE_T_ADVERTISE_HALF      0x0080 /* half duplex, bit:7 */
1536 #define IXGBE_MII_RESTART                       0x200
1537 #define IXGBE_MII_AUTONEG_COMPLETE              0x20
1538 #define IXGBE_MII_AUTONEG_LINK_UP               0x04
1539 #define IXGBE_MII_AUTONEG_REG                   0x0
1540 
1541 #define IXGBE_PHY_REVISION_MASK         0xFFFFFFF0
1542 #define IXGBE_MAX_PHY_ADDR              32
1543 
1544 /* PHY IDs*/
1545 #define TN1010_PHY_ID   0x00A19410
1546 #define TNX_FW_REV      0xB
1547 #define X540_PHY_ID     0x01540200
1548 #define X550_PHY_ID1    0x01540220
1549 #define X550_PHY_ID2    0x01540223
1550 #define X550_PHY_ID3    0x01540221
1551 #define X557_PHY_ID     0x01540240
1552 #define AQ_FW_REV       0x20
1553 #define QT2022_PHY_ID   0x0043A400
1554 #define ATH_PHY_ID      0x03429050
1555 
1556 /* PHY Types */
1557 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1558 
1559 /* Special PHY Init Routine */
1560 #define IXGBE_PHY_INIT_OFFSET_NL        0x002B
1561 #define IXGBE_PHY_INIT_END_NL           0xFFFF
1562 #define IXGBE_CONTROL_MASK_NL           0xF000
1563 #define IXGBE_DATA_MASK_NL              0x0FFF
1564 #define IXGBE_CONTROL_SHIFT_NL          12
1565 #define IXGBE_DELAY_NL                  0
1566 #define IXGBE_DATA_NL                   1
1567 #define IXGBE_CONTROL_NL                0x000F
1568 #define IXGBE_CONTROL_EOL_NL            0x0FFF
1569 #define IXGBE_CONTROL_SOL_NL            0x0000
1570 
1571 /* General purpose Interrupt Enable */
1572 #define IXGBE_SDP0_GPIEN        0x00000001 /* SDP0 */
1573 #define IXGBE_SDP1_GPIEN        0x00000002 /* SDP1 */
1574 #define IXGBE_SDP2_GPIEN        0x00000004 /* SDP2 */
1575 #define IXGBE_SDP0_GPIEN_X540   0x00000002 /* SDP0 on X540 and X550 */
1576 #define IXGBE_SDP1_GPIEN_X540   0x00000004 /* SDP1 on X540 and X550 */
1577 #define IXGBE_SDP2_GPIEN_X540   0x00000008 /* SDP2 on X540 and X550 */
1578 #define IXGBE_SDP0_GPIEN_X550   IXGBE_SDP0_GPIEN_X540
1579 #define IXGBE_SDP1_GPIEN_X550   IXGBE_SDP1_GPIEN_X540
1580 #define IXGBE_SDP2_GPIEN_X550   IXGBE_SDP2_GPIEN_X540
1581 #define IXGBE_SDP0_GPIEN_X550EM_x       IXGBE_SDP0_GPIEN_X540
1582 #define IXGBE_SDP1_GPIEN_X550EM_x       IXGBE_SDP1_GPIEN_X540
1583 #define IXGBE_SDP2_GPIEN_X550EM_x       IXGBE_SDP2_GPIEN_X540
1584 #define IXGBE_SDP0_GPIEN_BY_MAC(_hw)    IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1585 #define IXGBE_SDP1_GPIEN_BY_MAC(_hw)    IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1586 #define IXGBE_SDP2_GPIEN_BY_MAC(_hw)    IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1587 
1588 #define IXGBE_GPIE_MSIX_MODE    0x00000010 /* MSI-X mode */
1589 #define IXGBE_GPIE_OCD          0x00000020 /* Other Clear Disable */
1590 #define IXGBE_GPIE_EIMEN        0x00000040 /* Immediate Interrupt Enable */
1591 #define IXGBE_GPIE_EIAME        0x40000000
1592 #define IXGBE_GPIE_PBA_SUPPORT  0x80000000
1593 #define IXGBE_GPIE_RSC_DELAY_SHIFT      11
1594 #define IXGBE_GPIE_VTMODE_MASK  0x0000C000 /* VT Mode Mask */
1595 #define IXGBE_GPIE_VTMODE_16    0x00004000 /* 16 VFs 8 queues per VF */
1596 #define IXGBE_GPIE_VTMODE_32    0x00008000 /* 32 VFs 4 queues per VF */
1597 #define IXGBE_GPIE_VTMODE_64    0x0000C000 /* 64 VFs 2 queues per VF */
1598 
1599 /* Packet Buffer Initialization */
1600 #define IXGBE_MAX_PACKET_BUFFERS        8
1601 
1602 #define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
1603 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
1604 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
1605 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
1606 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
1607 #define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */


1745 #define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
1746 #define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
1747 
1748 /* Interrupt register bitmasks */
1749 
1750 /* Extended Interrupt Cause Read */
1751 #define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
1752 #define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
1753 #define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
1754 #define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
1755 #define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
1756 #define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
1757 #define IXGBE_EICR_LINKSEC      0x00200000 /* PN Threshold */
1758 #define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
1759 #define IXGBE_EICR_TS           0x00800000 /* Thermal Sensor Event */
1760 #define IXGBE_EICR_TIMESYNC     0x01000000 /* Timesync Event */
1761 #define IXGBE_EICR_GPI_SDP0     0x01000000 /* Gen Purpose Interrupt on SDP0 */
1762 #define IXGBE_EICR_GPI_SDP1     0x02000000 /* Gen Purpose Interrupt on SDP1 */
1763 #define IXGBE_EICR_GPI_SDP2     0x04000000 /* Gen Purpose Interrupt on SDP2 */
1764 #define IXGBE_EICR_ECC          0x10000000 /* ECC Error */
1765 #define IXGBE_EICR_GPI_SDP0_X540 0x02000000 /* Gen Purpose Interrupt on SDP0 */
1766 #define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */
1767 #define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */
1768 #define IXGBE_EICR_GPI_SDP0_X550        IXGBE_EICR_GPI_SDP0_X540
1769 #define IXGBE_EICR_GPI_SDP1_X550        IXGBE_EICR_GPI_SDP1_X540
1770 #define IXGBE_EICR_GPI_SDP2_X550        IXGBE_EICR_GPI_SDP2_X540
1771 #define IXGBE_EICR_GPI_SDP0_X550EM_x    IXGBE_EICR_GPI_SDP0_X540
1772 #define IXGBE_EICR_GPI_SDP1_X550EM_x    IXGBE_EICR_GPI_SDP1_X540
1773 #define IXGBE_EICR_GPI_SDP2_X550EM_x    IXGBE_EICR_GPI_SDP2_X540
1774 #define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1775 #define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1776 #define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1777 
1778 #define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
1779 #define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
1780 #define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
1781 #define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
1782 
1783 /* Extended Interrupt Cause Set */
1784 #define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1785 #define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1786 #define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
1787 #define IXGBE_EICS_PCI          IXGBE_EICR_PCI /* PCI Exception */
1788 #define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1789 #define IXGBE_EICS_LSC          IXGBE_EICR_LSC /* Link Status Change */
1790 #define IXGBE_EICS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1791 #define IXGBE_EICS_TIMESYNC     IXGBE_EICR_TIMESYNC /* Timesync Event */
1792 #define IXGBE_EICS_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1793 #define IXGBE_EICS_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1794 #define IXGBE_EICS_GPI_SDP2     IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1795 #define IXGBE_EICS_ECC          IXGBE_EICR_ECC /* ECC Error */
1796 #define IXGBE_EICS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1797 #define IXGBE_EICS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1798 #define IXGBE_EICS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1799 #define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1800 #define IXGBE_EICS_DHER         IXGBE_EICR_DHER /* Desc Handler Error */
1801 #define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1802 #define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1803 
1804 /* Extended Interrupt Mask Set */
1805 #define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1806 #define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR /* FDir Exception */
1807 #define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1808 #define IXGBE_EIMS_PCI          IXGBE_EICR_PCI /* PCI Exception */
1809 #define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1810 #define IXGBE_EIMS_LSC          IXGBE_EICR_LSC /* Link Status Change */
1811 #define IXGBE_EIMS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1812 #define IXGBE_EIMS_TS           IXGBE_EICR_TS /* Thermal Sensor Event */
1813 #define IXGBE_EIMS_TIMESYNC     IXGBE_EICR_TIMESYNC /* Timesync Event */
1814 #define IXGBE_EIMS_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1815 #define IXGBE_EIMS_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1816 #define IXGBE_EIMS_GPI_SDP2     IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1817 #define IXGBE_EIMS_ECC          IXGBE_EICR_ECC /* ECC Error */
1818 #define IXGBE_EIMS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1819 #define IXGBE_EIMS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1820 #define IXGBE_EIMS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1821 #define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1822 #define IXGBE_EIMS_DHER         IXGBE_EICR_DHER /* Descr Handler Error */
1823 #define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1824 #define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1825 
1826 /* Extended Interrupt Mask Clear */
1827 #define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1828 #define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR /* FDir Exception */
1829 #define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1830 #define IXGBE_EIMC_PCI          IXGBE_EICR_PCI /* PCI Exception */
1831 #define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1832 #define IXGBE_EIMC_LSC          IXGBE_EICR_LSC /* Link Status Change */
1833 #define IXGBE_EIMC_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1834 #define IXGBE_EIMC_TIMESYNC     IXGBE_EICR_TIMESYNC /* Timesync Event */
1835 #define IXGBE_EIMC_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1836 #define IXGBE_EIMC_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1837 #define IXGBE_EIMC_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
1838 #define IXGBE_EIMC_ECC          IXGBE_EICR_ECC /* ECC Error */
1839 #define IXGBE_EIMC_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1840 #define IXGBE_EIMC_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1841 #define IXGBE_EIMC_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1842 #define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1843 #define IXGBE_EIMC_DHER         IXGBE_EICR_DHER /* Desc Handler Err */
1844 #define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1845 #define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1846 
1847 #define IXGBE_EIMS_ENABLE_MASK ( \
1848                                 IXGBE_EIMS_RTX_QUEUE    | \
1849                                 IXGBE_EIMS_LSC          | \
1850                                 IXGBE_EIMS_TCP_TIMER    | \
1851                                 IXGBE_EIMS_OTHER)
1852 
1853 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1854 #define IXGBE_IMIR_PORT_IM_EN   0x00010000  /* TCP port enable */
1855 #define IXGBE_IMIR_PORT_BP      0x00020000  /* TCP port check bypass */
1856 #define IXGBE_IMIREXT_SIZE_BP   0x00001000  /* Packet size bypass */
1857 #define IXGBE_IMIREXT_CTRL_URG  0x00002000  /* Check URG bit in header */
1858 #define IXGBE_IMIREXT_CTRL_ACK  0x00004000  /* Check ACK bit in header */
1859 #define IXGBE_IMIREXT_CTRL_PSH  0x00008000  /* Check PSH bit in header */
1860 #define IXGBE_IMIREXT_CTRL_RST  0x00010000  /* Check RST bit in header */
1861 #define IXGBE_IMIREXT_CTRL_SYN  0x00020000  /* Check SYN bit in header */


1900 /* Interrupt Vector Allocation Registers */
1901 #define IXGBE_IVAR_REG_NUM              25
1902 #define IXGBE_IVAR_REG_NUM_82599        64
1903 #define IXGBE_IVAR_TXRX_ENTRY           96
1904 #define IXGBE_IVAR_RX_ENTRY             64
1905 #define IXGBE_IVAR_RX_QUEUE(_i)         (0 + (_i))
1906 #define IXGBE_IVAR_TX_QUEUE(_i)         (64 + (_i))
1907 #define IXGBE_IVAR_TX_ENTRY             32
1908 
1909 #define IXGBE_IVAR_TCP_TIMER_INDEX      96 /* 0 based index */
1910 #define IXGBE_IVAR_OTHER_CAUSES_INDEX   97 /* 0 based index */
1911 
1912 #define IXGBE_MSIX_VECTOR(_i)           (0 + (_i))
1913 
1914 #define IXGBE_IVAR_ALLOC_VAL            0x80 /* Interrupt Allocation valid */
1915 
1916 /* ETYPE Queue Filter/Select Bit Masks */
1917 #define IXGBE_MAX_ETQF_FILTERS          8
1918 #define IXGBE_ETQF_FCOE                 0x08000000 /* bit 27 */
1919 #define IXGBE_ETQF_BCN                  0x10000000 /* bit 28 */
1920 #define IXGBE_ETQF_TX_ANTISPOOF         0x20000000 /* bit 29 */
1921 #define IXGBE_ETQF_1588                 0x40000000 /* bit 30 */
1922 #define IXGBE_ETQF_FILTER_EN            0x80000000 /* bit 31 */
1923 #define IXGBE_ETQF_POOL_ENABLE          (1 << 26) /* bit 26 */
1924 #define IXGBE_ETQF_POOL_SHIFT           20
1925 
1926 #define IXGBE_ETQS_RX_QUEUE             0x007F0000 /* bits 22:16 */
1927 #define IXGBE_ETQS_RX_QUEUE_SHIFT       16
1928 #define IXGBE_ETQS_LLI                  0x20000000 /* bit 29 */
1929 #define IXGBE_ETQS_QUEUE_EN             0x80000000 /* bit 31 */
1930 
1931 /*
1932  * ETQF filter list: one static filter per filter consumer. This is
1933  *                 to avoid filter collisions later. Add new filters
1934  *                 here!!
1935  *
1936  * Current filters:
1937  *      EAPOL 802.1x (0x888e): Filter 0
1938  *      FCoE (0x8906):   Filter 2
1939  *      1588 (0x88f7):   Filter 3
1940  *      FIP  (0x8914):   Filter 4
1941  *      LLDP (0x88CC):   Filter 5
1942  *      LACP (0x8809):   Filter 6
1943  *      FC   (0x8808):   Filter 7
1944  */
1945 #define IXGBE_ETQF_FILTER_EAPOL         0
1946 #define IXGBE_ETQF_FILTER_FCOE          2
1947 #define IXGBE_ETQF_FILTER_1588          3
1948 #define IXGBE_ETQF_FILTER_FIP           4
1949 #define IXGBE_ETQF_FILTER_LLDP          5
1950 #define IXGBE_ETQF_FILTER_LACP          6
1951 #define IXGBE_ETQF_FILTER_FC            7
1952 /* VLAN Control Bit Masks */
1953 #define IXGBE_VLNCTRL_VET               0x0000FFFF  /* bits 0-15 */
1954 #define IXGBE_VLNCTRL_CFI               0x10000000  /* bit 28 */
1955 #define IXGBE_VLNCTRL_CFIEN             0x20000000  /* bit 29 */
1956 #define IXGBE_VLNCTRL_VFE               0x40000000  /* bit 30 */
1957 #define IXGBE_VLNCTRL_VME               0x80000000  /* bit 31 */
1958 
1959 /* VLAN pool filtering masks */
1960 #define IXGBE_VLVF_VIEN                 0x80000000  /* filter is valid */
1961 #define IXGBE_VLVF_ENTRIES              64
1962 #define IXGBE_VLVF_VLANID_MASK          0x00000FFF
1963 /* Per VF Port VLAN insertion rules */
1964 #define IXGBE_VMVIR_VLANA_DEFAULT       0x40000000 /* Always use default VLAN */
1965 #define IXGBE_VMVIR_VLANA_NEVER         0x80000000 /* Never insert VLAN tag */
1966 
1967 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE   0x8100  /* 802.1q protocol */
1968 
1969 /* STATUS Bit Masks */
1970 #define IXGBE_STATUS_LAN_ID             0x0000000C /* LAN ID */
1971 #define IXGBE_STATUS_LAN_ID_SHIFT       2 /* LAN ID Shift*/
1972 #define IXGBE_STATUS_GIO                0x00080000 /* GIO Master Ena Status */
1973 
1974 #define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
1975 #define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
1976 
1977 /* ESDP Bit Masks */
1978 #define IXGBE_ESDP_SDP0         0x00000001 /* SDP0 Data Value */
1979 #define IXGBE_ESDP_SDP1         0x00000002 /* SDP1 Data Value */
1980 #define IXGBE_ESDP_SDP2         0x00000004 /* SDP2 Data Value */
1981 #define IXGBE_ESDP_SDP3         0x00000008 /* SDP3 Data Value */
1982 #define IXGBE_ESDP_SDP4         0x00000010 /* SDP4 Data Value */
1983 #define IXGBE_ESDP_SDP5         0x00000020 /* SDP5 Data Value */
1984 #define IXGBE_ESDP_SDP6         0x00000040 /* SDP6 Data Value */
1985 #define IXGBE_ESDP_SDP7         0x00000080 /* SDP7 Data Value */
1986 #define IXGBE_ESDP_SDP0_DIR     0x00000100 /* SDP0 IO direction */
1987 #define IXGBE_ESDP_SDP1_DIR     0x00000200 /* SDP1 IO direction */
1988 #define IXGBE_ESDP_SDP2_DIR     0x00000400 /* SDP1 IO direction */
1989 #define IXGBE_ESDP_SDP3_DIR     0x00000800 /* SDP3 IO direction */
1990 #define IXGBE_ESDP_SDP4_DIR     0x00001000 /* SDP4 IO direction */
1991 #define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
1992 #define IXGBE_ESDP_SDP6_DIR     0x00004000 /* SDP6 IO direction */
1993 #define IXGBE_ESDP_SDP7_DIR     0x00008000 /* SDP7 IO direction */
1994 #define IXGBE_ESDP_SDP0_NATIVE  0x00010000 /* SDP0 IO mode */
1995 #define IXGBE_ESDP_SDP1_NATIVE  0x00020000 /* SDP1 IO mode */
1996 
1997 
1998 /* LEDCTL Bit Masks */
1999 #define IXGBE_LED_IVRT_BASE             0x00000040
2000 #define IXGBE_LED_BLINK_BASE            0x00000080
2001 #define IXGBE_LED_MODE_MASK_BASE        0x0000000F
2002 #define IXGBE_LED_OFFSET(_base, _i)     (_base << (8 * (_i)))
2003 #define IXGBE_LED_MODE_SHIFT(_i)        (8*(_i))
2004 #define IXGBE_LED_IVRT(_i)      IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
2005 #define IXGBE_LED_BLINK(_i)     IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
2006 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
2007 #define IXGBE_X557_LED_MANUAL_SET_MASK  (1 << 8)
2008 #define IXGBE_X557_MAX_LED_INDEX        3
2009 #define IXGBE_X557_LED_PROVISIONING     0xC430
2010 
2011 /* LED modes */
2012 #define IXGBE_LED_LINK_UP       0x0
2013 #define IXGBE_LED_LINK_10G      0x1
2014 #define IXGBE_LED_MAC           0x2
2015 #define IXGBE_LED_FILTER        0x3
2016 #define IXGBE_LED_LINK_ACTIVE   0x4
2017 #define IXGBE_LED_LINK_1G       0x5
2018 #define IXGBE_LED_ON            0xE
2019 #define IXGBE_LED_OFF           0xF
2020 
2021 /* AUTOC Bit Masks */
2022 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
2023 #define IXGBE_AUTOC_KX4_SUPP    0x80000000
2024 #define IXGBE_AUTOC_KX_SUPP     0x40000000
2025 #define IXGBE_AUTOC_PAUSE       0x30000000
2026 #define IXGBE_AUTOC_ASM_PAUSE   0x20000000
2027 #define IXGBE_AUTOC_SYM_PAUSE   0x10000000
2028 #define IXGBE_AUTOC_RF          0x08000000
2029 #define IXGBE_AUTOC_PD_TMR      0x06000000


2050 #define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2051 
2052 #define IXGBE_AUTOC_1G_PMA_PMD_MASK     0x00000200
2053 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT    9
2054 #define IXGBE_AUTOC_10G_PMA_PMD_MASK    0x00000180
2055 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT   7
2056 #define IXGBE_AUTOC_10G_XAUI    (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2057 #define IXGBE_AUTOC_10G_KX4     (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2058 #define IXGBE_AUTOC_10G_CX4     (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2059 #define IXGBE_AUTOC_1G_BX       (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2060 #define IXGBE_AUTOC_1G_KX       (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2061 #define IXGBE_AUTOC_1G_SFI      (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2062 #define IXGBE_AUTOC_1G_KX_BX    (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2063 
2064 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
2065 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK    0x00030000
2066 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT   16
2067 #define IXGBE_AUTOC2_10G_KR     (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2068 #define IXGBE_AUTOC2_10G_XFI    (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2069 #define IXGBE_AUTOC2_10G_SFI    (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2070 #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK    0x50000000
2071 #define IXGBE_AUTOC2_LINK_DISABLE_MASK          0x70000000
2072 
2073 #define IXGBE_MACC_FLU          0x00000001
2074 #define IXGBE_MACC_FSV_10G      0x00030000
2075 #define IXGBE_MACC_FS           0x00040000
2076 #define IXGBE_MAC_RX2TX_LPBK    0x00000002
2077 
2078 /* Veto Bit definiton */
2079 #define IXGBE_MMNGC_MNG_VETO    0x00000001
2080 
2081 /* LINKS Bit Masks */
2082 #define IXGBE_LINKS_KX_AN_COMP  0x80000000
2083 #define IXGBE_LINKS_UP          0x40000000
2084 #define IXGBE_LINKS_SPEED       0x20000000
2085 #define IXGBE_LINKS_MODE        0x18000000
2086 #define IXGBE_LINKS_RX_MODE     0x06000000
2087 #define IXGBE_LINKS_TX_MODE     0x01800000
2088 #define IXGBE_LINKS_XGXS_EN     0x00400000
2089 #define IXGBE_LINKS_SGMII_EN    0x02000000
2090 #define IXGBE_LINKS_PCS_1G_EN   0x00200000
2091 #define IXGBE_LINKS_1G_AN_EN    0x00100000
2092 #define IXGBE_LINKS_KX_AN_IDLE  0x00080000
2093 #define IXGBE_LINKS_1G_SYNC     0x00040000
2094 #define IXGBE_LINKS_10G_ALIGN   0x00020000
2095 #define IXGBE_LINKS_10G_LANE_SYNC       0x00017000
2096 #define IXGBE_LINKS_TL_FAULT            0x00001000
2097 #define IXGBE_LINKS_SIGNAL              0x00000F00
2098 
2099 #define IXGBE_LINKS_SPEED_NON_STD       0x08000000
2100 #define IXGBE_LINKS_SPEED_82599         0x30000000
2101 #define IXGBE_LINKS_SPEED_10G_82599     0x30000000
2102 #define IXGBE_LINKS_SPEED_1G_82599      0x20000000
2103 #define IXGBE_LINKS_SPEED_100_82599     0x10000000
2104 #define IXGBE_LINK_UP_TIME              90 /* 9.0 Seconds */
2105 #define IXGBE_AUTO_NEG_TIME             45 /* 4.5 Seconds */
2106 
2107 #define IXGBE_LINKS2_AN_SUPPORTED       0x00000040
2108 
2109 /* PCS1GLSTA Bit Masks */
2110 #define IXGBE_PCS1GLSTA_LINK_OK         1
2111 #define IXGBE_PCS1GLSTA_SYNK_OK         0x10
2112 #define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
2113 #define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
2114 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
2115 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
2116 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
2117 
2118 #define IXGBE_PCS1GANA_SYM_PAUSE        0x80
2119 #define IXGBE_PCS1GANA_ASM_PAUSE        0x100


2127 #define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
2128 
2129 /* ANLP1 Bit Masks */
2130 #define IXGBE_ANLP1_PAUSE               0x0C00
2131 #define IXGBE_ANLP1_SYM_PAUSE           0x0400
2132 #define IXGBE_ANLP1_ASM_PAUSE           0x0800
2133 #define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
2134 
2135 /* SW Semaphore Register bitmasks */
2136 #define IXGBE_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
2137 #define IXGBE_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
2138 #define IXGBE_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
2139 #define IXGBE_SWFW_REGSMP       0x80000000 /* Register Semaphore bit 31 */
2140 
2141 /* SW_FW_SYNC/GSSR definitions */
2142 #define IXGBE_GSSR_EEP_SM               0x0001
2143 #define IXGBE_GSSR_PHY0_SM              0x0002
2144 #define IXGBE_GSSR_PHY1_SM              0x0004
2145 #define IXGBE_GSSR_MAC_CSR_SM           0x0008
2146 #define IXGBE_GSSR_FLASH_SM             0x0010
2147 #define IXGBE_GSSR_NVM_UPDATE_SM        0x0200
2148 #define IXGBE_GSSR_SW_MNG_SM            0x0400
2149 #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */
2150 #define IXGBE_GSSR_I2C_MASK     0x1800
2151 #define IXGBE_GSSR_NVM_PHY_MASK 0xF
2152 
2153 /* FW Status register bitmask */
2154 #define IXGBE_FWSTS_FWRI        0x00000200 /* Firmware Reset Indication */
2155 
2156 /* EEC Register */
2157 #define IXGBE_EEC_SK            0x00000001 /* EEPROM Clock */
2158 #define IXGBE_EEC_CS            0x00000002 /* EEPROM Chip Select */
2159 #define IXGBE_EEC_DI            0x00000004 /* EEPROM Data In */
2160 #define IXGBE_EEC_DO            0x00000008 /* EEPROM Data Out */
2161 #define IXGBE_EEC_FWE_MASK      0x00000030 /* FLASH Write Enable */
2162 #define IXGBE_EEC_FWE_DIS       0x00000010 /* Disable FLASH writes */
2163 #define IXGBE_EEC_FWE_EN        0x00000020 /* Enable FLASH writes */
2164 #define IXGBE_EEC_FWE_SHIFT     4
2165 #define IXGBE_EEC_REQ           0x00000040 /* EEPROM Access Request */
2166 #define IXGBE_EEC_GNT           0x00000080 /* EEPROM Access Grant */
2167 #define IXGBE_EEC_PRES          0x00000100 /* EEPROM Present */
2168 #define IXGBE_EEC_ARD           0x00000200 /* EEPROM Auto Read Done */
2169 #define IXGBE_EEC_FLUP          0x00800000 /* Flash update command */
2170 #define IXGBE_EEC_SEC1VAL       0x02000000 /* Sector 1 Valid */
2171 #define IXGBE_EEC_FLUDONE       0x04000000 /* Flash update done */
2172 /* EEPROM Addressing bits based on type (0-small, 1-large) */
2173 #define IXGBE_EEC_ADDR_SIZE     0x00000400
2174 #define IXGBE_EEC_SIZE          0x00007800 /* EEPROM Size */
2175 #define IXGBE_EERD_MAX_ADDR     0x00003FFF /* EERD alows 14 bits for addr. */
2176 
2177 #define IXGBE_EEC_SIZE_SHIFT            11
2178 #define IXGBE_EEPROM_WORD_SIZE_SHIFT    6
2179 #define IXGBE_EEPROM_OPCODE_BITS        8
2180 
2181 /* FLA Register */
2182 #define IXGBE_FLA_LOCKED        0x00000040
2183 
2184 /* Part Number String Length */
2185 #define IXGBE_PBANUM_LENGTH     11
2186 
2187 /* Checksum and EEPROM pointers */
2188 #define IXGBE_PBANUM_PTR_GUARD          0xFAFA
2189 #define IXGBE_EEPROM_CHECKSUM           0x3F
2190 #define IXGBE_EEPROM_SUM                0xBABA
2191 #define IXGBE_PCIE_ANALOG_PTR           0x03
2192 #define IXGBE_ATLAS0_CONFIG_PTR         0x04
2193 #define IXGBE_PHY_PTR                   0x04
2194 #define IXGBE_ATLAS1_CONFIG_PTR         0x05
2195 #define IXGBE_OPTION_ROM_PTR            0x05
2196 #define IXGBE_PCIE_GENERAL_PTR          0x06
2197 #define IXGBE_PCIE_CONFIG0_PTR          0x07
2198 #define IXGBE_PCIE_CONFIG1_PTR          0x08
2199 #define IXGBE_CORE0_PTR                 0x09
2200 #define IXGBE_CORE1_PTR                 0x0A
2201 #define IXGBE_MAC0_PTR                  0x0B
2202 #define IXGBE_MAC1_PTR                  0x0C
2203 #define IXGBE_CSR0_CONFIG_PTR           0x0D
2204 #define IXGBE_CSR1_CONFIG_PTR           0x0E
2205 #define IXGBE_PCIE_ANALOG_PTR_X550      0x02
2206 #define IXGBE_SHADOW_RAM_SIZE_X550      0x4000
2207 #define IXGBE_IXGBE_PCIE_GENERAL_SIZE   0x24
2208 #define IXGBE_PCIE_CONFIG_SIZE          0x08
2209 #define IXGBE_EEPROM_LAST_WORD          0x41
2210 #define IXGBE_FW_PTR                    0x0F
2211 #define IXGBE_PBANUM0_PTR               0x15
2212 #define IXGBE_PBANUM1_PTR               0x16
2213 #define IXGBE_ALT_MAC_ADDR_PTR          0x37
2214 #define IXGBE_FREE_SPACE_PTR            0X3E
2215 
2216 #define IXGBE_SAN_MAC_ADDR_PTR          0x28
2217 #define IXGBE_DEVICE_CAPS               0x2C
2218 #define IXGBE_SERIAL_NUMBER_MAC_ADDR    0x11
2219 #define IXGBE_PCIE_MSIX_82599_CAPS      0x72
2220 #define IXGBE_MAX_MSIX_VECTORS_82599    0x40
2221 #define IXGBE_PCIE_MSIX_82598_CAPS      0x62
2222 #define IXGBE_MAX_MSIX_VECTORS_82598    0x13
2223 
2224 /* MSI-X capability fields masks */
2225 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
2226 
2227 /* Legacy EEPROM word offsets */
2228 #define IXGBE_ISCSI_BOOT_CAPS           0x0033
2229 #define IXGBE_ISCSI_SETUP_PORT_0        0x0030


2235 #define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
2236 #define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
2237 #define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
2238 #define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
2239 /* EEPROM reset Write Enable latch */
2240 #define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
2241 #define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
2242 #define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
2243 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
2244 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI        0xD8  /* EEPROM ERASE 64KB */
2245 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI        0xDB  /* EEPROM ERASE 256B */
2246 
2247 /* EEPROM Read Register */
2248 #define IXGBE_EEPROM_RW_REG_DATA        16 /* data offset in EEPROM read reg */
2249 #define IXGBE_EEPROM_RW_REG_DONE        2 /* Offset to READ done bit */
2250 #define IXGBE_EEPROM_RW_REG_START       1 /* First bit to start operation */
2251 #define IXGBE_EEPROM_RW_ADDR_SHIFT      2 /* Shift to the address bits */
2252 #define IXGBE_NVM_POLL_WRITE            1 /* Flag for polling for wr complete */
2253 #define IXGBE_NVM_POLL_READ             0 /* Flag for polling for rd complete */
2254 
2255 #define NVM_INIT_CTRL_3         0x38
2256 #define NVM_INIT_CTRL_3_LPLU    0x8
2257 #define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40
2258 #define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100
2259 
2260 #define IXGBE_ETH_LENGTH_OF_ADDRESS     6
2261 
2262 #define IXGBE_EEPROM_PAGE_SIZE_MAX      128
2263 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT        256 /* words rd in burst */
2264 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT        256 /* words wr in burst */
2265 #define IXGBE_EEPROM_CTRL_2             1 /* EEPROM CTRL word 2 */
2266 #define IXGBE_EEPROM_CCD_BIT            2
2267 
2268 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
2269 #define IXGBE_EEPROM_GRANT_ATTEMPTS     1000 /* EEPROM attempts to gain grant */
2270 #endif
2271 
2272 /* Number of 5 microseconds we wait for EERD read and
2273  * EERW write to complete */
2274 #define IXGBE_EERD_EEWR_ATTEMPTS        100000
2275 
2276 /* # attempts we wait for flush update to complete */
2277 #define IXGBE_FLUDONE_ATTEMPTS          20000
2278 
2279 #define IXGBE_PCIE_CTRL2                0x5   /* PCIe Control 2 Offset */
2280 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE   0x8   /* Dummy Function Enable */
2281 #define IXGBE_PCIE_CTRL2_LAN_DISABLE    0x2   /* LAN PCI Disable */
2282 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1   /* LAN Disable Select */
2283 
2284 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET         0x0
2285 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET         0x3
2286 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP         0x1
2287 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS         0x2
2288 #define IXGBE_FW_LESM_PARAMETERS_PTR            0x2
2289 #define IXGBE_FW_LESM_STATE_1                   0x1
2290 #define IXGBE_FW_LESM_STATE_ENABLED             0x8000 /* LESM Enable bit */
2291 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
2292 #define IXGBE_FW_PATCH_VERSION_4                0x7
2293 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR             0x33 /* iSCSI/FCOE block */
2294 #define IXGBE_FCOE_IBA_CAPS_FCOE                0x20 /* FCOE flags */
2295 #define IXGBE_ISCSI_FCOE_BLK_PTR                0x17 /* iSCSI/FCOE block */
2296 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET           0x0 /* FCOE flags */
2297 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE           0x1 /* FCOE flags enable bit */
2298 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR          0x27 /* Alt. SAN MAC block */
2299 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET      0x0 /* Alt SAN MAC capability */
2300 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET     0x1 /* Alt SAN MAC 0 offset */
2301 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET     0x4 /* Alt SAN MAC 1 offset */
2302 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET      0x7 /* Alt WWNN prefix offset */
2303 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET      0x8 /* Alt WWPN prefix offset */
2304 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC      0x0 /* Alt SAN MAC exists */
2305 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN      0x1 /* Alt WWN base exists */
2306 
2307 /* FW header offset */
2308 #define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR      0x4
2309 #define IXGBE_X540_FW_MODULE_MASK                       0x7FFF
2310 /* 4KB multiplier */
2311 #define IXGBE_X540_FW_MODULE_LENGTH                     0x1000
2312 /* version word 2 (month & day) */
2313 #define IXGBE_X540_FW_PATCH_VERSION_2           0x5
2314 /* version word 3 (silicon compatibility & year) */
2315 #define IXGBE_X540_FW_PATCH_VERSION_3           0x6
2316 /* version word 4 (major & minor numbers) */
2317 #define IXGBE_X540_FW_PATCH_VERSION_4           0x7
2318 
2319 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1   0x4 /* WoL supported on ports 0 & 1 */
2320 #define IXGBE_DEVICE_CAPS_WOL_PORT0     0x8 /* WoL supported on port 0 */
2321 #define IXGBE_DEVICE_CAPS_WOL_MASK      0xC /* Mask for WoL capabilities */
2322 
2323 /* PCI Bus Info */
2324 #define IXGBE_PCI_DEVICE_STATUS         0xAA
2325 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING     0x0020
2326 #define IXGBE_PCI_LINK_STATUS           0xB2
2327 #define IXGBE_PCI_DEVICE_CONTROL2       0xC8
2328 #define IXGBE_PCI_LINK_WIDTH            0x3F0
2329 #define IXGBE_PCI_LINK_WIDTH_1          0x10
2330 #define IXGBE_PCI_LINK_WIDTH_2          0x20
2331 #define IXGBE_PCI_LINK_WIDTH_4          0x40
2332 #define IXGBE_PCI_LINK_WIDTH_8          0x80
2333 #define IXGBE_PCI_LINK_SPEED            0xF
2334 #define IXGBE_PCI_LINK_SPEED_2500       0x1
2335 #define IXGBE_PCI_LINK_SPEED_5000       0x2
2336 #define IXGBE_PCI_LINK_SPEED_8000       0x3
2337 #define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
2338 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
2339 #define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
2340 
2341 #define IXGBE_PCIDEVCTRL2_TIMEO_MASK    0xf
2342 #define IXGBE_PCIDEVCTRL2_16_32ms_def   0x0
2343 #define IXGBE_PCIDEVCTRL2_50_100us      0x1
2344 #define IXGBE_PCIDEVCTRL2_1_2ms         0x2
2345 #define IXGBE_PCIDEVCTRL2_16_32ms       0x5
2346 #define IXGBE_PCIDEVCTRL2_65_130ms      0x6
2347 #define IXGBE_PCIDEVCTRL2_260_520ms     0x9
2348 #define IXGBE_PCIDEVCTRL2_1_2s          0xa
2349 #define IXGBE_PCIDEVCTRL2_4_8s          0xd
2350 #define IXGBE_PCIDEVCTRL2_17_34s        0xe
2351 
2352 /* Number of 100 microseconds we wait for PCI Express master disable */
2353 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT        800
2354 
2355 /* Check whether address is multicast. This is little-endian specific check.*/
2356 #define IXGBE_IS_MULTICAST(Address) \
2357                 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
2358 
2359 /* Check whether an address is broadcast. */
2360 #define IXGBE_IS_BROADCAST(Address) \
2361                 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
2362                 (((u8 *)(Address))[1] == ((u8)0xff)))
2363 
2364 /* RAH */
2365 #define IXGBE_RAH_VIND_MASK     0x003C0000
2366 #define IXGBE_RAH_VIND_SHIFT    18
2367 #define IXGBE_RAH_AV            0x80000000
2368 #define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
2369 
2370 /* Header split receive */
2371 #define IXGBE_RFCTL_ISCSI_DIS           0x00000001
2372 #define IXGBE_RFCTL_ISCSI_DWC_MASK      0x0000003E
2373 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT     1
2374 #define IXGBE_RFCTL_RSC_DIS             0x00000020
2375 #define IXGBE_RFCTL_NFSW_DIS            0x00000040
2376 #define IXGBE_RFCTL_NFSR_DIS            0x00000080
2377 #define IXGBE_RFCTL_NFS_VER_MASK        0x00000300
2378 #define IXGBE_RFCTL_NFS_VER_SHIFT       8
2379 #define IXGBE_RFCTL_NFS_VER_2           0
2380 #define IXGBE_RFCTL_NFS_VER_3           1
2381 #define IXGBE_RFCTL_NFS_VER_4           2
2382 #define IXGBE_RFCTL_IPV6_DIS            0x00000400
2383 #define IXGBE_RFCTL_IPV6_XSUM_DIS       0x00000800
2384 #define IXGBE_RFCTL_IPFRSP_DIS          0x00004000
2385 #define IXGBE_RFCTL_IPV6_EX_DIS         0x00010000
2386 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
2387 
2388 /* Transmit Config masks */
2389 #define IXGBE_TXDCTL_ENABLE             0x02000000 /* Ena specific Tx Queue */
2390 #define IXGBE_TXDCTL_SWFLSH             0x04000000 /* Tx Desc. wr-bk flushing */
2391 #define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
2392 /* Enable short packet padding to 64 bytes */
2393 #define IXGBE_TX_PAD_ENABLE             0x00000400
2394 #define IXGBE_JUMBO_FRAME_ENABLE        0x00000004  /* Allow jumbo frames */
2395 /* This allows for 16K packets + 4k for vlan */
2396 #define IXGBE_MAX_FRAME_SZ              0x40040000
2397 
2398 #define IXGBE_TDWBAL_HEAD_WB_ENABLE     0x1 /* Tx head write-back enable */
2399 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE   0x2 /* Tx seq# write-back enable */
2400 
2401 /* Receive Config masks */
2402 #define IXGBE_RXCTRL_RXEN               0x00000001 /* Enable Receiver */
2403 #define IXGBE_RXCTRL_DMBYPS             0x00000002 /* Desc Monitor Bypass */
2404 #define IXGBE_RXDCTL_ENABLE             0x02000000 /* Ena specific Rx Queue */
2405 #define IXGBE_RXDCTL_SWFLSH             0x04000000 /* Rx Desc wr-bk flushing */
2406 #define IXGBE_RXDCTL_RLPMLMASK          0x00003FFF /* X540 supported only */
2407 #define IXGBE_RXDCTL_RLPML_EN           0x00008000
2408 #define IXGBE_RXDCTL_VME                0x40000000 /* VLAN mode enable */
2409 
2410 #define IXGBE_TSAUXC_EN_CLK             0x00000004
2411 #define IXGBE_TSAUXC_SYNCLK             0x00000008
2412 #define IXGBE_TSAUXC_SDP0_INT           0x00000040
2413 #define IXGBE_TSAUXC_EN_TT0             0x00000001
2414 #define IXGBE_TSAUXC_EN_TT1             0x00000002
2415 #define IXGBE_TSAUXC_ST0                0x00000010
2416 #define IXGBE_TSAUXC_DISABLE_SYSTIME    0x80000000
2417 
2418 #define IXGBE_TSSDP_TS_SDP0_SEL_MASK    0x000000C0
2419 #define IXGBE_TSSDP_TS_SDP0_CLK0        0x00000080
2420 #define IXGBE_TSSDP_TS_SDP0_EN          0x00000100
2421 
2422 #define IXGBE_TSYNCTXCTL_VALID          0x00000001 /* Tx timestamp valid */
2423 #define IXGBE_TSYNCTXCTL_ENABLED        0x00000010 /* Tx timestamping enabled */
2424 
2425 #define IXGBE_TSYNCRXCTL_VALID          0x00000001 /* Rx timestamp valid */
2426 #define IXGBE_TSYNCRXCTL_TYPE_MASK      0x0000000E /* Rx type mask */
2427 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2     0x00
2428 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1     0x02
2429 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2  0x04
2430 #define IXGBE_TSYNCRXCTL_TYPE_ALL       0x08
2431 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2  0x0A
2432 #define IXGBE_TSYNCRXCTL_ENABLED        0x00000010 /* Rx Timestamping enabled */
2433 #define IXGBE_TSYNCRXCTL_TSIP_UT_EN     0x00800000 /* Rx Timestamp in Packet */
2434 #define IXGBE_TSYNCRXCTL_TSIP_UP_MASK   0xFF000000 /* Rx Timestamp UP Mask */
2435 
2436 #define IXGBE_TSIM_SYS_WRAP             0x00000001
2437 #define IXGBE_TSIM_TXTS                 0x00000002
2438 #define IXGBE_TSIM_TADJ                 0x00000080
2439 
2440 #define IXGBE_TSICR_SYS_WRAP            IXGBE_TSIM_SYS_WRAP
2441 #define IXGBE_TSICR_TXTS                IXGBE_TSIM_TXTS
2442 #define IXGBE_TSICR_TADJ                IXGBE_TSIM_TADJ
2443 
2444 #define IXGBE_RXMTRL_V1_CTRLT_MASK      0x000000FF
2445 #define IXGBE_RXMTRL_V1_SYNC_MSG        0x00
2446 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG   0x01
2447 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG    0x02
2448 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG  0x03
2449 #define IXGBE_RXMTRL_V1_MGMT_MSG        0x04
2450 
2451 #define IXGBE_RXMTRL_V2_MSGID_MASK      0x0000FF00
2452 #define IXGBE_RXMTRL_V2_SYNC_MSG        0x0000
2453 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG   0x0100
2454 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG  0x0200
2455 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
2456 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG    0x0800
2457 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG  0x0900
2458 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
2459 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG    0x0B00
2460 #define IXGBE_RXMTRL_V2_SIGNALLING_MSG  0x0C00
2461 #define IXGBE_RXMTRL_V2_MGMT_MSG        0x0D00
2462 
2463 #define IXGBE_FCTRL_SBP         0x00000002 /* Store Bad Packet */


2481 #define IXGBE_MRQC_MRQE_MASK    0xF /* Bits 3:0 */
2482 #define IXGBE_MRQC_RT8TCEN      0x00000002 /* 8 TC no RSS */
2483 #define IXGBE_MRQC_RT4TCEN      0x00000003 /* 4 TC no RSS */
2484 #define IXGBE_MRQC_RTRSS8TCEN   0x00000004 /* 8 TC w/ RSS */
2485 #define IXGBE_MRQC_RTRSS4TCEN   0x00000005 /* 4 TC w/ RSS */
2486 #define IXGBE_MRQC_VMDQEN       0x00000008 /* VMDq2 64 pools no RSS */
2487 #define IXGBE_MRQC_VMDQRSS32EN  0x0000000A /* VMDq2 32 pools w/ RSS */
2488 #define IXGBE_MRQC_VMDQRSS64EN  0x0000000B /* VMDq2 64 pools w/ RSS */
2489 #define IXGBE_MRQC_VMDQRT8TCEN  0x0000000C /* VMDq2/RT 16 pool 8 TC */
2490 #define IXGBE_MRQC_VMDQRT4TCEN  0x0000000D /* VMDq2/RT 32 pool 4 TC */
2491 #define IXGBE_MRQC_RSS_FIELD_MASK       0xFFFF0000
2492 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP   0x00010000
2493 #define IXGBE_MRQC_RSS_FIELD_IPV4       0x00020000
2494 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2495 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX    0x00080000
2496 #define IXGBE_MRQC_RSS_FIELD_IPV6       0x00100000
2497 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP   0x00200000
2498 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP   0x00400000
2499 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP   0x00800000
2500 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2501 #define IXGBE_MRQC_MULTIPLE_RSS         0x00002000
2502 #define IXGBE_MRQC_L3L4TXSWEN           0x00008000
2503 
2504 /* Queue Drop Enable */
2505 #define IXGBE_QDE_ENABLE        0x00000001
2506 #define IXGBE_QDE_HIDE_VLAN     0x00000002
2507 #define IXGBE_QDE_IDX_MASK      0x00007F00
2508 #define IXGBE_QDE_IDX_SHIFT     8
2509 #define IXGBE_QDE_WRITE         0x00010000
2510 #define IXGBE_QDE_READ          0x00020000
2511 
2512 #define IXGBE_TXD_POPTS_IXSM    0x01 /* Insert IP checksum */
2513 #define IXGBE_TXD_POPTS_TXSM    0x02 /* Insert TCP/UDP checksum */
2514 #define IXGBE_TXD_CMD_EOP       0x01000000 /* End of Packet */
2515 #define IXGBE_TXD_CMD_IFCS      0x02000000 /* Insert FCS (Ethernet CRC) */
2516 #define IXGBE_TXD_CMD_IC        0x04000000 /* Insert Checksum */
2517 #define IXGBE_TXD_CMD_RS        0x08000000 /* Report Status */
2518 #define IXGBE_TXD_CMD_DEXT      0x20000000 /* Desc extension (0 = legacy) */
2519 #define IXGBE_TXD_CMD_VLE       0x40000000 /* Add VLAN tag */
2520 #define IXGBE_TXD_STAT_DD       0x00000001 /* Descriptor Done */
2521 
2522 #define IXGBE_RXDADV_IPSEC_STATUS_SECP          0x00020000
2523 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2524 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
2525 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED    0x18000000
2526 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000


2528 #define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
2529 #define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
2530 #define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
2531 #define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
2532 #define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
2533 #define IXGBE_MTQC_4TC_4TQ      0x8 /* 4 TC if RT_ENA and VT_ENA */
2534 #define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2535 
2536 /* Receive Descriptor bit definitions */
2537 #define IXGBE_RXD_STAT_DD       0x01 /* Descriptor Done */
2538 #define IXGBE_RXD_STAT_EOP      0x02 /* End of Packet */
2539 #define IXGBE_RXD_STAT_FLM      0x04 /* FDir Match */
2540 #define IXGBE_RXD_STAT_VP       0x08 /* IEEE VLAN Packet */
2541 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
2542 #define IXGBE_RXDADV_NEXTP_SHIFT        0x00000004
2543 #define IXGBE_RXD_STAT_UDPCS    0x10 /* UDP xsum calculated */
2544 #define IXGBE_RXD_STAT_L4CS     0x20 /* L4 xsum calculated */
2545 #define IXGBE_RXD_STAT_IPCS     0x40 /* IP xsum calculated */
2546 #define IXGBE_RXD_STAT_PIF      0x80 /* passed in-exact filter */
2547 #define IXGBE_RXD_STAT_CRCV     0x100 /* Speculative CRC Valid */
2548 #define IXGBE_RXD_STAT_OUTERIPCS        0x100 /* Cloud IP xsum calculated */
2549 #define IXGBE_RXD_STAT_VEXT     0x200 /* 1st VLAN found */
2550 #define IXGBE_RXD_STAT_UDPV     0x400 /* Valid UDP checksum */
2551 #define IXGBE_RXD_STAT_DYNINT   0x800 /* Pkt caused INT via DYNINT */
2552 #define IXGBE_RXD_STAT_LLINT    0x800 /* Pkt caused Low Latency Interrupt */
2553 #define IXGBE_RXD_STAT_TSIP     0x08000 /* Time Stamp in packet buffer */
2554 #define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
2555 #define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
2556 #define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
2557 #define IXGBE_RXD_STAT_ACK      0x8000 /* ACK Packet indication */
2558 #define IXGBE_RXD_ERR_CE        0x01 /* CRC Error */
2559 #define IXGBE_RXD_ERR_LE        0x02 /* Length Error */
2560 #define IXGBE_RXD_ERR_PE        0x08 /* Packet Error */
2561 #define IXGBE_RXD_ERR_OSE       0x10 /* Oversize Error */
2562 #define IXGBE_RXD_ERR_USE       0x20 /* Undersize Error */
2563 #define IXGBE_RXD_ERR_TCPE      0x40 /* TCP/UDP Checksum Error */
2564 #define IXGBE_RXD_ERR_IPE       0x80 /* IP Checksum Error */
2565 #define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
2566 #define IXGBE_RXDADV_ERR_SHIFT          20 /* RDESC.ERRORS shift */
2567 #define IXGBE_RXDADV_ERR_OUTERIPER      0x04000000 /* CRC IP Header error */
2568 #define IXGBE_RXDADV_ERR_RXE            0x20000000 /* Any MAC Error */
2569 #define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCEOFe/IPE */
2570 #define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
2571 #define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
2572 #define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
2573 #define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
2574 #define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
2575 #define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
2576 #define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
2577 #define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
2578 #define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
2579 #define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
2580 #define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
2581 #define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
2582 #define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
2583 #define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
2584 #define IXGBE_RXD_PRI_SHIFT     13
2585 #define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
2586 #define IXGBE_RXD_CFI_SHIFT     12
2587 
2588 #define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
2589 #define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
2590 #define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
2591 #define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
2592 #define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
2593 #define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
2594 #define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
2595 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2596 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
2597 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2598 #define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
2599 #define IXGBE_RXDADV_STAT_TS            0x00010000 /* IEEE1588 Time Stamp */
2600 #define IXGBE_RXDADV_STAT_TSIP          0x00008000 /* Time Stamp in packet buffer */
2601 
2602 /* PSRTYPE bit definitions */
2603 #define IXGBE_PSRTYPE_TCPHDR    0x00000010
2604 #define IXGBE_PSRTYPE_UDPHDR    0x00000020
2605 #define IXGBE_PSRTYPE_IPV4HDR   0x00000100
2606 #define IXGBE_PSRTYPE_IPV6HDR   0x00000200
2607 #define IXGBE_PSRTYPE_L2HDR     0x00001000
2608 
2609 /* SRRCTL bit definitions */
2610 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10 /* so many KBs */
2611 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* 64byte resolution (>> 6)
2612                                            * + at bit 8 offset (<< 8)
2613                                            *  = (<< 2)
2614                                            */
2615 #define IXGBE_SRRCTL_RDMTS_SHIFT        22
2616 #define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
2617 #define IXGBE_SRRCTL_DROP_EN            0x10000000
2618 #define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
2619 #define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
2620 #define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
2621 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2622 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2623 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2624 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2625 #define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
2626 
2627 #define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
2628 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2629 
2630 #define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
2631 #define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
2632 #define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
2633 #define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
2634 #define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000


2642 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
2643 #define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
2644 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
2645 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
2646 #define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
2647 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2648 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
2649 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
2650 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2651 
2652 /* RSS Packet Types as indicated in the receive descriptor. */
2653 #define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
2654 #define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
2655 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
2656 #define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
2657 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
2658 #define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
2659 #define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
2660 #define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
2661 #define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
2662 #define IXGBE_RXDADV_PKTTYPE_VXLAN      0x00000800 /* VXLAN hdr present */
2663 #define IXGBE_RXDADV_PKTTYPE_TUNNEL     0x00010000 /* Tunnel type */
2664 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
2665 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
2666 #define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
2667 #define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
2668 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
2669 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
2670 
2671 /* Security Processing bit Indication */
2672 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP         0x00020000
2673 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
2674 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
2675 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
2676 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
2677 
2678 /* Masks to determine if packets should be dropped due to frame errors */
2679 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2680                                 IXGBE_RXD_ERR_CE | \
2681                                 IXGBE_RXD_ERR_LE | \
2682                                 IXGBE_RXD_ERR_PE | \
2683                                 IXGBE_RXD_ERR_OSE | \


2694 
2695 /* Multicast bit mask */
2696 #define IXGBE_MCSTCTRL_MFE      0x4
2697 
2698 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2699 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE        8
2700 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE        8
2701 #define IXGBE_REQ_TX_BUFFER_GRANULARITY         1024
2702 
2703 /* Vlan-specific macros */
2704 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
2705 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK  0xE000 /* Priority in upper 3 bits */
2706 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
2707 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2708 
2709 /* SR-IOV specific macros */
2710 #define IXGBE_MBVFICR_INDEX(vf_number)  (vf_number >> 4)
2711 #define IXGBE_MBVFICR(_i)               (0x00710 + ((_i) * 4))
2712 #define IXGBE_VFLRE(_i)                 (((_i & 1) ? 0x001C0 : 0x00600))
2713 #define IXGBE_VFLREC(_i)                 (0x00700 + ((_i) * 4))
2714 /* Translated register #defines */
2715 #define IXGBE_PVFCTRL(P)        (0x00300 + (4 * (P)))
2716 #define IXGBE_PVFSTATUS(P)      (0x00008 + (0 * (P)))
2717 #define IXGBE_PVFLINKS(P)       (0x042A4 + (0 * (P)))
2718 #define IXGBE_PVFRTIMER(P)      (0x00048 + (0 * (P)))
2719 #define IXGBE_PVFMAILBOX(P)     (0x04C00 + (4 * (P)))
2720 #define IXGBE_PVFRXMEMWRAP(P)   (0x03190 + (0 * (P)))
2721 #define IXGBE_PVTEICR(P)        (0x00B00 + (4 * (P)))
2722 #define IXGBE_PVTEICS(P)        (0x00C00 + (4 * (P)))
2723 #define IXGBE_PVTEIMS(P)        (0x00D00 + (4 * (P)))
2724 #define IXGBE_PVTEIMC(P)        (0x00E00 + (4 * (P)))
2725 #define IXGBE_PVTEIAC(P)        (0x00F00 + (4 * (P)))
2726 #define IXGBE_PVTEIAM(P)        (0x04D00 + (4 * (P)))
2727 #define IXGBE_PVTEITR(P)        (((P) < 24) ? (0x00820 + ((P) * 4)) : \
2728                                  (0x012300 + (((P) - 24) * 4)))
2729 #define IXGBE_PVTIVAR(P)        (0x12500 + (4 * (P)))
2730 #define IXGBE_PVTIVAR_MISC(P)   (0x04E00 + (4 * (P)))
2731 #define IXGBE_PVTRSCINT(P)      (0x12000 + (4 * (P)))
2732 #define IXGBE_VFPBACL(P)        (0x110C8 + (4 * (P)))
2733 #define IXGBE_PVFRDBAL(P)       ((P < 64) ? (0x01000 + (0x40 * (P))) \
2734                                  : (0x0D000 + (0x40 * ((P) - 64))))
2735 #define IXGBE_PVFRDBAH(P)       ((P < 64) ? (0x01004 + (0x40 * (P))) \
2736                                  : (0x0D004 + (0x40 * ((P) - 64))))
2737 #define IXGBE_PVFRDLEN(P)       ((P < 64) ? (0x01008 + (0x40 * (P))) \
2738                                  : (0x0D008 + (0x40 * ((P) - 64))))
2739 #define IXGBE_PVFRDH(P)         ((P < 64) ? (0x01010 + (0x40 * (P))) \
2740                                  : (0x0D010 + (0x40 * ((P) - 64))))
2741 #define IXGBE_PVFRDT(P)         ((P < 64) ? (0x01018 + (0x40 * (P))) \
2742                                  : (0x0D018 + (0x40 * ((P) - 64))))
2743 #define IXGBE_PVFRXDCTL(P)      ((P < 64) ? (0x01028 + (0x40 * (P))) \
2744                                  : (0x0D028 + (0x40 * ((P) - 64))))
2745 #define IXGBE_PVFSRRCTL(P)      ((P < 64) ? (0x01014 + (0x40 * (P))) \
2746                                  : (0x0D014 + (0x40 * ((P) - 64))))
2747 #define IXGBE_PVFPSRTYPE(P)     (0x0EA00 + (4 * (P)))
2748 #define IXGBE_PVFTDBAL(P)       (0x06000 + (0x40 * (P)))
2749 #define IXGBE_PVFTDBAH(P)       (0x06004 + (0x40 * (P)))
2750 #define IXGBE_PVFTTDLEN(P)      (0x06008 + (0x40 * (P)))
2751 #define IXGBE_PVFTDH(P)         (0x06010 + (0x40 * (P)))
2752 #define IXGBE_PVFTDT(P)         (0x06018 + (0x40 * (P)))
2753 #define IXGBE_PVFTXDCTL(P)      (0x06028 + (0x40 * (P)))
2754 #define IXGBE_PVFTDWBAL(P)      (0x06038 + (0x40 * (P)))
2755 #define IXGBE_PVFTDWBAH(P)      (0x0603C + (0x40 * (P)))
2756 #define IXGBE_PVFDCA_RXCTRL(P)  (((P) < 64) ? (0x0100C + (0x40 * (P))) \
2757                                  : (0x0D00C + (0x40 * ((P) - 64))))
2758 #define IXGBE_PVFDCA_TXCTRL(P)  (0x0600C + (0x40 * (P)))
2759 #define IXGBE_PVFGPRC(x)        (0x0101C + (0x40 * (x)))
2760 #define IXGBE_PVFGPTC(x)        (0x08300 + (0x04 * (x)))
2761 #define IXGBE_PVFGORC_LSB(x)    (0x01020 + (0x40 * (x)))
2762 #define IXGBE_PVFGORC_MSB(x)    (0x0D020 + (0x40 * (x)))
2763 #define IXGBE_PVFGOTC_LSB(x)    (0x08400 + (0x08 * (x)))
2764 #define IXGBE_PVFGOTC_MSB(x)    (0x08404 + (0x08 * (x)))
2765 #define IXGBE_PVFMPRC(x)        (0x0D01C + (0x40 * (x)))
2766 
2767 #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2768                 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2769 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2770                 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2771 
2772 #define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \
2773                 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2774 #define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \
2775                 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2776 
2777 /* Little Endian defines */
2778 #ifndef __le16
2779 #define __le16  u16
2780 #endif
2781 #ifndef __le32
2782 #define __le32  u32
2783 #endif
2784 #ifndef __le64
2785 #define __le64  u64
2786 
2787 #endif
2788 #ifndef __be16
2789 /* Big Endian defines */
2790 #define __be16  u16
2791 #define __be32  u32
2792 #define __be64  u64
2793 
2794 #endif
2795 enum ixgbe_fdir_pballoc_type {
2796         IXGBE_FDIR_PBALLOC_NONE = 0,
2797         IXGBE_FDIR_PBALLOC_64K  = 1,
2798         IXGBE_FDIR_PBALLOC_128K = 2,
2799         IXGBE_FDIR_PBALLOC_256K = 3,
2800 };
2801 
2802 /* Flow Director register values */
2803 #define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
2804 #define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
2805 #define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
2806 #define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
2807 #define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
2808 #define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
2809 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
2810 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
2811 #define IXGBE_FDIRCTRL_DROP_Q_MASK              0x00007F00
2812 #define IXGBE_FDIRCTRL_FLEX_SHIFT               16
2813 #define IXGBE_FDIRCTRL_DROP_NO_MATCH            0x00008000
2814 #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT         21
2815 #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN       0x0001 /* bit 23:21, 001b */
2816 #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD         0x0002 /* bit 23:21, 010b */
2817 #define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
2818 #define IXGBE_FDIRCTRL_FILTERMODE_MASK          0x00E00000
2819 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
2820 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
2821 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
2822 
2823 #define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
2824 #define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
2825 #define IXGBE_FDIRIP6M_DIPM_SHIFT               16
2826 #define IXGBE_FDIRM_VLANID                      0x00000001
2827 #define IXGBE_FDIRM_VLANP                       0x00000002
2828 #define IXGBE_FDIRM_POOL                        0x00000004
2829 #define IXGBE_FDIRM_L4P                         0x00000008
2830 #define IXGBE_FDIRM_FLEX                        0x00000010
2831 #define IXGBE_FDIRM_DIPv6                       0x00000020
2832 #define IXGBE_FDIRM_L3P                         0x00000040
2833 
2834 #define IXGBE_FDIRIP6M_INNER_MAC        0x03F0 /* bit 9:4 */
2835 #define IXGBE_FDIRIP6M_TUNNEL_TYPE      0x0800 /* bit 11 */
2836 #define IXGBE_FDIRIP6M_TNI_VNI          0xF000 /* bit 15:12 */
2837 #define IXGBE_FDIRIP6M_TNI_VNI_24       0x1000 /* bit 12 */
2838 #define IXGBE_FDIRIP6M_ALWAYS_MASK      0x040F /* bit 10, 3:0 */
2839 
2840 #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
2841 #define IXGBE_FDIRFREE_FREE_SHIFT               0
2842 #define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
2843 #define IXGBE_FDIRFREE_COLL_SHIFT               16
2844 #define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
2845 #define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
2846 #define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
2847 #define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
2848 #define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
2849 #define IXGBE_FDIRUSTAT_ADD_SHIFT               0
2850 #define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
2851 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
2852 #define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
2853 #define IXGBE_FDIRFSTAT_FADD_SHIFT              0
2854 #define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
2855 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
2856 #define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
2857 #define IXGBE_FDIRVLAN_FLEX_SHIFT               16
2858 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
2859 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
2860 
2861 #define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
2862 #define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
2863 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
2864 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
2865 #define IXGBE_FDIRCMD_FILTER_VALID              0x00000004
2866 #define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
2867 #define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
2868 #define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
2869 #define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
2870 #define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
2871 #define IXGBE_FDIRCMD_IPV6                      0x00000080
2872 #define IXGBE_FDIRCMD_CLEARHT                   0x00000100
2873 #define IXGBE_FDIRCMD_DROP                      0x00000200
2874 #define IXGBE_FDIRCMD_INT                       0x00000400
2875 #define IXGBE_FDIRCMD_LAST                      0x00000800
2876 #define IXGBE_FDIRCMD_COLLISION                 0x00001000
2877 #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
2878 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
2879 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
2880 #define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT       23
2881 #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
2882 #define IXGBE_FDIR_INIT_DONE_POLL               10
2883 #define IXGBE_FDIRCMD_CMD_POLL                  10
2884 #define IXGBE_FDIRCMD_TUNNEL_FILTER             0x00800000
2885 #define IXGBE_FDIR_DROP_QUEUE                   127
2886 

2887 
2888 /* Manageablility Host Interface defines */
2889 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH  1792 /* Num of bytes in range */
2890 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
2891 #define IXGBE_HI_COMMAND_TIMEOUT        500 /* Process HI command limit */
2892 #define IXGBE_HI_FLASH_ERASE_TIMEOUT    1000 /* Process Erase command limit */
2893 #define IXGBE_HI_FLASH_UPDATE_TIMEOUT   5000 /* Process Update command limit */
2894 #define IXGBE_HI_FLASH_APPLY_TIMEOUT    0 /* Process Apply command limit */
2895 #define IXGBE_HI_PHY_MGMT_REQ_TIMEOUT   2000 /* Wait up to 2 seconds */
2896 
2897 /* CEM Support */
2898 #define FW_CEM_HDR_LEN                  0x4
2899 #define FW_CEM_CMD_DRIVER_INFO          0xDD
2900 #define FW_CEM_CMD_DRIVER_INFO_LEN      0x5
2901 #define FW_CEM_CMD_RESERVED             0X0
2902 #define FW_CEM_UNUSED_VER               0x0
2903 #define FW_CEM_MAX_RETRIES              3
2904 #define FW_CEM_RESP_STATUS_SUCCESS      0x1
2905 #define FW_READ_SHADOW_RAM_CMD          0x31
2906 #define FW_READ_SHADOW_RAM_LEN          0x6
2907 #define FW_WRITE_SHADOW_RAM_CMD         0x33
2908 #define FW_WRITE_SHADOW_RAM_LEN         0xA /* 8 plus 1 WORD to write */
2909 #define FW_SHADOW_RAM_DUMP_CMD          0x36
2910 #define FW_SHADOW_RAM_DUMP_LEN          0
2911 #define FW_DEFAULT_CHECKSUM             0xFF /* checksum always 0xFF */
2912 #define FW_NVM_DATA_OFFSET              3
2913 #define FW_MAX_READ_BUFFER_SIZE         1024
2914 #define FW_DISABLE_RXEN_CMD             0xDE
2915 #define FW_DISABLE_RXEN_LEN             0x1
2916 #define FW_PHY_MGMT_REQ_CMD             0x20
2917 #define FW_INT_PHY_REQ_CMD              0xB
2918 #define FW_INT_PHY_REQ_LEN              10
2919 #define FW_INT_PHY_REQ_READ             0
2920 #define FW_INT_PHY_REQ_WRITE            1
2921 
2922 /* Host Interface Command Structures */
2923 
2924 struct ixgbe_hic_hdr {
2925         u8 cmd;
2926         u8 buf_len;
2927         union {
2928                 u8 cmd_resv;
2929                 u8 ret_status;
2930         } cmd_or_resp;
2931         u8 checksum;
2932 };
2933 
2934 struct ixgbe_hic_hdr2_req {
2935         u8 cmd;
2936         u8 buf_lenh;
2937         u8 buf_lenl;
2938         u8 checksum;
2939 };
2940 
2941 struct ixgbe_hic_hdr2_rsp {
2942         u8 cmd;
2943         u8 buf_lenl;
2944         u8 buf_lenh_status;     /* 7-5: high bits of buf_len, 4-0: status */
2945         u8 checksum;
2946 };
2947 
2948 union ixgbe_hic_hdr2 {
2949         struct ixgbe_hic_hdr2_req req;
2950         struct ixgbe_hic_hdr2_rsp rsp;
2951 };
2952 
2953 struct ixgbe_hic_drv_info {
2954         struct ixgbe_hic_hdr hdr;
2955         u8 port_num;
2956         u8 ver_sub;
2957         u8 ver_build;
2958         u8 ver_min;
2959         u8 ver_maj;
2960         u8 pad; /* end spacing to ensure length is mult. of dword */
2961         u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2962 };
2963 
2964 /* These need to be dword aligned */
2965 struct ixgbe_hic_read_shadow_ram {
2966         union ixgbe_hic_hdr2 hdr;
2967         u32 address;
2968         u16 length;
2969         u16 pad2;
2970         u16 data;
2971         u16 pad3;
2972 };
2973 
2974 struct ixgbe_hic_write_shadow_ram {
2975         union ixgbe_hic_hdr2 hdr;
2976         u32 address;
2977         u16 length;
2978         u16 pad2;
2979         u16 data;
2980         u16 pad3;
2981 };
2982 
2983 struct ixgbe_hic_disable_rxen {
2984         struct ixgbe_hic_hdr hdr;
2985         u8  port_number;
2986         u8  pad2;
2987         u16 pad3;
2988 };
2989 
2990 struct ixgbe_hic_internal_phy_req {
2991         struct ixgbe_hic_hdr hdr;
2992         u8 port_number;
2993         u8 command_type;
2994         u16 address;
2995         u16 rsv1;
2996         u32 write_data;
2997         u16 pad;
2998 };
2999 
3000 struct ixgbe_hic_internal_phy_resp {
3001         struct ixgbe_hic_hdr hdr;
3002         u32 read_data;
3003 };
3004 
3005 
3006 /* Transmit Descriptor - Legacy */
3007 struct ixgbe_legacy_tx_desc {
3008         u64 buffer_addr; /* Address of the descriptor's data buffer */
3009         union {
3010                 __le32 data;
3011                 struct {
3012                         __le16 length; /* Data buffer length */
3013                         u8 cso; /* Checksum offset */
3014                         u8 cmd; /* Descriptor control */
3015                 } flags;
3016         } lower;
3017         union {
3018                 __le32 data;
3019                 struct {
3020                         u8 status; /* Descriptor status */
3021                         u8 css; /* Checksum start */
3022                         __le16 vlan;
3023                 } fields;
3024         } upper;
3025 };


3127 #define IXGBE_ADVTXD_TUCMD_L4T_UDP      0x00000000 /* L4 Packet TYPE of UDP */
3128 #define IXGBE_ADVTXD_TUCMD_L4T_TCP      0x00000800 /* L4 Packet TYPE of TCP */
3129 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP     0x00001000 /* L4 Packet TYPE of SCTP */
3130 #define IXGBE_ADVTXD_TUCMD_MKRREQ       0x00002000 /* req Markers and CRC */
3131 #define IXGBE_ADVTXD_POPTS_IPSEC        0x00000400 /* IPSec offload request */
3132 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
3133 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
3134 #define IXGBE_ADVTXT_TUCMD_FCOE         0x00008000 /* FCoE Frame Type */
3135 #define IXGBE_ADVTXD_FCOEF_EOF_MASK     (0x3 << 10) /* FC EOF index */
3136 #define IXGBE_ADVTXD_FCOEF_SOF          ((1 << 2) << 10) /* FC SOF index */
3137 #define IXGBE_ADVTXD_FCOEF_PARINC       ((1 << 3) << 10) /* Rel_Off in F_CTL */
3138 #define IXGBE_ADVTXD_FCOEF_ORIE         ((1 << 4) << 10) /* Orientation End */
3139 #define IXGBE_ADVTXD_FCOEF_ORIS         ((1 << 5) << 10) /* Orientation Start */
3140 #define IXGBE_ADVTXD_FCOEF_EOF_N        (0x0 << 10) /* 00: EOFn */
3141 #define IXGBE_ADVTXD_FCOEF_EOF_T        (0x1 << 10) /* 01: EOFt */
3142 #define IXGBE_ADVTXD_FCOEF_EOF_NI       (0x2 << 10) /* 10: EOFni */
3143 #define IXGBE_ADVTXD_FCOEF_EOF_A        (0x3 << 10) /* 11: EOFa */
3144 #define IXGBE_ADVTXD_L4LEN_SHIFT        8  /* Adv ctxt L4LEN shift */
3145 #define IXGBE_ADVTXD_MSS_SHIFT          16  /* Adv ctxt MSS shift */
3146 
3147 #define IXGBE_ADVTXD_OUTER_IPLEN        16 /* Adv ctxt OUTERIPLEN shift */
3148 #define IXGBE_ADVTXD_TUNNEL_LEN         24 /* Adv ctxt TUNNELLEN shift */
3149 #define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT  16 /* Adv Tx Desc Tunnel Type shift */
3150 #define IXGBE_ADVTXD_OUTERIPCS_SHIFT    17 /* Adv Tx Desc OUTERIPCS Shift */
3151 #define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE  1  /* Adv Tx Desc Tunnel Type NVGRE */
3152 
3153 /* Autonegotiation advertised speeds */
3154 typedef u32 ixgbe_autoneg_advertised;
3155 /* Link speed */
3156 typedef u32 ixgbe_link_speed;
3157 #define IXGBE_LINK_SPEED_UNKNOWN        0
3158 #define IXGBE_LINK_SPEED_100_FULL       0x0008
3159 #define IXGBE_LINK_SPEED_1GB_FULL       0x0020
3160 #define IXGBE_LINK_SPEED_2_5GB_FULL     0x0400
3161 #define IXGBE_LINK_SPEED_5GB_FULL       0x0800
3162 #define IXGBE_LINK_SPEED_10GB_FULL      0x0080
3163 #define IXGBE_LINK_SPEED_82598_AUTONEG  (IXGBE_LINK_SPEED_1GB_FULL | \
3164                                          IXGBE_LINK_SPEED_10GB_FULL)
3165 #define IXGBE_LINK_SPEED_82599_AUTONEG  (IXGBE_LINK_SPEED_100_FULL | \
3166                                          IXGBE_LINK_SPEED_1GB_FULL | \
3167                                          IXGBE_LINK_SPEED_10GB_FULL)
3168 

3169 /* Physical layer type */
3170 typedef u32 ixgbe_physical_layer;
3171 #define IXGBE_PHYSICAL_LAYER_UNKNOWN            0
3172 #define IXGBE_PHYSICAL_LAYER_10GBASE_T          0x0001
3173 #define IXGBE_PHYSICAL_LAYER_1000BASE_T         0x0002
3174 #define IXGBE_PHYSICAL_LAYER_100BASE_TX         0x0004
3175 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU        0x0008
3176 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR         0x0010
3177 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM        0x0020
3178 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR         0x0040
3179 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4        0x0080
3180 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4        0x0100
3181 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX        0x0200
3182 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX        0x0400
3183 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR         0x0800
3184 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI       0x1000
3185 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA      0x2000
3186 #define IXGBE_PHYSICAL_LAYER_1000BASE_SX        0x4000
3187 
3188 /* Flow Control Data Sheet defined values


3241                          2 * IXGBE_B2BT(_max_frame_tc))
3242 
3243 /* Calculate low threshold delay values */
3244 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
3245                         (2 * IXGBE_B2BT(_max_frame_tc) + \
3246                         (36 * IXGBE_PCI_DELAY / 25) + 1)
3247 #define IXGBE_LOW_DV(_max_frame_tc) \
3248                         (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
3249 
3250 /* Software ATR hash keys */
3251 #define IXGBE_ATR_BUCKET_HASH_KEY       0x3DAD14E2
3252 #define IXGBE_ATR_SIGNATURE_HASH_KEY    0x174D3614
3253 
3254 /* Software ATR input stream values and masks */
3255 #define IXGBE_ATR_HASH_MASK             0x7fff
3256 #define IXGBE_ATR_L4TYPE_MASK           0x3
3257 #define IXGBE_ATR_L4TYPE_UDP            0x1
3258 #define IXGBE_ATR_L4TYPE_TCP            0x2
3259 #define IXGBE_ATR_L4TYPE_SCTP           0x3
3260 #define IXGBE_ATR_L4TYPE_IPV6_MASK      0x4
3261 #define IXGBE_ATR_L4TYPE_TUNNEL_MASK    0x10
3262 enum ixgbe_atr_flow_type {
3263         IXGBE_ATR_FLOW_TYPE_IPV4        = 0x0,
3264         IXGBE_ATR_FLOW_TYPE_UDPV4       = 0x1,
3265         IXGBE_ATR_FLOW_TYPE_TCPV4       = 0x2,
3266         IXGBE_ATR_FLOW_TYPE_SCTPV4      = 0x3,
3267         IXGBE_ATR_FLOW_TYPE_IPV6        = 0x4,
3268         IXGBE_ATR_FLOW_TYPE_UDPV6       = 0x5,
3269         IXGBE_ATR_FLOW_TYPE_TCPV6       = 0x6,
3270         IXGBE_ATR_FLOW_TYPE_SCTPV6      = 0x7,
3271         IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4       = 0x10,
3272         IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4      = 0x11,
3273         IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4      = 0x12,
3274         IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4     = 0x13,
3275         IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6       = 0x14,
3276         IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6      = 0x15,
3277         IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6      = 0x16,
3278         IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6     = 0x17,
3279 };
3280 
3281 /* Flow Director ATR input struct. */
3282 union ixgbe_atr_input {
3283         /*
3284          * Byte layout in order, all values with MSB first:
3285          *
3286          * vm_pool      - 1 byte
3287          * flow_type    - 1 byte
3288          * vlan_id      - 2 bytes
3289          * src_ip       - 16 bytes
3290          * inner_mac    - 6 bytes
3291          * cloud_mode   - 2 bytes
3292          * tni_vni      - 4 bytes
3293          * dst_ip       - 16 bytes
3294          * src_port     - 2 bytes
3295          * dst_port     - 2 bytes
3296          * flex_bytes   - 2 bytes
3297          * bkt_hash     - 2 bytes
3298          */
3299         struct {
3300                 u8 vm_pool;
3301                 u8 flow_type;
3302                 __be16 vlan_id;
3303                 __be32 dst_ip[4];
3304                 __be32 src_ip[4];
3305                 u8 inner_mac[6];
3306                 __be16 tunnel_type;
3307                 __be32 tni_vni;
3308                 __be16 src_port;
3309                 __be16 dst_port;
3310                 __be16 flex_bytes;
3311                 __be16 bkt_hash;
3312         } formatted;
3313         __be32 dword_stream[14];
3314 };
3315 
3316 /* Flow Director compressed ATR hash input struct */
3317 union ixgbe_atr_hash_dword {
3318         struct {
3319                 u8 vm_pool;
3320                 u8 flow_type;
3321                 __be16 vlan_id;
3322         } formatted;
3323         __be32 ip;
3324         struct {
3325                 __be16 src;
3326                 __be16 dst;
3327         } port;
3328         __be16 flex_bytes;
3329         __be32 dword;
3330 };
3331 
3332 
3333 #define IXGBE_MVALS_INIT(m)     \
3334         IXGBE_CAT(EEC, m),              \
3335         IXGBE_CAT(FLA, m),              \
3336         IXGBE_CAT(GRC, m),              \
3337         IXGBE_CAT(SRAMREL, m),          \
3338         IXGBE_CAT(FACTPS, m),           \
3339         IXGBE_CAT(SWSM, m),             \
3340         IXGBE_CAT(SWFW_SYNC, m),        \
3341         IXGBE_CAT(FWSM, m),             \
3342         IXGBE_CAT(SDP0_GPIEN, m),       \
3343         IXGBE_CAT(SDP1_GPIEN, m),       \
3344         IXGBE_CAT(SDP2_GPIEN, m),       \
3345         IXGBE_CAT(EICR_GPI_SDP0, m),    \
3346         IXGBE_CAT(EICR_GPI_SDP1, m),    \
3347         IXGBE_CAT(EICR_GPI_SDP2, m),    \
3348         IXGBE_CAT(CIAA, m),             \
3349         IXGBE_CAT(CIAD, m),             \
3350         IXGBE_CAT(I2C_CLK_IN, m),       \
3351         IXGBE_CAT(I2C_CLK_OUT, m),      \
3352         IXGBE_CAT(I2C_DATA_IN, m),      \
3353         IXGBE_CAT(I2C_DATA_OUT, m),     \
3354         IXGBE_CAT(I2C_DATA_OE_N_EN, m), \
3355         IXGBE_CAT(I2C_BB_EN, m),        \
3356         IXGBE_CAT(I2C_CLK_OE_N_EN, m),  \
3357         IXGBE_CAT(I2CCTL, m)
3358 
3359 enum ixgbe_mvals {
3360         IXGBE_MVALS_INIT(_IDX),
3361         IXGBE_MVALS_IDX_LIMIT
3362 };
3363 
3364 /*
3365  * Unavailable: The FCoE Boot Option ROM is not present in the flash.
3366  * Disabled: Present; boot order is not set for any targets on the port.
3367  * Enabled: Present; boot order is set for at least one target on the port.
3368  */
3369 enum ixgbe_fcoe_boot_status {
3370         ixgbe_fcoe_bootstatus_disabled = 0,
3371         ixgbe_fcoe_bootstatus_enabled = 1,
3372         ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
3373 };
3374 
3375 enum ixgbe_eeprom_type {
3376         ixgbe_eeprom_uninitialized = 0,
3377         ixgbe_eeprom_spi,
3378         ixgbe_flash,
3379         ixgbe_eeprom_none /* No NVM support */
3380 };
3381 
3382 enum ixgbe_mac_type {
3383         ixgbe_mac_unknown = 0,
3384         ixgbe_mac_82598EB,
3385         ixgbe_mac_82599EB,
3386         ixgbe_mac_82599_vf,
3387         ixgbe_mac_X540,
3388         ixgbe_mac_X540_vf,
3389         ixgbe_mac_X550,
3390         ixgbe_mac_X550EM_x,
3391         ixgbe_mac_X550_vf,
3392         ixgbe_mac_X550EM_x_vf,
3393         ixgbe_num_macs
3394 };
3395 
3396 enum ixgbe_phy_type {
3397         ixgbe_phy_unknown = 0,
3398         ixgbe_phy_none,
3399         ixgbe_phy_tn,
3400         ixgbe_phy_aq,
3401         ixgbe_phy_x550em_kr,
3402         ixgbe_phy_x550em_kx4,
3403         ixgbe_phy_x550em_ext_t,
3404         ixgbe_phy_cu_unknown,
3405         ixgbe_phy_qt,
3406         ixgbe_phy_xaui,
3407         ixgbe_phy_nl,
3408         ixgbe_phy_sfp_passive_tyco,
3409         ixgbe_phy_sfp_passive_unknown,
3410         ixgbe_phy_sfp_active_unknown,
3411         ixgbe_phy_sfp_avago,
3412         ixgbe_phy_sfp_ftl,
3413         ixgbe_phy_sfp_ftl_active,
3414         ixgbe_phy_sfp_unknown,
3415         ixgbe_phy_sfp_intel,
3416         ixgbe_phy_qsfp_passive_unknown,
3417         ixgbe_phy_qsfp_active_unknown,
3418         ixgbe_phy_qsfp_intel,
3419         ixgbe_phy_qsfp_unknown,
3420         ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
3421         ixgbe_phy_generic
3422 };
3423 
3424 /*
3425  * SFP+ module type IDs:
3426  *
3427  * ID   Module Type
3428  * =============
3429  * 0    SFP_DA_CU
3430  * 1    SFP_SR
3431  * 2    SFP_LR
3432  * 3    SFP_DA_CU_CORE0 - 82599-specific
3433  * 4    SFP_DA_CU_CORE1 - 82599-specific
3434  * 5    SFP_SR/LR_CORE0 - 82599-specific
3435  * 6    SFP_SR/LR_CORE1 - 82599-specific
3436  */
3437 enum ixgbe_sfp_type {
3438         ixgbe_sfp_type_da_cu = 0,
3439         ixgbe_sfp_type_sr = 1,
3440         ixgbe_sfp_type_lr = 2,
3441         ixgbe_sfp_type_da_cu_core0 = 3,
3442         ixgbe_sfp_type_da_cu_core1 = 4,
3443         ixgbe_sfp_type_srlr_core0 = 5,
3444         ixgbe_sfp_type_srlr_core1 = 6,
3445         ixgbe_sfp_type_da_act_lmt_core0 = 7,
3446         ixgbe_sfp_type_da_act_lmt_core1 = 8,
3447         ixgbe_sfp_type_1g_cu_core0 = 9,
3448         ixgbe_sfp_type_1g_cu_core1 = 10,
3449         ixgbe_sfp_type_1g_sx_core0 = 11,
3450         ixgbe_sfp_type_1g_sx_core1 = 12,
3451         ixgbe_sfp_type_1g_lx_core0 = 13,
3452         ixgbe_sfp_type_1g_lx_core1 = 14,
3453         ixgbe_sfp_type_not_present = 0xFFFE,
3454         ixgbe_sfp_type_unknown = 0xFFFF
3455 };
3456 
3457 enum ixgbe_media_type {
3458         ixgbe_media_type_unknown = 0,
3459         ixgbe_media_type_fiber,
3460         ixgbe_media_type_fiber_fixed,
3461         ixgbe_media_type_fiber_qsfp,
3462         ixgbe_media_type_copper,
3463         ixgbe_media_type_backplane,
3464         ixgbe_media_type_cx4,
3465         ixgbe_media_type_virtual
3466 };
3467 
3468 /* Flow Control Settings */
3469 enum ixgbe_fc_mode {
3470         ixgbe_fc_none = 0,
3471         ixgbe_fc_rx_pause,
3472         ixgbe_fc_tx_pause,
3473         ixgbe_fc_full,
3474         ixgbe_fc_default
3475 };
3476 
3477 /* Smart Speed Settings */
3478 #define IXGBE_SMARTSPEED_MAX_RETRIES    3
3479 enum ixgbe_smart_speed {
3480         ixgbe_smart_speed_auto = 0,
3481         ixgbe_smart_speed_on,
3482         ixgbe_smart_speed_off
3483 };
3484 
3485 /* PCI bus types */
3486 enum ixgbe_bus_type {
3487         ixgbe_bus_type_unknown = 0,
3488         ixgbe_bus_type_pci,
3489         ixgbe_bus_type_pcix,
3490         ixgbe_bus_type_pci_express,
3491         ixgbe_bus_type_internal,
3492         ixgbe_bus_type_reserved
3493 };
3494 
3495 /* PCI bus speeds */
3496 enum ixgbe_bus_speed {
3497         ixgbe_bus_speed_unknown = 0,
3498         ixgbe_bus_speed_33      = 33,
3499         ixgbe_bus_speed_66      = 66,
3500         ixgbe_bus_speed_100     = 100,
3501         ixgbe_bus_speed_120     = 120,
3502         ixgbe_bus_speed_133     = 133,
3503         ixgbe_bus_speed_2500    = 2500,
3504         ixgbe_bus_speed_5000    = 5000,
3505         ixgbe_bus_speed_8000    = 8000,
3506         ixgbe_bus_speed_reserved
3507 };
3508 
3509 /* PCI bus widths */
3510 enum ixgbe_bus_width {
3511         ixgbe_bus_width_unknown = 0,


3628         u64 o2bgptc;
3629         u64 o2bspc;
3630 };
3631 
3632 /* forward declaration */
3633 struct ixgbe_hw;
3634 
3635 /* iterator type for walking multicast address lists */
3636 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
3637                                   u32 *vmdq);
3638 
3639 /* Function pointer table */
3640 struct ixgbe_eeprom_operations {
3641         s32 (*init_params)(struct ixgbe_hw *);
3642         s32 (*read)(struct ixgbe_hw *, u16, u16 *);
3643         s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3644         s32 (*write)(struct ixgbe_hw *, u16, u16);
3645         s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3646         s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
3647         s32 (*update_checksum)(struct ixgbe_hw *);
3648         s32 (*calc_checksum)(struct ixgbe_hw *);
3649 };
3650 
3651 struct ixgbe_mac_operations {
3652         s32 (*init_hw)(struct ixgbe_hw *);
3653         s32 (*reset_hw)(struct ixgbe_hw *);
3654         s32 (*start_hw)(struct ixgbe_hw *);
3655         s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
3656         void (*enable_relaxed_ordering)(struct ixgbe_hw *);
3657         enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3658         u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
3659         s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3660         s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3661         s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
3662         s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3663         s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3664         s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
3665         s32 (*stop_adapter)(struct ixgbe_hw *);
3666         s32 (*get_bus_info)(struct ixgbe_hw *);
3667         void (*set_lan_id)(struct ixgbe_hw *);
3668         s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3669         s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3670         s32 (*setup_sfp)(struct ixgbe_hw *);
3671         s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3672         s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
3673         s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
3674         s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3675         void (*release_swfw_sync)(struct ixgbe_hw *, u32);
3676         s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3677         s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3678 
3679         /* Link */
3680         void (*disable_tx_laser)(struct ixgbe_hw *);
3681         void (*enable_tx_laser)(struct ixgbe_hw *);
3682         void (*flap_tx_laser)(struct ixgbe_hw *);
3683         s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3684         s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3685         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3686         s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3687                                      bool *);
3688         void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3689 
3690         /* Packet Buffer manipulation */
3691         void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
3692 
3693         /* LED */
3694         s32 (*led_on)(struct ixgbe_hw *, u32);
3695         s32 (*led_off)(struct ixgbe_hw *, u32);
3696         s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3697         s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
3698 
3699         /* RAR, Multicast, VLAN */
3700         s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3701         s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
3702         s32 (*clear_rar)(struct ixgbe_hw *, u32);
3703         s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
3704         s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3705         s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3706         s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3707         s32 (*init_rx_addrs)(struct ixgbe_hw *);
3708         s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3709                                    ixgbe_mc_addr_itr);
3710         s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3711                                    ixgbe_mc_addr_itr, bool clear);
3712         s32 (*enable_mc)(struct ixgbe_hw *);
3713         s32 (*disable_mc)(struct ixgbe_hw *);
3714         s32 (*clear_vfta)(struct ixgbe_hw *);
3715         s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
3716         s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);
3717         s32 (*init_uta_tables)(struct ixgbe_hw *);
3718         void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3719         void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3720 
3721         /* Flow Control */
3722         s32 (*fc_enable)(struct ixgbe_hw *);
3723         s32 (*setup_fc)(struct ixgbe_hw *);
3724 
3725         /* Manageability interface */
3726         s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
3727         void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);
3728         void (*disable_rx)(struct ixgbe_hw *hw);
3729         void (*enable_rx)(struct ixgbe_hw *hw);
3730         void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3731                                            unsigned int);
3732         void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
3733         s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
3734         s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
3735         s32 (*dmac_config)(struct ixgbe_hw *hw);
3736         s32 (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee);
3737         s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);
3738         s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);
3739         void (*disable_mdd)(struct ixgbe_hw *hw);
3740         void (*enable_mdd)(struct ixgbe_hw *hw);
3741         void (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap);
3742         void (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);
3743 };
3744 
3745 struct ixgbe_phy_operations {
3746         s32 (*identify)(struct ixgbe_hw *);
3747         s32 (*identify_sfp)(struct ixgbe_hw *);
3748         s32 (*init)(struct ixgbe_hw *);
3749         s32 (*reset)(struct ixgbe_hw *);
3750         s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3751         s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3752         s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
3753         s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
3754         s32 (*setup_link)(struct ixgbe_hw *);
3755         s32 (*setup_internal_link)(struct ixgbe_hw *);
3756         s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3757         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3758         s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3759         s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3760         s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3761         s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
3762         s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3763         s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3764         void (*i2c_bus_clear)(struct ixgbe_hw *);
3765         s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
3766         s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
3767         s32 (*check_overtemp)(struct ixgbe_hw *);
3768         s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
3769         s32 (*enter_lplu)(struct ixgbe_hw *);
3770         s32 (*handle_lasi)(struct ixgbe_hw *hw);
3771         s32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3772                                           u16 *value);
3773         s32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3774                                           u16 value);
3775         s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3776                                       u8 *value);
3777         s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3778                                        u8 value);
3779 };
3780 
3781 struct ixgbe_eeprom_info {
3782         struct ixgbe_eeprom_operations ops;
3783         enum ixgbe_eeprom_type type;
3784         u32 semaphore_delay;
3785         u16 word_size;
3786         u16 address_bits;
3787         u16 word_page_size;
3788         u16 ctrl_word_3;
3789 };
3790 
3791 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED       0x01
3792 struct ixgbe_mac_info {
3793         struct ixgbe_mac_operations ops;
3794         enum ixgbe_mac_type type;
3795         u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3796         u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3797         u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3798         /* prefix for World Wide Node Name (WWNN) */
3799         u16 wwnn_prefix;
3800         /* prefix for World Wide Port Name (WWPN) */
3801         u16 wwpn_prefix;
3802 #define IXGBE_MAX_MTA                   128
3803         u32 mta_shadow[IXGBE_MAX_MTA];
3804         s32 mc_filter_type;
3805         u32 mcft_size;
3806         u32 vft_size;
3807         u32 num_rar_entries;
3808         u32 rar_highwater;
3809         u32 rx_pb_size;
3810         u32 max_tx_queues;
3811         u32 max_rx_queues;
3812         u32 orig_autoc;
3813         u8  san_mac_rar_index;
3814         bool get_link_status;
3815         u32 orig_autoc2;
3816         u16 max_msix_vectors;
3817         bool arc_subsystem_valid;
3818         bool orig_link_settings_stored;
3819         bool autotry_restart;
3820         u8 flags;
3821         struct ixgbe_dmac_config dmac_config;
3822         bool set_lben;
3823         u32  max_link_up_time;
3824 };
3825 
3826 struct ixgbe_phy_info {
3827         struct ixgbe_phy_operations ops;
3828         enum ixgbe_phy_type type;
3829         u32 addr;
3830         u32 id;
3831         enum ixgbe_sfp_type sfp_type;
3832         bool sfp_setup_needed;
3833         u32 revision;
3834         enum ixgbe_media_type media_type;
3835         u32 phy_semaphore_mask;
3836         bool reset_disable;
3837         ixgbe_autoneg_advertised autoneg_advertised;
3838         ixgbe_link_speed speeds_supported;
3839         enum ixgbe_smart_speed smart_speed;
3840         bool smart_speed_active;
3841         bool multispeed_fiber;
3842         bool reset_if_overtemp;
3843         bool qsfp_shared_i2c_bus;
3844         u32 nw_mng_if_sel;
3845 };
3846 
3847 #include "ixgbe_mbx.h"
3848 
3849 struct ixgbe_mbx_operations {
3850         void (*init_params)(struct ixgbe_hw *hw);
3851         s32  (*read)(struct ixgbe_hw *, u32 *, u16,  u16);
3852         s32  (*write)(struct ixgbe_hw *, u32 *, u16, u16);
3853         s32  (*read_posted)(struct ixgbe_hw *, u32 *, u16,  u16);
3854         s32  (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3855         s32  (*check_for_msg)(struct ixgbe_hw *, u16);
3856         s32  (*check_for_ack)(struct ixgbe_hw *, u16);
3857         s32  (*check_for_rst)(struct ixgbe_hw *, u16);
3858 };
3859 
3860 struct ixgbe_mbx_stats {
3861         u32 msgs_tx;
3862         u32 msgs_rx;
3863 
3864         u32 acks;
3865         u32 reqs;
3866         u32 rsts;
3867 };
3868 
3869 struct ixgbe_mbx_info {
3870         struct ixgbe_mbx_operations ops;
3871         struct ixgbe_mbx_stats stats;
3872         u32 timeout;
3873         u32 usec_delay;
3874         u32 v2p_mailbox;
3875         u16 size;
3876 };
3877 
3878 struct ixgbe_hw {
3879         u8 IOMEM *hw_addr;
3880         void *back;
3881         struct ixgbe_mac_info mac;
3882         struct ixgbe_addr_filter_info addr_ctrl;
3883         struct ixgbe_fc_info fc;
3884         struct ixgbe_phy_info phy;
3885         struct ixgbe_eeprom_info eeprom;
3886         struct ixgbe_bus_info bus;
3887         struct ixgbe_mbx_info mbx;
3888         const u32 *mvals;
3889         u16 device_id;
3890         u16 vendor_id;
3891         u16 subsystem_device_id;
3892         u16 subsystem_vendor_id;
3893         u8 revision_id;
3894         bool adapter_stopped;
3895         int api_version;
3896         bool force_full_reset;
3897         bool allow_unsupported_sfp;
3898         bool wol_enabled;
3899 };
3900 
3901 #define ixgbe_call_func(hw, func, params, error) \
3902                 (func != NULL) ? func params : error
3903 
3904 
3905 /* Error Codes */
3906 #define IXGBE_SUCCESS                           0
3907 #define IXGBE_ERR_EEPROM                        -1
3908 #define IXGBE_ERR_EEPROM_CHECKSUM               -2
3909 #define IXGBE_ERR_PHY                           -3
3910 #define IXGBE_ERR_CONFIG                        -4
3911 #define IXGBE_ERR_PARAM                         -5
3912 #define IXGBE_ERR_MAC_TYPE                      -6
3913 #define IXGBE_ERR_UNKNOWN_PHY                   -7
3914 #define IXGBE_ERR_LINK_SETUP                    -8
3915 #define IXGBE_ERR_ADAPTER_STOPPED               -9
3916 #define IXGBE_ERR_INVALID_MAC_ADDR              -10
3917 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11
3918 #define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12


3920 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14
3921 #define IXGBE_ERR_RESET_FAILED                  -15
3922 #define IXGBE_ERR_SWFW_SYNC                     -16
3923 #define IXGBE_ERR_PHY_ADDR_INVALID              -17
3924 #define IXGBE_ERR_I2C                           -18
3925 #define IXGBE_ERR_SFP_NOT_SUPPORTED             -19
3926 #define IXGBE_ERR_SFP_NOT_PRESENT               -20
3927 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT       -21
3928 #define IXGBE_ERR_NO_SAN_ADDR_PTR               -22
3929 #define IXGBE_ERR_FDIR_REINIT_FAILED            -23
3930 #define IXGBE_ERR_EEPROM_VERSION                -24
3931 #define IXGBE_ERR_NO_SPACE                      -25
3932 #define IXGBE_ERR_OVERTEMP                      -26
3933 #define IXGBE_ERR_FC_NOT_NEGOTIATED             -27
3934 #define IXGBE_ERR_FC_NOT_SUPPORTED              -28
3935 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
3936 #define IXGBE_ERR_PBA_SECTION                   -31
3937 #define IXGBE_ERR_INVALID_ARGUMENT              -32
3938 #define IXGBE_ERR_HOST_INTERFACE_COMMAND        -33
3939 #define IXGBE_ERR_OUT_OF_MEM                    -34
3940 #define IXGBE_ERR_FEATURE_NOT_SUPPORTED         -36
3941 #define IXGBE_ERR_EEPROM_PROTECTED_REGION       -37
3942 #define IXGBE_ERR_FDIR_CMD_INCOMPLETE           -38
3943 
3944 #define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
3945 
3946 
3947 #define IXGBE_FUSES0_GROUP(_i)          (0x11158 + ((_i) * 4))
3948 #define IXGBE_FUSES0_300MHZ             (1 << 5)
3949 #define IXGBE_FUSES0_REV1               (1 << 6)
3950 
3951 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)  ((P) ? 0x8010 : 0x4010)
3952 #define IXGBE_KRM_LINK_CTRL_1(P)        ((P) ? 0x820C : 0x420C)
3953 #define IXGBE_KRM_AN_CNTL_1(P)          ((P) ? 0x822C : 0x422C)
3954 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P)  ((P) ? 0x8634 : 0x4634)
3955 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P)  ((P) ? 0x8638 : 0x4638)
3956 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
3957 #define IXGBE_KRM_PMD_DFX_BURNIN(P)     ((P) ? 0x8E00 : 0x4E00)
3958 #define IXGBE_KRM_TX_COEFF_CTRL_1(P)    ((P) ? 0x9520 : 0x5520)
3959 #define IXGBE_KRM_RX_ANA_CTL(P)         ((P) ? 0x9A00 : 0x5A00)
3960 
3961 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B            (1 << 9)
3962 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS          (1 << 11)
3963 
3964 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK     (0x7 << 8)
3965 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G       (2 << 8)
3966 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G      (4 << 8)
3967 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ           (1 << 14)
3968 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC           (1 << 15)
3969 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX            (1 << 16)
3970 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR            (1 << 18)
3971 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX           (1 << 24)
3972 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR           (1 << 26)
3973 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE            (1 << 29)
3974 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART           (1 << 31)
3975 
3976 #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE                   (1 << 28)
3977 #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE                   (1 << 29)
3978 
3979 #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN                 (1 << 6)
3980 #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN            (1 << 15)
3981 #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN           (1 << 16)
3982 
3983 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL   (1 << 4)
3984 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS    (1 << 2)
3985 
3986 #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK       (0x3 << 16)
3987 
3988 #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN      (1 << 1)
3989 #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN       (1 << 2)
3990 #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN              (1 << 3)
3991 #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN              (1 << 31)
3992 
3993 #define IXGBE_SB_IOSF_INDIRECT_CTRL     0x00011144
3994 #define IXGBE_SB_IOSF_INDIRECT_DATA     0x00011148
3995 
3996 #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT           0
3997 #define IXGBE_SB_IOSF_CTRL_ADDR_MASK            0xFF
3998 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT      18
3999 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK       \
4000                                 (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
4001 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT       20
4002 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK        \
4003                                 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
4004 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT  28
4005 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK   0x7
4006 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT           31
4007 #define IXGBE_SB_IOSF_CTRL_BUSY         (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
4008 #define IXGBE_SB_IOSF_TARGET_KR_PHY     0
4009 
4010 #define IXGBE_NW_MNG_IF_SEL             0x00011178
4011 #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24)
4012 
4013 #endif /* _IXGBE_TYPE_H_ */