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   3   Copyright (c) 2001-2015, Intel Corporation 
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  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34 
  35 #ifndef _IXGBE_DCB_82598_H_
  36 #define _IXGBE_DCB_82598_H_
  37 
  38 /* DCB register definitions */
  39 
  40 #define IXGBE_DPMCS_MTSOS_SHIFT 16
  41 #define IXGBE_DPMCS_TDPAC       0x00000001 /* 0 Round Robin,
  42                                             * 1 DFP - Deficit Fixed Priority */
  43 #define IXGBE_DPMCS_TRM         0x00000010 /* Transmit Recycle Mode */
  44 #define IXGBE_DPMCS_ARBDIS      0x00000040 /* DCB arbiter disable */
  45 #define IXGBE_DPMCS_TSOEF       0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
  46 
  47 #define IXGBE_RUPPBMR_MQA       0x80000000 /* Enable UP to queue mapping */
  48 
  49 #define IXGBE_RT2CR_MCL_SHIFT   12 /* Offset to Max Credit Limit setting */
  50 #define IXGBE_RT2CR_LSP         0x80000000 /* LSP enable bit */
  51 
  52 #define IXGBE_RDRXCTL_MPBEN     0x00000010 /* DMA config for multiple packet
  53                                             * buffers enable */
  54 #define IXGBE_RDRXCTL_MCEN      0x00000040 /* DMA config for multiple cores
  55                                             * (RSS) enable */
  56 
  57 #define IXGBE_TDTQ2TCCR_MCL_SHIFT       12
  58 #define IXGBE_TDTQ2TCCR_BWG_SHIFT       9
  59 #define IXGBE_TDTQ2TCCR_GSP     0x40000000
  60 #define IXGBE_TDTQ2TCCR_LSP     0x80000000
  61 
  62 #define IXGBE_TDPT2TCCR_MCL_SHIFT       12
  63 #define IXGBE_TDPT2TCCR_BWG_SHIFT       9
  64 #define IXGBE_TDPT2TCCR_GSP     0x40000000
  65 #define IXGBE_TDPT2TCCR_LSP     0x80000000
  66 
  67 #define IXGBE_PDPMCS_TPPAC      0x00000020 /* 0 Round Robin,
  68                                             * 1 DFP - Deficit Fixed Priority */
  69 #define IXGBE_PDPMCS_ARBDIS     0x00000040 /* Arbiter disable */
  70 #define IXGBE_PDPMCS_TRM        0x00000100 /* Transmit Recycle Mode enable */
  71 
  72 #define IXGBE_DTXCTL_ENDBUBD    0x00000004 /* Enable DBU buffer division */
  73 
  74 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
  75 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
  76 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
  77 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
  78 
  79 /* DCB driver APIs */
  80 
  81 /* DCB PFC */
  82 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8);
  83 
  84 /* DCB stats */
  85 s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *);
  86 s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *,
  87                                  struct ixgbe_hw_stats *, u8);
  88 s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *,
  89                                   struct ixgbe_hw_stats *, u8);
  90 
  91 /* DCB config arbiters */
  92 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
  93                                            u8 *, u8 *);
  94 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
  95                                            u8 *, u8 *);
  96 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *);
  97 
  98 /* DCB initialization */
  99 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *);
 100 #endif /* _IXGBE_DCB_82958_H_ */