1 /******************************************************************************
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3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #ifndef _IXGBE_DCB_H_
36 #define _IXGBE_DCB_H_
37
38 #include "ixgbe_type.h"
39
40 /* DCB defines */
41 /* DCB credit calculation defines */
42 #define IXGBE_DCB_CREDIT_QUANTUM 64
43 #define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */
44 #define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/
45 #define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL)
46
47 /* 513 for 32KB TSO packet */
48 #define IXGBE_DCB_MIN_TSO_CREDIT \
49 ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1)
50
51 /* DCB configuration defines */
52 #define IXGBE_DCB_MAX_USER_PRIORITY 8
53 #define IXGBE_DCB_MAX_BW_GROUP 8
54 #define IXGBE_DCB_BW_PERCENT 100
55
56 #define IXGBE_DCB_TX_CONFIG 0
57 #define IXGBE_DCB_RX_CONFIG 1
58
59 /* DCB capability defines */
60 #define IXGBE_DCB_PG_SUPPORT 0x00000001
61 #define IXGBE_DCB_PFC_SUPPORT 0x00000002
62 #define IXGBE_DCB_BCN_SUPPORT 0x00000004
63 #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008
64 #define IXGBE_DCB_GSP_SUPPORT 0x00000010
65
66 struct ixgbe_dcb_support {
67 u32 capabilities; /* DCB capabilities */
68
69 /* Each bit represents a number of TCs configurable in the hw.
70 * If 8 traffic classes can be configured, the value is 0x80. */
71 u8 traffic_classes;
72 u8 pfc_traffic_classes;
73 };
74
75 enum ixgbe_dcb_tsa {
76 ixgbe_dcb_tsa_ets = 0,
77 ixgbe_dcb_tsa_group_strict_cee,
78 ixgbe_dcb_tsa_strict
79 };
80
81 /* Traffic class bandwidth allocation per direction */
82 struct ixgbe_dcb_tc_path {
83 u8 bwg_id; /* Bandwidth Group (BWG) ID */
84 u8 bwg_percent; /* % of BWG's bandwidth */
85 u8 link_percent; /* % of link bandwidth */
86 u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
87 u16 data_credits_refill; /* Credit refill amount in 64B granularity */
88 u16 data_credits_max; /* Max credits for a configured packet buffer
89 * in 64B granularity.*/
90 enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */
91 };
92
93 enum ixgbe_dcb_pfc {
94 ixgbe_dcb_pfc_disabled = 0,
95 ixgbe_dcb_pfc_enabled,
96 ixgbe_dcb_pfc_enabled_txonly,
97 ixgbe_dcb_pfc_enabled_rxonly
98 };
99
100 /* Traffic class configuration */
101 struct ixgbe_dcb_tc_config {
102 struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */
103 enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */
104
105 u16 desc_credits_max; /* For Tx Descriptor arbitration */
106 u8 tc; /* Traffic class (TC) */
107 };
108
109 enum ixgbe_dcb_pba {
110 /* PBA[0-7] each use 64KB FIFO */
111 ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL,
112 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
113 ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED
114 };
115
116 struct ixgbe_dcb_num_tcs {
117 u8 pg_tcs;
118 u8 pfc_tcs;
119 };
120
121 struct ixgbe_dcb_config {
122 struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS];
123 struct ixgbe_dcb_support support;
124 struct ixgbe_dcb_num_tcs num_tcs;
125 u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */
126 bool pfc_mode_enable;
127 bool round_robin_enable;
128
129 enum ixgbe_dcb_pba rx_pba_cfg;
130
131 u32 dcb_cfg_version; /* Not used...OS-specific? */
132 u32 link_speed; /* For bandwidth allocation validation purpose */
133 bool vt_mode;
134 };
135
136 /* DCB driver APIs */
137
138 /* DCB rule checking */
139 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *);
140
141 /* DCB credits calculation */
142 s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int);
143 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *,
144 struct ixgbe_dcb_config *, u32, u8);
145
146 /* DCB PFC */
147 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *);
148 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
149
150 /* DCB stats */
151 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
152 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
153 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
154
155 /* DCB config arbiters */
156 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *,
157 struct ixgbe_dcb_config *);
158 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *,
159 struct ixgbe_dcb_config *);
160 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *,
161 struct ixgbe_dcb_config *);
162
163 /* DCB unpack routines */
164 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *);
165 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *);
166 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *);
167 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *);
168 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *);
169 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *);
170 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);
171
172 /* DCB initialization */
173 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *);
174 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
175 #endif /* _IXGBE_DCB_H_ */