1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37
38 /**
39 * ixgbe_init_shared_code - Initialize the shared code
40 * @hw: pointer to hardware structure
41 *
42 * This will assign function pointers and assign the MAC type and PHY code.
43 * Does not touch the hardware. This function must be called prior to any
44 * other function in the shared code. The ixgbe_hw structure should be
45 * memset to 0 prior to calling this function. The following fields in
46 * hw structure should be filled in prior to calling this function:
47 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
48 * subsystem_vendor_id, and revision_id
49 **/
50 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
51 {
52 s32 status;
53
54 DEBUGFUNC("ixgbe_init_shared_code");
55
56 /*
57 * Set the mac type
58 */
59 status = ixgbe_set_mac_type(hw);
60 if (status != IXGBE_SUCCESS)
61 return (status);
62
63 switch (hw->mac.type) {
64 case ixgbe_mac_82598EB:
65 status = ixgbe_init_ops_82598(hw);
66 break;
67 case ixgbe_mac_82599EB:
68 status = ixgbe_init_ops_82599(hw);
69 break;
70 case ixgbe_mac_X540:
71 status = ixgbe_init_ops_X540(hw);
72 break;
73 default:
74 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
75 break;
76 }
77
78 return status;
79 }
80
81 /**
82 * ixgbe_set_mac_type - Sets MAC type
83 * @hw: pointer to the HW structure
84 *
85 * This function sets the mac type of the adapter based on the
86 * vendor ID and device ID stored in the hw structure.
87 **/
88 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
89 {
90 s32 ret_val = IXGBE_SUCCESS;
91
92 DEBUGFUNC("ixgbe_set_mac_type\n");
93
94 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
95 switch (hw->device_id) {
96 case IXGBE_DEV_ID_82598:
97 case IXGBE_DEV_ID_82598_BX:
98 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
99 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
100 case IXGBE_DEV_ID_82598AT:
101 case IXGBE_DEV_ID_82598AT2:
102 case IXGBE_DEV_ID_82598EB_CX4:
103 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
104 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
105 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
106 case IXGBE_DEV_ID_82598EB_XF_LR:
107 case IXGBE_DEV_ID_82598EB_SFP_LOM:
108 hw->mac.type = ixgbe_mac_82598EB;
109 break;
110 case IXGBE_DEV_ID_82599_KX4:
111 case IXGBE_DEV_ID_82599_KX4_MEZZ:
112 case IXGBE_DEV_ID_82599_XAUI_LOM:
113 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
114 case IXGBE_DEV_ID_82599_KR:
115 case IXGBE_DEV_ID_82599_SFP:
116 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
117 case IXGBE_DEV_ID_82599_SFP_FCOE:
118 case IXGBE_DEV_ID_82599_SFP_EM:
119 case IXGBE_DEV_ID_82599_SFP_SF2:
120 case IXGBE_DEV_ID_82599EN_SFP:
121 case IXGBE_DEV_ID_82599_CX4:
122 case IXGBE_DEV_ID_82599_T3_LOM:
123 hw->mac.type = ixgbe_mac_82599EB;
124 break;
125 case IXGBE_DEV_ID_82599_VF:
126 hw->mac.type = ixgbe_mac_82599_vf;
127 break;
128 case IXGBE_DEV_ID_X540_VF:
129 hw->mac.type = ixgbe_mac_X540_vf;
130 break;
131 case IXGBE_DEV_ID_X540T:
132 case IXGBE_DEV_ID_X540T1:
133 hw->mac.type = ixgbe_mac_X540;
134 break;
135 default:
136 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
137 break;
138 }
139 } else {
140 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
141 }
142
143 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
144 hw->mac.type, ret_val);
145 return ret_val;
146 }
147
148 /**
149 * ixgbe_init_hw - Initialize the hardware
150 * @hw: pointer to hardware structure
151 *
152 * Initialize the hardware by resetting and then starting the hardware
153 **/
154 s32 ixgbe_init_hw(struct ixgbe_hw *hw)
155 {
156 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
157 IXGBE_NOT_IMPLEMENTED);
158 }
159
160 /**
161 * ixgbe_reset_hw - Performs a hardware reset
433 {
434 s32 status = IXGBE_SUCCESS;
435
436 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
437 (hw, firmware_version),
438 IXGBE_NOT_IMPLEMENTED);
439 return status;
440 }
441
442 /**
443 * ixgbe_read_phy_reg - Read PHY register
444 * @hw: pointer to hardware structure
445 * @reg_addr: 32 bit address of PHY register to read
446 * @phy_data: Pointer to read data from PHY register
447 *
448 * Reads a value from a specified PHY register
449 **/
450 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
451 u16 *phy_data)
452 {
453 s32 status;
454
455 if (hw->phy.id == 0)
456 status = ixgbe_identify_phy(hw);
457 else
458 status = IXGBE_SUCCESS;
459
460 if (status == IXGBE_SUCCESS) {
461 status = ixgbe_call_func(hw, hw->phy.ops.read_reg,
462 (hw, reg_addr, device_type, phy_data),
463 IXGBE_NOT_IMPLEMENTED);
464 }
465 return (status);
466 }
467
468 /**
469 * ixgbe_write_phy_reg - Write PHY register
470 * @hw: pointer to hardware structure
471 * @reg_addr: 32 bit PHY register to write
472 * @phy_data: Data to write to the PHY register
473 *
474 * Writes a value to specified PHY register
475 **/
476 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
477 u16 phy_data)
478 {
479 s32 status;
480
481 if (hw->phy.id == 0)
482 status = ixgbe_identify_phy(hw);
483 else
484 status = IXGBE_SUCCESS;
485
486 if (status == IXGBE_SUCCESS) {
487 status = ixgbe_call_func(hw, hw->phy.ops.write_reg,
488 (hw, reg_addr, device_type, phy_data),
489 IXGBE_NOT_IMPLEMENTED);
490 }
491
492 return status;
493 }
494
495 /**
496 * ixgbe_setup_phy_link - Restart PHY autoneg
497 * @hw: pointer to hardware structure
498 *
499 * Restart autonegotiation and PHY and waits for completion.
500 **/
501 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
502 {
503 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
504 IXGBE_NOT_IMPLEMENTED);
505 }
506
507 /**
508 * ixgbe_check_phy_link - Determine link and speed status
509 * @hw: pointer to hardware structure
510 *
511 * Reads a PHY register to determine if link is up and the current speed for
512 * the PHY.
513 **/
514 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
515 bool *link_up)
516 {
517 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
518 link_up), IXGBE_NOT_IMPLEMENTED);
519 }
520
521 /**
522 * ixgbe_setup_phy_link_speed - Set auto advertise
523 * @hw: pointer to hardware structure
524 * @speed: new link speed
525 * @autoneg: TRUE if autonegotiation enabled
526 *
527 * Sets the auto advertised capabilities
528 **/
529 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
530 bool autoneg,
531 bool autoneg_wait_to_complete)
532 {
533 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
534 autoneg, autoneg_wait_to_complete),
535 IXGBE_NOT_IMPLEMENTED);
536 }
537
538 /**
539 * ixgbe_check_link - Get link and speed status
540 * @hw: pointer to hardware structure
541 *
542 * Reads the links register to determine if link is up and the current speed
543 **/
544 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
545 bool *link_up, bool link_up_wait_to_complete)
546 {
547 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
548 link_up, link_up_wait_to_complete),
549 IXGBE_NOT_IMPLEMENTED);
550 }
551
552 /**
553 * ixgbe_disable_tx_laser - Disable Tx laser
554 * @hw: pointer to hardware structure
555 *
556 * If the driver needs to disable the laser on SFI optics.
557 **/
558 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
574 }
575
576 /**
577 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
578 * @hw: pointer to hardware structure
579 *
580 * When the driver changes the link speeds that it can support then
581 * flap the tx laser to alert the link partner to start autotry
582 * process on its end.
583 **/
584 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
585 {
586 if (hw->mac.ops.flap_tx_laser)
587 hw->mac.ops.flap_tx_laser(hw);
588 }
589
590 /**
591 * ixgbe_setup_link - Set link speed
592 * @hw: pointer to hardware structure
593 * @speed: new link speed
594 * @autoneg: TRUE if autonegotiation enabled
595 *
596 * Configures link settings. Restarts the link.
597 * Performs autonegotiation if needed.
598 **/
599 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
600 bool autoneg,
601 bool autoneg_wait_to_complete)
602 {
603 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
604 autoneg, autoneg_wait_to_complete),
605 IXGBE_NOT_IMPLEMENTED);
606 }
607
608 /**
609 * ixgbe_get_link_capabilities - Returns link capabilities
610 * @hw: pointer to hardware structure
611 *
612 * Determines the link capabilities of the current configuration.
613 **/
614 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
615 bool *autoneg)
616 {
617 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
618 speed, autoneg), IXGBE_NOT_IMPLEMENTED);
619 }
620
621 /**
622 * ixgbe_led_on - Turn on LEDs
623 * @hw: pointer to hardware structure
624 * @index: led number to turn on
625 *
626 * Turns on the software controllable LEDs.
627 **/
628 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
982 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
983 bool *vfta_changed)
984 {
985 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
986 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
987 }
988
989 /**
990 * ixgbe_fc_enable - Enable flow control
991 * @hw: pointer to hardware structure
992 *
993 * Configures the flow control settings based on SW configuration.
994 **/
995 s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
996 {
997 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
998 IXGBE_NOT_IMPLEMENTED);
999 }
1000
1001 /**
1002 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
1003 * @hw: pointer to hardware structure
1004 * @maj: driver major number to be sent to firmware
1005 * @min: driver minor number to be sent to firmware
1006 * @build: driver build number to be sent to firmware
1007 * @ver: driver version number to be sent to firmware
1008 **/
1009 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
1010 u8 ver)
1011 {
1012 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1013 build, ver), IXGBE_NOT_IMPLEMENTED);
1014 }
1015
1016
1017 /**
1018 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
1019 * @hw: pointer to hardware structure
1020 * @reg: analog register to read
1021 * @val: read value
1022 *
1023 * Performs write operation to analog register specified.
1024 **/
1025 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1026 {
1027 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
1028 val), IXGBE_NOT_IMPLEMENTED);
1029 }
1030
1031 /**
1032 * ixgbe_write_analog_reg8 - Writes 8 bit analog register
1033 * @hw: pointer to hardware structure
1034 * @reg: analog register to write
1035 * @val: value to write
1036 *
1037 * Performs write operation to Atlas analog register specified.
1042 val), IXGBE_NOT_IMPLEMENTED);
1043 }
1044
1045 /**
1046 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
1047 * @hw: pointer to hardware structure
1048 *
1049 * Initializes the Unicast Table Arrays to zero on device load. This
1050 * is part of the Rx init addr execution path.
1051 **/
1052 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
1053 {
1054 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
1055 IXGBE_NOT_IMPLEMENTED);
1056 }
1057
1058 /**
1059 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
1060 * @hw: pointer to hardware structure
1061 * @byte_offset: byte offset to read
1062 * @data: value read
1063 *
1064 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1065 **/
1066 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1067 u8 *data)
1068 {
1069 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
1070 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1071 }
1072
1073 /**
1074 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1075 * @hw: pointer to hardware structure
1076 * @byte_offset: byte offset to write
1077 * @data: value to write
1078 *
1079 * Performs byte write operation to SFP module's EEPROM over I2C interface
1080 * at a specified device address.
1081 **/
1082 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1083 u8 data)
1084 {
1085 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
1086 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1087 }
1088
1089 /**
1090 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1091 * @hw: pointer to hardware structure
1092 * @byte_offset: EEPROM byte offset to write
1093 * @eeprom_data: value to write
1094 *
1095 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1096 **/
1097 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
1098 u8 byte_offset, u8 eeprom_data)
1099 {
1100 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
1101 (hw, byte_offset, eeprom_data),
1102 IXGBE_NOT_IMPLEMENTED);
1103 }
1104
1105 /**
1106 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1107 * @hw: pointer to hardware structure
1108 * @byte_offset: EEPROM byte offset to read
1109 * @eeprom_data: value read
1157 /**
1158 * ixgbe_enable_sec_rx_path - Enables the receive data path
1159 * @hw: pointer to hardware structure
1160 *
1161 * Enables the receive data path.
1162 **/
1163 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
1164 {
1165 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
1166 (hw), IXGBE_NOT_IMPLEMENTED);
1167 }
1168
1169 /**
1170 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
1171 * @hw: pointer to hardware structure
1172 * @mask: Mask to specify which semaphore to acquire
1173 *
1174 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
1175 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1176 **/
1177 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1178 {
1179 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
1180 (hw, mask), IXGBE_NOT_IMPLEMENTED);
1181 }
1182
1183 /**
1184 * ixgbe_release_swfw_semaphore - Release SWFW semaphore
1185 * @hw: pointer to hardware structure
1186 * @mask: Mask to specify which semaphore to release
1187 *
1188 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
1189 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1190 **/
1191 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1192 {
1193 if (hw->mac.ops.release_swfw_sync)
1194 hw->mac.ops.release_swfw_sync(hw, mask);
1195 }
1196
|
1 /******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37
38 #define IXGBE_EMPTY_PARAM
39
40 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {
41 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM)
42 };
43
44 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
45 IXGBE_MVALS_INIT(_X540)
46 };
47
48 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
49 IXGBE_MVALS_INIT(_X550)
50 };
51
52 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
53 IXGBE_MVALS_INIT(_X550EM_x)
54 };
55
56 /**
57 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
58 * @hw: pointer to hardware structure
59 * @map: pointer to u8 arr for returning map
60 *
61 * Read the rtrup2tc HW register and resolve its content into map
62 **/
63 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)
64 {
65 if (hw->mac.ops.get_rtrup2tc)
66 hw->mac.ops.get_rtrup2tc(hw, map);
67 }
68
69 /**
70 * ixgbe_init_shared_code - Initialize the shared code
71 * @hw: pointer to hardware structure
72 *
73 * This will assign function pointers and assign the MAC type and PHY code.
74 * Does not touch the hardware. This function must be called prior to any
75 * other function in the shared code. The ixgbe_hw structure should be
76 * memset to 0 prior to calling this function. The following fields in
77 * hw structure should be filled in prior to calling this function:
78 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
79 * subsystem_vendor_id, and revision_id
80 **/
81 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
82 {
83 s32 status;
84
85 DEBUGFUNC("ixgbe_init_shared_code");
86
87 /*
88 * Set the mac type
89 */
90 ixgbe_set_mac_type(hw);
91
92 switch (hw->mac.type) {
93 case ixgbe_mac_82598EB:
94 status = ixgbe_init_ops_82598(hw);
95 break;
96 case ixgbe_mac_82599EB:
97 status = ixgbe_init_ops_82599(hw);
98 break;
99 case ixgbe_mac_X540:
100 status = ixgbe_init_ops_X540(hw);
101 break;
102 case ixgbe_mac_X550:
103 status = ixgbe_init_ops_X550(hw);
104 break;
105 case ixgbe_mac_X550EM_x:
106 status = ixgbe_init_ops_X550EM(hw);
107 break;
108 case ixgbe_mac_82599_vf:
109 case ixgbe_mac_X540_vf:
110 case ixgbe_mac_X550_vf:
111 case ixgbe_mac_X550EM_x_vf:
112 status = ixgbe_init_ops_vf(hw);
113 break;
114 default:
115 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
116 break;
117 }
118 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;
119
120 return status;
121 }
122
123 /**
124 * ixgbe_set_mac_type - Sets MAC type
125 * @hw: pointer to the HW structure
126 *
127 * This function sets the mac type of the adapter based on the
128 * vendor ID and device ID stored in the hw structure.
129 **/
130 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
131 {
132 s32 ret_val = IXGBE_SUCCESS;
133
134 DEBUGFUNC("ixgbe_set_mac_type\n");
135
136 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) {
137 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
138 "Unsupported vendor id: %x", hw->vendor_id);
139 return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
140 }
141
142 hw->mvals = ixgbe_mvals_base;
143
144 switch (hw->device_id) {
145 case IXGBE_DEV_ID_82598:
146 case IXGBE_DEV_ID_82598_BX:
147 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
148 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
149 case IXGBE_DEV_ID_82598AT:
150 case IXGBE_DEV_ID_82598AT2:
151 case IXGBE_DEV_ID_82598EB_CX4:
152 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
153 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
154 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
155 case IXGBE_DEV_ID_82598EB_XF_LR:
156 case IXGBE_DEV_ID_82598EB_SFP_LOM:
157 hw->mac.type = ixgbe_mac_82598EB;
158 break;
159 case IXGBE_DEV_ID_82599_KX4:
160 case IXGBE_DEV_ID_82599_KX4_MEZZ:
161 case IXGBE_DEV_ID_82599_XAUI_LOM:
162 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
163 case IXGBE_DEV_ID_82599_KR:
164 case IXGBE_DEV_ID_82599_SFP:
165 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
166 case IXGBE_DEV_ID_82599_SFP_FCOE:
167 case IXGBE_DEV_ID_82599_SFP_EM:
168 case IXGBE_DEV_ID_82599_SFP_SF2:
169 case IXGBE_DEV_ID_82599_SFP_SF_QP:
170 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
171 case IXGBE_DEV_ID_82599EN_SFP:
172 case IXGBE_DEV_ID_82599_CX4:
173 case IXGBE_DEV_ID_82599_BYPASS:
174 case IXGBE_DEV_ID_82599_T3_LOM:
175 hw->mac.type = ixgbe_mac_82599EB;
176 break;
177 case IXGBE_DEV_ID_82599_VF:
178 case IXGBE_DEV_ID_82599_VF_HV:
179 hw->mac.type = ixgbe_mac_82599_vf;
180 break;
181 case IXGBE_DEV_ID_X540_VF:
182 case IXGBE_DEV_ID_X540_VF_HV:
183 hw->mac.type = ixgbe_mac_X540_vf;
184 hw->mvals = ixgbe_mvals_X540;
185 break;
186 case IXGBE_DEV_ID_X540T:
187 case IXGBE_DEV_ID_X540T1:
188 case IXGBE_DEV_ID_X540_BYPASS:
189 hw->mac.type = ixgbe_mac_X540;
190 hw->mvals = ixgbe_mvals_X540;
191 break;
192 case IXGBE_DEV_ID_X550T:
193 case IXGBE_DEV_ID_X550T1:
194 hw->mac.type = ixgbe_mac_X550;
195 hw->mvals = ixgbe_mvals_X550;
196 break;
197 case IXGBE_DEV_ID_X550EM_X_KX4:
198 case IXGBE_DEV_ID_X550EM_X_KR:
199 case IXGBE_DEV_ID_X550EM_X_10G_T:
200 case IXGBE_DEV_ID_X550EM_X_1G_T:
201 case IXGBE_DEV_ID_X550EM_X_SFP:
202 hw->mac.type = ixgbe_mac_X550EM_x;
203 hw->mvals = ixgbe_mvals_X550EM_x;
204 break;
205 case IXGBE_DEV_ID_X550_VF:
206 case IXGBE_DEV_ID_X550_VF_HV:
207 hw->mac.type = ixgbe_mac_X550_vf;
208 hw->mvals = ixgbe_mvals_X550;
209 break;
210 case IXGBE_DEV_ID_X550EM_X_VF:
211 case IXGBE_DEV_ID_X550EM_X_VF_HV:
212 hw->mac.type = ixgbe_mac_X550EM_x_vf;
213 hw->mvals = ixgbe_mvals_X550EM_x;
214 break;
215 default:
216 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
217 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
218 "Unsupported device id: %x",
219 hw->device_id);
220 break;
221 }
222
223 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
224 hw->mac.type, ret_val);
225 return ret_val;
226 }
227
228 /**
229 * ixgbe_init_hw - Initialize the hardware
230 * @hw: pointer to hardware structure
231 *
232 * Initialize the hardware by resetting and then starting the hardware
233 **/
234 s32 ixgbe_init_hw(struct ixgbe_hw *hw)
235 {
236 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
237 IXGBE_NOT_IMPLEMENTED);
238 }
239
240 /**
241 * ixgbe_reset_hw - Performs a hardware reset
513 {
514 s32 status = IXGBE_SUCCESS;
515
516 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
517 (hw, firmware_version),
518 IXGBE_NOT_IMPLEMENTED);
519 return status;
520 }
521
522 /**
523 * ixgbe_read_phy_reg - Read PHY register
524 * @hw: pointer to hardware structure
525 * @reg_addr: 32 bit address of PHY register to read
526 * @phy_data: Pointer to read data from PHY register
527 *
528 * Reads a value from a specified PHY register
529 **/
530 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
531 u16 *phy_data)
532 {
533 if (hw->phy.id == 0)
534 ixgbe_identify_phy(hw);
535
536 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
537 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
538 }
539
540 /**
541 * ixgbe_write_phy_reg - Write PHY register
542 * @hw: pointer to hardware structure
543 * @reg_addr: 32 bit PHY register to write
544 * @phy_data: Data to write to the PHY register
545 *
546 * Writes a value to specified PHY register
547 **/
548 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
549 u16 phy_data)
550 {
551 if (hw->phy.id == 0)
552 ixgbe_identify_phy(hw);
553
554 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
555 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
556 }
557
558 /**
559 * ixgbe_setup_phy_link - Restart PHY autoneg
560 * @hw: pointer to hardware structure
561 *
562 * Restart autonegotiation and PHY and waits for completion.
563 **/
564 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
565 {
566 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
567 IXGBE_NOT_IMPLEMENTED);
568 }
569
570 /**
571 * ixgbe_setup_internal_phy - Configure integrated PHY
572 * @hw: pointer to hardware structure
573 *
574 * Reconfigure the integrated PHY in order to enable talk to the external PHY.
575 * Returns success if not implemented, since nothing needs to be done in this
576 * case.
577 */
578 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)
579 {
580 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw),
581 IXGBE_SUCCESS);
582 }
583
584 /**
585 * ixgbe_check_phy_link - Determine link and speed status
586 * @hw: pointer to hardware structure
587 *
588 * Reads a PHY register to determine if link is up and the current speed for
589 * the PHY.
590 **/
591 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
592 bool *link_up)
593 {
594 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
595 link_up), IXGBE_NOT_IMPLEMENTED);
596 }
597
598 /**
599 * ixgbe_setup_phy_link_speed - Set auto advertise
600 * @hw: pointer to hardware structure
601 * @speed: new link speed
602 *
603 * Sets the auto advertised capabilities
604 **/
605 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
606 bool autoneg_wait_to_complete)
607 {
608 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
609 autoneg_wait_to_complete),
610 IXGBE_NOT_IMPLEMENTED);
611 }
612
613 /**
614 * ixgbe_set_phy_power - Control the phy power state
615 * @hw: pointer to hardware structure
616 * @on: TRUE for on, FALSE for off
617 */
618 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on)
619 {
620 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on),
621 IXGBE_NOT_IMPLEMENTED);
622 }
623
624 /**
625 * ixgbe_check_link - Get link and speed status
626 * @hw: pointer to hardware structure
627 *
628 * Reads the links register to determine if link is up and the current speed
629 **/
630 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
631 bool *link_up, bool link_up_wait_to_complete)
632 {
633 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
634 link_up, link_up_wait_to_complete),
635 IXGBE_NOT_IMPLEMENTED);
636 }
637
638 /**
639 * ixgbe_disable_tx_laser - Disable Tx laser
640 * @hw: pointer to hardware structure
641 *
642 * If the driver needs to disable the laser on SFI optics.
643 **/
644 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
660 }
661
662 /**
663 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
664 * @hw: pointer to hardware structure
665 *
666 * When the driver changes the link speeds that it can support then
667 * flap the tx laser to alert the link partner to start autotry
668 * process on its end.
669 **/
670 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
671 {
672 if (hw->mac.ops.flap_tx_laser)
673 hw->mac.ops.flap_tx_laser(hw);
674 }
675
676 /**
677 * ixgbe_setup_link - Set link speed
678 * @hw: pointer to hardware structure
679 * @speed: new link speed
680 *
681 * Configures link settings. Restarts the link.
682 * Performs autonegotiation if needed.
683 **/
684 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
685 bool autoneg_wait_to_complete)
686 {
687 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
688 autoneg_wait_to_complete),
689 IXGBE_NOT_IMPLEMENTED);
690 }
691
692 /**
693 * ixgbe_setup_mac_link - Set link speed
694 * @hw: pointer to hardware structure
695 * @speed: new link speed
696 *
697 * Configures link settings. Restarts the link.
698 * Performs autonegotiation if needed.
699 **/
700 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
701 bool autoneg_wait_to_complete)
702 {
703 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed,
704 autoneg_wait_to_complete),
705 IXGBE_NOT_IMPLEMENTED);
706 }
707
708 /**
709 * ixgbe_get_link_capabilities - Returns link capabilities
710 * @hw: pointer to hardware structure
711 *
712 * Determines the link capabilities of the current configuration.
713 **/
714 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
715 bool *autoneg)
716 {
717 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
718 speed, autoneg), IXGBE_NOT_IMPLEMENTED);
719 }
720
721 /**
722 * ixgbe_led_on - Turn on LEDs
723 * @hw: pointer to hardware structure
724 * @index: led number to turn on
725 *
726 * Turns on the software controllable LEDs.
727 **/
728 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
1082 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
1083 bool *vfta_changed)
1084 {
1085 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
1086 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
1087 }
1088
1089 /**
1090 * ixgbe_fc_enable - Enable flow control
1091 * @hw: pointer to hardware structure
1092 *
1093 * Configures the flow control settings based on SW configuration.
1094 **/
1095 s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
1096 {
1097 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
1098 IXGBE_NOT_IMPLEMENTED);
1099 }
1100
1101 /**
1102 * ixgbe_setup_fc - Set up flow control
1103 * @hw: pointer to hardware structure
1104 *
1105 * Called at init time to set up flow control.
1106 **/
1107 s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
1108 {
1109 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw),
1110 IXGBE_NOT_IMPLEMENTED);
1111 }
1112
1113 /**
1114 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
1115 * @hw: pointer to hardware structure
1116 * @maj: driver major number to be sent to firmware
1117 * @min: driver minor number to be sent to firmware
1118 * @build: driver build number to be sent to firmware
1119 * @ver: driver version number to be sent to firmware
1120 **/
1121 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
1122 u8 ver)
1123 {
1124 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1125 build, ver), IXGBE_NOT_IMPLEMENTED);
1126 }
1127
1128
1129
1130 /**
1131 * ixgbe_dmac_config - Configure DMA Coalescing registers.
1132 * @hw: pointer to hardware structure
1133 *
1134 * Configure DMA coalescing. If enabling dmac, dmac is activated.
1135 * When disabling dmac, dmac enable dmac bit is cleared.
1136 **/
1137 s32 ixgbe_dmac_config(struct ixgbe_hw *hw)
1138 {
1139 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw),
1140 IXGBE_NOT_IMPLEMENTED);
1141 }
1142
1143 /**
1144 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.
1145 * @hw: pointer to hardware structure
1146 *
1147 * Disables dmac, updates per TC settings, and then enable dmac.
1148 **/
1149 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)
1150 {
1151 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw),
1152 IXGBE_NOT_IMPLEMENTED);
1153 }
1154
1155 /**
1156 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.
1157 * @hw: pointer to hardware structure
1158 *
1159 * Configure DMA coalescing threshold per TC and set high priority bit for
1160 * FCOE TC. The dmac enable bit must be cleared before configuring.
1161 **/
1162 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)
1163 {
1164 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw),
1165 IXGBE_NOT_IMPLEMENTED);
1166 }
1167
1168 /**
1169 * ixgbe_setup_eee - Enable/disable EEE support
1170 * @hw: pointer to the HW structure
1171 * @enable_eee: boolean flag to enable EEE
1172 *
1173 * Enable/disable EEE based on enable_ee flag.
1174 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1175 * are modified.
1176 *
1177 **/
1178 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee)
1179 {
1180 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee),
1181 IXGBE_NOT_IMPLEMENTED);
1182 }
1183
1184 /**
1185 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning
1186 * @hw: pointer to hardware structure
1187 * @enbale: enable or disable source address pruning
1188 * @pool: Rx pool - Rx pool to toggle source address pruning
1189 **/
1190 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
1191 unsigned int pool)
1192 {
1193 if (hw->mac.ops.set_source_address_pruning)
1194 hw->mac.ops.set_source_address_pruning(hw, enable, pool);
1195 }
1196
1197 /**
1198 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing
1199 * @hw: pointer to hardware structure
1200 * @enable: enable or disable switch for Ethertype anti-spoofing
1201 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1202 *
1203 **/
1204 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
1205 {
1206 if (hw->mac.ops.set_ethertype_anti_spoofing)
1207 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf);
1208 }
1209
1210 /**
1211 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register
1212 * @hw: pointer to hardware structure
1213 * @reg_addr: 32 bit address of PHY register to read
1214 * @device_type: type of device you want to communicate with
1215 * @phy_data: Pointer to read data from PHY register
1216 *
1217 * Reads a value from a specified PHY register
1218 **/
1219 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
1220 u32 device_type, u32 *phy_data)
1221 {
1222 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,
1223 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
1224 }
1225
1226 /**
1227 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband
1228 * @hw: pointer to hardware structure
1229 * @reg_addr: 32 bit PHY register to write
1230 * @device_type: type of device you want to communicate with
1231 * @phy_data: Data to write to the PHY register
1232 *
1233 * Writes a value to specified PHY register
1234 **/
1235 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
1236 u32 device_type, u32 phy_data)
1237 {
1238 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,
1239 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
1240 }
1241
1242 /**
1243 * ixgbe_disable_mdd - Disable malicious driver detection
1244 * @hw: pointer to hardware structure
1245 *
1246 **/
1247 void ixgbe_disable_mdd(struct ixgbe_hw *hw)
1248 {
1249 if (hw->mac.ops.disable_mdd)
1250 hw->mac.ops.disable_mdd(hw);
1251 }
1252
1253 /**
1254 * ixgbe_enable_mdd - Enable malicious driver detection
1255 * @hw: pointer to hardware structure
1256 *
1257 **/
1258 void ixgbe_enable_mdd(struct ixgbe_hw *hw)
1259 {
1260 if (hw->mac.ops.enable_mdd)
1261 hw->mac.ops.enable_mdd(hw);
1262 }
1263
1264 /**
1265 * ixgbe_mdd_event - Handle malicious driver detection event
1266 * @hw: pointer to hardware structure
1267 * @vf_bitmap: vf bitmap of malicious vfs
1268 *
1269 **/
1270 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)
1271 {
1272 if (hw->mac.ops.mdd_event)
1273 hw->mac.ops.mdd_event(hw, vf_bitmap);
1274 }
1275
1276 /**
1277 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver
1278 * detection event
1279 * @hw: pointer to hardware structure
1280 * @vf: vf index
1281 *
1282 **/
1283 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)
1284 {
1285 if (hw->mac.ops.restore_mdd_vf)
1286 hw->mac.ops.restore_mdd_vf(hw, vf);
1287 }
1288
1289 /**
1290 * ixgbe_enter_lplu - Transition to low power states
1291 * @hw: pointer to hardware structure
1292 *
1293 * Configures Low Power Link Up on transition to low power states
1294 * (from D0 to non-D0).
1295 **/
1296 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw)
1297 {
1298 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw),
1299 IXGBE_NOT_IMPLEMENTED);
1300 }
1301
1302 /**
1303 * ixgbe_handle_lasi - Handle external Base T PHY interrupt
1304 * @hw: pointer to hardware structure
1305 *
1306 * Handle external Base T PHY interrupt. If high temperature
1307 * failure alarm then return error, else if link status change
1308 * then setup internal/external PHY link
1309 *
1310 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1311 * failure alarm, else return PHY access status.
1312 */
1313 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw)
1314 {
1315 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),
1316 IXGBE_NOT_IMPLEMENTED);
1317 }
1318
1319 /**
1320 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
1321 * @hw: pointer to hardware structure
1322 * @reg: analog register to read
1323 * @val: read value
1324 *
1325 * Performs write operation to analog register specified.
1326 **/
1327 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1328 {
1329 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
1330 val), IXGBE_NOT_IMPLEMENTED);
1331 }
1332
1333 /**
1334 * ixgbe_write_analog_reg8 - Writes 8 bit analog register
1335 * @hw: pointer to hardware structure
1336 * @reg: analog register to write
1337 * @val: value to write
1338 *
1339 * Performs write operation to Atlas analog register specified.
1344 val), IXGBE_NOT_IMPLEMENTED);
1345 }
1346
1347 /**
1348 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
1349 * @hw: pointer to hardware structure
1350 *
1351 * Initializes the Unicast Table Arrays to zero on device load. This
1352 * is part of the Rx init addr execution path.
1353 **/
1354 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
1355 {
1356 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
1357 IXGBE_NOT_IMPLEMENTED);
1358 }
1359
1360 /**
1361 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
1362 * @hw: pointer to hardware structure
1363 * @byte_offset: byte offset to read
1364 * @dev_addr: I2C bus address to read from
1365 * @data: value read
1366 *
1367 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1368 **/
1369 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1370 u8 *data)
1371 {
1372 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
1373 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1374 }
1375
1376 /**
1377 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address
1378 * @hw: pointer to hardware structure
1379 * @byte_offset: byte offset to read
1380 * @dev_addr: I2C bus address to read from
1381 * @data: value read
1382 *
1383 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1384 **/
1385 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1386 u8 dev_addr, u8 *data)
1387 {
1388 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,
1389 (hw, byte_offset, dev_addr, data),
1390 IXGBE_NOT_IMPLEMENTED);
1391 }
1392
1393 /**
1394 * ixgbe_read_i2c_combined - Perform I2C read combined operation
1395 * @hw: pointer to the hardware structure
1396 * @addr: I2C bus address to read from
1397 * @reg: I2C device register to read from
1398 * @val: pointer to location to receive read value
1399 *
1400 * Returns an error code on error.
1401 */
1402 s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
1403 {
1404 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr,
1405 reg, val), IXGBE_NOT_IMPLEMENTED);
1406 }
1407
1408 /**
1409 * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation
1410 * @hw: pointer to the hardware structure
1411 * @addr: I2C bus address to read from
1412 * @reg: I2C device register to read from
1413 * @val: pointer to location to receive read value
1414 *
1415 * Returns an error code on error.
1416 **/
1417 s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,
1418 u16 *val)
1419 {
1420 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked,
1421 (hw, addr, reg, val),
1422 IXGBE_NOT_IMPLEMENTED);
1423 }
1424
1425 /**
1426 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1427 * @hw: pointer to hardware structure
1428 * @byte_offset: byte offset to write
1429 * @dev_addr: I2C bus address to write to
1430 * @data: value to write
1431 *
1432 * Performs byte write operation to SFP module's EEPROM over I2C interface
1433 * at a specified device address.
1434 **/
1435 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1436 u8 data)
1437 {
1438 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
1439 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1440 }
1441
1442 /**
1443 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
1444 * @hw: pointer to hardware structure
1445 * @byte_offset: byte offset to write
1446 * @dev_addr: I2C bus address to write to
1447 * @data: value to write
1448 *
1449 * Performs byte write operation to SFP module's EEPROM over I2C interface
1450 * at a specified device address.
1451 **/
1452 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1453 u8 dev_addr, u8 data)
1454 {
1455 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,
1456 (hw, byte_offset, dev_addr, data),
1457 IXGBE_NOT_IMPLEMENTED);
1458 }
1459
1460 /**
1461 * ixgbe_write_i2c_combined - Perform I2C write combined operation
1462 * @hw: pointer to the hardware structure
1463 * @addr: I2C bus address to write to
1464 * @reg: I2C device register to write to
1465 * @val: value to write
1466 *
1467 * Returns an error code on error.
1468 */
1469 s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
1470 {
1471 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr,
1472 reg, val), IXGBE_NOT_IMPLEMENTED);
1473 }
1474
1475 /**
1476 * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation
1477 * @hw: pointer to the hardware structure
1478 * @addr: I2C bus address to write to
1479 * @reg: I2C device register to write to
1480 * @val: value to write
1481 *
1482 * Returns an error code on error.
1483 **/
1484 s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,
1485 u16 val)
1486 {
1487 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked,
1488 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1489 }
1490
1491 /**
1492 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1493 * @hw: pointer to hardware structure
1494 * @byte_offset: EEPROM byte offset to write
1495 * @eeprom_data: value to write
1496 *
1497 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1498 **/
1499 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
1500 u8 byte_offset, u8 eeprom_data)
1501 {
1502 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
1503 (hw, byte_offset, eeprom_data),
1504 IXGBE_NOT_IMPLEMENTED);
1505 }
1506
1507 /**
1508 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1509 * @hw: pointer to hardware structure
1510 * @byte_offset: EEPROM byte offset to read
1511 * @eeprom_data: value read
1559 /**
1560 * ixgbe_enable_sec_rx_path - Enables the receive data path
1561 * @hw: pointer to hardware structure
1562 *
1563 * Enables the receive data path.
1564 **/
1565 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
1566 {
1567 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
1568 (hw), IXGBE_NOT_IMPLEMENTED);
1569 }
1570
1571 /**
1572 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
1573 * @hw: pointer to hardware structure
1574 * @mask: Mask to specify which semaphore to acquire
1575 *
1576 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
1577 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1578 **/
1579 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1580 {
1581 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
1582 (hw, mask), IXGBE_NOT_IMPLEMENTED);
1583 }
1584
1585 /**
1586 * ixgbe_release_swfw_semaphore - Release SWFW semaphore
1587 * @hw: pointer to hardware structure
1588 * @mask: Mask to specify which semaphore to release
1589 *
1590 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
1591 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1592 **/
1593 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1594 {
1595 if (hw->mac.ops.release_swfw_sync)
1596 hw->mac.ops.release_swfw_sync(hw, mask);
1597 }
1598
1599
1600 void ixgbe_disable_rx(struct ixgbe_hw *hw)
1601 {
1602 if (hw->mac.ops.disable_rx)
1603 hw->mac.ops.disable_rx(hw);
1604 }
1605
1606 void ixgbe_enable_rx(struct ixgbe_hw *hw)
1607 {
1608 if (hw->mac.ops.enable_rx)
1609 hw->mac.ops.enable_rx(hw);
1610 }
1611
1612 /**
1613 * ixgbe_set_rate_select_speed - Set module link speed
1614 * @hw: pointer to hardware structure
1615 * @speed: link speed to set
1616 *
1617 * Set module link speed via the rate select.
1618 */
1619 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
1620 {
1621 if (hw->mac.ops.set_rate_select_speed)
1622 hw->mac.ops.set_rate_select_speed(hw, speed);
1623 }
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