1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37
38 /**
39 * ixgbe_init_shared_code - Initialize the shared code
40 * @hw: pointer to hardware structure
41 *
42 * This will assign function pointers and assign the MAC type and PHY code.
43 * Does not touch the hardware. This function must be called prior to any
44 * other function in the shared code. The ixgbe_hw structure should be
45 * memset to 0 prior to calling this function. The following fields in
46 * hw structure should be filled in prior to calling this function:
47 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
48 * subsystem_vendor_id, and revision_id
49 **/
50 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
51 {
52 s32 status;
53
54 DEBUGFUNC("ixgbe_init_shared_code");
55
56 /*
57 * Set the mac type
58 */
59 status = ixgbe_set_mac_type(hw);
60 if (status != IXGBE_SUCCESS)
61 return (status);
62
63 switch (hw->mac.type) {
64 case ixgbe_mac_82598EB:
65 status = ixgbe_init_ops_82598(hw);
66 break;
67 case ixgbe_mac_82599EB:
68 status = ixgbe_init_ops_82599(hw);
69 break;
70 case ixgbe_mac_X540:
71 status = ixgbe_init_ops_X540(hw);
72 break;
73 default:
74 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
75 break;
76 }
77
78 return status;
79 }
80
81 /**
82 * ixgbe_set_mac_type - Sets MAC type
83 * @hw: pointer to the HW structure
84 *
85 * This function sets the mac type of the adapter based on the
86 * vendor ID and device ID stored in the hw structure.
87 **/
88 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
89 {
90 s32 ret_val = IXGBE_SUCCESS;
91
92 DEBUGFUNC("ixgbe_set_mac_type\n");
93
94 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
95 switch (hw->device_id) {
96 case IXGBE_DEV_ID_82598:
97 case IXGBE_DEV_ID_82598_BX:
98 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
99 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
100 case IXGBE_DEV_ID_82598AT:
101 case IXGBE_DEV_ID_82598AT2:
102 case IXGBE_DEV_ID_82598EB_CX4:
103 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
104 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
105 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
106 case IXGBE_DEV_ID_82598EB_XF_LR:
107 case IXGBE_DEV_ID_82598EB_SFP_LOM:
108 hw->mac.type = ixgbe_mac_82598EB;
109 break;
110 case IXGBE_DEV_ID_82599_KX4:
111 case IXGBE_DEV_ID_82599_KX4_MEZZ:
112 case IXGBE_DEV_ID_82599_XAUI_LOM:
113 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
114 case IXGBE_DEV_ID_82599_KR:
115 case IXGBE_DEV_ID_82599_SFP:
116 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
117 case IXGBE_DEV_ID_82599_SFP_FCOE:
118 case IXGBE_DEV_ID_82599_SFP_EM:
119 case IXGBE_DEV_ID_82599_SFP_SF2:
120 case IXGBE_DEV_ID_82599EN_SFP:
121 case IXGBE_DEV_ID_82599_CX4:
122 case IXGBE_DEV_ID_82599_T3_LOM:
123 hw->mac.type = ixgbe_mac_82599EB;
124 break;
125 case IXGBE_DEV_ID_82599_VF:
126 hw->mac.type = ixgbe_mac_82599_vf;
127 break;
128 case IXGBE_DEV_ID_X540_VF:
129 hw->mac.type = ixgbe_mac_X540_vf;
130 break;
131 case IXGBE_DEV_ID_X540T:
132 case IXGBE_DEV_ID_X540T1:
133 hw->mac.type = ixgbe_mac_X540;
134 break;
135 default:
136 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
137 break;
138 }
139 } else {
140 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
141 }
142
143 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
144 hw->mac.type, ret_val);
145 return ret_val;
146 }
147
148 /**
149 * ixgbe_init_hw - Initialize the hardware
150 * @hw: pointer to hardware structure
151 *
152 * Initialize the hardware by resetting and then starting the hardware
153 **/
154 s32 ixgbe_init_hw(struct ixgbe_hw *hw)
155 {
156 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
157 IXGBE_NOT_IMPLEMENTED);
158 }
159
160 /**
161 * ixgbe_reset_hw - Performs a hardware reset
162 * @hw: pointer to hardware structure
163 *
164 * Resets the hardware by resetting the transmit and receive units, masks and
165 * clears all interrupts, performs a PHY reset, and performs a MAC reset
166 **/
167 s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
168 {
169 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
170 IXGBE_NOT_IMPLEMENTED);
171 }
172
173 /**
174 * ixgbe_start_hw - Prepares hardware for Rx/Tx
175 * @hw: pointer to hardware structure
176 *
177 * Starts the hardware by filling the bus info structure and media type,
178 * clears all on chip counters, initializes receive address registers,
179 * multicast table, VLAN filter table, calls routine to setup link and
180 * flow control settings, and leaves transmit and receive units disabled
181 * and uninitialized.
182 **/
183 s32 ixgbe_start_hw(struct ixgbe_hw *hw)
184 {
185 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
186 IXGBE_NOT_IMPLEMENTED);
187 }
188
189 /**
190 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
191 * which is disabled by default in ixgbe_start_hw();
192 *
193 * @hw: pointer to hardware structure
194 *
195 * Enable relaxed ordering;
196 **/
197 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)
198 {
199 if (hw->mac.ops.enable_relaxed_ordering)
200 hw->mac.ops.enable_relaxed_ordering(hw);
201 }
202
203 /**
204 * ixgbe_clear_hw_cntrs - Clear hardware counters
205 * @hw: pointer to hardware structure
206 *
207 * Clears all hardware statistics counters by reading them from the hardware
208 * Statistics counters are clear on read.
209 **/
210 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
211 {
212 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
213 IXGBE_NOT_IMPLEMENTED);
214 }
215
216 /**
217 * ixgbe_get_media_type - Get media type
218 * @hw: pointer to hardware structure
219 *
220 * Returns the media type (fiber, copper, backplane)
221 **/
222 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
223 {
224 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
225 ixgbe_media_type_unknown);
226 }
227
228 /**
229 * ixgbe_get_mac_addr - Get MAC address
230 * @hw: pointer to hardware structure
231 * @mac_addr: Adapter MAC address
232 *
233 * Reads the adapter's MAC address from the first Receive Address Register
234 * (RAR0) A reset of the adapter must have been performed prior to calling
235 * this function in order for the MAC address to have been loaded from the
236 * EEPROM into RAR0
237 **/
238 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
239 {
240 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
241 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
242 }
243
244 /**
245 * ixgbe_get_san_mac_addr - Get SAN MAC address
246 * @hw: pointer to hardware structure
247 * @san_mac_addr: SAN MAC address
248 *
249 * Reads the SAN MAC address from the EEPROM, if it's available. This is
250 * per-port, so set_lan_id() must be called before reading the addresses.
251 **/
252 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
253 {
254 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
255 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
256 }
257
258 /**
259 * ixgbe_set_san_mac_addr - Write a SAN MAC address
260 * @hw: pointer to hardware structure
261 * @san_mac_addr: SAN MAC address
262 *
263 * Writes A SAN MAC address to the EEPROM.
264 **/
265 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
266 {
267 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
268 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
269 }
270
271 /**
272 * ixgbe_get_device_caps - Get additional device capabilities
273 * @hw: pointer to hardware structure
274 * @device_caps: the EEPROM word for device capabilities
275 *
276 * Reads the extra device capabilities from the EEPROM
277 **/
278 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
279 {
280 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
281 (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
282 }
283
284 /**
285 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
286 * @hw: pointer to hardware structure
287 * @wwnn_prefix: the alternative WWNN prefix
288 * @wwpn_prefix: the alternative WWPN prefix
289 *
290 * This function will read the EEPROM from the alternative SAN MAC address
291 * block to check the support for the alternative WWNN/WWPN prefix support.
292 **/
293 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
294 u16 *wwpn_prefix)
295 {
296 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
297 (hw, wwnn_prefix, wwpn_prefix),
298 IXGBE_NOT_IMPLEMENTED);
299 }
300
301 /**
302 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM
303 * @hw: pointer to hardware structure
304 * @bs: the fcoe boot status
305 *
306 * This function will read the FCOE boot status from the iSCSI FCOE block
307 **/
308 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
309 {
310 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
311 (hw, bs),
312 IXGBE_NOT_IMPLEMENTED);
313 }
314
315 /**
316 * ixgbe_get_bus_info - Set PCI bus info
317 * @hw: pointer to hardware structure
318 *
319 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
320 **/
321 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
322 {
323 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
324 IXGBE_NOT_IMPLEMENTED);
325 }
326
327 /**
328 * ixgbe_get_num_of_tx_queues - Get Tx queues
329 * @hw: pointer to hardware structure
330 *
331 * Returns the number of transmit queues for the given adapter.
332 **/
333 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
334 {
335 return hw->mac.max_tx_queues;
336 }
337
338 /**
339 * ixgbe_get_num_of_rx_queues - Get Rx queues
340 * @hw: pointer to hardware structure
341 *
342 * Returns the number of receive queues for the given adapter.
343 **/
344 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
345 {
346 return hw->mac.max_rx_queues;
347 }
348
349 /**
350 * ixgbe_stop_adapter - Disable Rx/Tx units
351 * @hw: pointer to hardware structure
352 *
353 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
354 * disables transmit and receive units. The adapter_stopped flag is used by
355 * the shared code and drivers to determine if the adapter is in a stopped
356 * state and should not touch the hardware.
357 **/
358 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
359 {
360 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
361 IXGBE_NOT_IMPLEMENTED);
362 }
363
364 /**
365 * ixgbe_read_pba_string - Reads part number string from EEPROM
366 * @hw: pointer to hardware structure
367 * @pba_num: stores the part number string from the EEPROM
368 * @pba_num_size: part number string buffer length
369 *
370 * Reads the part number string from the EEPROM.
371 **/
372 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
373 {
374 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
375 }
376
377 /**
378 * ixgbe_read_pba_num - Reads part number from EEPROM
379 * @hw: pointer to hardware structure
380 * @pba_num: stores the part number from the EEPROM
381 *
382 * Reads the part number from the EEPROM.
383 **/
384 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
385 {
386 return ixgbe_read_pba_num_generic(hw, pba_num);
387 }
388
389 /**
390 * ixgbe_identify_phy - Get PHY type
391 * @hw: pointer to hardware structure
392 *
393 * Determines the physical layer module found on the current adapter.
394 **/
395 s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
396 {
397 s32 status = IXGBE_SUCCESS;
398
399 if (hw->phy.type == ixgbe_phy_unknown) {
400 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
401 IXGBE_NOT_IMPLEMENTED);
402 }
403
404 return status;
405 }
406
407 /**
408 * ixgbe_reset_phy - Perform a PHY reset
409 * @hw: pointer to hardware structure
410 **/
411 s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
412 {
413 s32 status = IXGBE_SUCCESS;
414
415 if (hw->phy.type == ixgbe_phy_unknown) {
416 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)
417 status = IXGBE_ERR_PHY;
418 }
419
420 if (status == IXGBE_SUCCESS) {
421 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
422 IXGBE_NOT_IMPLEMENTED);
423 }
424 return status;
425 }
426
427 /**
428 * ixgbe_get_phy_firmware_version -
429 * @hw: pointer to hardware structure
430 * @firmware_version: pointer to firmware version
431 **/
432 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
433 {
434 s32 status = IXGBE_SUCCESS;
435
436 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
437 (hw, firmware_version),
438 IXGBE_NOT_IMPLEMENTED);
439 return status;
440 }
441
442 /**
443 * ixgbe_read_phy_reg - Read PHY register
444 * @hw: pointer to hardware structure
445 * @reg_addr: 32 bit address of PHY register to read
446 * @phy_data: Pointer to read data from PHY register
447 *
448 * Reads a value from a specified PHY register
449 **/
450 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
451 u16 *phy_data)
452 {
453 s32 status;
454
455 if (hw->phy.id == 0)
456 status = ixgbe_identify_phy(hw);
457 else
458 status = IXGBE_SUCCESS;
459
460 if (status == IXGBE_SUCCESS) {
461 status = ixgbe_call_func(hw, hw->phy.ops.read_reg,
462 (hw, reg_addr, device_type, phy_data),
463 IXGBE_NOT_IMPLEMENTED);
464 }
465 return (status);
466 }
467
468 /**
469 * ixgbe_write_phy_reg - Write PHY register
470 * @hw: pointer to hardware structure
471 * @reg_addr: 32 bit PHY register to write
472 * @phy_data: Data to write to the PHY register
473 *
474 * Writes a value to specified PHY register
475 **/
476 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
477 u16 phy_data)
478 {
479 s32 status;
480
481 if (hw->phy.id == 0)
482 status = ixgbe_identify_phy(hw);
483 else
484 status = IXGBE_SUCCESS;
485
486 if (status == IXGBE_SUCCESS) {
487 status = ixgbe_call_func(hw, hw->phy.ops.write_reg,
488 (hw, reg_addr, device_type, phy_data),
489 IXGBE_NOT_IMPLEMENTED);
490 }
491
492 return status;
493 }
494
495 /**
496 * ixgbe_setup_phy_link - Restart PHY autoneg
497 * @hw: pointer to hardware structure
498 *
499 * Restart autonegotiation and PHY and waits for completion.
500 **/
501 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
502 {
503 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
504 IXGBE_NOT_IMPLEMENTED);
505 }
506
507 /**
508 * ixgbe_check_phy_link - Determine link and speed status
509 * @hw: pointer to hardware structure
510 *
511 * Reads a PHY register to determine if link is up and the current speed for
512 * the PHY.
513 **/
514 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
515 bool *link_up)
516 {
517 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
518 link_up), IXGBE_NOT_IMPLEMENTED);
519 }
520
521 /**
522 * ixgbe_setup_phy_link_speed - Set auto advertise
523 * @hw: pointer to hardware structure
524 * @speed: new link speed
525 * @autoneg: TRUE if autonegotiation enabled
526 *
527 * Sets the auto advertised capabilities
528 **/
529 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
530 bool autoneg,
531 bool autoneg_wait_to_complete)
532 {
533 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
534 autoneg, autoneg_wait_to_complete),
535 IXGBE_NOT_IMPLEMENTED);
536 }
537
538 /**
539 * ixgbe_check_link - Get link and speed status
540 * @hw: pointer to hardware structure
541 *
542 * Reads the links register to determine if link is up and the current speed
543 **/
544 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
545 bool *link_up, bool link_up_wait_to_complete)
546 {
547 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
548 link_up, link_up_wait_to_complete),
549 IXGBE_NOT_IMPLEMENTED);
550 }
551
552 /**
553 * ixgbe_disable_tx_laser - Disable Tx laser
554 * @hw: pointer to hardware structure
555 *
556 * If the driver needs to disable the laser on SFI optics.
557 **/
558 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
559 {
560 if (hw->mac.ops.disable_tx_laser)
561 hw->mac.ops.disable_tx_laser(hw);
562 }
563
564 /**
565 * ixgbe_enable_tx_laser - Enable Tx laser
566 * @hw: pointer to hardware structure
567 *
568 * If the driver needs to enable the laser on SFI optics.
569 **/
570 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
571 {
572 if (hw->mac.ops.enable_tx_laser)
573 hw->mac.ops.enable_tx_laser(hw);
574 }
575
576 /**
577 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
578 * @hw: pointer to hardware structure
579 *
580 * When the driver changes the link speeds that it can support then
581 * flap the tx laser to alert the link partner to start autotry
582 * process on its end.
583 **/
584 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
585 {
586 if (hw->mac.ops.flap_tx_laser)
587 hw->mac.ops.flap_tx_laser(hw);
588 }
589
590 /**
591 * ixgbe_setup_link - Set link speed
592 * @hw: pointer to hardware structure
593 * @speed: new link speed
594 * @autoneg: TRUE if autonegotiation enabled
595 *
596 * Configures link settings. Restarts the link.
597 * Performs autonegotiation if needed.
598 **/
599 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
600 bool autoneg,
601 bool autoneg_wait_to_complete)
602 {
603 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
604 autoneg, autoneg_wait_to_complete),
605 IXGBE_NOT_IMPLEMENTED);
606 }
607
608 /**
609 * ixgbe_get_link_capabilities - Returns link capabilities
610 * @hw: pointer to hardware structure
611 *
612 * Determines the link capabilities of the current configuration.
613 **/
614 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
615 bool *autoneg)
616 {
617 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
618 speed, autoneg), IXGBE_NOT_IMPLEMENTED);
619 }
620
621 /**
622 * ixgbe_led_on - Turn on LEDs
623 * @hw: pointer to hardware structure
624 * @index: led number to turn on
625 *
626 * Turns on the software controllable LEDs.
627 **/
628 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
629 {
630 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
631 IXGBE_NOT_IMPLEMENTED);
632 }
633
634 /**
635 * ixgbe_led_off - Turn off LEDs
636 * @hw: pointer to hardware structure
637 * @index: led number to turn off
638 *
639 * Turns off the software controllable LEDs.
640 **/
641 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
642 {
643 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
644 IXGBE_NOT_IMPLEMENTED);
645 }
646
647 /**
648 * ixgbe_blink_led_start - Blink LEDs
649 * @hw: pointer to hardware structure
650 * @index: led number to blink
651 *
652 * Blink LED based on index.
653 **/
654 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
655 {
656 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
657 IXGBE_NOT_IMPLEMENTED);
658 }
659
660 /**
661 * ixgbe_blink_led_stop - Stop blinking LEDs
662 * @hw: pointer to hardware structure
663 *
664 * Stop blinking LED based on index.
665 **/
666 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
667 {
668 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
669 IXGBE_NOT_IMPLEMENTED);
670 }
671
672 /**
673 * ixgbe_init_eeprom_params - Initialize EEPROM parameters
674 * @hw: pointer to hardware structure
675 *
676 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
677 * ixgbe_hw struct in order to set up EEPROM access.
678 **/
679 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
680 {
681 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
682 IXGBE_NOT_IMPLEMENTED);
683 }
684
685
686 /**
687 * ixgbe_write_eeprom - Write word to EEPROM
688 * @hw: pointer to hardware structure
689 * @offset: offset within the EEPROM to be written to
690 * @data: 16 bit word to be written to the EEPROM
691 *
692 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
693 * called after this function, the EEPROM will most likely contain an
694 * invalid checksum.
695 **/
696 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
697 {
698 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
699 IXGBE_NOT_IMPLEMENTED);
700 }
701
702 /**
703 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
704 * @hw: pointer to hardware structure
705 * @offset: offset within the EEPROM to be written to
706 * @data: 16 bit word(s) to be written to the EEPROM
707 * @words: number of words
708 *
709 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
710 * called after this function, the EEPROM will most likely contain an
711 * invalid checksum.
712 **/
713 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
714 u16 *data)
715 {
716 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
717 (hw, offset, words, data),
718 IXGBE_NOT_IMPLEMENTED);
719 }
720
721 /**
722 * ixgbe_read_eeprom - Read word from EEPROM
723 * @hw: pointer to hardware structure
724 * @offset: offset within the EEPROM to be read
725 * @data: read 16 bit value from EEPROM
726 *
727 * Reads 16 bit value from EEPROM
728 **/
729 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
730 {
731 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
732 IXGBE_NOT_IMPLEMENTED);
733 }
734
735 /**
736 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
737 * @hw: pointer to hardware structure
738 * @offset: offset within the EEPROM to be read
739 * @data: read 16 bit word(s) from EEPROM
740 * @words: number of words
741 *
742 * Reads 16 bit word(s) from EEPROM
743 **/
744 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
745 u16 words, u16 *data)
746 {
747 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
748 (hw, offset, words, data),
749 IXGBE_NOT_IMPLEMENTED);
750 }
751
752 /**
753 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
754 * @hw: pointer to hardware structure
755 * @checksum_val: calculated checksum
756 *
757 * Performs checksum calculation and validates the EEPROM checksum
758 **/
759 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
760 {
761 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
762 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
763 }
764
765 /**
766 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
767 * @hw: pointer to hardware structure
768 **/
769 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
770 {
771 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
772 IXGBE_NOT_IMPLEMENTED);
773 }
774
775 /**
776 * ixgbe_insert_mac_addr - Find a RAR for this mac address
777 * @hw: pointer to hardware structure
778 * @addr: Address to put into receive address register
779 * @vmdq: VMDq pool to assign
780 *
781 * Puts an ethernet address into a receive address register, or
782 * finds the rar that it is aleady in; adds to the pool list
783 **/
784 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
785 {
786 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
787 (hw, addr, vmdq),
788 IXGBE_NOT_IMPLEMENTED);
789 }
790
791 /**
792 * ixgbe_set_rar - Set Rx address register
793 * @hw: pointer to hardware structure
794 * @index: Receive address register to write
795 * @addr: Address to put into receive address register
796 * @vmdq: VMDq "set"
797 * @enable_addr: set flag that address is active
798 *
799 * Puts an ethernet address into a receive address register.
800 **/
801 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
802 u32 enable_addr)
803 {
804 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
805 enable_addr), IXGBE_NOT_IMPLEMENTED);
806 }
807
808 /**
809 * ixgbe_clear_rar - Clear Rx address register
810 * @hw: pointer to hardware structure
811 * @index: Receive address register to write
812 *
813 * Puts an ethernet address into a receive address register.
814 **/
815 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
816 {
817 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
818 IXGBE_NOT_IMPLEMENTED);
819 }
820
821 /**
822 * ixgbe_set_vmdq - Associate a VMDq index with a receive address
823 * @hw: pointer to hardware structure
824 * @rar: receive address register index to associate with VMDq index
825 * @vmdq: VMDq set or pool index
826 **/
827 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
828 {
829 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
830 IXGBE_NOT_IMPLEMENTED);
831
832 }
833
834 /**
835 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
836 * @hw: pointer to hardware structure
837 * @vmdq: VMDq default pool index
838 **/
839 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
840 {
841 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
842 (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
843 }
844
845 /**
846 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
847 * @hw: pointer to hardware structure
848 * @rar: receive address register index to disassociate with VMDq index
849 * @vmdq: VMDq set or pool index
850 **/
851 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
852 {
853 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
854 IXGBE_NOT_IMPLEMENTED);
855 }
856
857 /**
858 * ixgbe_init_rx_addrs - Initializes receive address filters.
859 * @hw: pointer to hardware structure
860 *
861 * Places the MAC address in receive address register 0 and clears the rest
862 * of the receive address registers. Clears the multicast table. Assumes
863 * the receiver is in reset when the routine is called.
864 **/
865 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
866 {
867 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
868 IXGBE_NOT_IMPLEMENTED);
869 }
870
871 /**
872 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
873 * @hw: pointer to hardware structure
874 **/
875 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
876 {
877 return hw->mac.num_rar_entries;
878 }
879
880 /**
881 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
882 * @hw: pointer to hardware structure
883 * @addr_list: the list of new multicast addresses
884 * @addr_count: number of addresses
885 * @func: iterator function to walk the multicast address list
886 *
887 * The given list replaces any existing list. Clears the secondary addrs from
888 * receive address registers. Uses unused receive address registers for the
889 * first secondary addresses, and falls back to promiscuous mode as needed.
890 **/
891 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
892 u32 addr_count, ixgbe_mc_addr_itr func)
893 {
894 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
895 addr_list, addr_count, func),
896 IXGBE_NOT_IMPLEMENTED);
897 }
898
899 /**
900 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
901 * @hw: pointer to hardware structure
902 * @mc_addr_list: the list of new multicast addresses
903 * @mc_addr_count: number of addresses
904 * @func: iterator function to walk the multicast address list
905 *
906 * The given list replaces any existing list. Clears the MC addrs from receive
907 * address registers and the multicast table. Uses unused receive address
908 * registers for the first multicast addresses, and hashes the rest into the
909 * multicast table.
910 **/
911 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
912 u32 mc_addr_count, ixgbe_mc_addr_itr func,
913 bool clear)
914 {
915 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
916 mc_addr_list, mc_addr_count, func, clear),
917 IXGBE_NOT_IMPLEMENTED);
918 }
919
920 /**
921 * ixgbe_enable_mc - Enable multicast address in RAR
922 * @hw: pointer to hardware structure
923 *
924 * Enables multicast address in RAR and the use of the multicast hash table.
925 **/
926 s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
927 {
928 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
929 IXGBE_NOT_IMPLEMENTED);
930 }
931
932 /**
933 * ixgbe_disable_mc - Disable multicast address in RAR
934 * @hw: pointer to hardware structure
935 *
936 * Disables multicast address in RAR and the use of the multicast hash table.
937 **/
938 s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
939 {
940 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
941 IXGBE_NOT_IMPLEMENTED);
942 }
943
944 /**
945 * ixgbe_clear_vfta - Clear VLAN filter table
946 * @hw: pointer to hardware structure
947 *
948 * Clears the VLAN filer table, and the VMDq index associated with the filter
949 **/
950 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
951 {
952 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
953 IXGBE_NOT_IMPLEMENTED);
954 }
955
956 /**
957 * ixgbe_set_vfta - Set VLAN filter table
958 * @hw: pointer to hardware structure
959 * @vlan: VLAN id to write to VLAN filter
960 * @vind: VMDq output index that maps queue to VLAN id in VFTA
961 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
962 *
963 * Turn on/off specified VLAN in the VLAN filter table.
964 **/
965 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
966 {
967 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
968 vlan_on), IXGBE_NOT_IMPLEMENTED);
969 }
970
971 /**
972 * ixgbe_set_vlvf - Set VLAN Pool Filter
973 * @hw: pointer to hardware structure
974 * @vlan: VLAN id to write to VLAN filter
975 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
976 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
977 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
978 * should be changed
979 *
980 * Turn on/off specified bit in VLVF table.
981 **/
982 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
983 bool *vfta_changed)
984 {
985 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
986 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
987 }
988
989 /**
990 * ixgbe_fc_enable - Enable flow control
991 * @hw: pointer to hardware structure
992 *
993 * Configures the flow control settings based on SW configuration.
994 **/
995 s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
996 {
997 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
998 IXGBE_NOT_IMPLEMENTED);
999 }
1000
1001 /**
1002 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
1003 * @hw: pointer to hardware structure
1004 * @maj: driver major number to be sent to firmware
1005 * @min: driver minor number to be sent to firmware
1006 * @build: driver build number to be sent to firmware
1007 * @ver: driver version number to be sent to firmware
1008 **/
1009 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
1010 u8 ver)
1011 {
1012 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1013 build, ver), IXGBE_NOT_IMPLEMENTED);
1014 }
1015
1016
1017 /**
1018 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
1019 * @hw: pointer to hardware structure
1020 * @reg: analog register to read
1021 * @val: read value
1022 *
1023 * Performs write operation to analog register specified.
1024 **/
1025 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1026 {
1027 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
1028 val), IXGBE_NOT_IMPLEMENTED);
1029 }
1030
1031 /**
1032 * ixgbe_write_analog_reg8 - Writes 8 bit analog register
1033 * @hw: pointer to hardware structure
1034 * @reg: analog register to write
1035 * @val: value to write
1036 *
1037 * Performs write operation to Atlas analog register specified.
1038 **/
1039 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
1040 {
1041 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
1042 val), IXGBE_NOT_IMPLEMENTED);
1043 }
1044
1045 /**
1046 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
1047 * @hw: pointer to hardware structure
1048 *
1049 * Initializes the Unicast Table Arrays to zero on device load. This
1050 * is part of the Rx init addr execution path.
1051 **/
1052 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
1053 {
1054 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
1055 IXGBE_NOT_IMPLEMENTED);
1056 }
1057
1058 /**
1059 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
1060 * @hw: pointer to hardware structure
1061 * @byte_offset: byte offset to read
1062 * @data: value read
1063 *
1064 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1065 **/
1066 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1067 u8 *data)
1068 {
1069 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
1070 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1071 }
1072
1073 /**
1074 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1075 * @hw: pointer to hardware structure
1076 * @byte_offset: byte offset to write
1077 * @data: value to write
1078 *
1079 * Performs byte write operation to SFP module's EEPROM over I2C interface
1080 * at a specified device address.
1081 **/
1082 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1083 u8 data)
1084 {
1085 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
1086 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1087 }
1088
1089 /**
1090 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1091 * @hw: pointer to hardware structure
1092 * @byte_offset: EEPROM byte offset to write
1093 * @eeprom_data: value to write
1094 *
1095 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1096 **/
1097 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
1098 u8 byte_offset, u8 eeprom_data)
1099 {
1100 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
1101 (hw, byte_offset, eeprom_data),
1102 IXGBE_NOT_IMPLEMENTED);
1103 }
1104
1105 /**
1106 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1107 * @hw: pointer to hardware structure
1108 * @byte_offset: EEPROM byte offset to read
1109 * @eeprom_data: value read
1110 *
1111 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1112 **/
1113 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
1114 {
1115 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
1116 (hw, byte_offset, eeprom_data),
1117 IXGBE_NOT_IMPLEMENTED);
1118 }
1119
1120 /**
1121 * ixgbe_get_supported_physical_layer - Returns physical layer type
1122 * @hw: pointer to hardware structure
1123 *
1124 * Determines physical layer capabilities of the current configuration.
1125 **/
1126 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
1127 {
1128 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
1129 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1130 }
1131
1132 /**
1133 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
1134 * @hw: pointer to hardware structure
1135 * @regval: bitfield to write to the Rx DMA register
1136 *
1137 * Enables the Rx DMA unit of the device.
1138 **/
1139 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
1140 {
1141 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
1142 (hw, regval), IXGBE_NOT_IMPLEMENTED);
1143 }
1144
1145 /**
1146 * ixgbe_disable_sec_rx_path - Stops the receive data path
1147 * @hw: pointer to hardware structure
1148 *
1149 * Stops the receive data path.
1150 **/
1151 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
1152 {
1153 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
1154 (hw), IXGBE_NOT_IMPLEMENTED);
1155 }
1156
1157 /**
1158 * ixgbe_enable_sec_rx_path - Enables the receive data path
1159 * @hw: pointer to hardware structure
1160 *
1161 * Enables the receive data path.
1162 **/
1163 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
1164 {
1165 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
1166 (hw), IXGBE_NOT_IMPLEMENTED);
1167 }
1168
1169 /**
1170 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
1171 * @hw: pointer to hardware structure
1172 * @mask: Mask to specify which semaphore to acquire
1173 *
1174 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
1175 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1176 **/
1177 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1178 {
1179 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
1180 (hw, mask), IXGBE_NOT_IMPLEMENTED);
1181 }
1182
1183 /**
1184 * ixgbe_release_swfw_semaphore - Release SWFW semaphore
1185 * @hw: pointer to hardware structure
1186 * @mask: Mask to specify which semaphore to release
1187 *
1188 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
1189 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1190 **/
1191 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1192 {
1193 if (hw->mac.ops.release_swfw_sync)
1194 hw->mac.ops.release_swfw_sync(hw, mask);
1195 }
1196