1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 /*
28 * Intel 82365SL device and register definitions
29 */
30
31 #ifndef _PCIC_REG_H
32 #define _PCIC_REG_H
33
34 #pragma ident "%Z%%M% %I% %E% SMI"
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /*
41 * global information
42 */
43 #define PCIC_MAX_CONTROLLERS 4 /* maximum of 4 chips in system */
44
45 /*
46 * per socket information
47 */
48
49 #define PCIC_SOCKETS 2 /* number of sockets per PCIC chip */
50 #define PCIC_MEMWINDOWS 5 /* number of memory windows per socket */
51 #define PCIC_IOWINDOWS 2 /* number of I/O address windows per socket */
52 /* number of windows per chip */
53 #define PCIC_NUMWINDOWS ((PCIC_MEMWINDOWS + PCIC_IOWINDOWS) * PCIC_SOCKETS)
54 /* number of windows per socket */
55 #define PCIC_NUMWINSOCK (PCIC_MEMWINDOWS+PCIC_IOWINDOWS)
56
57 /*
58 * socket selection registers
59 *
60 * the PCIC allows up to 8 sockets per system
61 * this is done by having two sockets per chip and up to 4 chips per
62 * system. There can be up to 4 sockets (2 PCIC chips) per I/O address.
63 * There are two possible I/O address (index register) values.
64 * socket# I/O address value to write to index register
65 * 0 INDEX_REG0 BASE0 + SOCKET_0 + register offset
66 * 1 INDEX_REG0 BASE0 + SOCKET_1 + register offset
67 * 2 INDEX_REG0 BASE1 + SOCKET_0 + register offset
68 * 3 INDEX_REG0 BASE1 + SOCKET_1 + register offset
69 * next 4 are based off of INDEX_REG1
70 */
71
72 #define PCIC_INDEX_REG0 0x3e0 /* first possible index register */
73 #define PCIC_INDEX_REG1 0x3e2 /* second possible index register */
74
75 #define PCIC_BASE0 0x00 /* first set of sockets */
76 #define PCIC_BASE1 0x80 /* second set of sockets */
77
78 #define PCIC_SOCKET_0 0x00 /* first socket */
79 #define PCIC_SOCKET_1 0x40 /* second socket */
80
81 #define PCIC_DATA_REG0 (PCIC_INDEX_REG0+1)
82 #define PCIC_DATA_REG1 (PCIC_INDEX_REG1+1)
83
84 /*
85 * per socket register
86 * these are accessed by writing the offset value into the
87 * index register and adding the appropriate base offset and socket offset
88 * the register is then present in the data register.
89 */
90
91 /* General Registers */
92
93 #define PCIC_CHIP_REVISION 0x00 /* identification and revision */
94 #define PCIC_INTERFACE_STATUS 0x01 /* Interface status */
95 #define PCIC_POWER_CONTROL 0x02 /* Power and RESETDRV control */
96 #define PCIC_CARD_STATUS_CHANGE 0x04 /* card status change */
97 #define PCIC_MAPPING_ENABLE 0x06 /* address window mapping enable */
98 #define PCIC_CARD_DETECT 0x16 /* card detect&general control register */
99 #define PCIC_MISC_CTL_1 0x16 /* CL version */
100 #define PCIC_GLOBAL_CONTROL 0x1e /* global control register */
101 #define PCIC_MISC_CTL_2 0x1e /* CL version */
102 #define PCIC_CHIP_INFO 0x1f /* Cirrus Logic chip info register */
103
104 /* Interrupt Registers */
105
106 #define PCIC_INTERRUPT 0x03 /* interrupt & general control register */
107 #define PCIC_MANAGEMENT_INT 0x05 /* card status change interrupt register */
108
109 /* I/O Registers */
110
111 #define PCIC_IO_CONTROL 0x07 /* I/O Control register */
112 #define PCIC_IO_ADDR_0_STARTLOW 0x08 /* I/O address map 0 start low byte */
113 #define PCIC_IO_ADDR_0_STARTHI 0x09 /* I/O address map 0 start high byte */
114 #define PCIC_IO_ADDR_0_STOPLOW 0x0a /* I/O address map 0 stop low byte */
115 #define PCIC_IO_ADDR_0_STOPHI 0x0b /* I/O address map 0 stop high byte */
116 #define PCIC_IO_OFFSET_LOW 0x36 /* I/O Offset for CL */
117 #define PCIC_IO_OFFSET_HI 0x37
118 #define PCIC_IO_OFFSET_OFFSET 2
119
120 #define PCIC_IO_ADDR_1_OFFSET 5 /* offset to second I/O map register set */
121 #define PCIC_IO_WIN_MASK 0xf
122
123 /* Memory Registers */
124 /* window 0 */
125 #define PCIC_SYSMEM_0_STARTLOW 0x10 /* system memory map 0 start low byte */
126 #define PCIC_SYSMEM_0_STARTHI 0x11 /* system memory map 0 start high byte */
127 #define PCIC_SYSMEM_0_STOPLOW 0x12 /* system memory map 0 stop low byte */
128 #define PCIC_SYSMEM_0_STOPHI 0x13 /* system memory map 0 stop high byte */
129 #define PCIC_CARDMEM_0_LOW 0x14 /* card memory offset 0 low byte */
130 #define PCIC_CARDMEM_0_HI 0x15 /* card memory offset 0 high byte */
131
132 /* window 1 */
133 #define PCIC_SYSMEM_1_STARTLOW 0x18 /* system memory map 0 start low byte */
134 #define PCIC_SYSMEM_1_STARTHI 0x19 /* system memory map 0 start high byte */
135 #define PCIC_SYSMEM_1_STOPLOW 0x1a /* system memory map 0 stop low byte */
136 #define PCIC_SYSMEM_1_STOPHI 0x1b /* system memory map 0 stop high byte */
137 #define PCIC_CARDMEM_1_LOW 0x1c /* card memory offset 0 low byte */
138 #define PCIC_CARDMEM_1_HI 0x1d /* card memory offset 0 high byte */
139
140 #define PCIC_MEM_1_OFFSET 8 /* offset to second memory map register set */
141 #define PCIC_MEM_2_OFFSET 16
142 #define PCIC_MEM_3_OFFSET 24
143 #define PCIC_MEM_4_OFFSET 32
144
145 #define PCIC_IO_OFFSET 4 /* offset to next set of I/O map registers */
146
147 /* Cirrus Logic specific registers */
148 #define PCIC_TIME_SETUP_0 0x3A
149 #define PCIC_TIME_SETUP_1 0x3D
150 #define PCIC_TIME_COMMAND_0 0x3B
151 #define PCIC_TIME_COMMAND_1 0x3E
152 #define PCIC_TIME_RECOVER_0 0x3C
153 #define PCIC_TIME_RECOVER_1 0x3F
154 #define PCIC_ATA_CONTROL 0x26
155 #define PCIC_FIFO_CONTROL 0x17
156 #define PCIC_CL_EXINDEX 0x2e
157 #define PCIC_CL_EXDATA 0x2f
158
159 /*
160 * Cirrus Logic PCI-PCMCIA adapters extension register indicies
161 */
162 #define PCIC_CLEXT_SCRATCH 0x00
163 #define PCIC_CLEXT_DMASK_0 0x01
164 #define PCIC_CLEXT_EXT_CTL_1 0x03
165 #define PCIC_CLEXT_MMAP0_UA 0x05
166 #define PCIC_CLEXT_MMAP1_UA 0x06
167 #define PCIC_CLEXT_MMAP2_UA 0x07
168 #define PCIC_CLEXT_MMAP3_UA 0x08
169 #define PCIC_CLEXT_MMAP4_UA 0x09
170 #define PCIC_CLEXT_EXDATA 0x0a
171 #define PCIC_CLEXT_EXT_CTL_2 0x0b /* 6729 */
172 #define PCIC_CLEXT_MISC_CTL_3 0x25 /* 6730 */
173 #define PCIC_CLEXT_SMB_CTL 0x26 /* 6730 */
174
175 /* the 6832 is mapped into different offsets for extension regs */
176
177 #define PCIC_CBCLEXT_MMAP0_UA 0x40 /* minus the 0x800 */
178 #define PCIC_CBCLEXT_MMAP1_UA 0x41
179 #define PCIC_CBCLEXT_MMAP2_UA 0x42
180 #define PCIC_CBCLEXT_MMAP3_UA 0x43
181 #define PCIC_CBCLEXT_MMAP4_UA 0x44
182 #define PCIC_CBCLEXT_MMAP5_UA 0x45
183
184 #define PCIC_CLEXT_MISC_CTL_3_REV_MASK 0xf0
185
186 /*
187 * Cirrus Logic PCI-PCMCIA PCIC_CLEXT_EXT_CTL_1 reg bit definitions
188 */
189 #define PCIC_CLEXT_IRQ_LVL_MODE 0x08
190 #define PCIC_CLEXT_SMI_LVL_MODE 0x00 /* see errata 1.0 */
191
192 /*
193 * Cirrus Logic PCI-PCMCIA PCIC_MISC_CTL_2 reg bit definitions
194 */
195 #define PCIC_CL_LP_DYN_MODE 0x02 /* low-power dynamic mode */
196 #define PCIC_CL_TIMER_CLK_DIV 0x10 /* PCI clock divide */
197
198 /*
199 * Cirrus Logic PCI-PCMCIA PCIC_CLEXT_MISC_CTL_3 reg bit definitions
200 */
201 #define PCIC_CLEXT_INT_PC_PCI 0x00
202 #define PCIC_CLEXT_INT_EXT_HW 0x01
203 #define PCIC_CLEXT_INT_PCI_WAY 0x10
204 #define PCIC_CLEXT_INT_PCI 0x03 /* see errata 1.0 */
205 #define PCIC_CLEXT_PWR_EXT_HW 0x00
206 #define PCIC_CLEXT_PWR_RESERVED 0x04
207 #define PCIC_CLEXT_PWR_TI 0x80
208 #define PCIC_CLEXT_PWR_SMB 0xc0
209
210 /*
211 * Intel 82092-AA reg and bit definitions
212 */
213 #define PCIC_82092_PCICON 0x40 /* PCI configuration control */
214 #define PCIC_82092_PCICLK_25MHZ 0x01 /* 25MHz PCI clock */
215 #define PCIC_82092_SLOT_CONFIG 0x06 /* config mask */
216 #define PCIC_82092_2_SOCKETS 0x00 /* 2 sockets */
217 #define PCIC_82092_1_SOCKET 0x02 /* 1 socket + IDE */
218 #define PCIC_82092_4_SOCKETS 0x04 /* 4 sockets + IDE */
219 #define PCIC_82092_EN_TIMING 0x20 /* enhanced memory window timing */
220 #define PCIC_82092_PWB 0x08 /* Post Write Buffering */
221 #define PCIC_82092_RPFB 0x10 /* Read Prefetch Buffering */
222 #define PCIC_82092_PPIRR 0x50 /* interrupt routing register */
223 #define PCIC_82092_SMI_CTL(sock, state) (state << (sock * 2))
224 #define PCIC_82092_IRQ_CTL(sock, state) (state << ((sock * 2) + 1))
225 #define PCIC_82092_CTL_SMI 0x01
226 #define PCIC_82092_CTL_IRQ 0x02
227 #define PCIC_82092_INT_DISABLE 0x00
228 #define PCIC_82092_INT_ENABLE 0x01
229 #define PCIC_82092_CPAGE 0x26 /* CPAGE register */
230
231 /*
232 * identification and revision register
233 */
234 #define PCIC_REV_ID_MASK 0xc0
235 #define PCIC_REV_ID_IO 0x00
236 #define PCIC_REV_ID_MEM 0x40
237 #define PCIC_REV_ID_BOTH 0x80
238
239 /*
240 * interface status register bit definitions
241 */
242 #define PCIC_ISTAT_CD_MASK 0xC /* card detect mask */
243 #define PCIC_CD_PRESENT_OK 0xC /* card is present and fully seated */
244 #define PCIC_CD_NOTPRESENT 0x0 /* card not present */
245 #define PCIC_CD_NOTSEATED_1 0x8 /* card not fully seated */
246 #define PCIC_CD1 0x8
247 #define PCIC_CD_NOTSEATED_2 0x4 /* card not fully seated */
248 #define PCIC_CD2 0x4
249 #define PCIC_WRITE_PROTECT 0x10
250 #define PCIC_READY 0x20
251 #define PCIC_POWER_ON 0x40
252 #define PCIC_VPP_VALID 0x80
253 #define PCIC_BVD1 0x1
254 #define PCIC_BVD2 0x2
255
256 /*
257 * memory register definitions
258 */
259 #define SYSMEM_LOW(x) (((uint32_t)(x)>>12)&0xFF)
260 #define SYSMEM_HIGH(x) (((uint32_t)(x)>>20)&0xF)
261 #define SYSMEM_EXT(x) (((uint32_t)(x)>>24)&0xFF)
262 #define SYSMEM_WINDOW(x) (1<<(x))
263 #define SYSMEM_ZERO_WAIT 0x40 /* zero wait state bit */
264 #define SYSMEM_DATA_16 0x80 /* 16 bit memory bit */
265 #define SYSMEM_MEM16 0x20 /* 16 bit memory in window enable */
266 #define SYSMEM_CLTIMER_SET_0 0x00
267 #define SYSMEM_CLTIMER_SET_1 0x80
268
269 #define SYSMEM_82092_600NS 0x0110
270 #define SYSMEM_82092_250NS 0x0101
271 #define SYSMEM_82092_200NS 0x0100
272 #define SYSMEM_82092_150NS 0x0011
273 #define SYSMEM_82092_100NS 0x0010
274 #define SYSMEM_82092_80NS 0x0001
275
276 #define DEFAULT_AM_ADDR 0xd0000
277
278 #define CARDMEM_REG_ACTIVE 0x40
279 #define CARDMEM_WRITE_PROTECT 0x80
280
281 #define CARDMEM_LOW(x) (((uint32_t)((x))>>12)&0xFF)
282 #define CARDMEM_HIGH(x) (((uint32_t)((x))>>20)&0x3F)
283
284 #define POWER_CARD_ENABLE 0x10
285 #define POWER_3VCARD_ENABLE 0x18
286 #define POWER_OUTPUT_ENABLE 0x80
287 #define POWER_VPP_VCC_ENABLE 0x01
288 #define POWER_VPP_12V_ENABLE 0x02
289
290 /* interrupt register definitions */
291 #define PCIC_INTR_ENABLE 0x10
292 #define PCIC_IO_CARD 0x20
293 #define PCIC_RESET 0x40
294 #define PCIC_INTR_MASK 0x0f
295
296 /* card status change register definitions */
297 #define PCIC_CD_DETECT 0x08
298 #define PCIC_RD_DETECT 0x04
299 #define PCIC_BW_DETECT 0x02
300 #define PCIC_BD_DETECT 0x01
301 #define PCIC_CHANGE_MASK 0x0f
302
303 /* card status change interrupt register definitions */
304 #define PCIC_CD_ENABLE 0x08 /* card detect enable */
305 #define PCIC_RD_ENABLE 0x04 /* ready change enable */
306 #define PCIC_BW_ENABLE 0x02 /* battery warning enable */
307 #define PCIC_BD_ENABLE 0x01 /* battery deat enable */
308 #define PCIC_GPI_CHANGE 0x10 /* general purpose interrupt */
309 #define PCIC_CHANGE_DEFAULT (PCIC_CD_ENABLE|PCIC_RD_ENABLE|\
310 PCIC_BW_ENABLE|PCIC_BD_ENABLE)
311
312 /* card detect change register */
313 #define PCIC_GPI_ENABLE 0x04
314 #define PCIC_GPI_TRANSITION 0x08
315 #define PCIC_16MDI 0x01
316 #define PCIC_SOFT_CD_INTR 0x20
317
318 /* misc control 1 */
319 #define PCIC_MC_5VDETECT 0x01
320 #define PCIC_MC_3VCC 0x02
321 #define PCIC_MC_PULSE_SMI 0x04
322 #define PCIC_MC_PULSE_IRQ 0x08
323 #define PCIC_MC_SPEAKER_ENB 0x10
324 #define PCIC_MC_INPACK_ENB 0x80
325
326 /* global control registers definitions */
327 #define PCIC_GC_POWERDOWN 0x01
328 #define PCIC_GC_LEVELMODE 0x02
329 #define PCIC_GC_CSC_WRITE 0x04
330 #define PCIC_GC_IRQ1_PULSE 0x08
331
332 /* misc control 2 */
333 #define PCIC_MC_BYPASS_FS 0x01
334 #define PCIC_MC_LOWPOWER 0x02
335 #define PCIC_MC_SUSPEND 0x04
336 #define PCIC_5V_CORE 0x08
337 #define PCIC_LED_ENABLE 0x10
338 #define PCIC_THREESTATE 0x20
339 #define PCIC_CL_DMA 0x40
340 #define PCIC_IRQ15_RI_OUT 0x80
341
342 /* chip info register (Cirrus) definitions */
343 #define PCIC_CI_ID 0xc0
344 #define PCIC_CI_SLOTS 0x20
345
346 /* Vadem unique registers */
347 #define PCIC_VADEM_P1 0x0E
348 #define PCIC_VADEM_P2 0x37
349
350 #define PCIC_VG_VSENSE 0x1f
351 #define PCIC_VG_VSELECT 0x2f
352 #define PCIC_VG_CONTROL 0x38
353 #define PCIC_VG_TIMER 0x39
354 #define PCIC_VG_DMA 0x3A
355 #define PCIC_VG_EXT_A 0x3C
356 #define PCIC_VG_STATUS 0x3E
357
358 /* Vadem DMA Register */
359 #define PCIC_V_DMAWSB 0x04
360 #define PCIC_V_VADEMREV 0x40
361 #define PCIC_V_UNLOCK 0x80
362
363 /* Vadem identification register */
364 #define PCIC_VADEM_D3 0x8
365 #define PCIC_VADEM_365 0x9
366 #define PCIC_VADEM_465 0x8
367 #define PCIC_VADEM_468 0xB
368 #define PCIC_VADEM_469 0xC
369
370 /* Vadem Voltage Select */
371 #define PCIC_VSEL_EXTENDED 0x10 /* extended mode */
372 #define PCIC_VSEL_BUSSEL 0x20 /* extended buffers on ISA */
373
374 /* Vadem Control Register */
375 #define PCIC_VC_DELAYENABLE 0x10
376
377 /* Vadem Extended Mode Register A */
378 #define PCIC_VEXT_CABLEMODE 0x08 /* enable external cable */
379
380 #define PCIC_YENTA_MEM_PAGE 0x40 /* yenta defined extended address byte */
381
382 /* Ricoh Specific Registers */
383 #define PCIC_RF_CHIP_IDENT 0x3A
384 #define PCIC_RF_296 0x32
385 #define PCIC_RF_396 0xB2
386 #define PCIC_RF_MEM_PAGE PCIC_YENTA_MEM_PAGE
387
388 /* O2 Micro Specific registers */
389 #define PCIC_CENTDMA 0x3C
390 #define PCIC_MULTIFUNC 0x8C
391 #define PCIC_O2_CTRL1 0xD0
392 #define PCIC_O2_CTRL2 0xD4
393
394 /* Texas Instruments specific Registers */
395 #define PCIC_INTLINE_REG 0x3C
396 #define PCIC_INTPIN_REG 0x3D
397 #define PCIC_BRIDGE_CTL_REG 0x3e
398 #define PCIC_FUN_INT_MOD_ISA 0x80
399
400 /* for PCI1420 chip */
401 #define PCIC_BRDGCTL_INTR_MASK 0x80
402 #define PCIC_GPIO0_REG 0x88
403 #define PCIC_GPIO1_REG 0x89
404 #define PCIC_GPIO2_REG 0x8A
405 #define PCIC_GPIO3_REG 0x8B
406
407 #define PCIC_MFROUTE_REG 0x8c
408 #define PCIC_MFUNC0_MASK 0xF
409 #define PCIC_MFUNC0_INTA 0x2
410
411 #define PCIC_DIAG_REG 0x93
412 #define PCIC_GPIO_FMASK 0xC0
413 #define PCIC_GPIO_INTENBL 0x10
414 #define PCIC_GPIO_DELTA 0x08
415 #define PCIC_GPIO_DOUT 0x02
416 #define PCIC_GPIO_DIN 0x01
417 #define PCIC_GPIO_FOUTPUT 0xC0
418 #define PCIC_GPIO_FINPUT 0x80
419 #define PCIC_GPIO2_IS_PCILOCK 0x00
420 #define PCIC_GPIO3_IS_INTA 0x00
421 #define PCIC_TI_WINDOW_PAGE 0x3C /* legacy */
422 #define PCIC_TI_WINDOW_PAGE_PCI 0x40
423
424 #define PCIC_DIAG_REG 0x93 /* Diagnostic Register */
425 /* for PCI1225 chip */
426 #define PCIC_DIAG_CSC 0x20 /* CSC Interrupt Routing Control */
427 /* for PCI1221 and PCI1225 chips */
428 #define PCIC_DIAG_ASYNC 0x01 /* Async. interrupt enable */
429
430 #define PCIC_DEVCTL_REG 0x92 /* Device Control Register */
431 #define PCIC_DEVCTL_INTR_MASK 0x06 /* to mask out mode */
432 #define PCIC_DEVCTL_INTR_PCI 0x00 /* PCI style interrupts */
433 #define PCIC_DEVCTL_INTR_ISA 0x02 /* ISA style interrupts */
434 #define PCIC_DEVCTL_INTR_SER 0x04 /* serialize IRQ scheme */
435 #define PCIC_DEVCTL_INTR_RSVD 0x06 /* reserved */
436 /* for PCI1221 and PCI1225 chips */
437 #define PCIC_DEVCTL_3VCAPABLE 0x40 /* 3V socket capable force */
438 #define PCIC_DEVCTL_INTR_DFLT 0x06 /* default interrupt mode */
439
440 #define PCIC_CRDCTL_REG 0x91 /* Card Control Register */
441 #define PCIC_CRDCTL_RIENABLE 0x80 /* Ring indicate enable on TI1250a */
442 #define PCIC_CRDCTL_ZVENABLE 0x40 /* Z buffer enable on TI1250a */
443 #define PCIC_CRDCTL_PCIINTR 0x20 /* use PCI INT A/B */
444 #define PCIC_CRDCTL_PCICSC 0x10 /* PCI intr for status */
445 #define PCIC_CRDCTL_PCIFUNC 0x08 /* use PCI intr for cards */
446 #define PCIC_CRDCTL_SPKR_ENBL 0x02 /* Enable speaker plumbing */
447 #define PCIC_CRDCTL_IFG 0x01 /* card interrupt flag */
448
449 #define PCIC_SYSCTL_REG 0x80 /* System Control Register */
450 #define PCIC_SYSCTL_INTRTIE 0x20 /* tie INTA and INTB */
451
452 /* for Toshiba chips */
453 #define PCIC_TOSHIBA_SLOT_CTL_REG 0xa0 /* slot control register */
454 #define PCIC_TOSHIBA_SCR_SLOTON 0x80
455 #define PCIC_TOSHIBA_SCR_SLOTEN 0x40
456 #define PCIC_TOSHIBA_SCR_PRT_MASK 0xc
457 #define PCIC_TOSHIBA_SCR_PRT_3E0 0x0
458 #define PCIC_TOSHIBA_SCR_PRT_3E2 0x4
459 #define PCIC_TOSHIBA_SCR_PRT_3E4 0x8
460 #define PCIC_TOSHIBA_SCR_PRT_3E6 0xc
461 #define PCIC_TOSHIBA_INTR_CTL_REG 0xa1 /* interrupt control register */
462 #define PCIC_TOSHIBA_ICR_PIN_MASK 0x30
463 #define PCIC_TOSHIBA_ICR_PIN_DISEN 0x0
464 #define PCIC_TOSHIBA_ICR_PIN_INTA 0x10
465 #define PCIC_TOSHIBA_ICR_PIN_INTB 0x20
466 #define PCIC_TOSHIBA_ICR_MOD_CSC 0x4 /* CSC interrupt mode */
467 #define PCIC_TOSHIBA_ICR_MOD_FUN 0x2 /* Funtional interrupt mode */
468 #define PCIC_TOSHIBA_ICR_SRC 0x1 /* INTA or IRQ */
469
470 /* for Ricoh chips */
471 #define PCIC_RICOH_MISC_CTL 0x82
472 #define PCIC_RICOH_SIRQ_EN 0x80 /* serialized IRQ */
473 #define PCIC_RICOH_MISC_CTL_2 0xa0 /* ricoh */
474 #define PCIC_RICOH_CSC_INT_MOD 0x80 /* csc to ISA */
475 #define PCIC_RICOH_FUN_INT_MOD 0x40 /* cint to ISA */
476
477 /* for o2micro */
478 #define PCIC_O2MICRO_MISC_CTL 0x28
479 #define PCIC_O2MICRO_INT_MOD_MASK 0x300
480 #define PCIC_O2MICRO_INT_MOD_PCI 0x300
481 #define PCIC_O2MICRO_ISA_LEGACY 0x800
482 /* */
483
484 /* SMC 34C90 specific registers */
485 #define PCIC_SMC_MEM_PAGE 0x40
486
487 /* available interrupts and interrupt mask */
488 #define PCIC_IRQ(irq) (1 << (irq))
489 #define PCIC_IRQ03 PCIC_IRQ(3)
490 #define PCIC_IRQ04 PCIC_IRQ(4)
491 #define PCIC_IRQ05 PCIC_IRQ(5)
492 #define PCIC_IRQ07 PCIC_IRQ(7)
493 #define PCIC_IRQ09 PCIC_IRQ(9)
494 #define PCIC_IRQ10 PCIC_IRQ(10)
495 #define PCIC_IRQ11 PCIC_IRQ(11)
496 #define PCIC_IRQ12 PCIC_IRQ(12)
497 #define PCIC_IRQ14 PCIC_IRQ(14)
498 #define PCIC_IRQ15 PCIC_IRQ(15)
499
500 #define PCIC_AVAIL_IRQS (PCIC_IRQ03|PCIC_IRQ04|PCIC_IRQ05|PCIC_IRQ07|\
501 PCIC_IRQ09|PCIC_IRQ10|PCIC_IRQ11|PCIC_IRQ12|\
502 PCIC_IRQ14|PCIC_IRQ15)
503
504 /* page size used for window mapping and memory resource page size */
505 #define PCIC_PAGE 4096
506
507 /* used in I/O window mapping */
508 #define HIGH_BYTE(x) (uchar_t)((((ushort_t)(x)) >> 8) & 0xFF)
509 #define LOW_BYTE(x) (uchar_t)(((ushort_t)(x)) & 0xFF)
510 #define PCIC_IO_0_MASK 0x0f
511 #define PCIC_IO_1_MASK 0xf0
512 #define IOMEM_WINDOW(x) (1<<((x)+6))
513
514 #define IOMEM_16BIT 0x01
515 #define IOMEM_IOCS16 0x02
516 #define IOMEM_ZERO_WAIT 0x04
517 #define IOMEM_CLTIMER_SET_0 0x00 /* CL timer set selection */
518 #define IOMEM_CLTIMER_SET_1 0x08 /* CL timer set selection */
519 #define IOMEM_WAIT16 0x08
520 #define IOMEM_SETWIN(w, x) ((x) << ((w)*4))
521
522 #define IOMEM_FIRST 0 /* First I/O address */
523 #define IOMEM_LAST 0xFFFF /* Last I/O address */
524 #define IOMEM_MIN 1 /* minimum I/O window size */
525 #define IOMEM_MAX 0x10000 /* maximum I/O window size */
526 #define IOMEM_GRAN 1 /* granularity of request */
527 #define IOMEM_DECODE 16 /* number of address lines decoded */
528
529 #define MEM_FIRST 0x10000 /* first memory address */
530 #define MEM_LAST 0xFFFFF /* last memory address */
531 #define MEM_MIN PCIC_PAGE /* minimum window size */
532 #define MEM_MAX 0x10000 /* maximum window size */
533 #define PAGE_SHIFT 12 /* bits to shift */
534
535 #define SYSCLK 120 /* sysclk min time (ns) */
536 #define MEM_SPEED_MIN (SYSCLK*2)
537 #define MEM_SPEED_MAX (SYSCLK*6)
538
539 /* CardBus (Yenta) specific values */
540 #define CB_R2_OFFSET 0x800 /* R2 is always at offset 0x800 */
541 #define CB_CLEXT_OFFSET 0x900 /* Cirrus Logic extended at offset 0x900 */
542 #define CB_CB_OFFSET 0x00 /* Cardbus registers at offset 0 */
543
544 /* Cardbus registers in TI 1250A/Cirrus 6832 and probably others. */
545 /* Register offsets (these are 32 bit registers). */
546 #define CB_STATUS_EVENT 0x00
547 #define CB_STATUS_MASK 0x04
548 #define CB_PRESENT_STATE 0x08
549 #define CB_EVENT_FORCE 0x0c
550 #define CB_CONTROL 0x10
551
552 /* TI1420 */
553 #define CB_SOCKET_POWER 0x20
554
555 /* Cardbus registers in 02 0Z6912. */
556 #define CB_SZVCTRL 0x20
557 #define CB_SIMDCTRL 0x24
558 #define CB_MISCCTRL 0x28
559
560 /* Register bit definitions. */
561 #define BYTE_3(x) ((x)<<24)
562 #define BYTE_2(x) ((x)<<16)
563 #define BYTE_1(x) ((x)<<8)
564 #define BYTE_0(x) (x)
565
566 #define CB_SE_POWER_CYCLE BYTE_0(0x08)
567 #define CB_SE_CCDMASK BYTE_0(0x06)
568 #define CB_SE_CCD2 BYTE_0(0x04)
569 #define CB_SE_CCD1 BYTE_0(0x02)
570 #define CB_SE_CSTSCHG BYTE_0(0x01)
571
572 #define CB_SM_POWER_CYCLE BYTE_0(0x08)
573 #define CB_SM_CCDMASK BYTE_0(0x06)
574 #define CB_SM_CCD2 BYTE_0(0x04)
575 #define CB_SM_CCD1 BYTE_0(0x02)
576 #define CB_SM_CSTSCHG BYTE_0(0x01)
577
578 #define CB_PS_CSTSCHG BYTE_0(0x01)
579 #define CB_PS_CCDMASK BYTE_0(0x06)
580 #define CB_PS_NCCD1 BYTE_0(0x02)
581 #define CB_PS_NCCD2 BYTE_0(0x04)
582 #define CB_PS_POWER_CYCLE BYTE_0(0x08)
583 #define CB_PS_16BITCARD BYTE_0(0x10)
584 #define CB_PS_CBCARD BYTE_0(0x20)
585 #define CB_PS_INTERRUPT BYTE_0(0x40)
586 #define CB_PS_NOTACARD BYTE_0(0x80)
587
588 #define CB_PS_DATALOST BYTE_1(0x01)
589 #define CB_PS_BADVCC BYTE_1(0x02)
590 #define CB_PS_50VCARD BYTE_1(0x04)
591 #define CB_PS_33VCARD BYTE_1(0x08)
592 #define CB_PS_XVCARD BYTE_1(0x10)
593 #define CB_PS_YVCARD BYTE_1(0x20)
594
595 #define CB_PS_50VSOCKET BYTE_3(0x10)
596 #define CB_PS_33VSOCKET BYTE_3(0x20)
597 #define CB_PS_XVSOCKET BYTE_3(0x40)
598 #define CB_PS_YVSOCKET BYTE_3(0x80)
599
600 #define CB_EF_CSTSCHG BYTE_0(0x01)
601 #define CB_EF_CCD1 BYTE_0(0x02)
602 #define CB_EF_CCD2 BYTE_0(0x04)
603 #define CB_EF_POWER_CYCLE BYTE_0(0x08)
604 #define CB_EF_16BITCARD BYTE_0(0x10)
605 #define CB_EF_CBCARD BYTE_0(0x20)
606 #define CB_EF_NOTACARD BYTE_0(0x80)
607
608 #define CB_EF_DATALOST BYTE_1(0x01)
609 #define CB_EF_BADVCC BYTE_1(0x02)
610 #define CB_EF_50V BYTE_1(0x04)
611 #define CB_EF_33V BYTE_1(0x08)
612 #define CB_EF_XV BYTE_1(0x10)
613 #define CB_EF_YV BYTE_1(0x20)
614 #define CB_EF_CVTEST BYTE_1(0x40)
615
616 #define CB_C_VPPMASK BYTE_0(0x07)
617 #define CB_C_VCCMASK BYTE_0(0x70)
618
619 #define CB_C_VPP0V BYTE_0(0x00)
620 #define CB_C_VPP12V BYTE_0(0x01)
621 #define CB_C_VPPVCC BYTE_0(0x03)
622
623 #define CB_C_VCC0V BYTE_0(0x00)
624 #define CB_C_VCC50V BYTE_0(0x20)
625 #define CB_C_VCC33V BYTE_0(0x30)
626
627 #ifdef __cplusplus
628 }
629 #endif
630
631 #endif /* _PCIC_REG_H */