1 '\" te 2 .\" Copyright (c) 1996, Sun Microsystems, Inc. All Rights Reserved 3 .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. 4 .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. 5 .\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] 6 .TH CSX_PARSE_CISTPL_CFTABLE_ENTRY 9F "Dec 20, 1996" 7 .SH NAME 8 csx_Parse_CISTPL_CFTABLE_ENTRY \- parse 16-bit Card Configuration Table Entry 9 tuple 10 .SH SYNOPSIS 11 .LP 12 .nf 13 #include <sys/pccard.h> 14 15 16 17 \fBint32_t\fR \fBcsx_Parse_CISTPL_CFTABLE_ENTRY\fR(\fBclient_handle_t\fR \fIch\fR, \fBtuple_t *\fR\fItu\fR, 18 \fBcistpl_cftable_entry_t *\fR\fIcft\fR); 19 .fi 20 21 .SH INTERFACE LEVEL 22 .sp 23 .LP 24 Solaris \fBDDI \fRSpecific (Solaris \fBDDI) \fR 25 .SH PARAMETERS 26 .sp 27 .ne 2 28 .na 29 \fB\fIch\fR\fR 30 .ad 31 .RS 7n 32 Client handle returned from \fBcsx_RegisterClient\fR(9F). 33 .RE 34 35 .sp 36 .ne 2 37 .na 38 \fB\fItu\fR\fR 39 .ad 40 .RS 7n 41 Pointer to a \fBtuple_t\fR structure (see \fBtuple\fR(9S)) returned by a call 42 to \fBcsx_GetFirstTuple\fR(9F) or \fBcsx_GetNextTuple\fR(9F). 43 .RE 44 45 .sp 46 .ne 2 47 .na 48 \fB\fIcft\fR\fR 49 .ad 50 .RS 7n 51 Pointer to a \fBcistpl_cftable_entry_t\fR structure which contains the parsed 52 \fBCISTPL_CFTABLE_ENTRY\fR tuple information upon return from this function. 53 .RE 54 55 .SH DESCRIPTION 56 .sp 57 .LP 58 This function parses the 16 bit Card Configuration Table Entry tuple, 59 \fBCISTPL_CFTABLE_ENTRY,\fR into a form usable by \fBPC \fRCard drivers. 60 .sp 61 .LP 62 The \fBCISTPL_CFTABLE_ENTRY\fR tuple is used to describe each possible 63 configuration of a \fBPC \fRCard and to distinguish among the permitted 64 configurations. The \fBCISTPL_CONFIG\fR tuple must precede all 65 \fBCISTPL_CFTABLE_ENTRY\fR tuples. 66 .SH STRUCTURE MEMBERS 67 .sp 68 .LP 69 The structure members of \fBcistpl_cftable_entry_t\fR are: 70 .sp 71 .in +2 72 .nf 73 uint32_t flags; /* valid descriptions */ 74 uint32_t ifc; /* interface description */ 75 /* information */ 76 uint32_t pin; /* values for PRR */ 77 uint32_t index; /* configuration index number */ 78 cistpl_cftable_entry_pd_t pd; /* power requirements */ 79 /* description */ 80 cistpl_cftable_entry_speed_t speed; /* device speed description */ 81 cistpl_cftable_entry_io_t io; /* device I/O map */ 82 cistpl_cftable_entry_irq_t irq; /* device IRQ utilization */ 83 cistpl_cftable_entry_mem_t mem; /* device memory space */ 84 cistpl_cftable_entry_misc_t misc; /* miscellaneous 85 /* device features */ 86 .fi 87 .in -2 88 89 .sp 90 .LP 91 The \fBflags\fR field is defined and bit-mapped as follows: 92 .sp 93 .ne 2 94 .na 95 \fBCISTPL_CFTABLE_TPCE_DEFAULT\fR 96 .ad 97 .sp .6 98 .RS 4n 99 This is a default configuration 100 .RE 101 102 .sp 103 .ne 2 104 .na 105 \fBCISTPL_CFTABLE_TPCE_IF\fR 106 .ad 107 .sp .6 108 .RS 4n 109 If configuration byte exists 110 .RE 111 112 .sp 113 .ne 2 114 .na 115 \fBCISTPL_CFTABLE_TPCE_FS_PWR\fR 116 .ad 117 .sp .6 118 .RS 4n 119 Power information exists 120 .RE 121 122 .sp 123 .ne 2 124 .na 125 \fBCISTPL_CFTABLE_TPCE_FS_TD\fR 126 .ad 127 .sp .6 128 .RS 4n 129 Timing information exists 130 .RE 131 132 .sp 133 .ne 2 134 .na 135 \fBCISTPL_CFTABLE_TPCE_FS_IO\fR 136 .ad 137 .sp .6 138 .RS 4n 139 I/O information exists 140 .RE 141 142 .sp 143 .ne 2 144 .na 145 \fBCISTPL_CFTABLE_TPCE_FS_IRQ\fR 146 .ad 147 .sp .6 148 .RS 4n 149 IRQ information exists 150 .RE 151 152 .sp 153 .ne 2 154 .na 155 \fBCISTPL_CFTABLE_TPCE_FS_MEM\fR 156 .ad 157 .sp .6 158 .RS 4n 159 MEM space information exists 160 .RE 161 162 .sp 163 .ne 2 164 .na 165 \fBCISTPL_CFTABLE_TPCE_FS_MISC\fR 166 .ad 167 .sp .6 168 .RS 4n 169 MISC information exists 170 .RE 171 172 .sp 173 .ne 2 174 .na 175 \fBCISTPL_CFTABLE_TPCE_FS_STCE_EV\fR 176 .ad 177 .sp .6 178 .RS 4n 179 STCE_EV exists 180 .RE 181 182 .sp 183 .ne 2 184 .na 185 \fBCISTPL_CFTABLE_TPCE_FS_STCE_PD\fR 186 .ad 187 .sp .6 188 .RS 4n 189 STCE_PD exists 190 .RE 191 192 .sp 193 .LP 194 If the \fBCISTPL_CFTABLE_TPCE_IF\fR flag is set, the \fBifc\fR field is 195 bit-mapped and defined as follows: 196 .sp 197 .ne 2 198 .na 199 \fBCISTPL_CFTABLE_TPCE_IF_MEMORY\fR 200 .ad 201 .sp .6 202 .RS 4n 203 Memory interface 204 .RE 205 206 .sp 207 .ne 2 208 .na 209 \fBCISTPL_CFTABLE_TPCE_IF_IO_MEM\fR 210 .ad 211 .sp .6 212 .RS 4n 213 IO and memory 214 .RE 215 216 .sp 217 .ne 2 218 .na 219 \fBCISTPL_CFTABLE_TPCE_IF_CUSTOM_0\fR 220 .ad 221 .sp .6 222 .RS 4n 223 Custom interface 0 224 .RE 225 226 .sp 227 .ne 2 228 .na 229 \fBCISTPL_CFTABLE_TPCE_IF_CUSTOM_1\fR 230 .ad 231 .sp .6 232 .RS 4n 233 Custom interface 1 234 .RE 235 236 .sp 237 .ne 2 238 .na 239 \fBCISTPL_CFTABLE_TPCE_IF_CUSTOM_2\fR 240 .ad 241 .sp .6 242 .RS 4n 243 Custom interface 2 244 .RE 245 246 .sp 247 .ne 2 248 .na 249 \fBCISTPL_CFTABLE_TPCE_IF_CUSTOM_3\fR 250 .ad 251 .sp .6 252 .RS 4n 253 Custom interface 3 254 .RE 255 256 .sp 257 .ne 2 258 .na 259 \fBCISTPL_CFTABLE_TPCE_IF_MASK\fR 260 .ad 261 .sp .6 262 .RS 4n 263 Interface type mask 264 .RE 265 266 .sp 267 .ne 2 268 .na 269 \fBCISTPL_CFTABLE_TPCE_IF_BVD\fR 270 .ad 271 .sp .6 272 .RS 4n 273 BVD active in PRR 274 .RE 275 276 .sp 277 .ne 2 278 .na 279 \fBCISTPL_CFTABLE_TPCE_IF_WP\fR 280 .ad 281 .sp .6 282 .RS 4n 283 WP active in PRR 284 .RE 285 286 .sp 287 .ne 2 288 .na 289 \fBCISTPL_CFTABLE_TPCE_IF_RDY\fR 290 .ad 291 .sp .6 292 .RS 4n 293 RDY active in PRR 294 .RE 295 296 .sp 297 .ne 2 298 .na 299 \fBCISTPL_CFTABLE_TPCE_IF_MWAIT\fR 300 .ad 301 .sp .6 302 .RS 4n 303 WAIT - mem cycles 304 .RE 305 306 .sp 307 .LP 308 \fBpin\fR is a value for the Pin Replacement Register. 309 .sp 310 .LP 311 \fBindex\fR is a configuration index number. 312 .sp 313 .LP 314 The structure members of \fBcistpl_cftable_entry_pd_t\fR are: 315 .sp 316 .in +2 317 .nf 318 uint32_t flags; /* which descriptions are valid */ 319 cistpl_cftable_entry_pwr_t pd_vcc; /* VCC power description */ 320 cistpl_cftable_entry_pwr_t pd_vpp1; /* Vpp1 power description */ 321 cistpl_cftable_entry_pwr_t pd_vpp2; /* Vpp2 power description */ 322 .fi 323 .in -2 324 325 .sp 326 .LP 327 This \fBflags\fR field is bit-mapped and defined as follows: 328 .sp 329 .ne 2 330 .na 331 \fBCISTPL_CFTABLE_TPCE_FS_PWR_VCC\fR 332 .ad 333 .sp .6 334 .RS 4n 335 Vcc description valid 336 .RE 337 338 .sp 339 .ne 2 340 .na 341 \fBCISTPL_CFTABLE_TPCE_FS_PWR_VPP1\fR 342 .ad 343 .sp .6 344 .RS 4n 345 Vpp1 description valid 346 .RE 347 348 .sp 349 .ne 2 350 .na 351 \fBCISTPL_CFTABLE_TPCE_FS_PWR_VPP2\fR 352 .ad 353 .sp .6 354 .RS 4n 355 Vpp2 description valid 356 .RE 357 358 .sp 359 .LP 360 The structure members of \fBcistpl_cftable_entry_pwr_t\fR are: 361 .sp 362 .in +2 363 .nf 364 uint32_t nomV; /* nominal supply voltage */ 365 uint32_t nomV_flags; 366 uint32_t minV; /* minimum supply voltage */ 367 uint32_t minV_flags; 368 uint32_t maxV; /* maximum supply voltage */ 369 uint32_t maxV_flags; 370 uint32_t staticI; /* continuous supply current */ 371 uint32_t staticI_flags; 372 uint32_t avgI; /* max current required averaged over 1 sec. */ 373 uint32_t avgI_flags; 374 uint32_t peakI; /* max current required averaged over 10mS */ 375 uint32_t peakI_flags; 376 uint32_t pdownI; /* power down supply current required */ 377 uint32_t pdownI_flags; 378 .fi 379 .in -2 380 381 .sp 382 .LP 383 \fBnomV\fR, \fBminV\fR, \fBmaxV\fR, \fBstaticI\fR, \fBavgI\fR, 384 \fBpeakI_flag\fR, and \fBpdownI\fR are defined and bit-mapped as follows: 385 .sp 386 .ne 2 387 .na 388 \fBCISTPL_CFTABLE_PD_NOMV\fR 389 .ad 390 .RS 29n 391 Nominal supply voltage 392 .RE 393 394 .sp 395 .ne 2 396 .na 397 \fBCISTPL_CFTABLE_PD_MINV\fR 398 .ad 399 .RS 29n 400 Minimum supply voltage 401 .RE 402 403 .sp 404 .ne 2 405 .na 406 \fBCISTPL_CFTABLE_PD_MAXV\fR 407 .ad 408 .RS 29n 409 Maximum supply voltage 410 .RE 411 412 .sp 413 .ne 2 414 .na 415 \fBCISTPL_CFTABLE_PD_STATICI\fR 416 .ad 417 .RS 29n 418 Continuous supply current 419 .RE 420 421 .sp 422 .ne 2 423 .na 424 \fBCISTPL_CFTABLE_PD_AVGI\fR 425 .ad 426 .RS 29n 427 Maximum current required averaged over 1 second 428 .RE 429 430 .sp 431 .ne 2 432 .na 433 \fBCISTPL_CFTABLE_PD_PEAKI\fR 434 .ad 435 .RS 29n 436 Maximum current required averaged over 10mS 437 .RE 438 439 .sp 440 .ne 2 441 .na 442 \fBCISTPL_CFTABLE_PD_PDOWNI\fR 443 .ad 444 .RS 29n 445 Power down supply current required 446 .RE 447 448 .sp 449 .LP 450 \fBnomV_flags\fR, \fBminV_flags\fR, \fBmaxV_flags\fR, \fBstaticI_flags\fR, 451 \fBavgI_flags\fR, \fBpeakI_flags\fR, and \fBpdownI_flags\fR are defined and 452 bit-mapped as follows: 453 .sp 454 .ne 2 455 .na 456 \fBCISTPL_CFTABLE_PD_EXISTS\fR 457 .ad 458 .RS 30n 459 This parameter exists 460 .RE 461 462 .sp 463 .ne 2 464 .na 465 \fBCISTPL_CFTABLE_PD_MUL10\fR 466 .ad 467 .RS 30n 468 Multiply return value by 10 469 .RE 470 471 .sp 472 .ne 2 473 .na 474 \fBCISTPL_CFTABLE_PD_NC_SLEEP\fR 475 .ad 476 .RS 30n 477 No connection on sleep/power down 478 .RE 479 480 .sp 481 .ne 2 482 .na 483 \fBCISTPL_CFTABLE_PD_ZERO\fR 484 .ad 485 .RS 30n 486 Zero value required 487 .RE 488 489 .sp 490 .ne 2 491 .na 492 \fBCISTPL_CFTABLE_PD_NC\fR 493 .ad 494 .RS 30n 495 No connection ever 496 .RE 497 498 .sp 499 .LP 500 The structure members of \fBcistpl_cftable_entry_speed_t\fR are: 501 .sp 502 .in +2 503 .nf 504 uint32_t flags; /* which timing information is present */ 505 uint32_t wait; /* max WAIT time in device speed format */ 506 uint32_t nS_wait; /* max WAIT time in nS */ 507 uint32_t rdybsy; /* max RDY/BSY time in device speed format */ 508 uint32_t nS_rdybsy; /* max RDY/BSY time in nS */ 509 uint32_t rsvd; /* max RSVD time in device speed format */ 510 uint32_t nS_rsvd; /* max RSVD time in nS */ 511 .fi 512 .in -2 513 514 .sp 515 .LP 516 The \fBflags\fR field is bit-mapped and defined as follows: 517 .sp 518 .ne 2 519 .na 520 \fBCISTPL_CFTABLE_TPCE_FS_TD_WAIT\fR 521 .ad 522 .sp .6 523 .RS 4n 524 WAIT timing exists 525 .RE 526 527 .sp 528 .ne 2 529 .na 530 \fBCISTPL_CFTABLE_TPCE_FS_TD_RDY\fR 531 .ad 532 .sp .6 533 .RS 4n 534 RDY/BSY timing exists 535 .RE 536 537 .sp 538 .ne 2 539 .na 540 \fBCISTPL_CFTABLE_TPCE_FS_TD_RSVD\fR 541 .ad 542 .sp .6 543 .RS 4n 544 RSVD timing exists 545 .RE 546 547 .sp 548 .LP 549 The structure members of \fBcistpl_cftable_entry_io_t\fR are: 550 .sp 551 .in +2 552 .nf 553 uint32_t flags; /* direct copy of TPCE_IO byte in tuple */ 554 uint32_t addr_lines; /* number of decoded I/O address lines */ 555 uint32_t ranges; /* number of I/O ranges */ 556 cistpl_cftable_entry_io_range_t 557 range[CISTPL_CFTABLE_ENTRY_MAX_IO_RANGES]; 558 .fi 559 .in -2 560 561 .sp 562 .LP 563 The \fBflags\fR field is defined and bit-mapped as follows: 564 .sp 565 .ne 2 566 .na 567 \fBCISTPL_CFTABLE_TPCE_FS_IO_BUS\fR 568 .ad 569 .sp .6 570 .RS 4n 571 Bus width mask 572 .RE 573 574 .sp 575 .ne 2 576 .na 577 \fBCISTPL_CFTABLE_TPCE_FS_IO_BUS8\fR 578 .ad 579 .sp .6 580 .RS 4n 581 8-bit flag 582 .RE 583 584 .sp 585 .ne 2 586 .na 587 \fBCISTPL_CFTABLE_TPCE_FS_IO_BUS16\fR 588 .ad 589 .sp .6 590 .RS 4n 591 16-bit flag 592 .RE 593 594 .sp 595 .ne 2 596 .na 597 \fBCISTPL_CFTABLE_TPCE_FS_IO_RANGE\fR 598 .ad 599 .sp .6 600 .RS 4n 601 IO address ranges exist 602 .RE 603 604 .sp 605 .LP 606 The structure members of \fBcistpl_cftable_entry_io_range_t\fR are: 607 .sp 608 .in +2 609 .nf 610 uint32_t addr; /* I/O start address */ 611 uint32_t length; /* I/O register length */ 612 .fi 613 .in -2 614 615 .sp 616 .LP 617 The structure members of \fBcistpl_cftable_entry_irq_t\fR are: 618 .sp 619 .in +2 620 .nf 621 uint32_t flags; /* direct copy of TPCE_IR byte in tuple */ 622 uint32_t irqs; /* bit mask for each allowed IRQ */ 623 .fi 624 .in -2 625 626 .sp 627 .LP 628 The structure members of \fBcistpl_cftable_entry_mem_t\fR are: 629 .sp 630 .in +2 631 .nf 632 uint32_t flags; /* memory descriptor type and host addr info */ 633 uint32_t windows; /* number of memory space descriptors */ 634 cistpl_cftable_entry_mem_window_t 635 window[CISTPL_CFTABLE_ENTRY_MAX_MEM_WINDOWS]; 636 .fi 637 .in -2 638 639 .sp 640 .LP 641 The \fBflags\fR field is defined and bit-mapped as follows: 642 .sp 643 .ne 2 644 .na 645 \fBCISTPL_CFTABLE_TPCE_FS_MEM3\fR 646 .ad 647 .sp .6 648 .RS 4n 649 Space descriptors 650 .RE 651 652 .sp 653 .ne 2 654 .na 655 \fBCISTPL_CFTABLE_TPCE_FS_MEM2\fR 656 .ad 657 .sp .6 658 .RS 4n 659 \fBhost_addr\fR=\fBcard_addr\fR 660 .RE 661 662 .sp 663 .ne 2 664 .na 665 \fBCISTPL_CFTABLE_TPCE_FS_MEM1\fR 666 .ad 667 .sp .6 668 .RS 4n 669 Card address=0 any host address 670 .RE 671 672 .sp 673 .ne 2 674 .na 675 \fBCISTPL_CFTABLE_TPCE_FS_MEM_HOST\fR 676 .ad 677 .sp .6 678 .RS 4n 679 If host address is present in MEM3 680 .RE 681 682 .sp 683 .LP 684 The structure members of \fBcistpl_cftable_entry_mem_window_t\fR are: 685 .sp 686 .in +2 687 .nf 688 uint32_t length; /* length of this window */ 689 uint32_t card_addr; /* card address */ 690 uint32_t host_addr; /* host address */ 691 .fi 692 .in -2 693 694 .sp 695 .LP 696 The structure members of \fBcistpl_cftable_entry_misc_t\fR are: 697 .sp 698 .in +2 699 .nf 700 uint32_t flags; /* miscellaneous features flags */ 701 .fi 702 .in -2 703 704 .sp 705 .LP 706 The \fBflags\fR field is defined and bit-mapped as follows: 707 .sp 708 .ne 2 709 .na 710 \fBCISTPL_CFTABLE_TPCE_MI_MTC_MASK\fR 711 .ad 712 .sp .6 713 .RS 4n 714 Max twin cards mask 715 .RE 716 717 .sp 718 .ne 2 719 .na 720 \fBCISTPL_CFTABLE_TPCE_MI_AUDIO\fR 721 .ad 722 .sp .6 723 .RS 4n 724 Audio on BVD2 725 .RE 726 727 .sp 728 .ne 2 729 .na 730 \fBCISTPL_CFTABLE_TPCE_MI_READONLY\fR 731 .ad 732 .sp .6 733 .RS 4n 734 R/O storage 735 .RE 736 737 .sp 738 .ne 2 739 .na 740 \fBCISTPL_CFTABLE_TPCE_MI_PWRDOWN\fR 741 .ad 742 .sp .6 743 .RS 4n 744 Powerdown capable 745 .RE 746 747 .sp 748 .ne 2 749 .na 750 \fBCISTPL_CFTABLE_TPCE_MI_DRQ_MASK\fR 751 .ad 752 .sp .6 753 .RS 4n 754 DMAREQ mask 755 .RE 756 757 .sp 758 .ne 2 759 .na 760 \fBCISTPL_CFTABLE_TPCE_MI_DRQ_SPK\fR 761 .ad 762 .sp .6 763 .RS 4n 764 DMAREQ on SPKR 765 .RE 766 767 .sp 768 .ne 2 769 .na 770 \fBCISTPL_CFTABLE_TPCE_MI_DRQ_IOIS\fR 771 .ad 772 .sp .6 773 .RS 4n 774 DMAREQ on IOIS16 775 .RE 776 777 .sp 778 .ne 2 779 .na 780 \fBCISTPL_CFTABLE_TPCE_MI_DRQ_INP\fR 781 .ad 782 .sp .6 783 .RS 4n 784 DMAREQ on INPACK 785 .RE 786 787 .sp 788 .ne 2 789 .na 790 \fBCISTPL_CFTABLE_TPCE_MI_DMA_8\fR 791 .ad 792 .sp .6 793 .RS 4n 794 DMA width 8 bits 795 .RE 796 797 .sp 798 .ne 2 799 .na 800 \fBCISTPL_CFTABLE_TPCE_MI_DMA_16\fR 801 .ad 802 .sp .6 803 .RS 4n 804 DMA width 16 bits 805 .RE 806 807 .SH RETURN VALUES 808 .sp 809 .ne 2 810 .na 811 \fB\fBCS_SUCCESS\fR\fR 812 .ad 813 .RS 27n 814 Successful operation. 815 .RE 816 817 .sp 818 .ne 2 819 .na 820 \fB\fBCS_BAD_HANDLE\fR\fR 821 .ad 822 .RS 27n 823 Client handle is invalid. 824 .RE 825 826 .sp 827 .ne 2 828 .na 829 \fB\fBCS_UNKNOWN_TUPLE\fR\fR 830 .ad 831 .RS 27n 832 Parser does not know how to parse tuple. 833 .RE 834 835 .sp 836 .ne 2 837 .na 838 \fB\fBCS_NO_CARD\fR\fR 839 .ad 840 .RS 27n 841 No \fBPC \fRCard in socket. 842 .RE 843 844 .sp 845 .ne 2 846 .na 847 \fB\fBCS_NO_CIS\fR\fR 848 .ad 849 .RS 27n 850 No Card Information Structure (CIS) on \fBPC \fRCard. 851 .RE 852 853 .sp 854 .ne 2 855 .na 856 \fB\fBCS_UNSUPPORTED_FUNCTION\fR\fR 857 .ad 858 .RS 27n 859 No \fBPCMCIA \fRhardware installed. 860 .RE 861 862 .SH CONTEXT 863 .sp 864 .LP 865 This function may be called from user or kernel context. 866 .SH SEE ALSO 867 .sp 868 .LP 869 \fBcsx_GetFirstTuple\fR(9F), \fBcsx_GetTupleData\fR(9F), 870 \fBcsx_Parse_CISTPL_CONFIG\fR(9F), \fBcsx_RegisterClient\fR(9F), 871 \fBcsx_ValidateCIS\fR(9F), \fBtuple\fR(9S) 872 .sp 873 .LP 874 \fIPC Card 95 Standard, PCMCIA/JEIDA\fR