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Code reconciliation with other base.
Update tx waitq's code.
Create 2 threads, divide the workflow and deliver
to the hardware from the threads.
Optimise mutex's and code paths.
Split out offline target code.
Enable Fast Path for capable devices.
Merge fixes for Illumos issue 4819, fix mpt_sas command timeout handling.
Tweeks debug flags.
Lint and cstyle fixes.
Fix problem with running against 64bit msgaddr attributes for DMA.
Default is now to run like this.
Fixes for Illumos issue 4682.
Fix hang bug to do with tx_wq.
Re-arrange mptsas_poll() to disable interrupts before issuing the
command.
Improve the tx_waitq code path.
Major rework of mutexes.
During normal operation do not grab m_mutex during interrupt.
Use reply post queues instead.
Distribute command done processing around the threads.
Improved auto-request sense memory usage.
Re-arrange mptsas_intr() to reduce number of spurious interrupts.
Should not need m_in_callback flag. It prevents concurrent
command completion processing.
Added code to support using MSI-X interrupts across multiple
reply queues. Not tested with anything other than 3008 yet.
Use MSI-X interrupts, just one for now.
Pre-allocate array for request sense buffers, similar to command frames.
No more messing about with scsi_alloc_consistent_buf().
Add rolling buffer for *all* debug messages.
Improve mdb module and seperate out into mpt_sas3.
Initial modifications using the code changes present between
the LSI source code for FreeBSD drivers. Specifically the changes
between from mpslsi-source-17.00.00.00 -> mpslsi-source-03.00.00.00.
This mainly involves using a different scatter/gather element in
frame setup.
Changes to enable driver to compile.
Header paths, object lists, etc.
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--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas3/mptsas3_var.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas3/mptsas3_var.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
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14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 - * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
24 + * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
25 25 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
26 + * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
26 27 */
27 28
28 29 /*
29 30 * Copyright (c) 2000 to 2010, LSI Corporation.
30 31 * All rights reserved.
31 32 *
32 33 * Redistribution and use in source and binary forms of all code within
33 34 * this file that is exclusively owned by LSI, with or without
34 35 * modification, is permitted provided that, in addition to the CDDL 1.0
35 36 * License requirements, the following conditions are met:
36 37 *
37 38 * Neither the name of the author nor the names of its contributors may be
38 39 * used to endorse or promote products derived from this software without
39 40 * specific prior written permission.
40 41 *
41 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
42 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
43 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
44 45 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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45 46 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
46 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
47 48 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
48 49 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
49 50 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
50 51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
51 52 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
52 53 * DAMAGE.
53 54 */
54 55
55 -#ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
56 -#define _SYS_SCSI_ADAPTERS_MPTVAR_H
56 +#ifndef _SYS_SCSI_ADAPTERS_MPTSAS3_VAR_H
57 +#define _SYS_SCSI_ADAPTERS_MPTSAS3_VAR_H
57 58
58 59 #include <sys/byteorder.h>
60 +#include <sys/queue.h>
59 61 #include <sys/isa_defs.h>
60 62 #include <sys/sunmdi.h>
61 63 #include <sys/mdi_impldefs.h>
62 -#include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
63 -#include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
64 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
65 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
64 +#include <sys/scsi/adapters/mpt_sas3/mptsas3_hash.h>
65 +#include <sys/scsi/adapters/mpt_sas3/mptsas3_ioctl.h>
66 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_tool.h>
67 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_cnfg.h>
66 68
67 69 #ifdef __cplusplus
68 70 extern "C" {
69 71 #endif
70 72
71 73 /*
72 74 * Compile options
73 75 */
74 76 #ifdef DEBUG
75 77 #define MPTSAS_DEBUG /* turn on debugging code */
76 78 #endif /* DEBUG */
77 79
78 80 #define MPTSAS_INITIAL_SOFT_SPACE 4
79 81
80 82 #define MAX_MPI_PORTS 16
81 83
82 84 /*
83 85 * Note below macro definition and data type definition
84 86 * are used for phy mask handling, it should be changed
85 87 * simultaneously.
86 88 */
87 89 #define MPTSAS_MAX_PHYS 16
88 90 typedef uint16_t mptsas_phymask_t;
89 91
90 92 #define MPTSAS_INVALID_DEVHDL 0xffff
91 93 #define MPTSAS_SATA_GUID "sata-guid"
92 94
93 95 /*
94 96 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
95 97 * targets. There's no need to go overboard here, as the ordinary paths for
96 98 * I/O do not normally require hashed target lookups. These should be good
97 99 * enough and then some for any fabric within the hardware's capabilities.
98 100 */
99 101 #define MPTSAS_SMP_BUCKET_COUNT 23
100 102 #define MPTSAS_TARGET_BUCKET_COUNT 97
101 103
102 104 /*
103 105 * MPT HW defines
104 106 */
105 107 #define MPTSAS_MAX_DISKS_IN_CONFIG 14
106 108 #define MPTSAS_MAX_DISKS_IN_VOL 10
107 109 #define MPTSAS_MAX_HOTSPARES 2
108 110 #define MPTSAS_MAX_RAIDVOLS 2
109 111 #define MPTSAS_MAX_RAIDCONFIGS 5
110 112
111 113 /*
112 114 * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
113 115 * plus two means the prefix 'w' and end of the string '\0'.
114 116 */
115 117 #define MPTSAS_WWN_STRLEN (16 + 2)
116 118 #define MPTSAS_MAX_GUID_LEN 64
117 119
118 120 /*
119 121 * DMA routine flags
120 122 */
121 123 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2
122 124 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4
123 125 #define MPTSAS_DMA_HANDLE_BOUND 0x8
124 126
125 127 /*
126 128 * If the HBA supports DMA or bus-mastering, you may have your own
127 129 * scatter-gather list for physically non-contiguous memory in one
128 130 * I/O operation; if so, there's probably a size for that list.
129 131 * It must be placed in the ddi_dma_lim_t structure, so that the system
130 132 * DMA-support routines can use it to break up the I/O request, so we
131 133 * define it here.
132 134 */
133 135 #if defined(__sparc)
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134 136 #define MPTSAS_MAX_DMA_SEGS 1
135 137 #define MPTSAS_MAX_CMD_SEGS 1
136 138 #else
137 139 #define MPTSAS_MAX_DMA_SEGS 256
138 140 #define MPTSAS_MAX_CMD_SEGS 257
139 141 #endif
140 142 #define MPTSAS_MAX_FRAME_SGES(mpt) \
141 143 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
142 144
143 145 /*
144 - * Caculating how many 64-bit DMA simple elements can be stored in the first
146 + * Calculating how many 64-bit DMA simple elements can be stored in the first
145 147 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
146 148 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in
147 - * size.
149 + * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words
150 + * (16 bytes).
148 151 */
149 152 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
150 153 ((mpt->m_req_frame_size - \
151 - (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12)
154 + sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \
155 + (mpt->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \
156 + sizeof (MPI2_SGE_SIMPLE64)))
152 157
153 158 /*
154 159 * Scatter-gather list structure defined by HBA hardware
155 160 */
156 161 typedef struct NcrTableIndirect { /* Table Indirect entries */
157 162 uint32_t count; /* 24 bit count */
158 163 union {
159 164 uint32_t address32; /* 32 bit address */
160 165 struct {
161 166 uint32_t Low;
162 167 uint32_t High;
163 168 } address64; /* 64 bit address */
164 169 } addr;
165 170 } mptti_t;
166 171
167 172 /*
168 173 * preferred pkt_private length in 64-bit quantities
169 174 */
170 175 #ifdef _LP64
171 176 #define PKT_PRIV_SIZE 2
172 177 #define PKT_PRIV_LEN 16 /* in bytes */
173 178 #else /* _ILP32 */
174 179 #define PKT_PRIV_SIZE 1
175 180 #define PKT_PRIV_LEN 8 /* in bytes */
176 181 #endif
177 182
178 183 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
179 184 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
180 185 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
181 186
182 187 /*
183 188 * get offset of item in structure
184 189 */
185 190 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
186 191
187 192 /*
188 193 * WWID provided by LSI firmware is generated by firmware but the WWID is not
189 194 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
190 195 * address. According LSI's confirmation, the top nibble of RAID WWID is
191 196 * meanless, so the consensus between Solaris and OBP is to replace top nibble
192 197 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
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193 198 * format unit address.
194 199 */
195 200 #define MPTSAS_RAID_WWID(wwid) \
196 201 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
197 202
198 203 typedef struct mptsas_target_addr {
199 204 uint64_t mta_wwn;
200 205 mptsas_phymask_t mta_phymask;
201 206 } mptsas_target_addr_t;
202 207
208 +TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
209 +typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
210 +
203 211 typedef struct mptsas_target {
212 + kmutex_t m_t_mutex;
204 213 mptsas_target_addr_t m_addr;
205 214 refhash_link_t m_link;
206 - uint8_t m_dr_flag;
207 215 uint16_t m_devhdl;
208 216 uint32_t m_deviceinfo;
209 - uint8_t m_phynum;
210 217 uint32_t m_dups;
211 - int32_t m_timeout;
212 - int32_t m_timebase;
218 + uint8_t m_phynum;
219 + mptsas_active_cmdq_t m_active_cmdq;
213 220 int32_t m_t_throttle;
214 221 int32_t m_t_ncmds;
215 222 int32_t m_reset_delay;
216 223 int32_t m_t_nwait;
217 -
218 - uint16_t m_qfull_retry_interval;
219 - uint8_t m_qfull_retries;
224 + uint16_t m_io_flags;
220 225 uint16_t m_enclosure;
221 226 uint16_t m_slot_num;
222 - uint32_t m_tgt_unconfigured;
227 + uint16_t m_qfull_retry_interval;
228 + uint8_t m_qfull_retries;
229 + uint8_t m_tgt_unconfigured;
223 230 uint8_t m_led_status;
224 -
231 + uint8_t m_dr_flag;
225 232 } mptsas_target_t;
226 233
234 +/*
235 + * If you change this structure, be sure that mptsas_smp_target_copy()
236 + * does the right thing.
237 + */
227 238 typedef struct mptsas_smp {
228 239 mptsas_target_addr_t m_addr;
229 240 refhash_link_t m_link;
230 241 uint16_t m_devhdl;
231 242 uint32_t m_deviceinfo;
232 243 uint16_t m_pdevhdl;
233 244 uint32_t m_pdevinfo;
234 245 } mptsas_smp_t;
235 246
236 247 typedef struct mptsas_cache_frames {
237 248 ddi_dma_handle_t m_dma_hdl;
238 249 ddi_acc_handle_t m_acc_hdl;
239 250 caddr_t m_frames_addr;
240 - uint32_t m_phys_addr;
251 + uint64_t m_phys_addr;
241 252 } mptsas_cache_frames_t;
242 253
243 254 typedef struct mptsas_cmd {
244 255 uint_t cmd_flags; /* flags from scsi_init_pkt */
245 256 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
246 257 ddi_dma_cookie_t cmd_cookie;
247 258 uint_t cmd_cookiec;
248 259 uint_t cmd_winindex;
249 260 uint_t cmd_nwin;
250 261 uint_t cmd_cur_cookie;
251 262 off_t cmd_dma_offset;
252 263 size_t cmd_dma_len;
253 264 uint32_t cmd_totaldmacount;
254 -
255 - ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */
256 - ddi_dma_cookie_t cmd_arqcookie;
257 - struct buf *cmd_arq_buf;
258 - ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */
259 - ddi_dma_cookie_t cmd_ext_arqcookie;
260 - struct buf *cmd_ext_arq_buf;
265 + caddr_t cmd_arq_buf;
261 266
262 267 int cmd_pkt_flags;
263 268
264 - /* timer for command in active slot */
265 - int cmd_active_timeout;
269 + /* pending expiration time for command in active slot */
270 + hrtime_t cmd_active_expiration;
271 + TAILQ_ENTRY(mptsas_cmd) cmd_active_link;
266 272
267 273 struct scsi_pkt *cmd_pkt;
268 274 struct scsi_arq_status cmd_scb;
269 275 uchar_t cmd_cdblen; /* length of cdb */
270 276 uchar_t cmd_rqslen; /* len of requested rqsense */
271 277 uchar_t cmd_privlen;
278 + uint16_t cmd_extrqslen; /* len of extended rqsense */
279 + uint16_t cmd_extrqschunks; /* len in map chunks */
280 + uint16_t cmd_extrqsidx; /* Index into map */
272 281 uint_t cmd_scblen;
273 282 uint32_t cmd_dmacount;
274 283 uint64_t cmd_dma_addr;
275 284 uchar_t cmd_age;
276 285 ushort_t cmd_qfull_retries;
277 286 uchar_t cmd_queued; /* true if queued */
278 287 struct mptsas_cmd *cmd_linkp;
279 288 mptti_t *cmd_sg; /* Scatter/Gather structure */
280 289 uchar_t cmd_cdb[SCSI_CDB_SIZE];
281 290 uint64_t cmd_pkt_private[PKT_PRIV_LEN];
282 291 uint32_t cmd_slot;
283 292 uint32_t ioc_cmd_slot;
293 + uint8_t cmd_rpqidx;
284 294
285 295 mptsas_cache_frames_t *cmd_extra_frames;
286 296
287 297 uint32_t cmd_rfm;
288 298 mptsas_target_t *cmd_tgt_addr;
289 299 } mptsas_cmd_t;
290 300
291 301 /*
292 302 * These are the defined cmd_flags for this structure.
293 303 */
294 304 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */
295 305 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */
296 306 #define CFLAG_FINISHED 0x000004 /* command completed */
297 307 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */
298 308 #define CFLAG_COMPLETED 0x000010 /* completion routine called */
299 309 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */
300 310 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */
301 311 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */
302 312 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */
303 313 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */
304 314 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */
305 315 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */
306 316 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */
307 317 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */
308 318 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */
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309 319 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */
310 320 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */
311 321 #define CFLAG_FREE 0x010000 /* packet is on free list */
312 322 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */
313 323 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */
314 324 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
315 325 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
316 326 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
317 327 #define CFLAG_RETRY 0x400000 /* cmd has been retried */
318 328 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
319 -#define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */
320 329 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
321 330 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
322 331 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
323 332 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
324 333 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
325 334 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
326 335 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
327 336
337 +#ifdef MPTSAS_DEBUG
338 +/* Could be used with cmn_err %b */
339 +#define CFLAGS_DEBUG_BITS "\\020\\0CmdDisc\\1Watch\\2Finished\\3ChkSeg" \
340 + "\\4Cmpltd\\5Prepd\\6InTran\\7RestPtrs\\8ARQIP\\9TM\\10CArq" \
341 + "\\11DMAVal\\12DMASnd\\13CIopb\\14CDBExt\\15SCBExt\\16Free" \
342 + "\\17PrivExt\\18DMAPrtl\\19QFull\\20Tout\\21PMMRcv\\22Retry" \
343 + "\\23CIoc\\25PThru\\26XArq\\27CAck\\28TXq\\29FWCmd\\30Config\\31FWDiag"
344 +#endif
345 +
328 346 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
329 347 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
330 348 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
331 349 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
332 350 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
333 351 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0
334 352 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00
335 353 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01
336 354 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10
337 355 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20
338 356 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30
339 357
340 358 #define MPTSAS_HASH_ARRAY_SIZE 16
341 359 /*
342 360 * hash table definition
343 361 */
344 362
345 363 #define MPTSAS_HASH_FIRST 0xffff
346 364 #define MPTSAS_HASH_NEXT 0x0000
347 365
348 366 typedef struct mptsas_dma_alloc_state
349 367 {
350 368 ddi_dma_handle_t handle;
351 369 caddr_t memp;
352 370 size_t size;
353 371 ddi_acc_handle_t accessp;
354 372 ddi_dma_cookie_t cookie;
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355 373 } mptsas_dma_alloc_state_t;
356 374
357 375 /*
358 376 * passthrough request structure
359 377 */
360 378 typedef struct mptsas_pt_request {
361 379 uint8_t *request;
362 380 uint32_t request_size;
363 381 uint32_t data_size;
364 382 uint32_t dataout_size;
365 - uint32_t direction;
383 + uint8_t direction;
384 + uint8_t simple;
385 + uint16_t sgl_offset;
366 386 ddi_dma_cookie_t data_cookie;
367 387 ddi_dma_cookie_t dataout_cookie;
368 388 } mptsas_pt_request_t;
369 389
370 390 /*
371 391 * config page request structure
372 392 */
373 393 typedef struct mptsas_config_request {
374 394 uint32_t page_address;
375 395 uint8_t action;
376 396 uint8_t page_type;
377 397 uint8_t page_number;
378 398 uint8_t page_length;
379 399 uint8_t page_version;
380 400 uint8_t ext_page_type;
381 401 uint16_t ext_page_length;
382 402 } mptsas_config_request_t;
383 403
384 404 typedef struct mptsas_fw_diagnostic_buffer {
385 405 mptsas_dma_alloc_state_t buffer_data;
386 406 uint8_t extended_type;
387 407 uint8_t buffer_type;
388 408 uint8_t force_release;
389 409 uint32_t product_specific[23];
390 410 uint8_t immediate;
391 411 uint8_t enabled;
392 412 uint8_t valid_data;
393 413 uint8_t owned_by_firmware;
394 414 uint32_t unique_id;
395 415 } mptsas_fw_diagnostic_buffer_t;
396 416
397 417 /*
398 418 * FW diag request structure
399 419 */
400 420 typedef struct mptsas_diag_request {
401 421 mptsas_fw_diagnostic_buffer_t *pBuffer;
402 422 uint8_t function;
403 423 } mptsas_diag_request_t;
404 424
405 425 typedef struct mptsas_hash_node {
406 426 void *data;
407 427 struct mptsas_hash_node *next;
408 428 } mptsas_hash_node_t;
409 429
410 430 typedef struct mptsas_hash_table {
411 431 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
412 432 /*
413 433 * last position in traverse
414 434 */
415 435 struct mptsas_hash_node *cur;
416 436 uint16_t line;
417 437
418 438 } mptsas_hash_table_t;
419 439
420 440 /*
421 441 * RAID volume information
422 442 */
423 443 typedef struct mptsas_raidvol {
424 444 ushort_t m_israid;
425 445 uint16_t m_raidhandle;
426 446 uint64_t m_raidwwid;
427 447 uint8_t m_state;
428 448 uint32_t m_statusflags;
429 449 uint32_t m_settings;
430 450 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
431 451 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
432 452 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
433 453 uint64_t m_raidsize;
434 454 int m_raidlevel;
435 455 int m_ndisks;
436 456 mptsas_target_t *m_raidtgt;
437 457 } mptsas_raidvol_t;
438 458
439 459 /*
440 460 * RAID configurations
441 461 */
442 462 typedef struct mptsas_raidconfig {
443 463 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS];
444 464 uint16_t m_physdisk_devhdl[
445 465 MPTSAS_MAX_DISKS_IN_CONFIG];
446 466 uint8_t m_native;
447 467 } m_raidconfig_t;
448 468
449 469 /*
450 470 * Track outstanding commands. The index into the m_slot array is the SMID
451 471 * (system message ID) of the outstanding command. SMID 0 is reserved by the
452 472 * software/firmware protocol and is never used for any command we generate;
453 473 * as such, the assertion m_slot[0] == NULL is universally true. The last
454 474 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for
455 475 * task management commands. No normal SCSI or ATA command will ever occupy
456 476 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any
457 477 * time that a consistent view of the target array is obtainable.
458 478 *
459 479 * As such, m_n_normal is the maximum number of slots available to ordinary
460 480 * commands, and the relationship:
461 481 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2
462 482 * always holds after initialisation.
463 483 */
464 484 typedef struct mptsas_slots {
465 485 size_t m_size; /* size of struct, bytes */
466 486 uint_t m_n_normal; /* see above */
467 487 uint_t m_rotor; /* next slot idx to consider */
468 488 mptsas_cmd_t *m_slot[1];
469 489 } mptsas_slots_t;
470 490
471 491 /*
472 492 * Structure to hold command and packets for event ack
473 493 * and task management commands.
474 494 */
475 495 typedef struct m_event_struct {
476 496 struct mptsas_cmd m_event_cmd;
477 497 struct m_event_struct *m_event_linkp;
478 498 /*
479 499 * event member record the failure event and eventcntx
480 500 * event member would be used in send ack pending process
481 501 */
482 502 uint32_t m_event;
483 503 uint32_t m_eventcntx;
484 504 uint_t in_use;
485 505 struct scsi_pkt m_event_pkt; /* must be last */
486 506 /* ... scsi_pkt_size() */
487 507 } m_event_struct_t;
488 508 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \
489 509 sizeof (struct scsi_pkt) + scsi_pkt_size())
490 510
491 511 #define MAX_IOC_COMMANDS 8
492 512
493 513 /*
494 514 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
495 515 * A new event ack command requests mptsas_cmd and scsi_pkt structures
496 516 * from this pool, and returns it back when done.
497 517 */
498 518
499 519 typedef struct m_replyh_arg {
500 520 void *mpt;
501 521 uint32_t rfm;
502 522 } m_replyh_arg_t;
503 523 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
504 524 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
505 525
506 526 /*
507 527 * Flags for DR handler topology change
508 528 */
509 529 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0
510 530 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1
511 531 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2
512 532 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4
513 533 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8
514 534 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10
515 535
516 536 typedef struct mptsas_topo_change_list {
517 537 void *mpt;
518 538 uint_t event;
519 539 union {
520 540 uint8_t physport;
521 541 mptsas_phymask_t phymask;
522 542 } un;
523 543 uint16_t devhdl;
524 544 void *object;
525 545 uint8_t flags;
526 546 struct mptsas_topo_change_list *next;
527 547 } mptsas_topo_change_list_t;
528 548
529 549
530 550 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
531 551 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
532 552 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
533 553 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
534 554 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
535 555 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
536 556
537 557 /*
538 558 * Status types when calling mptsas_get_target_device_info
539 559 */
540 560 #define DEV_INFO_SUCCESS 0x0
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541 561 #define DEV_INFO_FAIL_PAGE0 0x1
542 562 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2
543 563 #define DEV_INFO_PHYS_DISK 0x3
544 564 #define DEV_INFO_FAIL_ALLOC 0x4
545 565
546 566 /*
547 567 * mpt hotplug event defines
548 568 */
549 569 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
550 570 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
551 -#define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04
571 +#define MPTSAS_DR_EVENT_REMOVE_HANDLE 0x04
552 572
553 573 /*
554 574 * SMP target hotplug events
555 575 */
556 576 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
557 577 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20
558 578 #define MPTSAS_DR_EVENT_MASK 0x3F
559 579
560 580 /*
561 581 * mpt hotplug status definition for m_dr_flag
562 582 */
563 583
564 584 /*
565 585 * MPTSAS_DR_INACTIVE
566 586 *
567 587 * The target is in a normal operating state.
568 588 * No dynamic reconfiguration operation is in progress.
569 589 */
570 590 #define MPTSAS_DR_INACTIVE 0x0
571 591 /*
572 592 * MPTSAS_DR_INTRANSITION
573 593 *
574 594 * The target is in a transition mode since
575 595 * hotplug event happens and offline procedure has not
576 596 * been finished
577 597 */
578 598 #define MPTSAS_DR_INTRANSITION 0x1
579 599
580 600 typedef struct mptsas_tgt_private {
581 601 int t_lun;
582 602 struct mptsas_target *t_private;
583 603 } mptsas_tgt_private_t;
584 604
585 605 /*
586 606 * The following defines are used in mptsas_set_init_mode to track the current
587 607 * state as we progress through reprogramming the HBA from target mode into
588 608 * initiator mode.
589 609 */
590 610
591 611 #define IOUC_READ_PAGE0 0x00000100
592 612 #define IOUC_READ_PAGE1 0x00000200
593 613 #define IOUC_WRITE_PAGE1 0x00000400
594 614 #define IOUC_DONE 0x00000800
595 615 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
596 616 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
597 617
598 618 /*
599 619 * Last allocated slot is used for TM requests. Since only m_max_requests
600 620 * frames are allocated, the last SMID will be m_max_requests - 1.
601 621 */
602 622 #define MPTSAS_SLOTS_SIZE(mpt) \
603 623 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
604 624 mpt->m_max_requests))
605 625 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
606 626
607 627 /*
608 628 * Macro for phy_flags
609 629 */
610 630
611 631 typedef struct smhba_info {
612 632 kmutex_t phy_mutex;
613 633 uint8_t phy_id;
614 634 uint64_t sas_addr;
615 635 char path[8];
616 636 uint16_t owner_devhdl;
617 637 uint16_t attached_devhdl;
618 638 uint8_t attached_phy_identify;
619 639 uint32_t attached_phy_info;
620 640 uint8_t programmed_link_rate;
621 641 uint8_t hw_link_rate;
622 642 uint8_t change_count;
623 643 uint32_t phy_info;
624 644 uint8_t negotiated_link_rate;
625 645 uint8_t port_num;
626 646 kstat_t *phy_stats;
627 647 uint32_t invalid_dword_count;
628 648 uint32_t running_disparity_error_count;
629 649 uint32_t loss_of_dword_sync_count;
630 650 uint32_t phy_reset_problem_count;
631 651 void *mpt;
632 652 } smhba_info_t;
633 653
634 654 typedef struct mptsas_phy_info {
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635 655 uint8_t port_num;
636 656 uint8_t port_flags;
637 657 uint16_t ctrl_devhdl;
638 658 uint32_t phy_device_type;
639 659 uint16_t attached_devhdl;
640 660 mptsas_phymask_t phy_mask;
641 661 smhba_info_t smhba_info;
642 662 } mptsas_phy_info_t;
643 663
644 664
645 -typedef struct mptsas_doneq_thread_arg {
665 +typedef struct mptsas_thread_arg {
646 666 void *mpt;
647 - uint64_t t;
648 -} mptsas_doneq_thread_arg_t;
667 + uint32_t t;
668 +} mptsas_thread_arg_t;
669 +
670 +typedef struct mptsas_done_list {
671 + mptsas_cmd_t *dl_q;
672 + mptsas_cmd_t **dl_tail;
673 + uint32_t dl_len;
674 +} mptsas_done_list_t;
649 675
650 676 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
651 677 typedef struct mptsas_doneq_thread_list {
652 - mptsas_cmd_t *doneq;
653 - mptsas_cmd_t **donetail;
678 + mptsas_done_list_t dlist;
654 679 kthread_t *threadp;
655 680 kcondvar_t cv;
656 681 ushort_t reserv1;
657 682 uint32_t reserv2;
658 683 kmutex_t mutex;
659 684 uint32_t flag;
660 - uint32_t len;
661 - mptsas_doneq_thread_arg_t arg;
685 + mptsas_thread_arg_t arg;
662 686 } mptsas_doneq_thread_list_t;
663 687
688 +typedef struct mptsas_reply_pqueue {
689 + kmutex_t rpq_mutex;
690 + uint8_t rpq_num;
691 + caddr_t rpq_queue; /* Pointer to this queue base */
692 + uint32_t rpq_index; /* Index of next replyq entry */
693 + uint32_t rpq_ncmds; /* Number of outstanding commands */
694 + mptsas_done_list_t rpq_dlist;
695 + uint32_t rpq_intr_count;
696 + uint32_t rpq_intr_unclaimed;
697 + uint32_t rpq_intr_mutexbusy;
698 +} mptsas_reply_pqueue_t;
699 +
700 +
701 +typedef struct mptsas_tx_waitqueue {
702 + kmutex_t txwq_mutex;
703 + kcondvar_t txwq_cv;
704 + kcondvar_t txwq_drain_cv;
705 + kthread_t *txwq_threadp;
706 + mptsas_cmd_t *txwq_cmdq; /* TX cmd queue for active request */
707 + mptsas_cmd_t **txwq_qtail; /* tx_wait queue tail ptr */
708 + uint32_t txwq_len; /* TX queue length */
709 + mptsas_thread_arg_t arg;
710 + uint8_t txwq_active; /* Thread active flag */
711 + uint8_t txwq_draining; /* TX queue draining flag */
712 + uint8_t txwq_wdrain;
713 +} mptsas_tx_waitqueue_t;
714 +
715 +#define NUM_TX_WAITQ 2
716 +
664 717 typedef struct mptsas {
665 718 int m_instance;
666 719
667 720 struct mptsas *m_next;
668 721
669 722 scsi_hba_tran_t *m_tran;
670 723 smp_hba_tran_t *m_smptran;
671 724 kmutex_t m_mutex;
672 725 kmutex_t m_passthru_mutex;
673 726 kcondvar_t m_cv;
674 727 kcondvar_t m_passthru_cv;
675 728 kcondvar_t m_fw_cv;
676 729 kcondvar_t m_config_cv;
677 730 kcondvar_t m_fw_diag_cv;
678 731 dev_info_t *m_dip;
679 732
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680 733 /*
681 734 * soft state flags
682 735 */
683 736 uint_t m_softstate;
684 737
685 738 refhash_t *m_targets;
686 739 refhash_t *m_smp_targets;
687 740
688 741 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
689 742 uint8_t m_num_raid_configs;
743 + uint8_t m_pref_tx_waitq;
690 744
691 745 struct mptsas_slots *m_active; /* outstanding cmds */
692 746
693 747 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
694 748 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
695 -
696 - kmutex_t m_tx_waitq_mutex;
697 - mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */
698 - mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */
699 - int m_tx_draining; /* TX queue draining flag */
700 -
701 - mptsas_cmd_t *m_doneq; /* queue of completed commands */
702 - mptsas_cmd_t **m_donetail; /* queue tail ptr */
749 + mptsas_tx_waitqueue_t m_tx_waitq[NUM_TX_WAITQ];
750 + uint16_t m_txwq_thread_threshold;
751 + uint16_t m_txwq_thread_n;
752 + uint8_t m_txwq_enabled;
753 + uint8_t m_txwq_allow_q_jumping;
754 + mptsas_done_list_t m_dlist; /* List of completed commands */
703 755
704 756 /*
705 757 * variables for helper threads (fan-out interrupts)
706 758 */
707 759 mptsas_doneq_thread_list_t *m_doneq_thread_id;
708 - uint32_t m_doneq_thread_n;
760 + uint16_t m_doneq_thread_n;
761 + uint16_t m_doneq_next_thread;
709 762 uint32_t m_doneq_thread_threshold;
710 763 uint32_t m_doneq_length_threshold;
711 - uint32_t m_doneq_len;
712 - kcondvar_t m_doneq_thread_cv;
713 - kmutex_t m_doneq_mutex;
764 + kcondvar_t m_qthread_cv;
765 + kmutex_t m_qthread_mutex;
714 766
715 - int m_ncmds; /* number of outstanding commands */
767 + uint32_t m_ncmds; /* number of outstanding commands */
768 + uint32_t m_ncstarted; /* ncmds started per interval */
769 + uint32_t m_lncstarted; /* record of last value */
716 770 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
717 771 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
718 772
719 773 ddi_acc_handle_t m_datap; /* operating regs data access handle */
720 774
721 775 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
722 776
723 777 ushort_t m_devid; /* device id of chip. */
724 778 uchar_t m_revid; /* revision of chip. */
725 779 uint16_t m_svid; /* subsystem Vendor ID of chip */
726 780 uint16_t m_ssid; /* subsystem Device ID of chip */
727 781
728 782 uchar_t m_sync_offset; /* default offset for this chip. */
729 783
730 784 timeout_id_t m_quiesce_timeid;
731 785
732 786 ddi_dma_handle_t m_dma_req_frame_hdl;
733 787 ddi_acc_handle_t m_acc_req_frame_hdl;
788 + ddi_dma_handle_t m_dma_req_sense_hdl;
789 + ddi_acc_handle_t m_acc_req_sense_hdl;
734 790 ddi_dma_handle_t m_dma_reply_frame_hdl;
735 791 ddi_acc_handle_t m_acc_reply_frame_hdl;
736 792 ddi_dma_handle_t m_dma_free_queue_hdl;
737 793 ddi_acc_handle_t m_acc_free_queue_hdl;
738 794 ddi_dma_handle_t m_dma_post_queue_hdl;
739 795 ddi_acc_handle_t m_acc_post_queue_hdl;
796 + uint8_t m_dma_flags;
740 797
741 798 /*
742 799 * list of reset notification requests
743 800 */
744 801 struct scsi_reset_notify_entry *m_reset_notify_listf;
745 802
746 803 /*
747 804 * qfull handling
748 805 */
749 806 timeout_id_t m_restart_cmd_timeid;
750 807
751 808 /*
752 809 * scsi reset delay per bus
753 810 */
754 811 uint_t m_scsi_reset_delay;
755 812
756 813 int m_pm_idle_delay;
757 814
758 815 uchar_t m_polled_intr; /* intr was polled. */
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759 816 uchar_t m_suspended; /* true if driver is suspended */
760 817
761 818 struct kmem_cache *m_kmem_cache;
762 819 struct kmem_cache *m_cache_frames;
763 820
764 821 /*
765 822 * hba options.
766 823 */
767 824 uint_t m_options;
768 825
769 - int m_in_callback;
770 -
771 826 int m_power_level; /* current power level */
772 827
773 828 int m_busy; /* power management busy state */
774 829
775 830 off_t m_pmcsr_offset; /* PMCSR offset */
776 831
777 832 ddi_acc_handle_t m_config_handle;
778 833
779 834 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
780 835 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
781 836 ddi_device_acc_attr_t m_dev_acc_attr;
782 837 ddi_device_acc_attr_t m_reg_acc_attr;
783 838
784 839 /*
785 840 * request/reply variables
786 841 */
787 842 caddr_t m_req_frame;
788 843 uint64_t m_req_frame_dma_addr;
844 + caddr_t m_req_sense;
845 + caddr_t m_extreq_sense;
846 + uint64_t m_req_sense_dma_addr;
789 847 caddr_t m_reply_frame;
790 848 uint64_t m_reply_frame_dma_addr;
791 849 caddr_t m_free_queue;
792 850 uint64_t m_free_queue_dma_addr;
793 851 caddr_t m_post_queue;
794 852 uint64_t m_post_queue_dma_addr;
853 + struct map *m_erqsense_map;
854 + mptsas_reply_pqueue_t *m_rep_post_queues;
795 855
796 856 m_replyh_arg_t *m_replyh_args;
797 857
798 858 uint16_t m_max_requests;
799 859 uint16_t m_req_frame_size;
860 + uint16_t m_req_sense_size;
800 861
801 862 /*
802 - * Max frames per request reprted in IOC Facts
863 + * Max frames per request reported in IOC Facts
803 864 */
804 865 uint8_t m_max_chain_depth;
805 866 /*
806 867 * Max frames per request which is used in reality. It's adjusted
807 868 * according DMA SG length attribute, and shall not exceed the
808 869 * m_max_chain_depth.
809 870 */
810 871 uint8_t m_max_request_frames;
872 + uint8_t m_max_msix_vectors;
873 + uint8_t m_reply_frame_size;
874 + uint8_t m_post_reply_qcount;
811 875
812 876 uint16_t m_free_queue_depth;
813 877 uint16_t m_post_queue_depth;
814 878 uint16_t m_max_replies;
815 879 uint32_t m_free_index;
816 - uint32_t m_post_index;
817 - uint8_t m_reply_frame_size;
818 880 uint32_t m_ioc_capabilities;
819 881
820 882 /*
883 + * Housekeeping.
884 + */
885 + uint64_t m_interrupt_count;
886 + uint32_t m_unclaimed_pm_interrupt_count;
887 + uint32_t m_unclaimed_polled_interrupt_count;
888 + uint32_t m_unclaimed_no_interrupt_count;
889 + uint32_t m_unclaimed_nocmd_interrupt_count;
890 +
891 + /*
821 892 * indicates if the firmware was upload by the driver
822 893 * at boot time
823 894 */
824 895 ushort_t m_fwupload;
825 896
826 897 uint16_t m_productid;
827 898
828 899 /*
829 900 * per instance data structures for dma memory resources for
830 901 * MPI handshake protocol. only one handshake cmd can run at a time.
831 902 */
832 903 ddi_dma_handle_t m_hshk_dma_hdl;
833 904 ddi_acc_handle_t m_hshk_acc_hdl;
834 905 caddr_t m_hshk_memp;
835 906 size_t m_hshk_dma_size;
836 907
837 908 /* Firmware version on the card at boot time */
838 909 uint32_t m_fwversion;
839 910
840 911 /* MSI specific fields */
841 912 ddi_intr_handle_t *m_htable; /* For array of interrupts */
842 913 int m_intr_type; /* What type of interrupt */
843 914 int m_intr_cnt; /* # of intrs count returned */
844 915 size_t m_intr_size; /* Size of intr array */
845 916 uint_t m_intr_pri; /* Interrupt priority */
846 917 int m_intr_cap; /* Interrupt capabilities */
847 918 ddi_taskq_t *m_event_taskq;
848 919
849 920 /* SAS specific information */
850 921
851 922 union {
852 923 uint64_t m_base_wwid; /* Base WWID */
853 924 struct {
854 925 #ifdef _BIG_ENDIAN
855 926 uint32_t m_base_wwid_hi;
856 927 uint32_t m_base_wwid_lo;
857 928 #else
858 929 uint32_t m_base_wwid_lo;
859 930 uint32_t m_base_wwid_hi;
860 931 #endif
861 932 } sasaddr;
862 933 } un;
863 934
864 935 uint8_t m_num_phys; /* # of PHYs */
865 936 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS];
866 937 uint8_t m_port_chng; /* initiator port changes */
867 938 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */
868 939 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */
869 940
870 941 /* FMA Capabilities */
871 942 int m_fm_capabilities;
872 943 ddi_taskq_t *m_dr_taskq;
873 944 int m_mpxio_enable;
874 945 uint8_t m_done_traverse_dev;
875 946 uint8_t m_done_traverse_smp;
876 947 int m_diag_action_in_progress;
877 948 uint16_t m_dev_handle;
878 949 uint16_t m_smp_devhdl;
879 950
880 951 /*
881 952 * Event recording
882 953 */
883 954 uint8_t m_event_index;
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884 955 uint32_t m_event_number;
885 956 uint32_t m_event_mask[4];
886 957 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
887 958
888 959 /*
889 960 * FW diag Buffer List
890 961 */
891 962 mptsas_fw_diagnostic_buffer_t
892 963 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
893 964
965 + /* GEN3 support */
966 + uint8_t m_MPI25;
967 +
894 968 /*
895 969 * Event Replay flag (MUR support)
896 970 */
897 971 uint8_t m_event_replay;
898 972
899 973 /*
900 974 * IR Capable flag
901 975 */
902 976 uint8_t m_ir_capable;
903 977
904 978 /*
905 979 * Is HBA processing a diag reset?
906 980 */
907 981 uint8_t m_in_reset;
908 982
909 983 /*
910 984 * per instance cmd data structures for task management cmds
911 985 */
912 986 m_event_struct_t m_event_task_mgmt; /* must be last */
913 987 /* ... scsi_pkt_size */
914 988 } mptsas_t;
915 989 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
916 990 sizeof (struct scsi_pkt) + scsi_pkt_size())
917 991 /*
918 992 * Only one of below two conditions is satisfied, we
919 993 * think the target is associated to the iport and
920 994 * allow call into mptsas_probe_lun().
921 995 * 1. physicalsport == physport
922 996 * 2. (phymask & (1 << physport)) == 0
923 997 * The condition #2 is because LSI uses lowest PHY
924 998 * number as the value of physical port when auto port
925 999 * configuration.
926 1000 */
927 1001 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
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928 1002 ((physicalport == physport) || (dynamicport && (phymask & \
929 1003 (1 << physport))))
930 1004
931 1005 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
932 1006 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
933 1007 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
934 1008 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
935 1009 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
936 1010 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
937 1011 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
938 -_NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type))
939 1012 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
940 -_NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets))
941 1013 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
942 1014
943 1015 /*
944 1016 * These should eventually migrate into the mpt header files
945 1017 * that may become the /kernel/misc/mpt module...
946 1018 */
947 1019 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
948 1020 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
949 1021 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
950 1022 mptsas_put_msg_Function(hdl, mp, Function); \
951 1023 mptsas_put_msg_Lun(hdl, mp, Lun)
952 1024
953 1025 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
954 1026 ddi_put16(hdl, &(mp)->DevHandle, (val))
955 1027 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
956 1028 ddi_put8(hdl, &(mp)->ChainOffset, (val))
957 1029 #define mptsas_put_msg_Function(hdl, mp, val) \
958 1030 ddi_put8(hdl, &(mp)->Function, (val))
959 1031 #define mptsas_put_msg_Lun(hdl, mp, val) \
960 1032 ddi_put8(hdl, &(mp)->LUN[1], (val))
961 1033
962 1034 #define mptsas_get_msg_Function(hdl, mp) \
963 1035 ddi_get8(hdl, &(mp)->Function)
964 1036
965 1037 #define mptsas_get_msg_MsgFlags(hdl, mp) \
966 1038 ddi_get8(hdl, &(mp)->MsgFlags)
967 1039
968 1040 #define MPTSAS_ENABLE_DRWE(hdl) \
969 1041 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
970 1042 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
971 1043 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
972 1044 MPI2_WRSEQ_1ST_KEY_VALUE); \
973 1045 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
974 1046 MPI2_WRSEQ_2ND_KEY_VALUE); \
975 1047 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
976 1048 MPI2_WRSEQ_3RD_KEY_VALUE); \
977 1049 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
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978 1050 MPI2_WRSEQ_4TH_KEY_VALUE); \
979 1051 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
980 1052 MPI2_WRSEQ_5TH_KEY_VALUE); \
981 1053 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
982 1054 MPI2_WRSEQ_6TH_KEY_VALUE);
983 1055
984 1056 /*
985 1057 * m_options flags
986 1058 */
987 1059 #define MPTSAS_OPT_PM 0x01 /* Power Management */
1060 +#define MPTSAS_OPT_MSI 0x02 /* PCI MSI Interrupts */
1061 +#define MPTSAS_OPT_MSI_X 0x04 /* PCI MSI-X Interrupts */
988 1062
989 1063 /*
990 1064 * m_softstate flags
991 1065 */
992 1066 #define MPTSAS_SS_DRAINING 0x02
993 1067 #define MPTSAS_SS_QUIESCED 0x04
994 1068 #define MPTSAS_SS_MSG_UNIT_RESET 0x08
995 1069 #define MPTSAS_DID_MSG_UNIT_RESET 0x10
996 1070
997 1071 /*
1072 + * m_dma_flags (allocated).
1073 + */
1074 +#define MPTSAS_REQ_FRAME 0x01
1075 +#define MPTSAS_REQ_SENSE 0x02
1076 +#define MPTSAS_REPLY_FRAME 0x04
1077 +#define MPTSAS_FREE_QUEUE 0x08
1078 +#define MPTSAS_POST_QUEUE 0x10
1079 +
1080 +/*
998 1081 * regspec defines.
999 1082 */
1000 1083 #define CONFIG_SPACE 0 /* regset[0] - configuration space */
1001 1084 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */
1002 1085 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */
1003 1086 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */
1004 1087
1005 1088 /*
1006 1089 * Handy constants
1007 1090 */
1008 1091 #define FALSE 0
1009 1092 #define TRUE 1
1093 +#define BLOCKED 2
1010 1094 #define UNDEFINED -1
1011 1095 #define FAILED -2
1012 1096
1013 1097 /*
1014 1098 * power management.
1015 1099 */
1016 1100 #define MPTSAS_POWER_ON(mpt) { \
1017 1101 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1018 1102 PCI_PMCSR_D0); \
1019 1103 delay(drv_usectohz(10000)); \
1020 1104 (void) pci_restore_config_regs(mpt->m_dip); \
1021 1105 mptsas_setup_cmd_reg(mpt); \
1022 1106 }
1023 1107
1024 1108 #define MPTSAS_POWER_OFF(mpt) { \
1025 1109 (void) pci_save_config_regs(mpt->m_dip); \
1026 1110 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1027 1111 PCI_PMCSR_D3HOT); \
1028 1112 mpt->m_power_level = PM_LEVEL_D3; \
1029 1113 }
1030 1114
1031 1115 /*
1032 1116 * inq_dtype:
1033 1117 * Bits 5 through 7 are the Peripheral Device Qualifier
1034 1118 * 001b: device not connected to the LUN
1035 1119 * Bits 0 through 4 are the Peripheral Device Type
1036 1120 * 1fh: Unknown or no device type
1037 1121 *
1038 1122 * Although the inquiry may return success, the following value
1039 1123 * means no valid LUN connected.
1040 1124 */
1041 1125 #define MPTSAS_VALID_LUN(sd_inq) \
1042 1126 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1043 1127 ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1044 1128
1045 1129 /*
1046 1130 * Default is to have 10 retries on receiving QFULL status and
1047 1131 * each retry to be after 100 ms.
1048 1132 */
1049 1133 #define QFULL_RETRIES 10
1050 1134 #define QFULL_RETRY_INTERVAL 100
1051 1135
1052 1136 /*
1053 1137 * Handy macros
1054 1138 */
1055 1139 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1056 1140 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1057 1141
1058 1142 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1059 1143 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1060 1144
1061 1145 /*
1062 1146 * poll time for mptsas_pollret() and mptsas_wait_intr()
1063 1147 */
1064 1148 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */
1065 1149
1066 1150 /*
1067 1151 * default time for mptsas_do_passthru
1068 1152 */
1069 1153 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */
1070 1154
1071 1155 /*
1072 1156 * macro to return the effective address of a given per-target field
1073 1157 */
1074 1158 #define EFF_ADDR(start, offset) ((start) + (offset))
1075 1159
1076 1160 #define SDEV2ADDR(devp) (&((devp)->sd_address))
1077 1161 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran)
1078 1162 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran)
1079 1163 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
1080 1164 #define DIP2TRAN(dip) (ddi_get_driver_private(dip))
1081 1165
1082 1166
1083 1167 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private)
1084 1168 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1085 1169 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd)))
1086 1170 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt)))
1087 1171
1088 1172 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap)))
1089 1173
1090 1174 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000)
1091 1175 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */
1092 1176 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */
1093 1177 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */
1094 1178
1095 1179 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \
1096 1180 &(mpt)->m_reg->HostInterruptStatus))
1097 1181
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1098 1182 #define MPTSAS_SET_SIGP(P) \
1099 1183 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1100 1184
1101 1185 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1102 1186 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1103 1187
1104 1188 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1105 1189 (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1106 1190
1107 1191
1108 -#define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \
1109 - ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\
1110 - req_desc_lo);\
1111 - ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\
1112 - req_desc_hi);
1192 +#define MPTSAS_START_CMD(mpt, req_desc) \
1193 + ddi_put64(mpt->m_datap, \
1194 + (uint64_t *)(void *)&mpt->m_reg->RequestDescriptorPostLow, \
1195 + req_desc); \
1196 + atomic_inc_32(&mpt->m_ncstarted)
1197 +
1113 1198
1114 1199 #define INTPENDING(mpt) \
1115 1200 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1116 1201
1117 1202 /*
1118 1203 * Mask all interrupts to disable
1119 1204 */
1120 1205 #define MPTSAS_DISABLE_INTR(mpt) \
1121 1206 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1122 1207 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1123 1208
1124 1209 /*
1125 1210 * Mask Doorbell and Reset interrupts to enable reply desc int.
1126 1211 */
1127 1212 #define MPTSAS_ENABLE_INTR(mpt) \
1128 1213 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1129 1214 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1130 1215
1131 -#define MPTSAS_GET_NEXT_REPLY(mpt, index) \
1132 - &((uint64_t *)(void *)mpt->m_post_queue)[index]
1216 +#define MPTSAS_GET_NEXT_REPLY(rpqp, index) \
1217 + &((uint64_t *)(void *)rpqp->rpq_queue)[index]
1133 1218
1134 1219 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1135 1220 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1136 1221
1137 1222 #define ClrSetBits32(hdl, reg, clr, set) \
1138 1223 ddi_put32(hdl, (reg), \
1139 1224 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1140 1225
1141 1226 #define ClrSetBits(reg, clr, set) \
1142 1227 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1143 1228 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1144 1229
1145 1230 #define MPTSAS_WAITQ_RM(mpt, cmdp) \
1146 1231 if ((cmdp = mpt->m_waitq) != NULL) { \
1147 1232 /* If the queue is now empty fix the tail pointer */ \
1148 1233 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1149 1234 mpt->m_waitqtail = &mpt->m_waitq; \
1150 1235 cmdp->cmd_linkp = NULL; \
1151 1236 cmdp->cmd_queued = FALSE; \
1152 1237 }
1153 1238
1154 1239 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \
1155 1240 if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1156 1241 /* If the queue is now empty fix the tail pointer */ \
1157 1242 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
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1158 1243 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1159 1244 cmdp->cmd_linkp = NULL; \
1160 1245 cmdp->cmd_queued = FALSE; \
1161 1246 }
1162 1247
1163 1248 /*
1164 1249 * defaults for the global properties
1165 1250 */
1166 1251 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
1167 1252 #define DEFAULT_TAG_AGE_LIMIT 2
1168 -#define DEFAULT_WD_TICK 10
1253 +#define DEFAULT_WD_TICK 1
1169 1254
1170 1255 /*
1171 1256 * invalid hostid.
1172 1257 */
1173 1258 #define MPTSAS_INVALID_HOSTID -1
1174 1259
1175 1260 /*
1176 1261 * Get/Set hostid from SCSI port configuration page
1177 1262 */
1178 1263 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1179 1264 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1180 1265
1181 1266 /*
1182 1267 * Config space.
1183 1268 */
1184 1269 #define MPTSAS_LATENCY_TIMER 0x40
1185 1270
1186 1271 /*
1187 1272 * Offset to firmware version
1188 1273 */
1189 1274 #define MPTSAS_FW_VERSION_OFFSET 9
1190 1275
1191 1276 /*
1192 1277 * Offset and masks to get at the ProductId field
1193 1278 */
1194 1279 #define MPTSAS_FW_PRODUCTID_OFFSET 8
1195 1280 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000
1196 1281 #define MPTSAS_FW_PRODUCTID_SHIFT 16
1197 1282
1198 1283 /*
1199 1284 * Subsystem ID for HBAs.
1200 1285 */
1201 1286 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1202 1287 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1203 1288
1204 1289 /*
1205 1290 * reset delay tick
1206 1291 */
1207 1292 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1208 1293
1209 1294 /*
1210 1295 * Ioc reset return values
1211 1296 */
1212 1297 #define MPTSAS_RESET_FAIL -1
1213 1298 #define MPTSAS_NO_RESET 0
1214 1299 #define MPTSAS_SUCCESS_HARDRESET 1
1215 1300 #define MPTSAS_SUCCESS_MUR 2
1216 1301
1217 1302 /*
1218 1303 * throttle support.
1219 1304 */
1220 1305 #define MAX_THROTTLE 32
1221 1306 #define HOLD_THROTTLE 0
1222 1307 #define DRAIN_THROTTLE -1
1223 1308 #define QFULL_THROTTLE -2
1224 1309
1225 1310 /*
1226 1311 * Passthrough/config request flags
1227 1312 */
1228 1313 #define MPTSAS_DATA_ALLOCATED 0x0001
1229 1314 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1230 1315 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1231 1316 #define MPTSAS_ADDRESS_REPLY 0x0008
1232 1317 #define MPTSAS_CMD_TIMEOUT 0x0010
1233 1318
1234 1319 /*
1235 1320 * response code tlr flag
1236 1321 */
1237 1322 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1238 1323
1239 1324 /*
1240 1325 * System Events
1241 1326 */
1242 1327 #ifndef DDI_VENDOR_LSI
1243 1328 #define DDI_VENDOR_LSI "LSI"
1244 1329 #endif /* DDI_VENDOR_LSI */
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1245 1330
1246 1331 /*
1247 1332 * Shared functions
1248 1333 */
1249 1334 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1250 1335 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1251 1336 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1252 1337 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1253 1338 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1254 1339 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1255 -int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1256 - uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1257 - uint8_t pageversion, uint8_t pagelength, uint32_t
1258 - SGEflagslength, uint32_t SGEaddress32);
1259 -int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1260 - uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1261 - uint8_t pageversion, uint16_t extpagelength,
1262 - uint32_t SGEflagslength, uint32_t SGEaddress32);
1263 1340 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1264 1341 uint8_t type, int mode);
1265 1342 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1266 1343 uint8_t type, int mode);
1267 1344 int mptsas_download_firmware();
1268 1345 int mptsas_can_download_firmware();
1269 1346 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1270 1347 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1271 1348 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1272 1349 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1273 1350 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1274 1351 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1275 1352 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1276 1353 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1277 1354 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1278 1355 uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1279 1356 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1280 1357
1281 1358 /*
1282 1359 * impl functions
1283 1360 */
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1284 1361 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1285 1362 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1286 1363 int mptsas_ioc_reset(mptsas_t *mpt, int);
1287 1364 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1288 1365 ddi_acc_handle_t accessp);
1289 1366 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1290 1367 ddi_acc_handle_t accessp);
1291 1368 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1292 1369 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1293 1370 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1294 - uint32_t SGEaddress32);
1371 + uint64_t SGEaddress);
1295 1372 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1296 1373 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1297 1374 uint8_t pageversion, uint16_t extpagelength,
1298 - uint32_t SGEflagslength, uint32_t SGEaddress32);
1375 + uint32_t SGEflagslength, uint64_t SGEaddress);
1299 1376
1300 1377 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1301 1378 struct scsi_pkt **pkt);
1302 1379 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1303 1380 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1304 1381 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
1305 1382 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1306 1383 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1307 1384 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1308 1385
1309 1386 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1310 1387 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1311 1388 int mode);
1312 1389 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1313 1390 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1314 -void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1315 1391 int mptsas_restart_ioc(mptsas_t *mpt);
1316 1392 void mptsas_update_driver_data(struct mptsas *mpt);
1317 1393 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1318 1394
1319 1395 /*
1320 1396 * init functions
1321 1397 */
1322 1398 int mptsas_ioc_get_facts(mptsas_t *mpt);
1323 1399 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1324 1400 int mptsas_ioc_enable_port(mptsas_t *mpt);
1325 1401 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1326 1402 int mptsas_ioc_init(mptsas_t *mpt);
1327 1403
1328 1404 /*
1329 1405 * configuration pages operation
1330 1406 */
1331 1407 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1332 1408 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1333 1409 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1334 - uint16_t *slot_num, uint16_t *enclosure);
1410 + uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags);
1335 1411 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1336 1412 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1337 1413 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1338 1414 mptsas_smp_t *info);
1339 1415 int mptsas_set_ioc_params(mptsas_t *mpt);
1340 1416 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1341 1417 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1342 1418 uint64_t *sas_wwn, uint8_t *portwidth);
1343 1419 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version);
1344 1420 int
1345 1421 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1346 1422 smhba_info_t *info);
1347 1423 int
1348 1424 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1349 1425 smhba_info_t *info);
1350 1426 int
1351 1427 mptsas_get_manufacture_page0(mptsas_t *mpt);
1352 1428 void
1353 1429 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1354 1430 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1355 1431 int mptsas_smhba_phy_init(mptsas_t *mpt);
1356 1432 /*
1357 1433 * RAID functions
1358 1434 */
1359 1435 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1360 1436 int mptsas_get_raid_info(mptsas_t *mpt);
1361 1437 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1362 1438 uint8_t physdisknum);
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1363 1439 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1364 1440 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1365 1441
1366 1442 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1367 1443 /*
1368 1444 * debugging.
1369 1445 */
1370 1446 #if defined(MPTSAS_DEBUG)
1371 1447
1372 1448 void mptsas_printf(char *fmt, ...);
1449 +void mptsas_debug_log(char *fmt, ...);
1373 1450
1374 1451 #define MPTSAS_DBGPR(m, args) \
1375 1452 if (mptsas_debug_flags & (m)) \
1376 - mptsas_printf args
1453 + mptsas_printf args; \
1454 + if (~mptsas_dbglog_imask & (m)) \
1455 + mptsas_debug_log args
1377 1456 #else /* ! defined(MPTSAS_DEBUG) */
1378 1457 #define MPTSAS_DBGPR(m, args)
1379 1458 #endif /* defined(MPTSAS_DEBUG) */
1380 1459
1381 1460 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
1382 1461 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */
1383 1462 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
1384 1463 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
1385 1464
1386 1465 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
1387 1466 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
1388 -#define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
1467 +#define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupt setup */
1389 1468 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
1390 1469
1391 1470 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
1392 1471 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
1393 1472 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
1394 1473 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
1395 1474
1396 1475 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
1397 1476 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
1398 1477 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
1399 -#define NDBG15(args) MPTSAS_DBGPR(0x8000, args)
1478 +#define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */
1400 1479
1401 -#define NDBG16(args) MPTSAS_DBGPR(0x010000, args)
1480 +#define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */
1402 1481 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
1403 -#define NDBG18(args) MPTSAS_DBGPR(0x040000, args)
1482 +#define NDBG18(args) MPTSAS_DBGPR(0x040000, args) /* Interrupts */
1404 1483 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
1405 1484
1406 1485 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
1407 1486 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
1408 1487 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
1409 1488 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */
1410 1489
1411 1490 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */
1412 1491 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */
1413 1492 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args)
1414 1493 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args)
1415 1494
1416 1495 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */
1417 1496 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */
1418 1497 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */
1419 1498 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */
1420 1499
1421 1500 /*
1422 1501 * auto request sense
1423 1502 */
1424 1503 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1425 1504 (pkt)->pkt_flags = (flag), \
1426 1505 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1427 1506 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1428 1507 (pkt)->pkt_address.a_lun
1429 1508
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1430 1509 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1431 1510 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1432 1511 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1433 1512 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1434 1513
1435 1514
1436 1515 #ifdef __cplusplus
1437 1516 }
1438 1517 #endif
1439 1518
1440 -#endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */
1519 +#endif /* _SYS_SCSI_ADAPTERS_MPTSAS3_VAR_H */
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