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Code reconciliation with other base.
Update tx waitq's code.
Create 2 threads, divide the workflow and deliver
to the hardware from the threads.
Optimise mutex's and code paths.
Split out offline target code.
Enable Fast Path for capable devices.
Merge fixes for Illumos issue 4819, fix mpt_sas command timeout handling.
Tweeks debug flags.
Lint and cstyle fixes.
Fix problem with running against 64bit msgaddr attributes for DMA.
Default is now to run like this.
Fixes for Illumos issue 4682.
Fix hang bug to do with tx_wq.
Re-arrange mptsas_poll() to disable interrupts before issuing the
command.
Improve the tx_waitq code path.
Major rework of mutexes.
During normal operation do not grab m_mutex during interrupt.
Use reply post queues instead.
Distribute command done processing around the threads.
Improved auto-request sense memory usage.
Re-arrange mptsas_intr() to reduce number of spurious interrupts.
Should not need m_in_callback flag. It prevents concurrent
command completion processing.
Added code to support using MSI-X interrupts across multiple
reply queues. Not tested with anything other than 3008 yet.
Use MSI-X interrupts, just one for now.
Pre-allocate array for request sense buffers, similar to command frames.
No more messing about with scsi_alloc_consistent_buf().
Add rolling buffer for *all* debug messages.
Improve mdb module and seperate out into mpt_sas3.
Initial modifications using the code changes present between
the LSI source code for FreeBSD drivers. Specifically the changes
between from mpslsi-source-17.00.00.00 -> mpslsi-source-03.00.00.00.
This mainly involves using a different scatter/gather element in
frame setup.
Changes to enable driver to compile.
Header paths, object lists, etc.
*** 19,30 ****
* CDDL HEADER END
*/
/*
* Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
! * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
* Copyright (c) 2013, Joyent, Inc. All rights reserved.
*/
/*
* Copyright (c) 2000 to 2010, LSI Corporation.
* All rights reserved.
--- 19,31 ----
* CDDL HEADER END
*/
/*
* Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
! * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
* Copyright (c) 2013, Joyent, Inc. All rights reserved.
+ * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
*/
/*
* Copyright (c) 2000 to 2010, LSI Corporation.
* All rights reserved.
*** 50,70 ****
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*/
! #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
! #define _SYS_SCSI_ADAPTERS_MPTVAR_H
#include <sys/byteorder.h>
#include <sys/isa_defs.h>
#include <sys/sunmdi.h>
#include <sys/mdi_impldefs.h>
! #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
! #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
! #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
! #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
#ifdef __cplusplus
extern "C" {
#endif
--- 51,72 ----
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*/
! #ifndef _SYS_SCSI_ADAPTERS_MPTSAS3_VAR_H
! #define _SYS_SCSI_ADAPTERS_MPTSAS3_VAR_H
#include <sys/byteorder.h>
+ #include <sys/queue.h>
#include <sys/isa_defs.h>
#include <sys/sunmdi.h>
#include <sys/mdi_impldefs.h>
! #include <sys/scsi/adapters/mpt_sas3/mptsas3_hash.h>
! #include <sys/scsi/adapters/mpt_sas3/mptsas3_ioctl.h>
! #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_tool.h>
! #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_cnfg.h>
#ifdef __cplusplus
extern "C" {
#endif
*** 139,156 ****
#endif
#define MPTSAS_MAX_FRAME_SGES(mpt) \
(((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
/*
! * Caculating how many 64-bit DMA simple elements can be stored in the first
* frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
* element storage. And 64-bit dma element is 3 double-words (12 bytes) in
! * size.
*/
#define MPTSAS_MAX_FRAME_SGES64(mpt) \
((mpt->m_req_frame_size - \
! (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12)
/*
* Scatter-gather list structure defined by HBA hardware
*/
typedef struct NcrTableIndirect { /* Table Indirect entries */
--- 141,161 ----
#endif
#define MPTSAS_MAX_FRAME_SGES(mpt) \
(((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
/*
! * Calculating how many 64-bit DMA simple elements can be stored in the first
* frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
* element storage. And 64-bit dma element is 3 double-words (12 bytes) in
! * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words
! * (16 bytes).
*/
#define MPTSAS_MAX_FRAME_SGES64(mpt) \
((mpt->m_req_frame_size - \
! sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \
! (mpt->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \
! sizeof (MPI2_SGE_SIMPLE64)))
/*
* Scatter-gather list structure defined by HBA hardware
*/
typedef struct NcrTableIndirect { /* Table Indirect entries */
*** 198,231 ****
typedef struct mptsas_target_addr {
uint64_t mta_wwn;
mptsas_phymask_t mta_phymask;
} mptsas_target_addr_t;
typedef struct mptsas_target {
mptsas_target_addr_t m_addr;
refhash_link_t m_link;
- uint8_t m_dr_flag;
uint16_t m_devhdl;
uint32_t m_deviceinfo;
- uint8_t m_phynum;
uint32_t m_dups;
! int32_t m_timeout;
! int32_t m_timebase;
int32_t m_t_throttle;
int32_t m_t_ncmds;
int32_t m_reset_delay;
int32_t m_t_nwait;
!
! uint16_t m_qfull_retry_interval;
! uint8_t m_qfull_retries;
uint16_t m_enclosure;
uint16_t m_slot_num;
! uint32_t m_tgt_unconfigured;
uint8_t m_led_status;
!
} mptsas_target_t;
typedef struct mptsas_smp {
mptsas_target_addr_t m_addr;
refhash_link_t m_link;
uint16_t m_devhdl;
uint32_t m_deviceinfo;
--- 203,242 ----
typedef struct mptsas_target_addr {
uint64_t mta_wwn;
mptsas_phymask_t mta_phymask;
} mptsas_target_addr_t;
+ TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
+ typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
+
typedef struct mptsas_target {
+ kmutex_t m_t_mutex;
mptsas_target_addr_t m_addr;
refhash_link_t m_link;
uint16_t m_devhdl;
uint32_t m_deviceinfo;
uint32_t m_dups;
! uint8_t m_phynum;
! mptsas_active_cmdq_t m_active_cmdq;
int32_t m_t_throttle;
int32_t m_t_ncmds;
int32_t m_reset_delay;
int32_t m_t_nwait;
! uint16_t m_io_flags;
uint16_t m_enclosure;
uint16_t m_slot_num;
! uint16_t m_qfull_retry_interval;
! uint8_t m_qfull_retries;
! uint8_t m_tgt_unconfigured;
uint8_t m_led_status;
! uint8_t m_dr_flag;
} mptsas_target_t;
+ /*
+ * If you change this structure, be sure that mptsas_smp_target_copy()
+ * does the right thing.
+ */
typedef struct mptsas_smp {
mptsas_target_addr_t m_addr;
refhash_link_t m_link;
uint16_t m_devhdl;
uint32_t m_deviceinfo;
*** 235,245 ****
typedef struct mptsas_cache_frames {
ddi_dma_handle_t m_dma_hdl;
ddi_acc_handle_t m_acc_hdl;
caddr_t m_frames_addr;
! uint32_t m_phys_addr;
} mptsas_cache_frames_t;
typedef struct mptsas_cmd {
uint_t cmd_flags; /* flags from scsi_init_pkt */
ddi_dma_handle_t cmd_dmahandle; /* dma handle */
--- 246,256 ----
typedef struct mptsas_cache_frames {
ddi_dma_handle_t m_dma_hdl;
ddi_acc_handle_t m_acc_hdl;
caddr_t m_frames_addr;
! uint64_t m_phys_addr;
} mptsas_cache_frames_t;
typedef struct mptsas_cmd {
uint_t cmd_flags; /* flags from scsi_init_pkt */
ddi_dma_handle_t cmd_dmahandle; /* dma handle */
*** 249,276 ****
uint_t cmd_nwin;
uint_t cmd_cur_cookie;
off_t cmd_dma_offset;
size_t cmd_dma_len;
uint32_t cmd_totaldmacount;
!
! ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */
! ddi_dma_cookie_t cmd_arqcookie;
! struct buf *cmd_arq_buf;
! ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */
! ddi_dma_cookie_t cmd_ext_arqcookie;
! struct buf *cmd_ext_arq_buf;
int cmd_pkt_flags;
! /* timer for command in active slot */
! int cmd_active_timeout;
struct scsi_pkt *cmd_pkt;
struct scsi_arq_status cmd_scb;
uchar_t cmd_cdblen; /* length of cdb */
uchar_t cmd_rqslen; /* len of requested rqsense */
uchar_t cmd_privlen;
uint_t cmd_scblen;
uint32_t cmd_dmacount;
uint64_t cmd_dma_addr;
uchar_t cmd_age;
ushort_t cmd_qfull_retries;
--- 260,285 ----
uint_t cmd_nwin;
uint_t cmd_cur_cookie;
off_t cmd_dma_offset;
size_t cmd_dma_len;
uint32_t cmd_totaldmacount;
! caddr_t cmd_arq_buf;
int cmd_pkt_flags;
! /* pending expiration time for command in active slot */
! hrtime_t cmd_active_expiration;
! TAILQ_ENTRY(mptsas_cmd) cmd_active_link;
struct scsi_pkt *cmd_pkt;
struct scsi_arq_status cmd_scb;
uchar_t cmd_cdblen; /* length of cdb */
uchar_t cmd_rqslen; /* len of requested rqsense */
uchar_t cmd_privlen;
+ uint16_t cmd_extrqslen; /* len of extended rqsense */
+ uint16_t cmd_extrqschunks; /* len in map chunks */
+ uint16_t cmd_extrqsidx; /* Index into map */
uint_t cmd_scblen;
uint32_t cmd_dmacount;
uint64_t cmd_dma_addr;
uchar_t cmd_age;
ushort_t cmd_qfull_retries;
*** 279,288 ****
--- 288,298 ----
mptti_t *cmd_sg; /* Scatter/Gather structure */
uchar_t cmd_cdb[SCSI_CDB_SIZE];
uint64_t cmd_pkt_private[PKT_PRIV_LEN];
uint32_t cmd_slot;
uint32_t ioc_cmd_slot;
+ uint8_t cmd_rpqidx;
mptsas_cache_frames_t *cmd_extra_frames;
uint32_t cmd_rfm;
mptsas_target_t *cmd_tgt_addr;
*** 314,332 ****
#define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
#define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
#define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
#define CFLAG_RETRY 0x400000 /* cmd has been retried */
#define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
- #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */
#define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
#define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
#define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
#define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
#define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
#define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
#define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
--- 324,350 ----
#define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
#define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
#define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
#define CFLAG_RETRY 0x400000 /* cmd has been retried */
#define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
#define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
#define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
#define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
#define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
#define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
#define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
#define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
+ #ifdef MPTSAS_DEBUG
+ /* Could be used with cmn_err %b */
+ #define CFLAGS_DEBUG_BITS "\\020\\0CmdDisc\\1Watch\\2Finished\\3ChkSeg" \
+ "\\4Cmpltd\\5Prepd\\6InTran\\7RestPtrs\\8ARQIP\\9TM\\10CArq" \
+ "\\11DMAVal\\12DMASnd\\13CIopb\\14CDBExt\\15SCBExt\\16Free" \
+ "\\17PrivExt\\18DMAPrtl\\19QFull\\20Tout\\21PMMRcv\\22Retry" \
+ "\\23CIoc\\25PThru\\26XArq\\27CAck\\28TXq\\29FWCmd\\30Config\\31FWDiag"
+ #endif
+
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
#define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
*** 360,370 ****
typedef struct mptsas_pt_request {
uint8_t *request;
uint32_t request_size;
uint32_t data_size;
uint32_t dataout_size;
! uint32_t direction;
ddi_dma_cookie_t data_cookie;
ddi_dma_cookie_t dataout_cookie;
} mptsas_pt_request_t;
/*
--- 378,390 ----
typedef struct mptsas_pt_request {
uint8_t *request;
uint32_t request_size;
uint32_t data_size;
uint32_t dataout_size;
! uint8_t direction;
! uint8_t simple;
! uint16_t sgl_offset;
ddi_dma_cookie_t data_cookie;
ddi_dma_cookie_t dataout_cookie;
} mptsas_pt_request_t;
/*
*** 546,556 ****
/*
* mpt hotplug event defines
*/
#define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
#define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
! #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04
/*
* SMP target hotplug events
*/
#define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
--- 566,576 ----
/*
* mpt hotplug event defines
*/
#define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
#define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
! #define MPTSAS_DR_EVENT_REMOVE_HANDLE 0x04
/*
* SMP target hotplug events
*/
#define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
*** 640,668 ****
mptsas_phymask_t phy_mask;
smhba_info_t smhba_info;
} mptsas_phy_info_t;
! typedef struct mptsas_doneq_thread_arg {
void *mpt;
! uint64_t t;
! } mptsas_doneq_thread_arg_t;
#define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
typedef struct mptsas_doneq_thread_list {
! mptsas_cmd_t *doneq;
! mptsas_cmd_t **donetail;
kthread_t *threadp;
kcondvar_t cv;
ushort_t reserv1;
uint32_t reserv2;
kmutex_t mutex;
uint32_t flag;
! uint32_t len;
! mptsas_doneq_thread_arg_t arg;
} mptsas_doneq_thread_list_t;
typedef struct mptsas {
int m_instance;
struct mptsas *m_next;
--- 660,721 ----
mptsas_phymask_t phy_mask;
smhba_info_t smhba_info;
} mptsas_phy_info_t;
! typedef struct mptsas_thread_arg {
void *mpt;
! uint32_t t;
! } mptsas_thread_arg_t;
!
! typedef struct mptsas_done_list {
! mptsas_cmd_t *dl_q;
! mptsas_cmd_t **dl_tail;
! uint32_t dl_len;
! } mptsas_done_list_t;
#define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
typedef struct mptsas_doneq_thread_list {
! mptsas_done_list_t dlist;
kthread_t *threadp;
kcondvar_t cv;
ushort_t reserv1;
uint32_t reserv2;
kmutex_t mutex;
uint32_t flag;
! mptsas_thread_arg_t arg;
} mptsas_doneq_thread_list_t;
+ typedef struct mptsas_reply_pqueue {
+ kmutex_t rpq_mutex;
+ uint8_t rpq_num;
+ caddr_t rpq_queue; /* Pointer to this queue base */
+ uint32_t rpq_index; /* Index of next replyq entry */
+ uint32_t rpq_ncmds; /* Number of outstanding commands */
+ mptsas_done_list_t rpq_dlist;
+ uint32_t rpq_intr_count;
+ uint32_t rpq_intr_unclaimed;
+ uint32_t rpq_intr_mutexbusy;
+ } mptsas_reply_pqueue_t;
+
+
+ typedef struct mptsas_tx_waitqueue {
+ kmutex_t txwq_mutex;
+ kcondvar_t txwq_cv;
+ kcondvar_t txwq_drain_cv;
+ kthread_t *txwq_threadp;
+ mptsas_cmd_t *txwq_cmdq; /* TX cmd queue for active request */
+ mptsas_cmd_t **txwq_qtail; /* tx_wait queue tail ptr */
+ uint32_t txwq_len; /* TX queue length */
+ mptsas_thread_arg_t arg;
+ uint8_t txwq_active; /* Thread active flag */
+ uint8_t txwq_draining; /* TX queue draining flag */
+ uint8_t txwq_wdrain;
+ } mptsas_tx_waitqueue_t;
+
+ #define NUM_TX_WAITQ 2
+
typedef struct mptsas {
int m_instance;
struct mptsas *m_next;
*** 685,720 ****
refhash_t *m_targets;
refhash_t *m_smp_targets;
m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
uint8_t m_num_raid_configs;
struct mptsas_slots *m_active; /* outstanding cmds */
mptsas_cmd_t *m_waitq; /* cmd queue for active request */
mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
!
! kmutex_t m_tx_waitq_mutex;
! mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */
! mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */
! int m_tx_draining; /* TX queue draining flag */
!
! mptsas_cmd_t *m_doneq; /* queue of completed commands */
! mptsas_cmd_t **m_donetail; /* queue tail ptr */
/*
* variables for helper threads (fan-out interrupts)
*/
mptsas_doneq_thread_list_t *m_doneq_thread_id;
! uint32_t m_doneq_thread_n;
uint32_t m_doneq_thread_threshold;
uint32_t m_doneq_length_threshold;
! uint32_t m_doneq_len;
! kcondvar_t m_doneq_thread_cv;
! kmutex_t m_doneq_mutex;
! int m_ncmds; /* number of outstanding commands */
m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
ddi_acc_handle_t m_datap; /* operating regs data access handle */
--- 738,774 ----
refhash_t *m_targets;
refhash_t *m_smp_targets;
m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
uint8_t m_num_raid_configs;
+ uint8_t m_pref_tx_waitq;
struct mptsas_slots *m_active; /* outstanding cmds */
mptsas_cmd_t *m_waitq; /* cmd queue for active request */
mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
! mptsas_tx_waitqueue_t m_tx_waitq[NUM_TX_WAITQ];
! uint16_t m_txwq_thread_threshold;
! uint16_t m_txwq_thread_n;
! uint8_t m_txwq_enabled;
! uint8_t m_txwq_allow_q_jumping;
! mptsas_done_list_t m_dlist; /* List of completed commands */
/*
* variables for helper threads (fan-out interrupts)
*/
mptsas_doneq_thread_list_t *m_doneq_thread_id;
! uint16_t m_doneq_thread_n;
! uint16_t m_doneq_next_thread;
uint32_t m_doneq_thread_threshold;
uint32_t m_doneq_length_threshold;
! kcondvar_t m_qthread_cv;
! kmutex_t m_qthread_mutex;
! uint32_t m_ncmds; /* number of outstanding commands */
! uint32_t m_ncstarted; /* ncmds started per interval */
! uint32_t m_lncstarted; /* record of last value */
m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
ddi_acc_handle_t m_datap; /* operating regs data access handle */
*** 729,744 ****
--- 783,801 ----
timeout_id_t m_quiesce_timeid;
ddi_dma_handle_t m_dma_req_frame_hdl;
ddi_acc_handle_t m_acc_req_frame_hdl;
+ ddi_dma_handle_t m_dma_req_sense_hdl;
+ ddi_acc_handle_t m_acc_req_sense_hdl;
ddi_dma_handle_t m_dma_reply_frame_hdl;
ddi_acc_handle_t m_acc_reply_frame_hdl;
ddi_dma_handle_t m_dma_free_queue_hdl;
ddi_acc_handle_t m_acc_free_queue_hdl;
ddi_dma_handle_t m_dma_post_queue_hdl;
ddi_acc_handle_t m_acc_post_queue_hdl;
+ uint8_t m_dma_flags;
/*
* list of reset notification requests
*/
struct scsi_reset_notify_entry *m_reset_notify_listf;
*** 764,775 ****
/*
* hba options.
*/
uint_t m_options;
- int m_in_callback;
-
int m_power_level; /* current power level */
int m_busy; /* power management busy state */
off_t m_pmcsr_offset; /* PMCSR offset */
--- 821,830 ----
*** 784,825 ****
/*
* request/reply variables
*/
caddr_t m_req_frame;
uint64_t m_req_frame_dma_addr;
caddr_t m_reply_frame;
uint64_t m_reply_frame_dma_addr;
caddr_t m_free_queue;
uint64_t m_free_queue_dma_addr;
caddr_t m_post_queue;
uint64_t m_post_queue_dma_addr;
m_replyh_arg_t *m_replyh_args;
uint16_t m_max_requests;
uint16_t m_req_frame_size;
/*
! * Max frames per request reprted in IOC Facts
*/
uint8_t m_max_chain_depth;
/*
* Max frames per request which is used in reality. It's adjusted
* according DMA SG length attribute, and shall not exceed the
* m_max_chain_depth.
*/
uint8_t m_max_request_frames;
uint16_t m_free_queue_depth;
uint16_t m_post_queue_depth;
uint16_t m_max_replies;
uint32_t m_free_index;
- uint32_t m_post_index;
- uint8_t m_reply_frame_size;
uint32_t m_ioc_capabilities;
/*
* indicates if the firmware was upload by the driver
* at boot time
*/
ushort_t m_fwupload;
--- 839,896 ----
/*
* request/reply variables
*/
caddr_t m_req_frame;
uint64_t m_req_frame_dma_addr;
+ caddr_t m_req_sense;
+ caddr_t m_extreq_sense;
+ uint64_t m_req_sense_dma_addr;
caddr_t m_reply_frame;
uint64_t m_reply_frame_dma_addr;
caddr_t m_free_queue;
uint64_t m_free_queue_dma_addr;
caddr_t m_post_queue;
uint64_t m_post_queue_dma_addr;
+ struct map *m_erqsense_map;
+ mptsas_reply_pqueue_t *m_rep_post_queues;
m_replyh_arg_t *m_replyh_args;
uint16_t m_max_requests;
uint16_t m_req_frame_size;
+ uint16_t m_req_sense_size;
/*
! * Max frames per request reported in IOC Facts
*/
uint8_t m_max_chain_depth;
/*
* Max frames per request which is used in reality. It's adjusted
* according DMA SG length attribute, and shall not exceed the
* m_max_chain_depth.
*/
uint8_t m_max_request_frames;
+ uint8_t m_max_msix_vectors;
+ uint8_t m_reply_frame_size;
+ uint8_t m_post_reply_qcount;
uint16_t m_free_queue_depth;
uint16_t m_post_queue_depth;
uint16_t m_max_replies;
uint32_t m_free_index;
uint32_t m_ioc_capabilities;
/*
+ * Housekeeping.
+ */
+ uint64_t m_interrupt_count;
+ uint32_t m_unclaimed_pm_interrupt_count;
+ uint32_t m_unclaimed_polled_interrupt_count;
+ uint32_t m_unclaimed_no_interrupt_count;
+ uint32_t m_unclaimed_nocmd_interrupt_count;
+
+ /*
* indicates if the firmware was upload by the driver
* at boot time
*/
ushort_t m_fwupload;
*** 889,898 ****
--- 960,972 ----
* FW diag Buffer List
*/
mptsas_fw_diagnostic_buffer_t
m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
+ /* GEN3 support */
+ uint8_t m_MPI25;
+
/*
* Event Replay flag (MUR support)
*/
uint8_t m_event_replay;
*** 933,945 ****
_NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
_NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
_NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
_NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
_NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
- _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type))
_NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
- _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets))
_NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
/*
* These should eventually migrate into the mpt header files
* that may become the /kernel/misc/mpt module...
--- 1007,1017 ----
*** 983,1002 ****
--- 1055,1085 ----
/*
* m_options flags
*/
#define MPTSAS_OPT_PM 0x01 /* Power Management */
+ #define MPTSAS_OPT_MSI 0x02 /* PCI MSI Interrupts */
+ #define MPTSAS_OPT_MSI_X 0x04 /* PCI MSI-X Interrupts */
/*
* m_softstate flags
*/
#define MPTSAS_SS_DRAINING 0x02
#define MPTSAS_SS_QUIESCED 0x04
#define MPTSAS_SS_MSG_UNIT_RESET 0x08
#define MPTSAS_DID_MSG_UNIT_RESET 0x10
/*
+ * m_dma_flags (allocated).
+ */
+ #define MPTSAS_REQ_FRAME 0x01
+ #define MPTSAS_REQ_SENSE 0x02
+ #define MPTSAS_REPLY_FRAME 0x04
+ #define MPTSAS_FREE_QUEUE 0x08
+ #define MPTSAS_POST_QUEUE 0x10
+
+ /*
* regspec defines.
*/
#define CONFIG_SPACE 0 /* regset[0] - configuration space */
#define IO_SPACE 1 /* regset[1] - used for i/o mapped device */
#define MEM_SPACE 2 /* regset[2] - used for memory mapped device */
*** 1005,1014 ****
--- 1088,1098 ----
/*
* Handy constants
*/
#define FALSE 0
#define TRUE 1
+ #define BLOCKED 2
#define UNDEFINED -1
#define FAILED -2
/*
* power management.
*** 1103,1117 ****
#define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
(uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
! #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \
! ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\
! req_desc_lo);\
! ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\
! req_desc_hi);
#define INTPENDING(mpt) \
(MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
/*
--- 1187,1202 ----
#define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
(uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
! #define MPTSAS_START_CMD(mpt, req_desc) \
! ddi_put64(mpt->m_datap, \
! (uint64_t *)(void *)&mpt->m_reg->RequestDescriptorPostLow, \
! req_desc); \
! atomic_inc_32(&mpt->m_ncstarted)
!
#define INTPENDING(mpt) \
(MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
/*
*** 1126,1137 ****
*/
#define MPTSAS_ENABLE_INTR(mpt) \
ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
(MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
! #define MPTSAS_GET_NEXT_REPLY(mpt, index) \
! &((uint64_t *)(void *)mpt->m_post_queue)[index]
#define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
(mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
#define ClrSetBits32(hdl, reg, clr, set) \
--- 1211,1222 ----
*/
#define MPTSAS_ENABLE_INTR(mpt) \
ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
(MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
! #define MPTSAS_GET_NEXT_REPLY(rpqp, index) \
! &((uint64_t *)(void *)rpqp->rpq_queue)[index]
#define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
(mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
#define ClrSetBits32(hdl, reg, clr, set) \
*** 1163,1173 ****
/*
* defaults for the global properties
*/
#define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
#define DEFAULT_TAG_AGE_LIMIT 2
! #define DEFAULT_WD_TICK 10
/*
* invalid hostid.
*/
#define MPTSAS_INVALID_HOSTID -1
--- 1248,1258 ----
/*
* defaults for the global properties
*/
#define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
#define DEFAULT_TAG_AGE_LIMIT 2
! #define DEFAULT_WD_TICK 1
/*
* invalid hostid.
*/
#define MPTSAS_INVALID_HOSTID -1
*** 1250,1267 ****
void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
- int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
- uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
- uint8_t pageversion, uint8_t pagelength, uint32_t
- SGEflagslength, uint32_t SGEaddress32);
- int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
- uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
- uint8_t pageversion, uint16_t extpagelength,
- uint32_t SGEflagslength, uint32_t SGEaddress32);
int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
uint8_t type, int mode);
int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
uint8_t type, int mode);
int mptsas_download_firmware();
--- 1335,1344 ----
*** 1289,1303 ****
int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
ddi_acc_handle_t accessp);
int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
! uint32_t SGEaddress32);
int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
uint8_t pageversion, uint16_t extpagelength,
! uint32_t SGEflagslength, uint32_t SGEaddress32);
int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
struct scsi_pkt **pkt);
void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
--- 1366,1380 ----
int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
ddi_acc_handle_t accessp);
int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
! uint64_t SGEaddress);
int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
uint8_t pageversion, uint16_t extpagelength,
! uint32_t SGEflagslength, uint64_t SGEaddress);
int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
struct scsi_pkt **pkt);
void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
*** 1309,1319 ****
int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
int mode);
int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
void mptsas_send_pending_event_ack(mptsas_t *mpt);
- void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
int mptsas_restart_ioc(mptsas_t *mpt);
void mptsas_update_driver_data(struct mptsas *mpt);
uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
/*
--- 1386,1395 ----
*** 1329,1339 ****
* configuration pages operation
*/
int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
! uint16_t *slot_num, uint16_t *enclosure);
int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
mptsas_smp_t *info);
int mptsas_set_ioc_params(mptsas_t *mpt);
--- 1405,1415 ----
* configuration pages operation
*/
int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
! uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags);
int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
mptsas_smp_t *info);
int mptsas_set_ioc_params(mptsas_t *mpt);
*** 1368,1381 ****
* debugging.
*/
#if defined(MPTSAS_DEBUG)
void mptsas_printf(char *fmt, ...);
#define MPTSAS_DBGPR(m, args) \
if (mptsas_debug_flags & (m)) \
! mptsas_printf args
#else /* ! defined(MPTSAS_DEBUG) */
#define MPTSAS_DBGPR(m, args)
#endif /* defined(MPTSAS_DEBUG) */
#define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
--- 1444,1460 ----
* debugging.
*/
#if defined(MPTSAS_DEBUG)
void mptsas_printf(char *fmt, ...);
+ void mptsas_debug_log(char *fmt, ...);
#define MPTSAS_DBGPR(m, args) \
if (mptsas_debug_flags & (m)) \
! mptsas_printf args; \
! if (~mptsas_dbglog_imask & (m)) \
! mptsas_debug_log args
#else /* ! defined(MPTSAS_DEBUG) */
#define MPTSAS_DBGPR(m, args)
#endif /* defined(MPTSAS_DEBUG) */
#define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
*** 1383,1408 ****
#define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
#define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
#define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
#define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
! #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
#define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
#define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
#define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
#define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
#define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
#define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
#define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
#define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
! #define NDBG15(args) MPTSAS_DBGPR(0x8000, args)
! #define NDBG16(args) MPTSAS_DBGPR(0x010000, args)
#define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
! #define NDBG18(args) MPTSAS_DBGPR(0x040000, args)
#define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
#define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
#define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
#define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
--- 1462,1487 ----
#define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
#define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
#define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
#define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
! #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupt setup */
#define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
#define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
#define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
#define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
#define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
#define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
#define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
#define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
! #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */
! #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */
#define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
! #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) /* Interrupts */
#define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
#define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
#define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
#define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
*** 1435,1440 ****
#ifdef __cplusplus
}
#endif
! #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */
--- 1514,1519 ----
#ifdef __cplusplus
}
#endif
! #endif /* _SYS_SCSI_ADAPTERS_MPTSAS3_VAR_H */