1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
  24  * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
  25  * Copyright (c) 2013, Joyent, Inc. All rights reserved.
  26  */
  27 
  28 /*
  29  * Copyright (c) 2000 to 2010, LSI Corporation.
  30  * All rights reserved.
  31  *
  32  * Redistribution and use in source and binary forms of all code within
  33  * this file that is exclusively owned by LSI, with or without
  34  * modification, is permitted provided that, in addition to the CDDL 1.0
  35  * License requirements, the following conditions are met:
  36  *
  37  *    Neither the name of the author nor the names of its contributors may be
  38  *    used to endorse or promote products derived from this software without
  39  *    specific prior written permission.
  40  *
  41  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  42  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  43  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  44  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  45  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  46  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  47  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  48  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  49  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  50  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  51  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  52  * DAMAGE.
  53  */
  54 
  55 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
  56 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
  57 
  58 #include <sys/byteorder.h>
  59 #include <sys/isa_defs.h>
  60 #include <sys/sunmdi.h>
  61 #include <sys/mdi_impldefs.h>
  62 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
  63 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
  64 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
  65 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
  66 
  67 #ifdef  __cplusplus
  68 extern "C" {
  69 #endif
  70 
  71 /*
  72  * Compile options
  73  */
  74 #ifdef DEBUG
  75 #define MPTSAS_DEBUG            /* turn on debugging code */
  76 #endif  /* DEBUG */
  77 
  78 #define MPTSAS_INITIAL_SOFT_SPACE       4
  79 
  80 #define MAX_MPI_PORTS           16
  81 
  82 /*
  83  * Note below macro definition and data type definition
  84  * are used for phy mask handling, it should be changed
  85  * simultaneously.
  86  */
  87 #define MPTSAS_MAX_PHYS         16
  88 typedef uint16_t                mptsas_phymask_t;
  89 
  90 #define MPTSAS_INVALID_DEVHDL   0xffff
  91 #define MPTSAS_SATA_GUID        "sata-guid"
  92 
  93 /*
  94  * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
  95  * targets.  There's no need to go overboard here, as the ordinary paths for
  96  * I/O do not normally require hashed target lookups.  These should be good
  97  * enough and then some for any fabric within the hardware's capabilities.
  98  */
  99 #define MPTSAS_SMP_BUCKET_COUNT         23
 100 #define MPTSAS_TARGET_BUCKET_COUNT      97
 101 
 102 /*
 103  * MPT HW defines
 104  */
 105 #define MPTSAS_MAX_DISKS_IN_CONFIG      14
 106 #define MPTSAS_MAX_DISKS_IN_VOL         10
 107 #define MPTSAS_MAX_HOTSPARES            2
 108 #define MPTSAS_MAX_RAIDVOLS             2
 109 #define MPTSAS_MAX_RAIDCONFIGS          5
 110 
 111 /*
 112  * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
 113  * plus two means the prefix 'w' and end of the string '\0'.
 114  */
 115 #define MPTSAS_WWN_STRLEN       (16 + 2)
 116 #define MPTSAS_MAX_GUID_LEN     64
 117 
 118 /*
 119  * DMA routine flags
 120  */
 121 #define MPTSAS_DMA_HANDLE_ALLOCD        0x2
 122 #define MPTSAS_DMA_MEMORY_ALLOCD        0x4
 123 #define MPTSAS_DMA_HANDLE_BOUND 0x8
 124 
 125 /*
 126  * If the HBA supports DMA or bus-mastering, you may have your own
 127  * scatter-gather list for physically non-contiguous memory in one
 128  * I/O operation; if so, there's probably a size for that list.
 129  * It must be placed in the ddi_dma_lim_t structure, so that the system
 130  * DMA-support routines can use it to break up the I/O request, so we
 131  * define it here.
 132  */
 133 #if defined(__sparc)
 134 #define MPTSAS_MAX_DMA_SEGS     1
 135 #define MPTSAS_MAX_CMD_SEGS     1
 136 #else
 137 #define MPTSAS_MAX_DMA_SEGS     256
 138 #define MPTSAS_MAX_CMD_SEGS     257
 139 #endif
 140 #define MPTSAS_MAX_FRAME_SGES(mpt) \
 141         (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
 142 
 143 /*
 144  * Caculating how many 64-bit DMA simple elements can be stored in the first
 145  * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
 146  * element storage.  And 64-bit dma element is 3 double-words (12 bytes) in
 147  * size.
 148  */
 149 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
 150         ((mpt->m_req_frame_size - \
 151         (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12)
 152 
 153 /*
 154  * Scatter-gather list structure defined by HBA hardware
 155  */
 156 typedef struct NcrTableIndirect {       /* Table Indirect entries */
 157         uint32_t count;         /* 24 bit count */
 158         union {
 159                 uint32_t address32;     /* 32 bit address */
 160                 struct {
 161                         uint32_t Low;
 162                         uint32_t High;
 163                 } address64;            /* 64 bit address */
 164         } addr;
 165 } mptti_t;
 166 
 167 /*
 168  * preferred pkt_private length in 64-bit quantities
 169  */
 170 #ifdef  _LP64
 171 #define PKT_PRIV_SIZE   2
 172 #define PKT_PRIV_LEN    16      /* in bytes */
 173 #else /* _ILP32 */
 174 #define PKT_PRIV_SIZE   1
 175 #define PKT_PRIV_LEN    8       /* in bytes */
 176 #endif
 177 
 178 #define PKT2CMD(pkt)    ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
 179 #define CMD2PKT(cmdp)   ((struct scsi_pkt *)((cmdp)->cmd_pkt))
 180 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
 181 
 182 /*
 183  * get offset of item in structure
 184  */
 185 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
 186 
 187 /*
 188  * WWID provided by LSI firmware is generated by firmware but the WWID is not
 189  * IEEE NAA standard format, OBP has no chance to distinguish format of unit
 190  * address. According LSI's confirmation, the top nibble of RAID WWID is
 191  * meanless, so the consensus between Solaris and OBP is to replace top nibble
 192  * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
 193  * format unit address.
 194  */
 195 #define MPTSAS_RAID_WWID(wwid) \
 196         ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
 197 
 198 typedef struct mptsas_target_addr {
 199         uint64_t mta_wwn;
 200         mptsas_phymask_t mta_phymask;
 201 } mptsas_target_addr_t;
 202 
 203 typedef struct mptsas_target {
 204                 mptsas_target_addr_t    m_addr;
 205                 refhash_link_t          m_link;
 206                 uint8_t                 m_dr_flag;
 207                 uint16_t                m_devhdl;
 208                 uint32_t                m_deviceinfo;
 209                 uint8_t                 m_phynum;
 210                 uint32_t                m_dups;
 211                 int32_t                 m_timeout;
 212                 int32_t                 m_timebase;
 213                 int32_t                 m_t_throttle;
 214                 int32_t                 m_t_ncmds;
 215                 int32_t                 m_reset_delay;
 216                 int32_t                 m_t_nwait;
 217 
 218                 uint16_t                m_qfull_retry_interval;
 219                 uint8_t                 m_qfull_retries;
 220                 uint16_t                m_enclosure;
 221                 uint16_t                m_slot_num;
 222                 uint32_t                m_tgt_unconfigured;
 223                 uint8_t                 m_led_status;
 224 
 225 } mptsas_target_t;
 226 
 227 typedef struct mptsas_smp {
 228         mptsas_target_addr_t    m_addr;
 229         refhash_link_t          m_link;
 230         uint16_t                m_devhdl;
 231         uint32_t                m_deviceinfo;
 232         uint16_t                m_pdevhdl;
 233         uint32_t                m_pdevinfo;
 234 } mptsas_smp_t;
 235 
 236 typedef struct mptsas_cache_frames {
 237         ddi_dma_handle_t m_dma_hdl;
 238         ddi_acc_handle_t m_acc_hdl;
 239         caddr_t m_frames_addr;
 240         uint32_t m_phys_addr;
 241 } mptsas_cache_frames_t;
 242 
 243 typedef struct  mptsas_cmd {
 244         uint_t                  cmd_flags;      /* flags from scsi_init_pkt */
 245         ddi_dma_handle_t        cmd_dmahandle;  /* dma handle */
 246         ddi_dma_cookie_t        cmd_cookie;
 247         uint_t                  cmd_cookiec;
 248         uint_t                  cmd_winindex;
 249         uint_t                  cmd_nwin;
 250         uint_t                  cmd_cur_cookie;
 251         off_t                   cmd_dma_offset;
 252         size_t                  cmd_dma_len;
 253         uint32_t                cmd_totaldmacount;
 254 
 255         ddi_dma_handle_t        cmd_arqhandle;  /* dma arq handle */
 256         ddi_dma_cookie_t        cmd_arqcookie;
 257         struct buf              *cmd_arq_buf;
 258         ddi_dma_handle_t        cmd_ext_arqhandle; /* dma extern arq handle */
 259         ddi_dma_cookie_t        cmd_ext_arqcookie;
 260         struct buf              *cmd_ext_arq_buf;
 261 
 262         int                     cmd_pkt_flags;
 263 
 264         /* timer for command in active slot */
 265         int                     cmd_active_timeout;
 266 
 267         struct scsi_pkt         *cmd_pkt;
 268         struct scsi_arq_status  cmd_scb;
 269         uchar_t                 cmd_cdblen;     /* length of cdb */
 270         uchar_t                 cmd_rqslen;     /* len of requested rqsense */
 271         uchar_t                 cmd_privlen;
 272         uint_t                  cmd_scblen;
 273         uint32_t                cmd_dmacount;
 274         uint64_t                cmd_dma_addr;
 275         uchar_t                 cmd_age;
 276         ushort_t                cmd_qfull_retries;
 277         uchar_t                 cmd_queued;     /* true if queued */
 278         struct mptsas_cmd       *cmd_linkp;
 279         mptti_t                 *cmd_sg; /* Scatter/Gather structure */
 280         uchar_t                 cmd_cdb[SCSI_CDB_SIZE];
 281         uint64_t                cmd_pkt_private[PKT_PRIV_LEN];
 282         uint32_t                cmd_slot;
 283         uint32_t                ioc_cmd_slot;
 284 
 285         mptsas_cache_frames_t   *cmd_extra_frames;
 286 
 287         uint32_t                cmd_rfm;
 288         mptsas_target_t         *cmd_tgt_addr;
 289 } mptsas_cmd_t;
 290 
 291 /*
 292  * These are the defined cmd_flags for this structure.
 293  */
 294 #define CFLAG_CMDDISC           0x000001 /* cmd currently disconnected */
 295 #define CFLAG_WATCH             0x000002 /* watchdog time for this command */
 296 #define CFLAG_FINISHED          0x000004 /* command completed */
 297 #define CFLAG_CHKSEG            0x000008 /* check cmd_data within seg */
 298 #define CFLAG_COMPLETED         0x000010 /* completion routine called */
 299 #define CFLAG_PREPARED          0x000020 /* pkt has been init'ed */
 300 #define CFLAG_IN_TRANSPORT      0x000040 /* in use by host adapter driver */
 301 #define CFLAG_RESTORE_PTRS      0x000080 /* implicit restore ptr on reconnect */
 302 #define CFLAG_ARQ_IN_PROGRESS   0x000100 /* auto request sense in progress */
 303 #define CFLAG_TRANFLAG          0x0001ff /* covers transport part of flags */
 304 #define CFLAG_TM_CMD            0x000200 /* cmd is a task management command */
 305 #define CFLAG_CMDARQ            0x000400 /* cmd is a 'rqsense' command */
 306 #define CFLAG_DMAVALID          0x000800 /* dma mapping valid */
 307 #define CFLAG_DMASEND           0x001000 /* data is going 'out' */
 308 #define CFLAG_CMDIOPB           0x002000 /* this is an 'iopb' packet */
 309 #define CFLAG_CDBEXTERN         0x004000 /* cdb kmem_alloc'd */
 310 #define CFLAG_SCBEXTERN         0x008000 /* scb kmem_alloc'd */
 311 #define CFLAG_FREE              0x010000 /* packet is on free list */
 312 #define CFLAG_PRIVEXTERN        0x020000 /* target private kmem_alloc'd */
 313 #define CFLAG_DMA_PARTIAL       0x040000 /* partial xfer OK */
 314 #define CFLAG_QFULL_STATUS      0x080000 /* pkt got qfull status */
 315 #define CFLAG_TIMEOUT           0x100000 /* passthru/config command timeout */
 316 #define CFLAG_PMM_RECEIVED      0x200000 /* use cmd_pmm* for saving pointers */
 317 #define CFLAG_RETRY             0x400000 /* cmd has been retried */
 318 #define CFLAG_CMDIOC            0x800000 /* cmd is just for for ioc, no io */
 319 #define CFLAG_EXTARQBUFVALID    0x1000000 /* extern arq buf handle is valid */
 320 #define CFLAG_PASSTHRU          0x2000000 /* cmd is a passthrough command */
 321 #define CFLAG_XARQ              0x4000000 /* cmd requests for extra sense */
 322 #define CFLAG_CMDACK            0x8000000 /* cmd for event ack */
 323 #define CFLAG_TXQ               0x10000000 /* cmd queued in the tx_waitq */
 324 #define CFLAG_FW_CMD            0x20000000 /* cmd is a fw up/down command */
 325 #define CFLAG_CONFIG            0x40000000 /* cmd is for config header/page */
 326 #define CFLAG_FW_DIAG           0x80000000 /* cmd is for FW diag buffers */
 327 
 328 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE                     8
 329 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK                     0xC0
 330 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL                       0x00
 331 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE                       0x40
 332 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT             0x80
 333 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT            0xC0
 334 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B          0x00
 335 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B          0x01
 336 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B          0x10
 337 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B          0x20
 338 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE                0x30
 339 
 340 #define MPTSAS_HASH_ARRAY_SIZE  16
 341 /*
 342  * hash table definition
 343  */
 344 
 345 #define MPTSAS_HASH_FIRST       0xffff
 346 #define MPTSAS_HASH_NEXT        0x0000
 347 
 348 typedef struct mptsas_dma_alloc_state
 349 {
 350         ddi_dma_handle_t        handle;
 351         caddr_t                 memp;
 352         size_t                  size;
 353         ddi_acc_handle_t        accessp;
 354         ddi_dma_cookie_t        cookie;
 355 } mptsas_dma_alloc_state_t;
 356 
 357 /*
 358  * passthrough request structure
 359  */
 360 typedef struct mptsas_pt_request {
 361         uint8_t *request;
 362         uint32_t request_size;
 363         uint32_t data_size;
 364         uint32_t dataout_size;
 365         uint32_t direction;
 366         ddi_dma_cookie_t data_cookie;
 367         ddi_dma_cookie_t dataout_cookie;
 368 } mptsas_pt_request_t;
 369 
 370 /*
 371  * config page request structure
 372  */
 373 typedef struct mptsas_config_request {
 374         uint32_t        page_address;
 375         uint8_t         action;
 376         uint8_t         page_type;
 377         uint8_t         page_number;
 378         uint8_t         page_length;
 379         uint8_t         page_version;
 380         uint8_t         ext_page_type;
 381         uint16_t        ext_page_length;
 382 } mptsas_config_request_t;
 383 
 384 typedef struct mptsas_fw_diagnostic_buffer {
 385         mptsas_dma_alloc_state_t        buffer_data;
 386         uint8_t                         extended_type;
 387         uint8_t                         buffer_type;
 388         uint8_t                         force_release;
 389         uint32_t                        product_specific[23];
 390         uint8_t                         immediate;
 391         uint8_t                         enabled;
 392         uint8_t                         valid_data;
 393         uint8_t                         owned_by_firmware;
 394         uint32_t                        unique_id;
 395 } mptsas_fw_diagnostic_buffer_t;
 396 
 397 /*
 398  * FW diag request structure
 399  */
 400 typedef struct mptsas_diag_request {
 401         mptsas_fw_diagnostic_buffer_t   *pBuffer;
 402         uint8_t                         function;
 403 } mptsas_diag_request_t;
 404 
 405 typedef struct mptsas_hash_node {
 406         void *data;
 407         struct mptsas_hash_node *next;
 408 } mptsas_hash_node_t;
 409 
 410 typedef struct mptsas_hash_table {
 411         struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
 412         /*
 413          * last position in traverse
 414          */
 415         struct mptsas_hash_node *cur;
 416         uint16_t line;
 417 
 418 } mptsas_hash_table_t;
 419 
 420 /*
 421  * RAID volume information
 422  */
 423 typedef struct mptsas_raidvol {
 424         ushort_t        m_israid;
 425         uint16_t        m_raidhandle;
 426         uint64_t        m_raidwwid;
 427         uint8_t         m_state;
 428         uint32_t        m_statusflags;
 429         uint32_t        m_settings;
 430         uint16_t        m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
 431         uint8_t         m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
 432         ushort_t        m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
 433         uint64_t        m_raidsize;
 434         int             m_raidlevel;
 435         int             m_ndisks;
 436         mptsas_target_t *m_raidtgt;
 437 } mptsas_raidvol_t;
 438 
 439 /*
 440  * RAID configurations
 441  */
 442 typedef struct mptsas_raidconfig {
 443                 mptsas_raidvol_t        m_raidvol[MPTSAS_MAX_RAIDVOLS];
 444                 uint16_t                m_physdisk_devhdl[
 445                                             MPTSAS_MAX_DISKS_IN_CONFIG];
 446                 uint8_t                 m_native;
 447 } m_raidconfig_t;
 448 
 449 /*
 450  * Track outstanding commands.  The index into the m_slot array is the SMID
 451  * (system message ID) of the outstanding command.  SMID 0 is reserved by the
 452  * software/firmware protocol and is never used for any command we generate;
 453  * as such, the assertion m_slot[0] == NULL is universally true.  The last
 454  * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for
 455  * task management commands.  No normal SCSI or ATA command will ever occupy
 456  * that slot.  Finally, the relationship m_slot[X]->cmd_slot == X holds at any
 457  * time that a consistent view of the target array is obtainable.
 458  *
 459  * As such, m_n_normal is the maximum number of slots available to ordinary
 460  * commands, and the relationship:
 461  * mpt->m_active->m_n_normal == mpt->m_max_requests - 2
 462  * always holds after initialisation.
 463  */
 464 typedef struct mptsas_slots {
 465         size_t                  m_size;         /* size of struct, bytes */
 466         uint_t                  m_n_normal;     /* see above */
 467         uint_t                  m_rotor;        /* next slot idx to consider */
 468         mptsas_cmd_t            *m_slot[1];
 469 } mptsas_slots_t;
 470 
 471 /*
 472  * Structure to hold command and packets for event ack
 473  * and task management commands.
 474  */
 475 typedef struct  m_event_struct {
 476         struct mptsas_cmd               m_event_cmd;
 477         struct m_event_struct   *m_event_linkp;
 478         /*
 479          * event member record the failure event and eventcntx
 480          * event member would be used in send ack pending process
 481          */
 482         uint32_t                m_event;
 483         uint32_t                m_eventcntx;
 484         uint_t                  in_use;
 485         struct scsi_pkt         m_event_pkt;    /* must be last */
 486                                                 /* ... scsi_pkt_size() */
 487 } m_event_struct_t;
 488 #define M_EVENT_STRUCT_SIZE     (sizeof (m_event_struct_t) - \
 489                                 sizeof (struct scsi_pkt) + scsi_pkt_size())
 490 
 491 #define MAX_IOC_COMMANDS        8
 492 
 493 /*
 494  * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
 495  * A new event ack command requests mptsas_cmd and scsi_pkt structures
 496  * from this pool, and returns it back when done.
 497  */
 498 
 499 typedef struct m_replyh_arg {
 500         void *mpt;
 501         uint32_t rfm;
 502 } m_replyh_arg_t;
 503 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
 504 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
 505 
 506 /*
 507  * Flags for DR handler topology change
 508  */
 509 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE         0x0
 510 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED            0x1
 511 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED                 0x2
 512 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED                0x4
 513 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED        0x8
 514 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE       0x10
 515 
 516 typedef struct mptsas_topo_change_list {
 517         void *mpt;
 518         uint_t  event;
 519         union {
 520                 uint8_t physport;
 521                 mptsas_phymask_t phymask;
 522         } un;
 523         uint16_t devhdl;
 524         void *object;
 525         uint8_t flags;
 526         struct mptsas_topo_change_list *next;
 527 } mptsas_topo_change_list_t;
 528 
 529 
 530 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
 531 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
 532 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
 533 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
 534 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
 535 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
 536 
 537 /*
 538  * Status types when calling mptsas_get_target_device_info
 539  */
 540 #define DEV_INFO_SUCCESS                0x0
 541 #define DEV_INFO_FAIL_PAGE0             0x1
 542 #define DEV_INFO_WRONG_DEVICE_TYPE      0x2
 543 #define DEV_INFO_PHYS_DISK              0x3
 544 #define DEV_INFO_FAIL_ALLOC             0x4
 545 
 546 /*
 547  * mpt hotplug event defines
 548  */
 549 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
 550 #define MPTSAS_DR_EVENT_OFFLINE_TARGET  0x02
 551 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE  0x04
 552 
 553 /*
 554  * SMP target hotplug events
 555  */
 556 #define MPTSAS_DR_EVENT_RECONFIG_SMP    0x10
 557 #define MPTSAS_DR_EVENT_OFFLINE_SMP     0x20
 558 #define MPTSAS_DR_EVENT_MASK            0x3F
 559 
 560 /*
 561  * mpt hotplug status definition for m_dr_flag
 562  */
 563 
 564 /*
 565  * MPTSAS_DR_INACTIVE
 566  *
 567  * The target is in a normal operating state.
 568  * No dynamic reconfiguration operation is in progress.
 569  */
 570 #define MPTSAS_DR_INACTIVE                              0x0
 571 /*
 572  * MPTSAS_DR_INTRANSITION
 573  *
 574  * The target is in a transition mode since
 575  * hotplug event happens and offline procedure has not
 576  * been finished
 577  */
 578 #define MPTSAS_DR_INTRANSITION                  0x1
 579 
 580 typedef struct mptsas_tgt_private {
 581         int t_lun;
 582         struct mptsas_target *t_private;
 583 } mptsas_tgt_private_t;
 584 
 585 /*
 586  * The following defines are used in mptsas_set_init_mode to track the current
 587  * state as we progress through reprogramming the HBA from target mode into
 588  * initiator mode.
 589  */
 590 
 591 #define IOUC_READ_PAGE0         0x00000100
 592 #define IOUC_READ_PAGE1         0x00000200
 593 #define IOUC_WRITE_PAGE1        0x00000400
 594 #define IOUC_DONE               0x00000800
 595 #define DISCOVERY_IN_PROGRESS   MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
 596 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
 597 
 598 /*
 599  * Last allocated slot is used for TM requests.  Since only m_max_requests
 600  * frames are allocated, the last SMID will be m_max_requests - 1.
 601  */
 602 #define MPTSAS_SLOTS_SIZE(mpt) \
 603         (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
 604                 mpt->m_max_requests))
 605 #define MPTSAS_TM_SLOT(mpt)     (mpt->m_max_requests - 1)
 606 
 607 /*
 608  * Macro for phy_flags
 609  */
 610 
 611 typedef struct smhba_info {
 612         kmutex_t        phy_mutex;
 613         uint8_t         phy_id;
 614         uint64_t        sas_addr;
 615         char            path[8];
 616         uint16_t        owner_devhdl;
 617         uint16_t        attached_devhdl;
 618         uint8_t         attached_phy_identify;
 619         uint32_t        attached_phy_info;
 620         uint8_t         programmed_link_rate;
 621         uint8_t         hw_link_rate;
 622         uint8_t         change_count;
 623         uint32_t        phy_info;
 624         uint8_t         negotiated_link_rate;
 625         uint8_t         port_num;
 626         kstat_t         *phy_stats;
 627         uint32_t        invalid_dword_count;
 628         uint32_t        running_disparity_error_count;
 629         uint32_t        loss_of_dword_sync_count;
 630         uint32_t        phy_reset_problem_count;
 631         void            *mpt;
 632 } smhba_info_t;
 633 
 634 typedef struct mptsas_phy_info {
 635         uint8_t                 port_num;
 636         uint8_t                 port_flags;
 637         uint16_t                ctrl_devhdl;
 638         uint32_t                phy_device_type;
 639         uint16_t                attached_devhdl;
 640         mptsas_phymask_t        phy_mask;
 641         smhba_info_t            smhba_info;
 642 } mptsas_phy_info_t;
 643 
 644 
 645 typedef struct mptsas_doneq_thread_arg {
 646         void            *mpt;
 647         uint64_t        t;
 648 } mptsas_doneq_thread_arg_t;
 649 
 650 #define MPTSAS_DONEQ_THREAD_ACTIVE      0x1
 651 typedef struct mptsas_doneq_thread_list {
 652         mptsas_cmd_t            *doneq;
 653         mptsas_cmd_t            **donetail;
 654         kthread_t               *threadp;
 655         kcondvar_t              cv;
 656         ushort_t                reserv1;
 657         uint32_t                reserv2;
 658         kmutex_t                mutex;
 659         uint32_t                flag;
 660         uint32_t                len;
 661         mptsas_doneq_thread_arg_t       arg;
 662 } mptsas_doneq_thread_list_t;
 663 
 664 typedef struct mptsas {
 665         int             m_instance;
 666 
 667         struct mptsas *m_next;
 668 
 669         scsi_hba_tran_t         *m_tran;
 670         smp_hba_tran_t          *m_smptran;
 671         kmutex_t                m_mutex;
 672         kmutex_t                m_passthru_mutex;
 673         kcondvar_t              m_cv;
 674         kcondvar_t              m_passthru_cv;
 675         kcondvar_t              m_fw_cv;
 676         kcondvar_t              m_config_cv;
 677         kcondvar_t              m_fw_diag_cv;
 678         dev_info_t              *m_dip;
 679 
 680         /*
 681          * soft state flags
 682          */
 683         uint_t          m_softstate;
 684 
 685         refhash_t       *m_targets;
 686         refhash_t       *m_smp_targets;
 687 
 688         m_raidconfig_t  m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
 689         uint8_t         m_num_raid_configs;
 690 
 691         struct mptsas_slots *m_active;  /* outstanding cmds */
 692 
 693         mptsas_cmd_t    *m_waitq;       /* cmd queue for active request */
 694         mptsas_cmd_t    **m_waitqtail;  /* wait queue tail ptr */
 695 
 696         kmutex_t        m_tx_waitq_mutex;
 697         mptsas_cmd_t    *m_tx_waitq;    /* TX cmd queue for active request */
 698         mptsas_cmd_t    **m_tx_waitqtail;       /* tx_wait queue tail ptr */
 699         int             m_tx_draining;  /* TX queue draining flag */
 700 
 701         mptsas_cmd_t    *m_doneq;       /* queue of completed commands */
 702         mptsas_cmd_t    **m_donetail;   /* queue tail ptr */
 703 
 704         /*
 705          * variables for helper threads (fan-out interrupts)
 706          */
 707         mptsas_doneq_thread_list_t      *m_doneq_thread_id;
 708         uint32_t                m_doneq_thread_n;
 709         uint32_t                m_doneq_thread_threshold;
 710         uint32_t                m_doneq_length_threshold;
 711         uint32_t                m_doneq_len;
 712         kcondvar_t              m_doneq_thread_cv;
 713         kmutex_t                m_doneq_mutex;
 714 
 715         int             m_ncmds;        /* number of outstanding commands */
 716         m_event_struct_t *m_ioc_event_cmdq;     /* cmd queue for ioc event */
 717         m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
 718 
 719         ddi_acc_handle_t m_datap;       /* operating regs data access handle */
 720 
 721         struct _MPI2_SYSTEM_INTERFACE_REGS      *m_reg;
 722 
 723         ushort_t        m_devid;        /* device id of chip. */
 724         uchar_t         m_revid;        /* revision of chip. */
 725         uint16_t        m_svid;         /* subsystem Vendor ID of chip */
 726         uint16_t        m_ssid;         /* subsystem Device ID of chip */
 727 
 728         uchar_t         m_sync_offset;  /* default offset for this chip. */
 729 
 730         timeout_id_t    m_quiesce_timeid;
 731 
 732         ddi_dma_handle_t m_dma_req_frame_hdl;
 733         ddi_acc_handle_t m_acc_req_frame_hdl;
 734         ddi_dma_handle_t m_dma_reply_frame_hdl;
 735         ddi_acc_handle_t m_acc_reply_frame_hdl;
 736         ddi_dma_handle_t m_dma_free_queue_hdl;
 737         ddi_acc_handle_t m_acc_free_queue_hdl;
 738         ddi_dma_handle_t m_dma_post_queue_hdl;
 739         ddi_acc_handle_t m_acc_post_queue_hdl;
 740 
 741         /*
 742          * list of reset notification requests
 743          */
 744         struct scsi_reset_notify_entry  *m_reset_notify_listf;
 745 
 746         /*
 747          * qfull handling
 748          */
 749         timeout_id_t    m_restart_cmd_timeid;
 750 
 751         /*
 752          * scsi reset delay per bus
 753          */
 754         uint_t          m_scsi_reset_delay;
 755 
 756         int             m_pm_idle_delay;
 757 
 758         uchar_t         m_polled_intr;  /* intr was polled. */
 759         uchar_t         m_suspended;    /* true if driver is suspended */
 760 
 761         struct kmem_cache *m_kmem_cache;
 762         struct kmem_cache *m_cache_frames;
 763 
 764         /*
 765          * hba options.
 766          */
 767         uint_t          m_options;
 768 
 769         int             m_in_callback;
 770 
 771         int             m_power_level;  /* current power level */
 772 
 773         int             m_busy;         /* power management busy state */
 774 
 775         off_t           m_pmcsr_offset; /* PMCSR offset */
 776 
 777         ddi_acc_handle_t m_config_handle;
 778 
 779         ddi_dma_attr_t          m_io_dma_attr;  /* Used for data I/O */
 780         ddi_dma_attr_t          m_msg_dma_attr; /* Used for message frames */
 781         ddi_device_acc_attr_t   m_dev_acc_attr;
 782         ddi_device_acc_attr_t   m_reg_acc_attr;
 783 
 784         /*
 785          * request/reply variables
 786          */
 787         caddr_t         m_req_frame;
 788         uint64_t        m_req_frame_dma_addr;
 789         caddr_t         m_reply_frame;
 790         uint64_t        m_reply_frame_dma_addr;
 791         caddr_t         m_free_queue;
 792         uint64_t        m_free_queue_dma_addr;
 793         caddr_t         m_post_queue;
 794         uint64_t        m_post_queue_dma_addr;
 795 
 796         m_replyh_arg_t *m_replyh_args;
 797 
 798         uint16_t        m_max_requests;
 799         uint16_t        m_req_frame_size;
 800 
 801         /*
 802          * Max frames per request reprted in IOC Facts
 803          */
 804         uint8_t         m_max_chain_depth;
 805         /*
 806          * Max frames per request which is used in reality. It's adjusted
 807          * according DMA SG length attribute, and shall not exceed the
 808          * m_max_chain_depth.
 809          */
 810         uint8_t         m_max_request_frames;
 811 
 812         uint16_t        m_free_queue_depth;
 813         uint16_t        m_post_queue_depth;
 814         uint16_t        m_max_replies;
 815         uint32_t        m_free_index;
 816         uint32_t        m_post_index;
 817         uint8_t         m_reply_frame_size;
 818         uint32_t        m_ioc_capabilities;
 819 
 820         /*
 821          * indicates if the firmware was upload by the driver
 822          * at boot time
 823          */
 824         ushort_t        m_fwupload;
 825 
 826         uint16_t        m_productid;
 827 
 828         /*
 829          * per instance data structures for dma memory resources for
 830          * MPI handshake protocol. only one handshake cmd can run at a time.
 831          */
 832         ddi_dma_handle_t        m_hshk_dma_hdl;
 833         ddi_acc_handle_t        m_hshk_acc_hdl;
 834         caddr_t                 m_hshk_memp;
 835         size_t                  m_hshk_dma_size;
 836 
 837         /* Firmware version on the card at boot time */
 838         uint32_t                m_fwversion;
 839 
 840         /* MSI specific fields */
 841         ddi_intr_handle_t       *m_htable;      /* For array of interrupts */
 842         int                     m_intr_type;    /* What type of interrupt */
 843         int                     m_intr_cnt;     /* # of intrs count returned */
 844         size_t                  m_intr_size;    /* Size of intr array */
 845         uint_t                  m_intr_pri;     /* Interrupt priority   */
 846         int                     m_intr_cap;     /* Interrupt capabilities */
 847         ddi_taskq_t             *m_event_taskq;
 848 
 849         /* SAS specific information */
 850 
 851         union {
 852                 uint64_t        m_base_wwid;    /* Base WWID */
 853                 struct {
 854 #ifdef _BIG_ENDIAN
 855                         uint32_t        m_base_wwid_hi;
 856                         uint32_t        m_base_wwid_lo;
 857 #else
 858                         uint32_t        m_base_wwid_lo;
 859                         uint32_t        m_base_wwid_hi;
 860 #endif
 861                 } sasaddr;
 862         } un;
 863 
 864         uint8_t                 m_num_phys;             /* # of PHYs */
 865         mptsas_phy_info_t       m_phy_info[MPTSAS_MAX_PHYS];
 866         uint8_t                 m_port_chng;    /* initiator port changes */
 867         MPI2_CONFIG_PAGE_MAN_0   m_MANU_page0;   /* Manufactor page 0 info */
 868         MPI2_CONFIG_PAGE_MAN_1   m_MANU_page1;   /* Manufactor page 1 info */
 869 
 870         /* FMA Capabilities */
 871         int                     m_fm_capabilities;
 872         ddi_taskq_t             *m_dr_taskq;
 873         int                     m_mpxio_enable;
 874         uint8_t                 m_done_traverse_dev;
 875         uint8_t                 m_done_traverse_smp;
 876         int                     m_diag_action_in_progress;
 877         uint16_t                m_dev_handle;
 878         uint16_t                m_smp_devhdl;
 879 
 880         /*
 881          * Event recording
 882          */
 883         uint8_t                 m_event_index;
 884         uint32_t                m_event_number;
 885         uint32_t                m_event_mask[4];
 886         mptsas_event_entry_t    m_events[MPTSAS_EVENT_QUEUE_SIZE];
 887 
 888         /*
 889          * FW diag Buffer List
 890          */
 891         mptsas_fw_diagnostic_buffer_t
 892                 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
 893 
 894         /*
 895          * Event Replay flag (MUR support)
 896          */
 897         uint8_t                 m_event_replay;
 898 
 899         /*
 900          * IR Capable flag
 901          */
 902         uint8_t                 m_ir_capable;
 903 
 904         /*
 905          * Is HBA processing a diag reset?
 906          */
 907         uint8_t                 m_in_reset;
 908 
 909         /*
 910          * per instance cmd data structures for task management cmds
 911          */
 912         m_event_struct_t        m_event_task_mgmt;      /* must be last */
 913                                                         /* ... scsi_pkt_size */
 914 } mptsas_t;
 915 #define MPTSAS_SIZE     (sizeof (struct mptsas) - \
 916                         sizeof (struct scsi_pkt) + scsi_pkt_size())
 917 /*
 918  * Only one of below two conditions is satisfied, we
 919  * think the target is associated to the iport and
 920  * allow call into mptsas_probe_lun().
 921  * 1. physicalsport == physport
 922  * 2. (phymask & (1 << physport)) == 0
 923  * The condition #2 is because LSI uses lowest PHY
 924  * number as the value of physical port when auto port
 925  * configuration.
 926  */
 927 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
 928         ((physicalport == physport) || (dynamicport && (phymask & \
 929         (1 << physport))))
 930 
 931 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
 932 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
 933 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
 934 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
 935 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
 936 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
 937 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
 938 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type))
 939 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
 940 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets))
 941 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
 942 
 943 /*
 944  * These should eventually migrate into the mpt header files
 945  * that may become the /kernel/misc/mpt module...
 946  */
 947 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
 948         mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
 949         mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
 950         mptsas_put_msg_Function(hdl, mp, Function); \
 951         mptsas_put_msg_Lun(hdl, mp, Lun)
 952 
 953 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
 954         ddi_put16(hdl, &(mp)->DevHandle, (val))
 955 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
 956         ddi_put8(hdl, &(mp)->ChainOffset, (val))
 957 #define mptsas_put_msg_Function(hdl, mp, val) \
 958         ddi_put8(hdl, &(mp)->Function, (val))
 959 #define mptsas_put_msg_Lun(hdl, mp, val) \
 960         ddi_put8(hdl, &(mp)->LUN[1], (val))
 961 
 962 #define mptsas_get_msg_Function(hdl, mp) \
 963         ddi_get8(hdl, &(mp)->Function)
 964 
 965 #define mptsas_get_msg_MsgFlags(hdl, mp) \
 966         ddi_get8(hdl, &(mp)->MsgFlags)
 967 
 968 #define MPTSAS_ENABLE_DRWE(hdl) \
 969         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
 970                 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
 971         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
 972                 MPI2_WRSEQ_1ST_KEY_VALUE); \
 973         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
 974                 MPI2_WRSEQ_2ND_KEY_VALUE); \
 975         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
 976                 MPI2_WRSEQ_3RD_KEY_VALUE); \
 977         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
 978                 MPI2_WRSEQ_4TH_KEY_VALUE); \
 979         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
 980                 MPI2_WRSEQ_5TH_KEY_VALUE); \
 981         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
 982                 MPI2_WRSEQ_6TH_KEY_VALUE);
 983 
 984 /*
 985  * m_options flags
 986  */
 987 #define MPTSAS_OPT_PM           0x01    /* Power Management */
 988 
 989 /*
 990  * m_softstate flags
 991  */
 992 #define MPTSAS_SS_DRAINING              0x02
 993 #define MPTSAS_SS_QUIESCED              0x04
 994 #define MPTSAS_SS_MSG_UNIT_RESET        0x08
 995 #define MPTSAS_DID_MSG_UNIT_RESET       0x10
 996 
 997 /*
 998  * regspec defines.
 999  */
1000 #define CONFIG_SPACE    0       /* regset[0] - configuration space */
1001 #define IO_SPACE        1       /* regset[1] - used for i/o mapped device */
1002 #define MEM_SPACE       2       /* regset[2] - used for memory mapped device */
1003 #define BASE_REG2       3       /* regset[3] - used for 875 scripts ram */
1004 
1005 /*
1006  * Handy constants
1007  */
1008 #define FALSE           0
1009 #define TRUE            1
1010 #define UNDEFINED       -1
1011 #define FAILED          -2
1012 
1013 /*
1014  * power management.
1015  */
1016 #define MPTSAS_POWER_ON(mpt) { \
1017         pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1018             PCI_PMCSR_D0); \
1019         delay(drv_usectohz(10000)); \
1020         (void) pci_restore_config_regs(mpt->m_dip); \
1021         mptsas_setup_cmd_reg(mpt); \
1022 }
1023 
1024 #define MPTSAS_POWER_OFF(mpt) { \
1025         (void) pci_save_config_regs(mpt->m_dip); \
1026         pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1027             PCI_PMCSR_D3HOT); \
1028         mpt->m_power_level = PM_LEVEL_D3; \
1029 }
1030 
1031 /*
1032  * inq_dtype:
1033  * Bits 5 through 7 are the Peripheral Device Qualifier
1034  * 001b: device not connected to the LUN
1035  * Bits 0 through 4 are the Peripheral Device Type
1036  * 1fh: Unknown or no device type
1037  *
1038  * Although the inquiry may return success, the following value
1039  * means no valid LUN connected.
1040  */
1041 #define MPTSAS_VALID_LUN(sd_inq) \
1042         (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1043         ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1044 
1045 /*
1046  * Default is to have 10 retries on receiving QFULL status and
1047  * each retry to be after 100 ms.
1048  */
1049 #define QFULL_RETRIES           10
1050 #define QFULL_RETRY_INTERVAL    100
1051 
1052 /*
1053  * Handy macros
1054  */
1055 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1056 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1057 
1058 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1059         ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1060 
1061 /*
1062  * poll time for mptsas_pollret() and mptsas_wait_intr()
1063  */
1064 #define MPTSAS_POLL_TIME        30000   /* 30 seconds */
1065 
1066 /*
1067  * default time for mptsas_do_passthru
1068  */
1069 #define MPTSAS_PASS_THRU_TIME_DEFAULT   60      /* 60 seconds */
1070 
1071 /*
1072  * macro to return the effective address of a given per-target field
1073  */
1074 #define EFF_ADDR(start, offset)         ((start) + (offset))
1075 
1076 #define SDEV2ADDR(devp)         (&((devp)->sd_address))
1077 #define SDEV2TRAN(devp)         ((devp)->sd_address.a_hba_tran)
1078 #define PKT2TRAN(pkt)           ((pkt)->pkt_address.a_hba_tran)
1079 #define ADDR2TRAN(ap)           ((ap)->a_hba_tran)
1080 #define DIP2TRAN(dip)           (ddi_get_driver_private(dip))
1081 
1082 
1083 #define TRAN2MPT(hba)           ((mptsas_t *)(hba)->tran_hba_private)
1084 #define DIP2MPT(dip)            (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1085 #define SDEV2MPT(sd)            (TRAN2MPT(SDEV2TRAN(sd)))
1086 #define PKT2MPT(pkt)            (TRAN2MPT(PKT2TRAN(pkt)))
1087 
1088 #define ADDR2MPT(ap)            (TRAN2MPT(ADDR2TRAN(ap)))
1089 
1090 #define POLL_TIMEOUT            (2 * SCSI_POLL_TIMEOUT * 1000000)
1091 #define SHORT_POLL_TIMEOUT      (1000000)       /* in usec, about 1 secs */
1092 #define MPTSAS_QUIESCE_TIMEOUT  1               /* 1 sec */
1093 #define MPTSAS_PM_IDLE_TIMEOUT  60              /* 60 seconds */
1094 
1095 #define MPTSAS_GET_ISTAT(mpt)  (ddi_get32((mpt)->m_datap, \
1096                         &(mpt)->m_reg->HostInterruptStatus))
1097 
1098 #define MPTSAS_SET_SIGP(P) \
1099                 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1100 
1101 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1102                         (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1103 
1104 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1105                         (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1106 
1107 
1108 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \
1109         ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\
1110             req_desc_lo);\
1111         ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\
1112             req_desc_hi);
1113 
1114 #define INTPENDING(mpt) \
1115         (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1116 
1117 /*
1118  * Mask all interrupts to disable
1119  */
1120 #define MPTSAS_DISABLE_INTR(mpt)        \
1121         ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1122             (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1123 
1124 /*
1125  * Mask Doorbell and Reset interrupts to enable reply desc int.
1126  */
1127 #define MPTSAS_ENABLE_INTR(mpt) \
1128         ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1129         (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1130 
1131 #define MPTSAS_GET_NEXT_REPLY(mpt, index)  \
1132         &((uint64_t *)(void *)mpt->m_post_queue)[index]
1133 
1134 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1135         (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1136 
1137 #define ClrSetBits32(hdl, reg, clr, set) \
1138         ddi_put32(hdl, (reg), \
1139             ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1140 
1141 #define ClrSetBits(reg, clr, set) \
1142         ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1143                 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1144 
1145 #define MPTSAS_WAITQ_RM(mpt, cmdp)      \
1146         if ((cmdp = mpt->m_waitq) != NULL) { \
1147                 /* If the queue is now empty fix the tail pointer */    \
1148                 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1149                         mpt->m_waitqtail = &mpt->m_waitq; \
1150                 cmdp->cmd_linkp = NULL; \
1151                 cmdp->cmd_queued = FALSE; \
1152         }
1153 
1154 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp)   \
1155         if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1156                 /* If the queue is now empty fix the tail pointer */    \
1157                 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1158                         mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1159                 cmdp->cmd_linkp = NULL; \
1160                 cmdp->cmd_queued = FALSE; \
1161         }
1162 
1163 /*
1164  * defaults for the global properties
1165  */
1166 #define DEFAULT_SCSI_OPTIONS    SCSI_OPTIONS_DR
1167 #define DEFAULT_TAG_AGE_LIMIT   2
1168 #define DEFAULT_WD_TICK         10
1169 
1170 /*
1171  * invalid hostid.
1172  */
1173 #define MPTSAS_INVALID_HOSTID  -1
1174 
1175 /*
1176  * Get/Set hostid from SCSI port configuration page
1177  */
1178 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1179 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1180 
1181 /*
1182  * Config space.
1183  */
1184 #define MPTSAS_LATENCY_TIMER    0x40
1185 
1186 /*
1187  * Offset to firmware version
1188  */
1189 #define MPTSAS_FW_VERSION_OFFSET        9
1190 
1191 /*
1192  * Offset and masks to get at the ProductId field
1193  */
1194 #define MPTSAS_FW_PRODUCTID_OFFSET      8
1195 #define MPTSAS_FW_PRODUCTID_MASK        0xFFFF0000
1196 #define MPTSAS_FW_PRODUCTID_SHIFT       16
1197 
1198 /*
1199  * Subsystem ID for HBAs.
1200  */
1201 #define MPTSAS_HBA_SUBSYSTEM_ID    0x10C0
1202 #define MPTSAS_RHEA_SUBSYSTEM_ID        0x10B0
1203 
1204 /*
1205  * reset delay tick
1206  */
1207 #define MPTSAS_WATCH_RESET_DELAY_TICK 50        /* specified in milli seconds */
1208 
1209 /*
1210  * Ioc reset return values
1211  */
1212 #define MPTSAS_RESET_FAIL       -1
1213 #define MPTSAS_NO_RESET         0
1214 #define MPTSAS_SUCCESS_HARDRESET        1
1215 #define MPTSAS_SUCCESS_MUR      2
1216 
1217 /*
1218  * throttle support.
1219  */
1220 #define MAX_THROTTLE    32
1221 #define HOLD_THROTTLE   0
1222 #define DRAIN_THROTTLE  -1
1223 #define QFULL_THROTTLE  -2
1224 
1225 /*
1226  * Passthrough/config request flags
1227  */
1228 #define MPTSAS_DATA_ALLOCATED           0x0001
1229 #define MPTSAS_DATAOUT_ALLOCATED        0x0002
1230 #define MPTSAS_REQUEST_POOL_CMD         0x0004
1231 #define MPTSAS_ADDRESS_REPLY            0x0008
1232 #define MPTSAS_CMD_TIMEOUT              0x0010
1233 
1234 /*
1235  * response code tlr flag
1236  */
1237 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF       0x02
1238 
1239 /*
1240  * System Events
1241  */
1242 #ifndef DDI_VENDOR_LSI
1243 #define DDI_VENDOR_LSI  "LSI"
1244 #endif  /* DDI_VENDOR_LSI */
1245 
1246 /*
1247  * Shared functions
1248  */
1249 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1250 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1251 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1252 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1253 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1254 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1255 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1256         uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1257         uint8_t pageversion, uint8_t pagelength, uint32_t
1258         SGEflagslength, uint32_t SGEaddress32);
1259 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1260         uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1261         uint8_t pageversion, uint16_t extpagelength,
1262         uint32_t SGEflagslength, uint32_t SGEaddress32);
1263 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1264         uint8_t type, int mode);
1265 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1266         uint8_t type, int mode);
1267 int mptsas_download_firmware();
1268 int mptsas_can_download_firmware();
1269 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1270 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1271 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1272 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1273 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1274 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1275 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1276 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1277     ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1278     uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1279 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1280 
1281 /*
1282  * impl functions
1283  */
1284 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1285 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1286 int mptsas_ioc_reset(mptsas_t *mpt, int);
1287 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1288     ddi_acc_handle_t accessp);
1289 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1290     ddi_acc_handle_t accessp);
1291 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1292     uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1293     uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1294     uint32_t SGEaddress32);
1295 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1296     uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1297     uint8_t pageversion, uint16_t extpagelength,
1298     uint32_t SGEflagslength, uint32_t SGEaddress32);
1299 
1300 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1301     struct scsi_pkt **pkt);
1302 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1303 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1304 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
1305 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1306     uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1307     caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1308 
1309 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1310     uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1311     int mode);
1312 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1313 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1314 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1315 int mptsas_restart_ioc(mptsas_t *mpt);
1316 void mptsas_update_driver_data(struct mptsas *mpt);
1317 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1318 
1319 /*
1320  * init functions
1321  */
1322 int mptsas_ioc_get_facts(mptsas_t *mpt);
1323 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1324 int mptsas_ioc_enable_port(mptsas_t *mpt);
1325 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1326 int mptsas_ioc_init(mptsas_t *mpt);
1327 
1328 /*
1329  * configuration pages operation
1330  */
1331 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1332     uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1333     uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1334     uint16_t *slot_num, uint16_t *enclosure);
1335 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1336 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1337 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1338     mptsas_smp_t *info);
1339 int mptsas_set_ioc_params(mptsas_t *mpt);
1340 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1341 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1342     uint64_t *sas_wwn, uint8_t *portwidth);
1343 int mptsas_get_bios_page3(mptsas_t *mpt,  uint32_t *bios_version);
1344 int
1345 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1346     smhba_info_t *info);
1347 int
1348 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1349     smhba_info_t *info);
1350 int
1351 mptsas_get_manufacture_page0(mptsas_t *mpt);
1352 void
1353 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1354 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1355 int mptsas_smhba_phy_init(mptsas_t *mpt);
1356 /*
1357  * RAID functions
1358  */
1359 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1360 int mptsas_get_raid_info(mptsas_t *mpt);
1361 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1362     uint8_t physdisknum);
1363 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1364 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1365 
1366 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1367 /*
1368  * debugging.
1369  */
1370 #if defined(MPTSAS_DEBUG)
1371 
1372 void mptsas_printf(char *fmt, ...);
1373 
1374 #define MPTSAS_DBGPR(m, args)   \
1375         if (mptsas_debug_flags & (m)) \
1376                 mptsas_printf args
1377 #else   /* ! defined(MPTSAS_DEBUG) */
1378 #define MPTSAS_DBGPR(m, args)
1379 #endif  /* defined(MPTSAS_DEBUG) */
1380 
1381 #define NDBG0(args)     MPTSAS_DBGPR(0x01, args)        /* init */
1382 #define NDBG1(args)     MPTSAS_DBGPR(0x02, args)        /* normal running */
1383 #define NDBG2(args)     MPTSAS_DBGPR(0x04, args)        /* property handling */
1384 #define NDBG3(args)     MPTSAS_DBGPR(0x08, args)        /* pkt handling */
1385 
1386 #define NDBG4(args)     MPTSAS_DBGPR(0x10, args)        /* kmem alloc/free */
1387 #define NDBG5(args)     MPTSAS_DBGPR(0x20, args)        /* polled cmds */
1388 #define NDBG6(args)     MPTSAS_DBGPR(0x40, args)        /* interrupts */
1389 #define NDBG7(args)     MPTSAS_DBGPR(0x80, args)        /* queue handling */
1390 
1391 #define NDBG8(args)     MPTSAS_DBGPR(0x0100, args)      /* arq */
1392 #define NDBG9(args)     MPTSAS_DBGPR(0x0200, args)      /* Tagged Q'ing */
1393 #define NDBG10(args)    MPTSAS_DBGPR(0x0400, args)      /* halting chip */
1394 #define NDBG11(args)    MPTSAS_DBGPR(0x0800, args)      /* power management */
1395 
1396 #define NDBG12(args)    MPTSAS_DBGPR(0x1000, args)      /* enumeration */
1397 #define NDBG13(args)    MPTSAS_DBGPR(0x2000, args)      /* configuration page */
1398 #define NDBG14(args)    MPTSAS_DBGPR(0x4000, args)      /* LED control */
1399 #define NDBG15(args)    MPTSAS_DBGPR(0x8000, args)
1400 
1401 #define NDBG16(args)    MPTSAS_DBGPR(0x010000, args)
1402 #define NDBG17(args)    MPTSAS_DBGPR(0x020000, args)    /* scatter/gather */
1403 #define NDBG18(args)    MPTSAS_DBGPR(0x040000, args)
1404 #define NDBG19(args)    MPTSAS_DBGPR(0x080000, args)    /* handshaking */
1405 
1406 #define NDBG20(args)    MPTSAS_DBGPR(0x100000, args)    /* events */
1407 #define NDBG21(args)    MPTSAS_DBGPR(0x200000, args)    /* dma */
1408 #define NDBG22(args)    MPTSAS_DBGPR(0x400000, args)    /* reset */
1409 #define NDBG23(args)    MPTSAS_DBGPR(0x800000, args)    /* abort */
1410 
1411 #define NDBG24(args)    MPTSAS_DBGPR(0x1000000, args)   /* capabilities */
1412 #define NDBG25(args)    MPTSAS_DBGPR(0x2000000, args)   /* flushing */
1413 #define NDBG26(args)    MPTSAS_DBGPR(0x4000000, args)
1414 #define NDBG27(args)    MPTSAS_DBGPR(0x8000000, args)
1415 
1416 #define NDBG28(args)    MPTSAS_DBGPR(0x10000000, args)  /* hotplug */
1417 #define NDBG29(args)    MPTSAS_DBGPR(0x20000000, args)  /* timeouts */
1418 #define NDBG30(args)    MPTSAS_DBGPR(0x40000000, args)  /* mptsas_watch */
1419 #define NDBG31(args)    MPTSAS_DBGPR(0x80000000, args)  /* negotations */
1420 
1421 /*
1422  * auto request sense
1423  */
1424 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1425         (pkt)->pkt_flags = (flag), \
1426         ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1427         ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1428             (pkt)->pkt_address.a_lun
1429 
1430 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1431         RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1432         FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1433         FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1434 
1435 
1436 #ifdef  __cplusplus
1437 }
1438 #endif
1439 
1440 #endif  /* _SYS_SCSI_ADAPTERS_MPTVAR_H */