Print this page
Initial modifications using the code changes present between
the LSI source code for FreeBSD drivers. Specifically the changes
between from mpslsi-source-17.00.00.00 -> mpslsi-source-03.00.00.00.
This mainly involves using a different scatter/gather element in
frame setup.
Split |
Close |
Expand all |
Collapse all |
--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas3/mpi/mpi2_ioc.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas3/mpi/mpi2_ioc.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
↓ open down ↓ |
12 lines elided |
↑ open up ↑ |
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 - * Copyright (c) 2000 to 2009, LSI Corporation.
24 - * All rights reserved.
23 + * Copyright (c) 2000-2012 LSI Corporation.
25 24 *
26 25 * Redistribution and use in source and binary forms of all code within
27 26 * this file that is exclusively owned by LSI, with or without
28 27 * modification, is permitted provided that, in addition to the CDDL 1.0
29 28 * License requirements, the following conditions are met:
30 29 *
31 30 * Neither the name of the author nor the names of its contributors may be
32 31 * used to endorse or promote products derived from this software without
33 32 * specific prior written permission.
34 33 *
35 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
38 37 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
39 38 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
40 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
41 40 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
42 41 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
43 42 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
↓ open down ↓ |
9 lines elided |
↑ open up ↑ |
44 43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
45 44 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46 45 * DAMAGE.
47 46 */
48 47
49 48 /*
50 49 * Name: mpi2_ioc.h
51 50 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
52 51 * Creation Date: October 11, 2006
53 52 *
54 - * mpi2_ioc.h Version: 02.00.12
53 + * mpi2_ioc.h Version: 02.00.xx
54 + *
55 + * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
56 + * prefix are for use only on MPI v2.5 products, and must not be used
57 + * with MPI v2.0 products. Unless otherwise noted, names beginning with
58 + * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
55 59 *
56 60 * Version History
57 61 * ---------------
58 62 *
59 63 * Date Version Description
60 64 * -------- -------- ------------------------------------------------------
61 65 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
62 66 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
63 67 * MaxTargets.
64 68 * Added TotalImageSize field to FWDownload Request.
65 69 * Added reserved words to FWUpload Request.
66 70 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
67 71 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
68 72 * request and replaced it with
69 73 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
70 74 * Replaced the MinReplyQueueDepth field of the IOCFacts
71 75 * reply with MaxReplyDescriptorPostQueueDepth.
72 76 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
73 77 * depth for the Reply Descriptor Post Queue.
74 78 * Added SASAddress field to Initiator Device Table
75 79 * Overflow Event data.
76 80 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
77 81 * for SAS Initiator Device Status Change Event data.
78 82 * Modified Reason Code defines for SAS Topology Change
79 83 * List Event data, including adding a bit for PHY Vacant
80 84 * status, and adding a mask for the Reason Code.
81 85 * Added define for
82 86 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
83 87 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
84 88 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
85 89 * the IOCFacts Reply.
86 90 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
87 91 * Moved MPI2_VERSION_UNION to mpi2.h.
88 92 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
89 93 * instead of enables, and added SASBroadcastPrimitiveMasks
90 94 * field.
91 95 * Added Log Entry Added Event and related structure.
92 96 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
93 97 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
94 98 * Added MaxVolumes and MaxPersistentEntries fields to
95 99 * IOCFacts reply.
96 100 * Added ProtocalFlags and IOCCapabilities fields to
97 101 * MPI2_FW_IMAGE_HEADER.
98 102 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
99 103 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
100 104 * a U16 (from a U32).
101 105 * Removed extra 's' from EventMasks name.
102 106 * 06-27-08 02.00.08 Fixed an offset in a comment.
103 107 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
104 108 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
105 109 * renamed MinReplyFrameSize to ReplyFrameSize.
106 110 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
107 111 * Added two new RAIDOperation values for Integrated RAID
108 112 * Operations Status Event data.
109 113 * Added four new IR Configuration Change List Event data
110 114 * ReasonCode values.
111 115 * Added two new ReasonCode defines for SAS Device Status
112 116 * Change Event data.
113 117 * Added three new DiscoveryStatus bits for the SAS
114 118 * Discovery event data.
115 119 * Added Multiplexing Status Change bit to the PhyStatus
116 120 * field of the SAS Topology Change List event data.
117 121 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
118 122 * BootFlags are now product-specific.
119 123 * Added defines for the indivdual signature bytes
120 124 * for MPI2_INIT_IMAGE_FOOTER.
121 125 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
122 126 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
123 127 * define.
124 128 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
↓ open down ↓ |
60 lines elided |
↑ open up ↑ |
125 129 * define.
126 130 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
127 131 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
128 132 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
129 133 * Added two new reason codes for SAS Device Status Change
130 134 * Event.
131 135 * Added new event: SAS PHY Counter.
132 136 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
133 137 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
134 138 * Added new product id family for 2208.
139 + * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
140 + * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
141 + * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
142 + * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
143 + * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
144 + * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
145 + * Added Host Based Discovery Phy Event data.
146 + * Added defines for ProductID Product field
147 + * (MPI2_FW_HEADER_PID_).
148 + * Modified values for SAS ProductID Family
149 + * (MPI2_FW_HEADER_PID_FAMILY_).
150 + * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
151 + * Added PowerManagementControl Request structures and
152 + * defines.
153 + * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
154 + * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
155 + * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
135 156 * --------------------------------------------------------------------------
136 157 */
137 158
138 159 #ifndef MPI2_IOC_H
139 160 #define MPI2_IOC_H
140 161
141 162 /*****************************************************************************
142 163 *
143 164 * IOC Messages
144 165 *
145 166 *****************************************************************************/
146 167
147 168 /****************************************************************************
148 169 * IOCInit message
149 170 ****************************************************************************/
150 171
151 172 /* IOCInit Request message */
152 173 typedef struct _MPI2_IOC_INIT_REQUEST
153 174 {
154 175 U8 WhoInit; /* 0x00 */
155 176 U8 Reserved1; /* 0x01 */
156 177 U8 ChainOffset; /* 0x02 */
↓ open down ↓ |
12 lines elided |
↑ open up ↑ |
157 178 U8 Function; /* 0x03 */
158 179 U16 Reserved2; /* 0x04 */
159 180 U8 Reserved3; /* 0x06 */
160 181 U8 MsgFlags; /* 0x07 */
161 182 U8 VP_ID; /* 0x08 */
162 183 U8 VF_ID; /* 0x09 */
163 184 U16 Reserved4; /* 0x0A */
164 185 U16 MsgVersion; /* 0x0C */
165 186 U16 HeaderVersion; /* 0x0E */
166 187 U32 Reserved5; /* 0x10 */
167 - U32 Reserved6; /* 0x14 */
168 - U16 Reserved7; /* 0x18 */
188 + U16 Reserved6; /* 0x14 */
189 + U8 Reserved7; /* 0x16 */
190 + U8 HostMSIxVectors; /* 0x17 */
191 + U16 Reserved8; /* 0x18 */
169 192 U16 SystemRequestFrameSize; /* 0x1A */
170 193 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
171 194 U16 ReplyFreeQueueDepth; /* 0x1E */
172 195 U32 SenseBufferAddressHigh; /* 0x20 */
173 196 U32 SystemReplyAddressHigh; /* 0x24 */
174 197 U64 SystemRequestFrameBaseAddress; /* 0x28 */
175 198 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
176 199 U64 ReplyFreeQueueAddress; /* 0x38 */
177 200 U64 TimeStamp; /* 0x40 */
178 201 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
179 202 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
180 203
181 204 /* WhoInit values */
182 205 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
183 206 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
184 207 #define MPI2_WHOINIT_ROM_BIOS (0x02)
185 208 #define MPI2_WHOINIT_PCI_PEER (0x03)
186 209 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
187 210 #define MPI2_WHOINIT_MANUFACTURER (0x05)
188 211
189 212 /* MsgVersion */
190 213 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
191 214 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
192 215 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
193 216 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
194 217
195 218 /* HeaderVersion */
196 219 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
197 220 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
198 221 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
199 222 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
200 223
201 224 /* minimum depth for the Reply Descriptor Post Queue */
202 225 #define MPI2_RDPQ_DEPTH_MIN (16)
203 226
204 227
205 228 /* IOCInit Reply message */
206 229 typedef struct _MPI2_IOC_INIT_REPLY
207 230 {
208 231 U8 WhoInit; /* 0x00 */
209 232 U8 Reserved1; /* 0x01 */
210 233 U8 MsgLength; /* 0x02 */
211 234 U8 Function; /* 0x03 */
212 235 U16 Reserved2; /* 0x04 */
213 236 U8 Reserved3; /* 0x06 */
214 237 U8 MsgFlags; /* 0x07 */
215 238 U8 VP_ID; /* 0x08 */
216 239 U8 VF_ID; /* 0x09 */
217 240 U16 Reserved4; /* 0x0A */
218 241 U16 Reserved5; /* 0x0C */
219 242 U16 IOCStatus; /* 0x0E */
220 243 U32 IOCLogInfo; /* 0x10 */
221 244 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
222 245 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
223 246
224 247
225 248 /****************************************************************************
226 249 * IOCFacts message
227 250 ****************************************************************************/
228 251
229 252 /* IOCFacts Request message */
230 253 typedef struct _MPI2_IOC_FACTS_REQUEST
231 254 {
232 255 U16 Reserved1; /* 0x00 */
233 256 U8 ChainOffset; /* 0x02 */
234 257 U8 Function; /* 0x03 */
235 258 U16 Reserved2; /* 0x04 */
236 259 U8 Reserved3; /* 0x06 */
237 260 U8 MsgFlags; /* 0x07 */
238 261 U8 VP_ID; /* 0x08 */
239 262 U8 VF_ID; /* 0x09 */
240 263 U16 Reserved4; /* 0x0A */
241 264 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
242 265 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
243 266
244 267
245 268 /* IOCFacts Reply message */
246 269 typedef struct _MPI2_IOC_FACTS_REPLY
247 270 {
248 271 U16 MsgVersion; /* 0x00 */
249 272 U8 MsgLength; /* 0x02 */
250 273 U8 Function; /* 0x03 */
251 274 U16 HeaderVersion; /* 0x04 */
252 275 U8 IOCNumber; /* 0x06 */
↓ open down ↓ |
74 lines elided |
↑ open up ↑ |
253 276 U8 MsgFlags; /* 0x07 */
254 277 U8 VP_ID; /* 0x08 */
255 278 U8 VF_ID; /* 0x09 */
256 279 U16 Reserved1; /* 0x0A */
257 280 U16 IOCExceptions; /* 0x0C */
258 281 U16 IOCStatus; /* 0x0E */
259 282 U32 IOCLogInfo; /* 0x10 */
260 283 U8 MaxChainDepth; /* 0x14 */
261 284 U8 WhoInit; /* 0x15 */
262 285 U8 NumberOfPorts; /* 0x16 */
263 - U8 Reserved2; /* 0x17 */
286 + U8 MaxMSIxVectors; /* 0x17 */
264 287 U16 RequestCredit; /* 0x18 */
265 288 U16 ProductID; /* 0x1A */
266 289 U32 IOCCapabilities; /* 0x1C */
267 290 MPI2_VERSION_UNION FWVersion; /* 0x20 */
268 291 U16 IOCRequestFrameSize; /* 0x24 */
269 292 U16 Reserved3; /* 0x26 */
270 293 U16 MaxInitiators; /* 0x28 */
271 294 U16 MaxTargets; /* 0x2A */
272 295 U16 MaxSasExpanders; /* 0x2C */
273 296 U16 MaxEnclosures; /* 0x2E */
274 297 U16 ProtocolFlags; /* 0x30 */
275 298 U16 HighPriorityCredit; /* 0x32 */
276 299 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
277 300 U8 ReplyFrameSize; /* 0x36 */
278 301 U8 MaxVolumes; /* 0x37 */
279 302 U16 MaxDevHandle; /* 0x38 */
280 303 U16 MaxPersistentEntries; /* 0x3A */
281 - U32 Reserved4; /* 0x3C */
304 + U16 MinDevHandle; /* 0x3C */
305 + U16 Reserved4; /* 0x3E */
282 306 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
283 307 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
284 308
285 309 /* MsgVersion */
286 310 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
287 311 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
288 312 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
289 313 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
290 314
291 315 /* HeaderVersion */
292 316 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
293 317 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
294 318 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
295 319 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
296 320
297 321 /* IOCExceptions */
298 322 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
299 323
300 324 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
301 325 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
302 326 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
303 327 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
304 328 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
305 329
306 330 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
↓ open down ↓ |
15 lines elided |
↑ open up ↑ |
307 331 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
308 332 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
309 333 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
310 334 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
311 335
312 336 /* defines for WhoInit field are after the IOCInit Request */
313 337
314 338 /* ProductID field uses MPI2_FW_HEADER_PID_ */
315 339
316 340 /* IOCCapabilities */
341 +#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
342 +#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
317 343 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
318 344 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
319 345 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
320 346 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
321 347 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
322 348 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
323 349 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
324 350 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
325 351 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
326 352 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
327 353 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
328 354 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
329 355
330 356 /* ProtocolFlags */
331 357 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
332 358 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
333 359
334 360
335 361 /****************************************************************************
336 362 * PortFacts message
337 363 ****************************************************************************/
338 364
339 365 /* PortFacts Request message */
340 366 typedef struct _MPI2_PORT_FACTS_REQUEST
341 367 {
342 368 U16 Reserved1; /* 0x00 */
343 369 U8 ChainOffset; /* 0x02 */
344 370 U8 Function; /* 0x03 */
345 371 U16 Reserved2; /* 0x04 */
346 372 U8 PortNumber; /* 0x06 */
347 373 U8 MsgFlags; /* 0x07 */
348 374 U8 VP_ID; /* 0x08 */
349 375 U8 VF_ID; /* 0x09 */
350 376 U16 Reserved3; /* 0x0A */
351 377 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
352 378 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
353 379
354 380 /* PortFacts Reply message */
355 381 typedef struct _MPI2_PORT_FACTS_REPLY
356 382 {
357 383 U16 Reserved1; /* 0x00 */
358 384 U8 MsgLength; /* 0x02 */
359 385 U8 Function; /* 0x03 */
360 386 U16 Reserved2; /* 0x04 */
361 387 U8 PortNumber; /* 0x06 */
362 388 U8 MsgFlags; /* 0x07 */
363 389 U8 VP_ID; /* 0x08 */
364 390 U8 VF_ID; /* 0x09 */
365 391 U16 Reserved3; /* 0x0A */
366 392 U16 Reserved4; /* 0x0C */
367 393 U16 IOCStatus; /* 0x0E */
368 394 U32 IOCLogInfo; /* 0x10 */
369 395 U8 Reserved5; /* 0x14 */
370 396 U8 PortType; /* 0x15 */
371 397 U16 Reserved6; /* 0x16 */
372 398 U16 MaxPostedCmdBuffers; /* 0x18 */
373 399 U16 Reserved7; /* 0x1A */
374 400 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
375 401 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
376 402
377 403 /* PortType values */
378 404 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
379 405 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
380 406 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
381 407 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
382 408 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
383 409
384 410
385 411 /****************************************************************************
386 412 * PortEnable message
387 413 ****************************************************************************/
388 414
389 415 /* PortEnable Request message */
390 416 typedef struct _MPI2_PORT_ENABLE_REQUEST
391 417 {
392 418 U16 Reserved1; /* 0x00 */
393 419 U8 ChainOffset; /* 0x02 */
394 420 U8 Function; /* 0x03 */
395 421 U8 Reserved2; /* 0x04 */
396 422 U8 PortFlags; /* 0x05 */
397 423 U8 Reserved3; /* 0x06 */
398 424 U8 MsgFlags; /* 0x07 */
399 425 U8 VP_ID; /* 0x08 */
400 426 U8 VF_ID; /* 0x09 */
401 427 U16 Reserved4; /* 0x0A */
402 428 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
403 429 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
404 430
405 431
406 432 /* PortEnable Reply message */
407 433 typedef struct _MPI2_PORT_ENABLE_REPLY
408 434 {
409 435 U16 Reserved1; /* 0x00 */
410 436 U8 MsgLength; /* 0x02 */
411 437 U8 Function; /* 0x03 */
412 438 U8 Reserved2; /* 0x04 */
413 439 U8 PortFlags; /* 0x05 */
414 440 U8 Reserved3; /* 0x06 */
415 441 U8 MsgFlags; /* 0x07 */
416 442 U8 VP_ID; /* 0x08 */
417 443 U8 VF_ID; /* 0x09 */
418 444 U16 Reserved4; /* 0x0A */
419 445 U16 Reserved5; /* 0x0C */
420 446 U16 IOCStatus; /* 0x0E */
421 447 U32 IOCLogInfo; /* 0x10 */
422 448 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
423 449 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
424 450
425 451
426 452 /****************************************************************************
427 453 * EventNotification message
428 454 ****************************************************************************/
429 455
430 456 /* EventNotification Request message */
431 457 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
432 458
433 459 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
434 460 {
435 461 U16 Reserved1; /* 0x00 */
436 462 U8 ChainOffset; /* 0x02 */
437 463 U8 Function; /* 0x03 */
438 464 U16 Reserved2; /* 0x04 */
439 465 U8 Reserved3; /* 0x06 */
440 466 U8 MsgFlags; /* 0x07 */
441 467 U8 VP_ID; /* 0x08 */
442 468 U8 VF_ID; /* 0x09 */
443 469 U16 Reserved4; /* 0x0A */
444 470 U32 Reserved5; /* 0x0C */
445 471 U32 Reserved6; /* 0x10 */
446 472 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
447 473 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
448 474 U16 Reserved7; /* 0x26 */
449 475 U32 Reserved8; /* 0x28 */
450 476 } MPI2_EVENT_NOTIFICATION_REQUEST,
451 477 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
452 478 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
453 479
454 480
455 481 /* EventNotification Reply message */
456 482 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
457 483 {
458 484 U16 EventDataLength; /* 0x00 */
459 485 U8 MsgLength; /* 0x02 */
460 486 U8 Function; /* 0x03 */
461 487 U16 Reserved1; /* 0x04 */
462 488 U8 AckRequired; /* 0x06 */
463 489 U8 MsgFlags; /* 0x07 */
464 490 U8 VP_ID; /* 0x08 */
465 491 U8 VF_ID; /* 0x09 */
466 492 U16 Reserved2; /* 0x0A */
467 493 U16 Reserved3; /* 0x0C */
468 494 U16 IOCStatus; /* 0x0E */
469 495 U32 IOCLogInfo; /* 0x10 */
470 496 U16 Event; /* 0x14 */
471 497 U16 Reserved4; /* 0x16 */
472 498 U32 EventContext; /* 0x18 */
473 499 U32 EventData[1]; /* 0x1C */
474 500 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
475 501 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
↓ open down ↓ |
149 lines elided |
↑ open up ↑ |
476 502
477 503 /* AckRequired */
478 504 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
479 505 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
480 506
481 507 /* Event */
482 508 #define MPI2_EVENT_LOG_DATA (0x0001)
483 509 #define MPI2_EVENT_STATE_CHANGE (0x0002)
484 510 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
485 511 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
486 -#define MPI2_EVENT_TASK_SET_FULL (0x000E)
512 +#define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
487 513 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
488 514 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
489 515 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
490 516 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
491 517 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
492 518 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
493 519 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
494 520 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
495 521 #define MPI2_EVENT_IR_VOLUME (0x001E)
496 522 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
497 523 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
498 524 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
499 525 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
500 526 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
527 +#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
528 +#define MPI2_EVENT_SAS_QUIESCE (0x0025)
501 529
502 530
503 531 /* Log Entry Added Event data */
504 532
505 533 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
506 534 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
507 535
508 536 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
509 537 {
510 538 U64 TimeStamp; /* 0x00 */
511 539 U32 Reserved1; /* 0x08 */
512 540 U16 LogSequence; /* 0x0C */
513 541 U16 LogEntryQualifier; /* 0x0E */
514 542 U8 VP_ID; /* 0x10 */
515 543 U8 VF_ID; /* 0x11 */
516 544 U16 Reserved2; /* 0x12 */
517 545 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
518 546 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
519 547 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
520 548 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
521 549
522 550 /* GPIO Interrupt Event data */
523 551
524 552 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
525 553 {
526 554 U8 GPIONum; /* 0x00 */
527 555 U8 Reserved1; /* 0x01 */
528 556 U16 Reserved2; /* 0x02 */
529 557 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
530 558 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
531 559 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
532 560
533 561 /* Hard Reset Received Event data */
534 562
535 563 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
↓ open down ↓ |
25 lines elided |
↑ open up ↑ |
536 564 {
537 565 U8 Reserved1; /* 0x00 */
538 566 U8 Port; /* 0x01 */
539 567 U16 Reserved2; /* 0x02 */
540 568 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
541 569 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
542 570 Mpi2EventDataHardResetReceived_t,
543 571 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
544 572
545 573 /* Task Set Full Event data */
574 +/* this event is obsolete */
546 575
547 576 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
548 577 {
549 578 U16 DevHandle; /* 0x00 */
550 579 U16 CurrentDepth; /* 0x02 */
551 580 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
552 581 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
553 582
554 583
555 584 /* SAS Device Status Change Event data */
556 585
557 586 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
558 587 {
559 588 U16 TaskTag; /* 0x00 */
560 589 U8 ReasonCode; /* 0x02 */
561 590 U8 Reserved1; /* 0x03 */
562 591 U8 ASC; /* 0x04 */
563 592 U8 ASCQ; /* 0x05 */
564 593 U16 DevHandle; /* 0x06 */
565 594 U32 Reserved2; /* 0x08 */
566 595 U64 SASAddress; /* 0x0C */
567 596 U8 LUN[8]; /* 0x14 */
568 597 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
569 598 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
570 599 Mpi2EventDataSasDeviceStatusChange_t,
571 600 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
572 601
573 602 /* SAS Device Status Change Event data ReasonCode values */
574 603 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
575 604 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
576 605 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
577 606 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
578 607 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
579 608 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
580 609 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
581 610 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
582 611 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
583 612 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
584 613 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
585 614 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
586 615 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
587 616
588 617
589 618 /* Integrated RAID Operation Status Event data */
590 619
591 620 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
592 621 {
593 622 U16 VolDevHandle; /* 0x00 */
594 623 U16 Reserved1; /* 0x02 */
595 624 U8 RAIDOperation; /* 0x04 */
596 625 U8 PercentComplete; /* 0x05 */
597 626 U16 Reserved2; /* 0x06 */
598 627 U32 Resereved3; /* 0x08 */
599 628 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
600 629 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
601 630 Mpi2EventDataIrOperationStatus_t,
602 631 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
603 632
604 633 /* Integrated RAID Operation Status Event data RAIDOperation values */
605 634 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
606 635 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
607 636 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
608 637 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
609 638 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
610 639
611 640
612 641 /* Integrated RAID Volume Event data */
613 642
614 643 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
615 644 {
616 645 U16 VolDevHandle; /* 0x00 */
617 646 U8 ReasonCode; /* 0x02 */
618 647 U8 Reserved1; /* 0x03 */
619 648 U32 NewValue; /* 0x04 */
620 649 U32 PreviousValue; /* 0x08 */
621 650 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
622 651 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
623 652
624 653 /* Integrated RAID Volume Event data ReasonCode values */
625 654 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
626 655 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
627 656 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
628 657
629 658
630 659 /* Integrated RAID Physical Disk Event data */
631 660
632 661 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
633 662 {
634 663 U16 Reserved1; /* 0x00 */
635 664 U8 ReasonCode; /* 0x02 */
636 665 U8 PhysDiskNum; /* 0x03 */
637 666 U16 PhysDiskDevHandle; /* 0x04 */
638 667 U16 Reserved2; /* 0x06 */
639 668 U16 Slot; /* 0x08 */
640 669 U16 EnclosureHandle; /* 0x0A */
641 670 U32 NewValue; /* 0x0C */
642 671 U32 PreviousValue; /* 0x10 */
643 672 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
644 673 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
645 674 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
646 675
647 676 /* Integrated RAID Physical Disk Event data ReasonCode values */
648 677 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
649 678 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
650 679 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
651 680
652 681
653 682 /* Integrated RAID Configuration Change List Event data */
654 683
655 684 /*
656 685 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
657 686 * one and check NumElements at runtime.
658 687 */
659 688 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
660 689 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
661 690 #endif
662 691
663 692 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
664 693 {
665 694 U16 ElementFlags; /* 0x00 */
666 695 U16 VolDevHandle; /* 0x02 */
667 696 U8 ReasonCode; /* 0x04 */
668 697 U8 PhysDiskNum; /* 0x05 */
669 698 U16 PhysDiskDevHandle; /* 0x06 */
670 699 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
671 700 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
672 701
673 702 /* IR Configuration Change List Event data ElementFlags values */
674 703 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
675 704 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
676 705 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
677 706 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
678 707
679 708 /* IR Configuration Change List Event data ReasonCode values */
680 709 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
681 710 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
682 711 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
683 712 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
684 713 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
685 714 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
686 715 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
687 716 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
688 717 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
689 718
690 719 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
691 720 {
692 721 U8 NumElements; /* 0x00 */
693 722 U8 Reserved1; /* 0x01 */
694 723 U8 Reserved2; /* 0x02 */
695 724 U8 ConfigNum; /* 0x03 */
696 725 U32 Flags; /* 0x04 */
697 726 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
698 727 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
699 728 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
700 729 Mpi2EventDataIrConfigChangeList_t,
701 730 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
702 731
703 732 /* IR Configuration Change List Event data Flags values */
704 733 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
705 734
706 735
707 736 /* SAS Discovery Event data */
708 737
709 738 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
710 739 {
711 740 U8 Flags; /* 0x00 */
712 741 U8 ReasonCode; /* 0x01 */
713 742 U8 PhysicalPort; /* 0x02 */
714 743 U8 Reserved1; /* 0x03 */
715 744 U32 DiscoveryStatus; /* 0x04 */
716 745 } MPI2_EVENT_DATA_SAS_DISCOVERY,
717 746 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
718 747 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
719 748
720 749 /* SAS Discovery Event data Flags values */
721 750 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
722 751 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
723 752
724 753 /* SAS Discovery Event data ReasonCode values */
725 754 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
726 755 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
727 756
728 757 /* SAS Discovery Event data DiscoveryStatus values */
729 758 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
730 759 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
731 760 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
732 761 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
733 762 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
734 763 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
735 764 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
736 765 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
737 766 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
738 767 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
739 768 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
740 769 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
741 770 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
742 771 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
743 772 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
744 773 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
745 774 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
746 775 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
747 776 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
748 777 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
749 778
750 779
751 780 /* SAS Broadcast Primitive Event data */
752 781
753 782 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
754 783 {
755 784 U8 PhyNum; /* 0x00 */
756 785 U8 Port; /* 0x01 */
757 786 U8 PortWidth; /* 0x02 */
758 787 U8 Primitive; /* 0x03 */
759 788 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
760 789 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
761 790 Mpi2EventDataSasBroadcastPrimitive_t,
762 791 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
763 792
764 793 /* defines for the Primitive field */
765 794 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
766 795 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
767 796 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
768 797 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
769 798 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
770 799 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
771 800 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
772 801 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
773 802
774 803
775 804 /* SAS Initiator Device Status Change Event data */
776 805
777 806 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
778 807 {
779 808 U8 ReasonCode; /* 0x00 */
780 809 U8 PhysicalPort; /* 0x01 */
781 810 U16 DevHandle; /* 0x02 */
782 811 U64 SASAddress; /* 0x04 */
783 812 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
784 813 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
785 814 Mpi2EventDataSasInitDevStatusChange_t,
786 815 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
787 816
788 817 /* SAS Initiator Device Status Change event ReasonCode values */
789 818 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
790 819 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
791 820
792 821
793 822 /* SAS Initiator Device Table Overflow Event data */
794 823
795 824 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
796 825 {
797 826 U16 MaxInit; /* 0x00 */
798 827 U16 CurrentInit; /* 0x02 */
799 828 U64 SASAddress; /* 0x04 */
800 829 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
801 830 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
802 831 Mpi2EventDataSasInitTableOverflow_t,
803 832 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
804 833
805 834
806 835 /* SAS Topology Change List Event data */
807 836
808 837 /*
809 838 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
810 839 * one and check NumEntries at runtime.
811 840 */
812 841 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
813 842 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
814 843 #endif
815 844
816 845 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
817 846 {
818 847 U16 AttachedDevHandle; /* 0x00 */
819 848 U8 LinkRate; /* 0x02 */
820 849 U8 PhyStatus; /* 0x03 */
821 850 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
822 851 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
823 852
824 853 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
825 854 {
826 855 U16 EnclosureHandle; /* 0x00 */
827 856 U16 ExpanderDevHandle; /* 0x02 */
828 857 U8 NumPhys; /* 0x04 */
829 858 U8 Reserved1; /* 0x05 */
830 859 U16 Reserved2; /* 0x06 */
831 860 U8 NumEntries; /* 0x08 */
↓ open down ↓ |
276 lines elided |
↑ open up ↑ |
832 861 U8 StartPhyNum; /* 0x09 */
833 862 U8 ExpStatus; /* 0x0A */
834 863 U8 PhysicalPort; /* 0x0B */
835 864 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
836 865 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
837 866 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
838 867 Mpi2EventDataSasTopologyChangeList_t,
839 868 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
840 869
841 870 /* values for the ExpStatus field */
871 +#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
842 872 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
843 873 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
844 874 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
845 875 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
846 876
847 877 /* defines for the LinkRate field */
848 878 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
849 879 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
850 880 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
851 881 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
852 882
853 883 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
854 884 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
855 885 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
856 886 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
857 887 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
858 888 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
889 +#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
859 890 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
860 891 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
861 892 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
893 +#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
862 894
863 895 /* values for the PhyStatus field */
864 896 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
865 897 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
866 898 /* values for the PhyStatus ReasonCode sub-field */
867 899 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
868 900 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
869 901 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
870 902 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
871 903 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
872 904 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
873 905
874 906
875 907 /* SAS Enclosure Device Status Change Event data */
876 908
877 909 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
878 910 {
879 911 U16 EnclosureHandle; /* 0x00 */
880 912 U8 ReasonCode; /* 0x02 */
881 913 U8 PhysicalPort; /* 0x03 */
882 914 U64 EnclosureLogicalID; /* 0x04 */
883 915 U16 NumSlots; /* 0x0C */
884 916 U16 StartSlot; /* 0x0E */
885 917 U32 PhyBits; /* 0x10 */
886 918 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
887 919 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
888 920 Mpi2EventDataSasEnclDevStatusChange_t,
889 921 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
890 922
891 923 /* SAS Enclosure Device Status Change event ReasonCode values */
892 924 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
893 925 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
894 926
895 927
896 928 /* SAS PHY Counter Event data */
897 929
898 930 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
899 931 {
900 932 U64 TimeStamp; /* 0x00 */
901 933 U32 Reserved1; /* 0x08 */
902 934 U8 PhyEventCode; /* 0x0C */
903 935 U8 PhyNum; /* 0x0D */
904 936 U16 Reserved2; /* 0x0E */
905 937 U32 PhyEventInfo; /* 0x10 */
906 938 U8 CounterType; /* 0x14 */
907 939 U8 ThresholdWindow; /* 0x15 */
908 940 U8 TimeUnits; /* 0x16 */
909 941 U8 Reserved3; /* 0x17 */
910 942 U32 EventThreshold; /* 0x18 */
911 943 U16 ThresholdFlags; /* 0x1C */
912 944 U16 Reserved4; /* 0x1E */
913 945 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
914 946 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
915 947 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
↓ open down ↓ |
44 lines elided |
↑ open up ↑ |
916 948
917 949 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
918 950
919 951 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
920 952
921 953 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
922 954
923 955 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
924 956
925 957
958 +/* SAS Quiesce Event data */
959 +
960 +typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE
961 +{
962 + U8 ReasonCode; /* 0x00 */
963 + U8 Reserved1; /* 0x01 */
964 + U16 Reserved2; /* 0x02 */
965 + U32 Reserved3; /* 0x04 */
966 +} MPI2_EVENT_DATA_SAS_QUIESCE,
967 + MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
968 + Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
969 +
970 +/* SAS Quiesce Event data ReasonCode values */
971 +#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
972 +#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
973 +
974 +
975 +/* Host Based Discovery Phy Event data */
976 +
977 +typedef struct _MPI2_EVENT_HBD_PHY_SAS
978 +{
979 + U8 Flags; /* 0x00 */
980 + U8 NegotiatedLinkRate; /* 0x01 */
981 + U8 PhyNum; /* 0x02 */
982 + U8 PhysicalPort; /* 0x03 */
983 + U32 Reserved1; /* 0x04 */
984 + U8 InitialFrame[28]; /* 0x08 */
985 +} MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
986 + Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
987 +
988 +/* values for the Flags field */
989 +#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
990 +#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
991 +
992 +/* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */
993 +
994 +typedef union _MPI2_EVENT_HBD_DESCRIPTOR
995 +{
996 + MPI2_EVENT_HBD_PHY_SAS Sas;
997 +} MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
998 + Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
999 +
1000 +typedef struct _MPI2_EVENT_DATA_HBD_PHY
1001 +{
1002 + U8 DescriptorType; /* 0x00 */
1003 + U8 Reserved1; /* 0x01 */
1004 + U16 Reserved2; /* 0x02 */
1005 + U32 Reserved3; /* 0x04 */
1006 + MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
1007 +} MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1008 + Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1009 +
1010 +/* values for the DescriptorType field */
1011 +#define MPI2_EVENT_HBD_DT_SAS (0x01)
1012 +
1013 +
1014 +
926 1015 /****************************************************************************
927 1016 * EventAck message
928 1017 ****************************************************************************/
929 1018
930 1019 /* EventAck Request message */
931 1020 typedef struct _MPI2_EVENT_ACK_REQUEST
932 1021 {
933 1022 U16 Reserved1; /* 0x00 */
934 1023 U8 ChainOffset; /* 0x02 */
935 1024 U8 Function; /* 0x03 */
936 1025 U16 Reserved2; /* 0x04 */
937 1026 U8 Reserved3; /* 0x06 */
938 1027 U8 MsgFlags; /* 0x07 */
939 1028 U8 VP_ID; /* 0x08 */
940 1029 U8 VF_ID; /* 0x09 */
941 1030 U16 Reserved4; /* 0x0A */
942 1031 U16 Event; /* 0x0C */
943 1032 U16 Reserved5; /* 0x0E */
944 1033 U32 EventContext; /* 0x10 */
945 1034 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
946 1035 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
947 1036
948 1037
949 1038 /* EventAck Reply message */
950 1039 typedef struct _MPI2_EVENT_ACK_REPLY
951 1040 {
952 1041 U16 Reserved1; /* 0x00 */
953 1042 U8 MsgLength; /* 0x02 */
954 1043 U8 Function; /* 0x03 */
955 1044 U16 Reserved2; /* 0x04 */
956 1045 U8 Reserved3; /* 0x06 */
957 1046 U8 MsgFlags; /* 0x07 */
958 1047 U8 VP_ID; /* 0x08 */
959 1048 U8 VF_ID; /* 0x09 */
960 1049 U16 Reserved4; /* 0x0A */
961 1050 U16 Reserved5; /* 0x0C */
↓ open down ↓ |
26 lines elided |
↑ open up ↑ |
962 1051 U16 IOCStatus; /* 0x0E */
963 1052 U32 IOCLogInfo; /* 0x10 */
964 1053 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
965 1054 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
966 1055
967 1056
968 1057 /****************************************************************************
969 1058 * FWDownload message
970 1059 ****************************************************************************/
971 1060
972 -/* FWDownload Request message */
1061 +/* MPI v2.0 FWDownload Request message */
973 1062 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
974 1063 {
975 1064 U8 ImageType; /* 0x00 */
976 1065 U8 Reserved1; /* 0x01 */
977 1066 U8 ChainOffset; /* 0x02 */
978 1067 U8 Function; /* 0x03 */
979 1068 U16 Reserved2; /* 0x04 */
980 1069 U8 Reserved3; /* 0x06 */
981 1070 U8 MsgFlags; /* 0x07 */
982 1071 U8 VP_ID; /* 0x08 */
983 1072 U8 VF_ID; /* 0x09 */
984 1073 U16 Reserved4; /* 0x0A */
985 1074 U32 TotalImageSize; /* 0x0C */
986 1075 U32 Reserved5; /* 0x10 */
987 1076 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
988 1077 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
↓ open down ↓ |
6 lines elided |
↑ open up ↑ |
989 1078 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
990 1079
991 1080 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
992 1081
993 1082 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
994 1083 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
995 1084 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
996 1085 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
997 1086 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
998 1087 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1088 +#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
999 1089 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1090 +#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1000 1091
1001 -/* FWDownload TransactionContext Element */
1092 +/* MPI v2.0 FWDownload TransactionContext Element */
1002 1093 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1003 1094 {
1004 1095 U8 Reserved1; /* 0x00 */
1005 1096 U8 ContextSize; /* 0x01 */
1006 1097 U8 DetailsLength; /* 0x02 */
1007 1098 U8 Flags; /* 0x03 */
1008 1099 U32 Reserved2; /* 0x04 */
1009 1100 U32 ImageOffset; /* 0x08 */
1010 1101 U32 ImageSize; /* 0x0C */
1011 1102 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1012 1103 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1013 1104
1105 +
1106 +/* MPI v2.5 FWDownload Request message */
1107 +typedef struct _MPI25_FW_DOWNLOAD_REQUEST
1108 +{
1109 + U8 ImageType; /* 0x00 */
1110 + U8 Reserved1; /* 0x01 */
1111 + U8 ChainOffset; /* 0x02 */
1112 + U8 Function; /* 0x03 */
1113 + U16 Reserved2; /* 0x04 */
1114 + U8 Reserved3; /* 0x06 */
1115 + U8 MsgFlags; /* 0x07 */
1116 + U8 VP_ID; /* 0x08 */
1117 + U8 VF_ID; /* 0x09 */
1118 + U16 Reserved4; /* 0x0A */
1119 + U32 TotalImageSize; /* 0x0C */
1120 + U32 Reserved5; /* 0x10 */
1121 + U32 Reserved6; /* 0x14 */
1122 + U32 ImageOffset; /* 0x18 */
1123 + U32 ImageSize; /* 0x1C */
1124 + MPI25_SGE_IO_UNION SGL; /* 0x20 */
1125 +} MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST,
1126 + Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest;
1127 +
1128 +
1014 1129 /* FWDownload Reply message */
1015 1130 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1016 1131 {
1017 1132 U8 ImageType; /* 0x00 */
1018 1133 U8 Reserved1; /* 0x01 */
1019 1134 U8 MsgLength; /* 0x02 */
1020 1135 U8 Function; /* 0x03 */
1021 1136 U16 Reserved2; /* 0x04 */
1022 1137 U8 Reserved3; /* 0x06 */
1023 1138 U8 MsgFlags; /* 0x07 */
1024 1139 U8 VP_ID; /* 0x08 */
1025 1140 U8 VF_ID; /* 0x09 */
1026 1141 U16 Reserved4; /* 0x0A */
1027 1142 U16 Reserved5; /* 0x0C */
↓ open down ↓ |
4 lines elided |
↑ open up ↑ |
1028 1143 U16 IOCStatus; /* 0x0E */
1029 1144 U32 IOCLogInfo; /* 0x10 */
1030 1145 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1031 1146 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1032 1147
1033 1148
1034 1149 /****************************************************************************
1035 1150 * FWUpload message
1036 1151 ****************************************************************************/
1037 1152
1038 -/* FWUpload Request message */
1153 +/* MPI v2.0 FWUpload Request message */
1039 1154 typedef struct _MPI2_FW_UPLOAD_REQUEST
1040 1155 {
1041 1156 U8 ImageType; /* 0x00 */
1042 1157 U8 Reserved1; /* 0x01 */
1043 1158 U8 ChainOffset; /* 0x02 */
1044 1159 U8 Function; /* 0x03 */
1045 1160 U16 Reserved2; /* 0x04 */
1046 1161 U8 Reserved3; /* 0x06 */
1047 1162 U8 MsgFlags; /* 0x07 */
1048 1163 U8 VP_ID; /* 0x08 */
1049 1164 U8 VF_ID; /* 0x09 */
1050 1165 U16 Reserved4; /* 0x0A */
1051 1166 U32 Reserved5; /* 0x0C */
1052 1167 U32 Reserved6; /* 0x10 */
1053 1168 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1054 1169 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1055 1170 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1056 1171
1057 1172 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
↓ open down ↓ |
9 lines elided |
↑ open up ↑ |
1058 1173 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1059 1174 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1060 1175 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1061 1176 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1062 1177 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1063 1178 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1064 1179 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1065 1180 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1066 1181 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1067 1182
1183 +/* MPI v2.0 FWUpload TransactionContext Element */
1068 1184 typedef struct _MPI2_FW_UPLOAD_TCSGE
1069 1185 {
1070 1186 U8 Reserved1; /* 0x00 */
1071 1187 U8 ContextSize; /* 0x01 */
1072 1188 U8 DetailsLength; /* 0x02 */
1073 1189 U8 Flags; /* 0x03 */
1074 1190 U32 Reserved2; /* 0x04 */
1075 1191 U32 ImageOffset; /* 0x08 */
1076 1192 U32 ImageSize; /* 0x0C */
1077 1193 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1078 1194 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1079 1195
1196 +
1197 +/* MPI v2.5 FWUpload Request message */
1198 +typedef struct _MPI25_FW_UPLOAD_REQUEST
1199 +{
1200 + U8 ImageType; /* 0x00 */
1201 + U8 Reserved1; /* 0x01 */
1202 + U8 ChainOffset; /* 0x02 */
1203 + U8 Function; /* 0x03 */
1204 + U16 Reserved2; /* 0x04 */
1205 + U8 Reserved3; /* 0x06 */
1206 + U8 MsgFlags; /* 0x07 */
1207 + U8 VP_ID; /* 0x08 */
1208 + U8 VF_ID; /* 0x09 */
1209 + U16 Reserved4; /* 0x0A */
1210 + U32 Reserved5; /* 0x0C */
1211 + U32 Reserved6; /* 0x10 */
1212 + U32 Reserved7; /* 0x14 */
1213 + U32 ImageOffset; /* 0x18 */
1214 + U32 ImageSize; /* 0x1C */
1215 + MPI25_SGE_IO_UNION SGL; /* 0x20 */
1216 +} MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST,
1217 + Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t;
1218 +
1219 +
1080 1220 /* FWUpload Reply message */
1081 1221 typedef struct _MPI2_FW_UPLOAD_REPLY
1082 1222 {
1083 1223 U8 ImageType; /* 0x00 */
1084 1224 U8 Reserved1; /* 0x01 */
1085 1225 U8 MsgLength; /* 0x02 */
1086 1226 U8 Function; /* 0x03 */
1087 1227 U16 Reserved2; /* 0x04 */
1088 1228 U8 Reserved3; /* 0x06 */
1089 1229 U8 MsgFlags; /* 0x07 */
1090 1230 U8 VP_ID; /* 0x08 */
1091 1231 U8 VF_ID; /* 0x09 */
1092 1232 U16 Reserved4; /* 0x0A */
1093 1233 U16 Reserved5; /* 0x0C */
1094 1234 U16 IOCStatus; /* 0x0E */
1095 1235 U32 IOCLogInfo; /* 0x10 */
1096 1236 U32 ActualImageSize; /* 0x14 */
1097 1237 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1098 1238 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1099 1239
1100 1240
1101 1241 /* FW Image Header */
1102 1242 typedef struct _MPI2_FW_IMAGE_HEADER
1103 1243 {
1104 1244 U32 Signature; /* 0x00 */
1105 1245 U32 Signature0; /* 0x04 */
1106 1246 U32 Signature1; /* 0x08 */
1107 1247 U32 Signature2; /* 0x0C */
1108 1248 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1109 1249 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1110 1250 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1111 1251 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1112 1252 U16 VendorID; /* 0x20 */
1113 1253 U16 ProductID; /* 0x22 */
1114 1254 U16 ProtocolFlags; /* 0x24 */
1115 1255 U16 Reserved26; /* 0x26 */
1116 1256 U32 IOCCapabilities; /* 0x28 */
1117 1257 U32 ImageSize; /* 0x2C */
1118 1258 U32 NextImageHeaderOffset; /* 0x30 */
1119 1259 U32 Checksum; /* 0x34 */
1120 1260 U32 Reserved38; /* 0x38 */
1121 1261 U32 Reserved3C; /* 0x3C */
1122 1262 U32 Reserved40; /* 0x40 */
1123 1263 U32 Reserved44; /* 0x44 */
1124 1264 U32 Reserved48; /* 0x48 */
1125 1265 U32 Reserved4C; /* 0x4C */
1126 1266 U32 Reserved50; /* 0x50 */
1127 1267 U32 Reserved54; /* 0x54 */
1128 1268 U32 Reserved58; /* 0x58 */
1129 1269 U32 Reserved5C; /* 0x5C */
1130 1270 U32 Reserved60; /* 0x60 */
1131 1271 U32 FirmwareVersionNameWhat; /* 0x64 */
1132 1272 U8 FirmwareVersionName[32]; /* 0x68 */
1133 1273 U32 VendorNameWhat; /* 0x88 */
1134 1274 U8 VendorName[32]; /* 0x8C */
1135 1275 U32 PackageNameWhat; /* 0x88 */
1136 1276 U8 PackageName[32]; /* 0x8C */
1137 1277 U32 ReservedD0; /* 0xD0 */
1138 1278 U32 ReservedD4; /* 0xD4 */
1139 1279 U32 ReservedD8; /* 0xD8 */
1140 1280 U32 ReservedDC; /* 0xDC */
1141 1281 U32 ReservedE0; /* 0xE0 */
1142 1282 U32 ReservedE4; /* 0xE4 */
1143 1283 U32 ReservedE8; /* 0xE8 */
1144 1284 U32 ReservedEC; /* 0xEC */
1145 1285 U32 ReservedF0; /* 0xF0 */
1146 1286 U32 ReservedF4; /* 0xF4 */
1147 1287 U32 ReservedF8; /* 0xF8 */
1148 1288 U32 ReservedFC; /* 0xFC */
1149 1289 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1150 1290 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1151 1291
1152 1292 /* Signature field */
1153 1293 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1154 1294 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1155 1295 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1156 1296
1157 1297 /* Signature0 field */
1158 1298 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1159 1299 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1160 1300
1161 1301 /* Signature1 field */
1162 1302 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1163 1303 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
↓ open down ↓ |
74 lines elided |
↑ open up ↑ |
1164 1304
1165 1305 /* Signature2 field */
1166 1306 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1167 1307 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1168 1308
1169 1309
1170 1310 /* defines for using the ProductID field */
1171 1311 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1172 1312 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1173 1313
1174 -#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1175 -#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1314 +#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1315 +#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1316 +#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1317 +#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1176 1318
1177 1319 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1178 -/* SAS */
1179 -#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0010)
1180 -#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0011)
1320 +/* SAS ProductID Family bits */
1321 +#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1322 +#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1323 +#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1181 1324
1182 1325 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1183 1326
1184 1327 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1185 1328
1186 1329
1187 1330 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1188 1331 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1189 1332 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1190 1333
1191 1334 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1192 1335
1193 1336 #define MPI2_FW_HEADER_SIZE (0x100)
1194 1337
1195 1338
1196 1339 /* Extended Image Header */
1197 1340 typedef struct _MPI2_EXT_IMAGE_HEADER
1198 1341
1199 1342 {
1200 1343 U8 ImageType; /* 0x00 */
1201 1344 U8 Reserved1; /* 0x01 */
1202 1345 U16 Reserved2; /* 0x02 */
1203 1346 U32 Checksum; /* 0x04 */
1204 1347 U32 ImageSize; /* 0x08 */
1205 1348 U32 NextImageHeaderOffset; /* 0x0C */
1206 1349 U32 PackageVersion; /* 0x10 */
1207 1350 U32 Reserved3; /* 0x14 */
1208 1351 U32 Reserved4; /* 0x18 */
1209 1352 U32 Reserved5; /* 0x1C */
1210 1353 U8 IdentifyString[32]; /* 0x20 */
1211 1354 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1212 1355 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1213 1356
1214 1357 /* useful offsets */
1215 1358 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1216 1359 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1217 1360 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1218 1361
1219 1362 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1220 1363
1221 1364 /* defines for the ImageType field */
1222 1365 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1223 1366 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1224 1367 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1225 1368 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1226 1369 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1227 1370 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1228 1371 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1229 1372 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1230 1373
1231 1374 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID)
1232 1375
1233 1376
1234 1377
1235 1378 /* FLASH Layout Extended Image Data */
1236 1379
1237 1380 /*
1238 1381 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1239 1382 * one and check RegionsPerLayout at runtime.
1240 1383 */
1241 1384 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1242 1385 #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1243 1386 #endif
1244 1387
1245 1388 /*
1246 1389 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1247 1390 * one and check NumberOfLayouts at runtime.
1248 1391 */
1249 1392 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1250 1393 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1251 1394 #endif
1252 1395
1253 1396 typedef struct _MPI2_FLASH_REGION
1254 1397 {
1255 1398 U8 RegionType; /* 0x00 */
1256 1399 U8 Reserved1; /* 0x01 */
1257 1400 U16 Reserved2; /* 0x02 */
1258 1401 U32 RegionOffset; /* 0x04 */
1259 1402 U32 RegionSize; /* 0x08 */
1260 1403 U32 Reserved3; /* 0x0C */
1261 1404 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1262 1405 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1263 1406
1264 1407 typedef struct _MPI2_FLASH_LAYOUT
1265 1408 {
1266 1409 U32 FlashSize; /* 0x00 */
1267 1410 U32 Reserved1; /* 0x04 */
1268 1411 U32 Reserved2; /* 0x08 */
1269 1412 U32 Reserved3; /* 0x0C */
1270 1413 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1271 1414 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1272 1415 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1273 1416
1274 1417 typedef struct _MPI2_FLASH_LAYOUT_DATA
1275 1418 {
1276 1419 U8 ImageRevision; /* 0x00 */
1277 1420 U8 Reserved1; /* 0x01 */
1278 1421 U8 SizeOfRegion; /* 0x02 */
1279 1422 U8 Reserved2; /* 0x03 */
1280 1423 U16 NumberOfLayouts; /* 0x04 */
1281 1424 U16 RegionsPerLayout; /* 0x06 */
1282 1425 U16 MinimumSectorAlignment; /* 0x08 */
1283 1426 U16 Reserved3; /* 0x0A */
1284 1427 U32 Reserved4; /* 0x0C */
1285 1428 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1286 1429 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1287 1430 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1288 1431
1289 1432 /* defines for the RegionType field */
1290 1433 #define MPI2_FLASH_REGION_UNUSED (0x00)
1291 1434 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1292 1435 #define MPI2_FLASH_REGION_BIOS (0x02)
1293 1436 #define MPI2_FLASH_REGION_NVDATA (0x03)
1294 1437 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1295 1438 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1296 1439 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1297 1440 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1298 1441 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1299 1442 #define MPI2_FLASH_REGION_INIT (0x0A)
1300 1443
1301 1444 /* ImageRevision */
1302 1445 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1303 1446
1304 1447
1305 1448
1306 1449 /* Supported Devices Extended Image Data */
1307 1450
1308 1451 /*
1309 1452 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1310 1453 * one and check NumberOfDevices at runtime.
1311 1454 */
1312 1455 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1313 1456 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1314 1457 #endif
1315 1458
1316 1459 typedef struct _MPI2_SUPPORTED_DEVICE
1317 1460 {
1318 1461 U16 DeviceID; /* 0x00 */
1319 1462 U16 VendorID; /* 0x02 */
1320 1463 U16 DeviceIDMask; /* 0x04 */
1321 1464 U16 Reserved1; /* 0x06 */
1322 1465 U8 LowPCIRev; /* 0x08 */
1323 1466 U8 HighPCIRev; /* 0x09 */
1324 1467 U16 Reserved2; /* 0x0A */
1325 1468 U32 Reserved3; /* 0x0C */
1326 1469 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1327 1470 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1328 1471
1329 1472 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1330 1473 {
1331 1474 U8 ImageRevision; /* 0x00 */
1332 1475 U8 Reserved1; /* 0x01 */
1333 1476 U8 NumberOfDevices; /* 0x02 */
1334 1477 U8 Reserved2; /* 0x03 */
1335 1478 U32 Reserved3; /* 0x04 */
1336 1479 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1337 1480 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1338 1481 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1339 1482
1340 1483 /* ImageRevision */
1341 1484 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1342 1485
1343 1486
1344 1487 /* Init Extended Image Data */
1345 1488
1346 1489 typedef struct _MPI2_INIT_IMAGE_FOOTER
1347 1490
1348 1491 {
1349 1492 U32 BootFlags; /* 0x00 */
1350 1493 U32 ImageSize; /* 0x04 */
1351 1494 U32 Signature0; /* 0x08 */
1352 1495 U32 Signature1; /* 0x0C */
1353 1496 U32 Signature2; /* 0x10 */
1354 1497 U32 ResetVector; /* 0x14 */
1355 1498 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1356 1499 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1357 1500
1358 1501 /* defines for the BootFlags field */
1359 1502 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1360 1503
1361 1504 /* defines for the ImageSize field */
1362 1505 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1363 1506
1364 1507 /* defines for the Signature0 field */
1365 1508 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1366 1509 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1367 1510
1368 1511 /* defines for the Signature1 field */
1369 1512 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1370 1513 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1371 1514
1372 1515 /* defines for the Signature2 field */
1373 1516 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1374 1517 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1375 1518
1376 1519 /* Signature fields as individual bytes */
1377 1520 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1378 1521 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1379 1522 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1380 1523 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1381 1524
1382 1525 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1383 1526 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1384 1527 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1385 1528 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
↓ open down ↓ |
195 lines elided |
↑ open up ↑ |
1386 1529
1387 1530 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1388 1531 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1389 1532 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1390 1533 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1391 1534
1392 1535 /* defines for the ResetVector field */
1393 1536 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1394 1537
1395 1538
1539 +/****************************************************************************
1540 +* PowerManagementControl message
1541 +****************************************************************************/
1542 +
1543 +/* PowerManagementControl Request message */
1544 +typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST
1545 +{
1546 + U8 Feature; /* 0x00 */
1547 + U8 Reserved1; /* 0x01 */
1548 + U8 ChainOffset; /* 0x02 */
1549 + U8 Function; /* 0x03 */
1550 + U16 Reserved2; /* 0x04 */
1551 + U8 Reserved3; /* 0x06 */
1552 + U8 MsgFlags; /* 0x07 */
1553 + U8 VP_ID; /* 0x08 */
1554 + U8 VF_ID; /* 0x09 */
1555 + U16 Reserved4; /* 0x0A */
1556 + U8 Parameter1; /* 0x0C */
1557 + U8 Parameter2; /* 0x0D */
1558 + U8 Parameter3; /* 0x0E */
1559 + U8 Parameter4; /* 0x0F */
1560 + U32 Reserved5; /* 0x10 */
1561 + U32 Reserved6; /* 0x14 */
1562 +} MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1563 + Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1564 +
1565 +/* defines for the Feature field */
1566 +#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1567 +#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1568 +#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03)
1569 +#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1570 +#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1571 +#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1572 +
1573 +/* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1574 +/* Parameter1 contains a PHY number */
1575 +/* Parameter2 indicates power condition action using these defines */
1576 +#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1577 +#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1578 +#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1579 +/* Parameter3 and Parameter4 are reserved */
1580 +
1581 +/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */
1582 +/* Parameter1 contains SAS port width modulation group number */
1583 +/* Parameter2 indicates IOC action using these defines */
1584 +#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1585 +#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1586 +#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1587 +/* Parameter3 indicates desired modulation level using these defines */
1588 +#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1589 +#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1590 +#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1591 +#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1592 +/* Parameter4 is reserved */
1593 +
1594 +/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1595 +/* Parameter1 indicates desired PCIe link speed using these defines */
1596 +#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00)
1597 +#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01)
1598 +#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02)
1599 +/* Parameter2 indicates desired PCIe link width using these defines */
1600 +#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01)
1601 +#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02)
1602 +#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04)
1603 +#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08)
1604 +/* Parameter3 and Parameter4 are reserved */
1605 +
1606 +/* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1607 +/* Parameter1 indicates desired IOC hardware clock speed using these defines */
1608 +#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1609 +#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1610 +#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1611 +#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1612 +/* Parameter2, Parameter3, and Parameter4 are reserved */
1613 +
1614 +
1615 +/* PowerManagementControl Reply message */
1616 +typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY
1617 +{
1618 + U8 Feature; /* 0x00 */
1619 + U8 Reserved1; /* 0x01 */
1620 + U8 MsgLength; /* 0x02 */
1621 + U8 Function; /* 0x03 */
1622 + U16 Reserved2; /* 0x04 */
1623 + U8 Reserved3; /* 0x06 */
1624 + U8 MsgFlags; /* 0x07 */
1625 + U8 VP_ID; /* 0x08 */
1626 + U8 VF_ID; /* 0x09 */
1627 + U16 Reserved4; /* 0x0A */
1628 + U16 Reserved5; /* 0x0C */
1629 + U16 IOCStatus; /* 0x0E */
1630 + U32 IOCLogInfo; /* 0x10 */
1631 +} MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1632 + Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1633 +
1634 +
1396 1635 #endif
1397 1636
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX