3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2000 to 2009, LSI Corporation.
24 * All rights reserved.
25 *
26 * Redistribution and use in source and binary forms of all code within
27 * this file that is exclusively owned by LSI, with or without
28 * modification, is permitted provided that, in addition to the CDDL 1.0
29 * License requirements, the following conditions are met:
30 *
31 * Neither the name of the author nor the names of its contributors may be
32 * used to endorse or promote products derived from this software without
33 * specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
38 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
39 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
41 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
42 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
43 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
45 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46 * DAMAGE.
47 */
48
49 /*
50 * Name: mpi2_ioc.h
51 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
52 * Creation Date: October 11, 2006
53 *
54 * mpi2_ioc.h Version: 02.00.12
55 *
56 * Version History
57 * ---------------
58 *
59 * Date Version Description
60 * -------- -------- ------------------------------------------------------
61 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
62 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
63 * MaxTargets.
64 * Added TotalImageSize field to FWDownload Request.
65 * Added reserved words to FWUpload Request.
66 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
67 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
68 * request and replaced it with
69 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
70 * Replaced the MinReplyQueueDepth field of the IOCFacts
71 * reply with MaxReplyDescriptorPostQueueDepth.
72 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
73 * depth for the Reply Descriptor Post Queue.
74 * Added SASAddress field to Initiator Device Table
115 * Added Multiplexing Status Change bit to the PhyStatus
116 * field of the SAS Topology Change List event data.
117 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
118 * BootFlags are now product-specific.
119 * Added defines for the indivdual signature bytes
120 * for MPI2_INIT_IMAGE_FOOTER.
121 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
122 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
123 * define.
124 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
125 * define.
126 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
127 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
128 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
129 * Added two new reason codes for SAS Device Status Change
130 * Event.
131 * Added new event: SAS PHY Counter.
132 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
133 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
134 * Added new product id family for 2208.
135 * --------------------------------------------------------------------------
136 */
137
138 #ifndef MPI2_IOC_H
139 #define MPI2_IOC_H
140
141 /*****************************************************************************
142 *
143 * IOC Messages
144 *
145 *****************************************************************************/
146
147 /****************************************************************************
148 * IOCInit message
149 ****************************************************************************/
150
151 /* IOCInit Request message */
152 typedef struct _MPI2_IOC_INIT_REQUEST
153 {
154 U8 WhoInit; /* 0x00 */
155 U8 Reserved1; /* 0x01 */
156 U8 ChainOffset; /* 0x02 */
157 U8 Function; /* 0x03 */
158 U16 Reserved2; /* 0x04 */
159 U8 Reserved3; /* 0x06 */
160 U8 MsgFlags; /* 0x07 */
161 U8 VP_ID; /* 0x08 */
162 U8 VF_ID; /* 0x09 */
163 U16 Reserved4; /* 0x0A */
164 U16 MsgVersion; /* 0x0C */
165 U16 HeaderVersion; /* 0x0E */
166 U32 Reserved5; /* 0x10 */
167 U32 Reserved6; /* 0x14 */
168 U16 Reserved7; /* 0x18 */
169 U16 SystemRequestFrameSize; /* 0x1A */
170 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
171 U16 ReplyFreeQueueDepth; /* 0x1E */
172 U32 SenseBufferAddressHigh; /* 0x20 */
173 U32 SystemReplyAddressHigh; /* 0x24 */
174 U64 SystemRequestFrameBaseAddress; /* 0x28 */
175 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
176 U64 ReplyFreeQueueAddress; /* 0x38 */
177 U64 TimeStamp; /* 0x40 */
178 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
179 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
180
181 /* WhoInit values */
182 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
183 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
184 #define MPI2_WHOINIT_ROM_BIOS (0x02)
185 #define MPI2_WHOINIT_PCI_PEER (0x03)
186 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
187 #define MPI2_WHOINIT_MANUFACTURER (0x05)
188
243
244
245 /* IOCFacts Reply message */
246 typedef struct _MPI2_IOC_FACTS_REPLY
247 {
248 U16 MsgVersion; /* 0x00 */
249 U8 MsgLength; /* 0x02 */
250 U8 Function; /* 0x03 */
251 U16 HeaderVersion; /* 0x04 */
252 U8 IOCNumber; /* 0x06 */
253 U8 MsgFlags; /* 0x07 */
254 U8 VP_ID; /* 0x08 */
255 U8 VF_ID; /* 0x09 */
256 U16 Reserved1; /* 0x0A */
257 U16 IOCExceptions; /* 0x0C */
258 U16 IOCStatus; /* 0x0E */
259 U32 IOCLogInfo; /* 0x10 */
260 U8 MaxChainDepth; /* 0x14 */
261 U8 WhoInit; /* 0x15 */
262 U8 NumberOfPorts; /* 0x16 */
263 U8 Reserved2; /* 0x17 */
264 U16 RequestCredit; /* 0x18 */
265 U16 ProductID; /* 0x1A */
266 U32 IOCCapabilities; /* 0x1C */
267 MPI2_VERSION_UNION FWVersion; /* 0x20 */
268 U16 IOCRequestFrameSize; /* 0x24 */
269 U16 Reserved3; /* 0x26 */
270 U16 MaxInitiators; /* 0x28 */
271 U16 MaxTargets; /* 0x2A */
272 U16 MaxSasExpanders; /* 0x2C */
273 U16 MaxEnclosures; /* 0x2E */
274 U16 ProtocolFlags; /* 0x30 */
275 U16 HighPriorityCredit; /* 0x32 */
276 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
277 U8 ReplyFrameSize; /* 0x36 */
278 U8 MaxVolumes; /* 0x37 */
279 U16 MaxDevHandle; /* 0x38 */
280 U16 MaxPersistentEntries; /* 0x3A */
281 U32 Reserved4; /* 0x3C */
282 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
283 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
284
285 /* MsgVersion */
286 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
287 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
288 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
289 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
290
291 /* HeaderVersion */
292 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
293 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
294 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
295 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
296
297 /* IOCExceptions */
298 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
299
300 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
301 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
302 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
303 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
304 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
305
306 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
307 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
308 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
309 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
310 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
311
312 /* defines for WhoInit field are after the IOCInit Request */
313
314 /* ProductID field uses MPI2_FW_HEADER_PID_ */
315
316 /* IOCCapabilities */
317 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
318 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
319 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
320 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
321 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
322 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
323 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
324 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
325 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
326 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
327 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
328 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
329
330 /* ProtocolFlags */
331 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
332 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
333
334
335 /****************************************************************************
336 * PortFacts message
466 U16 Reserved2; /* 0x0A */
467 U16 Reserved3; /* 0x0C */
468 U16 IOCStatus; /* 0x0E */
469 U32 IOCLogInfo; /* 0x10 */
470 U16 Event; /* 0x14 */
471 U16 Reserved4; /* 0x16 */
472 U32 EventContext; /* 0x18 */
473 U32 EventData[1]; /* 0x1C */
474 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
475 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
476
477 /* AckRequired */
478 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
479 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
480
481 /* Event */
482 #define MPI2_EVENT_LOG_DATA (0x0001)
483 #define MPI2_EVENT_STATE_CHANGE (0x0002)
484 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
485 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
486 #define MPI2_EVENT_TASK_SET_FULL (0x000E)
487 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
488 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
489 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
490 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
491 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
492 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
493 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
494 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
495 #define MPI2_EVENT_IR_VOLUME (0x001E)
496 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
497 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
498 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
499 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
500 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
501
502
503 /* Log Entry Added Event data */
504
505 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
506 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
507
508 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
509 {
510 U64 TimeStamp; /* 0x00 */
511 U32 Reserved1; /* 0x08 */
512 U16 LogSequence; /* 0x0C */
513 U16 LogEntryQualifier; /* 0x0E */
514 U8 VP_ID; /* 0x10 */
515 U8 VF_ID; /* 0x11 */
516 U16 Reserved2; /* 0x12 */
517 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
518 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
519 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
520 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
526 U8 GPIONum; /* 0x00 */
527 U8 Reserved1; /* 0x01 */
528 U16 Reserved2; /* 0x02 */
529 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
530 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
531 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
532
533 /* Hard Reset Received Event data */
534
535 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
536 {
537 U8 Reserved1; /* 0x00 */
538 U8 Port; /* 0x01 */
539 U16 Reserved2; /* 0x02 */
540 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
541 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
542 Mpi2EventDataHardResetReceived_t,
543 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
544
545 /* Task Set Full Event data */
546
547 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
548 {
549 U16 DevHandle; /* 0x00 */
550 U16 CurrentDepth; /* 0x02 */
551 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
552 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
553
554
555 /* SAS Device Status Change Event data */
556
557 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
558 {
559 U16 TaskTag; /* 0x00 */
560 U8 ReasonCode; /* 0x02 */
561 U8 Reserved1; /* 0x03 */
562 U8 ASC; /* 0x04 */
563 U8 ASCQ; /* 0x05 */
564 U16 DevHandle; /* 0x06 */
565 U32 Reserved2; /* 0x08 */
822 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
823
824 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
825 {
826 U16 EnclosureHandle; /* 0x00 */
827 U16 ExpanderDevHandle; /* 0x02 */
828 U8 NumPhys; /* 0x04 */
829 U8 Reserved1; /* 0x05 */
830 U16 Reserved2; /* 0x06 */
831 U8 NumEntries; /* 0x08 */
832 U8 StartPhyNum; /* 0x09 */
833 U8 ExpStatus; /* 0x0A */
834 U8 PhysicalPort; /* 0x0B */
835 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
836 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
837 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
838 Mpi2EventDataSasTopologyChangeList_t,
839 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
840
841 /* values for the ExpStatus field */
842 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
843 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
844 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
845 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
846
847 /* defines for the LinkRate field */
848 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
849 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
850 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
851 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
852
853 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
854 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
855 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
856 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
857 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
858 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
859 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
860 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
861 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
862
863 /* values for the PhyStatus field */
864 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
865 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
866 /* values for the PhyStatus ReasonCode sub-field */
867 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
868 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
869 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
870 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
871 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
872 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
873
874
875 /* SAS Enclosure Device Status Change Event data */
876
877 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
878 {
879 U16 EnclosureHandle; /* 0x00 */
880 U8 ReasonCode; /* 0x02 */
881 U8 PhysicalPort; /* 0x03 */
906 U8 CounterType; /* 0x14 */
907 U8 ThresholdWindow; /* 0x15 */
908 U8 TimeUnits; /* 0x16 */
909 U8 Reserved3; /* 0x17 */
910 U32 EventThreshold; /* 0x18 */
911 U16 ThresholdFlags; /* 0x1C */
912 U16 Reserved4; /* 0x1E */
913 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
914 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
915 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
916
917 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
918
919 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
920
921 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
922
923 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
924
925
926 /****************************************************************************
927 * EventAck message
928 ****************************************************************************/
929
930 /* EventAck Request message */
931 typedef struct _MPI2_EVENT_ACK_REQUEST
932 {
933 U16 Reserved1; /* 0x00 */
934 U8 ChainOffset; /* 0x02 */
935 U8 Function; /* 0x03 */
936 U16 Reserved2; /* 0x04 */
937 U8 Reserved3; /* 0x06 */
938 U8 MsgFlags; /* 0x07 */
939 U8 VP_ID; /* 0x08 */
940 U8 VF_ID; /* 0x09 */
941 U16 Reserved4; /* 0x0A */
942 U16 Event; /* 0x0C */
943 U16 Reserved5; /* 0x0E */
944 U32 EventContext; /* 0x10 */
945 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
952 U16 Reserved1; /* 0x00 */
953 U8 MsgLength; /* 0x02 */
954 U8 Function; /* 0x03 */
955 U16 Reserved2; /* 0x04 */
956 U8 Reserved3; /* 0x06 */
957 U8 MsgFlags; /* 0x07 */
958 U8 VP_ID; /* 0x08 */
959 U8 VF_ID; /* 0x09 */
960 U16 Reserved4; /* 0x0A */
961 U16 Reserved5; /* 0x0C */
962 U16 IOCStatus; /* 0x0E */
963 U32 IOCLogInfo; /* 0x10 */
964 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
965 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
966
967
968 /****************************************************************************
969 * FWDownload message
970 ****************************************************************************/
971
972 /* FWDownload Request message */
973 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
974 {
975 U8 ImageType; /* 0x00 */
976 U8 Reserved1; /* 0x01 */
977 U8 ChainOffset; /* 0x02 */
978 U8 Function; /* 0x03 */
979 U16 Reserved2; /* 0x04 */
980 U8 Reserved3; /* 0x06 */
981 U8 MsgFlags; /* 0x07 */
982 U8 VP_ID; /* 0x08 */
983 U8 VF_ID; /* 0x09 */
984 U16 Reserved4; /* 0x0A */
985 U32 TotalImageSize; /* 0x0C */
986 U32 Reserved5; /* 0x10 */
987 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
988 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
989 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
990
991 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
992
993 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
994 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
995 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
996 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
997 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
998 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
999 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1000
1001 /* FWDownload TransactionContext Element */
1002 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1003 {
1004 U8 Reserved1; /* 0x00 */
1005 U8 ContextSize; /* 0x01 */
1006 U8 DetailsLength; /* 0x02 */
1007 U8 Flags; /* 0x03 */
1008 U32 Reserved2; /* 0x04 */
1009 U32 ImageOffset; /* 0x08 */
1010 U32 ImageSize; /* 0x0C */
1011 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1012 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1013
1014 /* FWDownload Reply message */
1015 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1016 {
1017 U8 ImageType; /* 0x00 */
1018 U8 Reserved1; /* 0x01 */
1019 U8 MsgLength; /* 0x02 */
1020 U8 Function; /* 0x03 */
1021 U16 Reserved2; /* 0x04 */
1022 U8 Reserved3; /* 0x06 */
1023 U8 MsgFlags; /* 0x07 */
1024 U8 VP_ID; /* 0x08 */
1025 U8 VF_ID; /* 0x09 */
1026 U16 Reserved4; /* 0x0A */
1027 U16 Reserved5; /* 0x0C */
1028 U16 IOCStatus; /* 0x0E */
1029 U32 IOCLogInfo; /* 0x10 */
1030 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1031 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1032
1033
1034 /****************************************************************************
1035 * FWUpload message
1036 ****************************************************************************/
1037
1038 /* FWUpload Request message */
1039 typedef struct _MPI2_FW_UPLOAD_REQUEST
1040 {
1041 U8 ImageType; /* 0x00 */
1042 U8 Reserved1; /* 0x01 */
1043 U8 ChainOffset; /* 0x02 */
1044 U8 Function; /* 0x03 */
1045 U16 Reserved2; /* 0x04 */
1046 U8 Reserved3; /* 0x06 */
1047 U8 MsgFlags; /* 0x07 */
1048 U8 VP_ID; /* 0x08 */
1049 U8 VF_ID; /* 0x09 */
1050 U16 Reserved4; /* 0x0A */
1051 U32 Reserved5; /* 0x0C */
1052 U32 Reserved6; /* 0x10 */
1053 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1054 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1055 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1056
1057 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1058 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1059 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1060 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1061 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1062 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1063 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1064 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1065 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1066 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1067
1068 typedef struct _MPI2_FW_UPLOAD_TCSGE
1069 {
1070 U8 Reserved1; /* 0x00 */
1071 U8 ContextSize; /* 0x01 */
1072 U8 DetailsLength; /* 0x02 */
1073 U8 Flags; /* 0x03 */
1074 U32 Reserved2; /* 0x04 */
1075 U32 ImageOffset; /* 0x08 */
1076 U32 ImageSize; /* 0x0C */
1077 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1078 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1079
1080 /* FWUpload Reply message */
1081 typedef struct _MPI2_FW_UPLOAD_REPLY
1082 {
1083 U8 ImageType; /* 0x00 */
1084 U8 Reserved1; /* 0x01 */
1085 U8 MsgLength; /* 0x02 */
1086 U8 Function; /* 0x03 */
1087 U16 Reserved2; /* 0x04 */
1088 U8 Reserved3; /* 0x06 */
1089 U8 MsgFlags; /* 0x07 */
1090 U8 VP_ID; /* 0x08 */
1091 U8 VF_ID; /* 0x09 */
1092 U16 Reserved4; /* 0x0A */
1093 U16 Reserved5; /* 0x0C */
1094 U16 IOCStatus; /* 0x0E */
1095 U32 IOCLogInfo; /* 0x10 */
1096 U32 ActualImageSize; /* 0x14 */
1097 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1098 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1099
1156
1157 /* Signature0 field */
1158 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1159 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1160
1161 /* Signature1 field */
1162 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1163 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1164
1165 /* Signature2 field */
1166 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1167 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1168
1169
1170 /* defines for using the ProductID field */
1171 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1172 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1173
1174 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1175 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1176
1177 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1178 /* SAS */
1179 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0010)
1180 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0011)
1181
1182 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1183
1184 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1185
1186
1187 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1188 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1189 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1190
1191 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1192
1193 #define MPI2_FW_HEADER_SIZE (0x100)
1194
1195
1196 /* Extended Image Header */
1197 typedef struct _MPI2_EXT_IMAGE_HEADER
1198
1199 {
1200 U8 ImageType; /* 0x00 */
1376 /* Signature fields as individual bytes */
1377 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1378 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1379 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1380 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1381
1382 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1383 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1384 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1385 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1386
1387 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1388 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1389 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1390 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1391
1392 /* defines for the ResetVector field */
1393 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1394
1395
1396 #endif
1397
|
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2000-2012 LSI Corporation.
24 *
25 * Redistribution and use in source and binary forms of all code within
26 * this file that is exclusively owned by LSI, with or without
27 * modification, is permitted provided that, in addition to the CDDL 1.0
28 * License requirements, the following conditions are met:
29 *
30 * Neither the name of the author nor the names of its contributors may be
31 * used to endorse or promote products derived from this software without
32 * specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
37 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
38 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
40 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
41 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
42 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
44 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
45 * DAMAGE.
46 */
47
48 /*
49 * Name: mpi2_ioc.h
50 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
51 * Creation Date: October 11, 2006
52 *
53 * mpi2_ioc.h Version: 02.00.xx
54 *
55 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
56 * prefix are for use only on MPI v2.5 products, and must not be used
57 * with MPI v2.0 products. Unless otherwise noted, names beginning with
58 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
59 *
60 * Version History
61 * ---------------
62 *
63 * Date Version Description
64 * -------- -------- ------------------------------------------------------
65 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
66 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
67 * MaxTargets.
68 * Added TotalImageSize field to FWDownload Request.
69 * Added reserved words to FWUpload Request.
70 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
71 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
72 * request and replaced it with
73 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
74 * Replaced the MinReplyQueueDepth field of the IOCFacts
75 * reply with MaxReplyDescriptorPostQueueDepth.
76 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
77 * depth for the Reply Descriptor Post Queue.
78 * Added SASAddress field to Initiator Device Table
119 * Added Multiplexing Status Change bit to the PhyStatus
120 * field of the SAS Topology Change List event data.
121 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
122 * BootFlags are now product-specific.
123 * Added defines for the indivdual signature bytes
124 * for MPI2_INIT_IMAGE_FOOTER.
125 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
126 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
127 * define.
128 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
129 * define.
130 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
131 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
132 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
133 * Added two new reason codes for SAS Device Status Change
134 * Event.
135 * Added new event: SAS PHY Counter.
136 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
137 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
138 * Added new product id family for 2208.
139 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
140 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
141 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
142 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
143 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
144 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
145 * Added Host Based Discovery Phy Event data.
146 * Added defines for ProductID Product field
147 * (MPI2_FW_HEADER_PID_).
148 * Modified values for SAS ProductID Family
149 * (MPI2_FW_HEADER_PID_FAMILY_).
150 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
151 * Added PowerManagementControl Request structures and
152 * defines.
153 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
154 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
155 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
156 * --------------------------------------------------------------------------
157 */
158
159 #ifndef MPI2_IOC_H
160 #define MPI2_IOC_H
161
162 /*****************************************************************************
163 *
164 * IOC Messages
165 *
166 *****************************************************************************/
167
168 /****************************************************************************
169 * IOCInit message
170 ****************************************************************************/
171
172 /* IOCInit Request message */
173 typedef struct _MPI2_IOC_INIT_REQUEST
174 {
175 U8 WhoInit; /* 0x00 */
176 U8 Reserved1; /* 0x01 */
177 U8 ChainOffset; /* 0x02 */
178 U8 Function; /* 0x03 */
179 U16 Reserved2; /* 0x04 */
180 U8 Reserved3; /* 0x06 */
181 U8 MsgFlags; /* 0x07 */
182 U8 VP_ID; /* 0x08 */
183 U8 VF_ID; /* 0x09 */
184 U16 Reserved4; /* 0x0A */
185 U16 MsgVersion; /* 0x0C */
186 U16 HeaderVersion; /* 0x0E */
187 U32 Reserved5; /* 0x10 */
188 U16 Reserved6; /* 0x14 */
189 U8 Reserved7; /* 0x16 */
190 U8 HostMSIxVectors; /* 0x17 */
191 U16 Reserved8; /* 0x18 */
192 U16 SystemRequestFrameSize; /* 0x1A */
193 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
194 U16 ReplyFreeQueueDepth; /* 0x1E */
195 U32 SenseBufferAddressHigh; /* 0x20 */
196 U32 SystemReplyAddressHigh; /* 0x24 */
197 U64 SystemRequestFrameBaseAddress; /* 0x28 */
198 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
199 U64 ReplyFreeQueueAddress; /* 0x38 */
200 U64 TimeStamp; /* 0x40 */
201 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
202 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
203
204 /* WhoInit values */
205 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
206 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
207 #define MPI2_WHOINIT_ROM_BIOS (0x02)
208 #define MPI2_WHOINIT_PCI_PEER (0x03)
209 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
210 #define MPI2_WHOINIT_MANUFACTURER (0x05)
211
266
267
268 /* IOCFacts Reply message */
269 typedef struct _MPI2_IOC_FACTS_REPLY
270 {
271 U16 MsgVersion; /* 0x00 */
272 U8 MsgLength; /* 0x02 */
273 U8 Function; /* 0x03 */
274 U16 HeaderVersion; /* 0x04 */
275 U8 IOCNumber; /* 0x06 */
276 U8 MsgFlags; /* 0x07 */
277 U8 VP_ID; /* 0x08 */
278 U8 VF_ID; /* 0x09 */
279 U16 Reserved1; /* 0x0A */
280 U16 IOCExceptions; /* 0x0C */
281 U16 IOCStatus; /* 0x0E */
282 U32 IOCLogInfo; /* 0x10 */
283 U8 MaxChainDepth; /* 0x14 */
284 U8 WhoInit; /* 0x15 */
285 U8 NumberOfPorts; /* 0x16 */
286 U8 MaxMSIxVectors; /* 0x17 */
287 U16 RequestCredit; /* 0x18 */
288 U16 ProductID; /* 0x1A */
289 U32 IOCCapabilities; /* 0x1C */
290 MPI2_VERSION_UNION FWVersion; /* 0x20 */
291 U16 IOCRequestFrameSize; /* 0x24 */
292 U16 Reserved3; /* 0x26 */
293 U16 MaxInitiators; /* 0x28 */
294 U16 MaxTargets; /* 0x2A */
295 U16 MaxSasExpanders; /* 0x2C */
296 U16 MaxEnclosures; /* 0x2E */
297 U16 ProtocolFlags; /* 0x30 */
298 U16 HighPriorityCredit; /* 0x32 */
299 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
300 U8 ReplyFrameSize; /* 0x36 */
301 U8 MaxVolumes; /* 0x37 */
302 U16 MaxDevHandle; /* 0x38 */
303 U16 MaxPersistentEntries; /* 0x3A */
304 U16 MinDevHandle; /* 0x3C */
305 U16 Reserved4; /* 0x3E */
306 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
307 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
308
309 /* MsgVersion */
310 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
311 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
312 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
313 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
314
315 /* HeaderVersion */
316 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
317 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
318 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
319 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
320
321 /* IOCExceptions */
322 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
323
324 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
325 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
326 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
327 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
328 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
329
330 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
331 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
332 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
333 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
334 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
335
336 /* defines for WhoInit field are after the IOCInit Request */
337
338 /* ProductID field uses MPI2_FW_HEADER_PID_ */
339
340 /* IOCCapabilities */
341 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
342 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
343 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
344 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
345 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
346 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
347 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
348 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
349 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
350 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
351 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
352 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
353 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
354 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
355
356 /* ProtocolFlags */
357 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
358 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
359
360
361 /****************************************************************************
362 * PortFacts message
492 U16 Reserved2; /* 0x0A */
493 U16 Reserved3; /* 0x0C */
494 U16 IOCStatus; /* 0x0E */
495 U32 IOCLogInfo; /* 0x10 */
496 U16 Event; /* 0x14 */
497 U16 Reserved4; /* 0x16 */
498 U32 EventContext; /* 0x18 */
499 U32 EventData[1]; /* 0x1C */
500 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
501 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
502
503 /* AckRequired */
504 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
505 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
506
507 /* Event */
508 #define MPI2_EVENT_LOG_DATA (0x0001)
509 #define MPI2_EVENT_STATE_CHANGE (0x0002)
510 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
511 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
512 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
513 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
514 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
515 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
516 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
517 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
518 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
519 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
520 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
521 #define MPI2_EVENT_IR_VOLUME (0x001E)
522 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
523 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
524 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
525 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
526 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
527 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
528 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
529
530
531 /* Log Entry Added Event data */
532
533 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
534 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
535
536 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
537 {
538 U64 TimeStamp; /* 0x00 */
539 U32 Reserved1; /* 0x08 */
540 U16 LogSequence; /* 0x0C */
541 U16 LogEntryQualifier; /* 0x0E */
542 U8 VP_ID; /* 0x10 */
543 U8 VF_ID; /* 0x11 */
544 U16 Reserved2; /* 0x12 */
545 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
546 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
547 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
548 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
554 U8 GPIONum; /* 0x00 */
555 U8 Reserved1; /* 0x01 */
556 U16 Reserved2; /* 0x02 */
557 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
558 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
559 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
560
561 /* Hard Reset Received Event data */
562
563 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
564 {
565 U8 Reserved1; /* 0x00 */
566 U8 Port; /* 0x01 */
567 U16 Reserved2; /* 0x02 */
568 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
569 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
570 Mpi2EventDataHardResetReceived_t,
571 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
572
573 /* Task Set Full Event data */
574 /* this event is obsolete */
575
576 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
577 {
578 U16 DevHandle; /* 0x00 */
579 U16 CurrentDepth; /* 0x02 */
580 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
581 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
582
583
584 /* SAS Device Status Change Event data */
585
586 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
587 {
588 U16 TaskTag; /* 0x00 */
589 U8 ReasonCode; /* 0x02 */
590 U8 Reserved1; /* 0x03 */
591 U8 ASC; /* 0x04 */
592 U8 ASCQ; /* 0x05 */
593 U16 DevHandle; /* 0x06 */
594 U32 Reserved2; /* 0x08 */
851 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
852
853 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
854 {
855 U16 EnclosureHandle; /* 0x00 */
856 U16 ExpanderDevHandle; /* 0x02 */
857 U8 NumPhys; /* 0x04 */
858 U8 Reserved1; /* 0x05 */
859 U16 Reserved2; /* 0x06 */
860 U8 NumEntries; /* 0x08 */
861 U8 StartPhyNum; /* 0x09 */
862 U8 ExpStatus; /* 0x0A */
863 U8 PhysicalPort; /* 0x0B */
864 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
865 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
866 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
867 Mpi2EventDataSasTopologyChangeList_t,
868 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
869
870 /* values for the ExpStatus field */
871 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
872 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
873 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
874 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
875 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
876
877 /* defines for the LinkRate field */
878 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
879 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
880 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
881 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
882
883 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
884 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
885 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
886 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
887 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
888 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
889 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
890 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
891 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
892 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
893 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
894
895 /* values for the PhyStatus field */
896 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
897 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
898 /* values for the PhyStatus ReasonCode sub-field */
899 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
900 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
901 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
902 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
903 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
904 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
905
906
907 /* SAS Enclosure Device Status Change Event data */
908
909 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
910 {
911 U16 EnclosureHandle; /* 0x00 */
912 U8 ReasonCode; /* 0x02 */
913 U8 PhysicalPort; /* 0x03 */
938 U8 CounterType; /* 0x14 */
939 U8 ThresholdWindow; /* 0x15 */
940 U8 TimeUnits; /* 0x16 */
941 U8 Reserved3; /* 0x17 */
942 U32 EventThreshold; /* 0x18 */
943 U16 ThresholdFlags; /* 0x1C */
944 U16 Reserved4; /* 0x1E */
945 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
946 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
947 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
948
949 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
950
951 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
952
953 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
954
955 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
956
957
958 /* SAS Quiesce Event data */
959
960 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE
961 {
962 U8 ReasonCode; /* 0x00 */
963 U8 Reserved1; /* 0x01 */
964 U16 Reserved2; /* 0x02 */
965 U32 Reserved3; /* 0x04 */
966 } MPI2_EVENT_DATA_SAS_QUIESCE,
967 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
968 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
969
970 /* SAS Quiesce Event data ReasonCode values */
971 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
972 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
973
974
975 /* Host Based Discovery Phy Event data */
976
977 typedef struct _MPI2_EVENT_HBD_PHY_SAS
978 {
979 U8 Flags; /* 0x00 */
980 U8 NegotiatedLinkRate; /* 0x01 */
981 U8 PhyNum; /* 0x02 */
982 U8 PhysicalPort; /* 0x03 */
983 U32 Reserved1; /* 0x04 */
984 U8 InitialFrame[28]; /* 0x08 */
985 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
986 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
987
988 /* values for the Flags field */
989 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
990 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
991
992 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */
993
994 typedef union _MPI2_EVENT_HBD_DESCRIPTOR
995 {
996 MPI2_EVENT_HBD_PHY_SAS Sas;
997 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
998 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
999
1000 typedef struct _MPI2_EVENT_DATA_HBD_PHY
1001 {
1002 U8 DescriptorType; /* 0x00 */
1003 U8 Reserved1; /* 0x01 */
1004 U16 Reserved2; /* 0x02 */
1005 U32 Reserved3; /* 0x04 */
1006 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
1007 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1008 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1009
1010 /* values for the DescriptorType field */
1011 #define MPI2_EVENT_HBD_DT_SAS (0x01)
1012
1013
1014
1015 /****************************************************************************
1016 * EventAck message
1017 ****************************************************************************/
1018
1019 /* EventAck Request message */
1020 typedef struct _MPI2_EVENT_ACK_REQUEST
1021 {
1022 U16 Reserved1; /* 0x00 */
1023 U8 ChainOffset; /* 0x02 */
1024 U8 Function; /* 0x03 */
1025 U16 Reserved2; /* 0x04 */
1026 U8 Reserved3; /* 0x06 */
1027 U8 MsgFlags; /* 0x07 */
1028 U8 VP_ID; /* 0x08 */
1029 U8 VF_ID; /* 0x09 */
1030 U16 Reserved4; /* 0x0A */
1031 U16 Event; /* 0x0C */
1032 U16 Reserved5; /* 0x0E */
1033 U32 EventContext; /* 0x10 */
1034 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1041 U16 Reserved1; /* 0x00 */
1042 U8 MsgLength; /* 0x02 */
1043 U8 Function; /* 0x03 */
1044 U16 Reserved2; /* 0x04 */
1045 U8 Reserved3; /* 0x06 */
1046 U8 MsgFlags; /* 0x07 */
1047 U8 VP_ID; /* 0x08 */
1048 U8 VF_ID; /* 0x09 */
1049 U16 Reserved4; /* 0x0A */
1050 U16 Reserved5; /* 0x0C */
1051 U16 IOCStatus; /* 0x0E */
1052 U32 IOCLogInfo; /* 0x10 */
1053 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1054 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1055
1056
1057 /****************************************************************************
1058 * FWDownload message
1059 ****************************************************************************/
1060
1061 /* MPI v2.0 FWDownload Request message */
1062 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1063 {
1064 U8 ImageType; /* 0x00 */
1065 U8 Reserved1; /* 0x01 */
1066 U8 ChainOffset; /* 0x02 */
1067 U8 Function; /* 0x03 */
1068 U16 Reserved2; /* 0x04 */
1069 U8 Reserved3; /* 0x06 */
1070 U8 MsgFlags; /* 0x07 */
1071 U8 VP_ID; /* 0x08 */
1072 U8 VF_ID; /* 0x09 */
1073 U16 Reserved4; /* 0x0A */
1074 U32 TotalImageSize; /* 0x0C */
1075 U32 Reserved5; /* 0x10 */
1076 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1077 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1078 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1079
1080 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1081
1082 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1083 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1084 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1085 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1086 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1087 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1088 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1089 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1090 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1091
1092 /* MPI v2.0 FWDownload TransactionContext Element */
1093 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1094 {
1095 U8 Reserved1; /* 0x00 */
1096 U8 ContextSize; /* 0x01 */
1097 U8 DetailsLength; /* 0x02 */
1098 U8 Flags; /* 0x03 */
1099 U32 Reserved2; /* 0x04 */
1100 U32 ImageOffset; /* 0x08 */
1101 U32 ImageSize; /* 0x0C */
1102 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1103 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1104
1105
1106 /* MPI v2.5 FWDownload Request message */
1107 typedef struct _MPI25_FW_DOWNLOAD_REQUEST
1108 {
1109 U8 ImageType; /* 0x00 */
1110 U8 Reserved1; /* 0x01 */
1111 U8 ChainOffset; /* 0x02 */
1112 U8 Function; /* 0x03 */
1113 U16 Reserved2; /* 0x04 */
1114 U8 Reserved3; /* 0x06 */
1115 U8 MsgFlags; /* 0x07 */
1116 U8 VP_ID; /* 0x08 */
1117 U8 VF_ID; /* 0x09 */
1118 U16 Reserved4; /* 0x0A */
1119 U32 TotalImageSize; /* 0x0C */
1120 U32 Reserved5; /* 0x10 */
1121 U32 Reserved6; /* 0x14 */
1122 U32 ImageOffset; /* 0x18 */
1123 U32 ImageSize; /* 0x1C */
1124 MPI25_SGE_IO_UNION SGL; /* 0x20 */
1125 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST,
1126 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest;
1127
1128
1129 /* FWDownload Reply message */
1130 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1131 {
1132 U8 ImageType; /* 0x00 */
1133 U8 Reserved1; /* 0x01 */
1134 U8 MsgLength; /* 0x02 */
1135 U8 Function; /* 0x03 */
1136 U16 Reserved2; /* 0x04 */
1137 U8 Reserved3; /* 0x06 */
1138 U8 MsgFlags; /* 0x07 */
1139 U8 VP_ID; /* 0x08 */
1140 U8 VF_ID; /* 0x09 */
1141 U16 Reserved4; /* 0x0A */
1142 U16 Reserved5; /* 0x0C */
1143 U16 IOCStatus; /* 0x0E */
1144 U32 IOCLogInfo; /* 0x10 */
1145 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1146 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1147
1148
1149 /****************************************************************************
1150 * FWUpload message
1151 ****************************************************************************/
1152
1153 /* MPI v2.0 FWUpload Request message */
1154 typedef struct _MPI2_FW_UPLOAD_REQUEST
1155 {
1156 U8 ImageType; /* 0x00 */
1157 U8 Reserved1; /* 0x01 */
1158 U8 ChainOffset; /* 0x02 */
1159 U8 Function; /* 0x03 */
1160 U16 Reserved2; /* 0x04 */
1161 U8 Reserved3; /* 0x06 */
1162 U8 MsgFlags; /* 0x07 */
1163 U8 VP_ID; /* 0x08 */
1164 U8 VF_ID; /* 0x09 */
1165 U16 Reserved4; /* 0x0A */
1166 U32 Reserved5; /* 0x0C */
1167 U32 Reserved6; /* 0x10 */
1168 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1169 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1170 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1171
1172 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1173 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1174 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1175 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1176 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1177 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1178 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1179 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1180 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1181 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1182
1183 /* MPI v2.0 FWUpload TransactionContext Element */
1184 typedef struct _MPI2_FW_UPLOAD_TCSGE
1185 {
1186 U8 Reserved1; /* 0x00 */
1187 U8 ContextSize; /* 0x01 */
1188 U8 DetailsLength; /* 0x02 */
1189 U8 Flags; /* 0x03 */
1190 U32 Reserved2; /* 0x04 */
1191 U32 ImageOffset; /* 0x08 */
1192 U32 ImageSize; /* 0x0C */
1193 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1194 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1195
1196
1197 /* MPI v2.5 FWUpload Request message */
1198 typedef struct _MPI25_FW_UPLOAD_REQUEST
1199 {
1200 U8 ImageType; /* 0x00 */
1201 U8 Reserved1; /* 0x01 */
1202 U8 ChainOffset; /* 0x02 */
1203 U8 Function; /* 0x03 */
1204 U16 Reserved2; /* 0x04 */
1205 U8 Reserved3; /* 0x06 */
1206 U8 MsgFlags; /* 0x07 */
1207 U8 VP_ID; /* 0x08 */
1208 U8 VF_ID; /* 0x09 */
1209 U16 Reserved4; /* 0x0A */
1210 U32 Reserved5; /* 0x0C */
1211 U32 Reserved6; /* 0x10 */
1212 U32 Reserved7; /* 0x14 */
1213 U32 ImageOffset; /* 0x18 */
1214 U32 ImageSize; /* 0x1C */
1215 MPI25_SGE_IO_UNION SGL; /* 0x20 */
1216 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST,
1217 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t;
1218
1219
1220 /* FWUpload Reply message */
1221 typedef struct _MPI2_FW_UPLOAD_REPLY
1222 {
1223 U8 ImageType; /* 0x00 */
1224 U8 Reserved1; /* 0x01 */
1225 U8 MsgLength; /* 0x02 */
1226 U8 Function; /* 0x03 */
1227 U16 Reserved2; /* 0x04 */
1228 U8 Reserved3; /* 0x06 */
1229 U8 MsgFlags; /* 0x07 */
1230 U8 VP_ID; /* 0x08 */
1231 U8 VF_ID; /* 0x09 */
1232 U16 Reserved4; /* 0x0A */
1233 U16 Reserved5; /* 0x0C */
1234 U16 IOCStatus; /* 0x0E */
1235 U32 IOCLogInfo; /* 0x10 */
1236 U32 ActualImageSize; /* 0x14 */
1237 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1238 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1239
1296
1297 /* Signature0 field */
1298 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1299 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1300
1301 /* Signature1 field */
1302 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1303 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1304
1305 /* Signature2 field */
1306 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1307 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1308
1309
1310 /* defines for using the ProductID field */
1311 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1312 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1313
1314 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1315 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1316 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1317 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1318
1319 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1320 /* SAS ProductID Family bits */
1321 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1322 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1323 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1324
1325 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1326
1327 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1328
1329
1330 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1331 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1332 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1333
1334 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1335
1336 #define MPI2_FW_HEADER_SIZE (0x100)
1337
1338
1339 /* Extended Image Header */
1340 typedef struct _MPI2_EXT_IMAGE_HEADER
1341
1342 {
1343 U8 ImageType; /* 0x00 */
1519 /* Signature fields as individual bytes */
1520 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1521 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1522 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1523 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1524
1525 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1526 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1527 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1528 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1529
1530 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1531 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1532 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1533 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1534
1535 /* defines for the ResetVector field */
1536 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1537
1538
1539 /****************************************************************************
1540 * PowerManagementControl message
1541 ****************************************************************************/
1542
1543 /* PowerManagementControl Request message */
1544 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST
1545 {
1546 U8 Feature; /* 0x00 */
1547 U8 Reserved1; /* 0x01 */
1548 U8 ChainOffset; /* 0x02 */
1549 U8 Function; /* 0x03 */
1550 U16 Reserved2; /* 0x04 */
1551 U8 Reserved3; /* 0x06 */
1552 U8 MsgFlags; /* 0x07 */
1553 U8 VP_ID; /* 0x08 */
1554 U8 VF_ID; /* 0x09 */
1555 U16 Reserved4; /* 0x0A */
1556 U8 Parameter1; /* 0x0C */
1557 U8 Parameter2; /* 0x0D */
1558 U8 Parameter3; /* 0x0E */
1559 U8 Parameter4; /* 0x0F */
1560 U32 Reserved5; /* 0x10 */
1561 U32 Reserved6; /* 0x14 */
1562 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1563 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1564
1565 /* defines for the Feature field */
1566 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1567 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1568 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03)
1569 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1570 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1571 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1572
1573 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1574 /* Parameter1 contains a PHY number */
1575 /* Parameter2 indicates power condition action using these defines */
1576 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1577 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1578 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1579 /* Parameter3 and Parameter4 are reserved */
1580
1581 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */
1582 /* Parameter1 contains SAS port width modulation group number */
1583 /* Parameter2 indicates IOC action using these defines */
1584 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1585 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1586 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1587 /* Parameter3 indicates desired modulation level using these defines */
1588 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1589 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1590 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1591 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1592 /* Parameter4 is reserved */
1593
1594 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1595 /* Parameter1 indicates desired PCIe link speed using these defines */
1596 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00)
1597 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01)
1598 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02)
1599 /* Parameter2 indicates desired PCIe link width using these defines */
1600 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01)
1601 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02)
1602 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04)
1603 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08)
1604 /* Parameter3 and Parameter4 are reserved */
1605
1606 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1607 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1608 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1609 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1610 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1611 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1612 /* Parameter2, Parameter3, and Parameter4 are reserved */
1613
1614
1615 /* PowerManagementControl Reply message */
1616 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY
1617 {
1618 U8 Feature; /* 0x00 */
1619 U8 Reserved1; /* 0x01 */
1620 U8 MsgLength; /* 0x02 */
1621 U8 Function; /* 0x03 */
1622 U16 Reserved2; /* 0x04 */
1623 U8 Reserved3; /* 0x06 */
1624 U8 MsgFlags; /* 0x07 */
1625 U8 VP_ID; /* 0x08 */
1626 U8 VF_ID; /* 0x09 */
1627 U16 Reserved4; /* 0x0A */
1628 U16 Reserved5; /* 0x0C */
1629 U16 IOCStatus; /* 0x0E */
1630 U32 IOCLogInfo; /* 0x10 */
1631 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1632 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1633
1634
1635 #endif
1636
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