1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2000-2012 LSI Corporation. 24 * 25 * Redistribution and use in source and binary forms of all code within 26 * this file that is exclusively owned by LSI, with or without 27 * modification, is permitted provided that, in addition to the CDDL 1.0 28 * License requirements, the following conditions are met: 29 * 30 * Neither the name of the author nor the names of its contributors may be 31 * used to endorse or promote products derived from this software without 32 * specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 37 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 38 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 40 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 41 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 42 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 44 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 45 * DAMAGE. 46 */ 47 48 /* 49 * Name: mpi2_ioc.h 50 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 51 * Creation Date: October 11, 2006 52 * 53 * mpi2_ioc.h Version: 02.00.xx 54 * 55 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 56 * prefix are for use only on MPI v2.5 products, and must not be used 57 * with MPI v2.0 products. Unless otherwise noted, names beginning with 58 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 59 * 60 * Version History 61 * --------------- 62 * 63 * Date Version Description 64 * -------- -------- ------------------------------------------------------ 65 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 66 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 67 * MaxTargets. 68 * Added TotalImageSize field to FWDownload Request. 69 * Added reserved words to FWUpload Request. 70 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 71 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 72 * request and replaced it with 73 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 74 * Replaced the MinReplyQueueDepth field of the IOCFacts 75 * reply with MaxReplyDescriptorPostQueueDepth. 76 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 77 * depth for the Reply Descriptor Post Queue. 78 * Added SASAddress field to Initiator Device Table 79 * Overflow Event data. 80 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 81 * for SAS Initiator Device Status Change Event data. 82 * Modified Reason Code defines for SAS Topology Change 83 * List Event data, including adding a bit for PHY Vacant 84 * status, and adding a mask for the Reason Code. 85 * Added define for 86 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 87 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 88 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 89 * the IOCFacts Reply. 90 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 91 * Moved MPI2_VERSION_UNION to mpi2.h. 92 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 93 * instead of enables, and added SASBroadcastPrimitiveMasks 94 * field. 95 * Added Log Entry Added Event and related structure. 96 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 97 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 98 * Added MaxVolumes and MaxPersistentEntries fields to 99 * IOCFacts reply. 100 * Added ProtocalFlags and IOCCapabilities fields to 101 * MPI2_FW_IMAGE_HEADER. 102 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 103 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 104 * a U16 (from a U32). 105 * Removed extra 's' from EventMasks name. 106 * 06-27-08 02.00.08 Fixed an offset in a comment. 107 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 108 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 109 * renamed MinReplyFrameSize to ReplyFrameSize. 110 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 111 * Added two new RAIDOperation values for Integrated RAID 112 * Operations Status Event data. 113 * Added four new IR Configuration Change List Event data 114 * ReasonCode values. 115 * Added two new ReasonCode defines for SAS Device Status 116 * Change Event data. 117 * Added three new DiscoveryStatus bits for the SAS 118 * Discovery event data. 119 * Added Multiplexing Status Change bit to the PhyStatus 120 * field of the SAS Topology Change List event data. 121 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 122 * BootFlags are now product-specific. 123 * Added defines for the indivdual signature bytes 124 * for MPI2_INIT_IMAGE_FOOTER. 125 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 126 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 127 * define. 128 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 129 * define. 130 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 131 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 132 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 133 * Added two new reason codes for SAS Device Status Change 134 * Event. 135 * Added new event: SAS PHY Counter. 136 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 137 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 138 * Added new product id family for 2208. 139 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 140 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 141 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 142 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 143 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 144 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 145 * Added Host Based Discovery Phy Event data. 146 * Added defines for ProductID Product field 147 * (MPI2_FW_HEADER_PID_). 148 * Modified values for SAS ProductID Family 149 * (MPI2_FW_HEADER_PID_FAMILY_). 150 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 151 * Added PowerManagementControl Request structures and 152 * defines. 153 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 154 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 155 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 156 * -------------------------------------------------------------------------- 157 */ 158 159 #ifndef MPI2_IOC_H 160 #define MPI2_IOC_H 161 162 /***************************************************************************** 163 * 164 * IOC Messages 165 * 166 *****************************************************************************/ 167 168 /**************************************************************************** 169 * IOCInit message 170 ****************************************************************************/ 171 172 /* IOCInit Request message */ 173 typedef struct _MPI2_IOC_INIT_REQUEST 174 { 175 U8 WhoInit; /* 0x00 */ 176 U8 Reserved1; /* 0x01 */ 177 U8 ChainOffset; /* 0x02 */ 178 U8 Function; /* 0x03 */ 179 U16 Reserved2; /* 0x04 */ 180 U8 Reserved3; /* 0x06 */ 181 U8 MsgFlags; /* 0x07 */ 182 U8 VP_ID; /* 0x08 */ 183 U8 VF_ID; /* 0x09 */ 184 U16 Reserved4; /* 0x0A */ 185 U16 MsgVersion; /* 0x0C */ 186 U16 HeaderVersion; /* 0x0E */ 187 U32 Reserved5; /* 0x10 */ 188 U16 Reserved6; /* 0x14 */ 189 U8 Reserved7; /* 0x16 */ 190 U8 HostMSIxVectors; /* 0x17 */ 191 U16 Reserved8; /* 0x18 */ 192 U16 SystemRequestFrameSize; /* 0x1A */ 193 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 194 U16 ReplyFreeQueueDepth; /* 0x1E */ 195 U32 SenseBufferAddressHigh; /* 0x20 */ 196 U32 SystemReplyAddressHigh; /* 0x24 */ 197 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 198 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 199 U64 ReplyFreeQueueAddress; /* 0x38 */ 200 U64 TimeStamp; /* 0x40 */ 201 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 202 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 203 204 /* WhoInit values */ 205 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 206 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 207 #define MPI2_WHOINIT_ROM_BIOS (0x02) 208 #define MPI2_WHOINIT_PCI_PEER (0x03) 209 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 210 #define MPI2_WHOINIT_MANUFACTURER (0x05) 211 212 /* MsgVersion */ 213 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 214 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 215 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 216 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 217 218 /* HeaderVersion */ 219 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 220 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 221 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 222 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 223 224 /* minimum depth for the Reply Descriptor Post Queue */ 225 #define MPI2_RDPQ_DEPTH_MIN (16) 226 227 228 /* IOCInit Reply message */ 229 typedef struct _MPI2_IOC_INIT_REPLY 230 { 231 U8 WhoInit; /* 0x00 */ 232 U8 Reserved1; /* 0x01 */ 233 U8 MsgLength; /* 0x02 */ 234 U8 Function; /* 0x03 */ 235 U16 Reserved2; /* 0x04 */ 236 U8 Reserved3; /* 0x06 */ 237 U8 MsgFlags; /* 0x07 */ 238 U8 VP_ID; /* 0x08 */ 239 U8 VF_ID; /* 0x09 */ 240 U16 Reserved4; /* 0x0A */ 241 U16 Reserved5; /* 0x0C */ 242 U16 IOCStatus; /* 0x0E */ 243 U32 IOCLogInfo; /* 0x10 */ 244 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 245 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 246 247 248 /**************************************************************************** 249 * IOCFacts message 250 ****************************************************************************/ 251 252 /* IOCFacts Request message */ 253 typedef struct _MPI2_IOC_FACTS_REQUEST 254 { 255 U16 Reserved1; /* 0x00 */ 256 U8 ChainOffset; /* 0x02 */ 257 U8 Function; /* 0x03 */ 258 U16 Reserved2; /* 0x04 */ 259 U8 Reserved3; /* 0x06 */ 260 U8 MsgFlags; /* 0x07 */ 261 U8 VP_ID; /* 0x08 */ 262 U8 VF_ID; /* 0x09 */ 263 U16 Reserved4; /* 0x0A */ 264 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 265 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 266 267 268 /* IOCFacts Reply message */ 269 typedef struct _MPI2_IOC_FACTS_REPLY 270 { 271 U16 MsgVersion; /* 0x00 */ 272 U8 MsgLength; /* 0x02 */ 273 U8 Function; /* 0x03 */ 274 U16 HeaderVersion; /* 0x04 */ 275 U8 IOCNumber; /* 0x06 */ 276 U8 MsgFlags; /* 0x07 */ 277 U8 VP_ID; /* 0x08 */ 278 U8 VF_ID; /* 0x09 */ 279 U16 Reserved1; /* 0x0A */ 280 U16 IOCExceptions; /* 0x0C */ 281 U16 IOCStatus; /* 0x0E */ 282 U32 IOCLogInfo; /* 0x10 */ 283 U8 MaxChainDepth; /* 0x14 */ 284 U8 WhoInit; /* 0x15 */ 285 U8 NumberOfPorts; /* 0x16 */ 286 U8 MaxMSIxVectors; /* 0x17 */ 287 U16 RequestCredit; /* 0x18 */ 288 U16 ProductID; /* 0x1A */ 289 U32 IOCCapabilities; /* 0x1C */ 290 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 291 U16 IOCRequestFrameSize; /* 0x24 */ 292 U16 Reserved3; /* 0x26 */ 293 U16 MaxInitiators; /* 0x28 */ 294 U16 MaxTargets; /* 0x2A */ 295 U16 MaxSasExpanders; /* 0x2C */ 296 U16 MaxEnclosures; /* 0x2E */ 297 U16 ProtocolFlags; /* 0x30 */ 298 U16 HighPriorityCredit; /* 0x32 */ 299 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 300 U8 ReplyFrameSize; /* 0x36 */ 301 U8 MaxVolumes; /* 0x37 */ 302 U16 MaxDevHandle; /* 0x38 */ 303 U16 MaxPersistentEntries; /* 0x3A */ 304 U16 MinDevHandle; /* 0x3C */ 305 U16 Reserved4; /* 0x3E */ 306 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 307 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 308 309 /* MsgVersion */ 310 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 311 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 312 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 313 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 314 315 /* HeaderVersion */ 316 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 317 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 318 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 319 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 320 321 /* IOCExceptions */ 322 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 323 324 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 325 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 326 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 327 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 328 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 329 330 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 331 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 332 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 333 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 334 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 335 336 /* defines for WhoInit field are after the IOCInit Request */ 337 338 /* ProductID field uses MPI2_FW_HEADER_PID_ */ 339 340 /* IOCCapabilities */ 341 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) 342 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 343 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 344 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 345 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 346 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 347 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 348 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 349 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 350 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 351 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 352 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 353 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 354 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 355 356 /* ProtocolFlags */ 357 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 358 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 359 360 361 /**************************************************************************** 362 * PortFacts message 363 ****************************************************************************/ 364 365 /* PortFacts Request message */ 366 typedef struct _MPI2_PORT_FACTS_REQUEST 367 { 368 U16 Reserved1; /* 0x00 */ 369 U8 ChainOffset; /* 0x02 */ 370 U8 Function; /* 0x03 */ 371 U16 Reserved2; /* 0x04 */ 372 U8 PortNumber; /* 0x06 */ 373 U8 MsgFlags; /* 0x07 */ 374 U8 VP_ID; /* 0x08 */ 375 U8 VF_ID; /* 0x09 */ 376 U16 Reserved3; /* 0x0A */ 377 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 378 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 379 380 /* PortFacts Reply message */ 381 typedef struct _MPI2_PORT_FACTS_REPLY 382 { 383 U16 Reserved1; /* 0x00 */ 384 U8 MsgLength; /* 0x02 */ 385 U8 Function; /* 0x03 */ 386 U16 Reserved2; /* 0x04 */ 387 U8 PortNumber; /* 0x06 */ 388 U8 MsgFlags; /* 0x07 */ 389 U8 VP_ID; /* 0x08 */ 390 U8 VF_ID; /* 0x09 */ 391 U16 Reserved3; /* 0x0A */ 392 U16 Reserved4; /* 0x0C */ 393 U16 IOCStatus; /* 0x0E */ 394 U32 IOCLogInfo; /* 0x10 */ 395 U8 Reserved5; /* 0x14 */ 396 U8 PortType; /* 0x15 */ 397 U16 Reserved6; /* 0x16 */ 398 U16 MaxPostedCmdBuffers; /* 0x18 */ 399 U16 Reserved7; /* 0x1A */ 400 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 401 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 402 403 /* PortType values */ 404 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 405 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 406 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 407 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 408 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 409 410 411 /**************************************************************************** 412 * PortEnable message 413 ****************************************************************************/ 414 415 /* PortEnable Request message */ 416 typedef struct _MPI2_PORT_ENABLE_REQUEST 417 { 418 U16 Reserved1; /* 0x00 */ 419 U8 ChainOffset; /* 0x02 */ 420 U8 Function; /* 0x03 */ 421 U8 Reserved2; /* 0x04 */ 422 U8 PortFlags; /* 0x05 */ 423 U8 Reserved3; /* 0x06 */ 424 U8 MsgFlags; /* 0x07 */ 425 U8 VP_ID; /* 0x08 */ 426 U8 VF_ID; /* 0x09 */ 427 U16 Reserved4; /* 0x0A */ 428 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 429 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 430 431 432 /* PortEnable Reply message */ 433 typedef struct _MPI2_PORT_ENABLE_REPLY 434 { 435 U16 Reserved1; /* 0x00 */ 436 U8 MsgLength; /* 0x02 */ 437 U8 Function; /* 0x03 */ 438 U8 Reserved2; /* 0x04 */ 439 U8 PortFlags; /* 0x05 */ 440 U8 Reserved3; /* 0x06 */ 441 U8 MsgFlags; /* 0x07 */ 442 U8 VP_ID; /* 0x08 */ 443 U8 VF_ID; /* 0x09 */ 444 U16 Reserved4; /* 0x0A */ 445 U16 Reserved5; /* 0x0C */ 446 U16 IOCStatus; /* 0x0E */ 447 U32 IOCLogInfo; /* 0x10 */ 448 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 449 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 450 451 452 /**************************************************************************** 453 * EventNotification message 454 ****************************************************************************/ 455 456 /* EventNotification Request message */ 457 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 458 459 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 460 { 461 U16 Reserved1; /* 0x00 */ 462 U8 ChainOffset; /* 0x02 */ 463 U8 Function; /* 0x03 */ 464 U16 Reserved2; /* 0x04 */ 465 U8 Reserved3; /* 0x06 */ 466 U8 MsgFlags; /* 0x07 */ 467 U8 VP_ID; /* 0x08 */ 468 U8 VF_ID; /* 0x09 */ 469 U16 Reserved4; /* 0x0A */ 470 U32 Reserved5; /* 0x0C */ 471 U32 Reserved6; /* 0x10 */ 472 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 473 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 474 U16 Reserved7; /* 0x26 */ 475 U32 Reserved8; /* 0x28 */ 476 } MPI2_EVENT_NOTIFICATION_REQUEST, 477 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 478 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 479 480 481 /* EventNotification Reply message */ 482 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 483 { 484 U16 EventDataLength; /* 0x00 */ 485 U8 MsgLength; /* 0x02 */ 486 U8 Function; /* 0x03 */ 487 U16 Reserved1; /* 0x04 */ 488 U8 AckRequired; /* 0x06 */ 489 U8 MsgFlags; /* 0x07 */ 490 U8 VP_ID; /* 0x08 */ 491 U8 VF_ID; /* 0x09 */ 492 U16 Reserved2; /* 0x0A */ 493 U16 Reserved3; /* 0x0C */ 494 U16 IOCStatus; /* 0x0E */ 495 U32 IOCLogInfo; /* 0x10 */ 496 U16 Event; /* 0x14 */ 497 U16 Reserved4; /* 0x16 */ 498 U32 EventContext; /* 0x18 */ 499 U32 EventData[1]; /* 0x1C */ 500 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 501 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 502 503 /* AckRequired */ 504 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 505 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 506 507 /* Event */ 508 #define MPI2_EVENT_LOG_DATA (0x0001) 509 #define MPI2_EVENT_STATE_CHANGE (0x0002) 510 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 511 #define MPI2_EVENT_EVENT_CHANGE (0x000A) 512 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 513 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 514 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 515 #define MPI2_EVENT_SAS_DISCOVERY (0x0016) 516 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 517 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 518 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 519 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 520 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 521 #define MPI2_EVENT_IR_VOLUME (0x001E) 522 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 523 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 524 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 525 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 526 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 527 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 528 #define MPI2_EVENT_SAS_QUIESCE (0x0025) 529 530 531 /* Log Entry Added Event data */ 532 533 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 534 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 535 536 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 537 { 538 U64 TimeStamp; /* 0x00 */ 539 U32 Reserved1; /* 0x08 */ 540 U16 LogSequence; /* 0x0C */ 541 U16 LogEntryQualifier; /* 0x0E */ 542 U8 VP_ID; /* 0x10 */ 543 U8 VF_ID; /* 0x11 */ 544 U16 Reserved2; /* 0x12 */ 545 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 546 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 547 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 548 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 549 550 /* GPIO Interrupt Event data */ 551 552 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 553 { 554 U8 GPIONum; /* 0x00 */ 555 U8 Reserved1; /* 0x01 */ 556 U16 Reserved2; /* 0x02 */ 557 } MPI2_EVENT_DATA_GPIO_INTERRUPT, 558 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 559 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 560 561 /* Hard Reset Received Event data */ 562 563 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 564 { 565 U8 Reserved1; /* 0x00 */ 566 U8 Port; /* 0x01 */ 567 U16 Reserved2; /* 0x02 */ 568 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 569 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 570 Mpi2EventDataHardResetReceived_t, 571 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 572 573 /* Task Set Full Event data */ 574 /* this event is obsolete */ 575 576 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 577 { 578 U16 DevHandle; /* 0x00 */ 579 U16 CurrentDepth; /* 0x02 */ 580 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 581 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 582 583 584 /* SAS Device Status Change Event data */ 585 586 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 587 { 588 U16 TaskTag; /* 0x00 */ 589 U8 ReasonCode; /* 0x02 */ 590 U8 Reserved1; /* 0x03 */ 591 U8 ASC; /* 0x04 */ 592 U8 ASCQ; /* 0x05 */ 593 U16 DevHandle; /* 0x06 */ 594 U32 Reserved2; /* 0x08 */ 595 U64 SASAddress; /* 0x0C */ 596 U8 LUN[8]; /* 0x14 */ 597 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 598 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 599 Mpi2EventDataSasDeviceStatusChange_t, 600 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 601 602 /* SAS Device Status Change Event data ReasonCode values */ 603 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 604 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 605 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 606 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 607 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 608 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 609 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 610 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 611 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 612 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 613 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 614 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 615 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 616 617 618 /* Integrated RAID Operation Status Event data */ 619 620 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 621 { 622 U16 VolDevHandle; /* 0x00 */ 623 U16 Reserved1; /* 0x02 */ 624 U8 RAIDOperation; /* 0x04 */ 625 U8 PercentComplete; /* 0x05 */ 626 U16 Reserved2; /* 0x06 */ 627 U32 Resereved3; /* 0x08 */ 628 } MPI2_EVENT_DATA_IR_OPERATION_STATUS, 629 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 630 Mpi2EventDataIrOperationStatus_t, 631 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 632 633 /* Integrated RAID Operation Status Event data RAIDOperation values */ 634 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 635 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 636 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 637 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 638 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 639 640 641 /* Integrated RAID Volume Event data */ 642 643 typedef struct _MPI2_EVENT_DATA_IR_VOLUME 644 { 645 U16 VolDevHandle; /* 0x00 */ 646 U8 ReasonCode; /* 0x02 */ 647 U8 Reserved1; /* 0x03 */ 648 U32 NewValue; /* 0x04 */ 649 U32 PreviousValue; /* 0x08 */ 650 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 651 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 652 653 /* Integrated RAID Volume Event data ReasonCode values */ 654 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 655 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 656 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 657 658 659 /* Integrated RAID Physical Disk Event data */ 660 661 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 662 { 663 U16 Reserved1; /* 0x00 */ 664 U8 ReasonCode; /* 0x02 */ 665 U8 PhysDiskNum; /* 0x03 */ 666 U16 PhysDiskDevHandle; /* 0x04 */ 667 U16 Reserved2; /* 0x06 */ 668 U16 Slot; /* 0x08 */ 669 U16 EnclosureHandle; /* 0x0A */ 670 U32 NewValue; /* 0x0C */ 671 U32 PreviousValue; /* 0x10 */ 672 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 673 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 674 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 675 676 /* Integrated RAID Physical Disk Event data ReasonCode values */ 677 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 678 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 679 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 680 681 682 /* Integrated RAID Configuration Change List Event data */ 683 684 /* 685 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 686 * one and check NumElements at runtime. 687 */ 688 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 689 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 690 #endif 691 692 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 693 { 694 U16 ElementFlags; /* 0x00 */ 695 U16 VolDevHandle; /* 0x02 */ 696 U8 ReasonCode; /* 0x04 */ 697 U8 PhysDiskNum; /* 0x05 */ 698 U16 PhysDiskDevHandle; /* 0x06 */ 699 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 700 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 701 702 /* IR Configuration Change List Event data ElementFlags values */ 703 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 704 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 705 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 706 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 707 708 /* IR Configuration Change List Event data ReasonCode values */ 709 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 710 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 711 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 712 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 713 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 714 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 715 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 716 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 717 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 718 719 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 720 { 721 U8 NumElements; /* 0x00 */ 722 U8 Reserved1; /* 0x01 */ 723 U8 Reserved2; /* 0x02 */ 724 U8 ConfigNum; /* 0x03 */ 725 U32 Flags; /* 0x04 */ 726 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 727 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 728 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 729 Mpi2EventDataIrConfigChangeList_t, 730 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 731 732 /* IR Configuration Change List Event data Flags values */ 733 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 734 735 736 /* SAS Discovery Event data */ 737 738 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 739 { 740 U8 Flags; /* 0x00 */ 741 U8 ReasonCode; /* 0x01 */ 742 U8 PhysicalPort; /* 0x02 */ 743 U8 Reserved1; /* 0x03 */ 744 U32 DiscoveryStatus; /* 0x04 */ 745 } MPI2_EVENT_DATA_SAS_DISCOVERY, 746 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 747 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 748 749 /* SAS Discovery Event data Flags values */ 750 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 751 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 752 753 /* SAS Discovery Event data ReasonCode values */ 754 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 755 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 756 757 /* SAS Discovery Event data DiscoveryStatus values */ 758 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 759 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 760 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 761 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 762 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 763 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 764 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 765 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 766 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 767 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 768 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 769 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 770 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 771 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 772 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 773 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 774 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 775 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 776 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 777 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 778 779 780 /* SAS Broadcast Primitive Event data */ 781 782 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 783 { 784 U8 PhyNum; /* 0x00 */ 785 U8 Port; /* 0x01 */ 786 U8 PortWidth; /* 0x02 */ 787 U8 Primitive; /* 0x03 */ 788 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 789 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 790 Mpi2EventDataSasBroadcastPrimitive_t, 791 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 792 793 /* defines for the Primitive field */ 794 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 795 #define MPI2_EVENT_PRIMITIVE_SES (0x02) 796 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 797 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 798 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 799 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 800 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 801 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 802 803 804 /* SAS Initiator Device Status Change Event data */ 805 806 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 807 { 808 U8 ReasonCode; /* 0x00 */ 809 U8 PhysicalPort; /* 0x01 */ 810 U16 DevHandle; /* 0x02 */ 811 U64 SASAddress; /* 0x04 */ 812 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 813 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 814 Mpi2EventDataSasInitDevStatusChange_t, 815 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 816 817 /* SAS Initiator Device Status Change event ReasonCode values */ 818 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 819 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 820 821 822 /* SAS Initiator Device Table Overflow Event data */ 823 824 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 825 { 826 U16 MaxInit; /* 0x00 */ 827 U16 CurrentInit; /* 0x02 */ 828 U64 SASAddress; /* 0x04 */ 829 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 830 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 831 Mpi2EventDataSasInitTableOverflow_t, 832 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 833 834 835 /* SAS Topology Change List Event data */ 836 837 /* 838 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 839 * one and check NumEntries at runtime. 840 */ 841 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 842 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 843 #endif 844 845 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 846 { 847 U16 AttachedDevHandle; /* 0x00 */ 848 U8 LinkRate; /* 0x02 */ 849 U8 PhyStatus; /* 0x03 */ 850 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 851 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 852 853 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 854 { 855 U16 EnclosureHandle; /* 0x00 */ 856 U16 ExpanderDevHandle; /* 0x02 */ 857 U8 NumPhys; /* 0x04 */ 858 U8 Reserved1; /* 0x05 */ 859 U16 Reserved2; /* 0x06 */ 860 U8 NumEntries; /* 0x08 */ 861 U8 StartPhyNum; /* 0x09 */ 862 U8 ExpStatus; /* 0x0A */ 863 U8 PhysicalPort; /* 0x0B */ 864 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 865 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 866 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 867 Mpi2EventDataSasTopologyChangeList_t, 868 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 869 870 /* values for the ExpStatus field */ 871 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 872 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 873 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 874 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 875 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 876 877 /* defines for the LinkRate field */ 878 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 879 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 880 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 881 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 882 883 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 884 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 885 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 886 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 887 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 888 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 889 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 890 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 891 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 892 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 893 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) 894 895 /* values for the PhyStatus field */ 896 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 897 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 898 /* values for the PhyStatus ReasonCode sub-field */ 899 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 900 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 901 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 902 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 903 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 904 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 905 906 907 /* SAS Enclosure Device Status Change Event data */ 908 909 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 910 { 911 U16 EnclosureHandle; /* 0x00 */ 912 U8 ReasonCode; /* 0x02 */ 913 U8 PhysicalPort; /* 0x03 */ 914 U64 EnclosureLogicalID; /* 0x04 */ 915 U16 NumSlots; /* 0x0C */ 916 U16 StartSlot; /* 0x0E */ 917 U32 PhyBits; /* 0x10 */ 918 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 919 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 920 Mpi2EventDataSasEnclDevStatusChange_t, 921 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; 922 923 /* SAS Enclosure Device Status Change event ReasonCode values */ 924 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 925 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 926 927 928 /* SAS PHY Counter Event data */ 929 930 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 931 { 932 U64 TimeStamp; /* 0x00 */ 933 U32 Reserved1; /* 0x08 */ 934 U8 PhyEventCode; /* 0x0C */ 935 U8 PhyNum; /* 0x0D */ 936 U16 Reserved2; /* 0x0E */ 937 U32 PhyEventInfo; /* 0x10 */ 938 U8 CounterType; /* 0x14 */ 939 U8 ThresholdWindow; /* 0x15 */ 940 U8 TimeUnits; /* 0x16 */ 941 U8 Reserved3; /* 0x17 */ 942 U32 EventThreshold; /* 0x18 */ 943 U16 ThresholdFlags; /* 0x1C */ 944 U16 Reserved4; /* 0x1E */ 945 } MPI2_EVENT_DATA_SAS_PHY_COUNTER, 946 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 947 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 948 949 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 950 951 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 952 953 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 954 955 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 956 957 958 /* SAS Quiesce Event data */ 959 960 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 961 { 962 U8 ReasonCode; /* 0x00 */ 963 U8 Reserved1; /* 0x01 */ 964 U16 Reserved2; /* 0x02 */ 965 U32 Reserved3; /* 0x04 */ 966 } MPI2_EVENT_DATA_SAS_QUIESCE, 967 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 968 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 969 970 /* SAS Quiesce Event data ReasonCode values */ 971 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 972 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 973 974 975 /* Host Based Discovery Phy Event data */ 976 977 typedef struct _MPI2_EVENT_HBD_PHY_SAS 978 { 979 U8 Flags; /* 0x00 */ 980 U8 NegotiatedLinkRate; /* 0x01 */ 981 U8 PhyNum; /* 0x02 */ 982 U8 PhysicalPort; /* 0x03 */ 983 U32 Reserved1; /* 0x04 */ 984 U8 InitialFrame[28]; /* 0x08 */ 985 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 986 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 987 988 /* values for the Flags field */ 989 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 990 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 991 992 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 993 994 typedef union _MPI2_EVENT_HBD_DESCRIPTOR 995 { 996 MPI2_EVENT_HBD_PHY_SAS Sas; 997 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 998 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 999 1000 typedef struct _MPI2_EVENT_DATA_HBD_PHY 1001 { 1002 U8 DescriptorType; /* 0x00 */ 1003 U8 Reserved1; /* 0x01 */ 1004 U16 Reserved2; /* 0x02 */ 1005 U32 Reserved3; /* 0x04 */ 1006 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 1007 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 1008 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 1009 1010 /* values for the DescriptorType field */ 1011 #define MPI2_EVENT_HBD_DT_SAS (0x01) 1012 1013 1014 1015 /**************************************************************************** 1016 * EventAck message 1017 ****************************************************************************/ 1018 1019 /* EventAck Request message */ 1020 typedef struct _MPI2_EVENT_ACK_REQUEST 1021 { 1022 U16 Reserved1; /* 0x00 */ 1023 U8 ChainOffset; /* 0x02 */ 1024 U8 Function; /* 0x03 */ 1025 U16 Reserved2; /* 0x04 */ 1026 U8 Reserved3; /* 0x06 */ 1027 U8 MsgFlags; /* 0x07 */ 1028 U8 VP_ID; /* 0x08 */ 1029 U8 VF_ID; /* 0x09 */ 1030 U16 Reserved4; /* 0x0A */ 1031 U16 Event; /* 0x0C */ 1032 U16 Reserved5; /* 0x0E */ 1033 U32 EventContext; /* 0x10 */ 1034 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 1035 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 1036 1037 1038 /* EventAck Reply message */ 1039 typedef struct _MPI2_EVENT_ACK_REPLY 1040 { 1041 U16 Reserved1; /* 0x00 */ 1042 U8 MsgLength; /* 0x02 */ 1043 U8 Function; /* 0x03 */ 1044 U16 Reserved2; /* 0x04 */ 1045 U8 Reserved3; /* 0x06 */ 1046 U8 MsgFlags; /* 0x07 */ 1047 U8 VP_ID; /* 0x08 */ 1048 U8 VF_ID; /* 0x09 */ 1049 U16 Reserved4; /* 0x0A */ 1050 U16 Reserved5; /* 0x0C */ 1051 U16 IOCStatus; /* 0x0E */ 1052 U32 IOCLogInfo; /* 0x10 */ 1053 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1054 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1055 1056 1057 /**************************************************************************** 1058 * FWDownload message 1059 ****************************************************************************/ 1060 1061 /* MPI v2.0 FWDownload Request message */ 1062 typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1063 { 1064 U8 ImageType; /* 0x00 */ 1065 U8 Reserved1; /* 0x01 */ 1066 U8 ChainOffset; /* 0x02 */ 1067 U8 Function; /* 0x03 */ 1068 U16 Reserved2; /* 0x04 */ 1069 U8 Reserved3; /* 0x06 */ 1070 U8 MsgFlags; /* 0x07 */ 1071 U8 VP_ID; /* 0x08 */ 1072 U8 VF_ID; /* 0x09 */ 1073 U16 Reserved4; /* 0x0A */ 1074 U32 TotalImageSize; /* 0x0C */ 1075 U32 Reserved5; /* 0x10 */ 1076 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1077 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1078 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1079 1080 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1081 1082 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1083 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1084 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1085 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1086 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1087 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1088 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1089 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1090 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1091 1092 /* MPI v2.0 FWDownload TransactionContext Element */ 1093 typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1094 { 1095 U8 Reserved1; /* 0x00 */ 1096 U8 ContextSize; /* 0x01 */ 1097 U8 DetailsLength; /* 0x02 */ 1098 U8 Flags; /* 0x03 */ 1099 U32 Reserved2; /* 0x04 */ 1100 U32 ImageOffset; /* 0x08 */ 1101 U32 ImageSize; /* 0x0C */ 1102 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1103 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1104 1105 1106 /* MPI v2.5 FWDownload Request message */ 1107 typedef struct _MPI25_FW_DOWNLOAD_REQUEST 1108 { 1109 U8 ImageType; /* 0x00 */ 1110 U8 Reserved1; /* 0x01 */ 1111 U8 ChainOffset; /* 0x02 */ 1112 U8 Function; /* 0x03 */ 1113 U16 Reserved2; /* 0x04 */ 1114 U8 Reserved3; /* 0x06 */ 1115 U8 MsgFlags; /* 0x07 */ 1116 U8 VP_ID; /* 0x08 */ 1117 U8 VF_ID; /* 0x09 */ 1118 U16 Reserved4; /* 0x0A */ 1119 U32 TotalImageSize; /* 0x0C */ 1120 U32 Reserved5; /* 0x10 */ 1121 U32 Reserved6; /* 0x14 */ 1122 U32 ImageOffset; /* 0x18 */ 1123 U32 ImageSize; /* 0x1C */ 1124 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1125 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST, 1126 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest; 1127 1128 1129 /* FWDownload Reply message */ 1130 typedef struct _MPI2_FW_DOWNLOAD_REPLY 1131 { 1132 U8 ImageType; /* 0x00 */ 1133 U8 Reserved1; /* 0x01 */ 1134 U8 MsgLength; /* 0x02 */ 1135 U8 Function; /* 0x03 */ 1136 U16 Reserved2; /* 0x04 */ 1137 U8 Reserved3; /* 0x06 */ 1138 U8 MsgFlags; /* 0x07 */ 1139 U8 VP_ID; /* 0x08 */ 1140 U8 VF_ID; /* 0x09 */ 1141 U16 Reserved4; /* 0x0A */ 1142 U16 Reserved5; /* 0x0C */ 1143 U16 IOCStatus; /* 0x0E */ 1144 U32 IOCLogInfo; /* 0x10 */ 1145 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1146 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1147 1148 1149 /**************************************************************************** 1150 * FWUpload message 1151 ****************************************************************************/ 1152 1153 /* MPI v2.0 FWUpload Request message */ 1154 typedef struct _MPI2_FW_UPLOAD_REQUEST 1155 { 1156 U8 ImageType; /* 0x00 */ 1157 U8 Reserved1; /* 0x01 */ 1158 U8 ChainOffset; /* 0x02 */ 1159 U8 Function; /* 0x03 */ 1160 U16 Reserved2; /* 0x04 */ 1161 U8 Reserved3; /* 0x06 */ 1162 U8 MsgFlags; /* 0x07 */ 1163 U8 VP_ID; /* 0x08 */ 1164 U8 VF_ID; /* 0x09 */ 1165 U16 Reserved4; /* 0x0A */ 1166 U32 Reserved5; /* 0x0C */ 1167 U32 Reserved6; /* 0x10 */ 1168 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1169 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1170 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1171 1172 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1173 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1174 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1175 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1176 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1177 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1178 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1179 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1180 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1181 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1182 1183 /* MPI v2.0 FWUpload TransactionContext Element */ 1184 typedef struct _MPI2_FW_UPLOAD_TCSGE 1185 { 1186 U8 Reserved1; /* 0x00 */ 1187 U8 ContextSize; /* 0x01 */ 1188 U8 DetailsLength; /* 0x02 */ 1189 U8 Flags; /* 0x03 */ 1190 U32 Reserved2; /* 0x04 */ 1191 U32 ImageOffset; /* 0x08 */ 1192 U32 ImageSize; /* 0x0C */ 1193 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1194 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1195 1196 1197 /* MPI v2.5 FWUpload Request message */ 1198 typedef struct _MPI25_FW_UPLOAD_REQUEST 1199 { 1200 U8 ImageType; /* 0x00 */ 1201 U8 Reserved1; /* 0x01 */ 1202 U8 ChainOffset; /* 0x02 */ 1203 U8 Function; /* 0x03 */ 1204 U16 Reserved2; /* 0x04 */ 1205 U8 Reserved3; /* 0x06 */ 1206 U8 MsgFlags; /* 0x07 */ 1207 U8 VP_ID; /* 0x08 */ 1208 U8 VF_ID; /* 0x09 */ 1209 U16 Reserved4; /* 0x0A */ 1210 U32 Reserved5; /* 0x0C */ 1211 U32 Reserved6; /* 0x10 */ 1212 U32 Reserved7; /* 0x14 */ 1213 U32 ImageOffset; /* 0x18 */ 1214 U32 ImageSize; /* 0x1C */ 1215 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1216 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST, 1217 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t; 1218 1219 1220 /* FWUpload Reply message */ 1221 typedef struct _MPI2_FW_UPLOAD_REPLY 1222 { 1223 U8 ImageType; /* 0x00 */ 1224 U8 Reserved1; /* 0x01 */ 1225 U8 MsgLength; /* 0x02 */ 1226 U8 Function; /* 0x03 */ 1227 U16 Reserved2; /* 0x04 */ 1228 U8 Reserved3; /* 0x06 */ 1229 U8 MsgFlags; /* 0x07 */ 1230 U8 VP_ID; /* 0x08 */ 1231 U8 VF_ID; /* 0x09 */ 1232 U16 Reserved4; /* 0x0A */ 1233 U16 Reserved5; /* 0x0C */ 1234 U16 IOCStatus; /* 0x0E */ 1235 U32 IOCLogInfo; /* 0x10 */ 1236 U32 ActualImageSize; /* 0x14 */ 1237 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1238 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1239 1240 1241 /* FW Image Header */ 1242 typedef struct _MPI2_FW_IMAGE_HEADER 1243 { 1244 U32 Signature; /* 0x00 */ 1245 U32 Signature0; /* 0x04 */ 1246 U32 Signature1; /* 0x08 */ 1247 U32 Signature2; /* 0x0C */ 1248 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1249 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1250 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1251 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1252 U16 VendorID; /* 0x20 */ 1253 U16 ProductID; /* 0x22 */ 1254 U16 ProtocolFlags; /* 0x24 */ 1255 U16 Reserved26; /* 0x26 */ 1256 U32 IOCCapabilities; /* 0x28 */ 1257 U32 ImageSize; /* 0x2C */ 1258 U32 NextImageHeaderOffset; /* 0x30 */ 1259 U32 Checksum; /* 0x34 */ 1260 U32 Reserved38; /* 0x38 */ 1261 U32 Reserved3C; /* 0x3C */ 1262 U32 Reserved40; /* 0x40 */ 1263 U32 Reserved44; /* 0x44 */ 1264 U32 Reserved48; /* 0x48 */ 1265 U32 Reserved4C; /* 0x4C */ 1266 U32 Reserved50; /* 0x50 */ 1267 U32 Reserved54; /* 0x54 */ 1268 U32 Reserved58; /* 0x58 */ 1269 U32 Reserved5C; /* 0x5C */ 1270 U32 Reserved60; /* 0x60 */ 1271 U32 FirmwareVersionNameWhat; /* 0x64 */ 1272 U8 FirmwareVersionName[32]; /* 0x68 */ 1273 U32 VendorNameWhat; /* 0x88 */ 1274 U8 VendorName[32]; /* 0x8C */ 1275 U32 PackageNameWhat; /* 0x88 */ 1276 U8 PackageName[32]; /* 0x8C */ 1277 U32 ReservedD0; /* 0xD0 */ 1278 U32 ReservedD4; /* 0xD4 */ 1279 U32 ReservedD8; /* 0xD8 */ 1280 U32 ReservedDC; /* 0xDC */ 1281 U32 ReservedE0; /* 0xE0 */ 1282 U32 ReservedE4; /* 0xE4 */ 1283 U32 ReservedE8; /* 0xE8 */ 1284 U32 ReservedEC; /* 0xEC */ 1285 U32 ReservedF0; /* 0xF0 */ 1286 U32 ReservedF4; /* 0xF4 */ 1287 U32 ReservedF8; /* 0xF8 */ 1288 U32 ReservedFC; /* 0xFC */ 1289 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1290 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1291 1292 /* Signature field */ 1293 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1294 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1295 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1296 1297 /* Signature0 field */ 1298 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1299 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1300 1301 /* Signature1 field */ 1302 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1303 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1304 1305 /* Signature2 field */ 1306 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1307 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1308 1309 1310 /* defines for using the ProductID field */ 1311 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1312 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1313 1314 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1315 #define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1316 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1317 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1318 1319 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1320 /* SAS ProductID Family bits */ 1321 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1322 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1323 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) 1324 1325 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1326 1327 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1328 1329 1330 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1331 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1332 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1333 1334 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1335 1336 #define MPI2_FW_HEADER_SIZE (0x100) 1337 1338 1339 /* Extended Image Header */ 1340 typedef struct _MPI2_EXT_IMAGE_HEADER 1341 1342 { 1343 U8 ImageType; /* 0x00 */ 1344 U8 Reserved1; /* 0x01 */ 1345 U16 Reserved2; /* 0x02 */ 1346 U32 Checksum; /* 0x04 */ 1347 U32 ImageSize; /* 0x08 */ 1348 U32 NextImageHeaderOffset; /* 0x0C */ 1349 U32 PackageVersion; /* 0x10 */ 1350 U32 Reserved3; /* 0x14 */ 1351 U32 Reserved4; /* 0x18 */ 1352 U32 Reserved5; /* 0x1C */ 1353 U8 IdentifyString[32]; /* 0x20 */ 1354 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1355 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1356 1357 /* useful offsets */ 1358 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1359 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1360 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1361 1362 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1363 1364 /* defines for the ImageType field */ 1365 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1366 #define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1367 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1368 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1369 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1370 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1371 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1372 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1373 1374 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID) 1375 1376 1377 1378 /* FLASH Layout Extended Image Data */ 1379 1380 /* 1381 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1382 * one and check RegionsPerLayout at runtime. 1383 */ 1384 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1385 #define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1386 #endif 1387 1388 /* 1389 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1390 * one and check NumberOfLayouts at runtime. 1391 */ 1392 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1393 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1394 #endif 1395 1396 typedef struct _MPI2_FLASH_REGION 1397 { 1398 U8 RegionType; /* 0x00 */ 1399 U8 Reserved1; /* 0x01 */ 1400 U16 Reserved2; /* 0x02 */ 1401 U32 RegionOffset; /* 0x04 */ 1402 U32 RegionSize; /* 0x08 */ 1403 U32 Reserved3; /* 0x0C */ 1404 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1405 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1406 1407 typedef struct _MPI2_FLASH_LAYOUT 1408 { 1409 U32 FlashSize; /* 0x00 */ 1410 U32 Reserved1; /* 0x04 */ 1411 U32 Reserved2; /* 0x08 */ 1412 U32 Reserved3; /* 0x0C */ 1413 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1414 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1415 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1416 1417 typedef struct _MPI2_FLASH_LAYOUT_DATA 1418 { 1419 U8 ImageRevision; /* 0x00 */ 1420 U8 Reserved1; /* 0x01 */ 1421 U8 SizeOfRegion; /* 0x02 */ 1422 U8 Reserved2; /* 0x03 */ 1423 U16 NumberOfLayouts; /* 0x04 */ 1424 U16 RegionsPerLayout; /* 0x06 */ 1425 U16 MinimumSectorAlignment; /* 0x08 */ 1426 U16 Reserved3; /* 0x0A */ 1427 U32 Reserved4; /* 0x0C */ 1428 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1429 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1430 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1431 1432 /* defines for the RegionType field */ 1433 #define MPI2_FLASH_REGION_UNUSED (0x00) 1434 #define MPI2_FLASH_REGION_FIRMWARE (0x01) 1435 #define MPI2_FLASH_REGION_BIOS (0x02) 1436 #define MPI2_FLASH_REGION_NVDATA (0x03) 1437 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1438 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1439 #define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1440 #define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1441 #define MPI2_FLASH_REGION_MEGARAID (0x09) 1442 #define MPI2_FLASH_REGION_INIT (0x0A) 1443 1444 /* ImageRevision */ 1445 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1446 1447 1448 1449 /* Supported Devices Extended Image Data */ 1450 1451 /* 1452 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1453 * one and check NumberOfDevices at runtime. 1454 */ 1455 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1456 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1457 #endif 1458 1459 typedef struct _MPI2_SUPPORTED_DEVICE 1460 { 1461 U16 DeviceID; /* 0x00 */ 1462 U16 VendorID; /* 0x02 */ 1463 U16 DeviceIDMask; /* 0x04 */ 1464 U16 Reserved1; /* 0x06 */ 1465 U8 LowPCIRev; /* 0x08 */ 1466 U8 HighPCIRev; /* 0x09 */ 1467 U16 Reserved2; /* 0x0A */ 1468 U32 Reserved3; /* 0x0C */ 1469 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1470 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1471 1472 typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1473 { 1474 U8 ImageRevision; /* 0x00 */ 1475 U8 Reserved1; /* 0x01 */ 1476 U8 NumberOfDevices; /* 0x02 */ 1477 U8 Reserved2; /* 0x03 */ 1478 U32 Reserved3; /* 0x04 */ 1479 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1480 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1481 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1482 1483 /* ImageRevision */ 1484 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1485 1486 1487 /* Init Extended Image Data */ 1488 1489 typedef struct _MPI2_INIT_IMAGE_FOOTER 1490 1491 { 1492 U32 BootFlags; /* 0x00 */ 1493 U32 ImageSize; /* 0x04 */ 1494 U32 Signature0; /* 0x08 */ 1495 U32 Signature1; /* 0x0C */ 1496 U32 Signature2; /* 0x10 */ 1497 U32 ResetVector; /* 0x14 */ 1498 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1499 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1500 1501 /* defines for the BootFlags field */ 1502 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1503 1504 /* defines for the ImageSize field */ 1505 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1506 1507 /* defines for the Signature0 field */ 1508 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1509 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1510 1511 /* defines for the Signature1 field */ 1512 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1513 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1514 1515 /* defines for the Signature2 field */ 1516 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1517 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1518 1519 /* Signature fields as individual bytes */ 1520 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1521 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1522 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1523 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1524 1525 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1526 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1527 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1528 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1529 1530 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1531 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1532 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1533 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1534 1535 /* defines for the ResetVector field */ 1536 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1537 1538 1539 /**************************************************************************** 1540 * PowerManagementControl message 1541 ****************************************************************************/ 1542 1543 /* PowerManagementControl Request message */ 1544 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 1545 { 1546 U8 Feature; /* 0x00 */ 1547 U8 Reserved1; /* 0x01 */ 1548 U8 ChainOffset; /* 0x02 */ 1549 U8 Function; /* 0x03 */ 1550 U16 Reserved2; /* 0x04 */ 1551 U8 Reserved3; /* 0x06 */ 1552 U8 MsgFlags; /* 0x07 */ 1553 U8 VP_ID; /* 0x08 */ 1554 U8 VF_ID; /* 0x09 */ 1555 U16 Reserved4; /* 0x0A */ 1556 U8 Parameter1; /* 0x0C */ 1557 U8 Parameter2; /* 0x0D */ 1558 U8 Parameter3; /* 0x0E */ 1559 U8 Parameter4; /* 0x0F */ 1560 U32 Reserved5; /* 0x10 */ 1561 U32 Reserved6; /* 0x14 */ 1562 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1563 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1564 1565 /* defines for the Feature field */ 1566 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1567 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1568 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) 1569 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1570 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1571 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1572 1573 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1574 /* Parameter1 contains a PHY number */ 1575 /* Parameter2 indicates power condition action using these defines */ 1576 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1577 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1578 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1579 /* Parameter3 and Parameter4 are reserved */ 1580 1581 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 1582 /* Parameter1 contains SAS port width modulation group number */ 1583 /* Parameter2 indicates IOC action using these defines */ 1584 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1585 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1586 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1587 /* Parameter3 indicates desired modulation level using these defines */ 1588 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1589 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1590 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1591 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1592 /* Parameter4 is reserved */ 1593 1594 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1595 /* Parameter1 indicates desired PCIe link speed using these defines */ 1596 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) 1597 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) 1598 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) 1599 /* Parameter2 indicates desired PCIe link width using these defines */ 1600 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) 1601 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) 1602 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) 1603 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) 1604 /* Parameter3 and Parameter4 are reserved */ 1605 1606 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1607 /* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1608 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1609 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1610 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1611 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1612 /* Parameter2, Parameter3, and Parameter4 are reserved */ 1613 1614 1615 /* PowerManagementControl Reply message */ 1616 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 1617 { 1618 U8 Feature; /* 0x00 */ 1619 U8 Reserved1; /* 0x01 */ 1620 U8 MsgLength; /* 0x02 */ 1621 U8 Function; /* 0x03 */ 1622 U16 Reserved2; /* 0x04 */ 1623 U8 Reserved3; /* 0x06 */ 1624 U8 MsgFlags; /* 0x07 */ 1625 U8 VP_ID; /* 0x08 */ 1626 U8 VF_ID; /* 0x09 */ 1627 U16 Reserved4; /* 0x0A */ 1628 U16 Reserved5; /* 0x0C */ 1629 U16 IOCStatus; /* 0x0E */ 1630 U32 IOCLogInfo; /* 0x10 */ 1631 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1632 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1633 1634 1635 #endif 1636