1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2000 to 2009, LSI Corporation.
24 * All rights reserved.
25 *
26 * Redistribution and use in source and binary forms of all code within
27 * this file that is exclusively owned by LSI, with or without
28 * modification, is permitted provided that, in addition to the CDDL 1.0
29 * License requirements, the following conditions are met:
30 *
31 * Neither the name of the author nor the names of its contributors may be
32 * used to endorse or promote products derived from this software without
33 * specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
38 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
39 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
41 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
42 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
43 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
45 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46 * DAMAGE.
47 */
48
49 /*
50 * Name: mpi2_ioc.h
51 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
52 * Creation Date: October 11, 2006
53 *
54 * mpi2_ioc.h Version: 02.00.12
55 *
56 * Version History
57 * ---------------
58 *
59 * Date Version Description
60 * -------- -------- ------------------------------------------------------
61 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
62 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
63 * MaxTargets.
64 * Added TotalImageSize field to FWDownload Request.
65 * Added reserved words to FWUpload Request.
66 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
67 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
68 * request and replaced it with
69 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
70 * Replaced the MinReplyQueueDepth field of the IOCFacts
71 * reply with MaxReplyDescriptorPostQueueDepth.
72 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
73 * depth for the Reply Descriptor Post Queue.
74 * Added SASAddress field to Initiator Device Table
75 * Overflow Event data.
76 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
77 * for SAS Initiator Device Status Change Event data.
78 * Modified Reason Code defines for SAS Topology Change
79 * List Event data, including adding a bit for PHY Vacant
80 * status, and adding a mask for the Reason Code.
81 * Added define for
82 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
83 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
84 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
85 * the IOCFacts Reply.
86 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
87 * Moved MPI2_VERSION_UNION to mpi2.h.
88 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
89 * instead of enables, and added SASBroadcastPrimitiveMasks
90 * field.
91 * Added Log Entry Added Event and related structure.
92 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
93 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
94 * Added MaxVolumes and MaxPersistentEntries fields to
95 * IOCFacts reply.
96 * Added ProtocalFlags and IOCCapabilities fields to
97 * MPI2_FW_IMAGE_HEADER.
98 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
99 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
100 * a U16 (from a U32).
101 * Removed extra 's' from EventMasks name.
102 * 06-27-08 02.00.08 Fixed an offset in a comment.
103 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
104 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
105 * renamed MinReplyFrameSize to ReplyFrameSize.
106 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
107 * Added two new RAIDOperation values for Integrated RAID
108 * Operations Status Event data.
109 * Added four new IR Configuration Change List Event data
110 * ReasonCode values.
111 * Added two new ReasonCode defines for SAS Device Status
112 * Change Event data.
113 * Added three new DiscoveryStatus bits for the SAS
114 * Discovery event data.
115 * Added Multiplexing Status Change bit to the PhyStatus
116 * field of the SAS Topology Change List event data.
117 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
118 * BootFlags are now product-specific.
119 * Added defines for the indivdual signature bytes
120 * for MPI2_INIT_IMAGE_FOOTER.
121 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
122 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
123 * define.
124 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
125 * define.
126 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
127 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
128 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
129 * Added two new reason codes for SAS Device Status Change
130 * Event.
131 * Added new event: SAS PHY Counter.
132 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
133 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
134 * Added new product id family for 2208.
135 * --------------------------------------------------------------------------
136 */
137
138 #ifndef MPI2_IOC_H
139 #define MPI2_IOC_H
140
141 /*****************************************************************************
142 *
143 * IOC Messages
144 *
145 *****************************************************************************/
146
147 /****************************************************************************
148 * IOCInit message
149 ****************************************************************************/
150
151 /* IOCInit Request message */
152 typedef struct _MPI2_IOC_INIT_REQUEST
153 {
154 U8 WhoInit; /* 0x00 */
155 U8 Reserved1; /* 0x01 */
156 U8 ChainOffset; /* 0x02 */
157 U8 Function; /* 0x03 */
158 U16 Reserved2; /* 0x04 */
159 U8 Reserved3; /* 0x06 */
160 U8 MsgFlags; /* 0x07 */
161 U8 VP_ID; /* 0x08 */
162 U8 VF_ID; /* 0x09 */
163 U16 Reserved4; /* 0x0A */
164 U16 MsgVersion; /* 0x0C */
165 U16 HeaderVersion; /* 0x0E */
166 U32 Reserved5; /* 0x10 */
167 U32 Reserved6; /* 0x14 */
168 U16 Reserved7; /* 0x18 */
169 U16 SystemRequestFrameSize; /* 0x1A */
170 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
171 U16 ReplyFreeQueueDepth; /* 0x1E */
172 U32 SenseBufferAddressHigh; /* 0x20 */
173 U32 SystemReplyAddressHigh; /* 0x24 */
174 U64 SystemRequestFrameBaseAddress; /* 0x28 */
175 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
176 U64 ReplyFreeQueueAddress; /* 0x38 */
177 U64 TimeStamp; /* 0x40 */
178 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
179 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
180
181 /* WhoInit values */
182 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
183 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
184 #define MPI2_WHOINIT_ROM_BIOS (0x02)
185 #define MPI2_WHOINIT_PCI_PEER (0x03)
186 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
187 #define MPI2_WHOINIT_MANUFACTURER (0x05)
188
189 /* MsgVersion */
190 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
191 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
192 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
193 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
194
195 /* HeaderVersion */
196 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
197 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
198 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
199 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
200
201 /* minimum depth for the Reply Descriptor Post Queue */
202 #define MPI2_RDPQ_DEPTH_MIN (16)
203
204
205 /* IOCInit Reply message */
206 typedef struct _MPI2_IOC_INIT_REPLY
207 {
208 U8 WhoInit; /* 0x00 */
209 U8 Reserved1; /* 0x01 */
210 U8 MsgLength; /* 0x02 */
211 U8 Function; /* 0x03 */
212 U16 Reserved2; /* 0x04 */
213 U8 Reserved3; /* 0x06 */
214 U8 MsgFlags; /* 0x07 */
215 U8 VP_ID; /* 0x08 */
216 U8 VF_ID; /* 0x09 */
217 U16 Reserved4; /* 0x0A */
218 U16 Reserved5; /* 0x0C */
219 U16 IOCStatus; /* 0x0E */
220 U32 IOCLogInfo; /* 0x10 */
221 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
222 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
223
224
225 /****************************************************************************
226 * IOCFacts message
227 ****************************************************************************/
228
229 /* IOCFacts Request message */
230 typedef struct _MPI2_IOC_FACTS_REQUEST
231 {
232 U16 Reserved1; /* 0x00 */
233 U8 ChainOffset; /* 0x02 */
234 U8 Function; /* 0x03 */
235 U16 Reserved2; /* 0x04 */
236 U8 Reserved3; /* 0x06 */
237 U8 MsgFlags; /* 0x07 */
238 U8 VP_ID; /* 0x08 */
239 U8 VF_ID; /* 0x09 */
240 U16 Reserved4; /* 0x0A */
241 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
242 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
243
244
245 /* IOCFacts Reply message */
246 typedef struct _MPI2_IOC_FACTS_REPLY
247 {
248 U16 MsgVersion; /* 0x00 */
249 U8 MsgLength; /* 0x02 */
250 U8 Function; /* 0x03 */
251 U16 HeaderVersion; /* 0x04 */
252 U8 IOCNumber; /* 0x06 */
253 U8 MsgFlags; /* 0x07 */
254 U8 VP_ID; /* 0x08 */
255 U8 VF_ID; /* 0x09 */
256 U16 Reserved1; /* 0x0A */
257 U16 IOCExceptions; /* 0x0C */
258 U16 IOCStatus; /* 0x0E */
259 U32 IOCLogInfo; /* 0x10 */
260 U8 MaxChainDepth; /* 0x14 */
261 U8 WhoInit; /* 0x15 */
262 U8 NumberOfPorts; /* 0x16 */
263 U8 Reserved2; /* 0x17 */
264 U16 RequestCredit; /* 0x18 */
265 U16 ProductID; /* 0x1A */
266 U32 IOCCapabilities; /* 0x1C */
267 MPI2_VERSION_UNION FWVersion; /* 0x20 */
268 U16 IOCRequestFrameSize; /* 0x24 */
269 U16 Reserved3; /* 0x26 */
270 U16 MaxInitiators; /* 0x28 */
271 U16 MaxTargets; /* 0x2A */
272 U16 MaxSasExpanders; /* 0x2C */
273 U16 MaxEnclosures; /* 0x2E */
274 U16 ProtocolFlags; /* 0x30 */
275 U16 HighPriorityCredit; /* 0x32 */
276 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
277 U8 ReplyFrameSize; /* 0x36 */
278 U8 MaxVolumes; /* 0x37 */
279 U16 MaxDevHandle; /* 0x38 */
280 U16 MaxPersistentEntries; /* 0x3A */
281 U32 Reserved4; /* 0x3C */
282 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
283 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
284
285 /* MsgVersion */
286 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
287 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
288 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
289 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
290
291 /* HeaderVersion */
292 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
293 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
294 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
295 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
296
297 /* IOCExceptions */
298 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
299
300 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
301 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
302 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
303 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
304 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
305
306 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
307 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
308 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
309 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
310 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
311
312 /* defines for WhoInit field are after the IOCInit Request */
313
314 /* ProductID field uses MPI2_FW_HEADER_PID_ */
315
316 /* IOCCapabilities */
317 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
318 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
319 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
320 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
321 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
322 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
323 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
324 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
325 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
326 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
327 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
328 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
329
330 /* ProtocolFlags */
331 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
332 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
333
334
335 /****************************************************************************
336 * PortFacts message
337 ****************************************************************************/
338
339 /* PortFacts Request message */
340 typedef struct _MPI2_PORT_FACTS_REQUEST
341 {
342 U16 Reserved1; /* 0x00 */
343 U8 ChainOffset; /* 0x02 */
344 U8 Function; /* 0x03 */
345 U16 Reserved2; /* 0x04 */
346 U8 PortNumber; /* 0x06 */
347 U8 MsgFlags; /* 0x07 */
348 U8 VP_ID; /* 0x08 */
349 U8 VF_ID; /* 0x09 */
350 U16 Reserved3; /* 0x0A */
351 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
352 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
353
354 /* PortFacts Reply message */
355 typedef struct _MPI2_PORT_FACTS_REPLY
356 {
357 U16 Reserved1; /* 0x00 */
358 U8 MsgLength; /* 0x02 */
359 U8 Function; /* 0x03 */
360 U16 Reserved2; /* 0x04 */
361 U8 PortNumber; /* 0x06 */
362 U8 MsgFlags; /* 0x07 */
363 U8 VP_ID; /* 0x08 */
364 U8 VF_ID; /* 0x09 */
365 U16 Reserved3; /* 0x0A */
366 U16 Reserved4; /* 0x0C */
367 U16 IOCStatus; /* 0x0E */
368 U32 IOCLogInfo; /* 0x10 */
369 U8 Reserved5; /* 0x14 */
370 U8 PortType; /* 0x15 */
371 U16 Reserved6; /* 0x16 */
372 U16 MaxPostedCmdBuffers; /* 0x18 */
373 U16 Reserved7; /* 0x1A */
374 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
375 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
376
377 /* PortType values */
378 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
379 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
380 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
381 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
382 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
383
384
385 /****************************************************************************
386 * PortEnable message
387 ****************************************************************************/
388
389 /* PortEnable Request message */
390 typedef struct _MPI2_PORT_ENABLE_REQUEST
391 {
392 U16 Reserved1; /* 0x00 */
393 U8 ChainOffset; /* 0x02 */
394 U8 Function; /* 0x03 */
395 U8 Reserved2; /* 0x04 */
396 U8 PortFlags; /* 0x05 */
397 U8 Reserved3; /* 0x06 */
398 U8 MsgFlags; /* 0x07 */
399 U8 VP_ID; /* 0x08 */
400 U8 VF_ID; /* 0x09 */
401 U16 Reserved4; /* 0x0A */
402 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
403 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
404
405
406 /* PortEnable Reply message */
407 typedef struct _MPI2_PORT_ENABLE_REPLY
408 {
409 U16 Reserved1; /* 0x00 */
410 U8 MsgLength; /* 0x02 */
411 U8 Function; /* 0x03 */
412 U8 Reserved2; /* 0x04 */
413 U8 PortFlags; /* 0x05 */
414 U8 Reserved3; /* 0x06 */
415 U8 MsgFlags; /* 0x07 */
416 U8 VP_ID; /* 0x08 */
417 U8 VF_ID; /* 0x09 */
418 U16 Reserved4; /* 0x0A */
419 U16 Reserved5; /* 0x0C */
420 U16 IOCStatus; /* 0x0E */
421 U32 IOCLogInfo; /* 0x10 */
422 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
423 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
424
425
426 /****************************************************************************
427 * EventNotification message
428 ****************************************************************************/
429
430 /* EventNotification Request message */
431 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
432
433 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
434 {
435 U16 Reserved1; /* 0x00 */
436 U8 ChainOffset; /* 0x02 */
437 U8 Function; /* 0x03 */
438 U16 Reserved2; /* 0x04 */
439 U8 Reserved3; /* 0x06 */
440 U8 MsgFlags; /* 0x07 */
441 U8 VP_ID; /* 0x08 */
442 U8 VF_ID; /* 0x09 */
443 U16 Reserved4; /* 0x0A */
444 U32 Reserved5; /* 0x0C */
445 U32 Reserved6; /* 0x10 */
446 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
447 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
448 U16 Reserved7; /* 0x26 */
449 U32 Reserved8; /* 0x28 */
450 } MPI2_EVENT_NOTIFICATION_REQUEST,
451 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
452 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
453
454
455 /* EventNotification Reply message */
456 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
457 {
458 U16 EventDataLength; /* 0x00 */
459 U8 MsgLength; /* 0x02 */
460 U8 Function; /* 0x03 */
461 U16 Reserved1; /* 0x04 */
462 U8 AckRequired; /* 0x06 */
463 U8 MsgFlags; /* 0x07 */
464 U8 VP_ID; /* 0x08 */
465 U8 VF_ID; /* 0x09 */
466 U16 Reserved2; /* 0x0A */
467 U16 Reserved3; /* 0x0C */
468 U16 IOCStatus; /* 0x0E */
469 U32 IOCLogInfo; /* 0x10 */
470 U16 Event; /* 0x14 */
471 U16 Reserved4; /* 0x16 */
472 U32 EventContext; /* 0x18 */
473 U32 EventData[1]; /* 0x1C */
474 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
475 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
476
477 /* AckRequired */
478 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
479 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
480
481 /* Event */
482 #define MPI2_EVENT_LOG_DATA (0x0001)
483 #define MPI2_EVENT_STATE_CHANGE (0x0002)
484 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
485 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
486 #define MPI2_EVENT_TASK_SET_FULL (0x000E)
487 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
488 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
489 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
490 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
491 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
492 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
493 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
494 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
495 #define MPI2_EVENT_IR_VOLUME (0x001E)
496 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
497 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
498 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
499 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
500 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
501
502
503 /* Log Entry Added Event data */
504
505 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
506 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
507
508 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
509 {
510 U64 TimeStamp; /* 0x00 */
511 U32 Reserved1; /* 0x08 */
512 U16 LogSequence; /* 0x0C */
513 U16 LogEntryQualifier; /* 0x0E */
514 U8 VP_ID; /* 0x10 */
515 U8 VF_ID; /* 0x11 */
516 U16 Reserved2; /* 0x12 */
517 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
518 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
519 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
520 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
521
522 /* GPIO Interrupt Event data */
523
524 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
525 {
526 U8 GPIONum; /* 0x00 */
527 U8 Reserved1; /* 0x01 */
528 U16 Reserved2; /* 0x02 */
529 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
530 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
531 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
532
533 /* Hard Reset Received Event data */
534
535 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
536 {
537 U8 Reserved1; /* 0x00 */
538 U8 Port; /* 0x01 */
539 U16 Reserved2; /* 0x02 */
540 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
541 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
542 Mpi2EventDataHardResetReceived_t,
543 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
544
545 /* Task Set Full Event data */
546
547 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
548 {
549 U16 DevHandle; /* 0x00 */
550 U16 CurrentDepth; /* 0x02 */
551 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
552 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
553
554
555 /* SAS Device Status Change Event data */
556
557 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
558 {
559 U16 TaskTag; /* 0x00 */
560 U8 ReasonCode; /* 0x02 */
561 U8 Reserved1; /* 0x03 */
562 U8 ASC; /* 0x04 */
563 U8 ASCQ; /* 0x05 */
564 U16 DevHandle; /* 0x06 */
565 U32 Reserved2; /* 0x08 */
566 U64 SASAddress; /* 0x0C */
567 U8 LUN[8]; /* 0x14 */
568 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
569 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
570 Mpi2EventDataSasDeviceStatusChange_t,
571 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
572
573 /* SAS Device Status Change Event data ReasonCode values */
574 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
575 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
576 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
577 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
578 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
579 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
580 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
581 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
582 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
583 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
584 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
585 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
586 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
587
588
589 /* Integrated RAID Operation Status Event data */
590
591 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
592 {
593 U16 VolDevHandle; /* 0x00 */
594 U16 Reserved1; /* 0x02 */
595 U8 RAIDOperation; /* 0x04 */
596 U8 PercentComplete; /* 0x05 */
597 U16 Reserved2; /* 0x06 */
598 U32 Resereved3; /* 0x08 */
599 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
600 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
601 Mpi2EventDataIrOperationStatus_t,
602 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
603
604 /* Integrated RAID Operation Status Event data RAIDOperation values */
605 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
606 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
607 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
608 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
609 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
610
611
612 /* Integrated RAID Volume Event data */
613
614 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
615 {
616 U16 VolDevHandle; /* 0x00 */
617 U8 ReasonCode; /* 0x02 */
618 U8 Reserved1; /* 0x03 */
619 U32 NewValue; /* 0x04 */
620 U32 PreviousValue; /* 0x08 */
621 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
622 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
623
624 /* Integrated RAID Volume Event data ReasonCode values */
625 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
626 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
627 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
628
629
630 /* Integrated RAID Physical Disk Event data */
631
632 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
633 {
634 U16 Reserved1; /* 0x00 */
635 U8 ReasonCode; /* 0x02 */
636 U8 PhysDiskNum; /* 0x03 */
637 U16 PhysDiskDevHandle; /* 0x04 */
638 U16 Reserved2; /* 0x06 */
639 U16 Slot; /* 0x08 */
640 U16 EnclosureHandle; /* 0x0A */
641 U32 NewValue; /* 0x0C */
642 U32 PreviousValue; /* 0x10 */
643 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
644 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
645 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
646
647 /* Integrated RAID Physical Disk Event data ReasonCode values */
648 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
649 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
650 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
651
652
653 /* Integrated RAID Configuration Change List Event data */
654
655 /*
656 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
657 * one and check NumElements at runtime.
658 */
659 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
660 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
661 #endif
662
663 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
664 {
665 U16 ElementFlags; /* 0x00 */
666 U16 VolDevHandle; /* 0x02 */
667 U8 ReasonCode; /* 0x04 */
668 U8 PhysDiskNum; /* 0x05 */
669 U16 PhysDiskDevHandle; /* 0x06 */
670 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
671 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
672
673 /* IR Configuration Change List Event data ElementFlags values */
674 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
675 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
676 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
677 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
678
679 /* IR Configuration Change List Event data ReasonCode values */
680 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
681 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
682 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
683 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
684 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
685 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
686 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
687 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
688 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
689
690 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
691 {
692 U8 NumElements; /* 0x00 */
693 U8 Reserved1; /* 0x01 */
694 U8 Reserved2; /* 0x02 */
695 U8 ConfigNum; /* 0x03 */
696 U32 Flags; /* 0x04 */
697 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
698 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
699 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
700 Mpi2EventDataIrConfigChangeList_t,
701 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
702
703 /* IR Configuration Change List Event data Flags values */
704 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
705
706
707 /* SAS Discovery Event data */
708
709 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
710 {
711 U8 Flags; /* 0x00 */
712 U8 ReasonCode; /* 0x01 */
713 U8 PhysicalPort; /* 0x02 */
714 U8 Reserved1; /* 0x03 */
715 U32 DiscoveryStatus; /* 0x04 */
716 } MPI2_EVENT_DATA_SAS_DISCOVERY,
717 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
718 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
719
720 /* SAS Discovery Event data Flags values */
721 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
722 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
723
724 /* SAS Discovery Event data ReasonCode values */
725 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
726 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
727
728 /* SAS Discovery Event data DiscoveryStatus values */
729 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
730 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
731 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
732 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
733 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
734 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
735 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
736 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
737 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
738 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
739 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
740 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
741 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
742 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
743 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
744 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
745 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
746 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
747 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
748 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
749
750
751 /* SAS Broadcast Primitive Event data */
752
753 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
754 {
755 U8 PhyNum; /* 0x00 */
756 U8 Port; /* 0x01 */
757 U8 PortWidth; /* 0x02 */
758 U8 Primitive; /* 0x03 */
759 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
760 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
761 Mpi2EventDataSasBroadcastPrimitive_t,
762 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
763
764 /* defines for the Primitive field */
765 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
766 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
767 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
768 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
769 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
770 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
771 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
772 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
773
774
775 /* SAS Initiator Device Status Change Event data */
776
777 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
778 {
779 U8 ReasonCode; /* 0x00 */
780 U8 PhysicalPort; /* 0x01 */
781 U16 DevHandle; /* 0x02 */
782 U64 SASAddress; /* 0x04 */
783 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
784 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
785 Mpi2EventDataSasInitDevStatusChange_t,
786 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
787
788 /* SAS Initiator Device Status Change event ReasonCode values */
789 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
790 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
791
792
793 /* SAS Initiator Device Table Overflow Event data */
794
795 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
796 {
797 U16 MaxInit; /* 0x00 */
798 U16 CurrentInit; /* 0x02 */
799 U64 SASAddress; /* 0x04 */
800 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
801 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
802 Mpi2EventDataSasInitTableOverflow_t,
803 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
804
805
806 /* SAS Topology Change List Event data */
807
808 /*
809 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
810 * one and check NumEntries at runtime.
811 */
812 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
813 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
814 #endif
815
816 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
817 {
818 U16 AttachedDevHandle; /* 0x00 */
819 U8 LinkRate; /* 0x02 */
820 U8 PhyStatus; /* 0x03 */
821 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
822 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
823
824 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
825 {
826 U16 EnclosureHandle; /* 0x00 */
827 U16 ExpanderDevHandle; /* 0x02 */
828 U8 NumPhys; /* 0x04 */
829 U8 Reserved1; /* 0x05 */
830 U16 Reserved2; /* 0x06 */
831 U8 NumEntries; /* 0x08 */
832 U8 StartPhyNum; /* 0x09 */
833 U8 ExpStatus; /* 0x0A */
834 U8 PhysicalPort; /* 0x0B */
835 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
836 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
837 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
838 Mpi2EventDataSasTopologyChangeList_t,
839 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
840
841 /* values for the ExpStatus field */
842 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
843 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
844 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
845 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
846
847 /* defines for the LinkRate field */
848 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
849 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
850 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
851 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
852
853 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
854 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
855 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
856 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
857 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
858 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
859 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
860 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
861 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
862
863 /* values for the PhyStatus field */
864 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
865 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
866 /* values for the PhyStatus ReasonCode sub-field */
867 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
868 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
869 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
870 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
871 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
872 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
873
874
875 /* SAS Enclosure Device Status Change Event data */
876
877 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
878 {
879 U16 EnclosureHandle; /* 0x00 */
880 U8 ReasonCode; /* 0x02 */
881 U8 PhysicalPort; /* 0x03 */
882 U64 EnclosureLogicalID; /* 0x04 */
883 U16 NumSlots; /* 0x0C */
884 U16 StartSlot; /* 0x0E */
885 U32 PhyBits; /* 0x10 */
886 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
887 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
888 Mpi2EventDataSasEnclDevStatusChange_t,
889 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
890
891 /* SAS Enclosure Device Status Change event ReasonCode values */
892 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
893 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
894
895
896 /* SAS PHY Counter Event data */
897
898 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
899 {
900 U64 TimeStamp; /* 0x00 */
901 U32 Reserved1; /* 0x08 */
902 U8 PhyEventCode; /* 0x0C */
903 U8 PhyNum; /* 0x0D */
904 U16 Reserved2; /* 0x0E */
905 U32 PhyEventInfo; /* 0x10 */
906 U8 CounterType; /* 0x14 */
907 U8 ThresholdWindow; /* 0x15 */
908 U8 TimeUnits; /* 0x16 */
909 U8 Reserved3; /* 0x17 */
910 U32 EventThreshold; /* 0x18 */
911 U16 ThresholdFlags; /* 0x1C */
912 U16 Reserved4; /* 0x1E */
913 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
914 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
915 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
916
917 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
918
919 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
920
921 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
922
923 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
924
925
926 /****************************************************************************
927 * EventAck message
928 ****************************************************************************/
929
930 /* EventAck Request message */
931 typedef struct _MPI2_EVENT_ACK_REQUEST
932 {
933 U16 Reserved1; /* 0x00 */
934 U8 ChainOffset; /* 0x02 */
935 U8 Function; /* 0x03 */
936 U16 Reserved2; /* 0x04 */
937 U8 Reserved3; /* 0x06 */
938 U8 MsgFlags; /* 0x07 */
939 U8 VP_ID; /* 0x08 */
940 U8 VF_ID; /* 0x09 */
941 U16 Reserved4; /* 0x0A */
942 U16 Event; /* 0x0C */
943 U16 Reserved5; /* 0x0E */
944 U32 EventContext; /* 0x10 */
945 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
946 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
947
948
949 /* EventAck Reply message */
950 typedef struct _MPI2_EVENT_ACK_REPLY
951 {
952 U16 Reserved1; /* 0x00 */
953 U8 MsgLength; /* 0x02 */
954 U8 Function; /* 0x03 */
955 U16 Reserved2; /* 0x04 */
956 U8 Reserved3; /* 0x06 */
957 U8 MsgFlags; /* 0x07 */
958 U8 VP_ID; /* 0x08 */
959 U8 VF_ID; /* 0x09 */
960 U16 Reserved4; /* 0x0A */
961 U16 Reserved5; /* 0x0C */
962 U16 IOCStatus; /* 0x0E */
963 U32 IOCLogInfo; /* 0x10 */
964 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
965 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
966
967
968 /****************************************************************************
969 * FWDownload message
970 ****************************************************************************/
971
972 /* FWDownload Request message */
973 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
974 {
975 U8 ImageType; /* 0x00 */
976 U8 Reserved1; /* 0x01 */
977 U8 ChainOffset; /* 0x02 */
978 U8 Function; /* 0x03 */
979 U16 Reserved2; /* 0x04 */
980 U8 Reserved3; /* 0x06 */
981 U8 MsgFlags; /* 0x07 */
982 U8 VP_ID; /* 0x08 */
983 U8 VF_ID; /* 0x09 */
984 U16 Reserved4; /* 0x0A */
985 U32 TotalImageSize; /* 0x0C */
986 U32 Reserved5; /* 0x10 */
987 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
988 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
989 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
990
991 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
992
993 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
994 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
995 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
996 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
997 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
998 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
999 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1000
1001 /* FWDownload TransactionContext Element */
1002 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1003 {
1004 U8 Reserved1; /* 0x00 */
1005 U8 ContextSize; /* 0x01 */
1006 U8 DetailsLength; /* 0x02 */
1007 U8 Flags; /* 0x03 */
1008 U32 Reserved2; /* 0x04 */
1009 U32 ImageOffset; /* 0x08 */
1010 U32 ImageSize; /* 0x0C */
1011 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1012 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1013
1014 /* FWDownload Reply message */
1015 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1016 {
1017 U8 ImageType; /* 0x00 */
1018 U8 Reserved1; /* 0x01 */
1019 U8 MsgLength; /* 0x02 */
1020 U8 Function; /* 0x03 */
1021 U16 Reserved2; /* 0x04 */
1022 U8 Reserved3; /* 0x06 */
1023 U8 MsgFlags; /* 0x07 */
1024 U8 VP_ID; /* 0x08 */
1025 U8 VF_ID; /* 0x09 */
1026 U16 Reserved4; /* 0x0A */
1027 U16 Reserved5; /* 0x0C */
1028 U16 IOCStatus; /* 0x0E */
1029 U32 IOCLogInfo; /* 0x10 */
1030 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1031 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1032
1033
1034 /****************************************************************************
1035 * FWUpload message
1036 ****************************************************************************/
1037
1038 /* FWUpload Request message */
1039 typedef struct _MPI2_FW_UPLOAD_REQUEST
1040 {
1041 U8 ImageType; /* 0x00 */
1042 U8 Reserved1; /* 0x01 */
1043 U8 ChainOffset; /* 0x02 */
1044 U8 Function; /* 0x03 */
1045 U16 Reserved2; /* 0x04 */
1046 U8 Reserved3; /* 0x06 */
1047 U8 MsgFlags; /* 0x07 */
1048 U8 VP_ID; /* 0x08 */
1049 U8 VF_ID; /* 0x09 */
1050 U16 Reserved4; /* 0x0A */
1051 U32 Reserved5; /* 0x0C */
1052 U32 Reserved6; /* 0x10 */
1053 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1054 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1055 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1056
1057 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1058 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1059 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1060 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1061 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1062 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1063 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1064 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1065 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1066 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1067
1068 typedef struct _MPI2_FW_UPLOAD_TCSGE
1069 {
1070 U8 Reserved1; /* 0x00 */
1071 U8 ContextSize; /* 0x01 */
1072 U8 DetailsLength; /* 0x02 */
1073 U8 Flags; /* 0x03 */
1074 U32 Reserved2; /* 0x04 */
1075 U32 ImageOffset; /* 0x08 */
1076 U32 ImageSize; /* 0x0C */
1077 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1078 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1079
1080 /* FWUpload Reply message */
1081 typedef struct _MPI2_FW_UPLOAD_REPLY
1082 {
1083 U8 ImageType; /* 0x00 */
1084 U8 Reserved1; /* 0x01 */
1085 U8 MsgLength; /* 0x02 */
1086 U8 Function; /* 0x03 */
1087 U16 Reserved2; /* 0x04 */
1088 U8 Reserved3; /* 0x06 */
1089 U8 MsgFlags; /* 0x07 */
1090 U8 VP_ID; /* 0x08 */
1091 U8 VF_ID; /* 0x09 */
1092 U16 Reserved4; /* 0x0A */
1093 U16 Reserved5; /* 0x0C */
1094 U16 IOCStatus; /* 0x0E */
1095 U32 IOCLogInfo; /* 0x10 */
1096 U32 ActualImageSize; /* 0x14 */
1097 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1098 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1099
1100
1101 /* FW Image Header */
1102 typedef struct _MPI2_FW_IMAGE_HEADER
1103 {
1104 U32 Signature; /* 0x00 */
1105 U32 Signature0; /* 0x04 */
1106 U32 Signature1; /* 0x08 */
1107 U32 Signature2; /* 0x0C */
1108 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1109 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1110 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1111 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1112 U16 VendorID; /* 0x20 */
1113 U16 ProductID; /* 0x22 */
1114 U16 ProtocolFlags; /* 0x24 */
1115 U16 Reserved26; /* 0x26 */
1116 U32 IOCCapabilities; /* 0x28 */
1117 U32 ImageSize; /* 0x2C */
1118 U32 NextImageHeaderOffset; /* 0x30 */
1119 U32 Checksum; /* 0x34 */
1120 U32 Reserved38; /* 0x38 */
1121 U32 Reserved3C; /* 0x3C */
1122 U32 Reserved40; /* 0x40 */
1123 U32 Reserved44; /* 0x44 */
1124 U32 Reserved48; /* 0x48 */
1125 U32 Reserved4C; /* 0x4C */
1126 U32 Reserved50; /* 0x50 */
1127 U32 Reserved54; /* 0x54 */
1128 U32 Reserved58; /* 0x58 */
1129 U32 Reserved5C; /* 0x5C */
1130 U32 Reserved60; /* 0x60 */
1131 U32 FirmwareVersionNameWhat; /* 0x64 */
1132 U8 FirmwareVersionName[32]; /* 0x68 */
1133 U32 VendorNameWhat; /* 0x88 */
1134 U8 VendorName[32]; /* 0x8C */
1135 U32 PackageNameWhat; /* 0x88 */
1136 U8 PackageName[32]; /* 0x8C */
1137 U32 ReservedD0; /* 0xD0 */
1138 U32 ReservedD4; /* 0xD4 */
1139 U32 ReservedD8; /* 0xD8 */
1140 U32 ReservedDC; /* 0xDC */
1141 U32 ReservedE0; /* 0xE0 */
1142 U32 ReservedE4; /* 0xE4 */
1143 U32 ReservedE8; /* 0xE8 */
1144 U32 ReservedEC; /* 0xEC */
1145 U32 ReservedF0; /* 0xF0 */
1146 U32 ReservedF4; /* 0xF4 */
1147 U32 ReservedF8; /* 0xF8 */
1148 U32 ReservedFC; /* 0xFC */
1149 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1150 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1151
1152 /* Signature field */
1153 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1154 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1155 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1156
1157 /* Signature0 field */
1158 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1159 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1160
1161 /* Signature1 field */
1162 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1163 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1164
1165 /* Signature2 field */
1166 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1167 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1168
1169
1170 /* defines for using the ProductID field */
1171 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1172 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1173
1174 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1175 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1176
1177 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1178 /* SAS */
1179 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0010)
1180 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0011)
1181
1182 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1183
1184 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1185
1186
1187 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1188 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1189 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1190
1191 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1192
1193 #define MPI2_FW_HEADER_SIZE (0x100)
1194
1195
1196 /* Extended Image Header */
1197 typedef struct _MPI2_EXT_IMAGE_HEADER
1198
1199 {
1200 U8 ImageType; /* 0x00 */
1201 U8 Reserved1; /* 0x01 */
1202 U16 Reserved2; /* 0x02 */
1203 U32 Checksum; /* 0x04 */
1204 U32 ImageSize; /* 0x08 */
1205 U32 NextImageHeaderOffset; /* 0x0C */
1206 U32 PackageVersion; /* 0x10 */
1207 U32 Reserved3; /* 0x14 */
1208 U32 Reserved4; /* 0x18 */
1209 U32 Reserved5; /* 0x1C */
1210 U8 IdentifyString[32]; /* 0x20 */
1211 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1212 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1213
1214 /* useful offsets */
1215 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1216 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1217 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1218
1219 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1220
1221 /* defines for the ImageType field */
1222 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1223 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1224 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1225 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1226 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1227 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1228 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1229 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1230
1231 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID)
1232
1233
1234
1235 /* FLASH Layout Extended Image Data */
1236
1237 /*
1238 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1239 * one and check RegionsPerLayout at runtime.
1240 */
1241 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1242 #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1243 #endif
1244
1245 /*
1246 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1247 * one and check NumberOfLayouts at runtime.
1248 */
1249 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1250 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1251 #endif
1252
1253 typedef struct _MPI2_FLASH_REGION
1254 {
1255 U8 RegionType; /* 0x00 */
1256 U8 Reserved1; /* 0x01 */
1257 U16 Reserved2; /* 0x02 */
1258 U32 RegionOffset; /* 0x04 */
1259 U32 RegionSize; /* 0x08 */
1260 U32 Reserved3; /* 0x0C */
1261 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1262 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1263
1264 typedef struct _MPI2_FLASH_LAYOUT
1265 {
1266 U32 FlashSize; /* 0x00 */
1267 U32 Reserved1; /* 0x04 */
1268 U32 Reserved2; /* 0x08 */
1269 U32 Reserved3; /* 0x0C */
1270 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1271 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1272 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1273
1274 typedef struct _MPI2_FLASH_LAYOUT_DATA
1275 {
1276 U8 ImageRevision; /* 0x00 */
1277 U8 Reserved1; /* 0x01 */
1278 U8 SizeOfRegion; /* 0x02 */
1279 U8 Reserved2; /* 0x03 */
1280 U16 NumberOfLayouts; /* 0x04 */
1281 U16 RegionsPerLayout; /* 0x06 */
1282 U16 MinimumSectorAlignment; /* 0x08 */
1283 U16 Reserved3; /* 0x0A */
1284 U32 Reserved4; /* 0x0C */
1285 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1286 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1287 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1288
1289 /* defines for the RegionType field */
1290 #define MPI2_FLASH_REGION_UNUSED (0x00)
1291 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1292 #define MPI2_FLASH_REGION_BIOS (0x02)
1293 #define MPI2_FLASH_REGION_NVDATA (0x03)
1294 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1295 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1296 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1297 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1298 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1299 #define MPI2_FLASH_REGION_INIT (0x0A)
1300
1301 /* ImageRevision */
1302 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1303
1304
1305
1306 /* Supported Devices Extended Image Data */
1307
1308 /*
1309 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1310 * one and check NumberOfDevices at runtime.
1311 */
1312 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1313 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1314 #endif
1315
1316 typedef struct _MPI2_SUPPORTED_DEVICE
1317 {
1318 U16 DeviceID; /* 0x00 */
1319 U16 VendorID; /* 0x02 */
1320 U16 DeviceIDMask; /* 0x04 */
1321 U16 Reserved1; /* 0x06 */
1322 U8 LowPCIRev; /* 0x08 */
1323 U8 HighPCIRev; /* 0x09 */
1324 U16 Reserved2; /* 0x0A */
1325 U32 Reserved3; /* 0x0C */
1326 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1327 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1328
1329 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1330 {
1331 U8 ImageRevision; /* 0x00 */
1332 U8 Reserved1; /* 0x01 */
1333 U8 NumberOfDevices; /* 0x02 */
1334 U8 Reserved2; /* 0x03 */
1335 U32 Reserved3; /* 0x04 */
1336 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1337 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1338 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1339
1340 /* ImageRevision */
1341 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1342
1343
1344 /* Init Extended Image Data */
1345
1346 typedef struct _MPI2_INIT_IMAGE_FOOTER
1347
1348 {
1349 U32 BootFlags; /* 0x00 */
1350 U32 ImageSize; /* 0x04 */
1351 U32 Signature0; /* 0x08 */
1352 U32 Signature1; /* 0x0C */
1353 U32 Signature2; /* 0x10 */
1354 U32 ResetVector; /* 0x14 */
1355 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1356 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1357
1358 /* defines for the BootFlags field */
1359 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1360
1361 /* defines for the ImageSize field */
1362 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1363
1364 /* defines for the Signature0 field */
1365 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1366 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1367
1368 /* defines for the Signature1 field */
1369 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1370 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1371
1372 /* defines for the Signature2 field */
1373 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1374 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1375
1376 /* Signature fields as individual bytes */
1377 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1378 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1379 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1380 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1381
1382 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1383 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1384 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1385 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1386
1387 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1388 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1389 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1390 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1391
1392 /* defines for the ResetVector field */
1393 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1394
1395
1396 #endif
1397