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Initial modifications using the code changes present between
the LSI source code for FreeBSD drivers. Specifically the changes
between from mpslsi-source-17.00.00.00 -> mpslsi-source-03.00.00.00.
This mainly involves using a different scatter/gather element in
frame setup.
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--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas3/mpi/mpi2_cnfg.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas3/mpi/mpi2_cnfg.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
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13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 - * Copyright (c) 2000 to 2009, LSI Corporation.
24 - * All rights reserved.
23 + * Copyright (c) 2000-2012 LSI Corporation.
25 24 *
26 25 * Redistribution and use in source and binary forms of all code within
27 26 * this file that is exclusively owned by LSI, with or without
28 27 * modification, is permitted provided that, in addition to the CDDL 1.0
29 28 * License requirements, the following conditions are met:
30 29 *
31 30 * Neither the name of the author nor the names of its contributors may be
32 31 * used to endorse or promote products derived from this software without
33 32 * specific prior written permission.
34 33 *
35 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
38 37 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
39 38 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
40 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
41 40 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
42 41 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
43 42 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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44 43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
45 44 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46 45 * DAMAGE.
47 46 */
48 47
49 48 /*
50 49 * Name: mpi2_cnfg.h
51 50 * Title: MPI Configuration messages and pages
52 51 * Creation Date: November 10, 2006
53 52 *
54 - * mpi2_cnfg.h Version: 02.00.12
53 + * mpi2_cnfg.h Version: 02.00.xx
54 + *
55 + * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
56 + * prefix are for use only on MPI v2.5 products, and must not be used
57 + * with MPI v2.0 products. Unless otherwise noted, names beginning with
58 + * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
55 59 *
56 60 * Version History
57 61 * ---------------
58 62 *
59 63 * Date Version Description
60 64 * -------- -------- ------------------------------------------------------
61 65 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
62 66 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
63 67 * Added Manufacturing Page 11.
64 68 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
65 69 * define.
66 70 * 06-26-07 02.00.02 Adding generic structure for product-specific
67 71 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
68 72 * Rework of BIOS Page 2 configuration page.
69 73 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
70 74 * forms.
71 75 * Added configuration pages IOC Page 8 and Driver
72 76 * Persistent Mapping Page 0.
73 77 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
74 78 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
75 79 * RAID Physical Disk Pages 0 and 1, RAID Configuration
76 80 * Page 0).
77 81 * Added new value for AccessStatus field of SAS Device
78 82 * Page 0 (_SATA_NEEDS_INITIALIZATION).
79 83 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
80 84 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
81 85 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
82 86 * NVDATA.
83 87 * Modified IOC Page 7 to use masks and added field for
84 88 * SASBroadcastPrimitiveMasks.
85 89 * Added MPI2_CONFIG_PAGE_BIOS_4.
86 90 * Added MPI2_CONFIG_PAGE_LOG_0.
87 91 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
88 92 * Added SAS Device IDs.
89 93 * Updated Integrated RAID configuration pages including
90 94 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
91 95 * Page 0.
92 96 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
93 97 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
94 98 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
95 99 * Added missing MaxNumRoutedSasAddresses field to
96 100 * MPI2_CONFIG_PAGE_EXPANDER_0.
97 101 * Added SAS Port Page 0.
98 102 * Modified structure layout for
99 103 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
100 104 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
101 105 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
102 106 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
103 107 * to 0x000000FF.
104 108 * Added two new values for the Physical Disk Coercion Size
105 109 * bits in the Flags field of Manufacturing Page 4.
106 110 * Added product-specific Manufacturing pages 16 to 31.
107 111 * Modified Flags bits for controlling write cache on SATA
108 112 * drives in IO Unit Page 1.
109 113 * Added new bit to AdditionalControlFlags of SAS IO Unit
110 114 * Page 1 to control Invalid Topology Correction.
111 115 * Added additional defines for RAID Volume Page 0
112 116 * VolumeStatusFlags field.
113 117 * Modified meaning of RAID Volume Page 0 VolumeSettings
114 118 * define for auto-configure of hot-swap drives.
115 119 * Added SupportedPhysDisks field to RAID Volume Page 1 and
116 120 * added related defines.
117 121 * Added PhysDiskAttributes field (and related defines) to
118 122 * RAID Physical Disk Page 0.
119 123 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
120 124 * Added three new DiscoveryStatus bits for SAS IO Unit
121 125 * Page 0 and SAS Expander Page 0.
122 126 * Removed multiplexing information from SAS IO Unit pages.
123 127 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
124 128 * Removed Zone Address Resolved bit from PhyInfo and from
125 129 * Expander Page 0 Flags field.
126 130 * Added two new AccessStatus values to SAS Device Page 0
127 131 * for indicating routing problems. Added 3 reserved words
128 132 * to this page.
129 133 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
130 134 * Inserted missing reserved field into structure for IOC
131 135 * Page 6.
132 136 * Added more pending task bits to RAID Volume Page 0
133 137 * VolumeStatusFlags defines.
134 138 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
135 139 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
136 140 * and SAS Expander Page 0 to flag a downstream initiator
137 141 * when in simplified routing mode.
138 142 * Removed SATA Init Failure defines for DiscoveryStatus
139 143 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
140 144 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
141 145 * Added PortGroups, DmaGroup, and ControlGroup fields to
142 146 * SAS Device Page 0.
143 147 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
144 148 * Unit Page 6.
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145 149 * Added expander reduced functionality data to SAS
146 150 * Expander Page 0.
147 151 * Added SAS PHY Page 2 and SAS PHY Page 3.
148 152 * 07-30-09 02.00.12 Added IO Unit Page 7.
149 153 * Added new device ids.
150 154 * Added SAS IO Unit Page 5.
151 155 * Added partial and slumber power management capable flags
152 156 * to SAS Device Page 0 Flags field.
153 157 * Added PhyInfo defines for power condition.
154 158 * Added Ethernet configuration pages.
159 + * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
160 + * Added SAS PHY Page 4 structure and defines.
161 + * 02-10-10 02.00.14 Modified the comments for the configuration page
162 + * structures that contain an array of data. The host
163 + * should use the "count" field in the page data (e.g. the
164 + * NumPhys field) to determine the number of valid elements
165 + * in the array.
166 + * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
167 + * Added PowerManagementCapabilities to IO Unit Page 7.
168 + * Added PortWidthModGroup field to
169 + * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
170 + * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
171 + * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
172 + * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
173 + * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
174 + * define.
175 + * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
176 + * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
177 + * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
178 + * defines.
179 + * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
180 + * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
181 + * the Pinout field.
182 + * Added BoardTemperature and BoardTemperatureUnits fields
183 + * to MPI2_CONFIG_PAGE_IO_UNIT_7.
184 + * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
185 + * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
155 186 * --------------------------------------------------------------------------
156 187 */
157 188
158 189 #ifndef MPI2_CNFG_H
159 190 #define MPI2_CNFG_H
160 191
161 192 /*****************************************************************************
162 193 * Configuration Page Header and defines
163 194 *****************************************************************************/
164 195
165 196 /* Config Page Header */
166 197 typedef struct _MPI2_CONFIG_PAGE_HEADER
167 198 {
168 199 U8 PageVersion; /* 0x00 */
169 200 U8 PageLength; /* 0x01 */
170 201 U8 PageNumber; /* 0x02 */
171 202 U8 PageType; /* 0x03 */
172 203 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
173 204 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
174 205
175 206 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
176 207 {
177 208 MPI2_CONFIG_PAGE_HEADER Struct;
178 209 U8 Bytes[4];
179 210 U16 Word16[2];
180 211 U32 Word32;
181 212 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
182 213 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
183 214
184 215 /* Extended Config Page Header */
185 216 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
186 217 {
187 218 U8 PageVersion; /* 0x00 */
188 219 U8 Reserved1; /* 0x01 */
189 220 U8 PageNumber; /* 0x02 */
190 221 U8 PageType; /* 0x03 */
191 222 U16 ExtPageLength; /* 0x04 */
192 223 U8 ExtPageType; /* 0x06 */
193 224 U8 Reserved2; /* 0x07 */
194 225 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
195 226 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
196 227 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
197 228
198 229 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
199 230 {
200 231 MPI2_CONFIG_PAGE_HEADER Struct;
201 232 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
202 233 U8 Bytes[8];
203 234 U16 Word16[4];
204 235 U32 Word32[2];
205 236 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
206 237 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
207 238
208 239
209 240 /* PageType field values */
210 241 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
211 242 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
212 243 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
213 244 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
214 245
215 246 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
216 247 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
217 248 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
218 249 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
219 250 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
220 251 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
221 252 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
222 253 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
223 254
224 255 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
225 256
226 257
227 258 /* ExtPageType field values */
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228 259 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
229 260 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
230 261 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
231 262 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
232 263 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
233 264 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
234 265 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
235 266 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
236 267 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
237 268 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
269 +#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
238 270
239 271
240 272 /*****************************************************************************
241 273 * PageAddress defines
242 274 *****************************************************************************/
243 275
244 276 /* RAID Volume PageAddress format */
245 277 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
246 278 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
247 279 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
248 280
249 281 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
250 282
251 283
252 284 /* RAID Physical Disk PageAddress format */
253 285 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
254 286 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
255 287 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
256 288 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
257 289
258 290 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
259 291 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
260 292
261 293
262 294 /* SAS Expander PageAddress format */
263 295 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
264 296 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
265 297 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
266 298 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
267 299
268 300 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
269 301 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
270 302 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
271 303
272 304
273 305 /* SAS Device PageAddress format */
274 306 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
275 307 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
276 308 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
277 309
278 310 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
279 311
280 312
281 313 /* SAS PHY PageAddress format */
282 314 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
283 315 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
284 316 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
285 317
286 318 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
287 319 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
288 320
289 321
290 322 /* SAS Port PageAddress format */
291 323 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
292 324 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
293 325 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
294 326
295 327 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
296 328
297 329
298 330 /* SAS Enclosure PageAddress format */
299 331 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
300 332 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
301 333 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
302 334
303 335 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
304 336
305 337
306 338 /* RAID Configuration PageAddress format */
307 339 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
308 340 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
309 341 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
310 342 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
311 343
312 344 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
313 345
314 346
315 347 /* Driver Persistent Mapping PageAddress format */
316 348 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
317 349 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
318 350
319 351 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
320 352 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
321 353 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
322 354
323 355
324 356 /* Ethernet PageAddress format */
325 357 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
326 358 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
327 359
328 360 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
329 361
330 362
331 363
332 364 /****************************************************************************
333 365 * Configuration messages
334 366 ****************************************************************************/
335 367
336 368 /* Configuration Request Message */
337 369 typedef struct _MPI2_CONFIG_REQUEST
338 370 {
339 371 U8 Action; /* 0x00 */
340 372 U8 SGLFlags; /* 0x01 */
341 373 U8 ChainOffset; /* 0x02 */
342 374 U8 Function; /* 0x03 */
343 375 U16 ExtPageLength; /* 0x04 */
344 376 U8 ExtPageType; /* 0x06 */
345 377 U8 MsgFlags; /* 0x07 */
346 378 U8 VP_ID; /* 0x08 */
347 379 U8 VF_ID; /* 0x09 */
348 380 U16 Reserved1; /* 0x0A */
349 381 U32 Reserved2; /* 0x0C */
350 382 U32 Reserved3; /* 0x10 */
351 383 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
352 384 U32 PageAddress; /* 0x18 */
353 385 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
354 386 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
355 387 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
356 388
357 389 /* values for the Action field */
358 390 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
359 391 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
360 392 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
361 393 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
362 394 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
363 395 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
364 396 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
365 397 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
366 398
367 399 /* values for SGLFlags field are in the SGL section of mpi2.h */
368 400
369 401
370 402 /* Config Reply Message */
371 403 typedef struct _MPI2_CONFIG_REPLY
372 404 {
373 405 U8 Action; /* 0x00 */
374 406 U8 SGLFlags; /* 0x01 */
375 407 U8 MsgLength; /* 0x02 */
376 408 U8 Function; /* 0x03 */
377 409 U16 ExtPageLength; /* 0x04 */
378 410 U8 ExtPageType; /* 0x06 */
379 411 U8 MsgFlags; /* 0x07 */
380 412 U8 VP_ID; /* 0x08 */
381 413 U8 VF_ID; /* 0x09 */
382 414 U16 Reserved1; /* 0x0A */
383 415 U16 Reserved2; /* 0x0C */
384 416 U16 IOCStatus; /* 0x0E */
385 417 U32 IOCLogInfo; /* 0x10 */
386 418 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
387 419 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
388 420 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
389 421
390 422
391 423
392 424 /*****************************************************************************
393 425 *
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394 426 * C o n f i g u r a t i o n P a g e s
395 427 *
396 428 *****************************************************************************/
397 429
398 430 /****************************************************************************
399 431 * Manufacturing Config pages
400 432 ****************************************************************************/
401 433
402 434 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
403 435
404 -/* SAS */
436 +/* MPI v2.0 SAS products */
405 437 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
406 438 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
407 439 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
408 440 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
409 441 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
410 442 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
411 443 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
412 444
445 +#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
446 +
413 447 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
414 448 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
415 449 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
416 450 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
417 451 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
418 452 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
419 453 #define MPI2_MFGPAGE_DEVID_SAS2208_7 (0x0086)
420 454 #define MPI2_MFGPAGE_DEVID_SAS2208_8 (0x0087)
421 -
455 +#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
456 +#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
457 +#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
458 +
459 +/* MPI v2.5 SAS products */
460 +#define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
461 +#define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
462 +#define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
463 +#define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
464 +#define MPI25_MFGPAGE_DEVID_SAS3108_3 (0x0092)
465 +#define MPI25_MFGPAGE_DEVID_SAS3108_4 (0x0093)
466 +#define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
467 +#define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
422 468
423 469 /* Manufacturing Page 0 */
424 470
425 471 typedef struct _MPI2_CONFIG_PAGE_MAN_0
426 472 {
427 473 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
428 474 U8 ChipName[16]; /* 0x04 */
429 475 U8 ChipRevision[8]; /* 0x14 */
430 476 U8 BoardName[16]; /* 0x1C */
431 477 U8 BoardAssembly[16]; /* 0x2C */
432 478 U8 BoardTracerNumber[16]; /* 0x3C */
433 479 } MPI2_CONFIG_PAGE_MAN_0,
434 480 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
435 481 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
436 482
437 483 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
438 484
439 485
440 486 /* Manufacturing Page 1 */
441 487
442 488 typedef struct _MPI2_CONFIG_PAGE_MAN_1
443 489 {
444 490 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
445 491 U8 VPD[256]; /* 0x04 */
446 492 } MPI2_CONFIG_PAGE_MAN_1,
447 493 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
448 494 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
449 495
450 496 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
451 497
452 498
453 499 typedef struct _MPI2_CHIP_REVISION_ID
454 500 {
455 501 U16 DeviceID; /* 0x00 */
456 502 U8 PCIRevisionID; /* 0x02 */
457 503 U8 Reserved; /* 0x03 */
458 504 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
459 505 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
460 506
461 507
462 508 /* Manufacturing Page 2 */
463 509
464 510 /*
465 511 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
466 512 * one and check Header.PageLength at runtime.
467 513 */
468 514 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
469 515 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
470 516 #endif
471 517
472 518 typedef struct _MPI2_CONFIG_PAGE_MAN_2
473 519 {
474 520 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
475 521 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
476 522 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
477 523 } MPI2_CONFIG_PAGE_MAN_2,
478 524 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
479 525 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
480 526
481 527 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
482 528
483 529
484 530 /* Manufacturing Page 3 */
485 531
486 532 /*
487 533 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
488 534 * one and check Header.PageLength at runtime.
489 535 */
490 536 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
491 537 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
492 538 #endif
493 539
494 540 typedef struct _MPI2_CONFIG_PAGE_MAN_3
495 541 {
496 542 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
497 543 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
498 544 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
499 545 } MPI2_CONFIG_PAGE_MAN_3,
500 546 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
501 547 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
502 548
503 549 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
504 550
505 551
506 552 /* Manufacturing Page 4 */
507 553
508 554 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
509 555 {
510 556 U8 PowerSaveFlags; /* 0x00 */
511 557 U8 InternalOperationsSleepTime; /* 0x01 */
512 558 U8 InternalOperationsRunTime; /* 0x02 */
513 559 U8 HostIdleTime; /* 0x03 */
514 560 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
515 561 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
516 562 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
517 563
518 564 /* defines for the PowerSaveFlags field */
519 565 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
520 566 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
521 567 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
522 568 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
523 569
524 570 typedef struct _MPI2_CONFIG_PAGE_MAN_4
525 571 {
526 572 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
527 573 U32 Reserved1; /* 0x04 */
528 574 U32 Flags; /* 0x08 */
529 575 U8 InquirySize; /* 0x0C */
530 576 U8 Reserved2; /* 0x0D */
531 577 U16 Reserved3; /* 0x0E */
532 578 U8 InquiryData[56]; /* 0x10 */
533 579 U32 RAID0VolumeSettings; /* 0x48 */
534 580 U32 RAID1EVolumeSettings; /* 0x4C */
535 581 U32 RAID1VolumeSettings; /* 0x50 */
536 582 U32 RAID10VolumeSettings; /* 0x54 */
537 583 U32 Reserved4; /* 0x58 */
538 584 U32 Reserved5; /* 0x5C */
539 585 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
540 586 U8 MaxOCEDisks; /* 0x64 */
541 587 U8 ResyncRate; /* 0x65 */
542 588 U16 DataScrubDuration; /* 0x66 */
543 589 U8 MaxHotSpares; /* 0x68 */
544 590 U8 MaxPhysDisksPerVol; /* 0x69 */
545 591 U8 MaxPhysDisks; /* 0x6A */
546 592 U8 MaxVolumes; /* 0x6B */
547 593 } MPI2_CONFIG_PAGE_MAN_4,
548 594 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
549 595 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
550 596
551 597 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
552 598
553 599 /* Manufacturing Page 4 Flags field */
554 600 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
555 601 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
556 602
557 603 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
558 604 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
559 605 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
560 606
561 607 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
562 608 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
563 609 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
564 610 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
565 611 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
566 612
567 613 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
568 614 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
569 615 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
570 616 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
571 617
572 618 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
573 619 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
574 620 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
575 621 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
576 622 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
577 623 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
578 624 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
579 625 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
580 626
581 627
582 628 /* Manufacturing Page 5 */
583 629
584 630 /*
585 631 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
586 632 * one and check Header.PageLength or NumPhys at runtime.
587 633 */
588 634 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
589 635 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
590 636 #endif
591 637
592 638 typedef struct _MPI2_MANUFACTURING5_ENTRY
593 639 {
594 640 U64 WWID; /* 0x00 */
595 641 U64 DeviceName; /* 0x08 */
596 642 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
597 643 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
598 644
599 645 typedef struct _MPI2_CONFIG_PAGE_MAN_5
600 646 {
601 647 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
602 648 U8 NumPhys; /* 0x04 */
603 649 U8 Reserved1; /* 0x05 */
604 650 U16 Reserved2; /* 0x06 */
605 651 U32 Reserved3; /* 0x08 */
606 652 U32 Reserved4; /* 0x0C */
607 653 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
608 654 } MPI2_CONFIG_PAGE_MAN_5,
609 655 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
610 656 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
611 657
612 658 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
613 659
614 660
615 661 /* Manufacturing Page 6 */
616 662
617 663 typedef struct _MPI2_CONFIG_PAGE_MAN_6
618 664 {
619 665 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
620 666 U32 ProductSpecificInfo;/* 0x04 */
621 667 } MPI2_CONFIG_PAGE_MAN_6,
622 668 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
623 669 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
624 670
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625 671 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
626 672
627 673
628 674 /* Manufacturing Page 7 */
629 675
630 676 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
631 677 {
632 678 U32 Pinout; /* 0x00 */
633 679 U8 Connector[16]; /* 0x04 */
634 680 U8 Location; /* 0x14 */
635 - U8 Reserved1; /* 0x15 */
681 + U8 ReceptacleID; /* 0x15 */
636 682 U16 Slot; /* 0x16 */
637 683 U32 Reserved2; /* 0x18 */
638 684 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
639 685 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
640 686
641 687 /* defines for the Pinout field */
642 688 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
643 689 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
644 690 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
645 691 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
646 692 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
647 693 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
648 694 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
649 695 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
650 696 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
651 697 #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
652 698
653 699 /* defines for the Location field */
654 700 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
655 701 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
656 702 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
657 703 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
658 704 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
659 705 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
660 706 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
661 707
662 708 /*
663 709 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
664 710 * one and check NumPhys at runtime.
665 711 */
666 712 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
667 713 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
668 714 #endif
669 715
670 716 typedef struct _MPI2_CONFIG_PAGE_MAN_7
671 717 {
672 718 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
673 719 U32 Reserved1; /* 0x04 */
674 720 U32 Reserved2; /* 0x08 */
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675 721 U32 Flags; /* 0x0C */
676 722 U8 EnclosureName[16]; /* 0x10 */
677 723 U8 NumPhys; /* 0x20 */
678 724 U8 Reserved3; /* 0x21 */
679 725 U16 Reserved4; /* 0x22 */
680 726 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
681 727 } MPI2_CONFIG_PAGE_MAN_7,
682 728 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
683 729 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
684 730
685 -#define MPI2_MANUFACTURING7_PAGEVERSION (0x00)
731 +#define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
686 732
687 733 /* defines for the Flags field */
688 734 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
689 735
690 736
691 737 /*
692 738 * Generic structure to use for product-specific manufacturing pages
693 739 * (currently Manufacturing Page 8 through Manufacturing Page 31).
694 740 */
695 741
696 742 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
697 743 {
698 744 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
699 745 U32 ProductSpecificInfo;/* 0x04 */
700 746 } MPI2_CONFIG_PAGE_MAN_PS,
701 747 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
702 748 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
703 749
704 750 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
705 751 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
706 752 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
707 753 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
708 754 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
709 755 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
710 756 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
711 757 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
712 758 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
713 759 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
714 760 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
715 761 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
716 762 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
717 763 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
718 764 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
719 765 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
720 766 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
721 767 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
722 768 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
723 769 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
724 770 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
725 771 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
726 772 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
727 773 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
728 774
729 775
730 776 /****************************************************************************
731 777 * IO Unit Config Pages
732 778 ****************************************************************************/
733 779
734 780 /* IO Unit Page 0 */
735 781
736 782 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
737 783 {
738 784 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
739 785 U64 UniqueValue; /* 0x04 */
740 786 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
741 787 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
742 788 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
743 789 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
744 790
745 791 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
746 792
747 793
748 794 /* IO Unit Page 1 */
749 795
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750 796 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
751 797 {
752 798 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
753 799 U32 Flags; /* 0x04 */
754 800 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
755 801 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
756 802
757 803 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
758 804
759 805 /* IO Unit Page 1 Flags defines */
806 +#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
807 +#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
808 +#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
760 809 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
810 +#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
761 811 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
762 812 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
763 813 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
764 814 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
765 815 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
766 816 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
767 817 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
768 818 #define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
769 819 #define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
770 820
771 821
772 822 /* IO Unit Page 3 */
773 823
774 824 /*
775 825 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
776 826 * one and check Header.PageLength at runtime.
777 827 */
778 828 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
779 829 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
780 830 #endif
781 831
782 832 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
783 833 {
784 834 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
785 835 U8 GPIOCount; /* 0x04 */
786 836 U8 Reserved1; /* 0x05 */
787 837 U16 Reserved2; /* 0x06 */
788 838 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
789 839 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
790 840 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
791 841
792 842 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
793 843
794 844 /* defines for IO Unit Page 3 GPIOVal field */
795 845 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
796 846 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
797 847 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
798 848 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
799 849
800 850
801 851 /* IO Unit Page 5 */
802 852
803 853 /*
804 854 * Upper layer code (drivers, utilities, etc.) should leave this define set to
805 855 * one and check Header.PageLength or NumDmaEngines at runtime.
806 856 */
807 857 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
808 858 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
809 859 #endif
810 860
811 861 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5
812 862 {
813 863 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
814 864 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
815 865 U64 RaidAcceleratorBufferSize; /* 0x0C */
816 866 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
817 867 U8 RAControlSize; /* 0x1C */
818 868 U8 NumDmaEngines; /* 0x1D */
819 869 U8 RAMinControlSize; /* 0x1E */
820 870 U8 RAMaxControlSize; /* 0x1F */
821 871 U32 Reserved1; /* 0x20 */
822 872 U32 Reserved2; /* 0x24 */
823 873 U32 Reserved3; /* 0x28 */
824 874 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
825 875 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
826 876 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
827 877
828 878 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
829 879
830 880 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
831 881 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
832 882 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
833 883
834 884 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
835 885 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
836 886 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
837 887 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
838 888
839 889
840 890 /* IO Unit Page 6 */
841 891
842 892 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6
843 893 {
844 894 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
845 895 U16 Flags; /* 0x04 */
846 896 U8 RAHostControlSize; /* 0x06 */
847 897 U8 Reserved0; /* 0x07 */
848 898 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
849 899 U32 Reserved1; /* 0x10 */
850 900 U32 Reserved2; /* 0x14 */
851 901 U32 Reserved3; /* 0x18 */
852 902 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
853 903 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
854 904
855 905 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
856 906
857 907 /* defines for IO Unit Page 6 Flags field */
858 908 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
859 909
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860 910
861 911 /* IO Unit Page 7 */
862 912
863 913 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
864 914 {
865 915 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
866 916 U16 Reserved1; /* 0x04 */
867 917 U8 PCIeWidth; /* 0x06 */
868 918 U8 PCIeSpeed; /* 0x07 */
869 919 U32 ProcessorState; /* 0x08 */
870 - U32 Reserved2; /* 0x0C */
920 + U32 PowerManagementCapabilities; /* 0x0C */
871 921 U16 IOCTemperature; /* 0x10 */
872 922 U8 IOCTemperatureUnits; /* 0x12 */
873 923 U8 IOCSpeed; /* 0x13 */
874 - U32 Reserved3; /* 0x14 */
924 + U16 BoardTemperature; /* 0x14 */
925 + U8 BoardTemperatureUnits; /* 0x16 */
926 + U8 Reserved3; /* 0x17 */
875 927 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
876 928 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
877 929
878 -#define MPI2_IOUNITPAGE7_PAGEVERSION (0x00)
930 +#define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
879 931
880 932 /* defines for IO Unit Page 7 PCIeWidth field */
881 933 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
882 934 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
883 935 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
884 936 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
885 937
886 938 /* defines for IO Unit Page 7 PCIeSpeed field */
887 939 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
888 940 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
889 941 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
890 942
891 943 /* defines for IO Unit Page 7 ProcessorState field */
892 944 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
893 945 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
894 946
895 947 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
896 948 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
897 949 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
898 950
951 +/* defines for IO Unit Page 7 PowerManagementCapabilities field */
952 +#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
953 +#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
954 +#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
955 +#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008)
956 +#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004)
957 +
899 958 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
900 959 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
901 960 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
902 961 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
903 962
904 963 /* defines for IO Unit Page 7 IOCSpeed field */
905 964 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
906 965 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
907 966 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
908 967 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
909 968
969 +/* defines for IO Unit Page 7 BoardTemperatureUnits field */
970 +#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
971 +#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
972 +#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
910 973
911 974
912 975 /****************************************************************************
913 976 * IOC Config Pages
914 977 ****************************************************************************/
915 978
916 979 /* IOC Page 0 */
917 980
918 981 typedef struct _MPI2_CONFIG_PAGE_IOC_0
919 982 {
920 983 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
921 984 U32 Reserved1; /* 0x04 */
922 985 U32 Reserved2; /* 0x08 */
923 986 U16 VendorID; /* 0x0C */
924 987 U16 DeviceID; /* 0x0E */
925 988 U8 RevisionID; /* 0x10 */
926 989 U8 Reserved3; /* 0x11 */
927 990 U16 Reserved4; /* 0x12 */
928 991 U32 ClassCode; /* 0x14 */
929 992 U16 SubsystemVendorID; /* 0x18 */
930 993 U16 SubsystemID; /* 0x1A */
931 994 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
932 995 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
933 996
934 997 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
935 998
936 999
937 1000 /* IOC Page 1 */
938 1001
939 1002 typedef struct _MPI2_CONFIG_PAGE_IOC_1
940 1003 {
941 1004 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
942 1005 U32 Flags; /* 0x04 */
943 1006 U32 CoalescingTimeout; /* 0x08 */
944 1007 U8 CoalescingDepth; /* 0x0C */
945 1008 U8 PCISlotNum; /* 0x0D */
946 1009 U8 PCIBusNum; /* 0x0E */
947 1010 U8 PCIDomainSegment; /* 0x0F */
948 1011 U32 Reserved1; /* 0x10 */
949 1012 U32 Reserved2; /* 0x14 */
950 1013 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
951 1014 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
952 1015
953 1016 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
954 1017
955 1018 /* defines for IOC Page 1 Flags field */
956 1019 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
957 1020
958 1021 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
959 1022 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
960 1023 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
961 1024
962 1025 /* IOC Page 6 */
963 1026
964 1027 typedef struct _MPI2_CONFIG_PAGE_IOC_6
965 1028 {
966 1029 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
967 1030 U32 CapabilitiesFlags; /* 0x04 */
968 1031 U8 MaxDrivesRAID0; /* 0x08 */
969 1032 U8 MaxDrivesRAID1; /* 0x09 */
970 1033 U8 MaxDrivesRAID1E; /* 0x0A */
971 1034 U8 MaxDrivesRAID10; /* 0x0B */
972 1035 U8 MinDrivesRAID0; /* 0x0C */
973 1036 U8 MinDrivesRAID1; /* 0x0D */
974 1037 U8 MinDrivesRAID1E; /* 0x0E */
975 1038 U8 MinDrivesRAID10; /* 0x0F */
976 1039 U32 Reserved1; /* 0x10 */
977 1040 U8 MaxGlobalHotSpares; /* 0x14 */
978 1041 U8 MaxPhysDisks; /* 0x15 */
979 1042 U8 MaxVolumes; /* 0x16 */
980 1043 U8 MaxConfigs; /* 0x17 */
981 1044 U8 MaxOCEDisks; /* 0x18 */
982 1045 U8 Reserved2; /* 0x19 */
983 1046 U16 Reserved3; /* 0x1A */
984 1047 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
985 1048 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
986 1049 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
987 1050 U32 Reserved4; /* 0x28 */
988 1051 U32 Reserved5; /* 0x2C */
989 1052 U16 DefaultMetadataSize; /* 0x30 */
990 1053 U16 Reserved6; /* 0x32 */
991 1054 U16 MaxBadBlockTableEntries; /* 0x34 */
992 1055 U16 Reserved7; /* 0x36 */
993 1056 U32 IRNvsramVersion; /* 0x38 */
994 1057 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
995 1058 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
996 1059
997 1060 #define MPI2_IOCPAGE6_PAGEVERSION (0x04)
998 1061
999 1062 /* defines for IOC Page 6 CapabilitiesFlags */
1000 1063 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1001 1064 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1002 1065 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1003 1066 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1004 1067 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1005 1068
1006 1069
1007 1070 /* IOC Page 7 */
1008 1071
1009 1072 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1010 1073
1011 1074 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1012 1075 {
1013 1076 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1014 1077 U32 Reserved1; /* 0x04 */
1015 1078 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1016 1079 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1017 1080 U16 Reserved2; /* 0x1A */
1018 1081 U32 Reserved3; /* 0x1C */
1019 1082 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1020 1083 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1021 1084
1022 1085 #define MPI2_IOCPAGE7_PAGEVERSION (0x01)
1023 1086
1024 1087
1025 1088 /* IOC Page 8 */
1026 1089
1027 1090 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1028 1091 {
1029 1092 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1030 1093 U8 NumDevsPerEnclosure; /* 0x04 */
1031 1094 U8 Reserved1; /* 0x05 */
1032 1095 U16 Reserved2; /* 0x06 */
1033 1096 U16 MaxPersistentEntries; /* 0x08 */
1034 1097 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1035 1098 U16 Flags; /* 0x0C */
1036 1099 U16 Reserved3; /* 0x0E */
1037 1100 U16 IRVolumeMappingFlags; /* 0x10 */
1038 1101 U16 Reserved4; /* 0x12 */
1039 1102 U32 Reserved5; /* 0x14 */
1040 1103 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1041 1104 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1042 1105
1043 1106 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1044 1107
1045 1108 /* defines for IOC Page 8 Flags field */
1046 1109 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1047 1110 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1048 1111
1049 1112 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1050 1113 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1051 1114 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1052 1115
1053 1116 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1054 1117 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1055 1118
1056 1119 /* defines for IOC Page 8 IRVolumeMappingFlags */
1057 1120 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1058 1121 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1059 1122 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1060 1123
1061 1124
1062 1125 /****************************************************************************
1063 1126 * BIOS Config Pages
1064 1127 ****************************************************************************/
1065 1128
1066 1129 /* BIOS Page 1 */
1067 1130
1068 1131 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1069 1132 {
1070 1133 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1071 1134 U32 BiosOptions; /* 0x04 */
1072 1135 U32 IOCSettings; /* 0x08 */
1073 1136 U32 Reserved1; /* 0x0C */
1074 1137 U32 DeviceSettings; /* 0x10 */
1075 1138 U16 NumberOfDevices; /* 0x14 */
1076 1139 U16 Reserved2; /* 0x16 */
1077 1140 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1078 1141 U16 IOTimeoutSequential; /* 0x1A */
1079 1142 U16 IOTimeoutOther; /* 0x1C */
1080 1143 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1081 1144 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1082 1145 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1083 1146
1084 1147 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
1085 1148
1086 1149 /* values for BIOS Page 1 BiosOptions field */
1087 1150 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1088 1151
1089 1152 /* values for BIOS Page 1 IOCSettings field */
1090 1153 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1091 1154 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1092 1155 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1093 1156
1094 1157 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1095 1158 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1096 1159 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1097 1160 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1098 1161
1099 1162 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1100 1163 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1101 1164 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1102 1165 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1103 1166 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1104 1167
1105 1168 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1106 1169
1107 1170 /* values for BIOS Page 1 DeviceSettings field */
1108 1171 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1109 1172 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1110 1173 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1111 1174 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1112 1175 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1113 1176
1114 1177
1115 1178 /* BIOS Page 2 */
1116 1179
1117 1180 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1118 1181 {
1119 1182 U32 Reserved1; /* 0x00 */
1120 1183 U32 Reserved2; /* 0x04 */
1121 1184 U32 Reserved3; /* 0x08 */
1122 1185 U32 Reserved4; /* 0x0C */
1123 1186 U32 Reserved5; /* 0x10 */
1124 1187 U32 Reserved6; /* 0x14 */
1125 1188 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1126 1189 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1127 1190 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1128 1191
1129 1192 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1130 1193 {
1131 1194 U64 SASAddress; /* 0x00 */
1132 1195 U8 LUN[8]; /* 0x08 */
1133 1196 U32 Reserved1; /* 0x10 */
1134 1197 U32 Reserved2; /* 0x14 */
1135 1198 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1136 1199 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1137 1200
1138 1201 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1139 1202 {
1140 1203 U64 EnclosureLogicalID; /* 0x00 */
1141 1204 U32 Reserved1; /* 0x08 */
1142 1205 U32 Reserved2; /* 0x0C */
1143 1206 U16 SlotNumber; /* 0x10 */
1144 1207 U16 Reserved3; /* 0x12 */
1145 1208 U32 Reserved4; /* 0x14 */
1146 1209 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1147 1210 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1148 1211 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1149 1212
1150 1213 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1151 1214 {
1152 1215 U64 DeviceName; /* 0x00 */
1153 1216 U8 LUN[8]; /* 0x08 */
1154 1217 U32 Reserved1; /* 0x10 */
1155 1218 U32 Reserved2; /* 0x14 */
1156 1219 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1157 1220 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1158 1221
1159 1222 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1160 1223 {
1161 1224 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1162 1225 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1163 1226 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1164 1227 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1165 1228 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1166 1229 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1167 1230
1168 1231 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1169 1232 {
1170 1233 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1171 1234 U32 Reserved1; /* 0x04 */
1172 1235 U32 Reserved2; /* 0x08 */
1173 1236 U32 Reserved3; /* 0x0C */
1174 1237 U32 Reserved4; /* 0x10 */
1175 1238 U32 Reserved5; /* 0x14 */
1176 1239 U32 Reserved6; /* 0x18 */
1177 1240 U8 ReqBootDeviceForm; /* 0x1C */
1178 1241 U8 Reserved7; /* 0x1D */
1179 1242 U16 Reserved8; /* 0x1E */
1180 1243 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1181 1244 U8 ReqAltBootDeviceForm; /* 0x38 */
1182 1245 U8 Reserved9; /* 0x39 */
1183 1246 U16 Reserved10; /* 0x3A */
1184 1247 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1185 1248 U8 CurrentBootDeviceForm; /* 0x58 */
1186 1249 U8 Reserved11; /* 0x59 */
1187 1250 U16 Reserved12; /* 0x5A */
1188 1251 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1189 1252 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1190 1253 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1191 1254
1192 1255 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1193 1256
1194 1257 /* values for BIOS Page 2 BootDeviceForm fields */
1195 1258 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1196 1259 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1197 1260 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1198 1261 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1199 1262 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1200 1263
1201 1264
1202 1265 /* BIOS Page 3 */
1203 1266
1204 1267 typedef struct _MPI2_ADAPTER_INFO
1205 1268 {
1206 1269 U8 PciBusNumber; /* 0x00 */
1207 1270 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1208 1271 U16 AdapterFlags; /* 0x02 */
1209 1272 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1210 1273 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1211 1274
1212 1275 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1213 1276 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1214 1277
1215 1278 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1216 1279 {
1217 1280 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1218 1281 U32 GlobalFlags; /* 0x04 */
1219 1282 U32 BiosVersion; /* 0x08 */
1220 1283 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1221 1284 U32 Reserved1; /* 0x1C */
1222 1285 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1223 1286 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1224 1287
1225 1288 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1226 1289
1227 1290 /* values for BIOS Page 3 GlobalFlags */
1228 1291 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1229 1292 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1230 1293 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1231 1294
1232 1295 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1233 1296 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1234 1297 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1235 1298 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1236 1299
1237 1300
1238 1301 /* BIOS Page 4 */
1239 1302
1240 1303 /*
1241 1304 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1242 1305 * one and check Header.PageLength or NumPhys at runtime.
1243 1306 */
1244 1307 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1245 1308 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1246 1309 #endif
1247 1310
1248 1311 typedef struct _MPI2_BIOS4_ENTRY
1249 1312 {
1250 1313 U64 ReassignmentWWID; /* 0x00 */
1251 1314 U64 ReassignmentDeviceName; /* 0x08 */
1252 1315 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1253 1316 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1254 1317
1255 1318 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1256 1319 {
1257 1320 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1258 1321 U8 NumPhys; /* 0x04 */
1259 1322 U8 Reserved1; /* 0x05 */
1260 1323 U16 Reserved2; /* 0x06 */
1261 1324 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1262 1325 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1263 1326 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1264 1327
1265 1328 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1266 1329
1267 1330
1268 1331 /****************************************************************************
1269 1332 * RAID Volume Config Pages
1270 1333 ****************************************************************************/
1271 1334
1272 1335 /* RAID Volume Page 0 */
1273 1336
1274 1337 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1275 1338 {
1276 1339 U8 RAIDSetNum; /* 0x00 */
1277 1340 U8 PhysDiskMap; /* 0x01 */
1278 1341 U8 PhysDiskNum; /* 0x02 */
1279 1342 U8 Reserved; /* 0x03 */
1280 1343 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1281 1344 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1282 1345
1283 1346 /* defines for the PhysDiskMap field */
1284 1347 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1285 1348 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1286 1349
1287 1350 typedef struct _MPI2_RAIDVOL0_SETTINGS
1288 1351 {
1289 1352 U16 Settings; /* 0x00 */
1290 1353 U8 HotSparePool; /* 0x01 */
1291 1354 U8 Reserved; /* 0x02 */
1292 1355 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1293 1356 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1294 1357
1295 1358 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1296 1359 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1297 1360 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1298 1361 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1299 1362 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1300 1363 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1301 1364 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1302 1365 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1303 1366 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1304 1367
1305 1368 /* RAID Volume Page 0 VolumeSettings defines */
1306 1369 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1307 1370 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1308 1371
1309 1372 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1310 1373 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1311 1374 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1312 1375 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1313 1376
1314 1377 /*
1315 1378 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1316 1379 * one and check Header.PageLength at runtime.
1317 1380 */
1318 1381 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1319 1382 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1320 1383 #endif
1321 1384
1322 1385 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1323 1386 {
1324 1387 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1325 1388 U16 DevHandle; /* 0x04 */
1326 1389 U8 VolumeState; /* 0x06 */
1327 1390 U8 VolumeType; /* 0x07 */
1328 1391 U32 VolumeStatusFlags; /* 0x08 */
1329 1392 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1330 1393 U64 MaxLBA; /* 0x10 */
1331 1394 U32 StripeSize; /* 0x18 */
1332 1395 U16 BlockSize; /* 0x1C */
1333 1396 U16 Reserved1; /* 0x1E */
1334 1397 U8 SupportedPhysDisks; /* 0x20 */
1335 1398 U8 ResyncRate; /* 0x21 */
1336 1399 U16 DataScrubDuration; /* 0x22 */
1337 1400 U8 NumPhysDisks; /* 0x24 */
1338 1401 U8 Reserved2; /* 0x25 */
1339 1402 U8 Reserved3; /* 0x26 */
1340 1403 U8 InactiveStatus; /* 0x27 */
1341 1404 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1342 1405 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1343 1406 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1344 1407
1345 1408 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1346 1409
1347 1410 /* values for RAID VolumeState */
1348 1411 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1349 1412 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1350 1413 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1351 1414 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1352 1415 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1353 1416 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1354 1417
1355 1418 /* values for RAID VolumeType */
1356 1419 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1357 1420 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1358 1421 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1359 1422 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1360 1423 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1361 1424
1362 1425 /* values for RAID Volume Page 0 VolumeStatusFlags field */
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1363 1426 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1364 1427 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1365 1428 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1366 1429 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1367 1430 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1368 1431 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1369 1432 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1370 1433 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1371 1434 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1372 1435 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1436 +#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1373 1437 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1374 1438 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1375 1439 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1376 1440 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1377 1441 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1378 1442 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1379 1443 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1380 1444 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1381 1445
1382 1446 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1383 1447 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1384 1448 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1385 1449 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1386 1450 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1387 1451
1388 1452 /* values for RAID Volume Page 0 InactiveStatus field */
1389 1453 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1390 1454 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1391 1455 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1392 1456 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1393 1457 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1394 1458 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1395 1459 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1396 1460
1397 1461
1398 1462 /* RAID Volume Page 1 */
1399 1463
1400 1464 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1401 1465 {
1402 1466 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1403 1467 U16 DevHandle; /* 0x04 */
1404 1468 U16 Reserved0; /* 0x06 */
1405 1469 U8 GUID[24]; /* 0x08 */
1406 1470 U8 Name[16]; /* 0x20 */
1407 1471 U64 WWID; /* 0x30 */
1408 1472 U32 Reserved1; /* 0x38 */
1409 1473 U32 Reserved2; /* 0x3C */
1410 1474 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1411 1475 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1412 1476
1413 1477 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1414 1478
1415 1479
1416 1480 /****************************************************************************
1417 1481 * RAID Physical Disk Config Pages
1418 1482 ****************************************************************************/
1419 1483
1420 1484 /* RAID Physical Disk Page 0 */
1421 1485
1422 1486 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1423 1487 {
1424 1488 U16 Reserved1; /* 0x00 */
1425 1489 U8 HotSparePool; /* 0x02 */
1426 1490 U8 Reserved2; /* 0x03 */
1427 1491 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1428 1492 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1429 1493
1430 1494 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1431 1495
1432 1496 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1433 1497 {
1434 1498 U8 VendorID[8]; /* 0x00 */
1435 1499 U8 ProductID[16]; /* 0x08 */
1436 1500 U8 ProductRevLevel[4]; /* 0x18 */
1437 1501 U8 SerialNum[32]; /* 0x1C */
1438 1502 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1439 1503 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1440 1504 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1441 1505
1442 1506 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1443 1507 {
1444 1508 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1445 1509 U16 DevHandle; /* 0x04 */
1446 1510 U8 Reserved1; /* 0x06 */
1447 1511 U8 PhysDiskNum; /* 0x07 */
1448 1512 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1449 1513 U32 Reserved2; /* 0x0C */
1450 1514 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1451 1515 U32 Reserved3; /* 0x4C */
1452 1516 U8 PhysDiskState; /* 0x50 */
1453 1517 U8 OfflineReason; /* 0x51 */
1454 1518 U8 IncompatibleReason; /* 0x52 */
1455 1519 U8 PhysDiskAttributes; /* 0x53 */
1456 1520 U32 PhysDiskStatusFlags; /* 0x54 */
1457 1521 U64 DeviceMaxLBA; /* 0x58 */
1458 1522 U64 HostMaxLBA; /* 0x60 */
1459 1523 U64 CoercedMaxLBA; /* 0x68 */
1460 1524 U16 BlockSize; /* 0x70 */
1461 1525 U16 Reserved5; /* 0x72 */
1462 1526 U32 Reserved6; /* 0x74 */
1463 1527 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1464 1528 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1465 1529 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1466 1530
1467 1531 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1468 1532
1469 1533 /* PhysDiskState defines */
1470 1534 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1471 1535 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1472 1536 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1473 1537 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1474 1538 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1475 1539 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1476 1540 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1477 1541 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1478 1542
1479 1543 /* OfflineReason defines */
1480 1544 #define MPI2_PHYSDISK0_ONLINE (0x00)
1481 1545 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1482 1546 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1483 1547 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1484 1548 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
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1485 1549 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1486 1550 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1487 1551
1488 1552 /* IncompatibleReason defines */
1489 1553 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1490 1554 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1491 1555 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1492 1556 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1493 1557 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1494 1558 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1559 +#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1495 1560 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1496 1561
1497 1562 /* PhysDiskAttributes defines */
1498 1563 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1499 1564 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1565 +
1566 +#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1500 1567 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1501 1568 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1502 1569
1503 1570 /* PhysDiskStatusFlags defines */
1504 1571 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1505 1572 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1506 1573 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1507 1574 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1508 1575 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1509 1576 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1510 1577 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1511 1578 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1512 1579
1513 1580
1514 1581 /* RAID Physical Disk Page 1 */
1515 1582
1516 1583 /*
1517 1584 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1518 1585 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1519 1586 */
1520 1587 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1521 1588 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1522 1589 #endif
1523 1590
1524 1591 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1525 1592 {
1526 1593 U16 DevHandle; /* 0x00 */
1527 1594 U16 Reserved1; /* 0x02 */
1528 1595 U64 WWID; /* 0x04 */
1529 1596 U64 OwnerWWID; /* 0x0C */
1530 1597 U8 OwnerIdentifier; /* 0x14 */
1531 1598 U8 Reserved2; /* 0x15 */
1532 1599 U16 Flags; /* 0x16 */
1533 1600 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1534 1601 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1535 1602
1536 1603 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1537 1604 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1538 1605 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1539 1606 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1540 1607
1541 1608 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1542 1609 {
1543 1610 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1544 1611 U8 NumPhysDiskPaths; /* 0x04 */
1545 1612 U8 PhysDiskNum; /* 0x05 */
1546 1613 U16 Reserved1; /* 0x06 */
1547 1614 U32 Reserved2; /* 0x08 */
1548 1615 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1549 1616 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1550 1617 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1551 1618 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1552 1619
1553 1620 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1554 1621
1555 1622
1556 1623 /****************************************************************************
1557 1624 * values for fields used by several types of SAS Config Pages
1558 1625 ****************************************************************************/
1559 1626
1560 1627 /* values for NegotiatedLinkRates fields */
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1561 1628 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1562 1629 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1563 1630 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1564 1631 /* link rates used for Negotiated Physical and Logical Link Rate */
1565 1632 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1566 1633 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1567 1634 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1568 1635 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1569 1636 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1570 1637 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1638 +#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1571 1639 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1572 1640 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1573 1641 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1642 +#define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
1574 1643
1575 1644
1576 1645 /* values for AttachedPhyInfo fields */
1577 1646 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1578 1647 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1579 1648 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1580 1649
1581 1650 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1582 1651 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1583 1652 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1584 1653 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1585 1654 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1586 1655 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
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1587 1656 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1588 1657 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1589 1658 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1590 1659 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1591 1660
1592 1661
1593 1662 /* values for PhyInfo fields */
1594 1663 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1595 1664
1596 1665 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1666 +#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1597 1667 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1598 1668 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1599 1669 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1600 1670
1601 1671 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1602 1672 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1603 1673 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1604 1674 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1605 1675 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1606 1676 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1607 1677
1608 1678 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1609 1679 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1610 1680 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1611 1681 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1612 1682 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1613 1683 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1614 1684 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1615 1685 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1616 1686 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1617 1687 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1618 1688
1619 1689 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1620 1690 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1621 1691 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1622 1692 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1623 1693
1624 1694 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1625 1695 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1626 1696
1627 1697 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1628 1698 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1629 1699 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1630 1700 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1631 1701
1632 1702
1633 1703 /* values for SAS ProgrammedLinkRate fields */
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1634 1704 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1635 1705 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1636 1706 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1637 1707 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1638 1708 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1639 1709 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1640 1710 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1641 1711 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1642 1712 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1643 1713 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1714 +#define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
1644 1715
1645 1716
1646 1717 /* values for SAS HwLinkRate fields */
1647 1718 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1648 1719 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1649 1720 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1650 1721 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1651 1722 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1652 1723 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1653 1724 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1654 1725 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1726 +#define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
1655 1727
1656 1728
1657 1729
1658 1730 /****************************************************************************
1659 1731 * SAS IO Unit Config Pages
1660 1732 ****************************************************************************/
1661 1733
1662 1734 /* SAS IO Unit Page 0 */
1663 1735
1664 1736 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1665 1737 {
1666 1738 U8 Port; /* 0x00 */
1667 1739 U8 PortFlags; /* 0x01 */
1668 1740 U8 PhyFlags; /* 0x02 */
1669 1741 U8 NegotiatedLinkRate; /* 0x03 */
1670 1742 U32 ControllerPhyDeviceInfo;/* 0x04 */
1671 1743 U16 AttachedDevHandle; /* 0x08 */
1672 1744 U16 ControllerDevHandle; /* 0x0A */
1673 1745 U32 DiscoveryStatus; /* 0x0C */
1674 1746 U32 Reserved; /* 0x10 */
1675 1747 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1676 1748 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1677 1749
1678 1750 /*
1679 1751 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1680 1752 * one and check Header.ExtPageLength or NumPhys at runtime.
1681 1753 */
1682 1754 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1683 1755 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1684 1756 #endif
1685 1757
1686 1758 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1687 1759 {
1688 1760 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1689 1761 U32 Reserved1; /* 0x08 */
1690 1762 U8 NumPhys; /* 0x0C */
1691 1763 U8 Reserved2; /* 0x0D */
1692 1764 U16 Reserved3; /* 0x0E */
1693 1765 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1694 1766 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1695 1767 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1696 1768 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1697 1769
1698 1770 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1699 1771
1700 1772 /* values for SAS IO Unit Page 0 PortFlags */
1701 1773 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1702 1774 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1703 1775
1704 1776 /* values for SAS IO Unit Page 0 PhyFlags */
1705 1777 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1706 1778 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1707 1779
1708 1780 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1709 1781
1710 1782 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1711 1783
1712 1784 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1713 1785 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1714 1786 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1715 1787 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1716 1788 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1717 1789 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1718 1790 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1719 1791 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1720 1792 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1721 1793 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1722 1794 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1723 1795 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1724 1796 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1725 1797 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1726 1798 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1727 1799 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1728 1800 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1729 1801 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1730 1802 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1731 1803 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1732 1804 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1733 1805
1734 1806
1735 1807 /* SAS IO Unit Page 1 */
1736 1808
1737 1809 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1738 1810 {
1739 1811 U8 Port; /* 0x00 */
1740 1812 U8 PortFlags; /* 0x01 */
1741 1813 U8 PhyFlags; /* 0x02 */
1742 1814 U8 MaxMinLinkRate; /* 0x03 */
1743 1815 U32 ControllerPhyDeviceInfo; /* 0x04 */
1744 1816 U16 MaxTargetPortConnectTime; /* 0x08 */
1745 1817 U16 Reserved1; /* 0x0A */
1746 1818 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1747 1819 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1748 1820
1749 1821 /*
1750 1822 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1751 1823 * one and check Header.ExtPageLength or NumPhys at runtime.
1752 1824 */
1753 1825 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1754 1826 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1755 1827 #endif
1756 1828
1757 1829 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1758 1830 {
1759 1831 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1760 1832 U16 ControlFlags; /* 0x08 */
1761 1833 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1762 1834 U16 AdditionalControlFlags; /* 0x0C */
1763 1835 U16 SASWideMaxQueueDepth; /* 0x0E */
1764 1836 U8 NumPhys; /* 0x10 */
1765 1837 U8 SATAMaxQDepth; /* 0x11 */
1766 1838 U8 ReportDeviceMissingDelay; /* 0x12 */
1767 1839 U8 IODeviceMissingDelay; /* 0x13 */
1768 1840 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1769 1841 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1770 1842 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1771 1843 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1772 1844
1773 1845 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1774 1846
1775 1847 /* values for SAS IO Unit Page 1 ControlFlags */
1776 1848 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1777 1849 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1778 1850 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1779 1851 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1780 1852
1781 1853 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1782 1854 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1783 1855 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1784 1856 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1785 1857 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1786 1858
1787 1859 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1788 1860 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1789 1861 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1790 1862 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1791 1863 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1792 1864 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1793 1865 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1794 1866 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1795 1867
1796 1868 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1797 1869 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1798 1870 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1799 1871 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1800 1872 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1801 1873 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1802 1874 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1803 1875 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1804 1876 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1805 1877
1806 1878 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1807 1879 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1808 1880 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1809 1881
1810 1882 /* values for SAS IO Unit Page 1 PortFlags */
1811 1883 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
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1812 1884
1813 1885 /* values for SAS IO Unit Page 1 PhyFlags */
1814 1886 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1815 1887 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1816 1888
1817 1889 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1818 1890 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1819 1891 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1820 1892 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1821 1893 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1894 +#define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
1822 1895 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1823 1896 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1824 1897 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1825 1898 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1899 +#define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
1826 1900
1827 1901 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1828 1902
1829 1903
1830 1904 /* SAS IO Unit Page 4 */
1831 1905
1832 1906 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1833 1907 {
1834 1908 U8 MaxTargetSpinup; /* 0x00 */
1835 1909 U8 SpinupDelay; /* 0x01 */
1836 1910 U16 Reserved1; /* 0x02 */
1837 1911 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1838 1912 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1839 1913
1840 1914 /*
1841 1915 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1842 1916 * four and check Header.ExtPageLength or NumPhys at runtime.
1843 1917 */
1844 1918 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1845 1919 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1846 1920 #endif
1847 1921
1848 1922 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1849 1923 {
1850 1924 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1851 1925 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1852 1926 U32 Reserved1; /* 0x18 */
1853 1927 U32 Reserved2; /* 0x1C */
1854 1928 U32 Reserved3; /* 0x20 */
1855 1929 U8 BootDeviceWaitTime; /* 0x24 */
1856 1930 U8 Reserved4; /* 0x25 */
1857 1931 U16 Reserved5; /* 0x26 */
1858 1932 U8 NumPhys; /* 0x28 */
1859 1933 U8 PEInitialSpinupDelay; /* 0x29 */
1860 1934 U8 PEReplyDelay; /* 0x2A */
1861 1935 U8 Flags; /* 0x2B */
1862 1936 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1863 1937 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1864 1938 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1865 1939 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1866 1940
1867 1941 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1868 1942
1869 1943 /* defines for Flags field */
1870 1944 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
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1871 1945
1872 1946 /* defines for PHY field */
1873 1947 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1874 1948
1875 1949
1876 1950 /* SAS IO Unit Page 5 */
1877 1951
1878 1952 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
1879 1953 {
1880 1954 U8 ControlFlags; /* 0x00 */
1881 - U8 Reserved1; /* 0x01 */
1955 + U8 PortWidthModGroup; /* 0x01 */
1882 1956 U16 InactivityTimerExponent; /* 0x02 */
1883 1957 U8 SATAPartialTimeout; /* 0x04 */
1884 1958 U8 Reserved2; /* 0x05 */
1885 1959 U8 SATASlumberTimeout; /* 0x06 */
1886 1960 U8 Reserved3; /* 0x07 */
1887 1961 U8 SASPartialTimeout; /* 0x08 */
1888 1962 U8 Reserved4; /* 0x09 */
1889 1963 U8 SASSlumberTimeout; /* 0x0A */
1890 1964 U8 Reserved5; /* 0x0B */
1891 1965 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1892 1966 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1893 1967 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1894 1968
1895 1969 /* defines for ControlFlags field */
1896 1970 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1897 1971 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1898 1972 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1899 1973 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1900 1974
1975 +/* defines for PortWidthModeGroup field */
1976 +#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
1977 +
1901 1978 /* defines for InactivityTimerExponent field */
1902 1979 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
1903 1980 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
1904 1981 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
1905 1982 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
1906 1983 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
1907 1984 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
1908 1985 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
1909 1986 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
1910 1987
1911 1988 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
1912 1989 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
1913 1990 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
1914 1991 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
1915 1992 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
1916 1993 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
1917 1994 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
1918 1995 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
1919 1996
1920 1997 /*
1921 1998 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1922 1999 * one and check Header.ExtPageLength or NumPhys at runtime.
1923 2000 */
1924 2001 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
1925 2002 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
1926 2003 #endif
1927 2004
1928 2005 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
1929 2006 {
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1930 2007 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1931 2008 U8 NumPhys; /* 0x08 */
1932 2009 U8 Reserved1; /* 0x09 */
1933 2010 U16 Reserved2; /* 0x0A */
1934 2011 U32 Reserved3; /* 0x0C */
1935 2012 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
1936 2013 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
1937 2014 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
1938 2015 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
1939 2016
1940 -#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x00)
2017 +#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2018 +
2019 +
2020 +/* SAS IO Unit Page 6 */
2021 +
2022 +typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2023 +{
2024 + U8 CurrentStatus; /* 0x00 */
2025 + U8 CurrentModulation; /* 0x01 */
2026 + U8 CurrentUtilization; /* 0x02 */
2027 + U8 Reserved1; /* 0x03 */
2028 + U32 Reserved2; /* 0x04 */
2029 +} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2030 + MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2031 + Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2032 + MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2033 +
2034 +/* defines for CurrentStatus field */
2035 +#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2036 +#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2037 +#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2038 +#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2039 +#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2040 +#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2041 +#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2042 +#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2043 +
2044 +/* defines for CurrentModulation field */
2045 +#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2046 +#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2047 +#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2048 +#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2049 +
2050 +/*
2051 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2052 + * one and check the value returned for NumGroups at runtime.
2053 + */
2054 +#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2055 +#define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2056 +#endif
2057 +
2058 +typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6
2059 +{
2060 + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2061 + U32 Reserved1; /* 0x08 */
2062 + U32 Reserved2; /* 0x0C */
2063 + U8 NumGroups; /* 0x10 */
2064 + U8 Reserved3; /* 0x11 */
2065 + U16 Reserved4; /* 0x12 */
2066 + MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2067 + PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2068 +} MPI2_CONFIG_PAGE_SASIOUNIT_6,
2069 + MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2070 + Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2071 +
2072 +#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2073 +
2074 +
2075 +/* SAS IO Unit Page 7 */
2076 +
2077 +typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2078 +{
2079 + U8 Flags; /* 0x00 */
2080 + U8 Reserved1; /* 0x01 */
2081 + U16 Reserved2; /* 0x02 */
2082 + U8 Threshold75Pct; /* 0x04 */
2083 + U8 Threshold50Pct; /* 0x05 */
2084 + U8 Threshold25Pct; /* 0x06 */
2085 + U8 Reserved3; /* 0x07 */
2086 +} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2087 + MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2088 + Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2089 + MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2090 +
2091 +/* defines for Flags field */
2092 +#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2093 +
2094 +
2095 +/*
2096 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2097 + * one and check the value returned for NumGroups at runtime.
2098 + */
2099 +#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2100 +#define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2101 +#endif
2102 +
2103 +typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7
2104 +{
2105 + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2106 + U8 SamplingInterval; /* 0x08 */
2107 + U8 WindowLength; /* 0x09 */
2108 + U16 Reserved1; /* 0x0A */
2109 + U32 Reserved2; /* 0x0C */
2110 + U32 Reserved3; /* 0x10 */
2111 + U8 NumGroups; /* 0x14 */
2112 + U8 Reserved4; /* 0x15 */
2113 + U16 Reserved5; /* 0x16 */
2114 + MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2115 + PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2116 +} MPI2_CONFIG_PAGE_SASIOUNIT_7,
2117 + MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2118 + Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2119 +
2120 +#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2121 +
2122 +
2123 +/* SAS IO Unit Page 8 */
2124 +
2125 +typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8
2126 +{
2127 + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2128 + U32 Reserved1; /* 0x08 */
2129 + U32 PowerManagementCapabilities; /* 0x0C */
2130 + U32 Reserved2; /* 0x10 */
2131 +} MPI2_CONFIG_PAGE_SASIOUNIT_8,
2132 + MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2133 + Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2134 +
2135 +#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2136 +
2137 +/* defines for PowerManagementCapabilities field */
2138 +#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000)
2139 +#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800)
2140 +#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400)
2141 +#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200)
2142 +#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100)
2143 +#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010)
2144 +#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008)
2145 +#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004)
2146 +#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002)
2147 +#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001)
1941 2148
1942 2149
1943 2150
1944 2151
1945 2152 /****************************************************************************
1946 2153 * SAS Expander Config Pages
1947 2154 ****************************************************************************/
1948 2155
1949 2156 /* SAS Expander Page 0 */
1950 2157
1951 2158 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
1952 2159 {
1953 2160 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1954 2161 U8 PhysicalPort; /* 0x08 */
1955 2162 U8 ReportGenLength; /* 0x09 */
1956 2163 U16 EnclosureHandle; /* 0x0A */
1957 2164 U64 SASAddress; /* 0x0C */
1958 2165 U32 DiscoveryStatus; /* 0x14 */
1959 2166 U16 DevHandle; /* 0x18 */
1960 2167 U16 ParentDevHandle; /* 0x1A */
1961 2168 U16 ExpanderChangeCount; /* 0x1C */
1962 2169 U16 ExpanderRouteIndexes; /* 0x1E */
1963 2170 U8 NumPhys; /* 0x20 */
1964 2171 U8 SASLevel; /* 0x21 */
1965 2172 U16 Flags; /* 0x22 */
1966 2173 U16 STPBusInactivityTimeLimit; /* 0x24 */
1967 2174 U16 STPMaxConnectTimeLimit; /* 0x26 */
1968 2175 U16 STP_SMP_NexusLossTime; /* 0x28 */
1969 2176 U16 MaxNumRoutedSasAddresses; /* 0x2A */
1970 2177 U64 ActiveZoneManagerSASAddress;/* 0x2C */
1971 2178 U16 ZoneLockInactivityLimit; /* 0x34 */
1972 2179 U16 Reserved1; /* 0x36 */
1973 2180 U8 TimeToReducedFunc; /* 0x38 */
1974 2181 U8 InitialTimeToReducedFunc; /* 0x39 */
1975 2182 U8 MaxReducedFuncTime; /* 0x3A */
1976 2183 U8 Reserved2; /* 0x3B */
1977 2184 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
1978 2185 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
1979 2186
1980 2187 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
1981 2188
1982 2189 /* values for SAS Expander Page 0 DiscoveryStatus field */
1983 2190 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1984 2191 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1985 2192 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
1986 2193 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1987 2194 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1988 2195 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1989 2196 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1990 2197 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
1991 2198 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1992 2199 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
1993 2200 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
1994 2201 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
1995 2202 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
1996 2203 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
1997 2204 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
1998 2205 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1999 2206 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2000 2207 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2001 2208 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2002 2209 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2003 2210
2004 2211 /* values for SAS Expander Page 0 Flags field */
2005 2212 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2006 2213 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2007 2214 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2008 2215 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2009 2216 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2010 2217 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2011 2218 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2012 2219 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2013 2220 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2014 2221 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2015 2222 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2016 2223
2017 2224
2018 2225 /* SAS Expander Page 1 */
2019 2226
2020 2227 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2021 2228 {
2022 2229 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2023 2230 U8 PhysicalPort; /* 0x08 */
2024 2231 U8 Reserved1; /* 0x09 */
2025 2232 U16 Reserved2; /* 0x0A */
2026 2233 U8 NumPhys; /* 0x0C */
2027 2234 U8 Phy; /* 0x0D */
2028 2235 U16 NumTableEntriesProgrammed; /* 0x0E */
2029 2236 U8 ProgrammedLinkRate; /* 0x10 */
2030 2237 U8 HwLinkRate; /* 0x11 */
2031 2238 U16 AttachedDevHandle; /* 0x12 */
2032 2239 U32 PhyInfo; /* 0x14 */
2033 2240 U32 AttachedDeviceInfo; /* 0x18 */
2034 2241 U16 ExpanderDevHandle; /* 0x1C */
2035 2242 U8 ChangeCount; /* 0x1E */
2036 2243 U8 NegotiatedLinkRate; /* 0x1F */
2037 2244 U8 PhyIdentifier; /* 0x20 */
2038 2245 U8 AttachedPhyIdentifier; /* 0x21 */
2039 2246 U8 Reserved3; /* 0x22 */
2040 2247 U8 DiscoveryInfo; /* 0x23 */
2041 2248 U32 AttachedPhyInfo; /* 0x24 */
2042 2249 U8 ZoneGroup; /* 0x28 */
2043 2250 U8 SelfConfigStatus; /* 0x29 */
2044 2251 U16 Reserved4; /* 0x2A */
2045 2252 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2046 2253 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2047 2254
2048 2255 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2049 2256
2050 2257 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2051 2258
2052 2259 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2053 2260
2054 2261 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2055 2262
2056 2263 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2057 2264
2058 2265 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2059 2266
2060 2267 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2061 2268
2062 2269 /* values for SAS Expander Page 1 DiscoveryInfo field */
2063 2270 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2064 2271 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2065 2272 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2066 2273
2067 2274
2068 2275 /****************************************************************************
2069 2276 * SAS Device Config Pages
2070 2277 ****************************************************************************/
2071 2278
2072 2279 /* SAS Device Page 0 */
2073 2280
2074 2281 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2075 2282 {
2076 2283 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2077 2284 U16 Slot; /* 0x08 */
2078 2285 U16 EnclosureHandle; /* 0x0A */
2079 2286 U64 SASAddress; /* 0x0C */
2080 2287 U16 ParentDevHandle; /* 0x14 */
2081 2288 U8 PhyNum; /* 0x16 */
2082 2289 U8 AccessStatus; /* 0x17 */
2083 2290 U16 DevHandle; /* 0x18 */
2084 2291 U8 AttachedPhyIdentifier; /* 0x1A */
2085 2292 U8 ZoneGroup; /* 0x1B */
2086 2293 U32 DeviceInfo; /* 0x1C */
2087 2294 U16 Flags; /* 0x20 */
2088 2295 U8 PhysicalPort; /* 0x22 */
2089 2296 U8 MaxPortConnections; /* 0x23 */
2090 2297 U64 DeviceName; /* 0x24 */
2091 2298 U8 PortGroups; /* 0x2C */
2092 2299 U8 DmaGroup; /* 0x2D */
2093 2300 U8 ControlGroup; /* 0x2E */
2094 2301 U8 Reserved1; /* 0x2F */
2095 2302 U32 Reserved2; /* 0x30 */
2096 2303 U32 Reserved3; /* 0x34 */
2097 2304 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2098 2305 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2099 2306
2100 2307 #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2101 2308
2102 2309 /* values for SAS Device Page 0 AccessStatus field */
2103 2310 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2104 2311 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2105 2312 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2106 2313 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2107 2314 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2108 2315 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2109 2316 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2110 2317 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2111 2318 /* specific values for SATA Init failures */
2112 2319 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2113 2320 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2114 2321 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2115 2322 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2116 2323 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
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2117 2324 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2118 2325 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2119 2326 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2120 2327 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2121 2328 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2122 2329 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2123 2330
2124 2331 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2125 2332
2126 2333 /* values for SAS Device Page 0 Flags field */
2334 +#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2335 +#define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2127 2336 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2128 2337 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2129 2338 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2130 2339 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2131 2340 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2132 2341 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2133 2342 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2134 2343 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2135 2344 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2136 2345 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2137 2346 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2138 2347
2139 2348
2140 2349 /* SAS Device Page 1 */
2141 2350
2142 2351 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2143 2352 {
2144 2353 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2145 2354 U32 Reserved1; /* 0x08 */
2146 2355 U64 SASAddress; /* 0x0C */
2147 2356 U32 Reserved2; /* 0x14 */
2148 2357 U16 DevHandle; /* 0x18 */
2149 2358 U16 Reserved3; /* 0x1A */
2150 2359 U8 InitialRegDeviceFIS[20];/* 0x1C */
2151 2360 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2152 2361 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2153 2362
2154 2363 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2155 2364
2156 2365
2157 2366 /****************************************************************************
2158 2367 * SAS PHY Config Pages
2159 2368 ****************************************************************************/
2160 2369
2161 2370 /* SAS PHY Page 0 */
2162 2371
2163 2372 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2164 2373 {
2165 2374 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2166 2375 U16 OwnerDevHandle; /* 0x08 */
2167 2376 U16 Reserved1; /* 0x0A */
2168 2377 U16 AttachedDevHandle; /* 0x0C */
2169 2378 U8 AttachedPhyIdentifier; /* 0x0E */
2170 2379 U8 Reserved2; /* 0x0F */
2171 2380 U32 AttachedPhyInfo; /* 0x10 */
2172 2381 U8 ProgrammedLinkRate; /* 0x14 */
2173 2382 U8 HwLinkRate; /* 0x15 */
2174 2383 U8 ChangeCount; /* 0x16 */
2175 2384 U8 Flags; /* 0x17 */
2176 2385 U32 PhyInfo; /* 0x18 */
2177 2386 U8 NegotiatedLinkRate; /* 0x1C */
2178 2387 U8 Reserved3; /* 0x1D */
2179 2388 U16 Reserved4; /* 0x1E */
2180 2389 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2181 2390 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2182 2391
2183 2392 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2184 2393
2185 2394 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2186 2395
2187 2396 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2188 2397
2189 2398 /* values for SAS PHY Page 0 Flags field */
2190 2399 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2191 2400
2192 2401 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2193 2402
2194 2403 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2195 2404
2196 2405 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2197 2406
2198 2407
2199 2408 /* SAS PHY Page 1 */
2200 2409
2201 2410 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2202 2411 {
2203 2412 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2204 2413 U32 Reserved1; /* 0x08 */
2205 2414 U32 InvalidDwordCount; /* 0x0C */
2206 2415 U32 RunningDisparityErrorCount; /* 0x10 */
2207 2416 U32 LossDwordSynchCount; /* 0x14 */
2208 2417 U32 PhyResetProblemCount; /* 0x18 */
2209 2418 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2210 2419 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2211 2420
2212 2421 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2213 2422
2214 2423
2215 2424 /* SAS PHY Page 2 */
2216 2425
2217 2426 typedef struct _MPI2_SASPHY2_PHY_EVENT
2218 2427 {
2219 2428 U8 PhyEventCode; /* 0x00 */
2220 2429 U8 Reserved1; /* 0x01 */
2221 2430 U16 Reserved2; /* 0x02 */
2222 2431 U32 PhyEventInfo; /* 0x04 */
2223 2432 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2224 2433 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2225 2434
2226 2435 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2227 2436
2228 2437
2229 2438 /*
2230 2439 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2231 2440 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2232 2441 */
2233 2442 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2234 2443 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2235 2444 #endif
2236 2445
2237 2446 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2
2238 2447 {
2239 2448 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2240 2449 U32 Reserved1; /* 0x08 */
2241 2450 U8 NumPhyEvents; /* 0x0C */
2242 2451 U8 Reserved2; /* 0x0D */
2243 2452 U16 Reserved3; /* 0x0E */
2244 2453 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
2245 2454 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2246 2455 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2247 2456
2248 2457 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2249 2458
2250 2459
2251 2460 /* SAS PHY Page 3 */
2252 2461
2253 2462 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG
2254 2463 {
2255 2464 U8 PhyEventCode; /* 0x00 */
2256 2465 U8 Reserved1; /* 0x01 */
2257 2466 U16 Reserved2; /* 0x02 */
2258 2467 U8 CounterType; /* 0x04 */
2259 2468 U8 ThresholdWindow; /* 0x05 */
2260 2469 U8 TimeUnits; /* 0x06 */
2261 2470 U8 Reserved3; /* 0x07 */
2262 2471 U32 EventThreshold; /* 0x08 */
2263 2472 U16 ThresholdFlags; /* 0x0C */
2264 2473 U16 Reserved4; /* 0x0E */
2265 2474 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2266 2475 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2267 2476
2268 2477 /* values for PhyEventCode field */
2269 2478 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2270 2479 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2271 2480 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2272 2481 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2273 2482 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2274 2483 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2275 2484 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2276 2485 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2277 2486 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2278 2487 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2279 2488 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2280 2489 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2281 2490 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2282 2491 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2283 2492 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2284 2493 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2285 2494 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2286 2495 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2287 2496 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2288 2497 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2289 2498 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2290 2499 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2291 2500 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2292 2501 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2293 2502 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2294 2503 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2295 2504 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2296 2505 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2297 2506 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2298 2507 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2299 2508 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2300 2509 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2301 2510 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2302 2511 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2303 2512 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2304 2513 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2305 2514 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2306 2515
2307 2516 /* values for the CounterType field */
2308 2517 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2309 2518 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2310 2519 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2311 2520
2312 2521 /* values for the TimeUnits field */
2313 2522 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2314 2523 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2315 2524 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2316 2525 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2317 2526
2318 2527 /* values for the ThresholdFlags field */
2319 2528 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2320 2529 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2321 2530
2322 2531 /*
2323 2532 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2324 2533 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2325 2534 */
2326 2535 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2327 2536 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2328 2537 #endif
2329 2538
2330 2539 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
2331 2540 {
2332 2541 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2333 2542 U32 Reserved1; /* 0x08 */
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2334 2543 U8 NumPhyEvents; /* 0x0C */
2335 2544 U8 Reserved2; /* 0x0D */
2336 2545 U16 Reserved3; /* 0x0E */
2337 2546 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2338 2547 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2339 2548 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2340 2549
2341 2550 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2342 2551
2343 2552
2553 +/* SAS PHY Page 4 */
2554 +
2555 +typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4
2556 +{
2557 + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2558 + U16 Reserved1; /* 0x08 */
2559 + U8 Reserved2; /* 0x0A */
2560 + U8 Flags; /* 0x0B */
2561 + U8 InitialFrame[28]; /* 0x0C */
2562 +} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2563 + Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2564 +
2565 +#define MPI2_SASPHY4_PAGEVERSION (0x00)
2566 +
2567 +/* values for the Flags field */
2568 +#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2569 +#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2570 +
2571 +
2572 +
2573 +
2344 2574 /****************************************************************************
2345 2575 * SAS Port Config Pages
2346 2576 ****************************************************************************/
2347 2577
2348 2578 /* SAS Port Page 0 */
2349 2579
2350 2580 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2351 2581 {
2352 2582 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2353 2583 U8 PortNumber; /* 0x08 */
2354 2584 U8 PhysicalPort; /* 0x09 */
2355 2585 U8 PortWidth; /* 0x0A */
2356 2586 U8 PhysicalPortWidth; /* 0x0B */
2357 2587 U8 ZoneGroup; /* 0x0C */
2358 2588 U8 Reserved1; /* 0x0D */
2359 2589 U16 Reserved2; /* 0x0E */
2360 2590 U64 SASAddress; /* 0x10 */
2361 2591 U32 DeviceInfo; /* 0x18 */
2362 2592 U32 Reserved3; /* 0x1C */
2363 2593 U32 Reserved4; /* 0x20 */
2364 2594 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2365 2595 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2366 2596
2367 2597 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2368 2598
2369 2599 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2370 2600
2371 2601
2372 2602 /****************************************************************************
2373 2603 * SAS Enclosure Config Pages
2374 2604 ****************************************************************************/
2375 2605
2376 2606 /* SAS Enclosure Page 0 */
2377 2607
2378 2608 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2379 2609 {
2380 2610 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2381 2611 U32 Reserved1; /* 0x08 */
2382 2612 U64 EnclosureLogicalID; /* 0x0C */
2383 2613 U16 Flags; /* 0x14 */
2384 2614 U16 EnclosureHandle; /* 0x16 */
2385 2615 U16 NumSlots; /* 0x18 */
2386 2616 U16 StartSlot; /* 0x1A */
2387 2617 U16 Reserved2; /* 0x1C */
2388 2618 U16 SEPDevHandle; /* 0x1E */
2389 2619 U32 Reserved3; /* 0x20 */
2390 2620 U32 Reserved4; /* 0x24 */
2391 2621 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2392 2622 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2393 2623 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2394 2624
2395 2625 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2396 2626
2397 2627 /* values for SAS Enclosure Page 0 Flags field */
2398 2628 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2399 2629 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2400 2630 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2401 2631 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2402 2632 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2403 2633 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2404 2634 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2405 2635
2406 2636
2407 2637 /****************************************************************************
2408 2638 * Log Config Page
2409 2639 ****************************************************************************/
2410 2640
2411 2641 /* Log Page 0 */
2412 2642
2413 2643 /*
2414 2644 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2415 2645 * one and check Header.ExtPageLength or NumPhys at runtime.
2416 2646 */
2417 2647 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2418 2648 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2419 2649 #endif
2420 2650
2421 2651 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2422 2652
2423 2653 typedef struct _MPI2_LOG_0_ENTRY
2424 2654 {
2425 2655 U64 TimeStamp; /* 0x00 */
2426 2656 U32 Reserved1; /* 0x08 */
2427 2657 U16 LogSequence; /* 0x0C */
2428 2658 U16 LogEntryQualifier; /* 0x0E */
2429 2659 U8 VP_ID; /* 0x10 */
2430 2660 U8 VF_ID; /* 0x11 */
2431 2661 U16 Reserved2; /* 0x12 */
2432 2662 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2433 2663 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2434 2664 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2435 2665
2436 2666 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2437 2667 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2438 2668 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2439 2669 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2440 2670 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2441 2671 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2442 2672
2443 2673 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2444 2674 {
2445 2675 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2446 2676 U32 Reserved1; /* 0x08 */
2447 2677 U32 Reserved2; /* 0x0C */
2448 2678 U16 NumLogEntries; /* 0x10 */
2449 2679 U16 Reserved3; /* 0x12 */
2450 2680 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2451 2681 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2452 2682 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2453 2683
2454 2684 #define MPI2_LOG_0_PAGEVERSION (0x02)
2455 2685
2456 2686
2457 2687 /****************************************************************************
2458 2688 * RAID Config Page
2459 2689 ****************************************************************************/
2460 2690
2461 2691 /* RAID Page 0 */
2462 2692
2463 2693 /*
2464 2694 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2465 2695 * one and check Header.ExtPageLength or NumPhys at runtime.
2466 2696 */
2467 2697 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2468 2698 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2469 2699 #endif
2470 2700
2471 2701 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2472 2702 {
2473 2703 U16 ElementFlags; /* 0x00 */
2474 2704 U16 VolDevHandle; /* 0x02 */
2475 2705 U8 HotSparePool; /* 0x04 */
2476 2706 U8 PhysDiskNum; /* 0x05 */
2477 2707 U16 PhysDiskDevHandle; /* 0x06 */
2478 2708 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2479 2709 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2480 2710 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2481 2711
2482 2712 /* values for the ElementFlags field */
2483 2713 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2484 2714 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2485 2715 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2486 2716 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2487 2717 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2488 2718
2489 2719
2490 2720 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2491 2721 {
2492 2722 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2493 2723 U8 NumHotSpares; /* 0x08 */
2494 2724 U8 NumPhysDisks; /* 0x09 */
2495 2725 U8 NumVolumes; /* 0x0A */
2496 2726 U8 ConfigNum; /* 0x0B */
2497 2727 U32 Flags; /* 0x0C */
2498 2728 U8 ConfigGUID[24]; /* 0x10 */
2499 2729 U32 Reserved1; /* 0x28 */
2500 2730 U8 NumElements; /* 0x2C */
2501 2731 U8 Reserved2; /* 0x2D */
2502 2732 U16 Reserved3; /* 0x2E */
2503 2733 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2504 2734 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2505 2735 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2506 2736 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2507 2737
2508 2738 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2509 2739
2510 2740 /* values for RAID Configuration Page 0 Flags field */
2511 2741 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2512 2742
2513 2743
2514 2744 /****************************************************************************
2515 2745 * Driver Persistent Mapping Config Pages
2516 2746 ****************************************************************************/
2517 2747
2518 2748 /* Driver Persistent Mapping Page 0 */
2519 2749
2520 2750 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2521 2751 {
2522 2752 U64 PhysicalIdentifier; /* 0x00 */
2523 2753 U16 MappingInformation; /* 0x08 */
2524 2754 U16 DeviceIndex; /* 0x0A */
2525 2755 U32 PhysicalBitsMapping; /* 0x0C */
2526 2756 U32 Reserved1; /* 0x10 */
2527 2757 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2528 2758 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2529 2759 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2530 2760
2531 2761 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2532 2762 {
2533 2763 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2534 2764 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2535 2765 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2536 2766 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2537 2767 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2538 2768
2539 2769 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2540 2770
2541 2771 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2542 2772 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2543 2773 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2544 2774 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2545 2775
2546 2776
2547 2777 /****************************************************************************
2548 2778 * Ethernet Config Pages
2549 2779 ****************************************************************************/
2550 2780
2551 2781 /* Ethernet Page 0 */
2552 2782
2553 2783 /* IP address (union of IPv4 and IPv6) */
2554 2784 typedef union _MPI2_ETHERNET_IP_ADDR
2555 2785 {
2556 2786 U32 IPv4Addr;
2557 2787 U32 IPv6Addr[4];
2558 2788 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2559 2789 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2560 2790
2561 2791 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2562 2792
2563 2793 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0
2564 2794 {
2565 2795 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2566 2796 U8 NumInterfaces; /* 0x08 */
2567 2797 U8 Reserved0; /* 0x09 */
2568 2798 U16 Reserved1; /* 0x0A */
2569 2799 U32 Status; /* 0x0C */
2570 2800 U8 MediaState; /* 0x10 */
2571 2801 U8 Reserved2; /* 0x11 */
2572 2802 U16 Reserved3; /* 0x12 */
2573 2803 U8 MacAddress[6]; /* 0x14 */
2574 2804 U8 Reserved4; /* 0x1A */
2575 2805 U8 Reserved5; /* 0x1B */
2576 2806 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2577 2807 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2578 2808 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2579 2809 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2580 2810 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2581 2811 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2582 2812 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2583 2813 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2584 2814 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2585 2815
2586 2816 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2587 2817
2588 2818 /* values for Ethernet Page 0 Status field */
2589 2819 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2590 2820 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2591 2821 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2592 2822 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2593 2823 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2594 2824 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2595 2825 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2596 2826 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2597 2827 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2598 2828 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2599 2829 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2600 2830 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2601 2831
2602 2832 /* values for Ethernet Page 0 MediaState field */
2603 2833 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2604 2834 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2605 2835 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2606 2836
2607 2837 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2608 2838 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2609 2839 #define MPI2_ETHPG0_MS_10MBIT (0x01)
2610 2840 #define MPI2_ETHPG0_MS_100MBIT (0x02)
2611 2841 #define MPI2_ETHPG0_MS_1GBIT (0x03)
2612 2842
2613 2843
2614 2844 /* Ethernet Page 1 */
2615 2845
2616 2846 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1
2617 2847 {
2618 2848 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2619 2849 U32 Reserved0; /* 0x08 */
2620 2850 U32 Flags; /* 0x0C */
2621 2851 U8 MediaState; /* 0x10 */
2622 2852 U8 Reserved1; /* 0x11 */
2623 2853 U16 Reserved2; /* 0x12 */
2624 2854 U8 MacAddress[6]; /* 0x14 */
2625 2855 U8 Reserved3; /* 0x1A */
2626 2856 U8 Reserved4; /* 0x1B */
2627 2857 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2628 2858 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2629 2859 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2630 2860 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2631 2861 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2632 2862 U32 Reserved5; /* 0x6C */
2633 2863 U32 Reserved6; /* 0x70 */
2634 2864 U32 Reserved7; /* 0x74 */
2635 2865 U32 Reserved8; /* 0x78 */
2636 2866 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2637 2867 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2638 2868 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2639 2869
2640 2870 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2641 2871
2642 2872 /* values for Ethernet Page 1 Flags field */
2643 2873 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2644 2874 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2645 2875 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2646 2876 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2647 2877 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2648 2878 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2649 2879 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2650 2880 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2651 2881 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2652 2882
2653 2883 /* values for Ethernet Page 1 MediaState field */
2654 2884 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
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2655 2885 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2656 2886 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2657 2887
2658 2888 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2659 2889 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2660 2890 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2661 2891 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2662 2892 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2663 2893
2664 2894
2895 +/****************************************************************************
2896 +* Extended Manufacturing Config Pages
2897 +****************************************************************************/
2898 +
2899 +/*
2900 + * Generic structure to use for product-specific extended manufacturing pages
2901 + * (currently Extended Manufacturing Page 40 through Extended Manufacturing
2902 + * Page 60).
2903 + */
2904 +
2905 +typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS
2906 +{
2907 + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2908 + U32 ProductSpecificInfo; /* 0x08 */
2909 +} MPI2_CONFIG_PAGE_EXT_MAN_PS,
2910 + MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
2911 + Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
2912 +
2913 +/* PageVersion should be provided by product-specific code */
2914 +
2665 2915 #endif
2666 2916
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