3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2000 to 2009, LSI Corporation.
24 * All rights reserved.
25 *
26 * Redistribution and use in source and binary forms of all code within
27 * this file that is exclusively owned by LSI, with or without
28 * modification, is permitted provided that, in addition to the CDDL 1.0
29 * License requirements, the following conditions are met:
30 *
31 * Neither the name of the author nor the names of its contributors may be
32 * used to endorse or promote products derived from this software without
33 * specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
38 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
39 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
41 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
42 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
43 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
45 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46 * DAMAGE.
47 */
48
49 /*
50 * Name: mpi2_cnfg.h
51 * Title: MPI Configuration messages and pages
52 * Creation Date: November 10, 2006
53 *
54 * mpi2_cnfg.h Version: 02.00.12
55 *
56 * Version History
57 * ---------------
58 *
59 * Date Version Description
60 * -------- -------- ------------------------------------------------------
61 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
62 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
63 * Added Manufacturing Page 11.
64 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
65 * define.
66 * 06-26-07 02.00.02 Adding generic structure for product-specific
67 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
68 * Rework of BIOS Page 2 configuration page.
69 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
70 * forms.
71 * Added configuration pages IOC Page 8 and Driver
72 * Persistent Mapping Page 0.
73 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
74 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
135 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
136 * and SAS Expander Page 0 to flag a downstream initiator
137 * when in simplified routing mode.
138 * Removed SATA Init Failure defines for DiscoveryStatus
139 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
140 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
141 * Added PortGroups, DmaGroup, and ControlGroup fields to
142 * SAS Device Page 0.
143 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
144 * Unit Page 6.
145 * Added expander reduced functionality data to SAS
146 * Expander Page 0.
147 * Added SAS PHY Page 2 and SAS PHY Page 3.
148 * 07-30-09 02.00.12 Added IO Unit Page 7.
149 * Added new device ids.
150 * Added SAS IO Unit Page 5.
151 * Added partial and slumber power management capable flags
152 * to SAS Device Page 0 Flags field.
153 * Added PhyInfo defines for power condition.
154 * Added Ethernet configuration pages.
155 * --------------------------------------------------------------------------
156 */
157
158 #ifndef MPI2_CNFG_H
159 #define MPI2_CNFG_H
160
161 /*****************************************************************************
162 * Configuration Page Header and defines
163 *****************************************************************************/
164
165 /* Config Page Header */
166 typedef struct _MPI2_CONFIG_PAGE_HEADER
167 {
168 U8 PageVersion; /* 0x00 */
169 U8 PageLength; /* 0x01 */
170 U8 PageNumber; /* 0x02 */
171 U8 PageType; /* 0x03 */
172 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
173 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
174
218 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
219 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
220 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
221 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
222 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
223
224 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
225
226
227 /* ExtPageType field values */
228 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
229 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
230 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
231 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
232 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
233 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
234 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
235 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
236 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
237 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
238
239
240 /*****************************************************************************
241 * PageAddress defines
242 *****************************************************************************/
243
244 /* RAID Volume PageAddress format */
245 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
246 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
247 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
248
249 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
250
251
252 /* RAID Physical Disk PageAddress format */
253 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
254 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
255 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
256 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
257
384 U16 IOCStatus; /* 0x0E */
385 U32 IOCLogInfo; /* 0x10 */
386 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
387 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
388 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
389
390
391
392 /*****************************************************************************
393 *
394 * C o n f i g u r a t i o n P a g e s
395 *
396 *****************************************************************************/
397
398 /****************************************************************************
399 * Manufacturing Config pages
400 ****************************************************************************/
401
402 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
403
404 /* SAS */
405 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
406 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
407 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
408 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
409 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
410 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
411 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
412
413 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
414 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
415 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
416 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
417 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
418 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
419 #define MPI2_MFGPAGE_DEVID_SAS2208_7 (0x0086)
420 #define MPI2_MFGPAGE_DEVID_SAS2208_8 (0x0087)
421
422
423 /* Manufacturing Page 0 */
424
425 typedef struct _MPI2_CONFIG_PAGE_MAN_0
426 {
427 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
428 U8 ChipName[16]; /* 0x04 */
429 U8 ChipRevision[8]; /* 0x14 */
430 U8 BoardName[16]; /* 0x1C */
431 U8 BoardAssembly[16]; /* 0x2C */
432 U8 BoardTracerNumber[16]; /* 0x3C */
433 } MPI2_CONFIG_PAGE_MAN_0,
434 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
435 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
436
437 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
438
439
440 /* Manufacturing Page 1 */
441
615 /* Manufacturing Page 6 */
616
617 typedef struct _MPI2_CONFIG_PAGE_MAN_6
618 {
619 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
620 U32 ProductSpecificInfo;/* 0x04 */
621 } MPI2_CONFIG_PAGE_MAN_6,
622 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
623 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
624
625 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
626
627
628 /* Manufacturing Page 7 */
629
630 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
631 {
632 U32 Pinout; /* 0x00 */
633 U8 Connector[16]; /* 0x04 */
634 U8 Location; /* 0x14 */
635 U8 Reserved1; /* 0x15 */
636 U16 Slot; /* 0x16 */
637 U32 Reserved2; /* 0x18 */
638 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
639 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
640
641 /* defines for the Pinout field */
642 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
643 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
644 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
645 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
646 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
647 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
648 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
649 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
650 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
651 #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
652
653 /* defines for the Location field */
654 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
655 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
665 */
666 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
667 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
668 #endif
669
670 typedef struct _MPI2_CONFIG_PAGE_MAN_7
671 {
672 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
673 U32 Reserved1; /* 0x04 */
674 U32 Reserved2; /* 0x08 */
675 U32 Flags; /* 0x0C */
676 U8 EnclosureName[16]; /* 0x10 */
677 U8 NumPhys; /* 0x20 */
678 U8 Reserved3; /* 0x21 */
679 U16 Reserved4; /* 0x22 */
680 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
681 } MPI2_CONFIG_PAGE_MAN_7,
682 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
683 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
684
685 #define MPI2_MANUFACTURING7_PAGEVERSION (0x00)
686
687 /* defines for the Flags field */
688 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
689
690
691 /*
692 * Generic structure to use for product-specific manufacturing pages
693 * (currently Manufacturing Page 8 through Manufacturing Page 31).
694 */
695
696 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
697 {
698 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
699 U32 ProductSpecificInfo;/* 0x04 */
700 } MPI2_CONFIG_PAGE_MAN_PS,
701 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
702 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
703
704 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
705 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
740 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
741 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
742 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
743 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
744
745 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
746
747
748 /* IO Unit Page 1 */
749
750 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
751 {
752 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
753 U32 Flags; /* 0x04 */
754 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
755 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
756
757 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
758
759 /* IO Unit Page 1 Flags defines */
760 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
761 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
762 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
763 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
764 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
765 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
766 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
767 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
768 #define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
769 #define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
770
771
772 /* IO Unit Page 3 */
773
774 /*
775 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
776 * one and check Header.PageLength at runtime.
777 */
778 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
779 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
780 #endif
850 U32 Reserved2; /* 0x14 */
851 U32 Reserved3; /* 0x18 */
852 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
853 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
854
855 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
856
857 /* defines for IO Unit Page 6 Flags field */
858 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
859
860
861 /* IO Unit Page 7 */
862
863 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
864 {
865 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
866 U16 Reserved1; /* 0x04 */
867 U8 PCIeWidth; /* 0x06 */
868 U8 PCIeSpeed; /* 0x07 */
869 U32 ProcessorState; /* 0x08 */
870 U32 Reserved2; /* 0x0C */
871 U16 IOCTemperature; /* 0x10 */
872 U8 IOCTemperatureUnits; /* 0x12 */
873 U8 IOCSpeed; /* 0x13 */
874 U32 Reserved3; /* 0x14 */
875 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
876 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
877
878 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x00)
879
880 /* defines for IO Unit Page 7 PCIeWidth field */
881 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
882 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
883 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
884 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
885
886 /* defines for IO Unit Page 7 PCIeSpeed field */
887 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
888 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
889 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
890
891 /* defines for IO Unit Page 7 ProcessorState field */
892 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
893 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
894
895 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
896 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
897 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
898
899 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
900 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
901 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
902 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
903
904 /* defines for IO Unit Page 7 IOCSpeed field */
905 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
906 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
907 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
908 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
909
910
911
912 /****************************************************************************
913 * IOC Config Pages
914 ****************************************************************************/
915
916 /* IOC Page 0 */
917
918 typedef struct _MPI2_CONFIG_PAGE_IOC_0
919 {
920 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
921 U32 Reserved1; /* 0x04 */
922 U32 Reserved2; /* 0x08 */
923 U16 VendorID; /* 0x0C */
924 U16 DeviceID; /* 0x0E */
925 U8 RevisionID; /* 0x10 */
926 U8 Reserved3; /* 0x11 */
927 U16 Reserved4; /* 0x12 */
928 U32 ClassCode; /* 0x14 */
929 U16 SubsystemVendorID; /* 0x18 */
1353 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1354
1355 /* values for RAID VolumeType */
1356 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1357 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1358 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1359 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1360 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1361
1362 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1363 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1364 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1365 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1366 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1367 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1368 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1369 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1370 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1371 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1372 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1373 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1374 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1375 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1376 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1377 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1378 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1379 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1380 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1381
1382 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1383 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1384 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1385 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1386 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1387
1388 /* values for RAID Volume Page 0 InactiveStatus field */
1389 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1390 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1391 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1392 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1475 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1476 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1477 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1478
1479 /* OfflineReason defines */
1480 #define MPI2_PHYSDISK0_ONLINE (0x00)
1481 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1482 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1483 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1484 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1485 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1486 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1487
1488 /* IncompatibleReason defines */
1489 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1490 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1491 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1492 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1493 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1494 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1495 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1496
1497 /* PhysDiskAttributes defines */
1498 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1499 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1500 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1501 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1502
1503 /* PhysDiskStatusFlags defines */
1504 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1505 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1506 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1507 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1508 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1509 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1510 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1511 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1512
1513
1514 /* RAID Physical Disk Page 1 */
1515
1516 /*
1517 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1518 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1519 */
1551 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1552
1553 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1554
1555
1556 /****************************************************************************
1557 * values for fields used by several types of SAS Config Pages
1558 ****************************************************************************/
1559
1560 /* values for NegotiatedLinkRates fields */
1561 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1562 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1563 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1564 /* link rates used for Negotiated Physical and Logical Link Rate */
1565 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1566 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1567 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1568 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1569 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1570 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1571 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1572 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1573 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1574
1575
1576 /* values for AttachedPhyInfo fields */
1577 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1578 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1579 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1580
1581 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1582 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1583 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1584 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1585 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1586 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1587 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1588 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1589 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1590 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1591
1592
1593 /* values for PhyInfo fields */
1594 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1595
1596 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1597 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1598 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1599 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1600
1601 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1602 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1603 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1604 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1605 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1606 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1607
1608 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1609 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1610 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1611 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1612 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1613 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1614 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1615 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1616 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1624 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1625 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1626
1627 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1628 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1629 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1630 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1631
1632
1633 /* values for SAS ProgrammedLinkRate fields */
1634 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1635 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1636 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1637 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1638 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1639 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1640 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1641 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1642 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1643 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1644
1645
1646 /* values for SAS HwLinkRate fields */
1647 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1648 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1649 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1650 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1651 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1652 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1653 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1654 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1655
1656
1657
1658 /****************************************************************************
1659 * SAS IO Unit Config Pages
1660 ****************************************************************************/
1661
1662 /* SAS IO Unit Page 0 */
1663
1664 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1665 {
1666 U8 Port; /* 0x00 */
1667 U8 PortFlags; /* 0x01 */
1668 U8 PhyFlags; /* 0x02 */
1669 U8 NegotiatedLinkRate; /* 0x03 */
1670 U32 ControllerPhyDeviceInfo;/* 0x04 */
1671 U16 AttachedDevHandle; /* 0x08 */
1672 U16 ControllerDevHandle; /* 0x0A */
1673 U32 DiscoveryStatus; /* 0x0C */
1674 U32 Reserved; /* 0x10 */
1802 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1803 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1804 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1805
1806 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1807 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1808 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1809
1810 /* values for SAS IO Unit Page 1 PortFlags */
1811 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1812
1813 /* values for SAS IO Unit Page 1 PhyFlags */
1814 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1815 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1816
1817 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1818 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1819 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1820 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1821 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1822 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1823 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1824 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1825 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1826
1827 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1828
1829
1830 /* SAS IO Unit Page 4 */
1831
1832 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1833 {
1834 U8 MaxTargetSpinup; /* 0x00 */
1835 U8 SpinupDelay; /* 0x01 */
1836 U16 Reserved1; /* 0x02 */
1837 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1838 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1839
1840 /*
1841 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1842 * four and check Header.ExtPageLength or NumPhys at runtime.
1843 */
1844 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1845 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1861 U8 Flags; /* 0x2B */
1862 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1863 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1864 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1865 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1866
1867 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1868
1869 /* defines for Flags field */
1870 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1871
1872 /* defines for PHY field */
1873 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1874
1875
1876 /* SAS IO Unit Page 5 */
1877
1878 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
1879 {
1880 U8 ControlFlags; /* 0x00 */
1881 U8 Reserved1; /* 0x01 */
1882 U16 InactivityTimerExponent; /* 0x02 */
1883 U8 SATAPartialTimeout; /* 0x04 */
1884 U8 Reserved2; /* 0x05 */
1885 U8 SATASlumberTimeout; /* 0x06 */
1886 U8 Reserved3; /* 0x07 */
1887 U8 SASPartialTimeout; /* 0x08 */
1888 U8 Reserved4; /* 0x09 */
1889 U8 SASSlumberTimeout; /* 0x0A */
1890 U8 Reserved5; /* 0x0B */
1891 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1892 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1893 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1894
1895 /* defines for ControlFlags field */
1896 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1897 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1898 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1899 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1900
1901 /* defines for InactivityTimerExponent field */
1902 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
1903 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
1904 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
1905 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
1906 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
1907 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
1908 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
1909 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
1910
1911 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
1912 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
1913 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
1914 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
1915 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
1916 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
1917 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
1918 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
1919
1920 /*
1921 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1922 * one and check Header.ExtPageLength or NumPhys at runtime.
1923 */
1924 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
1925 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
1926 #endif
1927
1928 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
1929 {
1930 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1931 U8 NumPhys; /* 0x08 */
1932 U8 Reserved1; /* 0x09 */
1933 U16 Reserved2; /* 0x0A */
1934 U32 Reserved3; /* 0x0C */
1935 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
1936 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
1937 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
1938 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
1939
1940 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x00)
1941
1942
1943
1944
1945 /****************************************************************************
1946 * SAS Expander Config Pages
1947 ****************************************************************************/
1948
1949 /* SAS Expander Page 0 */
1950
1951 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
1952 {
1953 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1954 U8 PhysicalPort; /* 0x08 */
1955 U8 ReportGenLength; /* 0x09 */
1956 U16 EnclosureHandle; /* 0x0A */
1957 U64 SASAddress; /* 0x0C */
1958 U32 DiscoveryStatus; /* 0x14 */
1959 U16 DevHandle; /* 0x18 */
1960 U16 ParentDevHandle; /* 0x1A */
2107 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2108 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2109 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2110 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2111 /* specific values for SATA Init failures */
2112 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2113 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2114 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2115 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2116 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2117 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2118 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2119 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2120 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2121 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2122 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2123
2124 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2125
2126 /* values for SAS Device Page 0 Flags field */
2127 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2128 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2129 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2130 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2131 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2132 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2133 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2134 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2135 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2136 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2137 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2138
2139
2140 /* SAS Device Page 1 */
2141
2142 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2143 {
2144 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2145 U32 Reserved1; /* 0x08 */
2146 U64 SASAddress; /* 0x0C */
2324 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2325 */
2326 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2327 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2328 #endif
2329
2330 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
2331 {
2332 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2333 U32 Reserved1; /* 0x08 */
2334 U8 NumPhyEvents; /* 0x0C */
2335 U8 Reserved2; /* 0x0D */
2336 U16 Reserved3; /* 0x0E */
2337 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2338 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2339 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2340
2341 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2342
2343
2344 /****************************************************************************
2345 * SAS Port Config Pages
2346 ****************************************************************************/
2347
2348 /* SAS Port Page 0 */
2349
2350 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2351 {
2352 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2353 U8 PortNumber; /* 0x08 */
2354 U8 PhysicalPort; /* 0x09 */
2355 U8 PortWidth; /* 0x0A */
2356 U8 PhysicalPortWidth; /* 0x0B */
2357 U8 ZoneGroup; /* 0x0C */
2358 U8 Reserved1; /* 0x0D */
2359 U16 Reserved2; /* 0x0E */
2360 U64 SASAddress; /* 0x10 */
2361 U32 DeviceInfo; /* 0x18 */
2362 U32 Reserved3; /* 0x1C */
2363 U32 Reserved4; /* 0x20 */
2645 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2646 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2647 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2648 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2649 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2650 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2651 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2652
2653 /* values for Ethernet Page 1 MediaState field */
2654 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2655 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2656 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2657
2658 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2659 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2660 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2661 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2662 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2663
2664
2665 #endif
2666
|
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2000-2012 LSI Corporation.
24 *
25 * Redistribution and use in source and binary forms of all code within
26 * this file that is exclusively owned by LSI, with or without
27 * modification, is permitted provided that, in addition to the CDDL 1.0
28 * License requirements, the following conditions are met:
29 *
30 * Neither the name of the author nor the names of its contributors may be
31 * used to endorse or promote products derived from this software without
32 * specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
37 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
38 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
40 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
41 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
42 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
44 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
45 * DAMAGE.
46 */
47
48 /*
49 * Name: mpi2_cnfg.h
50 * Title: MPI Configuration messages and pages
51 * Creation Date: November 10, 2006
52 *
53 * mpi2_cnfg.h Version: 02.00.xx
54 *
55 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
56 * prefix are for use only on MPI v2.5 products, and must not be used
57 * with MPI v2.0 products. Unless otherwise noted, names beginning with
58 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
59 *
60 * Version History
61 * ---------------
62 *
63 * Date Version Description
64 * -------- -------- ------------------------------------------------------
65 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
66 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
67 * Added Manufacturing Page 11.
68 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
69 * define.
70 * 06-26-07 02.00.02 Adding generic structure for product-specific
71 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
72 * Rework of BIOS Page 2 configuration page.
73 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
74 * forms.
75 * Added configuration pages IOC Page 8 and Driver
76 * Persistent Mapping Page 0.
77 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
78 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
139 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
140 * and SAS Expander Page 0 to flag a downstream initiator
141 * when in simplified routing mode.
142 * Removed SATA Init Failure defines for DiscoveryStatus
143 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
144 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
145 * Added PortGroups, DmaGroup, and ControlGroup fields to
146 * SAS Device Page 0.
147 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
148 * Unit Page 6.
149 * Added expander reduced functionality data to SAS
150 * Expander Page 0.
151 * Added SAS PHY Page 2 and SAS PHY Page 3.
152 * 07-30-09 02.00.12 Added IO Unit Page 7.
153 * Added new device ids.
154 * Added SAS IO Unit Page 5.
155 * Added partial and slumber power management capable flags
156 * to SAS Device Page 0 Flags field.
157 * Added PhyInfo defines for power condition.
158 * Added Ethernet configuration pages.
159 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
160 * Added SAS PHY Page 4 structure and defines.
161 * 02-10-10 02.00.14 Modified the comments for the configuration page
162 * structures that contain an array of data. The host
163 * should use the "count" field in the page data (e.g. the
164 * NumPhys field) to determine the number of valid elements
165 * in the array.
166 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
167 * Added PowerManagementCapabilities to IO Unit Page 7.
168 * Added PortWidthModGroup field to
169 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
170 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
171 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
172 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
173 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
174 * define.
175 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
176 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
177 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
178 * defines.
179 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
180 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
181 * the Pinout field.
182 * Added BoardTemperature and BoardTemperatureUnits fields
183 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
184 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
185 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
186 * --------------------------------------------------------------------------
187 */
188
189 #ifndef MPI2_CNFG_H
190 #define MPI2_CNFG_H
191
192 /*****************************************************************************
193 * Configuration Page Header and defines
194 *****************************************************************************/
195
196 /* Config Page Header */
197 typedef struct _MPI2_CONFIG_PAGE_HEADER
198 {
199 U8 PageVersion; /* 0x00 */
200 U8 PageLength; /* 0x01 */
201 U8 PageNumber; /* 0x02 */
202 U8 PageType; /* 0x03 */
203 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
204 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
205
249 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
250 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
251 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
252 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
253 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
254
255 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
256
257
258 /* ExtPageType field values */
259 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
260 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
261 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
262 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
263 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
264 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
265 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
266 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
267 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
268 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
269 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
270
271
272 /*****************************************************************************
273 * PageAddress defines
274 *****************************************************************************/
275
276 /* RAID Volume PageAddress format */
277 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
278 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
279 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
280
281 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
282
283
284 /* RAID Physical Disk PageAddress format */
285 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
286 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
287 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
288 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
289
416 U16 IOCStatus; /* 0x0E */
417 U32 IOCLogInfo; /* 0x10 */
418 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
419 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
420 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
421
422
423
424 /*****************************************************************************
425 *
426 * C o n f i g u r a t i o n P a g e s
427 *
428 *****************************************************************************/
429
430 /****************************************************************************
431 * Manufacturing Config pages
432 ****************************************************************************/
433
434 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
435
436 /* MPI v2.0 SAS products */
437 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
438 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
439 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
440 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
441 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
442 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
443 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
444
445 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
446
447 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
448 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
449 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
450 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
451 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
452 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
453 #define MPI2_MFGPAGE_DEVID_SAS2208_7 (0x0086)
454 #define MPI2_MFGPAGE_DEVID_SAS2208_8 (0x0087)
455 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
456 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
457 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
458
459 /* MPI v2.5 SAS products */
460 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
461 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
462 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
463 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
464 #define MPI25_MFGPAGE_DEVID_SAS3108_3 (0x0092)
465 #define MPI25_MFGPAGE_DEVID_SAS3108_4 (0x0093)
466 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
467 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
468
469 /* Manufacturing Page 0 */
470
471 typedef struct _MPI2_CONFIG_PAGE_MAN_0
472 {
473 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
474 U8 ChipName[16]; /* 0x04 */
475 U8 ChipRevision[8]; /* 0x14 */
476 U8 BoardName[16]; /* 0x1C */
477 U8 BoardAssembly[16]; /* 0x2C */
478 U8 BoardTracerNumber[16]; /* 0x3C */
479 } MPI2_CONFIG_PAGE_MAN_0,
480 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
481 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
482
483 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
484
485
486 /* Manufacturing Page 1 */
487
661 /* Manufacturing Page 6 */
662
663 typedef struct _MPI2_CONFIG_PAGE_MAN_6
664 {
665 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
666 U32 ProductSpecificInfo;/* 0x04 */
667 } MPI2_CONFIG_PAGE_MAN_6,
668 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
669 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
670
671 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
672
673
674 /* Manufacturing Page 7 */
675
676 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
677 {
678 U32 Pinout; /* 0x00 */
679 U8 Connector[16]; /* 0x04 */
680 U8 Location; /* 0x14 */
681 U8 ReceptacleID; /* 0x15 */
682 U16 Slot; /* 0x16 */
683 U32 Reserved2; /* 0x18 */
684 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
685 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
686
687 /* defines for the Pinout field */
688 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
689 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
690 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
691 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
692 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
693 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
694 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
695 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
696 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
697 #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
698
699 /* defines for the Location field */
700 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
701 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
711 */
712 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
713 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
714 #endif
715
716 typedef struct _MPI2_CONFIG_PAGE_MAN_7
717 {
718 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
719 U32 Reserved1; /* 0x04 */
720 U32 Reserved2; /* 0x08 */
721 U32 Flags; /* 0x0C */
722 U8 EnclosureName[16]; /* 0x10 */
723 U8 NumPhys; /* 0x20 */
724 U8 Reserved3; /* 0x21 */
725 U16 Reserved4; /* 0x22 */
726 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
727 } MPI2_CONFIG_PAGE_MAN_7,
728 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
729 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
730
731 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
732
733 /* defines for the Flags field */
734 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
735
736
737 /*
738 * Generic structure to use for product-specific manufacturing pages
739 * (currently Manufacturing Page 8 through Manufacturing Page 31).
740 */
741
742 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
743 {
744 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
745 U32 ProductSpecificInfo;/* 0x04 */
746 } MPI2_CONFIG_PAGE_MAN_PS,
747 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
748 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
749
750 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
751 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
786 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
787 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
788 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
789 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
790
791 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
792
793
794 /* IO Unit Page 1 */
795
796 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
797 {
798 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
799 U32 Flags; /* 0x04 */
800 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
801 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
802
803 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
804
805 /* IO Unit Page 1 Flags defines */
806 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
807 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
808 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
809 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
810 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
811 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
812 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
813 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
814 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
815 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
816 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
817 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
818 #define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
819 #define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
820
821
822 /* IO Unit Page 3 */
823
824 /*
825 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
826 * one and check Header.PageLength at runtime.
827 */
828 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
829 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
830 #endif
900 U32 Reserved2; /* 0x14 */
901 U32 Reserved3; /* 0x18 */
902 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
903 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
904
905 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
906
907 /* defines for IO Unit Page 6 Flags field */
908 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
909
910
911 /* IO Unit Page 7 */
912
913 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
914 {
915 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
916 U16 Reserved1; /* 0x04 */
917 U8 PCIeWidth; /* 0x06 */
918 U8 PCIeSpeed; /* 0x07 */
919 U32 ProcessorState; /* 0x08 */
920 U32 PowerManagementCapabilities; /* 0x0C */
921 U16 IOCTemperature; /* 0x10 */
922 U8 IOCTemperatureUnits; /* 0x12 */
923 U8 IOCSpeed; /* 0x13 */
924 U16 BoardTemperature; /* 0x14 */
925 U8 BoardTemperatureUnits; /* 0x16 */
926 U8 Reserved3; /* 0x17 */
927 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
928 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
929
930 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
931
932 /* defines for IO Unit Page 7 PCIeWidth field */
933 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
934 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
935 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
936 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
937
938 /* defines for IO Unit Page 7 PCIeSpeed field */
939 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
940 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
941 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
942
943 /* defines for IO Unit Page 7 ProcessorState field */
944 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
945 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
946
947 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
948 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
949 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
950
951 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
952 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
953 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
954 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
955 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008)
956 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004)
957
958 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
959 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
960 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
961 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
962
963 /* defines for IO Unit Page 7 IOCSpeed field */
964 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
965 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
966 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
967 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
968
969 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
970 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
971 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
972 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
973
974
975 /****************************************************************************
976 * IOC Config Pages
977 ****************************************************************************/
978
979 /* IOC Page 0 */
980
981 typedef struct _MPI2_CONFIG_PAGE_IOC_0
982 {
983 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
984 U32 Reserved1; /* 0x04 */
985 U32 Reserved2; /* 0x08 */
986 U16 VendorID; /* 0x0C */
987 U16 DeviceID; /* 0x0E */
988 U8 RevisionID; /* 0x10 */
989 U8 Reserved3; /* 0x11 */
990 U16 Reserved4; /* 0x12 */
991 U32 ClassCode; /* 0x14 */
992 U16 SubsystemVendorID; /* 0x18 */
1416 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1417
1418 /* values for RAID VolumeType */
1419 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1420 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1421 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1422 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1423 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1424
1425 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1426 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1427 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1428 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1429 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1430 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1431 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1432 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1433 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1434 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1435 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1436 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1437 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1438 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1439 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1440 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1441 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1442 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1443 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1444 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1445
1446 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1447 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1448 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1449 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1450 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1451
1452 /* values for RAID Volume Page 0 InactiveStatus field */
1453 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1454 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1455 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1456 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1539 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1540 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1541 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1542
1543 /* OfflineReason defines */
1544 #define MPI2_PHYSDISK0_ONLINE (0x00)
1545 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1546 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1547 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1548 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1549 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1550 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1551
1552 /* IncompatibleReason defines */
1553 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1554 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1555 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1556 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1557 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1558 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1559 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1560 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1561
1562 /* PhysDiskAttributes defines */
1563 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1564 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1565
1566 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1567 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1568 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1569
1570 /* PhysDiskStatusFlags defines */
1571 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1572 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1573 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1574 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1575 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1576 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1577 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1578 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1579
1580
1581 /* RAID Physical Disk Page 1 */
1582
1583 /*
1584 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1585 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1586 */
1618 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1619
1620 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1621
1622
1623 /****************************************************************************
1624 * values for fields used by several types of SAS Config Pages
1625 ****************************************************************************/
1626
1627 /* values for NegotiatedLinkRates fields */
1628 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1629 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1630 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1631 /* link rates used for Negotiated Physical and Logical Link Rate */
1632 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1633 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1634 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1635 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1636 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1637 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1638 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1639 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1640 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1641 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1642 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
1643
1644
1645 /* values for AttachedPhyInfo fields */
1646 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1647 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1648 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1649
1650 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1651 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1652 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1653 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1654 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1655 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1656 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1657 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1658 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1659 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1660
1661
1662 /* values for PhyInfo fields */
1663 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1664
1665 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1666 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1667 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1668 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1669 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1670
1671 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1672 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1673 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1674 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1675 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1676 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1677
1678 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1679 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1680 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1681 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1682 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1683 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1684 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1685 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1686 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1694 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1695 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1696
1697 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1698 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1699 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1700 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1701
1702
1703 /* values for SAS ProgrammedLinkRate fields */
1704 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1705 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1706 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1707 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1708 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1709 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1710 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1711 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1712 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1713 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1714 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
1715
1716
1717 /* values for SAS HwLinkRate fields */
1718 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1719 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1720 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1721 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1722 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1723 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1724 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1725 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1726 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
1727
1728
1729
1730 /****************************************************************************
1731 * SAS IO Unit Config Pages
1732 ****************************************************************************/
1733
1734 /* SAS IO Unit Page 0 */
1735
1736 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1737 {
1738 U8 Port; /* 0x00 */
1739 U8 PortFlags; /* 0x01 */
1740 U8 PhyFlags; /* 0x02 */
1741 U8 NegotiatedLinkRate; /* 0x03 */
1742 U32 ControllerPhyDeviceInfo;/* 0x04 */
1743 U16 AttachedDevHandle; /* 0x08 */
1744 U16 ControllerDevHandle; /* 0x0A */
1745 U32 DiscoveryStatus; /* 0x0C */
1746 U32 Reserved; /* 0x10 */
1874 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1875 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1876 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1877
1878 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1879 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1880 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1881
1882 /* values for SAS IO Unit Page 1 PortFlags */
1883 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1884
1885 /* values for SAS IO Unit Page 1 PhyFlags */
1886 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1887 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1888
1889 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1890 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1891 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1892 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1893 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1894 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
1895 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1896 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1897 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1898 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1899 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
1900
1901 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1902
1903
1904 /* SAS IO Unit Page 4 */
1905
1906 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1907 {
1908 U8 MaxTargetSpinup; /* 0x00 */
1909 U8 SpinupDelay; /* 0x01 */
1910 U16 Reserved1; /* 0x02 */
1911 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1912 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1913
1914 /*
1915 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1916 * four and check Header.ExtPageLength or NumPhys at runtime.
1917 */
1918 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1919 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1935 U8 Flags; /* 0x2B */
1936 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1937 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1938 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1939 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1940
1941 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1942
1943 /* defines for Flags field */
1944 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1945
1946 /* defines for PHY field */
1947 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1948
1949
1950 /* SAS IO Unit Page 5 */
1951
1952 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
1953 {
1954 U8 ControlFlags; /* 0x00 */
1955 U8 PortWidthModGroup; /* 0x01 */
1956 U16 InactivityTimerExponent; /* 0x02 */
1957 U8 SATAPartialTimeout; /* 0x04 */
1958 U8 Reserved2; /* 0x05 */
1959 U8 SATASlumberTimeout; /* 0x06 */
1960 U8 Reserved3; /* 0x07 */
1961 U8 SASPartialTimeout; /* 0x08 */
1962 U8 Reserved4; /* 0x09 */
1963 U8 SASSlumberTimeout; /* 0x0A */
1964 U8 Reserved5; /* 0x0B */
1965 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1966 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1967 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1968
1969 /* defines for ControlFlags field */
1970 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1971 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1972 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1973 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1974
1975 /* defines for PortWidthModeGroup field */
1976 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
1977
1978 /* defines for InactivityTimerExponent field */
1979 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
1980 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
1981 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
1982 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
1983 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
1984 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
1985 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
1986 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
1987
1988 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
1989 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
1990 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
1991 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
1992 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
1993 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
1994 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
1995 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
1996
1997 /*
1998 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1999 * one and check Header.ExtPageLength or NumPhys at runtime.
2000 */
2001 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2002 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2003 #endif
2004
2005 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
2006 {
2007 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2008 U8 NumPhys; /* 0x08 */
2009 U8 Reserved1; /* 0x09 */
2010 U16 Reserved2; /* 0x0A */
2011 U32 Reserved3; /* 0x0C */
2012 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2013 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2014 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2015 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2016
2017 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2018
2019
2020 /* SAS IO Unit Page 6 */
2021
2022 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2023 {
2024 U8 CurrentStatus; /* 0x00 */
2025 U8 CurrentModulation; /* 0x01 */
2026 U8 CurrentUtilization; /* 0x02 */
2027 U8 Reserved1; /* 0x03 */
2028 U32 Reserved2; /* 0x04 */
2029 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2030 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2031 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2032 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2033
2034 /* defines for CurrentStatus field */
2035 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2036 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2037 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2038 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2039 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2040 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2041 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2042 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2043
2044 /* defines for CurrentModulation field */
2045 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2046 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2047 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2048 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2049
2050 /*
2051 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2052 * one and check the value returned for NumGroups at runtime.
2053 */
2054 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2055 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2056 #endif
2057
2058 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6
2059 {
2060 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2061 U32 Reserved1; /* 0x08 */
2062 U32 Reserved2; /* 0x0C */
2063 U8 NumGroups; /* 0x10 */
2064 U8 Reserved3; /* 0x11 */
2065 U16 Reserved4; /* 0x12 */
2066 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2067 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2068 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2069 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2070 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2071
2072 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2073
2074
2075 /* SAS IO Unit Page 7 */
2076
2077 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2078 {
2079 U8 Flags; /* 0x00 */
2080 U8 Reserved1; /* 0x01 */
2081 U16 Reserved2; /* 0x02 */
2082 U8 Threshold75Pct; /* 0x04 */
2083 U8 Threshold50Pct; /* 0x05 */
2084 U8 Threshold25Pct; /* 0x06 */
2085 U8 Reserved3; /* 0x07 */
2086 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2087 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2088 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2089 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2090
2091 /* defines for Flags field */
2092 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2093
2094
2095 /*
2096 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2097 * one and check the value returned for NumGroups at runtime.
2098 */
2099 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2100 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2101 #endif
2102
2103 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7
2104 {
2105 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2106 U8 SamplingInterval; /* 0x08 */
2107 U8 WindowLength; /* 0x09 */
2108 U16 Reserved1; /* 0x0A */
2109 U32 Reserved2; /* 0x0C */
2110 U32 Reserved3; /* 0x10 */
2111 U8 NumGroups; /* 0x14 */
2112 U8 Reserved4; /* 0x15 */
2113 U16 Reserved5; /* 0x16 */
2114 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2115 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2116 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2117 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2118 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2119
2120 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2121
2122
2123 /* SAS IO Unit Page 8 */
2124
2125 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8
2126 {
2127 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2128 U32 Reserved1; /* 0x08 */
2129 U32 PowerManagementCapabilities; /* 0x0C */
2130 U32 Reserved2; /* 0x10 */
2131 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2132 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2133 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2134
2135 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2136
2137 /* defines for PowerManagementCapabilities field */
2138 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000)
2139 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800)
2140 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400)
2141 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200)
2142 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100)
2143 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010)
2144 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008)
2145 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004)
2146 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002)
2147 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001)
2148
2149
2150
2151
2152 /****************************************************************************
2153 * SAS Expander Config Pages
2154 ****************************************************************************/
2155
2156 /* SAS Expander Page 0 */
2157
2158 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2159 {
2160 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2161 U8 PhysicalPort; /* 0x08 */
2162 U8 ReportGenLength; /* 0x09 */
2163 U16 EnclosureHandle; /* 0x0A */
2164 U64 SASAddress; /* 0x0C */
2165 U32 DiscoveryStatus; /* 0x14 */
2166 U16 DevHandle; /* 0x18 */
2167 U16 ParentDevHandle; /* 0x1A */
2314 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2315 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2316 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2317 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2318 /* specific values for SATA Init failures */
2319 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2320 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2321 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2322 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2323 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2324 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2325 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2326 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2327 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2328 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2329 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2330
2331 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2332
2333 /* values for SAS Device Page 0 Flags field */
2334 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2335 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2336 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2337 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2338 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2339 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2340 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2341 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2342 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2343 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2344 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2345 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2346 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2347
2348
2349 /* SAS Device Page 1 */
2350
2351 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2352 {
2353 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2354 U32 Reserved1; /* 0x08 */
2355 U64 SASAddress; /* 0x0C */
2533 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2534 */
2535 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2536 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2537 #endif
2538
2539 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
2540 {
2541 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2542 U32 Reserved1; /* 0x08 */
2543 U8 NumPhyEvents; /* 0x0C */
2544 U8 Reserved2; /* 0x0D */
2545 U16 Reserved3; /* 0x0E */
2546 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2547 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2548 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2549
2550 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2551
2552
2553 /* SAS PHY Page 4 */
2554
2555 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4
2556 {
2557 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2558 U16 Reserved1; /* 0x08 */
2559 U8 Reserved2; /* 0x0A */
2560 U8 Flags; /* 0x0B */
2561 U8 InitialFrame[28]; /* 0x0C */
2562 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2563 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2564
2565 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2566
2567 /* values for the Flags field */
2568 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2569 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2570
2571
2572
2573
2574 /****************************************************************************
2575 * SAS Port Config Pages
2576 ****************************************************************************/
2577
2578 /* SAS Port Page 0 */
2579
2580 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2581 {
2582 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2583 U8 PortNumber; /* 0x08 */
2584 U8 PhysicalPort; /* 0x09 */
2585 U8 PortWidth; /* 0x0A */
2586 U8 PhysicalPortWidth; /* 0x0B */
2587 U8 ZoneGroup; /* 0x0C */
2588 U8 Reserved1; /* 0x0D */
2589 U16 Reserved2; /* 0x0E */
2590 U64 SASAddress; /* 0x10 */
2591 U32 DeviceInfo; /* 0x18 */
2592 U32 Reserved3; /* 0x1C */
2593 U32 Reserved4; /* 0x20 */
2875 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2876 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2877 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2878 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2879 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2880 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2881 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2882
2883 /* values for Ethernet Page 1 MediaState field */
2884 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2885 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2886 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2887
2888 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2889 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2890 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2891 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2892 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2893
2894
2895 /****************************************************************************
2896 * Extended Manufacturing Config Pages
2897 ****************************************************************************/
2898
2899 /*
2900 * Generic structure to use for product-specific extended manufacturing pages
2901 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
2902 * Page 60).
2903 */
2904
2905 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS
2906 {
2907 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2908 U32 ProductSpecificInfo; /* 0x08 */
2909 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
2910 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
2911 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
2912
2913 /* PageVersion should be provided by product-specific code */
2914
2915 #endif
2916
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