1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright (c) 2000 to 2009, LSI Corporation.
  24  * All rights reserved.
  25  *
  26  * Redistribution and use in source and binary forms of all code within
  27  * this file that is exclusively owned by LSI, with or without
  28  * modification, is permitted provided that, in addition to the CDDL 1.0
  29  * License requirements, the following conditions are met:
  30  *
  31  *    Neither the name of the author nor the names of its contributors may be
  32  *    used to endorse or promote products derived from this software without
  33  *    specific prior written permission.
  34  *
  35  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  36  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  37  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  38  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  39  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  40  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  41  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  42  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  43  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  44  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  45  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  46  * DAMAGE.
  47  */
  48 
  49 /*
  50  *           Name:  mpi2_cnfg.h
  51  *          Title:  MPI Configuration messages and pages
  52  *  Creation Date:  November 10, 2006
  53  *
  54  *    mpi2_cnfg.h Version:  02.00.12
  55  *
  56  *  Version History
  57  *  ---------------
  58  *
  59  *  Date      Version   Description
  60  *  --------  --------  ------------------------------------------------------
  61  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  62  *  06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
  63  *                      Added Manufacturing Page 11.
  64  *                      Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
  65  *                      define.
  66  *  06-26-07  02.00.02  Adding generic structure for product-specific
  67  *                      Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
  68  *                      Rework of BIOS Page 2 configuration page.
  69  *                      Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
  70  *                      forms.
  71  *                      Added configuration pages IOC Page 8 and Driver
  72  *                      Persistent Mapping Page 0.
  73  *  08-31-07  02.00.03  Modified configuration pages dealing with Integrated
  74  *                      RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
  75  *                      RAID Physical Disk Pages 0 and 1, RAID Configuration
  76  *                      Page 0).
  77  *                      Added new value for AccessStatus field of SAS Device
  78  *                      Page 0 (_SATA_NEEDS_INITIALIZATION).
  79  *  10-31-07  02.00.04  Added missing SEPDevHandle field to
  80  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
  81  *  12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
  82  *                      NVDATA.
  83  *                      Modified IOC Page 7 to use masks and added field for
  84  *                      SASBroadcastPrimitiveMasks.
  85  *                      Added MPI2_CONFIG_PAGE_BIOS_4.
  86  *                      Added MPI2_CONFIG_PAGE_LOG_0.
  87  *  02-29-08  02.00.06  Modified various names to make them 32-character unique.
  88  *                      Added SAS Device IDs.
  89  *                      Updated Integrated RAID configuration pages including
  90  *                      Manufacturing Page 4, IOC Page 6, and RAID Configuration
  91  *                      Page 0.
  92  *  05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
  93  *                      Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
  94  *                      Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
  95  *                      Added missing MaxNumRoutedSasAddresses field to
  96  *                      MPI2_CONFIG_PAGE_EXPANDER_0.
  97  *                      Added SAS Port Page 0.
  98  *                      Modified structure layout for
  99  *                      MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
 100  *  06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
 101  *                      MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
 102  *  10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
 103  *                      to 0x000000FF.
 104  *                      Added two new values for the Physical Disk Coercion Size
 105  *                      bits in the Flags field of Manufacturing Page 4.
 106  *                      Added product-specific Manufacturing pages 16 to 31.
 107  *                      Modified Flags bits for controlling write cache on SATA
 108  *                      drives in IO Unit Page 1.
 109  *                      Added new bit to AdditionalControlFlags of SAS IO Unit
 110  *                      Page 1 to control Invalid Topology Correction.
 111  *                      Added additional defines for RAID Volume Page 0
 112  *                      VolumeStatusFlags field.
 113  *                      Modified meaning of RAID Volume Page 0 VolumeSettings
 114  *                      define for auto-configure of hot-swap drives.
 115  *                      Added SupportedPhysDisks field to RAID Volume Page 1 and
 116  *                      added related defines.
 117  *                      Added PhysDiskAttributes field (and related defines) to
 118  *                      RAID Physical Disk Page 0.
 119  *                      Added MPI2_SAS_PHYINFO_PHY_VACANT define.
 120  *                      Added three new DiscoveryStatus bits for SAS IO Unit
 121  *                      Page 0 and SAS Expander Page 0.
 122  *                      Removed multiplexing information from SAS IO Unit pages.
 123  *                      Added BootDeviceWaitTime field to SAS IO Unit Page 4.
 124  *                      Removed Zone Address Resolved bit from PhyInfo and from
 125  *                      Expander Page 0 Flags field.
 126  *                      Added two new AccessStatus values to SAS Device Page 0
 127  *                      for indicating routing problems. Added 3 reserved words
 128  *                      to this page.
 129  *  01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
 130  *                      Inserted missing reserved field into structure for IOC
 131  *                      Page 6.
 132  *                      Added more pending task bits to RAID Volume Page 0
 133  *                      VolumeStatusFlags defines.
 134  *                      Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
 135  *                      Added a new DiscoveryStatus bit for SAS IO Unit Page 0
 136  *                      and SAS Expander Page 0 to flag a downstream initiator
 137  *                      when in simplified routing mode.
 138  *                      Removed SATA Init Failure defines for DiscoveryStatus
 139  *                      fields of SAS IO Unit Page 0 and SAS Expander Page 0.
 140  *                      Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
 141  *                      Added PortGroups, DmaGroup, and ControlGroup fields to
 142  *                      SAS Device Page 0.
 143  *  05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
 144  *                      Unit Page 6.
 145  *                      Added expander reduced functionality data to SAS
 146  *                      Expander Page 0.
 147  *                      Added SAS PHY Page 2 and SAS PHY Page 3.
 148  *  07-30-09  02.00.12  Added IO Unit Page 7.
 149  *                      Added new device ids.
 150  *                      Added SAS IO Unit Page 5.
 151  *                      Added partial and slumber power management capable flags
 152  *                      to SAS Device Page 0 Flags field.
 153  *                      Added PhyInfo defines for power condition.
 154  *                      Added Ethernet configuration pages.
 155  *  --------------------------------------------------------------------------
 156  */
 157 
 158 #ifndef MPI2_CNFG_H
 159 #define MPI2_CNFG_H
 160 
 161 /*****************************************************************************
 162 *   Configuration Page Header and defines
 163 *****************************************************************************/
 164 
 165 /* Config Page Header */
 166 typedef struct _MPI2_CONFIG_PAGE_HEADER
 167 {
 168     U8                 PageVersion;                /* 0x00 */
 169     U8                 PageLength;                 /* 0x01 */
 170     U8                 PageNumber;                 /* 0x02 */
 171     U8                 PageType;                   /* 0x03 */
 172 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
 173   Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
 174 
 175 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
 176 {
 177    MPI2_CONFIG_PAGE_HEADER  Struct;
 178    U8                       Bytes[4];
 179    U16                      Word16[2];
 180    U32                      Word32;
 181 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
 182   Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
 183 
 184 /* Extended Config Page Header */
 185 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
 186 {
 187     U8                  PageVersion;                /* 0x00 */
 188     U8                  Reserved1;                  /* 0x01 */
 189     U8                  PageNumber;                 /* 0x02 */
 190     U8                  PageType;                   /* 0x03 */
 191     U16                 ExtPageLength;              /* 0x04 */
 192     U8                  ExtPageType;                /* 0x06 */
 193     U8                  Reserved2;                  /* 0x07 */
 194 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
 195   MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
 196   Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
 197 
 198 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
 199 {
 200    MPI2_CONFIG_PAGE_HEADER          Struct;
 201    MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
 202    U8                               Bytes[8];
 203    U16                              Word16[4];
 204    U32                              Word32[2];
 205 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
 206   Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
 207 
 208 
 209 /* PageType field values */
 210 #define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
 211 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
 212 #define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
 213 #define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
 214 
 215 #define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
 216 #define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
 217 #define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
 218 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
 219 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
 220 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
 221 #define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
 222 #define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
 223 
 224 #define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
 225 
 226 
 227 /* ExtPageType field values */
 228 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
 229 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
 230 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
 231 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
 232 #define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
 233 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
 234 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
 235 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
 236 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
 237 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
 238 
 239 
 240 /*****************************************************************************
 241 *   PageAddress defines
 242 *****************************************************************************/
 243 
 244 /* RAID Volume PageAddress format */
 245 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
 246 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
 247 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
 248 
 249 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
 250 
 251 
 252 /* RAID Physical Disk PageAddress format */
 253 #define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
 254 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
 255 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
 256 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
 257 
 258 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
 259 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
 260 
 261 
 262 /* SAS Expander PageAddress format */
 263 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
 264 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
 265 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
 266 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
 267 
 268 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
 269 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
 270 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
 271 
 272 
 273 /* SAS Device PageAddress format */
 274 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
 275 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
 276 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
 277 
 278 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
 279 
 280 
 281 /* SAS PHY PageAddress format */
 282 #define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
 283 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
 284 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
 285 
 286 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
 287 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
 288 
 289 
 290 /* SAS Port PageAddress format */
 291 #define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
 292 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
 293 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
 294 
 295 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
 296 
 297 
 298 /* SAS Enclosure PageAddress format */
 299 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
 300 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
 301 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
 302 
 303 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
 304 
 305 
 306 /* RAID Configuration PageAddress format */
 307 #define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
 308 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
 309 #define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
 310 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
 311 
 312 #define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
 313 
 314 
 315 /* Driver Persistent Mapping PageAddress format */
 316 #define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
 317 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
 318 
 319 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
 320 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
 321 #define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
 322 
 323 
 324 /* Ethernet PageAddress format */
 325 #define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
 326 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
 327 
 328 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
 329 
 330 
 331 
 332 /****************************************************************************
 333 *   Configuration messages
 334 ****************************************************************************/
 335 
 336 /* Configuration Request Message */
 337 typedef struct _MPI2_CONFIG_REQUEST
 338 {
 339     U8                      Action;                     /* 0x00 */
 340     U8                      SGLFlags;                   /* 0x01 */
 341     U8                      ChainOffset;                /* 0x02 */
 342     U8                      Function;                   /* 0x03 */
 343     U16                     ExtPageLength;              /* 0x04 */
 344     U8                      ExtPageType;                /* 0x06 */
 345     U8                      MsgFlags;                   /* 0x07 */
 346     U8                      VP_ID;                      /* 0x08 */
 347     U8                      VF_ID;                      /* 0x09 */
 348     U16                     Reserved1;                  /* 0x0A */
 349     U32                     Reserved2;                  /* 0x0C */
 350     U32                     Reserved3;                  /* 0x10 */
 351     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
 352     U32                     PageAddress;                /* 0x18 */
 353     MPI2_SGE_IO_UNION       PageBufferSGE;              /* 0x1C */
 354 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
 355   Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
 356 
 357 /* values for the Action field */
 358 #define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
 359 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
 360 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
 361 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
 362 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
 363 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
 364 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
 365 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
 366 
 367 /* values for SGLFlags field are in the SGL section of mpi2.h */
 368 
 369 
 370 /* Config Reply Message */
 371 typedef struct _MPI2_CONFIG_REPLY
 372 {
 373     U8                      Action;                     /* 0x00 */
 374     U8                      SGLFlags;                   /* 0x01 */
 375     U8                      MsgLength;                  /* 0x02 */
 376     U8                      Function;                   /* 0x03 */
 377     U16                     ExtPageLength;              /* 0x04 */
 378     U8                      ExtPageType;                /* 0x06 */
 379     U8                      MsgFlags;                   /* 0x07 */
 380     U8                      VP_ID;                      /* 0x08 */
 381     U8                      VF_ID;                      /* 0x09 */
 382     U16                     Reserved1;                  /* 0x0A */
 383     U16                     Reserved2;                  /* 0x0C */
 384     U16                     IOCStatus;                  /* 0x0E */
 385     U32                     IOCLogInfo;                 /* 0x10 */
 386     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
 387 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
 388   Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
 389 
 390 
 391 
 392 /*****************************************************************************
 393 *
 394 *               C o n f i g u r a t i o n    P a g e s
 395 *
 396 *****************************************************************************/
 397 
 398 /****************************************************************************
 399 *   Manufacturing Config pages
 400 ****************************************************************************/
 401 
 402 #define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
 403 
 404 /* SAS */
 405 #define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
 406 #define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
 407 #define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
 408 #define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
 409 #define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
 410 #define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
 411 #define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
 412 
 413 #define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
 414 #define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
 415 #define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
 416 #define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
 417 #define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
 418 #define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
 419 #define MPI2_MFGPAGE_DEVID_SAS2208_7                (0x0086)
 420 #define MPI2_MFGPAGE_DEVID_SAS2208_8                (0x0087)
 421 
 422 
 423 /* Manufacturing Page 0 */
 424 
 425 typedef struct _MPI2_CONFIG_PAGE_MAN_0
 426 {
 427     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 428     U8                      ChipName[16];               /* 0x04 */
 429     U8                      ChipRevision[8];            /* 0x14 */
 430     U8                      BoardName[16];              /* 0x1C */
 431     U8                      BoardAssembly[16];          /* 0x2C */
 432     U8                      BoardTracerNumber[16];      /* 0x3C */
 433 } MPI2_CONFIG_PAGE_MAN_0,
 434   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
 435   Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
 436 
 437 #define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
 438 
 439 
 440 /* Manufacturing Page 1 */
 441 
 442 typedef struct _MPI2_CONFIG_PAGE_MAN_1
 443 {
 444     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 445     U8                      VPD[256];                   /* 0x04 */
 446 } MPI2_CONFIG_PAGE_MAN_1,
 447   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
 448   Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
 449 
 450 #define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
 451 
 452 
 453 typedef struct _MPI2_CHIP_REVISION_ID
 454 {
 455     U16 DeviceID;                                       /* 0x00 */
 456     U8  PCIRevisionID;                                  /* 0x02 */
 457     U8  Reserved;                                       /* 0x03 */
 458 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
 459   Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
 460 
 461 
 462 /* Manufacturing Page 2 */
 463 
 464 /*
 465  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 466  * one and check Header.PageLength at runtime.
 467  */
 468 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
 469 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
 470 #endif
 471 
 472 typedef struct _MPI2_CONFIG_PAGE_MAN_2
 473 {
 474     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 475     MPI2_CHIP_REVISION_ID   ChipId;                     /* 0x04 */
 476     U32                     HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
 477 } MPI2_CONFIG_PAGE_MAN_2,
 478   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
 479   Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
 480 
 481 #define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
 482 
 483 
 484 /* Manufacturing Page 3 */
 485 
 486 /*
 487  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 488  * one and check Header.PageLength at runtime.
 489  */
 490 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
 491 #define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
 492 #endif
 493 
 494 typedef struct _MPI2_CONFIG_PAGE_MAN_3
 495 {
 496     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
 497     MPI2_CHIP_REVISION_ID               ChipId;         /* 0x04 */
 498     U32                                 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
 499 } MPI2_CONFIG_PAGE_MAN_3,
 500   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
 501   Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
 502 
 503 #define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
 504 
 505 
 506 /* Manufacturing Page 4 */
 507 
 508 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
 509 {
 510     U8                          PowerSaveFlags;                 /* 0x00 */
 511     U8                          InternalOperationsSleepTime;    /* 0x01 */
 512     U8                          InternalOperationsRunTime;      /* 0x02 */
 513     U8                          HostIdleTime;                   /* 0x03 */
 514 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
 515   MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
 516   Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
 517 
 518 /* defines for the PowerSaveFlags field */
 519 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
 520 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
 521 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
 522 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
 523 
 524 typedef struct _MPI2_CONFIG_PAGE_MAN_4
 525 {
 526     MPI2_CONFIG_PAGE_HEADER             Header;                 /* 0x00 */
 527     U32                                 Reserved1;              /* 0x04 */
 528     U32                                 Flags;                  /* 0x08 */
 529     U8                                  InquirySize;            /* 0x0C */
 530     U8                                  Reserved2;              /* 0x0D */
 531     U16                                 Reserved3;              /* 0x0E */
 532     U8                                  InquiryData[56];        /* 0x10 */
 533     U32                                 RAID0VolumeSettings;    /* 0x48 */
 534     U32                                 RAID1EVolumeSettings;   /* 0x4C */
 535     U32                                 RAID1VolumeSettings;    /* 0x50 */
 536     U32                                 RAID10VolumeSettings;   /* 0x54 */
 537     U32                                 Reserved4;              /* 0x58 */
 538     U32                                 Reserved5;              /* 0x5C */
 539     MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /* 0x60 */
 540     U8                                  MaxOCEDisks;            /* 0x64 */
 541     U8                                  ResyncRate;             /* 0x65 */
 542     U16                                 DataScrubDuration;      /* 0x66 */
 543     U8                                  MaxHotSpares;           /* 0x68 */
 544     U8                                  MaxPhysDisksPerVol;     /* 0x69 */
 545     U8                                  MaxPhysDisks;           /* 0x6A */
 546     U8                                  MaxVolumes;             /* 0x6B */
 547 } MPI2_CONFIG_PAGE_MAN_4,
 548   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
 549   Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
 550 
 551 #define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
 552 
 553 /* Manufacturing Page 4 Flags field */
 554 #define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
 555 #define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
 556 
 557 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
 558 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
 559 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
 560 
 561 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
 562 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
 563 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
 564 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
 565 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
 566 
 567 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
 568 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
 569 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
 570 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
 571 
 572 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
 573 #define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
 574 #define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
 575 #define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
 576 #define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
 577 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
 578 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
 579 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
 580 
 581 
 582 /* Manufacturing Page 5 */
 583 
 584 /*
 585  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 586  * one and check Header.PageLength or NumPhys at runtime.
 587  */
 588 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
 589 #define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
 590 #endif
 591 
 592 typedef struct _MPI2_MANUFACTURING5_ENTRY
 593 {
 594     U64                                 WWID;           /* 0x00 */
 595     U64                                 DeviceName;     /* 0x08 */
 596 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
 597   Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
 598 
 599 typedef struct _MPI2_CONFIG_PAGE_MAN_5
 600 {
 601     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
 602     U8                                  NumPhys;        /* 0x04 */
 603     U8                                  Reserved1;      /* 0x05 */
 604     U16                                 Reserved2;      /* 0x06 */
 605     U32                                 Reserved3;      /* 0x08 */
 606     U32                                 Reserved4;      /* 0x0C */
 607     MPI2_MANUFACTURING5_ENTRY           Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
 608 } MPI2_CONFIG_PAGE_MAN_5,
 609   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
 610   Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
 611 
 612 #define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
 613 
 614 
 615 /* Manufacturing Page 6 */
 616 
 617 typedef struct _MPI2_CONFIG_PAGE_MAN_6
 618 {
 619     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
 620     U32                             ProductSpecificInfo;/* 0x04 */
 621 } MPI2_CONFIG_PAGE_MAN_6,
 622   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
 623   Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
 624 
 625 #define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
 626 
 627 
 628 /* Manufacturing Page 7 */
 629 
 630 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
 631 {
 632     U32                         Pinout;                 /* 0x00 */
 633     U8                          Connector[16];          /* 0x04 */
 634     U8                          Location;               /* 0x14 */
 635     U8                          Reserved1;              /* 0x15 */
 636     U16                         Slot;                   /* 0x16 */
 637     U32                         Reserved2;              /* 0x18 */
 638 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
 639   Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
 640 
 641 /* defines for the Pinout field */
 642 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4                (0x00080000)
 643 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3                (0x00040000)
 644 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2                (0x00020000)
 645 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1                (0x00010000)
 646 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4                (0x00000800)
 647 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3                (0x00000400)
 648 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2                (0x00000200)
 649 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1                (0x00000100)
 650 #define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x00000002)
 651 #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN         (0x00000001)
 652 
 653 /* defines for the Location field */
 654 #define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
 655 #define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
 656 #define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
 657 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
 658 #define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
 659 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
 660 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
 661 
 662 /*
 663  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 664  * one and check NumPhys at runtime.
 665  */
 666 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
 667 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
 668 #endif
 669 
 670 typedef struct _MPI2_CONFIG_PAGE_MAN_7
 671 {
 672     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
 673     U32                             Reserved1;          /* 0x04 */
 674     U32                             Reserved2;          /* 0x08 */
 675     U32                             Flags;              /* 0x0C */
 676     U8                              EnclosureName[16];  /* 0x10 */
 677     U8                              NumPhys;            /* 0x20 */
 678     U8                              Reserved3;          /* 0x21 */
 679     U16                             Reserved4;          /* 0x22 */
 680     MPI2_MANPAGE7_CONNECTOR_INFO    ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
 681 } MPI2_CONFIG_PAGE_MAN_7,
 682   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
 683   Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
 684 
 685 #define MPI2_MANUFACTURING7_PAGEVERSION                 (0x00)
 686 
 687 /* defines for the Flags field */
 688 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
 689 
 690 
 691 /*
 692  * Generic structure to use for product-specific manufacturing pages
 693  * (currently Manufacturing Page 8 through Manufacturing Page 31).
 694  */
 695 
 696 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
 697 {
 698     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
 699     U32                             ProductSpecificInfo;/* 0x04 */
 700 } MPI2_CONFIG_PAGE_MAN_PS,
 701   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
 702   Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
 703 
 704 #define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
 705 #define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
 706 #define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
 707 #define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
 708 #define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
 709 #define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
 710 #define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
 711 #define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
 712 #define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
 713 #define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
 714 #define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
 715 #define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
 716 #define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
 717 #define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
 718 #define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
 719 #define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
 720 #define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
 721 #define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
 722 #define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
 723 #define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
 724 #define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
 725 #define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
 726 #define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
 727 #define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
 728 
 729 
 730 /****************************************************************************
 731 *   IO Unit Config Pages
 732 ****************************************************************************/
 733 
 734 /* IO Unit Page 0 */
 735 
 736 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
 737 {
 738     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 739     U64                     UniqueValue;                /* 0x04 */
 740     MPI2_VERSION_UNION      NvdataVersionDefault;       /* 0x08 */
 741     MPI2_VERSION_UNION      NvdataVersionPersistent;    /* 0x0A */
 742 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
 743   Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
 744 
 745 #define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
 746 
 747 
 748 /* IO Unit Page 1 */
 749 
 750 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
 751 {
 752     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 753     U32                     Flags;                      /* 0x04 */
 754 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
 755   Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
 756 
 757 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
 758 
 759 /* IO Unit Page 1 Flags defines */
 760 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
 761 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
 762 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
 763 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
 764 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
 765 #define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
 766 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
 767 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
 768 #define MPI2_IOUNITPAGE1_MULTI_PATHING                  (0x00000002)
 769 #define MPI2_IOUNITPAGE1_SINGLE_PATHING                 (0x00000000)
 770 
 771 
 772 /* IO Unit Page 3 */
 773 
 774 /*
 775  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 776  * one and check Header.PageLength at runtime.
 777  */
 778 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
 779 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (1)
 780 #endif
 781 
 782 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
 783 {
 784     MPI2_CONFIG_PAGE_HEADER Header;                                   /* 0x00 */
 785     U8                      GPIOCount;                                /* 0x04 */
 786     U8                      Reserved1;                                /* 0x05 */
 787     U16                     Reserved2;                                /* 0x06 */
 788     U16                     GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
 789 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
 790   Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
 791 
 792 #define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
 793 
 794 /* defines for IO Unit Page 3 GPIOVal field */
 795 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
 796 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
 797 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
 798 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
 799 
 800 
 801 /* IO Unit Page 5 */
 802 
 803 /*
 804  * Upper layer code (drivers, utilities, etc.) should leave this define set to
 805  * one and check Header.PageLength or NumDmaEngines at runtime.
 806  */
 807 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
 808 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
 809 #endif
 810 
 811 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5
 812 {
 813     MPI2_CONFIG_PAGE_HEADER Header;                                     /* 0x00 */
 814     U64                     RaidAcceleratorBufferBaseAddress;           /* 0x04 */
 815     U64                     RaidAcceleratorBufferSize;                  /* 0x0C */
 816     U64                     RaidAcceleratorControlBaseAddress;          /* 0x14 */
 817     U8                      RAControlSize;                              /* 0x1C */
 818     U8                      NumDmaEngines;                              /* 0x1D */
 819     U8                      RAMinControlSize;                           /* 0x1E */
 820     U8                      RAMaxControlSize;                           /* 0x1F */
 821     U32                     Reserved1;                                  /* 0x20 */
 822     U32                     Reserved2;                                  /* 0x24 */
 823     U32                     Reserved3;                                  /* 0x28 */
 824     U32                     DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
 825 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
 826   Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
 827 
 828 #define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
 829 
 830 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
 831 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFF00)
 832 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
 833 
 834 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
 835 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
 836 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
 837 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
 838 
 839 
 840 /* IO Unit Page 6 */
 841 
 842 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6
 843 {
 844     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 845     U16                     Flags;                                  /* 0x04 */
 846     U8                      RAHostControlSize;                      /* 0x06 */
 847     U8                      Reserved0;                              /* 0x07 */
 848     U64                     RaidAcceleratorHostControlBaseAddress;  /* 0x08 */
 849     U32                     Reserved1;                              /* 0x10 */
 850     U32                     Reserved2;                              /* 0x14 */
 851     U32                     Reserved3;                              /* 0x18 */
 852 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
 853   Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
 854 
 855 #define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
 856 
 857 /* defines for IO Unit Page 6 Flags field */
 858 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
 859 
 860 
 861 /* IO Unit Page 7 */
 862 
 863 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
 864 {
 865     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 866     U16                     Reserved1;                              /* 0x04 */
 867     U8                      PCIeWidth;                              /* 0x06 */
 868     U8                      PCIeSpeed;                              /* 0x07 */
 869     U32                     ProcessorState;                         /* 0x08 */
 870     U32                     Reserved2;                              /* 0x0C */
 871     U16                     IOCTemperature;                         /* 0x10 */
 872     U8                      IOCTemperatureUnits;                    /* 0x12 */
 873     U8                      IOCSpeed;                               /* 0x13 */
 874     U32                     Reserved3;                              /* 0x14 */
 875 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
 876   Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
 877 
 878 #define MPI2_IOUNITPAGE7_PAGEVERSION                    (0x00)
 879 
 880 /* defines for IO Unit Page 7 PCIeWidth field */
 881 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
 882 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
 883 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
 884 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
 885 
 886 /* defines for IO Unit Page 7 PCIeSpeed field */
 887 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
 888 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
 889 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
 890 
 891 /* defines for IO Unit Page 7 ProcessorState field */
 892 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
 893 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
 894 
 895 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
 896 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
 897 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
 898 
 899 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
 900 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
 901 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
 902 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
 903 
 904 /* defines for IO Unit Page 7 IOCSpeed field */
 905 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
 906 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
 907 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
 908 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
 909 
 910 
 911 
 912 /****************************************************************************
 913 *   IOC Config Pages
 914 ****************************************************************************/
 915 
 916 /* IOC Page 0 */
 917 
 918 typedef struct _MPI2_CONFIG_PAGE_IOC_0
 919 {
 920     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 921     U32                     Reserved1;                  /* 0x04 */
 922     U32                     Reserved2;                  /* 0x08 */
 923     U16                     VendorID;                   /* 0x0C */
 924     U16                     DeviceID;                   /* 0x0E */
 925     U8                      RevisionID;                 /* 0x10 */
 926     U8                      Reserved3;                  /* 0x11 */
 927     U16                     Reserved4;                  /* 0x12 */
 928     U32                     ClassCode;                  /* 0x14 */
 929     U16                     SubsystemVendorID;          /* 0x18 */
 930     U16                     SubsystemID;                /* 0x1A */
 931 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
 932   Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
 933 
 934 #define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
 935 
 936 
 937 /* IOC Page 1 */
 938 
 939 typedef struct _MPI2_CONFIG_PAGE_IOC_1
 940 {
 941     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 942     U32                     Flags;                      /* 0x04 */
 943     U32                     CoalescingTimeout;          /* 0x08 */
 944     U8                      CoalescingDepth;            /* 0x0C */
 945     U8                      PCISlotNum;                 /* 0x0D */
 946     U8                      PCIBusNum;                  /* 0x0E */
 947     U8                      PCIDomainSegment;           /* 0x0F */
 948     U32                     Reserved1;                  /* 0x10 */
 949     U32                     Reserved2;                  /* 0x14 */
 950 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
 951   Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
 952 
 953 #define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
 954 
 955 /* defines for IOC Page 1 Flags field */
 956 #define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
 957 
 958 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
 959 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
 960 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
 961 
 962 /* IOC Page 6 */
 963 
 964 typedef struct _MPI2_CONFIG_PAGE_IOC_6
 965 {
 966     MPI2_CONFIG_PAGE_HEADER Header;                         /* 0x00 */
 967     U32                     CapabilitiesFlags;              /* 0x04 */
 968     U8                      MaxDrivesRAID0;                 /* 0x08 */
 969     U8                      MaxDrivesRAID1;                 /* 0x09 */
 970     U8                      MaxDrivesRAID1E;                /* 0x0A */
 971     U8                      MaxDrivesRAID10;                /* 0x0B */
 972     U8                      MinDrivesRAID0;                 /* 0x0C */
 973     U8                      MinDrivesRAID1;                 /* 0x0D */
 974     U8                      MinDrivesRAID1E;                /* 0x0E */
 975     U8                      MinDrivesRAID10;                /* 0x0F */
 976     U32                     Reserved1;                      /* 0x10 */
 977     U8                      MaxGlobalHotSpares;             /* 0x14 */
 978     U8                      MaxPhysDisks;                   /* 0x15 */
 979     U8                      MaxVolumes;                     /* 0x16 */
 980     U8                      MaxConfigs;                     /* 0x17 */
 981     U8                      MaxOCEDisks;                    /* 0x18 */
 982     U8                      Reserved2;                      /* 0x19 */
 983     U16                     Reserved3;                      /* 0x1A */
 984     U32                     SupportedStripeSizeMapRAID0;    /* 0x1C */
 985     U32                     SupportedStripeSizeMapRAID1E;   /* 0x20 */
 986     U32                     SupportedStripeSizeMapRAID10;   /* 0x24 */
 987     U32                     Reserved4;                      /* 0x28 */
 988     U32                     Reserved5;                      /* 0x2C */
 989     U16                     DefaultMetadataSize;            /* 0x30 */
 990     U16                     Reserved6;                      /* 0x32 */
 991     U16                     MaxBadBlockTableEntries;        /* 0x34 */
 992     U16                     Reserved7;                      /* 0x36 */
 993     U32                     IRNvsramVersion;                /* 0x38 */
 994 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
 995   Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
 996 
 997 #define MPI2_IOCPAGE6_PAGEVERSION                       (0x04)
 998 
 999 /* defines for IOC Page 6 CapabilitiesFlags */
1000 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
1001 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
1002 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
1003 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
1004 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
1005 
1006 
1007 /* IOC Page 7 */
1008 
1009 #define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
1010 
1011 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1012 {
1013     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1014     U32                     Reserved1;                  /* 0x04 */
1015     U32                     EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1016     U16                     SASBroadcastPrimitiveMasks; /* 0x18 */
1017     U16                     Reserved2;                  /* 0x1A */
1018     U32                     Reserved3;                  /* 0x1C */
1019 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1020   Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1021 
1022 #define MPI2_IOCPAGE7_PAGEVERSION                       (0x01)
1023 
1024 
1025 /* IOC Page 8 */
1026 
1027 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1028 {
1029     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1030     U8                      NumDevsPerEnclosure;        /* 0x04 */
1031     U8                      Reserved1;                  /* 0x05 */
1032     U16                     Reserved2;                  /* 0x06 */
1033     U16                     MaxPersistentEntries;       /* 0x08 */
1034     U16                     MaxNumPhysicalMappedIDs;    /* 0x0A */
1035     U16                     Flags;                      /* 0x0C */
1036     U16                     Reserved3;                  /* 0x0E */
1037     U16                     IRVolumeMappingFlags;       /* 0x10 */
1038     U16                     Reserved4;                  /* 0x12 */
1039     U32                     Reserved5;                  /* 0x14 */
1040 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1041   Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1042 
1043 #define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
1044 
1045 /* defines for IOC Page 8 Flags field */
1046 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
1047 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
1048 
1049 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
1050 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
1051 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
1052 
1053 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
1054 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
1055 
1056 /* defines for IOC Page 8 IRVolumeMappingFlags */
1057 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
1058 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
1059 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
1060 
1061 
1062 /****************************************************************************
1063 *   BIOS Config Pages
1064 ****************************************************************************/
1065 
1066 /* BIOS Page 1 */
1067 
1068 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1069 {
1070     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1071     U32                     BiosOptions;                /* 0x04 */
1072     U32                     IOCSettings;                /* 0x08 */
1073     U32                     Reserved1;                  /* 0x0C */
1074     U32                     DeviceSettings;             /* 0x10 */
1075     U16                     NumberOfDevices;            /* 0x14 */
1076     U16                     Reserved2;                  /* 0x16 */
1077     U16                     IOTimeoutBlockDevicesNonRM; /* 0x18 */
1078     U16                     IOTimeoutSequential;        /* 0x1A */
1079     U16                     IOTimeoutOther;             /* 0x1C */
1080     U16                     IOTimeoutBlockDevicesRM;    /* 0x1E */
1081 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1082   Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1083 
1084 #define MPI2_BIOSPAGE1_PAGEVERSION                      (0x04)
1085 
1086 /* values for BIOS Page 1 BiosOptions field */
1087 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS             (0x00000001)
1088 
1089 /* values for BIOS Page 1 IOCSettings field */
1090 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
1091 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
1092 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
1093 
1094 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
1095 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
1096 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
1097 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
1098 
1099 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
1100 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
1101 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
1102 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
1103 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
1104 
1105 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
1106 
1107 /* values for BIOS Page 1 DeviceSettings field */
1108 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
1109 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
1110 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
1111 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
1112 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
1113 
1114 
1115 /* BIOS Page 2 */
1116 
1117 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1118 {
1119     U32         Reserved1;                              /* 0x00 */
1120     U32         Reserved2;                              /* 0x04 */
1121     U32         Reserved3;                              /* 0x08 */
1122     U32         Reserved4;                              /* 0x0C */
1123     U32         Reserved5;                              /* 0x10 */
1124     U32         Reserved6;                              /* 0x14 */
1125 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1126   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1127   Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1128 
1129 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1130 {
1131     U64         SASAddress;                             /* 0x00 */
1132     U8          LUN[8];                                 /* 0x08 */
1133     U32         Reserved1;                              /* 0x10 */
1134     U32         Reserved2;                              /* 0x14 */
1135 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1136   Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1137 
1138 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1139 {
1140     U64         EnclosureLogicalID;                     /* 0x00 */
1141     U32         Reserved1;                              /* 0x08 */
1142     U32         Reserved2;                              /* 0x0C */
1143     U16         SlotNumber;                             /* 0x10 */
1144     U16         Reserved3;                              /* 0x12 */
1145     U32         Reserved4;                              /* 0x14 */
1146 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1147   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1148   Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1149 
1150 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1151 {
1152     U64         DeviceName;                             /* 0x00 */
1153     U8          LUN[8];                                 /* 0x08 */
1154     U32         Reserved1;                              /* 0x10 */
1155     U32         Reserved2;                              /* 0x14 */
1156 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1157   Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1158 
1159 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1160 {
1161     MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
1162     MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
1163     MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1164     MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
1165 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1166   Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1167 
1168 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1169 {
1170     MPI2_CONFIG_PAGE_HEADER     Header;                 /* 0x00 */
1171     U32                         Reserved1;              /* 0x04 */
1172     U32                         Reserved2;              /* 0x08 */
1173     U32                         Reserved3;              /* 0x0C */
1174     U32                         Reserved4;              /* 0x10 */
1175     U32                         Reserved5;              /* 0x14 */
1176     U32                         Reserved6;              /* 0x18 */
1177     U8                          ReqBootDeviceForm;      /* 0x1C */
1178     U8                          Reserved7;              /* 0x1D */
1179     U16                         Reserved8;              /* 0x1E */
1180     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /* 0x20 */
1181     U8                          ReqAltBootDeviceForm;   /* 0x38 */
1182     U8                          Reserved9;              /* 0x39 */
1183     U16                         Reserved10;             /* 0x3A */
1184     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /* 0x3C */
1185     U8                          CurrentBootDeviceForm;  /* 0x58 */
1186     U8                          Reserved11;             /* 0x59 */
1187     U16                         Reserved12;             /* 0x5A */
1188     MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /* 0x58 */
1189 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1190   Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1191 
1192 #define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
1193 
1194 /* values for BIOS Page 2 BootDeviceForm fields */
1195 #define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
1196 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
1197 #define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
1198 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
1199 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
1200 
1201 
1202 /* BIOS Page 3 */
1203 
1204 typedef struct _MPI2_ADAPTER_INFO
1205 {
1206     U8      PciBusNumber;                               /* 0x00 */
1207     U8      PciDeviceAndFunctionNumber;                 /* 0x01 */
1208     U16     AdapterFlags;                               /* 0x02 */
1209 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1210   Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1211 
1212 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
1213 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
1214 
1215 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1216 {
1217     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1218     U32                     GlobalFlags;                /* 0x04 */
1219     U32                     BiosVersion;                /* 0x08 */
1220     MPI2_ADAPTER_INFO       AdapterOrder[4];            /* 0x0C */
1221     U32                     Reserved1;                  /* 0x1C */
1222 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1223   Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1224 
1225 #define MPI2_BIOSPAGE3_PAGEVERSION                      (0x00)
1226 
1227 /* values for BIOS Page 3 GlobalFlags */
1228 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
1229 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
1230 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
1231 
1232 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
1233 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
1234 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
1235 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
1236 
1237 
1238 /* BIOS Page 4 */
1239 
1240 /*
1241  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1242  * one and check Header.PageLength or NumPhys at runtime.
1243  */
1244 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1245 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
1246 #endif
1247 
1248 typedef struct _MPI2_BIOS4_ENTRY
1249 {
1250     U64                     ReassignmentWWID;       /* 0x00 */
1251     U64                     ReassignmentDeviceName; /* 0x08 */
1252 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1253   Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1254 
1255 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1256 {
1257     MPI2_CONFIG_PAGE_HEADER Header;                             /* 0x00 */
1258     U8                      NumPhys;                            /* 0x04 */
1259     U8                      Reserved1;                          /* 0x05 */
1260     U16                     Reserved2;                          /* 0x06 */
1261     MPI2_BIOS4_ENTRY        Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /* 0x08 */
1262 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1263   Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1264 
1265 #define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
1266 
1267 
1268 /****************************************************************************
1269 *   RAID Volume Config Pages
1270 ****************************************************************************/
1271 
1272 /* RAID Volume Page 0 */
1273 
1274 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1275 {
1276     U8                      RAIDSetNum;                 /* 0x00 */
1277     U8                      PhysDiskMap;                /* 0x01 */
1278     U8                      PhysDiskNum;                /* 0x02 */
1279     U8                      Reserved;                   /* 0x03 */
1280 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1281   Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1282 
1283 /* defines for the PhysDiskMap field */
1284 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
1285 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
1286 
1287 typedef struct _MPI2_RAIDVOL0_SETTINGS
1288 {
1289     U16                     Settings;                   /* 0x00 */
1290     U8                      HotSparePool;               /* 0x01 */
1291     U8                      Reserved;                   /* 0x02 */
1292 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1293   Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1294 
1295 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1296 #define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
1297 #define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
1298 #define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
1299 #define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
1300 #define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
1301 #define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
1302 #define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
1303 #define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
1304 
1305 /* RAID Volume Page 0 VolumeSettings defines */
1306 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
1307 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1308 
1309 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
1310 #define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
1311 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
1312 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
1313 
1314 /*
1315  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1316  * one and check Header.PageLength at runtime.
1317  */
1318 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1319 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
1320 #endif
1321 
1322 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1323 {
1324     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1325     U16                     DevHandle;                  /* 0x04 */
1326     U8                      VolumeState;                /* 0x06 */
1327     U8                      VolumeType;                 /* 0x07 */
1328     U32                     VolumeStatusFlags;          /* 0x08 */
1329     MPI2_RAIDVOL0_SETTINGS  VolumeSettings;             /* 0x0C */
1330     U64                     MaxLBA;                     /* 0x10 */
1331     U32                     StripeSize;                 /* 0x18 */
1332     U16                     BlockSize;                  /* 0x1C */
1333     U16                     Reserved1;                  /* 0x1E */
1334     U8                      SupportedPhysDisks;         /* 0x20 */
1335     U8                      ResyncRate;                 /* 0x21 */
1336     U16                     DataScrubDuration;          /* 0x22 */
1337     U8                      NumPhysDisks;               /* 0x24 */
1338     U8                      Reserved2;                  /* 0x25 */
1339     U8                      Reserved3;                  /* 0x26 */
1340     U8                      InactiveStatus;             /* 0x27 */
1341     MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1342 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1343   Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1344 
1345 #define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
1346 
1347 /* values for RAID VolumeState */
1348 #define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
1349 #define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
1350 #define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
1351 #define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
1352 #define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
1353 #define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
1354 
1355 /* values for RAID VolumeType */
1356 #define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
1357 #define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
1358 #define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
1359 #define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
1360 #define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
1361 
1362 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1363 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
1364 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
1365 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
1366 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
1367 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
1368 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
1369 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
1370 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
1371 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
1372 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
1373 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
1374 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
1375 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
1376 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
1377 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
1378 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
1379 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
1380 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
1381 
1382 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1383 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
1384 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
1385 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
1386 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
1387 
1388 /* values for RAID Volume Page 0 InactiveStatus field */
1389 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
1390 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
1391 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
1392 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
1393 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
1394 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
1395 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
1396 
1397 
1398 /* RAID Volume Page 1 */
1399 
1400 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1401 {
1402     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1403     U16                     DevHandle;                  /* 0x04 */
1404     U16                     Reserved0;                  /* 0x06 */
1405     U8                      GUID[24];                   /* 0x08 */
1406     U8                      Name[16];                   /* 0x20 */
1407     U64                     WWID;                       /* 0x30 */
1408     U32                     Reserved1;                  /* 0x38 */
1409     U32                     Reserved2;                  /* 0x3C */
1410 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1411   Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1412 
1413 #define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
1414 
1415 
1416 /****************************************************************************
1417 *   RAID Physical Disk Config Pages
1418 ****************************************************************************/
1419 
1420 /* RAID Physical Disk Page 0 */
1421 
1422 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1423 {
1424     U16                     Reserved1;                  /* 0x00 */
1425     U8                      HotSparePool;               /* 0x02 */
1426     U8                      Reserved2;                  /* 0x03 */
1427 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1428   Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1429 
1430 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1431 
1432 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1433 {
1434     U8                      VendorID[8];                /* 0x00 */
1435     U8                      ProductID[16];              /* 0x08 */
1436     U8                      ProductRevLevel[4];         /* 0x18 */
1437     U8                      SerialNum[32];              /* 0x1C */
1438 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1439   MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1440   Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1441 
1442 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1443 {
1444     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
1445     U16                             DevHandle;                  /* 0x04 */
1446     U8                              Reserved1;                  /* 0x06 */
1447     U8                              PhysDiskNum;                /* 0x07 */
1448     MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;           /* 0x08 */
1449     U32                             Reserved2;                  /* 0x0C */
1450     MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;                /* 0x10 */
1451     U32                             Reserved3;                  /* 0x4C */
1452     U8                              PhysDiskState;              /* 0x50 */
1453     U8                              OfflineReason;              /* 0x51 */
1454     U8                              IncompatibleReason;         /* 0x52 */
1455     U8                              PhysDiskAttributes;         /* 0x53 */
1456     U32                             PhysDiskStatusFlags;        /* 0x54 */
1457     U64                             DeviceMaxLBA;               /* 0x58 */
1458     U64                             HostMaxLBA;                 /* 0x60 */
1459     U64                             CoercedMaxLBA;              /* 0x68 */
1460     U16                             BlockSize;                  /* 0x70 */
1461     U16                             Reserved5;                  /* 0x72 */
1462     U32                             Reserved6;                  /* 0x74 */
1463 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1464   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1465   Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1466 
1467 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
1468 
1469 /* PhysDiskState defines */
1470 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
1471 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
1472 #define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
1473 #define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
1474 #define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
1475 #define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
1476 #define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
1477 #define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
1478 
1479 /* OfflineReason defines */
1480 #define MPI2_PHYSDISK0_ONLINE                           (0x00)
1481 #define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
1482 #define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
1483 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
1484 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
1485 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
1486 #define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
1487 
1488 /* IncompatibleReason defines */
1489 #define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
1490 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
1491 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
1492 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
1493 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
1494 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
1495 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
1496 
1497 /* PhysDiskAttributes defines */
1498 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
1499 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
1500 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
1501 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
1502 
1503 /* PhysDiskStatusFlags defines */
1504 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
1505 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
1506 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
1507 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
1508 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1509 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
1510 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
1511 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
1512 
1513 
1514 /* RAID Physical Disk Page 1 */
1515 
1516 /*
1517  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1518  * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1519  */
1520 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1521 #define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
1522 #endif
1523 
1524 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1525 {
1526     U16             DevHandle;          /* 0x00 */
1527     U16             Reserved1;          /* 0x02 */
1528     U64             WWID;               /* 0x04 */
1529     U64             OwnerWWID;          /* 0x0C */
1530     U8              OwnerIdentifier;    /* 0x14 */
1531     U8              Reserved2;          /* 0x15 */
1532     U16             Flags;              /* 0x16 */
1533 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1534   Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1535 
1536 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1537 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
1538 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
1539 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
1540 
1541 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1542 {
1543     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
1544     U8                              NumPhysDiskPaths;           /* 0x04 */
1545     U8                              PhysDiskNum;                /* 0x05 */
1546     U16                             Reserved1;                  /* 0x06 */
1547     U32                             Reserved2;                  /* 0x08 */
1548     MPI2_RAIDPHYSDISK1_PATH         PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1549 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1550   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1551   Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1552 
1553 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
1554 
1555 
1556 /****************************************************************************
1557 *   values for fields used by several types of SAS Config Pages
1558 ****************************************************************************/
1559 
1560 /* values for NegotiatedLinkRates fields */
1561 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
1562 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
1563 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
1564 /* link rates used for Negotiated Physical and Logical Link Rate */
1565 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
1566 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
1567 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
1568 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
1569 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
1570 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
1571 #define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
1572 #define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
1573 #define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
1574 
1575 
1576 /* values for AttachedPhyInfo fields */
1577 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
1578 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
1579 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
1580 
1581 #define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
1582 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
1583 #define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
1584 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
1585 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
1586 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
1587 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
1588 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
1589 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
1590 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
1591 
1592 
1593 /* values for PhyInfo fields */
1594 #define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
1595 
1596 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
1597 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
1598 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
1599 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
1600 
1601 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
1602 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
1603 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
1604 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
1605 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
1606 #define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
1607 
1608 #define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
1609 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
1610 #define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
1611 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
1612 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
1613 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
1614 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
1615 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
1616 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
1617 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
1618 
1619 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
1620 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
1621 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
1622 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
1623 
1624 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
1625 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
1626 
1627 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
1628 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
1629 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
1630 #define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
1631 
1632 
1633 /* values for SAS ProgrammedLinkRate fields */
1634 #define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
1635 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
1636 #define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
1637 #define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
1638 #define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
1639 #define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
1640 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
1641 #define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
1642 #define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
1643 #define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
1644 
1645 
1646 /* values for SAS HwLinkRate fields */
1647 #define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
1648 #define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
1649 #define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
1650 #define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
1651 #define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
1652 #define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
1653 #define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
1654 #define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
1655 
1656 
1657 
1658 /****************************************************************************
1659 *   SAS IO Unit Config Pages
1660 ****************************************************************************/
1661 
1662 /* SAS IO Unit Page 0 */
1663 
1664 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1665 {
1666     U8          Port;                   /* 0x00 */
1667     U8          PortFlags;              /* 0x01 */
1668     U8          PhyFlags;               /* 0x02 */
1669     U8          NegotiatedLinkRate;     /* 0x03 */
1670     U32         ControllerPhyDeviceInfo;/* 0x04 */
1671     U16         AttachedDevHandle;      /* 0x08 */
1672     U16         ControllerDevHandle;    /* 0x0A */
1673     U32         DiscoveryStatus;        /* 0x0C */
1674     U32         Reserved;               /* 0x10 */
1675 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1676   Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1677 
1678 /*
1679  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1680  * one and check Header.ExtPageLength or NumPhys at runtime.
1681  */
1682 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1683 #define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
1684 #endif
1685 
1686 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1687 {
1688     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
1689     U32                                 Reserved1;                          /* 0x08 */
1690     U8                                  NumPhys;                            /* 0x0C */
1691     U8                                  Reserved2;                          /* 0x0D */
1692     U16                                 Reserved3;                          /* 0x0E */
1693     MPI2_SAS_IO_UNIT0_PHY_DATA          PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];  /* 0x10 */
1694 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1695   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1696   Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1697 
1698 #define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
1699 
1700 /* values for SAS IO Unit Page 0 PortFlags */
1701 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
1702 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
1703 
1704 /* values for SAS IO Unit Page 0 PhyFlags */
1705 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
1706 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
1707 
1708 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1709 
1710 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1711 
1712 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1713 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
1714 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
1715 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
1716 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
1717 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
1718 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
1719 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
1720 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
1721 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
1722 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
1723 #define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
1724 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
1725 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
1726 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
1727 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
1728 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
1729 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
1730 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
1731 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
1732 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
1733 
1734 
1735 /* SAS IO Unit Page 1 */
1736 
1737 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1738 {
1739     U8          Port;                       /* 0x00 */
1740     U8          PortFlags;                  /* 0x01 */
1741     U8          PhyFlags;                   /* 0x02 */
1742     U8          MaxMinLinkRate;             /* 0x03 */
1743     U32         ControllerPhyDeviceInfo;    /* 0x04 */
1744     U16         MaxTargetPortConnectTime;   /* 0x08 */
1745     U16         Reserved1;                  /* 0x0A */
1746 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1747   Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1748 
1749 /*
1750  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1751  * one and check Header.ExtPageLength or NumPhys at runtime.
1752  */
1753 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1754 #define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
1755 #endif
1756 
1757 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1758 {
1759     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
1760     U16                                 ControlFlags;                       /* 0x08 */
1761     U16                                 SASNarrowMaxQueueDepth;             /* 0x0A */
1762     U16                                 AdditionalControlFlags;             /* 0x0C */
1763     U16                                 SASWideMaxQueueDepth;               /* 0x0E */
1764     U8                                  NumPhys;                            /* 0x10 */
1765     U8                                  SATAMaxQDepth;                      /* 0x11 */
1766     U8                                  ReportDeviceMissingDelay;           /* 0x12 */
1767     U8                                  IODeviceMissingDelay;               /* 0x13 */
1768     MPI2_SAS_IO_UNIT1_PHY_DATA          PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /* 0x14 */
1769 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1770   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1771   Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1772 
1773 #define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
1774 
1775 /* values for SAS IO Unit Page 1 ControlFlags */
1776 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
1777 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
1778 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000)
1779 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
1780 
1781 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
1782 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
1783 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
1784 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
1785 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
1786 
1787 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
1788 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
1789 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
1790 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
1791 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
1792 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
1793 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
1794 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001)
1795 
1796 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1797 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
1798 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
1799 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
1800 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
1801 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
1802 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
1803 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
1804 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
1805 
1806 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1807 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
1808 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
1809 
1810 /* values for SAS IO Unit Page 1 PortFlags */
1811 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
1812 
1813 /* values for SAS IO Unit Page 1 PhyFlags */
1814 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
1815 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
1816 
1817 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1818 #define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
1819 #define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
1820 #define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
1821 #define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
1822 #define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
1823 #define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
1824 #define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
1825 #define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
1826 
1827 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1828 
1829 
1830 /* SAS IO Unit Page 4 */
1831 
1832 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1833 {
1834     U8          MaxTargetSpinup;            /* 0x00 */
1835     U8          SpinupDelay;                /* 0x01 */
1836     U16         Reserved1;                  /* 0x02 */
1837 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1838   Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1839 
1840 /*
1841  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1842  * four and check Header.ExtPageLength or NumPhys at runtime.
1843  */
1844 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1845 #define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
1846 #endif
1847 
1848 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1849 {
1850     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
1851     MPI2_SAS_IOUNIT4_SPINUP_GROUP       SpinupGroupParameters[4];       /* 0x08 */
1852     U32                                 Reserved1;                      /* 0x18 */
1853     U32                                 Reserved2;                      /* 0x1C */
1854     U32                                 Reserved3;                      /* 0x20 */
1855     U8                                  BootDeviceWaitTime;             /* 0x24 */
1856     U8                                  Reserved4;                      /* 0x25 */
1857     U16                                 Reserved5;                      /* 0x26 */
1858     U8                                  NumPhys;                        /* 0x28 */
1859     U8                                  PEInitialSpinupDelay;           /* 0x29 */
1860     U8                                  PEReplyDelay;                   /* 0x2A */
1861     U8                                  Flags;                          /* 0x2B */
1862     U8                                  PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /* 0x2C */
1863 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1864   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1865   Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1866 
1867 #define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
1868 
1869 /* defines for Flags field */
1870 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
1871 
1872 /* defines for PHY field */
1873 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
1874 
1875 
1876 /* SAS IO Unit Page 5 */
1877 
1878 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
1879 {
1880     U8          ControlFlags;               /* 0x00 */
1881     U8          Reserved1;                  /* 0x01 */
1882     U16         InactivityTimerExponent;    /* 0x02 */
1883     U8          SATAPartialTimeout;         /* 0x04 */
1884     U8          Reserved2;                  /* 0x05 */
1885     U8          SATASlumberTimeout;         /* 0x06 */
1886     U8          Reserved3;                  /* 0x07 */
1887     U8          SASPartialTimeout;          /* 0x08 */
1888     U8          Reserved4;                  /* 0x09 */
1889     U8          SASSlumberTimeout;          /* 0x0A */
1890     U8          Reserved5;                  /* 0x0B */
1891 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1892   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1893   Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1894 
1895 /* defines for ControlFlags field */
1896 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
1897 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
1898 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
1899 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
1900 
1901 /* defines for InactivityTimerExponent field */
1902 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
1903 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
1904 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
1905 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
1906 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
1907 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
1908 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
1909 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
1910 
1911 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
1912 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
1913 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
1914 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
1915 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
1916 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
1917 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
1918 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
1919 
1920 /*
1921  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1922  * one and check Header.ExtPageLength or NumPhys at runtime.
1923  */
1924 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
1925 #define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
1926 #endif
1927 
1928 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
1929 {
1930     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
1931     U8                                  NumPhys;                            /* 0x08 */
1932     U8                                  Reserved1;                          /* 0x09 */
1933     U16                                 Reserved2;                          /* 0x0A */
1934     U32                                 Reserved3;                          /* 0x0C */
1935     MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS   SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];  /* 0x10 */
1936 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
1937   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
1938   Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
1939 
1940 #define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x00)
1941 
1942 
1943 
1944 
1945 /****************************************************************************
1946 *   SAS Expander Config Pages
1947 ****************************************************************************/
1948 
1949 /* SAS Expander Page 0 */
1950 
1951 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
1952 {
1953     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
1954     U8                                  PhysicalPort;               /* 0x08 */
1955     U8                                  ReportGenLength;            /* 0x09 */
1956     U16                                 EnclosureHandle;            /* 0x0A */
1957     U64                                 SASAddress;                 /* 0x0C */
1958     U32                                 DiscoveryStatus;            /* 0x14 */
1959     U16                                 DevHandle;                  /* 0x18 */
1960     U16                                 ParentDevHandle;            /* 0x1A */
1961     U16                                 ExpanderChangeCount;        /* 0x1C */
1962     U16                                 ExpanderRouteIndexes;       /* 0x1E */
1963     U8                                  NumPhys;                    /* 0x20 */
1964     U8                                  SASLevel;                   /* 0x21 */
1965     U16                                 Flags;                      /* 0x22 */
1966     U16                                 STPBusInactivityTimeLimit;  /* 0x24 */
1967     U16                                 STPMaxConnectTimeLimit;     /* 0x26 */
1968     U16                                 STP_SMP_NexusLossTime;      /* 0x28 */
1969     U16                                 MaxNumRoutedSasAddresses;   /* 0x2A */
1970     U64                                 ActiveZoneManagerSASAddress;/* 0x2C */
1971     U16                                 ZoneLockInactivityLimit;    /* 0x34 */
1972     U16                                 Reserved1;                  /* 0x36 */
1973     U8                                  TimeToReducedFunc;          /* 0x38 */
1974     U8                                  InitialTimeToReducedFunc;   /* 0x39 */
1975     U8                                  MaxReducedFuncTime;         /* 0x3A */
1976     U8                                  Reserved2;                  /* 0x3B */
1977 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
1978   Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
1979 
1980 #define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
1981 
1982 /* values for SAS Expander Page 0 DiscoveryStatus field */
1983 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
1984 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
1985 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
1986 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
1987 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
1988 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1989 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
1990 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
1991 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
1992 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
1993 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
1994 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
1995 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
1996 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
1997 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
1998 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
1999 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
2000 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
2001 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
2002 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
2003 
2004 /* values for SAS Expander Page 0 Flags field */
2005 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
2006 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
2007 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
2008 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
2009 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
2010 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
2011 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
2012 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
2013 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
2014 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
2015 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
2016 
2017 
2018 /* SAS Expander Page 1 */
2019 
2020 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2021 {
2022     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2023     U8                                  PhysicalPort;               /* 0x08 */
2024     U8                                  Reserved1;                  /* 0x09 */
2025     U16                                 Reserved2;                  /* 0x0A */
2026     U8                                  NumPhys;                    /* 0x0C */
2027     U8                                  Phy;                        /* 0x0D */
2028     U16                                 NumTableEntriesProgrammed;  /* 0x0E */
2029     U8                                  ProgrammedLinkRate;         /* 0x10 */
2030     U8                                  HwLinkRate;                 /* 0x11 */
2031     U16                                 AttachedDevHandle;          /* 0x12 */
2032     U32                                 PhyInfo;                    /* 0x14 */
2033     U32                                 AttachedDeviceInfo;         /* 0x18 */
2034     U16                                 ExpanderDevHandle;          /* 0x1C */
2035     U8                                  ChangeCount;                /* 0x1E */
2036     U8                                  NegotiatedLinkRate;         /* 0x1F */
2037     U8                                  PhyIdentifier;              /* 0x20 */
2038     U8                                  AttachedPhyIdentifier;      /* 0x21 */
2039     U8                                  Reserved3;                  /* 0x22 */
2040     U8                                  DiscoveryInfo;              /* 0x23 */
2041     U32                                 AttachedPhyInfo;            /* 0x24 */
2042     U8                                  ZoneGroup;                  /* 0x28 */
2043     U8                                  SelfConfigStatus;           /* 0x29 */
2044     U16                                 Reserved4;                  /* 0x2A */
2045 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2046   Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2047 
2048 #define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
2049 
2050 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2051 
2052 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2053 
2054 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2055 
2056 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2057 
2058 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2059 
2060 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2061 
2062 /* values for SAS Expander Page 1 DiscoveryInfo field */
2063 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
2064 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
2065 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
2066 
2067 
2068 /****************************************************************************
2069 *   SAS Device Config Pages
2070 ****************************************************************************/
2071 
2072 /* SAS Device Page 0 */
2073 
2074 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2075 {
2076     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2077     U16                                 Slot;                   /* 0x08 */
2078     U16                                 EnclosureHandle;        /* 0x0A */
2079     U64                                 SASAddress;             /* 0x0C */
2080     U16                                 ParentDevHandle;        /* 0x14 */
2081     U8                                  PhyNum;                 /* 0x16 */
2082     U8                                  AccessStatus;           /* 0x17 */
2083     U16                                 DevHandle;              /* 0x18 */
2084     U8                                  AttachedPhyIdentifier;  /* 0x1A */
2085     U8                                  ZoneGroup;              /* 0x1B */
2086     U32                                 DeviceInfo;             /* 0x1C */
2087     U16                                 Flags;                  /* 0x20 */
2088     U8                                  PhysicalPort;           /* 0x22 */
2089     U8                                  MaxPortConnections;     /* 0x23 */
2090     U64                                 DeviceName;             /* 0x24 */
2091     U8                                  PortGroups;             /* 0x2C */
2092     U8                                  DmaGroup;               /* 0x2D */
2093     U8                                  ControlGroup;           /* 0x2E */
2094     U8                                  Reserved1;              /* 0x2F */
2095     U32                                 Reserved2;              /* 0x30 */
2096     U32                                 Reserved3;              /* 0x34 */
2097 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2098   Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2099 
2100 #define MPI2_SASDEVICE0_PAGEVERSION         (0x08)
2101 
2102 /* values for SAS Device Page 0 AccessStatus field */
2103 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
2104 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
2105 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
2106 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
2107 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
2108 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
2109 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
2110 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
2111 /* specific values for SATA Init failures */
2112 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
2113 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
2114 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
2115 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
2116 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
2117 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
2118 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
2119 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
2120 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
2121 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
2122 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
2123 
2124 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2125 
2126 /* values for SAS Device Page 0 Flags field */
2127 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
2128 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
2129 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
2130 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
2131 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
2132 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
2133 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
2134 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
2135 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
2136 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
2137 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2138 
2139 
2140 /* SAS Device Page 1 */
2141 
2142 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2143 {
2144     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2145     U32                                 Reserved1;              /* 0x08 */
2146     U64                                 SASAddress;             /* 0x0C */
2147     U32                                 Reserved2;              /* 0x14 */
2148     U16                                 DevHandle;              /* 0x18 */
2149     U16                                 Reserved3;              /* 0x1A */
2150     U8                                  InitialRegDeviceFIS[20];/* 0x1C */
2151 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2152   Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2153 
2154 #define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
2155 
2156 
2157 /****************************************************************************
2158 *   SAS PHY Config Pages
2159 ****************************************************************************/
2160 
2161 /* SAS PHY Page 0 */
2162 
2163 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2164 {
2165     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2166     U16                                 OwnerDevHandle;         /* 0x08 */
2167     U16                                 Reserved1;              /* 0x0A */
2168     U16                                 AttachedDevHandle;      /* 0x0C */
2169     U8                                  AttachedPhyIdentifier;  /* 0x0E */
2170     U8                                  Reserved2;              /* 0x0F */
2171     U32                                 AttachedPhyInfo;        /* 0x10 */
2172     U8                                  ProgrammedLinkRate;     /* 0x14 */
2173     U8                                  HwLinkRate;             /* 0x15 */
2174     U8                                  ChangeCount;            /* 0x16 */
2175     U8                                  Flags;                  /* 0x17 */
2176     U32                                 PhyInfo;                /* 0x18 */
2177     U8                                  NegotiatedLinkRate;     /* 0x1C */
2178     U8                                  Reserved3;              /* 0x1D */
2179     U16                                 Reserved4;              /* 0x1E */
2180 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2181   Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2182 
2183 #define MPI2_SASPHY0_PAGEVERSION            (0x03)
2184 
2185 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2186 
2187 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2188 
2189 /* values for SAS PHY Page 0 Flags field */
2190 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
2191 
2192 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2193 
2194 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2195 
2196 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2197 
2198 
2199 /* SAS PHY Page 1 */
2200 
2201 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2202 {
2203     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2204     U32                                 Reserved1;                  /* 0x08 */
2205     U32                                 InvalidDwordCount;          /* 0x0C */
2206     U32                                 RunningDisparityErrorCount; /* 0x10 */
2207     U32                                 LossDwordSynchCount;        /* 0x14 */
2208     U32                                 PhyResetProblemCount;       /* 0x18 */
2209 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2210   Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2211 
2212 #define MPI2_SASPHY1_PAGEVERSION            (0x01)
2213 
2214 
2215 /* SAS PHY Page 2 */
2216 
2217 typedef struct _MPI2_SASPHY2_PHY_EVENT
2218 {
2219     U8          PhyEventCode;       /* 0x00 */
2220     U8          Reserved1;          /* 0x01 */
2221     U16         Reserved2;          /* 0x02 */
2222     U32         PhyEventInfo;       /* 0x04 */
2223 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2224   Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2225 
2226 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2227 
2228 
2229 /*
2230  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2231  * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2232  */
2233 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2234 #define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
2235 #endif
2236 
2237 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2
2238 {
2239     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2240     U32                                 Reserved1;                  /* 0x08 */
2241     U8                                  NumPhyEvents;               /* 0x0C */
2242     U8                                  Reserved2;                  /* 0x0D */
2243     U16                                 Reserved3;                  /* 0x0E */
2244     MPI2_SASPHY2_PHY_EVENT              PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
2245 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2246   Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2247 
2248 #define MPI2_SASPHY2_PAGEVERSION            (0x00)
2249 
2250 
2251 /* SAS PHY Page 3 */
2252 
2253 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG
2254 {
2255     U8          PhyEventCode;       /* 0x00 */
2256     U8          Reserved1;          /* 0x01 */
2257     U16         Reserved2;          /* 0x02 */
2258     U8          CounterType;        /* 0x04 */
2259     U8          ThresholdWindow;    /* 0x05 */
2260     U8          TimeUnits;          /* 0x06 */
2261     U8          Reserved3;          /* 0x07 */
2262     U32         EventThreshold;     /* 0x08 */
2263     U16         ThresholdFlags;     /* 0x0C */
2264     U16         Reserved4;          /* 0x0E */
2265 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2266   Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2267 
2268 /* values for PhyEventCode field */
2269 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
2270 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
2271 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
2272 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
2273 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
2274 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
2275 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
2276 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
2277 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
2278 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
2279 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
2280 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
2281 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
2282 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
2283 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
2284 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
2285 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
2286 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
2287 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
2288 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
2289 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
2290 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
2291 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
2292 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
2293 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
2294 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
2295 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
2296 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
2297 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
2298 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
2299 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
2300 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
2301 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
2302 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
2303 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
2304 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
2305 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
2306 
2307 /* values for the CounterType field */
2308 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
2309 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
2310 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
2311 
2312 /* values for the TimeUnits field */
2313 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
2314 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
2315 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
2316 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
2317 
2318 /* values for the ThresholdFlags field */
2319 #define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
2320 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
2321 
2322 /*
2323  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2324  * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2325  */
2326 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2327 #define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
2328 #endif
2329 
2330 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
2331 {
2332     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2333     U32                                 Reserved1;                  /* 0x08 */
2334     U8                                  NumPhyEvents;               /* 0x0C */
2335     U8                                  Reserved2;                  /* 0x0D */
2336     U16                                 Reserved3;                  /* 0x0E */
2337     MPI2_SASPHY3_PHY_EVENT_CONFIG       PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2338 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2339   Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2340 
2341 #define MPI2_SASPHY3_PAGEVERSION            (0x00)
2342 
2343 
2344 /****************************************************************************
2345 *   SAS Port Config Pages
2346 ****************************************************************************/
2347 
2348 /* SAS Port Page 0 */
2349 
2350 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2351 {
2352     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2353     U8                                  PortNumber;                 /* 0x08 */
2354     U8                                  PhysicalPort;               /* 0x09 */
2355     U8                                  PortWidth;                  /* 0x0A */
2356     U8                                  PhysicalPortWidth;          /* 0x0B */
2357     U8                                  ZoneGroup;                  /* 0x0C */
2358     U8                                  Reserved1;                  /* 0x0D */
2359     U16                                 Reserved2;                  /* 0x0E */
2360     U64                                 SASAddress;                 /* 0x10 */
2361     U32                                 DeviceInfo;                 /* 0x18 */
2362     U32                                 Reserved3;                  /* 0x1C */
2363     U32                                 Reserved4;                  /* 0x20 */
2364 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2365   Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2366 
2367 #define MPI2_SASPORT0_PAGEVERSION           (0x00)
2368 
2369 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2370 
2371 
2372 /****************************************************************************
2373 *   SAS Enclosure Config Pages
2374 ****************************************************************************/
2375 
2376 /* SAS Enclosure Page 0 */
2377 
2378 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2379 {
2380     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2381     U32                                 Reserved1;                  /* 0x08 */
2382     U64                                 EnclosureLogicalID;         /* 0x0C */
2383     U16                                 Flags;                      /* 0x14 */
2384     U16                                 EnclosureHandle;            /* 0x16 */
2385     U16                                 NumSlots;                   /* 0x18 */
2386     U16                                 StartSlot;                  /* 0x1A */
2387     U16                                 Reserved2;                  /* 0x1C */
2388     U16                                 SEPDevHandle;               /* 0x1E */
2389     U32                                 Reserved3;                  /* 0x20 */
2390     U32                                 Reserved4;                  /* 0x24 */
2391 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2392   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2393   Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2394 
2395 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x03)
2396 
2397 /* values for SAS Enclosure Page 0 Flags field */
2398 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
2399 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
2400 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
2401 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
2402 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
2403 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
2404 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
2405 
2406 
2407 /****************************************************************************
2408 *   Log Config Page
2409 ****************************************************************************/
2410 
2411 /* Log Page 0 */
2412 
2413 /*
2414  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2415  * one and check Header.ExtPageLength or NumPhys at runtime.
2416  */
2417 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2418 #define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
2419 #endif
2420 
2421 #define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
2422 
2423 typedef struct _MPI2_LOG_0_ENTRY
2424 {
2425     U64         TimeStamp;                          /* 0x00 */
2426     U32         Reserved1;                          /* 0x08 */
2427     U16         LogSequence;                        /* 0x0C */
2428     U16         LogEntryQualifier;                  /* 0x0E */
2429     U8          VP_ID;                              /* 0x10 */
2430     U8          VF_ID;                              /* 0x11 */
2431     U16         Reserved2;                          /* 0x12 */
2432     U8          LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2433 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2434   Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2435 
2436 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2437 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
2438 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
2439 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
2440 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
2441 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
2442 
2443 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2444 {
2445     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2446     U32                                 Reserved1;                  /* 0x08 */
2447     U32                                 Reserved2;                  /* 0x0C */
2448     U16                                 NumLogEntries;              /* 0x10 */
2449     U16                                 Reserved3;                  /* 0x12 */
2450     MPI2_LOG_0_ENTRY                    LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2451 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2452   Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2453 
2454 #define MPI2_LOG_0_PAGEVERSION              (0x02)
2455 
2456 
2457 /****************************************************************************
2458 *   RAID Config Page
2459 ****************************************************************************/
2460 
2461 /* RAID Page 0 */
2462 
2463 /*
2464  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2465  * one and check Header.ExtPageLength or NumPhys at runtime.
2466  */
2467 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2468 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
2469 #endif
2470 
2471 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2472 {
2473     U16                     ElementFlags;               /* 0x00 */
2474     U16                     VolDevHandle;               /* 0x02 */
2475     U8                      HotSparePool;               /* 0x04 */
2476     U8                      PhysDiskNum;                /* 0x05 */
2477     U16                     PhysDiskDevHandle;          /* 0x06 */
2478 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2479   MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2480   Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2481 
2482 /* values for the ElementFlags field */
2483 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
2484 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
2485 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
2486 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
2487 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
2488 
2489 
2490 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2491 {
2492     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2493     U8                                  NumHotSpares;               /* 0x08 */
2494     U8                                  NumPhysDisks;               /* 0x09 */
2495     U8                                  NumVolumes;                 /* 0x0A */
2496     U8                                  ConfigNum;                  /* 0x0B */
2497     U32                                 Flags;                      /* 0x0C */
2498     U8                                  ConfigGUID[24];             /* 0x10 */
2499     U32                                 Reserved1;                  /* 0x28 */
2500     U8                                  NumElements;                /* 0x2C */
2501     U8                                  Reserved2;                  /* 0x2D */
2502     U16                                 Reserved3;                  /* 0x2E */
2503     MPI2_RAIDCONFIG0_CONFIG_ELEMENT     ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2504 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2505   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2506   Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2507 
2508 #define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
2509 
2510 /* values for RAID Configuration Page 0 Flags field */
2511 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
2512 
2513 
2514 /****************************************************************************
2515 *   Driver Persistent Mapping Config Pages
2516 ****************************************************************************/
2517 
2518 /* Driver Persistent Mapping Page 0 */
2519 
2520 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2521 {
2522     U64                                 PhysicalIdentifier;         /* 0x00 */
2523     U16                                 MappingInformation;         /* 0x08 */
2524     U16                                 DeviceIndex;                /* 0x0A */
2525     U32                                 PhysicalBitsMapping;        /* 0x0C */
2526     U32                                 Reserved1;                  /* 0x10 */
2527 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2528   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2529   Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2530 
2531 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2532 {
2533     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2534     MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;                      /* 0x08 */
2535 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2536   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2537   Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2538 
2539 #define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
2540 
2541 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2542 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
2543 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
2544 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
2545 
2546 
2547 /****************************************************************************
2548 *   Ethernet Config Pages
2549 ****************************************************************************/
2550 
2551 /* Ethernet Page 0 */
2552 
2553 /* IP address (union of IPv4 and IPv6) */
2554 typedef union _MPI2_ETHERNET_IP_ADDR
2555 {
2556     U32     IPv4Addr;
2557     U32     IPv6Addr[4];
2558 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2559   Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2560 
2561 #define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
2562 
2563 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0
2564 {
2565     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2566     U8                                  NumInterfaces;          /* 0x08 */
2567     U8                                  Reserved0;              /* 0x09 */
2568     U16                                 Reserved1;              /* 0x0A */
2569     U32                                 Status;                 /* 0x0C */
2570     U8                                  MediaState;             /* 0x10 */
2571     U8                                  Reserved2;              /* 0x11 */
2572     U16                                 Reserved3;              /* 0x12 */
2573     U8                                  MacAddress[6];          /* 0x14 */
2574     U8                                  Reserved4;              /* 0x1A */
2575     U8                                  Reserved5;              /* 0x1B */
2576     MPI2_ETHERNET_IP_ADDR               IpAddress;              /* 0x1C */
2577     MPI2_ETHERNET_IP_ADDR               SubnetMask;             /* 0x2C */
2578     MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;       /* 0x3C */
2579     MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;          /* 0x4C */
2580     MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;          /* 0x5C */
2581     MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;          /* 0x6C */
2582     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2583 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2584   Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2585 
2586 #define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
2587 
2588 /* values for Ethernet Page 0 Status field */
2589 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
2590 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
2591 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
2592 #define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
2593 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
2594 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
2595 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
2596 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
2597 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
2598 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
2599 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
2600 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
2601 
2602 /* values for Ethernet Page 0 MediaState field */
2603 #define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
2604 #define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
2605 #define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
2606 
2607 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
2608 #define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
2609 #define MPI2_ETHPG0_MS_10MBIT                       (0x01)
2610 #define MPI2_ETHPG0_MS_100MBIT                      (0x02)
2611 #define MPI2_ETHPG0_MS_1GBIT                        (0x03)
2612 
2613 
2614 /* Ethernet Page 1 */
2615 
2616 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1
2617 {
2618     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2619     U32                                 Reserved0;              /* 0x08 */
2620     U32                                 Flags;                  /* 0x0C */
2621     U8                                  MediaState;             /* 0x10 */
2622     U8                                  Reserved1;              /* 0x11 */
2623     U16                                 Reserved2;              /* 0x12 */
2624     U8                                  MacAddress[6];          /* 0x14 */
2625     U8                                  Reserved3;              /* 0x1A */
2626     U8                                  Reserved4;              /* 0x1B */
2627     MPI2_ETHERNET_IP_ADDR               StaticIpAddress;        /* 0x1C */
2628     MPI2_ETHERNET_IP_ADDR               StaticSubnetMask;       /* 0x2C */
2629     MPI2_ETHERNET_IP_ADDR               StaticGatewayIpAddress; /* 0x3C */
2630     MPI2_ETHERNET_IP_ADDR               StaticDNS1IpAddress;    /* 0x4C */
2631     MPI2_ETHERNET_IP_ADDR               StaticDNS2IpAddress;    /* 0x5C */
2632     U32                                 Reserved5;              /* 0x6C */
2633     U32                                 Reserved6;              /* 0x70 */
2634     U32                                 Reserved7;              /* 0x74 */
2635     U32                                 Reserved8;              /* 0x78 */
2636     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2637 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2638   Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2639 
2640 #define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
2641 
2642 /* values for Ethernet Page 1 Flags field */
2643 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
2644 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
2645 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
2646 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
2647 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
2648 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
2649 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
2650 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
2651 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
2652 
2653 /* values for Ethernet Page 1 MediaState field */
2654 #define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
2655 #define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
2656 #define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
2657 
2658 #define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
2659 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
2660 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
2661 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
2662 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
2663 
2664 
2665 #endif
2666