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Add support for more than 8 MSI-X interrupts.
Tidy up interrupt assignement and card ID messages.
Initial modifications using the code changes present between
the LSI source code for FreeBSD drivers. Specifically the changes
between from mpslsi-source-17.00.00.00 -> mpslsi-source-03.00.00.00.
This mainly involves using a different scatter/gather element in
frame setup.
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--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas3/mpi/mpi2.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas3/mpi/mpi2.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
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13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 - * Copyright (c) 2000 to 2009, LSI Corporation.
24 - * All rights reserved.
23 + * Copyright (c) 2000-2012 LSI Corporation.
25 24 *
26 25 * Redistribution and use in source and binary forms of all code within
27 26 * this file that is exclusively owned by LSI, with or without
28 27 * modification, is permitted provided that, in addition to the CDDL 1.0
29 28 * License requirements, the following conditions are met:
30 29 *
31 30 * Neither the name of the author nor the names of its contributors may be
32 31 * used to endorse or promote products derived from this software without
33 32 * specific prior written permission.
34 33 *
35 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
38 37 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
39 38 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
40 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
41 40 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
42 41 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
43 42 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
44 43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
45 44 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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46 45 * DAMAGE.
47 46 */
48 47
49 48 /*
50 49 * Name: mpi2.h
51 50 * Title: MPI Message independent structures and definitions
52 51 * including System Interface Register Set and
53 52 * scatter/gather formats.
54 53 * Creation Date: June 21, 2006
55 54 *
56 - * mpi2.h Version: 02.00.13
55 + * mpi2.h Version: 02.00.xx
56 + *
57 + * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
58 + * prefix are for use only on MPI v2.5 products, and must not be used
59 + * with MPI v2.0 products. Unless otherwise noted, names beginning with
60 + * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
57 61 *
58 62 * Version History
59 63 * ---------------
60 64 *
61 65 * Date Version Description
62 66 * -------- -------- ------------------------------------------------------
63 67 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
64 68 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
65 69 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
66 70 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
67 71 * Moved ReplyPostHostIndex register to offset 0x6C of the
68 72 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
69 73 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
70 74 * Added union of request descriptors.
71 75 * Added union of reply descriptors.
72 76 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
73 77 * Added define for MPI2_VERSION_02_00.
74 78 * Fixed the size of the FunctionDependent5 field in the
75 79 * MPI2_DEFAULT_REPLY structure.
76 80 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
77 81 * Removed the MPI-defined Fault Codes and extended the
78 82 * product specific codes up to 0xEFFF.
79 83 * Added a sixth key value for the WriteSequence register
80 84 * and changed the flush value to 0x0.
81 85 * Added message function codes for Diagnostic Buffer Post
82 86 * and Diagnsotic Release.
83 87 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
84 88 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
85 89 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
86 90 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
87 91 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
88 92 * Added #defines for marking a reply descriptor as unused.
89 93 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
90 94 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
91 95 * Moved LUN field defines from mpi2_init.h.
92 96 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
93 97 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
94 98 * In all request and reply descriptors, replaced VF_ID
95 99 * field with MSIxIndex field.
96 100 * Removed DevHandle field from
97 101 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
98 102 * bytes reserved.
99 103 * Added RAID Accelerator functionality.
100 104 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
101 105 * --------------------------------------------------------------------------
102 106 */
103 107
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104 108 #ifndef MPI2_H
105 109 #define MPI2_H
106 110
107 111
108 112 /*****************************************************************************
109 113 *
110 114 * MPI Version Definitions
111 115 *
112 116 *****************************************************************************/
113 117
114 -#define MPI2_VERSION_MAJOR (0x02)
115 -#define MPI2_VERSION_MINOR (0x00)
116 118 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
117 119 #define MPI2_VERSION_MAJOR_SHIFT (8)
118 120 #define MPI2_VERSION_MINOR_MASK (0x00FF)
119 121 #define MPI2_VERSION_MINOR_SHIFT (0)
122 +
123 +/* major version for all MPI v2.x */
124 +#define MPI2_VERSION_MAJOR (0x02)
125 +
126 +/* minor version for MPI v2.0 compatible products */
127 +#define MPI2_VERSION_MINOR (0x00)
120 128 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
121 129 MPI2_VERSION_MINOR)
122 -
123 130 #define MPI2_VERSION_02_00 (0x0200)
124 131
125 -/* versioning for this MPI header set */
126 -#define MPI2_HEADER_VERSION_UNIT (0x0D)
132 +
133 +/* minor version for MPI v2.5 compatible products */
134 +#define MPI25_VERSION_MINOR (0x05)
135 +#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
136 + MPI25_VERSION_MINOR)
137 +#define MPI2_VERSION_02_05 (0x0205)
138 +
139 +
140 +/* Unit and Dev versioning for this MPI header set */
141 +#define MPI2_HEADER_VERSION_UNIT (0x12)
127 142 #define MPI2_HEADER_VERSION_DEV (0x00)
128 143 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
129 144 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
130 145 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
131 146 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
132 147 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
133 148
134 149
135 150 /*****************************************************************************
136 151 *
137 152 * IOC State Definitions
138 153 *
139 154 *****************************************************************************/
140 155
141 156 #define MPI2_IOC_STATE_RESET (0x00000000)
142 157 #define MPI2_IOC_STATE_READY (0x10000000)
143 158 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
144 159 #define MPI2_IOC_STATE_FAULT (0x40000000)
145 160
146 161 #define MPI2_IOC_STATE_MASK (0xF0000000)
147 162 #define MPI2_IOC_STATE_SHIFT (28)
148 163
149 164 /* Fault state range for prodcut specific codes */
150 165 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
151 166 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
152 167
153 168
154 169 /*****************************************************************************
155 170 *
156 171 * System Interface Register Definitions
157 172 *
158 173 *****************************************************************************/
159 174
160 175 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
161 176 {
162 177 U32 Doorbell; /* 0x00 */
163 178 U32 WriteSequence; /* 0x04 */
164 179 U32 HostDiagnostic; /* 0x08 */
165 180 U32 Reserved1; /* 0x0C */
166 181 U32 DiagRWData; /* 0x10 */
167 182 U32 DiagRWAddressLow; /* 0x14 */
168 183 U32 DiagRWAddressHigh; /* 0x18 */
169 184 U32 Reserved2[5]; /* 0x1C */
170 185 U32 HostInterruptStatus; /* 0x30 */
171 186 U32 HostInterruptMask; /* 0x34 */
172 187 U32 DCRData; /* 0x38 */
173 188 U32 DCRAddress; /* 0x3C */
174 189 U32 Reserved3[2]; /* 0x40 */
175 190 U32 ReplyFreeHostIndex; /* 0x48 */
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176 191 U32 Reserved4[8]; /* 0x4C */
177 192 U32 ReplyPostHostIndex; /* 0x6C */
178 193 U32 Reserved5; /* 0x70 */
179 194 U32 HCBSize; /* 0x74 */
180 195 U32 HCBAddressLow; /* 0x78 */
181 196 U32 HCBAddressHigh; /* 0x7C */
182 197 U32 Reserved6[16]; /* 0x80 */
183 198 U32 RequestDescriptorPostLow; /* 0xC0 */
184 199 U32 RequestDescriptorPostHigh; /* 0xC4 */
185 200 U32 Reserved7[14]; /* 0xC8 */
201 + U32 Reserved8[128]; /* 0x100 */
202 + U32 Reserved10[3]; /* 0x300 */
203 + U32 SuppReplyPostHostIndex[32]; /* 0x30C */
186 204 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
187 205 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
188 206
189 207 /*
190 208 * Defines for working with the Doorbell register.
191 209 */
192 210 #define MPI2_DOORBELL_OFFSET (0x00000000)
193 211
194 212 /* IOC --> System values */
195 213 #define MPI2_DOORBELL_USED (0x08000000)
196 214 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
197 215 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
198 216 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
199 217 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
200 218
201 219 /* System --> IOC values */
202 220 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
203 221 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
204 222 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
205 223 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
206 224
207 225
208 226 /*
209 227 * Defines for the WriteSequence register
210 228 */
211 229 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
212 230 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
213 231 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
214 232 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
215 233 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
216 234 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
217 235 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
218 236 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
219 237 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
220 238
221 239 /*
222 240 * Defines for the HostDiagnostic register
223 241 */
224 242 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
225 243
226 244 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
227 245 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
228 246 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
229 247
230 248 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
231 249 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
232 250 #define MPI2_DIAG_HCB_MODE (0x00000100)
233 251 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
234 252 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
235 253 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
236 254 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
237 255 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
238 256 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
239 257
240 258 /*
241 259 * Offsets for DiagRWData and address
242 260 */
243 261 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
244 262 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
245 263 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
246 264
247 265 /*
248 266 * Defines for the HostInterruptStatus register
249 267 */
250 268 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
251 269 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
252 270 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
253 271 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
254 272 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
255 273 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
256 274 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
257 275
258 276 /*
259 277 * Defines for the HostInterruptMask register
260 278 */
261 279 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
262 280 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
263 281 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
264 282 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
265 283 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
266 284 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
267 285
268 286 /*
269 287 * Offsets for DCRData and address
270 288 */
271 289 #define MPI2_DCR_DATA_OFFSET (0x00000038)
272 290 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
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273 291
274 292 /*
275 293 * Offset for the Reply Free Queue
276 294 */
277 295 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
278 296
279 297 /*
280 298 * Offset for the Reply Descriptor Post Queue
281 299 */
282 300 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
301 +#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
302 +#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
303 +#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
283 304
284 305 /*
285 306 * Defines for the HCBSize and address
286 307 */
287 308 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
288 309 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
289 310 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
290 311
291 312 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
292 313 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
293 314
294 315 /*
295 316 * Offsets for the Request Queue
296 317 */
297 318 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
298 319 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
299 320
321 +/*
322 + * Offset for the Supplimentary Host Index Base
323 + * For use with more than 8 MSI-X interrupts.
324 + */
325 +#define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
326 +
300 327
301 328 /*****************************************************************************
302 329 *
303 330 * Message Descriptors
304 331 *
305 332 *****************************************************************************/
306 333
307 334 /* Request Descriptors */
308 335
309 336 /* Default Request Descriptor */
310 337 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
311 338 {
312 339 U8 RequestFlags; /* 0x00 */
313 340 U8 MSIxIndex; /* 0x01 */
314 341 U16 SMID; /* 0x02 */
315 342 U16 LMID; /* 0x04 */
316 343 U16 DescriptorTypeDependent; /* 0x06 */
317 344 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
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318 345 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
319 346 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
320 347
321 348 /* defines for the RequestFlags field */
322 349 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
323 350 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
324 351 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
325 352 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
326 353 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
327 354 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
355 +#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
328 356
329 357 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
330 358
331 359
332 360 /* High Priority Request Descriptor */
333 361 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
334 362 {
335 363 U8 RequestFlags; /* 0x00 */
336 364 U8 MSIxIndex; /* 0x01 */
337 365 U16 SMID; /* 0x02 */
338 366 U16 LMID; /* 0x04 */
339 367 U16 Reserved1; /* 0x06 */
340 368 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
341 369 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
342 370 Mpi2HighPriorityRequestDescriptor_t,
343 371 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
344 372
345 373
346 374 /* SCSI IO Request Descriptor */
347 375 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
348 376 {
349 377 U8 RequestFlags; /* 0x00 */
350 378 U8 MSIxIndex; /* 0x01 */
351 379 U16 SMID; /* 0x02 */
352 380 U16 LMID; /* 0x04 */
353 381 U16 DevHandle; /* 0x06 */
354 382 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
355 383 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
356 384 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
357 385
358 386
359 387 /* SCSI Target Request Descriptor */
360 388 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
361 389 {
362 390 U8 RequestFlags; /* 0x00 */
363 391 U8 MSIxIndex; /* 0x01 */
364 392 U16 SMID; /* 0x02 */
365 393 U16 LMID; /* 0x04 */
366 394 U16 IoIndex; /* 0x06 */
367 395 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
368 396 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
369 397 Mpi2SCSITargetRequestDescriptor_t,
370 398 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
371 399
372 400
373 401 /* RAID Accelerator Request Descriptor */
374 402 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
375 403 {
376 404 U8 RequestFlags; /* 0x00 */
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377 405 U8 MSIxIndex; /* 0x01 */
378 406 U16 SMID; /* 0x02 */
379 407 U16 LMID; /* 0x04 */
380 408 U16 Reserved; /* 0x06 */
381 409 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
382 410 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
383 411 Mpi2RAIDAcceleratorRequestDescriptor_t,
384 412 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
385 413
386 414
415 +/* Fast Path SCSI IO Request Descriptor */
416 +typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
417 + MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
418 + MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
419 + Mpi25FastPathSCSIIORequestDescriptor_t,
420 + MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t;
421 +
422 +
387 423 /* union of Request Descriptors */
388 424 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
389 425 {
390 426 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
391 427 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
392 428 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
393 429 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
394 430 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
431 + MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
395 432 U64 Words;
396 433 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
397 434 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
398 435
399 436
400 437 /* Reply Descriptors */
401 438
402 439 /* Default Reply Descriptor */
403 440 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
404 441 {
405 442 U8 ReplyFlags; /* 0x00 */
406 443 U8 MSIxIndex; /* 0x01 */
407 444 U16 DescriptorTypeDependent1; /* 0x02 */
408 445 U32 DescriptorTypeDependent2; /* 0x04 */
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409 446 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
410 447 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
411 448
412 449 /* defines for the ReplyFlags field */
413 450 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
414 451 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
415 452 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
416 453 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
417 454 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
418 455 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
456 +#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
419 457 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
420 458
421 459 /* values for marking a reply descriptor as unused */
422 460 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
423 461 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
424 462
425 463 /* Address Reply Descriptor */
426 464 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
427 465 {
428 466 U8 ReplyFlags; /* 0x00 */
429 467 U8 MSIxIndex; /* 0x01 */
430 468 U16 SMID; /* 0x02 */
431 469 U32 ReplyFrameAddress; /* 0x04 */
432 470 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
433 471 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
434 472
435 473 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
436 474
437 475
438 476 /* SCSI IO Success Reply Descriptor */
439 477 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
440 478 {
441 479 U8 ReplyFlags; /* 0x00 */
442 480 U8 MSIxIndex; /* 0x01 */
443 481 U16 SMID; /* 0x02 */
444 482 U16 TaskTag; /* 0x04 */
445 483 U16 Reserved1; /* 0x06 */
446 484 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
447 485 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
448 486 Mpi2SCSIIOSuccessReplyDescriptor_t,
449 487 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
450 488
451 489
452 490 /* TargetAssist Success Reply Descriptor */
453 491 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
454 492 {
455 493 U8 ReplyFlags; /* 0x00 */
456 494 U8 MSIxIndex; /* 0x01 */
457 495 U16 SMID; /* 0x02 */
458 496 U8 SequenceNumber; /* 0x04 */
459 497 U8 Reserved1; /* 0x05 */
460 498 U16 IoIndex; /* 0x06 */
461 499 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
462 500 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
463 501 Mpi2TargetAssistSuccessReplyDescriptor_t,
464 502 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
465 503
466 504
467 505 /* Target Command Buffer Reply Descriptor */
468 506 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
469 507 {
470 508 U8 ReplyFlags; /* 0x00 */
471 509 U8 MSIxIndex; /* 0x01 */
472 510 U8 VP_ID; /* 0x02 */
473 511 U8 Flags; /* 0x03 */
474 512 U16 InitiatorDevHandle; /* 0x04 */
475 513 U16 IoIndex; /* 0x06 */
476 514 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
477 515 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
478 516 Mpi2TargetCommandBufferReplyDescriptor_t,
479 517 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
480 518
481 519 /* defines for Flags field */
482 520 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
483 521
484 522
485 523 /* RAID Accelerator Success Reply Descriptor */
486 524 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
487 525 {
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488 526 U8 ReplyFlags; /* 0x00 */
489 527 U8 MSIxIndex; /* 0x01 */
490 528 U16 SMID; /* 0x02 */
491 529 U32 Reserved; /* 0x04 */
492 530 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
493 531 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
494 532 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
495 533 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
496 534
497 535
536 +/* Fast Path SCSI IO Success Reply Descriptor */
537 +typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
538 + MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
539 + MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
540 + Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
541 + MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
542 +
543 +
498 544 /* union of Reply Descriptors */
499 545 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
500 546 {
501 547 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
502 548 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
503 549 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
504 550 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
505 551 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
506 552 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
553 + MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
507 554 U64 Words;
508 555 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
509 556 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
510 557
511 558
512 559
513 560 /*****************************************************************************
514 561 *
515 562 * Message Functions
516 563 * 0x80 -> 0x8F reserved for private message use per product
517 564 *
518 565 *
519 566 *****************************************************************************/
520 567
521 568 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
522 569 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
523 570 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
524 571 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
525 572 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
526 573 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
527 574 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
528 575 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
529 576 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
530 577 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
531 578 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
532 579 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
533 580 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
534 581 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
535 582 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
536 583 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
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537 584 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
538 585 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
539 586 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
540 587 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
541 588 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
542 589 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
543 590 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
544 591 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
545 592 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
546 593 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
594 +#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
595 +#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
596 +#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
597 +#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
547 598
548 599
549 600
550 601 /* Doorbell functions */
551 602 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
552 -/* #define MPI2_FUNCTION_IO_UNIT_RESET (0x41) */
553 603 #define MPI2_FUNCTION_HANDSHAKE (0x42)
554 604
555 605
556 606 /*****************************************************************************
557 607 *
558 608 * IOC Status Values
559 609 *
560 610 *****************************************************************************/
561 611
562 612 /* mask for IOCStatus status value */
563 613 #define MPI2_IOCSTATUS_MASK (0x7FFF)
564 614
565 615 /****************************************************************************
566 616 * Common IOCStatus values for all replies
567 617 ****************************************************************************/
568 618
569 619 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
570 620 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
571 621 #define MPI2_IOCSTATUS_BUSY (0x0002)
572 622 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
573 623 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
574 624 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
575 625 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
576 626 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
577 627 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
578 628 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
579 629
580 630 /****************************************************************************
581 631 * Config IOCStatus values
582 632 ****************************************************************************/
583 633
584 634 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
585 635 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
586 636 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
587 637 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
588 638 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
589 639 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
590 640
591 641 /****************************************************************************
592 642 * SCSI IO Reply
593 643 ****************************************************************************/
594 644
595 645 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
596 646 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
597 647 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
598 648 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
599 649 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
600 650 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
601 651 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
602 652 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
603 653 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
604 654 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
605 655 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
606 656 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
607 657
608 658 /****************************************************************************
609 659 * For use by SCSI Initiator and SCSI Target end-to-end data protection
610 660 ****************************************************************************/
611 661
612 662 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
613 663 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
614 664 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
615 665
616 666 /****************************************************************************
617 667 * SCSI Target values
618 668 ****************************************************************************/
619 669
620 670 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
621 671 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
622 672 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
623 673 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
624 674 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
625 675 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
626 676 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
627 677 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
628 678 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
629 679 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
630 680
631 681 /****************************************************************************
632 682 * Serial Attached SCSI values
633 683 ****************************************************************************/
634 684
635 685 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
636 686 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
637 687
638 688 /****************************************************************************
639 689 * Diagnostic Buffer Post / Diagnostic Release values
640 690 ****************************************************************************/
641 691
642 692 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
643 693
644 694 /****************************************************************************
645 695 * RAID Accelerator values
646 696 ****************************************************************************/
647 697
648 698 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
649 699
650 700 /****************************************************************************
651 701 * IOCStatus flag to indicate that log info is available
652 702 ****************************************************************************/
653 703
654 704 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
655 705
656 706 /****************************************************************************
657 707 * IOCLogInfo Types
658 708 ****************************************************************************/
659 709
660 710 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
661 711 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
662 712 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
663 713 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
664 714 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
665 715 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
666 716 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
667 717 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
668 718
669 719
670 720 /*****************************************************************************
671 721 *
672 722 * Standard Message Structures
673 723 *
674 724 *****************************************************************************/
675 725
676 726 /****************************************************************************
677 727 * Request Message Header for all request messages
678 728 ****************************************************************************/
679 729
680 730 typedef struct _MPI2_REQUEST_HEADER
681 731 {
682 732 U16 FunctionDependent1; /* 0x00 */
683 733 U8 ChainOffset; /* 0x02 */
684 734 U8 Function; /* 0x03 */
685 735 U16 FunctionDependent2; /* 0x04 */
686 736 U8 FunctionDependent3; /* 0x06 */
687 737 U8 MsgFlags; /* 0x07 */
688 738 U8 VP_ID; /* 0x08 */
689 739 U8 VF_ID; /* 0x09 */
690 740 U16 Reserved1; /* 0x0A */
691 741 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
692 742 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
693 743
694 744
695 745 /****************************************************************************
696 746 * Default Reply
697 747 ****************************************************************************/
698 748
699 749 typedef struct _MPI2_DEFAULT_REPLY
700 750 {
701 751 U16 FunctionDependent1; /* 0x00 */
702 752 U8 MsgLength; /* 0x02 */
703 753 U8 Function; /* 0x03 */
704 754 U16 FunctionDependent2; /* 0x04 */
705 755 U8 FunctionDependent3; /* 0x06 */
706 756 U8 MsgFlags; /* 0x07 */
707 757 U8 VP_ID; /* 0x08 */
708 758 U8 VF_ID; /* 0x09 */
709 759 U16 Reserved1; /* 0x0A */
710 760 U16 FunctionDependent5; /* 0x0C */
711 761 U16 IOCStatus; /* 0x0E */
712 762 U32 IOCLogInfo; /* 0x10 */
713 763 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
714 764 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
715 765
716 766
717 767 /* common version structure/union used in messages and configuration pages */
718 768
719 769 typedef struct _MPI2_VERSION_STRUCT
720 770 {
721 771 U8 Dev; /* 0x00 */
722 772 U8 Unit; /* 0x01 */
723 773 U8 Minor; /* 0x02 */
724 774 U8 Major; /* 0x03 */
725 775 } MPI2_VERSION_STRUCT;
726 776
727 777 typedef union _MPI2_VERSION_UNION
728 778 {
729 779 MPI2_VERSION_STRUCT Struct;
730 780 U32 Word;
731 781 } MPI2_VERSION_UNION;
732 782
733 783
734 784 /* LUN field defines, common to many structures */
735 785 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
736 786 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
737 787 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
738 788 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
739 789 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
740 790 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
741 791
742 792
743 793 /*****************************************************************************
744 794 *
745 795 * Fusion-MPT MPI Scatter Gather Elements
746 796 *
747 797 *****************************************************************************/
748 798
749 799 /****************************************************************************
750 800 * MPI Simple Element structures
751 801 ****************************************************************************/
752 802
753 803 typedef struct _MPI2_SGE_SIMPLE32
754 804 {
755 805 U32 FlagsLength;
756 806 U32 Address;
757 807 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
758 808 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
759 809
760 810 typedef struct _MPI2_SGE_SIMPLE64
761 811 {
762 812 U32 FlagsLength;
763 813 U64 Address;
764 814 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
765 815 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
766 816
767 817 typedef struct _MPI2_SGE_SIMPLE_UNION
768 818 {
769 819 U32 FlagsLength;
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770 820 union
771 821 {
772 822 U32 Address32;
773 823 U64 Address64;
774 824 } u;
775 825 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
776 826 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
777 827
778 828
779 829 /****************************************************************************
780 -* MPI Chain Element structures
830 +* MPI Chain Element structures - for MPI v2.0 products only
781 831 ****************************************************************************/
782 832
783 833 typedef struct _MPI2_SGE_CHAIN32
784 834 {
785 835 U16 Length;
786 836 U8 NextChainOffset;
787 837 U8 Flags;
788 838 U32 Address;
789 839 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
790 840 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
791 841
792 842 typedef struct _MPI2_SGE_CHAIN64
793 843 {
794 844 U16 Length;
795 845 U8 NextChainOffset;
796 846 U8 Flags;
797 847 U64 Address;
798 848 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
799 849 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
800 850
801 851 typedef struct _MPI2_SGE_CHAIN_UNION
802 852 {
803 853 U16 Length;
804 854 U8 NextChainOffset;
805 855 U8 Flags;
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806 856 union
807 857 {
808 858 U32 Address32;
809 859 U64 Address64;
810 860 } u;
811 861 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
812 862 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
813 863
814 864
815 865 /****************************************************************************
816 -* MPI Transaction Context Element structures
866 +* MPI Transaction Context Element structures - for MPI v2.0 products only
817 867 ****************************************************************************/
818 868
819 869 typedef struct _MPI2_SGE_TRANSACTION32
820 870 {
821 871 U8 Reserved;
822 872 U8 ContextSize;
823 873 U8 DetailsLength;
824 874 U8 Flags;
825 875 U32 TransactionContext[1];
826 876 U32 TransactionDetails[1];
827 877 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
828 878 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
829 879
830 880 typedef struct _MPI2_SGE_TRANSACTION64
831 881 {
832 882 U8 Reserved;
833 883 U8 ContextSize;
834 884 U8 DetailsLength;
835 885 U8 Flags;
836 886 U32 TransactionContext[2];
837 887 U32 TransactionDetails[1];
838 888 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
839 889 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
840 890
841 891 typedef struct _MPI2_SGE_TRANSACTION96
842 892 {
843 893 U8 Reserved;
844 894 U8 ContextSize;
845 895 U8 DetailsLength;
846 896 U8 Flags;
847 897 U32 TransactionContext[3];
848 898 U32 TransactionDetails[1];
849 899 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
850 900 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
851 901
852 902 typedef struct _MPI2_SGE_TRANSACTION128
853 903 {
854 904 U8 Reserved;
855 905 U8 ContextSize;
856 906 U8 DetailsLength;
857 907 U8 Flags;
858 908 U32 TransactionContext[4];
859 909 U32 TransactionDetails[1];
860 910 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
861 911 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
862 912
863 913 typedef struct _MPI2_SGE_TRANSACTION_UNION
864 914 {
865 915 U8 Reserved;
866 916 U8 ContextSize;
867 917 U8 DetailsLength;
868 918 U8 Flags;
869 919 union
870 920 {
871 921 U32 TransactionContext32[1];
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872 922 U32 TransactionContext64[2];
873 923 U32 TransactionContext96[3];
874 924 U32 TransactionContext128[4];
875 925 } u;
876 926 U32 TransactionDetails[1];
877 927 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
878 928 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
879 929
880 930
881 931 /****************************************************************************
882 -* MPI SGE union for IO SGL's
932 +* MPI SGE union for IO SGL's - for MPI v2.0 products only
883 933 ****************************************************************************/
884 934
885 935 typedef struct _MPI2_MPI_SGE_IO_UNION
886 936 {
887 937 union
888 938 {
889 939 MPI2_SGE_SIMPLE_UNION Simple;
890 940 MPI2_SGE_CHAIN_UNION Chain;
891 941 } u;
892 942 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
893 943 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
894 944
895 945
896 946 /****************************************************************************
897 -* MPI SGE union for SGL's with Simple and Transaction elements
947 +* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
898 948 ****************************************************************************/
899 949
900 950 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
901 951 {
902 952 union
903 953 {
904 954 MPI2_SGE_SIMPLE_UNION Simple;
905 955 MPI2_SGE_TRANSACTION_UNION Transaction;
906 956 } u;
907 957 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
908 958 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
909 959
910 960
911 961 /****************************************************************************
912 962 * All MPI SGE types union
913 963 ****************************************************************************/
914 964
915 965 typedef struct _MPI2_MPI_SGE_UNION
916 966 {
917 967 union
918 968 {
919 969 MPI2_SGE_SIMPLE_UNION Simple;
920 970 MPI2_SGE_CHAIN_UNION Chain;
921 971 MPI2_SGE_TRANSACTION_UNION Transaction;
922 972 } u;
923 973 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
924 974 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
925 975
926 976
927 977 /****************************************************************************
928 978 * MPI SGE field definition and masks
929 979 ****************************************************************************/
930 980
931 981 /* Flags field bit definitions */
932 982
933 983 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
934 984 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
935 985 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
936 986 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
937 987 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
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938 988 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
939 989 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
940 990
941 991 #define MPI2_SGE_FLAGS_SHIFT (24)
942 992
943 993 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
944 994 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
945 995
946 996 /* Element Type */
947 997
948 -#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
998 +#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */
949 999 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
950 -#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
1000 +#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */
951 1001 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
952 1002
953 1003 /* Address location */
954 1004
955 1005 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
956 1006
957 1007 /* Direction */
958 1008
959 1009 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
960 1010 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
961 1011
1012 +#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1013 +#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1014 +
962 1015 /* Address Size */
963 1016
964 1017 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
965 1018 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
966 1019
967 1020 /* Context Size */
968 1021
969 1022 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
970 1023 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
971 1024 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
972 1025 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
973 1026
974 1027 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
975 1028 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
976 1029
977 1030 /****************************************************************************
978 1031 * MPI SGE operation Macros
979 1032 ****************************************************************************/
980 1033
981 1034 /* SIMPLE FlagsLength manipulations... */
982 1035 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
983 1036 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
984 1037 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
985 1038 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
986 1039
987 1040 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
988 1041
989 1042 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
990 1043 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
991 1044 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
992 1045
993 1046 /* CAUTION - The following are READ-MODIFY-WRITE! */
994 1047 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
995 1048 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
996 1049
997 1050 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
998 1051
999 1052
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1000 1053 /*****************************************************************************
1001 1054 *
1002 1055 * Fusion-MPT IEEE Scatter Gather Elements
1003 1056 *
1004 1057 *****************************************************************************/
1005 1058
1006 1059 /****************************************************************************
1007 1060 * IEEE Simple Element structures
1008 1061 ****************************************************************************/
1009 1062
1063 +/* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1010 1064 typedef struct _MPI2_IEEE_SGE_SIMPLE32
1011 1065 {
1012 1066 U32 Address;
1013 1067 U32 FlagsLength;
1014 1068 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1015 1069 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1016 1070
1017 1071 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1018 1072 {
1019 1073 U64 Address;
1020 1074 U32 Length;
1021 1075 U16 Reserved1;
1022 1076 U8 Reserved2;
1023 1077 U8 Flags;
1024 1078 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1025 1079 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1026 1080
1027 1081 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1028 1082 {
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1029 1083 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1030 1084 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1031 1085 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1032 1086 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1033 1087
1034 1088
1035 1089 /****************************************************************************
1036 1090 * IEEE Chain Element structures
1037 1091 ****************************************************************************/
1038 1092
1093 +/* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1039 1094 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1040 1095
1096 +/* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1041 1097 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1042 1098
1043 1099 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1044 1100 {
1045 1101 MPI2_IEEE_SGE_CHAIN32 Chain32;
1046 1102 MPI2_IEEE_SGE_CHAIN64 Chain64;
1047 1103 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1048 1104 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1049 1105
1106 +/* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */
1107 +typedef struct _MPI25_IEEE_SGE_CHAIN64
1108 +{
1109 + U64 Address;
1110 + U32 Length;
1111 + U16 Reserved1;
1112 + U8 NextChainOffset;
1113 + U8 Flags;
1114 +} MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
1115 + Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
1116 +
1050 1117
1051 1118 /****************************************************************************
1052 1119 * All IEEE SGE types union
1053 1120 ****************************************************************************/
1054 1121
1122 +/* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1055 1123 typedef struct _MPI2_IEEE_SGE_UNION
1056 1124 {
1057 1125 union
1058 1126 {
1059 1127 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1060 1128 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1061 1129 } u;
1062 1130 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1063 1131 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1064 1132
1065 1133
1066 1134 /****************************************************************************
1135 +* IEEE SGE union for IO SGL's
1136 +****************************************************************************/
1137 +
1138 +typedef union _MPI25_SGE_IO_UNION
1139 +{
1140 + MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1141 + MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1142 +} MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION,
1143 + Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t;
1144 +
1145 +
1146 +/****************************************************************************
1067 1147 * IEEE SGE field definitions and masks
1068 1148 ****************************************************************************/
1069 1149
1070 1150 /* Flags field bit definitions */
1071 1151
1072 1152 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1153 +#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1073 1154
1074 1155 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1075 1156
1076 1157 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1077 1158
1078 1159 /* Element Type */
1079 1160
1080 1161 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1081 1162 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1082 1163
1083 1164 /* Data Location Address Space */
1084 1165
1085 1166 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1086 -#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1087 -#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1167 +#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* IEEE Simple Element only */
1168 +#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* IEEE Simple Element only */
1088 1169 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1089 -#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1170 +#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* IEEE Simple Element only */
1171 +#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (0x03) /* IEEE Chain Element only */
1090 1172
1091 1173
1092 1174 /****************************************************************************
1093 1175 * IEEE SGE operation Macros
1094 1176 ****************************************************************************/
1095 1177
1096 1178 /* SIMPLE FlagsLength manipulations... */
1097 1179 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1098 1180 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1099 1181 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1100 1182
1101 1183 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1102 1184
1103 1185 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1104 1186 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1105 1187 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1106 1188
1107 1189 /* CAUTION - The following are READ-MODIFY-WRITE! */
1108 1190 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1109 1191 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1110 1192
1111 1193
1112 1194
1113 1195
1114 1196 /*****************************************************************************
1115 1197 *
1116 1198 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1117 1199 *
1118 1200 *****************************************************************************/
1119 1201
1120 1202 typedef union _MPI2_SIMPLE_SGE_UNION
1121 1203 {
1122 1204 MPI2_SGE_SIMPLE_UNION MpiSimple;
1123 1205 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1124 1206 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1125 1207 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1126 1208
1127 1209
1128 1210 typedef union _MPI2_SGE_IO_UNION
1129 1211 {
1130 1212 MPI2_SGE_SIMPLE_UNION MpiSimple;
1131 1213 MPI2_SGE_CHAIN_UNION MpiChain;
1132 1214 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1133 1215 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1134 1216 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1135 1217 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1136 1218
1137 1219
1138 1220 /****************************************************************************
1139 1221 *
1140 1222 * Values for SGLFlags field, used in many request messages with an SGL
1141 1223 *
1142 1224 ****************************************************************************/
1143 1225
1144 1226 /* values for MPI SGL Data Location Address Space subfield */
1145 1227 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1146 1228 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1147 1229 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1148 1230 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1149 1231 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1150 1232 /* values for SGL Type subfield */
1151 1233 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1152 1234 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1153 1235 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1154 1236 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1155 1237
1156 1238
1157 1239 #endif
1158 1240
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