1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2000 to 2009, LSI Corporation.
24 * All rights reserved.
25 *
26 * Redistribution and use in source and binary forms of all code within
27 * this file that is exclusively owned by LSI, with or without
28 * modification, is permitted provided that, in addition to the CDDL 1.0
29 * License requirements, the following conditions are met:
30 *
31 * Neither the name of the author nor the names of its contributors may be
32 * used to endorse or promote products derived from this software without
33 * specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
38 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
39 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
41 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
42 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
43 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
45 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46 * DAMAGE.
47 */
48
49 /*
50 * Name: mpi2.h
51 * Title: MPI Message independent structures and definitions
52 * including System Interface Register Set and
53 * scatter/gather formats.
54 * Creation Date: June 21, 2006
55 *
56 * mpi2.h Version: 02.00.13
57 *
58 * Version History
59 * ---------------
60 *
61 * Date Version Description
62 * -------- -------- ------------------------------------------------------
63 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
64 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
65 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
66 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
67 * Moved ReplyPostHostIndex register to offset 0x6C of the
68 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
69 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
70 * Added union of request descriptors.
71 * Added union of reply descriptors.
72 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
73 * Added define for MPI2_VERSION_02_00.
74 * Fixed the size of the FunctionDependent5 field in the
75 * MPI2_DEFAULT_REPLY structure.
76 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
77 * Removed the MPI-defined Fault Codes and extended the
78 * product specific codes up to 0xEFFF.
79 * Added a sixth key value for the WriteSequence register
80 * and changed the flush value to 0x0.
81 * Added message function codes for Diagnostic Buffer Post
82 * and Diagnsotic Release.
83 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
84 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
85 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
88 * Added #defines for marking a reply descriptor as unused.
89 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
90 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
91 * Moved LUN field defines from mpi2_init.h.
92 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
93 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
94 * In all request and reply descriptors, replaced VF_ID
95 * field with MSIxIndex field.
96 * Removed DevHandle field from
97 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
98 * bytes reserved.
99 * Added RAID Accelerator functionality.
100 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
101 * --------------------------------------------------------------------------
102 */
103
104 #ifndef MPI2_H
105 #define MPI2_H
106
107
108 /*****************************************************************************
109 *
110 * MPI Version Definitions
111 *
112 *****************************************************************************/
113
114 #define MPI2_VERSION_MAJOR (0x02)
115 #define MPI2_VERSION_MINOR (0x00)
116 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
117 #define MPI2_VERSION_MAJOR_SHIFT (8)
118 #define MPI2_VERSION_MINOR_MASK (0x00FF)
119 #define MPI2_VERSION_MINOR_SHIFT (0)
120 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
121 MPI2_VERSION_MINOR)
122
123 #define MPI2_VERSION_02_00 (0x0200)
124
125 /* versioning for this MPI header set */
126 #define MPI2_HEADER_VERSION_UNIT (0x0D)
127 #define MPI2_HEADER_VERSION_DEV (0x00)
128 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
129 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
130 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
131 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
132 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
133
134
135 /*****************************************************************************
136 *
137 * IOC State Definitions
138 *
139 *****************************************************************************/
140
141 #define MPI2_IOC_STATE_RESET (0x00000000)
142 #define MPI2_IOC_STATE_READY (0x10000000)
143 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
144 #define MPI2_IOC_STATE_FAULT (0x40000000)
145
146 #define MPI2_IOC_STATE_MASK (0xF0000000)
147 #define MPI2_IOC_STATE_SHIFT (28)
148
149 /* Fault state range for prodcut specific codes */
150 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
151 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
152
153
154 /*****************************************************************************
155 *
156 * System Interface Register Definitions
157 *
158 *****************************************************************************/
159
160 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
161 {
162 U32 Doorbell; /* 0x00 */
163 U32 WriteSequence; /* 0x04 */
164 U32 HostDiagnostic; /* 0x08 */
165 U32 Reserved1; /* 0x0C */
166 U32 DiagRWData; /* 0x10 */
167 U32 DiagRWAddressLow; /* 0x14 */
168 U32 DiagRWAddressHigh; /* 0x18 */
169 U32 Reserved2[5]; /* 0x1C */
170 U32 HostInterruptStatus; /* 0x30 */
171 U32 HostInterruptMask; /* 0x34 */
172 U32 DCRData; /* 0x38 */
173 U32 DCRAddress; /* 0x3C */
174 U32 Reserved3[2]; /* 0x40 */
175 U32 ReplyFreeHostIndex; /* 0x48 */
176 U32 Reserved4[8]; /* 0x4C */
177 U32 ReplyPostHostIndex; /* 0x6C */
178 U32 Reserved5; /* 0x70 */
179 U32 HCBSize; /* 0x74 */
180 U32 HCBAddressLow; /* 0x78 */
181 U32 HCBAddressHigh; /* 0x7C */
182 U32 Reserved6[16]; /* 0x80 */
183 U32 RequestDescriptorPostLow; /* 0xC0 */
184 U32 RequestDescriptorPostHigh; /* 0xC4 */
185 U32 Reserved7[14]; /* 0xC8 */
186 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
187 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
188
189 /*
190 * Defines for working with the Doorbell register.
191 */
192 #define MPI2_DOORBELL_OFFSET (0x00000000)
193
194 /* IOC --> System values */
195 #define MPI2_DOORBELL_USED (0x08000000)
196 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
197 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
198 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
199 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
200
201 /* System --> IOC values */
202 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
203 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
204 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
205 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
206
207
208 /*
209 * Defines for the WriteSequence register
210 */
211 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
212 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
213 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
214 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
215 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
216 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
217 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
218 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
219 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
220
221 /*
222 * Defines for the HostDiagnostic register
223 */
224 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
225
226 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
227 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
228 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
229
230 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
231 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
232 #define MPI2_DIAG_HCB_MODE (0x00000100)
233 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
234 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
235 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
236 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
237 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
238 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
239
240 /*
241 * Offsets for DiagRWData and address
242 */
243 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
244 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
245 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
246
247 /*
248 * Defines for the HostInterruptStatus register
249 */
250 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
251 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
252 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
253 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
254 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
255 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
256 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
257
258 /*
259 * Defines for the HostInterruptMask register
260 */
261 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
262 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
263 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
264 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
265 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
266 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
267
268 /*
269 * Offsets for DCRData and address
270 */
271 #define MPI2_DCR_DATA_OFFSET (0x00000038)
272 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
273
274 /*
275 * Offset for the Reply Free Queue
276 */
277 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
278
279 /*
280 * Offset for the Reply Descriptor Post Queue
281 */
282 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
283
284 /*
285 * Defines for the HCBSize and address
286 */
287 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
288 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
289 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
290
291 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
292 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
293
294 /*
295 * Offsets for the Request Queue
296 */
297 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
298 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
299
300
301 /*****************************************************************************
302 *
303 * Message Descriptors
304 *
305 *****************************************************************************/
306
307 /* Request Descriptors */
308
309 /* Default Request Descriptor */
310 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
311 {
312 U8 RequestFlags; /* 0x00 */
313 U8 MSIxIndex; /* 0x01 */
314 U16 SMID; /* 0x02 */
315 U16 LMID; /* 0x04 */
316 U16 DescriptorTypeDependent; /* 0x06 */
317 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
318 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
319 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
320
321 /* defines for the RequestFlags field */
322 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
323 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
324 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
325 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
326 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
327 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
328
329 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
330
331
332 /* High Priority Request Descriptor */
333 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
334 {
335 U8 RequestFlags; /* 0x00 */
336 U8 MSIxIndex; /* 0x01 */
337 U16 SMID; /* 0x02 */
338 U16 LMID; /* 0x04 */
339 U16 Reserved1; /* 0x06 */
340 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
341 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
342 Mpi2HighPriorityRequestDescriptor_t,
343 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
344
345
346 /* SCSI IO Request Descriptor */
347 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
348 {
349 U8 RequestFlags; /* 0x00 */
350 U8 MSIxIndex; /* 0x01 */
351 U16 SMID; /* 0x02 */
352 U16 LMID; /* 0x04 */
353 U16 DevHandle; /* 0x06 */
354 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
355 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
356 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
357
358
359 /* SCSI Target Request Descriptor */
360 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
361 {
362 U8 RequestFlags; /* 0x00 */
363 U8 MSIxIndex; /* 0x01 */
364 U16 SMID; /* 0x02 */
365 U16 LMID; /* 0x04 */
366 U16 IoIndex; /* 0x06 */
367 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
368 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
369 Mpi2SCSITargetRequestDescriptor_t,
370 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
371
372
373 /* RAID Accelerator Request Descriptor */
374 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
375 {
376 U8 RequestFlags; /* 0x00 */
377 U8 MSIxIndex; /* 0x01 */
378 U16 SMID; /* 0x02 */
379 U16 LMID; /* 0x04 */
380 U16 Reserved; /* 0x06 */
381 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
382 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
383 Mpi2RAIDAcceleratorRequestDescriptor_t,
384 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
385
386
387 /* union of Request Descriptors */
388 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
389 {
390 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
391 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
392 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
393 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
394 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
395 U64 Words;
396 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
397 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
398
399
400 /* Reply Descriptors */
401
402 /* Default Reply Descriptor */
403 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
404 {
405 U8 ReplyFlags; /* 0x00 */
406 U8 MSIxIndex; /* 0x01 */
407 U16 DescriptorTypeDependent1; /* 0x02 */
408 U32 DescriptorTypeDependent2; /* 0x04 */
409 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
410 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
411
412 /* defines for the ReplyFlags field */
413 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
414 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
415 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
416 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
417 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
418 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
419 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
420
421 /* values for marking a reply descriptor as unused */
422 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
423 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
424
425 /* Address Reply Descriptor */
426 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
427 {
428 U8 ReplyFlags; /* 0x00 */
429 U8 MSIxIndex; /* 0x01 */
430 U16 SMID; /* 0x02 */
431 U32 ReplyFrameAddress; /* 0x04 */
432 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
433 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
434
435 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
436
437
438 /* SCSI IO Success Reply Descriptor */
439 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
440 {
441 U8 ReplyFlags; /* 0x00 */
442 U8 MSIxIndex; /* 0x01 */
443 U16 SMID; /* 0x02 */
444 U16 TaskTag; /* 0x04 */
445 U16 Reserved1; /* 0x06 */
446 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
447 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
448 Mpi2SCSIIOSuccessReplyDescriptor_t,
449 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
450
451
452 /* TargetAssist Success Reply Descriptor */
453 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
454 {
455 U8 ReplyFlags; /* 0x00 */
456 U8 MSIxIndex; /* 0x01 */
457 U16 SMID; /* 0x02 */
458 U8 SequenceNumber; /* 0x04 */
459 U8 Reserved1; /* 0x05 */
460 U16 IoIndex; /* 0x06 */
461 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
462 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
463 Mpi2TargetAssistSuccessReplyDescriptor_t,
464 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
465
466
467 /* Target Command Buffer Reply Descriptor */
468 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
469 {
470 U8 ReplyFlags; /* 0x00 */
471 U8 MSIxIndex; /* 0x01 */
472 U8 VP_ID; /* 0x02 */
473 U8 Flags; /* 0x03 */
474 U16 InitiatorDevHandle; /* 0x04 */
475 U16 IoIndex; /* 0x06 */
476 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
477 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
478 Mpi2TargetCommandBufferReplyDescriptor_t,
479 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
480
481 /* defines for Flags field */
482 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
483
484
485 /* RAID Accelerator Success Reply Descriptor */
486 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
487 {
488 U8 ReplyFlags; /* 0x00 */
489 U8 MSIxIndex; /* 0x01 */
490 U16 SMID; /* 0x02 */
491 U32 Reserved; /* 0x04 */
492 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
493 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
494 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
495 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
496
497
498 /* union of Reply Descriptors */
499 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
500 {
501 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
502 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
503 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
504 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
505 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
506 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
507 U64 Words;
508 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
509 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
510
511
512
513 /*****************************************************************************
514 *
515 * Message Functions
516 * 0x80 -> 0x8F reserved for private message use per product
517 *
518 *
519 *****************************************************************************/
520
521 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
522 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
523 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
524 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
525 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
526 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
527 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
528 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
529 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
530 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
531 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
532 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
533 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
534 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
535 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
536 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
537 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
538 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
539 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
540 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
541 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
542 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
543 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
544 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
545 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
546 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
547
548
549
550 /* Doorbell functions */
551 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
552 /* #define MPI2_FUNCTION_IO_UNIT_RESET (0x41) */
553 #define MPI2_FUNCTION_HANDSHAKE (0x42)
554
555
556 /*****************************************************************************
557 *
558 * IOC Status Values
559 *
560 *****************************************************************************/
561
562 /* mask for IOCStatus status value */
563 #define MPI2_IOCSTATUS_MASK (0x7FFF)
564
565 /****************************************************************************
566 * Common IOCStatus values for all replies
567 ****************************************************************************/
568
569 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
570 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
571 #define MPI2_IOCSTATUS_BUSY (0x0002)
572 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
573 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
574 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
575 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
576 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
577 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
578 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
579
580 /****************************************************************************
581 * Config IOCStatus values
582 ****************************************************************************/
583
584 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
585 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
586 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
587 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
588 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
589 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
590
591 /****************************************************************************
592 * SCSI IO Reply
593 ****************************************************************************/
594
595 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
596 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
597 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
598 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
599 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
600 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
601 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
602 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
603 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
604 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
605 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
606 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
607
608 /****************************************************************************
609 * For use by SCSI Initiator and SCSI Target end-to-end data protection
610 ****************************************************************************/
611
612 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
613 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
614 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
615
616 /****************************************************************************
617 * SCSI Target values
618 ****************************************************************************/
619
620 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
621 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
622 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
623 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
624 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
625 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
626 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
627 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
628 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
629 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
630
631 /****************************************************************************
632 * Serial Attached SCSI values
633 ****************************************************************************/
634
635 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
636 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
637
638 /****************************************************************************
639 * Diagnostic Buffer Post / Diagnostic Release values
640 ****************************************************************************/
641
642 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
643
644 /****************************************************************************
645 * RAID Accelerator values
646 ****************************************************************************/
647
648 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
649
650 /****************************************************************************
651 * IOCStatus flag to indicate that log info is available
652 ****************************************************************************/
653
654 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
655
656 /****************************************************************************
657 * IOCLogInfo Types
658 ****************************************************************************/
659
660 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
661 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
662 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
663 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
664 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
665 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
666 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
667 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
668
669
670 /*****************************************************************************
671 *
672 * Standard Message Structures
673 *
674 *****************************************************************************/
675
676 /****************************************************************************
677 * Request Message Header for all request messages
678 ****************************************************************************/
679
680 typedef struct _MPI2_REQUEST_HEADER
681 {
682 U16 FunctionDependent1; /* 0x00 */
683 U8 ChainOffset; /* 0x02 */
684 U8 Function; /* 0x03 */
685 U16 FunctionDependent2; /* 0x04 */
686 U8 FunctionDependent3; /* 0x06 */
687 U8 MsgFlags; /* 0x07 */
688 U8 VP_ID; /* 0x08 */
689 U8 VF_ID; /* 0x09 */
690 U16 Reserved1; /* 0x0A */
691 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
692 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
693
694
695 /****************************************************************************
696 * Default Reply
697 ****************************************************************************/
698
699 typedef struct _MPI2_DEFAULT_REPLY
700 {
701 U16 FunctionDependent1; /* 0x00 */
702 U8 MsgLength; /* 0x02 */
703 U8 Function; /* 0x03 */
704 U16 FunctionDependent2; /* 0x04 */
705 U8 FunctionDependent3; /* 0x06 */
706 U8 MsgFlags; /* 0x07 */
707 U8 VP_ID; /* 0x08 */
708 U8 VF_ID; /* 0x09 */
709 U16 Reserved1; /* 0x0A */
710 U16 FunctionDependent5; /* 0x0C */
711 U16 IOCStatus; /* 0x0E */
712 U32 IOCLogInfo; /* 0x10 */
713 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
714 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
715
716
717 /* common version structure/union used in messages and configuration pages */
718
719 typedef struct _MPI2_VERSION_STRUCT
720 {
721 U8 Dev; /* 0x00 */
722 U8 Unit; /* 0x01 */
723 U8 Minor; /* 0x02 */
724 U8 Major; /* 0x03 */
725 } MPI2_VERSION_STRUCT;
726
727 typedef union _MPI2_VERSION_UNION
728 {
729 MPI2_VERSION_STRUCT Struct;
730 U32 Word;
731 } MPI2_VERSION_UNION;
732
733
734 /* LUN field defines, common to many structures */
735 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
736 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
737 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
738 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
739 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
740 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
741
742
743 /*****************************************************************************
744 *
745 * Fusion-MPT MPI Scatter Gather Elements
746 *
747 *****************************************************************************/
748
749 /****************************************************************************
750 * MPI Simple Element structures
751 ****************************************************************************/
752
753 typedef struct _MPI2_SGE_SIMPLE32
754 {
755 U32 FlagsLength;
756 U32 Address;
757 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
758 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
759
760 typedef struct _MPI2_SGE_SIMPLE64
761 {
762 U32 FlagsLength;
763 U64 Address;
764 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
765 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
766
767 typedef struct _MPI2_SGE_SIMPLE_UNION
768 {
769 U32 FlagsLength;
770 union
771 {
772 U32 Address32;
773 U64 Address64;
774 } u;
775 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
776 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
777
778
779 /****************************************************************************
780 * MPI Chain Element structures
781 ****************************************************************************/
782
783 typedef struct _MPI2_SGE_CHAIN32
784 {
785 U16 Length;
786 U8 NextChainOffset;
787 U8 Flags;
788 U32 Address;
789 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
790 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
791
792 typedef struct _MPI2_SGE_CHAIN64
793 {
794 U16 Length;
795 U8 NextChainOffset;
796 U8 Flags;
797 U64 Address;
798 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
799 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
800
801 typedef struct _MPI2_SGE_CHAIN_UNION
802 {
803 U16 Length;
804 U8 NextChainOffset;
805 U8 Flags;
806 union
807 {
808 U32 Address32;
809 U64 Address64;
810 } u;
811 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
812 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
813
814
815 /****************************************************************************
816 * MPI Transaction Context Element structures
817 ****************************************************************************/
818
819 typedef struct _MPI2_SGE_TRANSACTION32
820 {
821 U8 Reserved;
822 U8 ContextSize;
823 U8 DetailsLength;
824 U8 Flags;
825 U32 TransactionContext[1];
826 U32 TransactionDetails[1];
827 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
828 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
829
830 typedef struct _MPI2_SGE_TRANSACTION64
831 {
832 U8 Reserved;
833 U8 ContextSize;
834 U8 DetailsLength;
835 U8 Flags;
836 U32 TransactionContext[2];
837 U32 TransactionDetails[1];
838 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
839 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
840
841 typedef struct _MPI2_SGE_TRANSACTION96
842 {
843 U8 Reserved;
844 U8 ContextSize;
845 U8 DetailsLength;
846 U8 Flags;
847 U32 TransactionContext[3];
848 U32 TransactionDetails[1];
849 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
850 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
851
852 typedef struct _MPI2_SGE_TRANSACTION128
853 {
854 U8 Reserved;
855 U8 ContextSize;
856 U8 DetailsLength;
857 U8 Flags;
858 U32 TransactionContext[4];
859 U32 TransactionDetails[1];
860 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
861 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
862
863 typedef struct _MPI2_SGE_TRANSACTION_UNION
864 {
865 U8 Reserved;
866 U8 ContextSize;
867 U8 DetailsLength;
868 U8 Flags;
869 union
870 {
871 U32 TransactionContext32[1];
872 U32 TransactionContext64[2];
873 U32 TransactionContext96[3];
874 U32 TransactionContext128[4];
875 } u;
876 U32 TransactionDetails[1];
877 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
878 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
879
880
881 /****************************************************************************
882 * MPI SGE union for IO SGL's
883 ****************************************************************************/
884
885 typedef struct _MPI2_MPI_SGE_IO_UNION
886 {
887 union
888 {
889 MPI2_SGE_SIMPLE_UNION Simple;
890 MPI2_SGE_CHAIN_UNION Chain;
891 } u;
892 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
893 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
894
895
896 /****************************************************************************
897 * MPI SGE union for SGL's with Simple and Transaction elements
898 ****************************************************************************/
899
900 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
901 {
902 union
903 {
904 MPI2_SGE_SIMPLE_UNION Simple;
905 MPI2_SGE_TRANSACTION_UNION Transaction;
906 } u;
907 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
908 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
909
910
911 /****************************************************************************
912 * All MPI SGE types union
913 ****************************************************************************/
914
915 typedef struct _MPI2_MPI_SGE_UNION
916 {
917 union
918 {
919 MPI2_SGE_SIMPLE_UNION Simple;
920 MPI2_SGE_CHAIN_UNION Chain;
921 MPI2_SGE_TRANSACTION_UNION Transaction;
922 } u;
923 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
924 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
925
926
927 /****************************************************************************
928 * MPI SGE field definition and masks
929 ****************************************************************************/
930
931 /* Flags field bit definitions */
932
933 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
934 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
935 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
936 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
937 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
938 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
939 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
940
941 #define MPI2_SGE_FLAGS_SHIFT (24)
942
943 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
944 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
945
946 /* Element Type */
947
948 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
949 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
950 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
951 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
952
953 /* Address location */
954
955 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
956
957 /* Direction */
958
959 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
960 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
961
962 /* Address Size */
963
964 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
965 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
966
967 /* Context Size */
968
969 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
970 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
971 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
972 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
973
974 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
975 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
976
977 /****************************************************************************
978 * MPI SGE operation Macros
979 ****************************************************************************/
980
981 /* SIMPLE FlagsLength manipulations... */
982 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
983 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
984 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
985 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
986
987 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
988
989 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
990 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
991 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
992
993 /* CAUTION - The following are READ-MODIFY-WRITE! */
994 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
995 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
996
997 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
998
999
1000 /*****************************************************************************
1001 *
1002 * Fusion-MPT IEEE Scatter Gather Elements
1003 *
1004 *****************************************************************************/
1005
1006 /****************************************************************************
1007 * IEEE Simple Element structures
1008 ****************************************************************************/
1009
1010 typedef struct _MPI2_IEEE_SGE_SIMPLE32
1011 {
1012 U32 Address;
1013 U32 FlagsLength;
1014 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1015 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1016
1017 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1018 {
1019 U64 Address;
1020 U32 Length;
1021 U16 Reserved1;
1022 U8 Reserved2;
1023 U8 Flags;
1024 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1025 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1026
1027 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1028 {
1029 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1030 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1031 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1032 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1033
1034
1035 /****************************************************************************
1036 * IEEE Chain Element structures
1037 ****************************************************************************/
1038
1039 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1040
1041 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1042
1043 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1044 {
1045 MPI2_IEEE_SGE_CHAIN32 Chain32;
1046 MPI2_IEEE_SGE_CHAIN64 Chain64;
1047 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1048 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1049
1050
1051 /****************************************************************************
1052 * All IEEE SGE types union
1053 ****************************************************************************/
1054
1055 typedef struct _MPI2_IEEE_SGE_UNION
1056 {
1057 union
1058 {
1059 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1060 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1061 } u;
1062 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1063 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1064
1065
1066 /****************************************************************************
1067 * IEEE SGE field definitions and masks
1068 ****************************************************************************/
1069
1070 /* Flags field bit definitions */
1071
1072 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1073
1074 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1075
1076 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1077
1078 /* Element Type */
1079
1080 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1081 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1082
1083 /* Data Location Address Space */
1084
1085 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1086 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1087 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1088 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1089 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1090
1091
1092 /****************************************************************************
1093 * IEEE SGE operation Macros
1094 ****************************************************************************/
1095
1096 /* SIMPLE FlagsLength manipulations... */
1097 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1098 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1099 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1100
1101 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1102
1103 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1104 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1105 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1106
1107 /* CAUTION - The following are READ-MODIFY-WRITE! */
1108 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1109 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1110
1111
1112
1113
1114 /*****************************************************************************
1115 *
1116 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1117 *
1118 *****************************************************************************/
1119
1120 typedef union _MPI2_SIMPLE_SGE_UNION
1121 {
1122 MPI2_SGE_SIMPLE_UNION MpiSimple;
1123 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1124 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1125 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1126
1127
1128 typedef union _MPI2_SGE_IO_UNION
1129 {
1130 MPI2_SGE_SIMPLE_UNION MpiSimple;
1131 MPI2_SGE_CHAIN_UNION MpiChain;
1132 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1133 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1134 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1135 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1136
1137
1138 /****************************************************************************
1139 *
1140 * Values for SGLFlags field, used in many request messages with an SGL
1141 *
1142 ****************************************************************************/
1143
1144 /* values for MPI SGL Data Location Address Space subfield */
1145 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1146 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1147 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1148 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1149 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1150 /* values for SGL Type subfield */
1151 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1152 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1153 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1154 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1155
1156
1157 #endif
1158