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Code reconciliation with other base.
hg changesets 607a5b46a793..b706c96317c3
Fix ncpus for early boot config
Purge the ack to the interrupt before exiting mptsas_intr()
Changes from code review
Optimise slot alocation through rotor and the use
of per target mutex in start path.
Update tx waitq's code.
Create 2 threads, divide the workflow and deliver
to the hardware from the threads.
Optimise mutex's and code paths.
Split out offline target code.
Test timeouts code
Add support for more than 8 MSI-X interrupts.
Tidy up interrupt assignement and card ID messages.
Enable Fast Path for capable devices.
Merge fixes for Illumos issue 4819, fix mpt_sas command timeout handling.
Tweeks debug flags.
Default to process done commands all in threads if only 1 interrupt.
Lint and cstyle fixes.
Fix problem with running against 64bit msgaddr attributes for DMA.
Default is now to run like this.
Don't take tx_waiq_mutex if draining isn't set.
Fixes for Illumos issue 4682.
Fix hang bug to do with tx_wq.
Re-arrange mptsas_poll() to disable interrupts before issuing the
command.
Improve the tx_waitq code path.
Major rework of mutexes.
During normal operation do not grab m_mutex during interrupt.
Use reply post queues instead.
Make a few variable non static so you can change in /etc/system.
Fixes to some address arithmetic using 32bit values.
Distribute command done processing around the threads.
Improved auto-request sense memory usage.
Fix for Nexenta commit 36c74113a21
OS-91 mptsas does inquiry without setting pkt_time
Add comment about testing.
Test firmware version of 2008 controllers for MSI-X Compatibility.
Re-arrange mptsas_intr() to reduce number of spurious interrupts.
Fix bug in mptsas_free_post_queue().
Change mptsas_doneq_mv() to not loop.
Should not need m_in_callback flag. It prevents concurrent
command completion processing.
Added code to support using MSI-X interrupts across multiple
reply queues. Not tested with anything other than 3008 yet.
Change output "mptsas%d" -> "mptsas3%d".
Add SAS3 specific messages (12.0Gb).
Allow over-ride for interrupt type.
Restrict pre MPI2.5 to MSI interrupts.
Allow watchdog timout to work for mptsas_smhba_setup() in attach().
Merge fixes for "4403 mpt_sas panic when pulling a drive", commit f7d0d869a9ae78d
Use MSI-X interrupts, just one for now.
Pre-allocate array for request sense buffers, similar to command frames.
No more messing about with scsi_alloc_consistent_buf().
Add rolling buffer for *all* debug messages.
Improve mdb module and seperate out into mpt_sas3.
Initial modifications using the code changes present between
the LSI source code for FreeBSD drivers. Specifically the changes
between from mpslsi-source-17.00.00.00 -> mpslsi-source-03.00.00.00.
This mainly involves using a different scatter/gather element in
frame setup.
Change some obvious references sas -> sas3.
Changes to enable driver to compile.
Header paths, object lists, etc.
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--- old/usr/src/uts/common/io/scsi/adapters/mpt_sas3/mptsas3.c
+++ new/usr/src/uts/common/io/scsi/adapters/mpt_sas3/mptsas3.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
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14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 - * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
24 + * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
25 25 * Copyright (c) 2014, Joyent, Inc. All rights reserved.
26 + * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
27 + * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved.
26 28 */
27 29
28 30 /*
29 31 * Copyright (c) 2000 to 2010, LSI Corporation.
30 32 * All rights reserved.
31 33 *
32 34 * Redistribution and use in source and binary forms of all code within
33 35 * this file that is exclusively owned by LSI, with or without
34 36 * modification, is permitted provided that, in addition to the CDDL 1.0
35 37 * License requirements, the following conditions are met:
36 38 *
37 39 * Neither the name of the author nor the names of its contributors may be
38 40 * used to endorse or promote products derived from this software without
39 41 * specific prior written permission.
40 42 *
41 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
42 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
43 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
44 46 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
45 47 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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46 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
47 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
48 50 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
49 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
50 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
51 53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
52 54 * DAMAGE.
53 55 */
54 56
55 57 /*
56 - * mptsas - This is a driver based on LSI Logic's MPT2.0 interface.
58 + * mptsas3 - This is a driver based on LSI Logic's MPT2.0/2.5 interface.
57 59 *
58 60 */
59 61
60 62 #if defined(lint) || defined(DEBUG)
61 63 #define MPTSAS_DEBUG
62 64 #endif
63 65
64 66 /*
65 67 * standard header files.
66 68 */
67 69 #include <sys/note.h>
68 70 #include <sys/scsi/scsi.h>
69 71 #include <sys/pci.h>
70 72 #include <sys/file.h>
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71 73 #include <sys/policy.h>
72 74 #include <sys/model.h>
73 75 #include <sys/sysevent.h>
74 76 #include <sys/sysevent/eventdefs.h>
75 77 #include <sys/sysevent/dr.h>
76 78 #include <sys/sata/sata_defs.h>
77 79 #include <sys/scsi/generic/sas.h>
78 80 #include <sys/scsi/impl/scsi_sas.h>
79 81
80 82 #pragma pack(1)
81 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
82 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
83 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
84 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
85 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
86 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
87 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
88 -#include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
83 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_type.h>
84 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2.h>
85 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_cnfg.h>
86 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_init.h>
87 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_ioc.h>
88 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_sas.h>
89 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_tool.h>
90 +#include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_raid.h>
89 91 #pragma pack()
90 92
91 93 /*
92 94 * private header files.
93 95 *
94 96 */
95 97 #include <sys/scsi/impl/scsi_reset_notify.h>
96 -#include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
97 -#include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
98 -#include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
99 -#include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
98 +#include <sys/scsi/adapters/mpt_sas3/mptsas3_var.h>
99 +#include <sys/scsi/adapters/mpt_sas3/mptsas3_ioctl.h>
100 +#include <sys/scsi/adapters/mpt_sas3/mptsas3_smhba.h>
101 +#include <sys/scsi/adapters/mpt_sas3/mptsas3_hash.h>
100 102 #include <sys/raidioctl.h>
101 103
102 104 #include <sys/fs/dv_node.h> /* devfs_clean */
103 105
104 106 /*
105 107 * FMA header files
106 108 */
107 109 #include <sys/ddifm.h>
108 110 #include <sys/fm/protocol.h>
109 111 #include <sys/fm/util.h>
110 112 #include <sys/fm/io/ddi.h>
111 113
112 114 /*
113 115 * autoconfiguration data and routines.
114 116 */
115 117 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
116 118 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
117 119 static int mptsas_power(dev_info_t *dip, int component, int level);
118 120
119 121 /*
120 122 * cb_ops function
121 123 */
122 124 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
123 125 cred_t *credp, int *rval);
124 126 #ifdef __sparc
125 127 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
126 128 #else /* __sparc */
127 129 static int mptsas_quiesce(dev_info_t *devi);
128 130 #endif /* __sparc */
129 131
130 132 /*
131 133 * Resource initilaization for hardware
132 134 */
133 135 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
134 136 static void mptsas_disable_bus_master(mptsas_t *mpt);
135 137 static void mptsas_hba_fini(mptsas_t *mpt);
136 138 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
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137 139 static int mptsas_hba_setup(mptsas_t *mpt);
138 140 static void mptsas_hba_teardown(mptsas_t *mpt);
139 141 static int mptsas_config_space_init(mptsas_t *mpt);
140 142 static void mptsas_config_space_fini(mptsas_t *mpt);
141 143 static void mptsas_iport_register(mptsas_t *mpt);
142 144 static int mptsas_smp_setup(mptsas_t *mpt);
143 145 static void mptsas_smp_teardown(mptsas_t *mpt);
144 146 static int mptsas_cache_create(mptsas_t *mpt);
145 147 static void mptsas_cache_destroy(mptsas_t *mpt);
146 148 static int mptsas_alloc_request_frames(mptsas_t *mpt);
149 +static int mptsas_alloc_sense_bufs(mptsas_t *mpt);
147 150 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
148 151 static int mptsas_alloc_free_queue(mptsas_t *mpt);
149 152 static int mptsas_alloc_post_queue(mptsas_t *mpt);
153 +static void mptsas_free_post_queue(mptsas_t *mpt);
150 154 static void mptsas_alloc_reply_args(mptsas_t *mpt);
151 155 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
152 156 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
153 157 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
154 158
155 159 /*
156 160 * SCSA function prototypes
157 161 */
158 162 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
159 163 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
160 164 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
161 165 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
162 166 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
163 167 int tgtonly);
164 168 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
165 169 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
166 170 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
167 171 int tgtlen, int flags, int (*callback)(), caddr_t arg);
168 172 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
169 173 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
170 174 struct scsi_pkt *pkt);
171 175 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
172 176 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
173 177 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
174 178 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
175 179 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
176 180 void (*callback)(caddr_t), caddr_t arg);
177 181 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
178 182 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
179 183 static int mptsas_scsi_quiesce(dev_info_t *dip);
180 184 static int mptsas_scsi_unquiesce(dev_info_t *dip);
181 185 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
182 186 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
183 187
184 188 /*
185 189 * SMP functions
186 190 */
187 191 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
188 192
189 193 /*
190 194 * internal function prototypes.
191 195 */
192 196 static void mptsas_list_add(mptsas_t *mpt);
193 197 static void mptsas_list_del(mptsas_t *mpt);
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194 198
195 199 static int mptsas_quiesce_bus(mptsas_t *mpt);
196 200 static int mptsas_unquiesce_bus(mptsas_t *mpt);
197 201
198 202 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
199 203 static void mptsas_free_handshake_msg(mptsas_t *mpt);
200 204
201 205 static void mptsas_ncmds_checkdrain(void *arg);
202 206
203 207 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
204 -static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
205 -static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
206 -static void mptsas_accept_tx_waitq(mptsas_t *mpt);
208 +static void mptsas_retry_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
209 +static int mptsas_save_cmd_to_slot(mptsas_t *mpt, mptsas_cmd_t *cmd);
210 +static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp,
211 + int *tran_rval);
212 +static void mptsas_accept_tx_waitqs(mptsas_t *mpt);
213 +static void mptsas_unblock_tx_waitqs(mptsas_t *mpt);
214 +static void mptsas_drain_tx_waitq(mptsas_t *mpt, mptsas_tx_waitqueue_t *txwq);
215 +static int mptsas_check_targ_intxtion(mptsas_target_t *ptgt, int cmd_pkt_flags);
207 216
208 217 static int mptsas_do_detach(dev_info_t *dev);
209 218 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
210 219 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
211 220 struct scsi_pkt *pkt);
212 221 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
213 222
214 223 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
215 224 static void mptsas_handle_event(void *args);
216 225 static int mptsas_handle_event_sync(void *args);
217 226 static void mptsas_handle_dr(void *args);
218 227 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
219 228 dev_info_t *pdip);
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220 229
221 230 static void mptsas_restart_cmd(void *);
222 231
223 232 static void mptsas_flush_hba(mptsas_t *mpt);
224 233 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
225 234 uint8_t tasktype);
226 235 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
227 236 uchar_t reason, uint_t stat);
228 237
229 238 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
230 -static void mptsas_process_intr(mptsas_t *mpt,
239 +static void mptsas_process_intr(mptsas_t *mpt, mptsas_reply_pqueue_t *rpqp,
231 240 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
232 241 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
233 - pMpi2ReplyDescriptorsUnion_t reply_desc);
242 + mptsas_reply_pqueue_t *rpqp, pMpi2ReplyDescriptorsUnion_t reply_desc);
234 243 static void mptsas_handle_address_reply(mptsas_t *mpt,
235 244 pMpi2ReplyDescriptorsUnion_t reply_desc);
236 245 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
237 246 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
238 247 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
239 248
240 249 static void mptsas_watch(void *arg);
241 250 static void mptsas_watchsubr(mptsas_t *mpt);
242 -static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl);
251 +static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt);
243 252
244 253 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
245 254 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
246 255 uint8_t *data, uint32_t request_size, uint32_t reply_size,
247 - uint32_t data_size, uint32_t direction, uint8_t *dataout,
256 + uint32_t data_size, uint8_t direction, uint8_t *dataout,
248 257 uint32_t dataout_size, short timeout, int mode);
249 258 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
250 259
251 260 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
252 261 uint32_t unique_id);
253 262 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
254 263 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
255 264 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
256 265 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
257 266 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
258 267 uint32_t diag_type);
259 268 static int mptsas_diag_register(mptsas_t *mpt,
260 269 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
261 270 static int mptsas_diag_unregister(mptsas_t *mpt,
262 271 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
263 272 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
264 273 uint32_t *return_code);
265 274 static int mptsas_diag_read_buffer(mptsas_t *mpt,
266 275 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
267 276 uint32_t *return_code, int ioctl_mode);
268 277 static int mptsas_diag_release(mptsas_t *mpt,
269 278 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
270 279 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
271 280 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
272 281 int ioctl_mode);
273 282 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
274 283 int mode);
275 284
276 285 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
277 286 int cmdlen, int tgtlen, int statuslen, int kf);
278 287 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
279 288
280 289 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
281 290 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
282 291
283 292 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
284 293 int kmflags);
285 294 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
286 295
287 296 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
288 297 mptsas_cmd_t *cmd);
289 298 static void mptsas_check_task_mgt(mptsas_t *mpt,
290 299 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
291 300 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
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292 301 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
293 302 int *resid);
294 303
295 304 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
296 305 static void mptsas_free_active_slots(mptsas_t *mpt);
297 306 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
298 307
299 308 static void mptsas_restart_hba(mptsas_t *mpt);
300 309 static void mptsas_restart_waitq(mptsas_t *mpt);
301 310
302 -static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
311 +static void mptsas_deliver_doneq_thread(mptsas_t *mpt,
312 + mptsas_done_list_t *dlist);
303 313 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
304 -static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
314 +static void mptsas_rpdoneq_add(mptsas_t *mpt, mptsas_reply_pqueue_t *rpqp,
315 + mptsas_cmd_t *cmd);
316 +static void mptsas_doneq_mv(mptsas_done_list_t *from,
317 + mptsas_doneq_thread_list_t *item);
305 318
306 319 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
307 320 static void mptsas_doneq_empty(mptsas_t *mpt);
308 -static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
321 +static void mptsas_rpdoneq_empty(mptsas_reply_pqueue_t *rpqp);
322 +static void mptsas_doneq_thread(mptsas_thread_arg_t *arg);
323 +static void mptsas_tx_waitq_thread(mptsas_thread_arg_t *arg);
309 324
310 325 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
311 326 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
312 -static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt);
313 -static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
314 -
315 327
316 328 static void mptsas_start_watch_reset_delay();
317 329 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
318 330 static void mptsas_watch_reset_delay(void *arg);
319 331 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
332 +static void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt,
333 + int what);
334 +static void mptsas_set_throttle_mtx(struct mptsas *mpt, mptsas_target_t *ptgt,
335 + int what);
336 +static void mptsas_remove_cmd_nomtx(mptsas_t *mpt, mptsas_cmd_t *cmd);
320 337
321 338 /*
322 339 * helper functions
323 340 */
324 341 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
325 342
326 343 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
327 344 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
328 345 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
329 346 int lun);
330 347 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
331 348 int lun);
332 349 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
333 350 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
334 351
335 352 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
336 353 int *lun);
337 354 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
338 355
339 356 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt,
340 357 mptsas_phymask_t phymask, uint8_t phy);
341 358 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt,
342 359 mptsas_phymask_t phymask, uint64_t wwid);
343 360 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt,
344 361 mptsas_phymask_t phymask, uint64_t wwid);
345 362
346 363 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
347 364 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
348 365
349 366 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
350 367 uint16_t *handle, mptsas_target_t **pptgt);
351 368 static void mptsas_update_phymask(mptsas_t *mpt);
352 369
353 370 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
354 371 uint32_t *status, uint8_t cmd);
355 372 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
356 373 mptsas_phymask_t *phymask);
357 374 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
358 375 mptsas_phymask_t phymask);
359 376 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt);
360 377
361 378
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362 379 /*
363 380 * Enumeration / DR functions
364 381 */
365 382 static void mptsas_config_all(dev_info_t *pdip);
366 383 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
367 384 dev_info_t **lundip);
368 385 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
369 386 dev_info_t **lundip);
370 387
371 388 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
372 -static int mptsas_offline_target(dev_info_t *pdip, char *name);
389 +static int mptsas_offline_targetdev(dev_info_t *pdip, char *name);
390 +static void mptsas_offline_target(mptsas_t *mpt, mptsas_target_t *ptgt,
391 + uint8_t topo_flags, dev_info_t *parent);
373 392
374 393 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
375 394 dev_info_t **dip);
376 395
377 396 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
378 397 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
379 398 dev_info_t **dip, mptsas_target_t *ptgt);
380 399
381 400 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
382 401 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
383 402
384 403 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
385 404 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
386 405 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
387 406 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
388 407 int lun);
389 408
390 409 static void mptsas_offline_missed_luns(dev_info_t *pdip,
391 410 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
392 411 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
393 412 mdi_pathinfo_t *rpip, uint_t flags);
394 413
395 414 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
396 415 dev_info_t **smp_dip);
397 416 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
398 417 uint_t flags);
399 418
400 419 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
401 420 int mode, int *rval);
402 421 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
403 422 int mode, int *rval);
404 423 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
405 424 int mode, int *rval);
406 425 static void mptsas_record_event(void *args);
407 426 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
408 427 int mode);
409 428
410 429 mptsas_target_t *mptsas_tgt_alloc(mptsas_t *, uint16_t, uint64_t,
411 430 uint32_t, mptsas_phymask_t, uint8_t);
412 431 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *);
413 432 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
414 433 dev_info_t **smp_dip);
415 434
416 435 /*
417 436 * Power management functions
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418 437 */
419 438 static int mptsas_get_pci_cap(mptsas_t *mpt);
420 439 static int mptsas_init_pm(mptsas_t *mpt);
421 440
422 441 /*
423 442 * MPT MSI tunable:
424 443 *
425 444 * By default MSI is enabled on all supported platforms.
426 445 */
427 446 boolean_t mptsas_enable_msi = B_TRUE;
447 +boolean_t mptsas_enable_msix = B_TRUE;
428 448 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
429 449
450 +/*
451 + * Global switch for use of MPI2.5 FAST PATH.
452 + */
453 +boolean_t mptsas3_use_fastpath = B_TRUE;
454 +
430 455 static int mptsas_register_intrs(mptsas_t *);
431 456 static void mptsas_unregister_intrs(mptsas_t *);
432 457 static int mptsas_add_intrs(mptsas_t *, int);
433 458 static void mptsas_rem_intrs(mptsas_t *);
434 459
435 460 /*
436 461 * FMA Prototypes
437 462 */
438 463 static void mptsas_fm_init(mptsas_t *mpt);
439 464 static void mptsas_fm_fini(mptsas_t *mpt);
440 465 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
441 466
442 467 extern pri_t minclsyspri, maxclsyspri;
468 +/*
469 + * NCPUS is used to determine some optimal configurations for number
470 + * of threads created to perform specific jobs. If we are invoked because
471 + * a disk is part of the root file system ncpus may still be 1 so check
472 + * boot_ncpus as well.
473 + */
474 +extern int ncpus, boot_ncpus;
475 +#define NCPUS max(ncpus, boot_ncpus)
443 476
444 477 /*
445 478 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
446 479 * under this device that the paths to a physical device are created when
447 480 * MPxIO is used.
448 481 */
449 482 extern dev_info_t *scsi_vhci_dip;
450 483
451 484 /*
452 485 * Tunable timeout value for Inquiry VPD page 0x83
453 486 * By default the value is 30 seconds.
454 487 */
455 488 int mptsas_inq83_retry_timeout = 30;
456 489
457 490 /*
491 + * Tunable for default SCSI pkt timeout. Defaults to 5 seconds, which should
492 + * be plenty for INQUIRY and REPORT_LUNS, which are the only commands currently
493 + * issued by mptsas directly.
494 + */
495 +int mptsas_scsi_pkt_time = 5;
496 +
497 +/*
458 498 * This is used to allocate memory for message frame storage, not for
459 499 * data I/O DMA. All message frames must be stored in the first 4G of
460 500 * physical memory.
461 501 */
462 502 ddi_dma_attr_t mptsas_dma_attrs = {
463 503 DMA_ATTR_V0, /* attribute layout version */
464 504 0x0ull, /* address low - should be 0 (longlong) */
465 505 0xffffffffull, /* address high - 32-bit max range */
466 506 0x00ffffffull, /* count max - max DMA object size */
467 507 4, /* allocation alignment requirements */
468 508 0x78, /* burstsizes - binary encoded values */
469 509 1, /* minxfer - gran. of DMA engine */
470 510 0x00ffffffull, /* maxxfer - gran. of DMA engine */
471 511 0xffffffffull, /* max segment size (DMA boundary) */
472 512 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
473 513 512, /* granularity - device transfer size */
474 514 0 /* flags, set to 0 */
475 515 };
476 516
477 517 /*
478 518 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
479 519 * physical addresses are supported.)
480 520 */
481 521 ddi_dma_attr_t mptsas_dma_attrs64 = {
482 522 DMA_ATTR_V0, /* attribute layout version */
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483 523 0x0ull, /* address low - should be 0 (longlong) */
484 524 0xffffffffffffffffull, /* address high - 64-bit max */
485 525 0x00ffffffull, /* count max - max DMA object size */
486 526 4, /* allocation alignment requirements */
487 527 0x78, /* burstsizes - binary encoded values */
488 528 1, /* minxfer - gran. of DMA engine */
489 529 0x00ffffffull, /* maxxfer - gran. of DMA engine */
490 530 0xffffffffull, /* max segment size (DMA boundary) */
491 531 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
492 532 512, /* granularity - device transfer size */
493 - DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */
533 + 0 /* flags, set to 0 */
494 534 };
495 535
496 536 ddi_device_acc_attr_t mptsas_dev_attr = {
497 537 DDI_DEVICE_ATTR_V1,
498 538 DDI_STRUCTURE_LE_ACC,
499 539 DDI_STRICTORDER_ACC,
500 540 DDI_DEFAULT_ACC
501 541 };
502 542
503 543 static struct cb_ops mptsas_cb_ops = {
504 544 scsi_hba_open, /* open */
505 545 scsi_hba_close, /* close */
506 546 nodev, /* strategy */
507 547 nodev, /* print */
508 548 nodev, /* dump */
509 549 nodev, /* read */
510 550 nodev, /* write */
511 551 mptsas_ioctl, /* ioctl */
512 552 nodev, /* devmap */
513 553 nodev, /* mmap */
514 554 nodev, /* segmap */
515 555 nochpoll, /* chpoll */
516 556 ddi_prop_op, /* cb_prop_op */
517 557 NULL, /* streamtab */
518 558 D_MP, /* cb_flag */
519 559 CB_REV, /* rev */
520 560 nodev, /* aread */
521 561 nodev /* awrite */
522 562 };
523 563
524 564 static struct dev_ops mptsas_ops = {
525 565 DEVO_REV, /* devo_rev, */
526 566 0, /* refcnt */
527 567 ddi_no_info, /* info */
528 568 nulldev, /* identify */
529 569 nulldev, /* probe */
530 570 mptsas_attach, /* attach */
531 571 mptsas_detach, /* detach */
532 572 #ifdef __sparc
533 573 mptsas_reset,
534 574 #else
535 575 nodev, /* reset */
536 576 #endif /* __sparc */
537 577 &mptsas_cb_ops, /* driver operations */
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538 578 NULL, /* bus operations */
539 579 mptsas_power, /* power management */
540 580 #ifdef __sparc
541 581 ddi_quiesce_not_needed
542 582 #else
543 583 mptsas_quiesce /* quiesce */
544 584 #endif /* __sparc */
545 585 };
546 586
547 587
548 -#define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24"
588 +#define MPTSAS_MOD_STRING "MPTSAS3 HBA Driver 00.00.01"
549 589
550 590 static struct modldrv modldrv = {
551 591 &mod_driverops, /* Type of module. This one is a driver */
552 592 MPTSAS_MOD_STRING, /* Name of the module. */
553 593 &mptsas_ops, /* driver ops */
554 594 };
555 595
556 596 static struct modlinkage modlinkage = {
557 597 MODREV_1, &modldrv, NULL
558 598 };
559 599 #define TARGET_PROP "target"
560 600 #define LUN_PROP "lun"
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561 601 #define LUN64_PROP "lun64"
562 602 #define SAS_PROP "sas-mpt"
563 603 #define MDI_GUID "wwn"
564 604 #define NDI_GUID "guid"
565 605 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
566 606
567 607 /*
568 608 * Local static data
569 609 */
570 610 #if defined(MPTSAS_DEBUG)
571 -uint32_t mptsas_debug_flags = 0;
611 +uint32_t mptsas_debug_flags = 0x0;
612 +/*
613 + * Flags to ignore these messages in local debug ring buffer.
614 + * Default is to ignore the watchsubr() output which normally happens
615 + * every second.
616 + */
617 +uint32_t mptsas_dbglog_imask = 0x40000000;
618 +uint32_t mptsas_test_timeout = 0;
572 619 #endif /* defined(MPTSAS_DEBUG) */
573 620 uint32_t mptsas_debug_resets = 0;
574 621
575 622 static kmutex_t mptsas_global_mutex;
576 -static void *mptsas_state; /* soft state ptr */
623 +static void *mptsas3_state; /* soft state ptr */
577 624 static krwlock_t mptsas_global_rwlock;
578 625
579 626 static kmutex_t mptsas_log_mutex;
580 627 static char mptsas_log_buf[256];
581 628 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
582 629
583 630 static mptsas_t *mptsas_head, *mptsas_tail;
584 631 static clock_t mptsas_scsi_watchdog_tick;
585 632 static clock_t mptsas_tick;
586 633 static timeout_id_t mptsas_reset_watch;
587 634 static timeout_id_t mptsas_timeout_id;
588 635 static int mptsas_timeouts_enabled = 0;
636 +
637 +/*
638 + * Maximum number of MSI-X interrupts any instance of mptsas3 can use.
639 + * Note that if you want to increase this you may have to also bump the
640 + * value of ddi_msix_alloc_limit which defaults to 8.
641 + * Set to zero to fall back to other interrupt types.
642 + */
643 +int mptsas3_max_msix_intrs = 8;
644 +
645 +/*
646 + * Default length for extended auto request sense buffers.
647 + * All sense buffers need to be under the same alloc because there
648 + * is only one common top 32bits (of 64bits) address register.
649 + * Most requests only require 32 bytes, but some request >256.
650 + * We use rmalloc()/rmfree() on this additional memory to manage the
651 + * "extended" requests.
652 + */
653 +int mptsas_extreq_sense_bufsize = 256*64;
654 +
655 +/*
656 + * Believe that all software resrictions of having to run with DMA
657 + * attributes to limit allocation to the first 4G are removed.
658 + * However, this flag remains to enable quick switchback should suspicious
659 + * problems emerge.
660 + * Note that scsi_alloc_consistent_buf() does still adhering to allocating
661 + * 32 bit addressable memory, but we can cope if that is changed now.
662 + */
663 +int mptsas_use_64bit_msgaddr = 1;
664 +
589 665 /*
590 666 * warlock directives
591 667 */
592 668 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
593 669 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
594 670 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
595 671 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
596 672 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
597 673 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
598 674
599 675 /*
600 676 * SM - HBA statics
601 677 */
602 678 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
603 679
604 680 #ifdef MPTSAS_DEBUG
605 681 void debug_enter(char *);
606 682 #endif
607 683
608 684 /*
609 685 * Notes:
610 686 * - scsi_hba_init(9F) initializes SCSI HBA modules
611 687 * - must call scsi_hba_fini(9F) if modload() fails
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612 688 */
613 689 int
614 690 _init(void)
615 691 {
616 692 int status;
617 693 /* CONSTCOND */
618 694 ASSERT(NO_COMPETING_THREADS);
619 695
620 696 NDBG0(("_init"));
621 697
622 - status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
698 + status = ddi_soft_state_init(&mptsas3_state, MPTSAS_SIZE,
623 699 MPTSAS_INITIAL_SOFT_SPACE);
624 700 if (status != 0) {
625 701 return (status);
626 702 }
627 703
628 704 if ((status = scsi_hba_init(&modlinkage)) != 0) {
629 - ddi_soft_state_fini(&mptsas_state);
705 + ddi_soft_state_fini(&mptsas3_state);
630 706 return (status);
631 707 }
632 708
633 709 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
634 710 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
635 711 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
636 712
637 713 if ((status = mod_install(&modlinkage)) != 0) {
638 714 mutex_destroy(&mptsas_log_mutex);
639 715 rw_destroy(&mptsas_global_rwlock);
640 716 mutex_destroy(&mptsas_global_mutex);
641 - ddi_soft_state_fini(&mptsas_state);
717 + ddi_soft_state_fini(&mptsas3_state);
642 718 scsi_hba_fini(&modlinkage);
643 719 }
644 720
645 721 return (status);
646 722 }
647 723
648 724 /*
649 725 * Notes:
650 726 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
651 727 */
652 728 int
653 729 _fini(void)
654 730 {
655 731 int status;
656 732 /* CONSTCOND */
657 733 ASSERT(NO_COMPETING_THREADS);
658 734
659 735 NDBG0(("_fini"));
660 736
661 737 if ((status = mod_remove(&modlinkage)) == 0) {
662 - ddi_soft_state_fini(&mptsas_state);
738 + ddi_soft_state_fini(&mptsas3_state);
663 739 scsi_hba_fini(&modlinkage);
664 740 mutex_destroy(&mptsas_global_mutex);
665 741 rw_destroy(&mptsas_global_rwlock);
666 742 mutex_destroy(&mptsas_log_mutex);
667 743 }
668 744 return (status);
669 745 }
670 746
671 747 /*
672 748 * The loadable-module _info(9E) entry point
673 749 */
674 750 int
675 751 _info(struct modinfo *modinfop)
676 752 {
677 753 /* CONSTCOND */
678 754 ASSERT(NO_COMPETING_THREADS);
679 755 NDBG0(("mptsas _info"));
680 756
681 757 return (mod_info(&modlinkage, modinfop));
682 758 }
683 759
684 760 static int
685 761 mptsas_target_eval_devhdl(const void *op, void *arg)
686 762 {
687 763 uint16_t dh = *(uint16_t *)arg;
688 764 const mptsas_target_t *tp = op;
689 765
690 766 return ((int)tp->m_devhdl - (int)dh);
691 767 }
692 768
693 769 static int
694 770 mptsas_target_eval_slot(const void *op, void *arg)
695 771 {
696 772 mptsas_led_control_t *lcp = arg;
697 773 const mptsas_target_t *tp = op;
698 774
699 775 if (tp->m_enclosure != lcp->Enclosure)
700 776 return ((int)tp->m_enclosure - (int)lcp->Enclosure);
701 777
702 778 return ((int)tp->m_slot_num - (int)lcp->Slot);
703 779 }
704 780
705 781 static int
706 782 mptsas_target_eval_nowwn(const void *op, void *arg)
707 783 {
708 784 uint8_t phy = *(uint8_t *)arg;
709 785 const mptsas_target_t *tp = op;
710 786
711 787 if (tp->m_addr.mta_wwn != 0)
712 788 return (-1);
713 789
714 790 return ((int)tp->m_phynum - (int)phy);
715 791 }
716 792
717 793 static int
718 794 mptsas_smp_eval_devhdl(const void *op, void *arg)
719 795 {
720 796 uint16_t dh = *(uint16_t *)arg;
721 797 const mptsas_smp_t *sp = op;
722 798
723 799 return ((int)sp->m_devhdl - (int)dh);
724 800 }
725 801
726 802 static uint64_t
727 803 mptsas_target_addr_hash(const void *tp)
728 804 {
729 805 const mptsas_target_addr_t *tap = tp;
730 806
731 807 return ((tap->mta_wwn & 0xffffffffffffULL) |
732 808 ((uint64_t)tap->mta_phymask << 48));
733 809 }
734 810
735 811 static int
736 812 mptsas_target_addr_cmp(const void *a, const void *b)
737 813 {
738 814 const mptsas_target_addr_t *aap = a;
739 815 const mptsas_target_addr_t *bap = b;
740 816
741 817 if (aap->mta_wwn < bap->mta_wwn)
742 818 return (-1);
743 819 if (aap->mta_wwn > bap->mta_wwn)
744 820 return (1);
745 821 return ((int)bap->mta_phymask - (int)aap->mta_phymask);
746 822 }
747 823
748 824 static void
749 825 mptsas_target_free(void *op)
750 826 {
751 827 kmem_free(op, sizeof (mptsas_target_t));
752 828 }
753 829
754 830 static void
755 831 mptsas_smp_free(void *op)
756 832 {
757 833 kmem_free(op, sizeof (mptsas_smp_t));
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758 834 }
759 835
760 836 static void
761 837 mptsas_destroy_hashes(mptsas_t *mpt)
762 838 {
763 839 mptsas_target_t *tp;
764 840 mptsas_smp_t *sp;
765 841
766 842 for (tp = refhash_first(mpt->m_targets); tp != NULL;
767 843 tp = refhash_next(mpt->m_targets, tp)) {
844 + mutex_destroy(&tp->m_t_mutex);
768 845 refhash_remove(mpt->m_targets, tp);
769 846 }
770 847 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
771 848 sp = refhash_next(mpt->m_smp_targets, sp)) {
772 849 refhash_remove(mpt->m_smp_targets, sp);
773 850 }
774 851 refhash_destroy(mpt->m_targets);
775 852 refhash_destroy(mpt->m_smp_targets);
776 853 mpt->m_targets = NULL;
777 854 mpt->m_smp_targets = NULL;
778 855 }
779 856
780 857 static int
781 858 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
782 859 {
783 860 dev_info_t *pdip;
784 861 mptsas_t *mpt;
785 862 scsi_hba_tran_t *hba_tran;
786 863 char *iport = NULL;
787 864 char phymask[MPTSAS_MAX_PHYS];
788 865 mptsas_phymask_t phy_mask = 0;
789 866 int dynamic_port = 0;
790 867 uint32_t page_address;
791 868 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
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792 869 int rval = DDI_FAILURE;
793 870 int i = 0;
794 871 uint8_t numphys = 0;
795 872 uint8_t phy_id;
796 873 uint8_t phy_port = 0;
797 874 uint16_t attached_devhdl = 0;
798 875 uint32_t dev_info;
799 876 uint64_t attached_sas_wwn;
800 877 uint16_t dev_hdl;
801 878 uint16_t pdev_hdl;
802 - uint16_t bay_num, enclosure;
879 + uint16_t bay_num, enclosure, io_flags;
803 880 char attached_wwnstr[MPTSAS_WWN_STRLEN];
804 881
805 882 /* CONSTCOND */
806 883 ASSERT(NO_COMPETING_THREADS);
807 884
808 885 switch (cmd) {
809 886 case DDI_ATTACH:
810 887 break;
811 888
812 889 case DDI_RESUME:
813 890 /*
814 891 * If this a scsi-iport node, nothing to do here.
815 892 */
816 893 return (DDI_SUCCESS);
817 894
818 895 default:
819 896 return (DDI_FAILURE);
820 897 }
821 898
822 899 pdip = ddi_get_parent(dip);
823 900
824 901 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
825 902 NULL) {
826 903 cmn_err(CE_WARN, "Failed attach iport because fail to "
827 904 "get tran vector for the HBA node");
828 905 return (DDI_FAILURE);
829 906 }
830 907
831 908 mpt = TRAN2MPT(hba_tran);
832 909 ASSERT(mpt != NULL);
833 910 if (mpt == NULL)
834 911 return (DDI_FAILURE);
835 912
836 913 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
837 914 NULL) {
838 915 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
839 916 "get tran vector for the iport node");
840 917 return (DDI_FAILURE);
841 918 }
842 919
843 920 /*
844 921 * Overwrite parent's tran_hba_private to iport's tran vector
845 922 */
846 923 hba_tran->tran_hba_private = mpt;
847 924
848 925 ddi_report_dev(dip);
849 926
850 927 /*
851 928 * Get SAS address for initiator port according dev_handle
852 929 */
853 930 iport = ddi_get_name_addr(dip);
854 931 if (iport && strncmp(iport, "v0", 2) == 0) {
855 932 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
856 933 MPTSAS_VIRTUAL_PORT, 1) !=
857 934 DDI_PROP_SUCCESS) {
858 935 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
859 936 MPTSAS_VIRTUAL_PORT);
860 937 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
861 938 "prop update failed");
862 939 return (DDI_FAILURE);
863 940 }
864 941 return (DDI_SUCCESS);
865 942 }
866 943
867 944 mutex_enter(&mpt->m_mutex);
868 945 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
869 946 bzero(phymask, sizeof (phymask));
870 947 (void) sprintf(phymask,
871 948 "%x", mpt->m_phy_info[i].phy_mask);
872 949 if (strcmp(phymask, iport) == 0) {
873 950 break;
874 951 }
875 952 }
876 953
877 954 if (i == MPTSAS_MAX_PHYS) {
878 955 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
879 956 "seems not exist", iport);
880 957 mutex_exit(&mpt->m_mutex);
881 958 return (DDI_FAILURE);
882 959 }
883 960
884 961 phy_mask = mpt->m_phy_info[i].phy_mask;
885 962
886 963 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
887 964 dynamic_port = 1;
888 965 else
889 966 dynamic_port = 0;
890 967
891 968 /*
892 969 * Update PHY info for smhba
893 970 */
894 971 if (mptsas_smhba_phy_init(mpt)) {
895 972 mutex_exit(&mpt->m_mutex);
896 973 mptsas_log(mpt, CE_WARN, "mptsas phy update "
897 974 "failed");
898 975 return (DDI_FAILURE);
899 976 }
900 977
901 978 mutex_exit(&mpt->m_mutex);
902 979
903 980 numphys = 0;
904 981 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
905 982 if ((phy_mask >> i) & 0x01) {
906 983 numphys++;
907 984 }
908 985 }
909 986
910 987 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
911 988 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
912 989 mpt->un.m_base_wwid);
913 990
914 991 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
915 992 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
916 993 DDI_PROP_SUCCESS) {
917 994 (void) ddi_prop_remove(DDI_DEV_T_NONE,
918 995 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
919 996 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
920 997 "prop update failed");
921 998 return (DDI_FAILURE);
922 999 }
923 1000 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
924 1001 MPTSAS_NUM_PHYS, numphys) !=
925 1002 DDI_PROP_SUCCESS) {
926 1003 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
927 1004 return (DDI_FAILURE);
928 1005 }
929 1006
930 1007 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
931 1008 "phymask", phy_mask) !=
932 1009 DDI_PROP_SUCCESS) {
933 1010 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
934 1011 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
935 1012 "prop update failed");
936 1013 return (DDI_FAILURE);
937 1014 }
938 1015
939 1016 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
940 1017 "dynamic-port", dynamic_port) !=
941 1018 DDI_PROP_SUCCESS) {
942 1019 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
943 1020 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
944 1021 "prop update failed");
945 1022 return (DDI_FAILURE);
946 1023 }
947 1024 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
948 1025 MPTSAS_VIRTUAL_PORT, 0) !=
949 1026 DDI_PROP_SUCCESS) {
950 1027 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
951 1028 MPTSAS_VIRTUAL_PORT);
952 1029 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
953 1030 "prop update failed");
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954 1031 return (DDI_FAILURE);
955 1032 }
956 1033 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask,
957 1034 &attached_devhdl);
958 1035
959 1036 mutex_enter(&mpt->m_mutex);
960 1037 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
961 1038 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
962 1039 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
963 1040 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
964 - &pdev_hdl, &bay_num, &enclosure);
1041 + &pdev_hdl, &bay_num, &enclosure, &io_flags);
965 1042 if (rval != DDI_SUCCESS) {
966 1043 mptsas_log(mpt, CE_WARN,
967 1044 "Failed to get device page0 for handle:%d",
968 1045 attached_devhdl);
969 1046 mutex_exit(&mpt->m_mutex);
970 1047 return (DDI_FAILURE);
971 1048 }
972 1049
973 1050 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
974 1051 bzero(phymask, sizeof (phymask));
975 1052 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
976 1053 if (strcmp(phymask, iport) == 0) {
977 1054 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
978 1055 "%x",
979 1056 mpt->m_phy_info[i].phy_mask);
980 1057 }
981 1058 }
982 1059 mutex_exit(&mpt->m_mutex);
983 1060
984 1061 bzero(attached_wwnstr, sizeof (attached_wwnstr));
985 1062 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
986 1063 attached_sas_wwn);
987 1064 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
988 1065 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
989 1066 DDI_PROP_SUCCESS) {
990 1067 (void) ddi_prop_remove(DDI_DEV_T_NONE,
991 1068 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
992 1069 return (DDI_FAILURE);
993 1070 }
994 1071
995 1072 /* Create kstats for each phy on this iport */
996 1073
997 1074 mptsas_create_phy_stats(mpt, iport, dip);
998 1075
999 1076 /*
1000 1077 * register sas hba iport with mdi (MPxIO/vhci)
1001 1078 */
1002 1079 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
1003 1080 dip, 0) == MDI_SUCCESS) {
1004 1081 mpt->m_mpxio_enable = TRUE;
1005 1082 }
1006 1083 return (DDI_SUCCESS);
1007 1084 }
1008 1085
1009 1086 /*
1010 1087 * Notes:
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1011 1088 * Set up all device state and allocate data structures,
1012 1089 * mutexes, condition variables, etc. for device operation.
1013 1090 * Add interrupts needed.
1014 1091 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
1015 1092 */
1016 1093 static int
1017 1094 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
1018 1095 {
1019 1096 mptsas_t *mpt = NULL;
1020 1097 int instance, i, j;
1021 - int doneq_thread_num;
1022 - char intr_added = 0;
1098 + int q_thread_num;
1023 1099 char map_setup = 0;
1024 1100 char config_setup = 0;
1025 1101 char hba_attach_setup = 0;
1026 1102 char smp_attach_setup = 0;
1027 1103 char mutex_init_done = 0;
1028 1104 char event_taskq_create = 0;
1029 1105 char dr_taskq_create = 0;
1030 1106 char doneq_thread_create = 0;
1107 + char txwq_thread_create = 0;
1108 + char added_watchdog = 0;
1031 1109 scsi_hba_tran_t *hba_tran;
1032 1110 uint_t mem_bar = MEM_SPACE;
1033 1111 int rval = DDI_FAILURE;
1034 1112
1035 1113 /* CONSTCOND */
1036 1114 ASSERT(NO_COMPETING_THREADS);
1037 1115
1038 1116 if (scsi_hba_iport_unit_address(dip)) {
1039 1117 return (mptsas_iport_attach(dip, cmd));
1040 1118 }
1041 1119
1042 1120 switch (cmd) {
1043 1121 case DDI_ATTACH:
1044 1122 break;
1045 1123
1046 1124 case DDI_RESUME:
1047 1125 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
1048 1126 return (DDI_FAILURE);
1049 1127
1050 1128 mpt = TRAN2MPT(hba_tran);
1051 1129
1052 1130 if (!mpt) {
1053 1131 return (DDI_FAILURE);
1054 1132 }
1055 1133
1056 1134 /*
1057 1135 * Reset hardware and softc to "no outstanding commands"
1058 1136 * Note that a check condition can result on first command
1059 1137 * to a target.
1060 1138 */
1061 1139 mutex_enter(&mpt->m_mutex);
1062 1140
1063 1141 /*
1064 1142 * raise power.
1065 1143 */
1066 1144 if (mpt->m_options & MPTSAS_OPT_PM) {
1067 1145 mutex_exit(&mpt->m_mutex);
1068 1146 (void) pm_busy_component(dip, 0);
1069 1147 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
1070 1148 if (rval == DDI_SUCCESS) {
1071 1149 mutex_enter(&mpt->m_mutex);
1072 1150 } else {
1073 1151 /*
1074 1152 * The pm_raise_power() call above failed,
1075 1153 * and that can only occur if we were unable
1076 1154 * to reset the hardware. This is probably
1077 1155 * due to unhealty hardware, and because
1078 1156 * important filesystems(such as the root
1079 1157 * filesystem) could be on the attached disks,
1080 1158 * it would not be a good idea to continue,
1081 1159 * as we won't be entirely certain we are
1082 1160 * writing correct data. So we panic() here
1083 1161 * to not only prevent possible data corruption,
1084 1162 * but to give developers or end users a hope
1085 1163 * of identifying and correcting any problems.
1086 1164 */
1087 1165 fm_panic("mptsas could not reset hardware "
1088 1166 "during resume");
1089 1167 }
1090 1168 }
1091 1169
1092 1170 mpt->m_suspended = 0;
1093 1171
1094 1172 /*
1095 1173 * Reinitialize ioc
1096 1174 */
1097 1175 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1098 1176 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1099 1177 mutex_exit(&mpt->m_mutex);
1100 1178 if (mpt->m_options & MPTSAS_OPT_PM) {
1101 1179 (void) pm_idle_component(dip, 0);
1102 1180 }
1103 1181 fm_panic("mptsas init chip fail during resume");
1104 1182 }
1105 1183 /*
1106 1184 * mptsas_update_driver_data needs interrupts so enable them
1107 1185 * first.
1108 1186 */
1109 1187 MPTSAS_ENABLE_INTR(mpt);
1110 1188 mptsas_update_driver_data(mpt);
1111 1189
1112 1190 /* start requests, if possible */
1113 1191 mptsas_restart_hba(mpt);
1114 1192
1115 1193 mutex_exit(&mpt->m_mutex);
1116 1194
1117 1195 /*
1118 1196 * Restart watch thread
1119 1197 */
1120 1198 mutex_enter(&mptsas_global_mutex);
1121 1199 if (mptsas_timeout_id == 0) {
1122 1200 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1123 1201 mptsas_tick);
1124 1202 mptsas_timeouts_enabled = 1;
1125 1203 }
1126 1204 mutex_exit(&mptsas_global_mutex);
1127 1205
1128 1206 /* report idle status to pm framework */
1129 1207 if (mpt->m_options & MPTSAS_OPT_PM) {
1130 1208 (void) pm_idle_component(dip, 0);
1131 1209 }
1132 1210
1133 1211 return (DDI_SUCCESS);
1134 1212
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1135 1213 default:
1136 1214 return (DDI_FAILURE);
1137 1215
1138 1216 }
1139 1217
1140 1218 instance = ddi_get_instance(dip);
1141 1219
1142 1220 /*
1143 1221 * Allocate softc information.
1144 1222 */
1145 - if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1223 + if (ddi_soft_state_zalloc(mptsas3_state, instance) != DDI_SUCCESS) {
1146 1224 mptsas_log(NULL, CE_WARN,
1147 1225 "mptsas%d: cannot allocate soft state", instance);
1148 1226 goto fail;
1149 1227 }
1150 1228
1151 - mpt = ddi_get_soft_state(mptsas_state, instance);
1229 + mpt = ddi_get_soft_state(mptsas3_state, instance);
1152 1230
1153 1231 if (mpt == NULL) {
1154 1232 mptsas_log(NULL, CE_WARN,
1155 1233 "mptsas%d: cannot get soft state", instance);
1156 1234 goto fail;
1157 1235 }
1158 1236
1159 1237 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1160 1238 scsi_size_clean(dip);
1161 1239
1162 1240 mpt->m_dip = dip;
1163 1241 mpt->m_instance = instance;
1164 1242
1165 1243 /* Make a per-instance copy of the structures */
1166 1244 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1167 - mpt->m_msg_dma_attr = mptsas_dma_attrs;
1245 + if (mptsas_use_64bit_msgaddr) {
1246 + mpt->m_msg_dma_attr = mptsas_dma_attrs64;
1247 + } else {
1248 + mpt->m_msg_dma_attr = mptsas_dma_attrs;
1249 + }
1168 1250 mpt->m_reg_acc_attr = mptsas_dev_attr;
1169 1251 mpt->m_dev_acc_attr = mptsas_dev_attr;
1170 1252
1171 1253 /*
1254 + * Round down the arq sense buffer size to nearest 16 bytes.
1255 + */
1256 + mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE;
1257 +
1258 + /*
1172 1259 * Initialize FMA
1173 1260 */
1174 1261 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1175 1262 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1176 1263 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1177 1264 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1178 1265
1179 1266 mptsas_fm_init(mpt);
1180 1267
1181 1268 if (mptsas_alloc_handshake_msg(mpt,
1182 1269 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1183 1270 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1184 1271 goto fail;
1185 1272 }
1186 1273
1187 1274 /*
1188 1275 * Setup configuration space
1189 1276 */
1190 1277 if (mptsas_config_space_init(mpt) == FALSE) {
1191 1278 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1192 1279 goto fail;
1193 1280 }
1194 1281 config_setup++;
1195 1282
1196 1283 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1197 1284 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1198 1285 mptsas_log(mpt, CE_WARN, "map setup failed");
1199 1286 goto fail;
1200 1287 }
1201 1288 map_setup++;
1202 1289
1203 1290 /*
1204 1291 * A taskq is created for dealing with the event handler
1205 1292 */
1206 1293 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1207 1294 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1208 1295 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1209 1296 goto fail;
1210 1297 }
1211 1298 event_taskq_create++;
1212 1299
1213 1300 /*
1214 1301 * A taskq is created for dealing with dr events
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1215 1302 */
1216 1303 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1217 1304 "mptsas_dr_taskq",
1218 1305 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1219 1306 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1220 1307 "failed");
1221 1308 goto fail;
1222 1309 }
1223 1310 dr_taskq_create++;
1224 1311
1312 + cv_init(&mpt->m_qthread_cv, NULL, CV_DRIVER, NULL);
1313 + mutex_init(&mpt->m_qthread_mutex, NULL, MUTEX_DRIVER, NULL);
1314 +
1315 + i = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1316 + 0, "mptsas_enable_txwq_prop", NCPUS > 1);
1317 + if (i) {
1318 + mpt->m_txwq_thread_n = NUM_TX_WAITQ;
1319 + mpt->m_txwq_enabled = FALSE;
1320 + if (ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1321 + 0, "mptsas_allow_txwq_jumping", 0)) {
1322 + mpt->m_txwq_allow_q_jumping = TRUE;
1323 + }
1324 + i = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1325 + 0, "mptsas_txwq_threashold_prop", 80000);
1326 + mpt->m_txwq_thread_threshold = (uint16_t)i;
1327 + } else {
1328 + mpt->m_txwq_thread_n = 0;
1329 + mpt->m_txwq_enabled = FALSE;
1330 + }
1331 +
1332 + if (mpt->m_txwq_thread_n) {
1333 + mutex_enter(&mpt->m_qthread_mutex);
1334 + for (j = 0; j < NUM_TX_WAITQ; j++) {
1335 + mutex_init(&mpt->m_tx_waitq[j].txwq_mutex, NULL,
1336 + MUTEX_DRIVER,
1337 + NULL);
1338 + cv_init(&mpt->m_tx_waitq[j].txwq_cv, NULL, CV_DRIVER,
1339 + NULL);
1340 + cv_init(&mpt->m_tx_waitq[j].txwq_drain_cv, NULL,
1341 + CV_DRIVER, NULL);
1342 + mpt->m_tx_waitq[j].txwq_active = TRUE;
1343 + mpt->m_tx_waitq[j].txwq_draining = FALSE;
1344 + mpt->m_tx_waitq[j].txwq_cmdq = NULL;
1345 + mpt->m_tx_waitq[j].txwq_qtail =
1346 + &mpt->m_tx_waitq[j].txwq_cmdq;
1347 + mutex_enter(&mpt->m_tx_waitq[j].txwq_mutex);
1348 + mpt->m_tx_waitq[j].arg.mpt = mpt;
1349 + mpt->m_tx_waitq[j].arg.t = j;
1350 + mpt->m_tx_waitq[j].txwq_threadp =
1351 + thread_create(NULL, 0, mptsas_tx_waitq_thread,
1352 + &mpt->m_tx_waitq[j].arg,
1353 + 0, &p0, TS_RUN, maxclsyspri - 10);
1354 + mutex_exit(&mpt->m_tx_waitq[j].txwq_mutex);
1355 + }
1356 + mutex_exit(&mpt->m_qthread_mutex);
1357 + txwq_thread_create++;
1358 + }
1359 +
1225 1360 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1226 1361 0, "mptsas_doneq_thread_threshold_prop", 10);
1227 1362 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1228 1363 0, "mptsas_doneq_length_threshold_prop", 8);
1229 1364 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1230 - 0, "mptsas_doneq_thread_n_prop", 8);
1365 + 0, "mptsas_doneq_thread_n_prop", min(NCPUS, 8));
1231 1366
1232 1367 if (mpt->m_doneq_thread_n) {
1233 - cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1234 - mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1235 -
1236 - mutex_enter(&mpt->m_doneq_mutex);
1368 + mutex_enter(&mpt->m_qthread_mutex);
1237 1369 mpt->m_doneq_thread_id =
1238 1370 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1239 1371 * mpt->m_doneq_thread_n, KM_SLEEP);
1240 1372
1241 1373 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1242 1374 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1243 1375 CV_DRIVER, NULL);
1244 1376 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1245 1377 MUTEX_DRIVER, NULL);
1246 1378 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1247 1379 mpt->m_doneq_thread_id[j].flag |=
1248 1380 MPTSAS_DONEQ_THREAD_ACTIVE;
1249 1381 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1250 1382 mpt->m_doneq_thread_id[j].arg.t = j;
1251 1383 mpt->m_doneq_thread_id[j].threadp =
1252 1384 thread_create(NULL, 0, mptsas_doneq_thread,
1253 1385 &mpt->m_doneq_thread_id[j].arg,
1254 - 0, &p0, TS_RUN, minclsyspri);
1255 - mpt->m_doneq_thread_id[j].donetail =
1256 - &mpt->m_doneq_thread_id[j].doneq;
1386 + 0, &p0, TS_RUN, maxclsyspri - 10);
1387 + mpt->m_doneq_thread_id[j].dlist.dl_tail =
1388 + &mpt->m_doneq_thread_id[j].dlist.dl_q;
1257 1389 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1258 1390 }
1259 - mutex_exit(&mpt->m_doneq_mutex);
1391 + mutex_exit(&mpt->m_qthread_mutex);
1260 1392 doneq_thread_create++;
1261 1393 }
1262 1394
1263 - /* Initialize mutex used in interrupt handler */
1264 - mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1265 - DDI_INTR_PRI(mpt->m_intr_pri));
1395 + /*
1396 + * Disable hardware interrupt since we're not ready to
1397 + * handle it yet.
1398 + */
1399 + MPTSAS_DISABLE_INTR(mpt);
1400 +
1401 + /*
1402 + * Initialize mutex used in interrupt handler.
1403 + * We don't support hi-level so the mutex's are all adaptive
1404 + * and we don't want to register the interrupts until we get
1405 + * the chip type information from _init_chip() below.
1406 + * Otherwise we would use DDI_INTR_PRI(mpt->m_intr_pri)
1407 + * rather than NULL in the mutex_init() calls.
1408 + */
1409 + mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, NULL);
1266 1410 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1267 - mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER,
1268 - DDI_INTR_PRI(mpt->m_intr_pri));
1269 1411 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1270 1412 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1271 - NULL, MUTEX_DRIVER,
1272 - DDI_INTR_PRI(mpt->m_intr_pri));
1413 + NULL, MUTEX_DRIVER, NULL);
1273 1414 }
1274 1415
1275 1416 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1276 1417 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1277 1418 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1278 1419 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1279 1420 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1280 1421 mutex_init_done++;
1281 1422
1282 - /*
1283 - * Disable hardware interrupt since we're not ready to
1284 - * handle it yet.
1285 - */
1286 - MPTSAS_DISABLE_INTR(mpt);
1287 - if (mptsas_register_intrs(mpt) == FALSE)
1288 - goto fail;
1289 - intr_added++;
1290 -
1291 1423 mutex_enter(&mpt->m_mutex);
1292 1424 /*
1293 1425 * Initialize power management component
1294 1426 */
1295 1427 if (mpt->m_options & MPTSAS_OPT_PM) {
1296 1428 if (mptsas_init_pm(mpt)) {
1297 1429 mutex_exit(&mpt->m_mutex);
1298 1430 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1299 1431 "failed");
1300 1432 goto fail;
1301 1433 }
1302 1434 }
1303 1435
1304 1436 /*
1305 1437 * Initialize chip using Message Unit Reset, if allowed
1306 1438 */
1307 1439 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1308 1440 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1309 1441 mutex_exit(&mpt->m_mutex);
1310 1442 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1311 1443 goto fail;
1312 1444 }
1313 1445
1314 1446 /*
1315 1447 * Fill in the phy_info structure and get the base WWID
1316 1448 */
1317 1449 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1318 1450 mptsas_log(mpt, CE_WARN,
1319 1451 "mptsas_get_manufacture_page5 failed!");
1320 1452 goto fail;
1321 1453 }
1322 1454
1323 1455 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1324 1456 mptsas_log(mpt, CE_WARN,
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1325 1457 "mptsas_get_sas_io_unit_page_hndshk failed!");
1326 1458 goto fail;
1327 1459 }
1328 1460
1329 1461 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1330 1462 mptsas_log(mpt, CE_WARN,
1331 1463 "mptsas_get_manufacture_page0 failed!");
1332 1464 goto fail;
1333 1465 }
1334 1466
1467 + /*
1468 + * If we only have one interrupt the default for doneq_thread_threshold
1469 + * should be 0 so that all completion processing goes to the threads.
1470 + * Only change it if it wasn't set from .conf file.
1471 + */
1472 + if (mpt->m_doneq_thread_n != 0 &&
1473 + ddi_prop_exists(DDI_DEV_T_ANY, dip,
1474 + 0, "mptsas_doneq_length_threshold_prop") == 0 &&
1475 + mpt->m_intr_cnt == 1) {
1476 + mpt->m_doneq_length_threshold = 0;
1477 + }
1478 +
1479 +
1335 1480 mutex_exit(&mpt->m_mutex);
1336 1481
1337 1482 /*
1338 1483 * Register the iport for multiple port HBA
1339 1484 */
1340 1485 mptsas_iport_register(mpt);
1341 1486
1342 1487 /*
1343 1488 * initialize SCSI HBA transport structure
1344 1489 */
1345 1490 if (mptsas_hba_setup(mpt) == FALSE)
1346 1491 goto fail;
1347 1492 hba_attach_setup++;
1348 1493
1349 1494 if (mptsas_smp_setup(mpt) == FALSE)
1350 1495 goto fail;
1351 1496 smp_attach_setup++;
1352 1497
1353 1498 if (mptsas_cache_create(mpt) == FALSE)
1354 1499 goto fail;
1355 1500
1356 1501 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1357 1502 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
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1358 1503 if (mpt->m_scsi_reset_delay == 0) {
1359 1504 mptsas_log(mpt, CE_NOTE,
1360 1505 "scsi_reset_delay of 0 is not recommended,"
1361 1506 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1362 1507 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1363 1508 }
1364 1509
1365 1510 /*
1366 1511 * Initialize the wait and done FIFO queue
1367 1512 */
1368 - mpt->m_donetail = &mpt->m_doneq;
1513 + mpt->m_dlist.dl_tail = &mpt->m_dlist.dl_q;
1369 1514 mpt->m_waitqtail = &mpt->m_waitq;
1370 - mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
1371 - mpt->m_tx_draining = 0;
1372 1515
1373 1516 /*
1374 1517 * ioc cmd queue initialize
1375 1518 */
1376 1519 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1377 1520 mpt->m_dev_handle = 0xFFFF;
1378 1521
1379 1522 MPTSAS_ENABLE_INTR(mpt);
1380 1523
1381 1524 /*
1382 1525 * enable event notification
1383 1526 */
1384 1527 mutex_enter(&mpt->m_mutex);
1385 1528 if (mptsas_ioc_enable_event_notification(mpt)) {
1386 1529 mutex_exit(&mpt->m_mutex);
1387 1530 goto fail;
1388 1531 }
1389 1532 mutex_exit(&mpt->m_mutex);
1390 1533
1391 1534 /*
1392 - * Initialize PHY info for smhba
1535 + * used for mptsas_watch
1536 + */
1537 + mptsas_list_add(mpt);
1538 +
1539 + mutex_enter(&mptsas_global_mutex);
1540 + if (mptsas_timeouts_enabled == 0) {
1541 + mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1542 + dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1543 +
1544 + mptsas_tick = mptsas_scsi_watchdog_tick *
1545 + drv_usectohz((clock_t)1000000);
1546 +
1547 + mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1548 + mptsas_timeouts_enabled = 1;
1549 + }
1550 + mutex_exit(&mptsas_global_mutex);
1551 + added_watchdog++;
1552 +
1553 + /*
1554 + * Initialize PHY info for smhba.
1555 + * This requires watchdog to be enabled otherwise if interrupts
1556 + * don't work the system will hang.
1393 1557 */
1394 1558 if (mptsas_smhba_setup(mpt)) {
1395 1559 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1396 1560 "failed");
1397 1561 goto fail;
1398 1562 }
1399 1563
1400 1564 /* Check all dma handles allocated in attach */
1401 1565 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1402 1566 != DDI_SUCCESS) ||
1567 + (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl)
1568 + != DDI_SUCCESS) ||
1403 1569 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1404 1570 != DDI_SUCCESS) ||
1405 1571 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1406 1572 != DDI_SUCCESS) ||
1407 1573 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1408 1574 != DDI_SUCCESS) ||
1409 1575 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1410 1576 != DDI_SUCCESS)) {
1411 1577 goto fail;
1412 1578 }
1413 1579
1414 1580 /* Check all acc handles allocated in attach */
1415 1581 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1416 1582 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1417 1583 != DDI_SUCCESS) ||
1584 + (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl)
1585 + != DDI_SUCCESS) ||
1418 1586 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1419 1587 != DDI_SUCCESS) ||
1420 1588 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1421 1589 != DDI_SUCCESS) ||
1422 1590 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1423 1591 != DDI_SUCCESS) ||
1424 1592 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1425 1593 != DDI_SUCCESS) ||
1426 1594 (mptsas_check_acc_handle(mpt->m_config_handle)
1427 1595 != DDI_SUCCESS)) {
1428 1596 goto fail;
1429 1597 }
1430 1598
1431 1599 /*
1432 1600 * After this point, we are not going to fail the attach.
1433 1601 */
1434 - /*
1435 - * used for mptsas_watch
1436 - */
1437 - mptsas_list_add(mpt);
1438 -
1439 - mutex_enter(&mptsas_global_mutex);
1440 - if (mptsas_timeouts_enabled == 0) {
1441 - mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1442 - dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1443 -
1444 - mptsas_tick = mptsas_scsi_watchdog_tick *
1445 - drv_usectohz((clock_t)1000000);
1446 -
1447 - mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1448 - mptsas_timeouts_enabled = 1;
1449 - }
1450 - mutex_exit(&mptsas_global_mutex);
1451 1602
1452 1603 /* Print message of HBA present */
1453 1604 ddi_report_dev(dip);
1454 1605
1455 1606 /* report idle status to pm framework */
1456 1607 if (mpt->m_options & MPTSAS_OPT_PM) {
1457 1608 (void) pm_idle_component(dip, 0);
1458 1609 }
1459 1610
1460 1611 return (DDI_SUCCESS);
1461 1612
1462 1613 fail:
1463 1614 mptsas_log(mpt, CE_WARN, "attach failed");
1464 1615 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1465 1616 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1466 1617 if (mpt) {
1467 - mutex_enter(&mptsas_global_mutex);
1618 + /* deallocate in reverse order */
1619 + if (added_watchdog) {
1620 + mptsas_list_del(mpt);
1621 + mutex_enter(&mptsas_global_mutex);
1468 1622
1469 - if (mptsas_timeout_id && (mptsas_head == NULL)) {
1470 - timeout_id_t tid = mptsas_timeout_id;
1471 - mptsas_timeouts_enabled = 0;
1472 - mptsas_timeout_id = 0;
1623 + if (mptsas_timeout_id && (mptsas_head == NULL)) {
1624 + timeout_id_t tid = mptsas_timeout_id;
1625 + mptsas_timeouts_enabled = 0;
1626 + mptsas_timeout_id = 0;
1627 + mutex_exit(&mptsas_global_mutex);
1628 + (void) untimeout(tid);
1629 + mutex_enter(&mptsas_global_mutex);
1630 + }
1473 1631 mutex_exit(&mptsas_global_mutex);
1474 - (void) untimeout(tid);
1475 - mutex_enter(&mptsas_global_mutex);
1476 1632 }
1477 - mutex_exit(&mptsas_global_mutex);
1478 - /* deallocate in reverse order */
1633 +
1479 1634 mptsas_cache_destroy(mpt);
1480 1635
1481 1636 if (smp_attach_setup) {
1482 1637 mptsas_smp_teardown(mpt);
1483 1638 }
1484 1639 if (hba_attach_setup) {
1485 1640 mptsas_hba_teardown(mpt);
1486 1641 }
1487 1642
1488 1643 if (mpt->m_targets)
1489 1644 refhash_destroy(mpt->m_targets);
1490 1645 if (mpt->m_smp_targets)
1491 1646 refhash_destroy(mpt->m_smp_targets);
1492 1647
1493 1648 if (mpt->m_active) {
1494 1649 mptsas_free_active_slots(mpt);
1495 1650 }
1496 - if (intr_added) {
1651 + if (mpt->m_intr_cnt) {
1497 1652 mptsas_unregister_intrs(mpt);
1498 1653 }
1499 1654
1500 1655 if (doneq_thread_create) {
1501 - mutex_enter(&mpt->m_doneq_mutex);
1502 - doneq_thread_num = mpt->m_doneq_thread_n;
1503 - for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1656 + mutex_enter(&mpt->m_qthread_mutex);
1657 + q_thread_num = mpt->m_doneq_thread_n;
1658 + for (j = 0; j < q_thread_num; j++) {
1504 1659 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1505 1660 mpt->m_doneq_thread_id[j].flag &=
1506 1661 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1507 1662 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1508 1663 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1509 1664 }
1510 1665 while (mpt->m_doneq_thread_n) {
1511 - cv_wait(&mpt->m_doneq_thread_cv,
1512 - &mpt->m_doneq_mutex);
1666 + cv_wait(&mpt->m_qthread_cv,
1667 + &mpt->m_qthread_mutex);
1513 1668 }
1514 - for (j = 0; j < doneq_thread_num; j++) {
1669 + for (j = 0; j < q_thread_num; j++) {
1515 1670 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1516 1671 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1517 1672 }
1518 1673 kmem_free(mpt->m_doneq_thread_id,
1519 1674 sizeof (mptsas_doneq_thread_list_t)
1520 - * doneq_thread_num);
1521 - mutex_exit(&mpt->m_doneq_mutex);
1522 - cv_destroy(&mpt->m_doneq_thread_cv);
1523 - mutex_destroy(&mpt->m_doneq_mutex);
1675 + * q_thread_num);
1676 + mutex_exit(&mpt->m_qthread_mutex);
1677 + }
1678 + if (txwq_thread_create) {
1679 + mutex_enter(&mpt->m_qthread_mutex);
1680 + q_thread_num = mpt->m_txwq_thread_n;
1681 + for (j = 0; j < q_thread_num; j++) {
1682 + mutex_enter(&mpt->m_tx_waitq[j].txwq_mutex);
1683 + mpt->m_tx_waitq[j].txwq_active = FALSE;
1684 + cv_signal(&mpt->m_tx_waitq[j].txwq_cv);
1685 + mutex_exit(&mpt->m_tx_waitq[j].txwq_mutex);
1686 + }
1687 + while (mpt->m_txwq_thread_n) {
1688 + cv_wait(&mpt->m_qthread_cv,
1689 + &mpt->m_qthread_mutex);
1690 + }
1691 + for (j = 0; j < q_thread_num; j++) {
1692 + cv_destroy(&mpt->m_tx_waitq[j].txwq_cv);
1693 + cv_destroy(&mpt->m_tx_waitq[j].txwq_drain_cv);
1694 + mutex_destroy(&mpt->m_tx_waitq[j].txwq_mutex);
1695 + }
1524 1696 }
1525 1697 if (event_taskq_create) {
1526 1698 ddi_taskq_destroy(mpt->m_event_taskq);
1527 1699 }
1528 1700 if (dr_taskq_create) {
1529 1701 ddi_taskq_destroy(mpt->m_dr_taskq);
1530 1702 }
1531 1703 if (mutex_init_done) {
1532 - mutex_destroy(&mpt->m_tx_waitq_mutex);
1704 + mutex_destroy(&mpt->m_qthread_mutex);
1533 1705 mutex_destroy(&mpt->m_passthru_mutex);
1534 1706 mutex_destroy(&mpt->m_mutex);
1535 1707 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1536 1708 mutex_destroy(
1537 1709 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1538 1710 }
1711 + cv_destroy(&mpt->m_qthread_cv);
1539 1712 cv_destroy(&mpt->m_cv);
1540 1713 cv_destroy(&mpt->m_passthru_cv);
1541 1714 cv_destroy(&mpt->m_fw_cv);
1542 1715 cv_destroy(&mpt->m_config_cv);
1543 1716 cv_destroy(&mpt->m_fw_diag_cv);
1544 1717 }
1545 1718
1546 1719 if (map_setup) {
1547 1720 mptsas_cfg_fini(mpt);
1548 1721 }
1549 1722 if (config_setup) {
1550 1723 mptsas_config_space_fini(mpt);
1551 1724 }
1552 1725 mptsas_free_handshake_msg(mpt);
1553 1726 mptsas_hba_fini(mpt);
1554 1727
1555 1728 mptsas_fm_fini(mpt);
1556 - ddi_soft_state_free(mptsas_state, instance);
1729 + ddi_soft_state_free(mptsas3_state, instance);
1557 1730 ddi_prop_remove_all(dip);
1558 1731 }
1559 1732 return (DDI_FAILURE);
1560 1733 }
1561 1734
1562 1735 static int
1563 1736 mptsas_suspend(dev_info_t *devi)
1564 1737 {
1565 1738 mptsas_t *mpt, *g;
1566 1739 scsi_hba_tran_t *tran;
1567 1740
1568 1741 if (scsi_hba_iport_unit_address(devi)) {
1569 1742 return (DDI_SUCCESS);
1570 1743 }
1571 1744
1572 1745 if ((tran = ddi_get_driver_private(devi)) == NULL)
1573 1746 return (DDI_SUCCESS);
1574 1747
1575 1748 mpt = TRAN2MPT(tran);
1576 1749 if (!mpt) {
1577 1750 return (DDI_SUCCESS);
1578 1751 }
1579 1752
1580 1753 mutex_enter(&mpt->m_mutex);
1581 1754
1582 1755 if (mpt->m_suspended++) {
1583 1756 mutex_exit(&mpt->m_mutex);
1584 1757 return (DDI_SUCCESS);
1585 1758 }
1586 1759
1587 1760 /*
1588 1761 * Cancel timeout threads for this mpt
1589 1762 */
1590 1763 if (mpt->m_quiesce_timeid) {
1591 1764 timeout_id_t tid = mpt->m_quiesce_timeid;
1592 1765 mpt->m_quiesce_timeid = 0;
1593 1766 mutex_exit(&mpt->m_mutex);
1594 1767 (void) untimeout(tid);
1595 1768 mutex_enter(&mpt->m_mutex);
1596 1769 }
1597 1770
1598 1771 if (mpt->m_restart_cmd_timeid) {
1599 1772 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1600 1773 mpt->m_restart_cmd_timeid = 0;
1601 1774 mutex_exit(&mpt->m_mutex);
1602 1775 (void) untimeout(tid);
1603 1776 mutex_enter(&mpt->m_mutex);
1604 1777 }
1605 1778
1606 1779 mutex_exit(&mpt->m_mutex);
1607 1780
1608 1781 (void) pm_idle_component(mpt->m_dip, 0);
1609 1782
1610 1783 /*
1611 1784 * Cancel watch threads if all mpts suspended
1612 1785 */
1613 1786 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1614 1787 for (g = mptsas_head; g != NULL; g = g->m_next) {
1615 1788 if (!g->m_suspended)
1616 1789 break;
1617 1790 }
1618 1791 rw_exit(&mptsas_global_rwlock);
1619 1792
1620 1793 mutex_enter(&mptsas_global_mutex);
1621 1794 if (g == NULL) {
1622 1795 timeout_id_t tid;
1623 1796
1624 1797 mptsas_timeouts_enabled = 0;
1625 1798 if (mptsas_timeout_id) {
1626 1799 tid = mptsas_timeout_id;
1627 1800 mptsas_timeout_id = 0;
1628 1801 mutex_exit(&mptsas_global_mutex);
1629 1802 (void) untimeout(tid);
1630 1803 mutex_enter(&mptsas_global_mutex);
1631 1804 }
1632 1805 if (mptsas_reset_watch) {
1633 1806 tid = mptsas_reset_watch;
1634 1807 mptsas_reset_watch = 0;
1635 1808 mutex_exit(&mptsas_global_mutex);
1636 1809 (void) untimeout(tid);
1637 1810 mutex_enter(&mptsas_global_mutex);
1638 1811 }
1639 1812 }
1640 1813 mutex_exit(&mptsas_global_mutex);
1641 1814
1642 1815 mutex_enter(&mpt->m_mutex);
1643 1816
1644 1817 /*
1645 1818 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1646 1819 */
1647 1820 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1648 1821 (mpt->m_power_level != PM_LEVEL_D0)) {
1649 1822 mutex_exit(&mpt->m_mutex);
1650 1823 return (DDI_SUCCESS);
1651 1824 }
1652 1825
1653 1826 /* Disable HBA interrupts in hardware */
1654 1827 MPTSAS_DISABLE_INTR(mpt);
1655 1828 /*
1656 1829 * Send RAID action system shutdown to sync IR
1657 1830 */
1658 1831 mptsas_raid_action_system_shutdown(mpt);
1659 1832
1660 1833 mutex_exit(&mpt->m_mutex);
1661 1834
1662 1835 /* drain the taskq */
1663 1836 ddi_taskq_wait(mpt->m_event_taskq);
1664 1837 ddi_taskq_wait(mpt->m_dr_taskq);
1665 1838
1666 1839 return (DDI_SUCCESS);
1667 1840 }
1668 1841
1669 1842 #ifdef __sparc
1670 1843 /*ARGSUSED*/
1671 1844 static int
1672 1845 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1673 1846 {
1674 1847 mptsas_t *mpt;
1675 1848 scsi_hba_tran_t *tran;
1676 1849
1677 1850 /*
1678 1851 * If this call is for iport, just return.
1679 1852 */
1680 1853 if (scsi_hba_iport_unit_address(devi))
1681 1854 return (DDI_SUCCESS);
1682 1855
1683 1856 if ((tran = ddi_get_driver_private(devi)) == NULL)
1684 1857 return (DDI_SUCCESS);
1685 1858
1686 1859 if ((mpt = TRAN2MPT(tran)) == NULL)
1687 1860 return (DDI_SUCCESS);
1688 1861
1689 1862 /*
1690 1863 * Send RAID action system shutdown to sync IR. Disable HBA
1691 1864 * interrupts in hardware first.
1692 1865 */
1693 1866 MPTSAS_DISABLE_INTR(mpt);
1694 1867 mptsas_raid_action_system_shutdown(mpt);
1695 1868
1696 1869 return (DDI_SUCCESS);
1697 1870 }
1698 1871 #else /* __sparc */
1699 1872 /*
1700 1873 * quiesce(9E) entry point.
1701 1874 *
1702 1875 * This function is called when the system is single-threaded at high
1703 1876 * PIL with preemption disabled. Therefore, this function must not be
1704 1877 * blocked.
1705 1878 *
1706 1879 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1707 1880 * DDI_FAILURE indicates an error condition and should almost never happen.
1708 1881 */
1709 1882 static int
1710 1883 mptsas_quiesce(dev_info_t *devi)
1711 1884 {
1712 1885 mptsas_t *mpt;
1713 1886 scsi_hba_tran_t *tran;
1714 1887
1715 1888 /*
1716 1889 * If this call is for iport, just return.
1717 1890 */
1718 1891 if (scsi_hba_iport_unit_address(devi))
1719 1892 return (DDI_SUCCESS);
1720 1893
1721 1894 if ((tran = ddi_get_driver_private(devi)) == NULL)
1722 1895 return (DDI_SUCCESS);
1723 1896
1724 1897 if ((mpt = TRAN2MPT(tran)) == NULL)
1725 1898 return (DDI_SUCCESS);
1726 1899
1727 1900 /* Disable HBA interrupts in hardware */
1728 1901 MPTSAS_DISABLE_INTR(mpt);
1729 1902 /* Send RAID action system shutdonw to sync IR */
1730 1903 mptsas_raid_action_system_shutdown(mpt);
1731 1904
1732 1905 return (DDI_SUCCESS);
1733 1906 }
1734 1907 #endif /* __sparc */
1735 1908
1736 1909 /*
1737 1910 * detach(9E). Remove all device allocations and system resources;
1738 1911 * disable device interrupts.
1739 1912 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1740 1913 */
1741 1914 static int
1742 1915 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1743 1916 {
1744 1917 /* CONSTCOND */
1745 1918 ASSERT(NO_COMPETING_THREADS);
1746 1919 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1747 1920
1748 1921 switch (cmd) {
1749 1922 case DDI_DETACH:
1750 1923 return (mptsas_do_detach(devi));
1751 1924
1752 1925 case DDI_SUSPEND:
1753 1926 return (mptsas_suspend(devi));
1754 1927
1755 1928 default:
1756 1929 return (DDI_FAILURE);
1757 1930 }
1758 1931 /* NOTREACHED */
1759 1932 }
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1760 1933
1761 1934 static int
1762 1935 mptsas_do_detach(dev_info_t *dip)
1763 1936 {
1764 1937 mptsas_t *mpt;
1765 1938 scsi_hba_tran_t *tran;
1766 1939 int circ = 0;
1767 1940 int circ1 = 0;
1768 1941 mdi_pathinfo_t *pip = NULL;
1769 1942 int i;
1770 - int doneq_thread_num = 0;
1943 + int q_thread_num = 0;
1771 1944
1772 1945 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1773 1946
1774 1947 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1775 1948 return (DDI_FAILURE);
1776 1949
1777 1950 mpt = TRAN2MPT(tran);
1778 1951 if (!mpt) {
1779 1952 return (DDI_FAILURE);
1780 1953 }
1781 1954 /*
1782 1955 * Still have pathinfo child, should not detach mpt driver
1783 1956 */
1784 1957 if (scsi_hba_iport_unit_address(dip)) {
1785 1958 if (mpt->m_mpxio_enable) {
1786 1959 /*
1787 1960 * MPxIO enabled for the iport
1788 1961 */
1789 1962 ndi_devi_enter(scsi_vhci_dip, &circ1);
1790 1963 ndi_devi_enter(dip, &circ);
1791 1964 while (pip = mdi_get_next_client_path(dip, NULL)) {
1792 1965 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1793 1966 continue;
1794 1967 }
1795 1968 ndi_devi_exit(dip, circ);
1796 1969 ndi_devi_exit(scsi_vhci_dip, circ1);
1797 1970 NDBG12(("detach failed because of "
1798 1971 "outstanding path info"));
1799 1972 return (DDI_FAILURE);
1800 1973 }
1801 1974 ndi_devi_exit(dip, circ);
1802 1975 ndi_devi_exit(scsi_vhci_dip, circ1);
1803 1976 (void) mdi_phci_unregister(dip, 0);
1804 1977 }
1805 1978
1806 1979 ddi_prop_remove_all(dip);
1807 1980
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1808 1981 return (DDI_SUCCESS);
1809 1982 }
1810 1983
1811 1984 /* Make sure power level is D0 before accessing registers */
1812 1985 if (mpt->m_options & MPTSAS_OPT_PM) {
1813 1986 (void) pm_busy_component(dip, 0);
1814 1987 if (mpt->m_power_level != PM_LEVEL_D0) {
1815 1988 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1816 1989 DDI_SUCCESS) {
1817 1990 mptsas_log(mpt, CE_WARN,
1818 - "mptsas%d: Raise power request failed.",
1991 + "mptsas3%d: Raise power request failed.",
1819 1992 mpt->m_instance);
1820 1993 (void) pm_idle_component(dip, 0);
1821 1994 return (DDI_FAILURE);
1822 1995 }
1823 1996 }
1824 1997 }
1825 1998
1826 1999 /*
1827 2000 * Send RAID action system shutdown to sync IR. After action, send a
1828 2001 * Message Unit Reset. Since after that DMA resource will be freed,
1829 2002 * set ioc to READY state will avoid HBA initiated DMA operation.
1830 2003 */
1831 2004 mutex_enter(&mpt->m_mutex);
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1832 2005 MPTSAS_DISABLE_INTR(mpt);
1833 2006 mptsas_raid_action_system_shutdown(mpt);
1834 2007 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1835 2008 (void) mptsas_ioc_reset(mpt, FALSE);
1836 2009 mutex_exit(&mpt->m_mutex);
1837 2010 mptsas_rem_intrs(mpt);
1838 2011 ddi_taskq_destroy(mpt->m_event_taskq);
1839 2012 ddi_taskq_destroy(mpt->m_dr_taskq);
1840 2013
1841 2014 if (mpt->m_doneq_thread_n) {
1842 - mutex_enter(&mpt->m_doneq_mutex);
1843 - doneq_thread_num = mpt->m_doneq_thread_n;
2015 + mutex_enter(&mpt->m_qthread_mutex);
2016 + q_thread_num = mpt->m_doneq_thread_n;
1844 2017 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1845 2018 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1846 2019 mpt->m_doneq_thread_id[i].flag &=
1847 2020 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1848 2021 cv_signal(&mpt->m_doneq_thread_id[i].cv);
1849 2022 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1850 2023 }
1851 2024 while (mpt->m_doneq_thread_n) {
1852 - cv_wait(&mpt->m_doneq_thread_cv,
1853 - &mpt->m_doneq_mutex);
2025 + cv_wait(&mpt->m_qthread_cv,
2026 + &mpt->m_qthread_mutex);
1854 2027 }
1855 - for (i = 0; i < doneq_thread_num; i++) {
2028 + for (i = 0; i < q_thread_num; i++) {
1856 2029 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1857 2030 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1858 2031 }
1859 2032 kmem_free(mpt->m_doneq_thread_id,
1860 2033 sizeof (mptsas_doneq_thread_list_t)
1861 - * doneq_thread_num);
1862 - mutex_exit(&mpt->m_doneq_mutex);
1863 - cv_destroy(&mpt->m_doneq_thread_cv);
1864 - mutex_destroy(&mpt->m_doneq_mutex);
2034 + * q_thread_num);
2035 + mutex_exit(&mpt->m_qthread_mutex);
2036 + }
2037 + if (mpt->m_txwq_thread_n) {
2038 + mutex_enter(&mpt->m_qthread_mutex);
2039 + q_thread_num = mpt->m_txwq_thread_n;
2040 + for (i = 0; i < q_thread_num; i++) {
2041 + mutex_enter(&mpt->m_tx_waitq[i].txwq_mutex);
2042 + mpt->m_tx_waitq[i].txwq_active = FALSE;
2043 + cv_signal(&mpt->m_tx_waitq[i].txwq_cv);
2044 + mutex_exit(&mpt->m_tx_waitq[i].txwq_mutex);
2045 + }
2046 + while (mpt->m_txwq_thread_n) {
2047 + cv_wait(&mpt->m_qthread_cv,
2048 + &mpt->m_qthread_mutex);
2049 + }
2050 + for (i = 0; i < q_thread_num; i++) {
2051 + cv_destroy(&mpt->m_tx_waitq[i].txwq_cv);
2052 + cv_destroy(&mpt->m_tx_waitq[i].txwq_drain_cv);
2053 + mutex_destroy(&mpt->m_tx_waitq[i].txwq_mutex);
2054 + }
1865 2055 }
1866 2056
1867 2057 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1868 2058
1869 2059 mptsas_list_del(mpt);
1870 2060
1871 2061 /*
1872 2062 * Cancel timeout threads for this mpt
1873 2063 */
1874 2064 mutex_enter(&mpt->m_mutex);
1875 2065 if (mpt->m_quiesce_timeid) {
1876 2066 timeout_id_t tid = mpt->m_quiesce_timeid;
1877 2067 mpt->m_quiesce_timeid = 0;
1878 2068 mutex_exit(&mpt->m_mutex);
1879 2069 (void) untimeout(tid);
1880 2070 mutex_enter(&mpt->m_mutex);
1881 2071 }
1882 2072
1883 2073 if (mpt->m_restart_cmd_timeid) {
1884 2074 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1885 2075 mpt->m_restart_cmd_timeid = 0;
1886 2076 mutex_exit(&mpt->m_mutex);
1887 2077 (void) untimeout(tid);
1888 2078 mutex_enter(&mpt->m_mutex);
1889 2079 }
1890 2080
1891 2081 mutex_exit(&mpt->m_mutex);
1892 2082
1893 2083 /*
1894 2084 * last mpt? ... if active, CANCEL watch threads.
1895 2085 */
1896 2086 mutex_enter(&mptsas_global_mutex);
1897 2087 if (mptsas_head == NULL) {
1898 2088 timeout_id_t tid;
1899 2089 /*
1900 2090 * Clear mptsas_timeouts_enable so that the watch thread
1901 2091 * gets restarted on DDI_ATTACH
1902 2092 */
1903 2093 mptsas_timeouts_enabled = 0;
1904 2094 if (mptsas_timeout_id) {
1905 2095 tid = mptsas_timeout_id;
1906 2096 mptsas_timeout_id = 0;
1907 2097 mutex_exit(&mptsas_global_mutex);
1908 2098 (void) untimeout(tid);
1909 2099 mutex_enter(&mptsas_global_mutex);
1910 2100 }
1911 2101 if (mptsas_reset_watch) {
1912 2102 tid = mptsas_reset_watch;
1913 2103 mptsas_reset_watch = 0;
1914 2104 mutex_exit(&mptsas_global_mutex);
1915 2105 (void) untimeout(tid);
1916 2106 mutex_enter(&mptsas_global_mutex);
1917 2107 }
1918 2108 }
1919 2109 mutex_exit(&mptsas_global_mutex);
1920 2110
1921 2111 /*
1922 2112 * Delete Phy stats
1923 2113 */
1924 2114 mptsas_destroy_phy_stats(mpt);
1925 2115
1926 2116 mptsas_destroy_hashes(mpt);
1927 2117
1928 2118 /*
1929 2119 * Delete nt_active.
1930 2120 */
1931 2121 mutex_enter(&mpt->m_mutex);
1932 2122 mptsas_free_active_slots(mpt);
1933 2123 mutex_exit(&mpt->m_mutex);
1934 2124
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1935 2125 /* deallocate everything that was allocated in mptsas_attach */
1936 2126 mptsas_cache_destroy(mpt);
1937 2127
1938 2128 mptsas_hba_fini(mpt);
1939 2129 mptsas_cfg_fini(mpt);
1940 2130
1941 2131 /* Lower the power informing PM Framework */
1942 2132 if (mpt->m_options & MPTSAS_OPT_PM) {
1943 2133 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
1944 2134 mptsas_log(mpt, CE_WARN,
1945 - "!mptsas%d: Lower power request failed "
2135 + "!mptsas3%d: Lower power request failed "
1946 2136 "during detach, ignoring.",
1947 2137 mpt->m_instance);
1948 2138 }
1949 2139
1950 - mutex_destroy(&mpt->m_tx_waitq_mutex);
2140 + mutex_destroy(&mpt->m_qthread_mutex);
1951 2141 mutex_destroy(&mpt->m_passthru_mutex);
1952 2142 mutex_destroy(&mpt->m_mutex);
1953 2143 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1954 2144 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
1955 2145 }
2146 + cv_destroy(&mpt->m_qthread_cv);
1956 2147 cv_destroy(&mpt->m_cv);
1957 2148 cv_destroy(&mpt->m_passthru_cv);
1958 2149 cv_destroy(&mpt->m_fw_cv);
1959 2150 cv_destroy(&mpt->m_config_cv);
1960 2151 cv_destroy(&mpt->m_fw_diag_cv);
1961 2152
1962 2153
1963 2154 mptsas_smp_teardown(mpt);
1964 2155 mptsas_hba_teardown(mpt);
1965 2156
1966 2157 mptsas_config_space_fini(mpt);
1967 2158
1968 2159 mptsas_free_handshake_msg(mpt);
1969 2160
1970 2161 mptsas_fm_fini(mpt);
1971 - ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
2162 + ddi_soft_state_free(mptsas3_state, ddi_get_instance(dip));
1972 2163 ddi_prop_remove_all(dip);
1973 2164
1974 2165 return (DDI_SUCCESS);
1975 2166 }
1976 2167
1977 2168 static void
1978 2169 mptsas_list_add(mptsas_t *mpt)
1979 2170 {
1980 2171 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1981 2172
1982 2173 if (mptsas_head == NULL) {
1983 2174 mptsas_head = mpt;
1984 2175 } else {
1985 2176 mptsas_tail->m_next = mpt;
1986 2177 }
1987 2178 mptsas_tail = mpt;
1988 2179 rw_exit(&mptsas_global_rwlock);
1989 2180 }
1990 2181
1991 2182 static void
1992 2183 mptsas_list_del(mptsas_t *mpt)
1993 2184 {
1994 2185 mptsas_t *m;
1995 2186 /*
1996 2187 * Remove device instance from the global linked list
1997 2188 */
1998 2189 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1999 2190 if (mptsas_head == mpt) {
2000 2191 m = mptsas_head = mpt->m_next;
2001 2192 } else {
2002 2193 for (m = mptsas_head; m != NULL; m = m->m_next) {
2003 2194 if (m->m_next == mpt) {
2004 2195 m->m_next = mpt->m_next;
2005 2196 break;
2006 2197 }
2007 2198 }
2008 2199 if (m == NULL) {
2009 2200 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
2010 2201 }
2011 2202 }
2012 2203
2013 2204 if (mptsas_tail == mpt) {
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2014 2205 mptsas_tail = m;
2015 2206 }
2016 2207 rw_exit(&mptsas_global_rwlock);
2017 2208 }
2018 2209
2019 2210 static int
2020 2211 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
2021 2212 {
2022 2213 ddi_dma_attr_t task_dma_attrs;
2023 2214
2215 + mpt->m_hshk_dma_size = 0;
2024 2216 task_dma_attrs = mpt->m_msg_dma_attr;
2025 2217 task_dma_attrs.dma_attr_sgllen = 1;
2026 2218 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
2027 2219
2028 2220 /* allocate Task Management ddi_dma resources */
2029 2221 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
2030 2222 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
2031 2223 alloc_size, NULL) == FALSE) {
2032 2224 return (DDI_FAILURE);
2033 2225 }
2034 2226 mpt->m_hshk_dma_size = alloc_size;
2035 2227
2036 2228 return (DDI_SUCCESS);
2037 2229 }
2038 2230
2039 2231 static void
2040 2232 mptsas_free_handshake_msg(mptsas_t *mpt)
2041 2233 {
2234 + if (mpt->m_hshk_dma_size == 0)
2235 + return;
2042 2236 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
2043 2237 mpt->m_hshk_dma_size = 0;
2044 2238 }
2045 2239
2046 2240 static int
2047 2241 mptsas_hba_setup(mptsas_t *mpt)
2048 2242 {
2049 2243 scsi_hba_tran_t *hba_tran;
2050 2244 int tran_flags;
2051 2245
2052 2246 /* Allocate a transport structure */
2053 2247 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
2054 2248 SCSI_HBA_CANSLEEP);
2055 2249 ASSERT(mpt->m_tran != NULL);
2056 2250
2057 2251 hba_tran->tran_hba_private = mpt;
2058 2252 hba_tran->tran_tgt_private = NULL;
2059 2253
2060 2254 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
2061 2255 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
2062 2256
2063 2257 hba_tran->tran_start = mptsas_scsi_start;
2064 2258 hba_tran->tran_reset = mptsas_scsi_reset;
2065 2259 hba_tran->tran_abort = mptsas_scsi_abort;
2066 2260 hba_tran->tran_getcap = mptsas_scsi_getcap;
2067 2261 hba_tran->tran_setcap = mptsas_scsi_setcap;
2068 2262 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
2069 2263 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
2070 2264
2071 2265 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
2072 2266 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
2073 2267 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
2074 2268
2075 2269 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
2076 2270 hba_tran->tran_get_name = mptsas_get_name;
2077 2271
2078 2272 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
2079 2273 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
2080 2274 hba_tran->tran_bus_reset = NULL;
2081 2275
2082 2276 hba_tran->tran_add_eventcall = NULL;
2083 2277 hba_tran->tran_get_eventcookie = NULL;
2084 2278 hba_tran->tran_post_event = NULL;
2085 2279 hba_tran->tran_remove_eventcall = NULL;
2086 2280
2087 2281 hba_tran->tran_bus_config = mptsas_bus_config;
2088 2282
2089 2283 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2090 2284
2091 2285 /*
2092 2286 * All children of the HBA are iports. We need tran was cloned.
2093 2287 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2094 2288 * inherited to iport's tran vector.
2095 2289 */
2096 2290 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2097 2291
2098 2292 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2099 2293 hba_tran, tran_flags) != DDI_SUCCESS) {
2100 2294 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2101 2295 scsi_hba_tran_free(hba_tran);
2102 2296 mpt->m_tran = NULL;
2103 2297 return (FALSE);
2104 2298 }
2105 2299 return (TRUE);
2106 2300 }
2107 2301
2108 2302 static void
2109 2303 mptsas_hba_teardown(mptsas_t *mpt)
2110 2304 {
2111 2305 (void) scsi_hba_detach(mpt->m_dip);
2112 2306 if (mpt->m_tran != NULL) {
2113 2307 scsi_hba_tran_free(mpt->m_tran);
2114 2308 mpt->m_tran = NULL;
2115 2309 }
2116 2310 }
2117 2311
2118 2312 static void
2119 2313 mptsas_iport_register(mptsas_t *mpt)
2120 2314 {
2121 2315 int i, j;
2122 2316 mptsas_phymask_t mask = 0x0;
2123 2317 /*
2124 2318 * initial value of mask is 0
2125 2319 */
2126 2320 mutex_enter(&mpt->m_mutex);
2127 2321 for (i = 0; i < mpt->m_num_phys; i++) {
2128 2322 mptsas_phymask_t phy_mask = 0x0;
2129 2323 char phy_mask_name[MPTSAS_MAX_PHYS];
2130 2324 uint8_t current_port;
2131 2325
2132 2326 if (mpt->m_phy_info[i].attached_devhdl == 0)
2133 2327 continue;
2134 2328
2135 2329 bzero(phy_mask_name, sizeof (phy_mask_name));
2136 2330
2137 2331 current_port = mpt->m_phy_info[i].port_num;
2138 2332
2139 2333 if ((mask & (1 << i)) != 0)
2140 2334 continue;
2141 2335
2142 2336 for (j = 0; j < mpt->m_num_phys; j++) {
2143 2337 if (mpt->m_phy_info[j].attached_devhdl &&
2144 2338 (mpt->m_phy_info[j].port_num == current_port)) {
2145 2339 phy_mask |= (1 << j);
2146 2340 }
2147 2341 }
2148 2342 mask = mask | phy_mask;
2149 2343
2150 2344 for (j = 0; j < mpt->m_num_phys; j++) {
2151 2345 if ((phy_mask >> j) & 0x01) {
2152 2346 mpt->m_phy_info[j].phy_mask = phy_mask;
2153 2347 }
2154 2348 }
2155 2349
2156 2350 (void) sprintf(phy_mask_name, "%x", phy_mask);
2157 2351
2158 2352 mutex_exit(&mpt->m_mutex);
2159 2353 /*
2160 2354 * register a iport
2161 2355 */
2162 2356 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2163 2357 mutex_enter(&mpt->m_mutex);
2164 2358 }
2165 2359 mutex_exit(&mpt->m_mutex);
2166 2360 /*
2167 2361 * register a virtual port for RAID volume always
2168 2362 */
2169 2363 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2170 2364
2171 2365 }
2172 2366
2173 2367 static int
2174 2368 mptsas_smp_setup(mptsas_t *mpt)
2175 2369 {
2176 2370 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2177 2371 ASSERT(mpt->m_smptran != NULL);
2178 2372 mpt->m_smptran->smp_tran_hba_private = mpt;
2179 2373 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2180 2374 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2181 2375 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2182 2376 smp_hba_tran_free(mpt->m_smptran);
2183 2377 mpt->m_smptran = NULL;
2184 2378 return (FALSE);
2185 2379 }
2186 2380 /*
2187 2381 * Initialize smp hash table
2188 2382 */
2189 2383 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT,
2190 2384 mptsas_target_addr_hash, mptsas_target_addr_cmp,
2191 2385 mptsas_smp_free, sizeof (mptsas_smp_t),
2192 2386 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr),
2193 2387 KM_SLEEP);
2194 2388 mpt->m_smp_devhdl = 0xFFFF;
2195 2389
2196 2390 return (TRUE);
2197 2391 }
2198 2392
2199 2393 static void
2200 2394 mptsas_smp_teardown(mptsas_t *mpt)
2201 2395 {
2202 2396 (void) smp_hba_detach(mpt->m_dip);
2203 2397 if (mpt->m_smptran != NULL) {
2204 2398 smp_hba_tran_free(mpt->m_smptran);
2205 2399 mpt->m_smptran = NULL;
2206 2400 }
2207 2401 mpt->m_smp_devhdl = 0;
2208 2402 }
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2209 2403
2210 2404 static int
2211 2405 mptsas_cache_create(mptsas_t *mpt)
2212 2406 {
2213 2407 int instance = mpt->m_instance;
2214 2408 char buf[64];
2215 2409
2216 2410 /*
2217 2411 * create kmem cache for packets
2218 2412 */
2219 - (void) sprintf(buf, "mptsas%d_cache", instance);
2413 + (void) sprintf(buf, "mptsas3%d_cache", instance);
2220 2414 mpt->m_kmem_cache = kmem_cache_create(buf,
2221 - sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2415 + sizeof (struct mptsas_cmd) + scsi_pkt_size(), 16,
2222 2416 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2223 2417 NULL, (void *)mpt, NULL, 0);
2224 2418
2225 2419 if (mpt->m_kmem_cache == NULL) {
2226 2420 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2227 2421 return (FALSE);
2228 2422 }
2229 2423
2230 2424 /*
2231 2425 * create kmem cache for extra SGL frames if SGL cannot
2232 2426 * be accomodated into main request frame.
2233 2427 */
2234 - (void) sprintf(buf, "mptsas%d_cache_frames", instance);
2428 + (void) sprintf(buf, "mptsas3%d_cache_frames", instance);
2235 2429 mpt->m_cache_frames = kmem_cache_create(buf,
2236 - sizeof (mptsas_cache_frames_t), 8,
2430 + sizeof (mptsas_cache_frames_t), 16,
2237 2431 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2238 2432 NULL, (void *)mpt, NULL, 0);
2239 2433
2240 2434 if (mpt->m_cache_frames == NULL) {
2241 2435 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2242 2436 return (FALSE);
2243 2437 }
2244 2438
2245 2439 return (TRUE);
2246 2440 }
2247 2441
2248 2442 static void
2249 2443 mptsas_cache_destroy(mptsas_t *mpt)
2250 2444 {
2251 2445 /* deallocate in reverse order */
2252 2446 if (mpt->m_cache_frames) {
2253 2447 kmem_cache_destroy(mpt->m_cache_frames);
2254 2448 mpt->m_cache_frames = NULL;
2255 2449 }
2256 2450 if (mpt->m_kmem_cache) {
2257 2451 kmem_cache_destroy(mpt->m_kmem_cache);
2258 2452 mpt->m_kmem_cache = NULL;
2259 2453 }
2260 2454 }
2261 2455
2262 2456 static int
2263 2457 mptsas_power(dev_info_t *dip, int component, int level)
2264 2458 {
2265 2459 #ifndef __lock_lint
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2266 2460 _NOTE(ARGUNUSED(component))
2267 2461 #endif
2268 2462 mptsas_t *mpt;
2269 2463 int rval = DDI_SUCCESS;
2270 2464 int polls = 0;
2271 2465 uint32_t ioc_status;
2272 2466
2273 2467 if (scsi_hba_iport_unit_address(dip) != 0)
2274 2468 return (DDI_SUCCESS);
2275 2469
2276 - mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2470 + mpt = ddi_get_soft_state(mptsas3_state, ddi_get_instance(dip));
2277 2471 if (mpt == NULL) {
2278 2472 return (DDI_FAILURE);
2279 2473 }
2280 2474
2281 2475 mutex_enter(&mpt->m_mutex);
2282 2476
2283 2477 /*
2284 2478 * If the device is busy, don't lower its power level
2285 2479 */
2286 2480 if (mpt->m_busy && (mpt->m_power_level > level)) {
2287 2481 mutex_exit(&mpt->m_mutex);
2288 2482 return (DDI_FAILURE);
2289 2483 }
2290 2484 switch (level) {
2291 2485 case PM_LEVEL_D0:
2292 - NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2486 + NDBG11(("mptsas3%d: turning power ON.", mpt->m_instance));
2293 2487 MPTSAS_POWER_ON(mpt);
2294 2488 /*
2295 2489 * Wait up to 30 seconds for IOC to come out of reset.
2296 2490 */
2297 2491 while (((ioc_status = ddi_get32(mpt->m_datap,
2298 2492 &mpt->m_reg->Doorbell)) &
2299 2493 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2300 2494 if (polls++ > 3000) {
2301 2495 break;
2302 2496 }
2303 2497 delay(drv_usectohz(10000));
2304 2498 }
2305 2499 /*
2306 2500 * If IOC is not in operational state, try to hard reset it.
2307 2501 */
2308 2502 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2309 2503 MPI2_IOC_STATE_OPERATIONAL) {
2310 2504 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
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2311 2505 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2312 2506 mptsas_log(mpt, CE_WARN,
2313 2507 "mptsas_power: hard reset failed");
2314 2508 mutex_exit(&mpt->m_mutex);
2315 2509 return (DDI_FAILURE);
2316 2510 }
2317 2511 }
2318 2512 mpt->m_power_level = PM_LEVEL_D0;
2319 2513 break;
2320 2514 case PM_LEVEL_D3:
2321 - NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2515 + NDBG11(("mptsas3%d: turning power OFF.", mpt->m_instance));
2322 2516 MPTSAS_POWER_OFF(mpt);
2323 2517 break;
2324 2518 default:
2325 - mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2519 + mptsas_log(mpt, CE_WARN, "mptsas3%d: unknown power level <%x>.",
2326 2520 mpt->m_instance, level);
2327 2521 rval = DDI_FAILURE;
2328 2522 break;
2329 2523 }
2330 2524 mutex_exit(&mpt->m_mutex);
2331 2525 return (rval);
2332 2526 }
2333 2527
2334 2528 /*
2335 2529 * Initialize configuration space and figure out which
2336 2530 * chip and revison of the chip the mpt driver is using.
2337 2531 */
2338 2532 static int
2339 2533 mptsas_config_space_init(mptsas_t *mpt)
2340 2534 {
2341 2535 NDBG0(("mptsas_config_space_init"));
2342 2536
2343 2537 if (mpt->m_config_handle != NULL)
2344 2538 return (TRUE);
2345 2539
2346 2540 if (pci_config_setup(mpt->m_dip,
2347 2541 &mpt->m_config_handle) != DDI_SUCCESS) {
2348 2542 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2349 2543 return (FALSE);
2350 2544 }
2351 2545
2352 2546 /*
2353 2547 * This is a workaround for a XMITS ASIC bug which does not
2354 2548 * drive the CBE upper bits.
2355 2549 */
2356 2550 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2357 2551 PCI_STAT_PERROR) {
2358 2552 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2359 2553 PCI_STAT_PERROR);
2360 2554 }
2361 2555
2362 2556 mptsas_setup_cmd_reg(mpt);
2363 2557
2364 2558 /*
2365 2559 * Get the chip device id:
2366 2560 */
2367 2561 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2368 2562
2369 2563 /*
2370 2564 * Save the revision.
2371 2565 */
2372 2566 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2373 2567
2374 2568 /*
2375 2569 * Save the SubSystem Vendor and Device IDs
2376 2570 */
2377 2571 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2378 2572 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2379 2573
2380 2574 /*
2381 2575 * Set the latency timer to 0x40 as specified by the upa -> pci
2382 2576 * bridge chip design team. This may be done by the sparc pci
2383 2577 * bus nexus driver, but the driver should make sure the latency
2384 2578 * timer is correct for performance reasons.
2385 2579 */
2386 2580 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2387 2581 MPTSAS_LATENCY_TIMER);
2388 2582
2389 2583 (void) mptsas_get_pci_cap(mpt);
2390 2584 return (TRUE);
2391 2585 }
2392 2586
2393 2587 static void
2394 2588 mptsas_config_space_fini(mptsas_t *mpt)
2395 2589 {
2396 2590 if (mpt->m_config_handle != NULL) {
2397 2591 mptsas_disable_bus_master(mpt);
2398 2592 pci_config_teardown(&mpt->m_config_handle);
2399 2593 mpt->m_config_handle = NULL;
2400 2594 }
2401 2595 }
2402 2596
2403 2597 static void
2404 2598 mptsas_setup_cmd_reg(mptsas_t *mpt)
2405 2599 {
2406 2600 ushort_t cmdreg;
2407 2601
2408 2602 /*
2409 2603 * Set the command register to the needed values.
2410 2604 */
2411 2605 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2412 2606 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2413 2607 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2414 2608 cmdreg &= ~PCI_COMM_IO;
2415 2609 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2416 2610 }
2417 2611
2418 2612 static void
2419 2613 mptsas_disable_bus_master(mptsas_t *mpt)
2420 2614 {
2421 2615 ushort_t cmdreg;
2422 2616
2423 2617 /*
2424 2618 * Clear the master enable bit in the PCI command register.
2425 2619 * This prevents any bus mastering activity like DMA.
2426 2620 */
2427 2621 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2428 2622 cmdreg &= ~PCI_COMM_ME;
2429 2623 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2430 2624 }
2431 2625
2432 2626 int
2433 2627 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2434 2628 {
2435 2629 ddi_dma_attr_t attrs;
2436 2630
2437 2631 attrs = mpt->m_io_dma_attr;
2438 2632 attrs.dma_attr_sgllen = 1;
2439 2633
2440 2634 ASSERT(dma_statep != NULL);
2441 2635
2442 2636 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2443 2637 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2444 2638 &dma_statep->cookie) == FALSE) {
2445 2639 return (DDI_FAILURE);
2446 2640 }
2447 2641
2448 2642 return (DDI_SUCCESS);
2449 2643 }
2450 2644
2451 2645 void
2452 2646 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2453 2647 {
2454 2648 ASSERT(dma_statep != NULL);
2455 2649 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2456 2650 dma_statep->size = 0;
2457 2651 }
2458 2652
2459 2653 int
2460 2654 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2461 2655 {
2462 2656 ddi_dma_attr_t attrs;
2463 2657 ddi_dma_handle_t dma_handle;
2464 2658 caddr_t memp;
2465 2659 ddi_acc_handle_t accessp;
2466 2660 int rval;
2467 2661
2468 2662 ASSERT(mutex_owned(&mpt->m_mutex));
2469 2663
2470 2664 attrs = mpt->m_msg_dma_attr;
2471 2665 attrs.dma_attr_sgllen = 1;
2472 2666 attrs.dma_attr_granular = size;
2473 2667
2474 2668 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2475 2669 &accessp, &memp, size, NULL) == FALSE) {
2476 2670 return (DDI_FAILURE);
2477 2671 }
2478 2672
2479 2673 rval = (*callback) (mpt, memp, var, accessp);
2480 2674
2481 2675 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2482 2676 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2483 2677 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2484 2678 rval = DDI_FAILURE;
2485 2679 }
2486 2680
2487 2681 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2488 2682 return (rval);
2489 2683
2490 2684 }
2491 2685
2492 2686 static int
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2493 2687 mptsas_alloc_request_frames(mptsas_t *mpt)
2494 2688 {
2495 2689 ddi_dma_attr_t frame_dma_attrs;
2496 2690 caddr_t memp;
2497 2691 ddi_dma_cookie_t cookie;
2498 2692 size_t mem_size;
2499 2693
2500 2694 /*
2501 2695 * re-alloc when it has already alloced
2502 2696 */
2503 - mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2504 - &mpt->m_acc_req_frame_hdl);
2697 + if (mpt->m_dma_flags & MPTSAS_REQ_FRAME) {
2698 + mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2699 + &mpt->m_acc_req_frame_hdl);
2700 + mpt->m_dma_flags &= ~MPTSAS_REQ_FRAME;
2701 + }
2505 2702
2506 2703 /*
2507 2704 * The size of the request frame pool is:
2508 2705 * Number of Request Frames * Request Frame Size
2509 2706 */
2510 2707 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2511 2708
2512 2709 /*
2513 2710 * set the DMA attributes. System Request Message Frames must be
2514 2711 * aligned on a 16-byte boundry.
2515 2712 */
2516 2713 frame_dma_attrs = mpt->m_msg_dma_attr;
2517 2714 frame_dma_attrs.dma_attr_align = 16;
2518 2715 frame_dma_attrs.dma_attr_sgllen = 1;
2519 2716
2520 2717 /*
2521 2718 * allocate the request frame pool.
2522 2719 */
2523 2720 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2524 2721 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2525 2722 mem_size, &cookie) == FALSE) {
2526 2723 return (DDI_FAILURE);
2527 2724 }
2528 2725
2529 2726 /*
2530 2727 * Store the request frame memory address. This chip uses this
2531 2728 * address to dma to and from the driver's frame. The second
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2532 2729 * address is the address mpt uses to fill in the frame.
2533 2730 */
2534 2731 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2535 2732 mpt->m_req_frame = memp;
2536 2733
2537 2734 /*
2538 2735 * Clear the request frame pool.
2539 2736 */
2540 2737 bzero(mpt->m_req_frame, mem_size);
2541 2738
2739 + mpt->m_dma_flags |= MPTSAS_REQ_FRAME;
2740 + return (DDI_SUCCESS);
2741 +}
2742 +
2743 +static int
2744 +mptsas_alloc_sense_bufs(mptsas_t *mpt)
2745 +{
2746 + ddi_dma_attr_t sense_dma_attrs;
2747 + caddr_t memp;
2748 + ddi_dma_cookie_t cookie;
2749 + size_t mem_size;
2750 + int num_extrqsense_bufs;
2751 +
2752 + /*
2753 + * re-alloc when it has already alloced
2754 + */
2755 + if (mpt->m_dma_flags & MPTSAS_REQ_SENSE) {
2756 + rmfreemap(mpt->m_erqsense_map);
2757 + mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2758 + &mpt->m_acc_req_sense_hdl);
2759 + mpt->m_dma_flags &= ~MPTSAS_REQ_SENSE;
2760 + }
2761 +
2762 + /*
2763 + * The size of the request sense pool is:
2764 + * (Number of Request Frames - 2 ) * Request Sense Size +
2765 + * extra memory for extended sense requests.
2766 + */
2767 + mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) +
2768 + mptsas_extreq_sense_bufsize;
2769 +
2770 + /*
2771 + * set the DMA attributes. ARQ buffers
2772 + * aligned on a 16-byte boundry.
2773 + */
2774 + sense_dma_attrs = mpt->m_msg_dma_attr;
2775 + sense_dma_attrs.dma_attr_align = 16;
2776 + sense_dma_attrs.dma_attr_sgllen = 1;
2777 +
2778 + /*
2779 + * allocate the request sense buffer pool.
2780 + */
2781 + if (mptsas_dma_addr_create(mpt, sense_dma_attrs,
2782 + &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp,
2783 + mem_size, &cookie) == FALSE) {
2784 + return (DDI_FAILURE);
2785 + }
2786 +
2787 + /*
2788 + * Store the request sense base memory address. This chip uses this
2789 + * address to dma the request sense data. The second
2790 + * address is the address mpt uses to access the data.
2791 + * The third is the base for the extended rqsense buffers.
2792 + */
2793 + mpt->m_req_sense_dma_addr = cookie.dmac_laddress;
2794 + mpt->m_req_sense = memp;
2795 + memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size;
2796 + mpt->m_extreq_sense = memp;
2797 +
2798 + /*
2799 + * The extra memory is divided up into multiples of the base
2800 + * buffer size in order to allocate via rmalloc().
2801 + * Note that the rmallocmap cannot start at zero!
2802 + */
2803 + num_extrqsense_bufs = mptsas_extreq_sense_bufsize /
2804 + mpt->m_req_sense_size;
2805 + mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs);
2806 + rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1);
2807 +
2808 + /*
2809 + * Clear the pool.
2810 + */
2811 + bzero(mpt->m_req_sense, mem_size);
2812 +
2813 + mpt->m_dma_flags |= MPTSAS_REQ_SENSE;
2542 2814 return (DDI_SUCCESS);
2543 2815 }
2544 2816
2545 2817 static int
2546 2818 mptsas_alloc_reply_frames(mptsas_t *mpt)
2547 2819 {
2548 2820 ddi_dma_attr_t frame_dma_attrs;
2549 2821 caddr_t memp;
2550 2822 ddi_dma_cookie_t cookie;
2551 2823 size_t mem_size;
2552 2824
2553 2825 /*
2554 2826 * re-alloc when it has already alloced
2555 2827 */
2556 - mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2557 - &mpt->m_acc_reply_frame_hdl);
2828 + if (mpt->m_dma_flags & MPTSAS_REPLY_FRAME) {
2829 + mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2830 + &mpt->m_acc_reply_frame_hdl);
2831 + mpt->m_dma_flags &= ~MPTSAS_REPLY_FRAME;
2832 + }
2558 2833
2559 2834 /*
2560 2835 * The size of the reply frame pool is:
2561 2836 * Number of Reply Frames * Reply Frame Size
2562 2837 */
2563 2838 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2564 2839
2565 2840 /*
2566 2841 * set the DMA attributes. System Reply Message Frames must be
2567 2842 * aligned on a 4-byte boundry. This is the default.
2568 2843 */
2569 2844 frame_dma_attrs = mpt->m_msg_dma_attr;
2570 2845 frame_dma_attrs.dma_attr_sgllen = 1;
2571 2846
2572 2847 /*
2573 2848 * allocate the reply frame pool
2574 2849 */
2575 2850 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2576 2851 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2577 2852 mem_size, &cookie) == FALSE) {
2578 2853 return (DDI_FAILURE);
2579 2854 }
2580 2855
2581 2856 /*
2582 2857 * Store the reply frame memory address. This chip uses this
2583 2858 * address to dma to and from the driver's frame. The second
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2584 2859 * address is the address mpt uses to process the frame.
2585 2860 */
2586 2861 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2587 2862 mpt->m_reply_frame = memp;
2588 2863
2589 2864 /*
2590 2865 * Clear the reply frame pool.
2591 2866 */
2592 2867 bzero(mpt->m_reply_frame, mem_size);
2593 2868
2869 + mpt->m_dma_flags |= MPTSAS_REPLY_FRAME;
2594 2870 return (DDI_SUCCESS);
2595 2871 }
2596 2872
2597 2873 static int
2598 2874 mptsas_alloc_free_queue(mptsas_t *mpt)
2599 2875 {
2600 2876 ddi_dma_attr_t frame_dma_attrs;
2601 2877 caddr_t memp;
2602 2878 ddi_dma_cookie_t cookie;
2603 2879 size_t mem_size;
2604 2880
2605 2881 /*
2606 2882 * re-alloc when it has already alloced
2607 2883 */
2608 - mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2609 - &mpt->m_acc_free_queue_hdl);
2884 + if (mpt->m_dma_flags & MPTSAS_FREE_QUEUE) {
2885 + mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2886 + &mpt->m_acc_free_queue_hdl);
2887 + mpt->m_dma_flags &= ~MPTSAS_FREE_QUEUE;
2888 + }
2610 2889
2611 2890 /*
2612 2891 * The reply free queue size is:
2613 2892 * Reply Free Queue Depth * 4
2614 2893 * The "4" is the size of one 32 bit address (low part of 64-bit
2615 2894 * address)
2616 2895 */
2617 2896 mem_size = mpt->m_free_queue_depth * 4;
2618 2897
2619 2898 /*
2620 2899 * set the DMA attributes The Reply Free Queue must be aligned on a
2621 2900 * 16-byte boundry.
2622 2901 */
2623 2902 frame_dma_attrs = mpt->m_msg_dma_attr;
2624 2903 frame_dma_attrs.dma_attr_align = 16;
2625 2904 frame_dma_attrs.dma_attr_sgllen = 1;
2626 2905
2627 2906 /*
2628 2907 * allocate the reply free queue
2629 2908 */
2630 2909 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2631 2910 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2632 2911 mem_size, &cookie) == FALSE) {
2633 2912 return (DDI_FAILURE);
2634 2913 }
2635 2914
2636 2915 /*
2637 2916 * Store the reply free queue memory address. This chip uses this
2638 2917 * address to read from the reply free queue. The second address
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2639 2918 * is the address mpt uses to manage the queue.
2640 2919 */
2641 2920 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2642 2921 mpt->m_free_queue = memp;
2643 2922
2644 2923 /*
2645 2924 * Clear the reply free queue memory.
2646 2925 */
2647 2926 bzero(mpt->m_free_queue, mem_size);
2648 2927
2928 + mpt->m_dma_flags |= MPTSAS_FREE_QUEUE;
2649 2929 return (DDI_SUCCESS);
2650 2930 }
2651 2931
2932 +static void
2933 +mptsas_free_post_queue(mptsas_t *mpt)
2934 +{
2935 + mptsas_reply_pqueue_t *rpqp;
2936 + int i;
2937 +
2938 + if (mpt->m_dma_flags & MPTSAS_POST_QUEUE) {
2939 + mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2940 + &mpt->m_acc_post_queue_hdl);
2941 + rpqp = mpt->m_rep_post_queues;
2942 + for (i = 0; i < mpt->m_post_reply_qcount; i++) {
2943 + mutex_destroy(&rpqp->rpq_mutex);
2944 + rpqp++;
2945 + }
2946 + kmem_free(mpt->m_rep_post_queues,
2947 + sizeof (mptsas_reply_pqueue_t) *
2948 + mpt->m_post_reply_qcount);
2949 + mpt->m_dma_flags &= ~MPTSAS_POST_QUEUE;
2950 + }
2951 +}
2952 +
2652 2953 static int
2653 2954 mptsas_alloc_post_queue(mptsas_t *mpt)
2654 2955 {
2655 2956 ddi_dma_attr_t frame_dma_attrs;
2656 2957 caddr_t memp;
2657 2958 ddi_dma_cookie_t cookie;
2658 2959 size_t mem_size;
2960 + mptsas_reply_pqueue_t *rpqp;
2961 + int i;
2659 2962
2660 2963 /*
2661 2964 * re-alloc when it has already alloced
2662 2965 */
2663 - mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2664 - &mpt->m_acc_post_queue_hdl);
2966 + mptsas_free_post_queue(mpt);
2665 2967
2666 2968 /*
2667 2969 * The reply descriptor post queue size is:
2668 2970 * Reply Descriptor Post Queue Depth * 8
2669 2971 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2670 2972 */
2671 - mem_size = mpt->m_post_queue_depth * 8;
2973 + mpt->m_post_reply_qcount = mpt->m_intr_cnt;
2974 + mem_size = mpt->m_post_queue_depth * 8 * mpt->m_post_reply_qcount;
2672 2975
2673 2976 /*
2674 2977 * set the DMA attributes. The Reply Descriptor Post Queue must be
2675 2978 * aligned on a 16-byte boundry.
2676 2979 */
2677 2980 frame_dma_attrs = mpt->m_msg_dma_attr;
2678 2981 frame_dma_attrs.dma_attr_align = 16;
2679 2982 frame_dma_attrs.dma_attr_sgllen = 1;
2680 2983
2681 2984 /*
2682 - * allocate the reply post queue
2985 + * Allocate the reply post queue(s).
2986 + * MPI2.5 introduces a method to allocate multiple queues
2987 + * using a redirect table. For now stick to one contiguous
2988 + * chunck. This can get as big as 1Mbyte for 16 queues.
2989 + * The spec gives no indication that the queue size can be
2990 + * reduced if you have many of them.
2683 2991 */
2684 2992 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2685 2993 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2686 2994 mem_size, &cookie) == FALSE) {
2687 2995 return (DDI_FAILURE);
2688 2996 }
2689 2997
2690 2998 /*
2691 2999 * Store the reply descriptor post queue memory address. This chip
2692 3000 * uses this address to write to the reply descriptor post queue. The
2693 3001 * second address is the address mpt uses to manage the queue.
2694 3002 */
2695 3003 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2696 3004 mpt->m_post_queue = memp;
2697 3005
3006 + mpt->m_rep_post_queues = kmem_zalloc(sizeof (mptsas_reply_pqueue_t) *
3007 + mpt->m_post_reply_qcount, KM_SLEEP);
3008 + rpqp = mpt->m_rep_post_queues;
3009 + for (i = 0; i < mpt->m_post_reply_qcount; i++) {
3010 + rpqp->rpq_queue = memp;
3011 + mutex_init(&rpqp->rpq_mutex, NULL, MUTEX_DRIVER, NULL);
3012 + rpqp->rpq_dlist.dl_tail = &rpqp->rpq_dlist.dl_q;
3013 + rpqp->rpq_num = (uint8_t)i;
3014 + memp += (mpt->m_post_queue_depth * 8);
3015 + rpqp++;
3016 + }
3017 +
2698 3018 /*
2699 3019 * Clear the reply post queue memory.
2700 3020 */
2701 3021 bzero(mpt->m_post_queue, mem_size);
2702 3022
3023 + mpt->m_dma_flags |= MPTSAS_POST_QUEUE;
2703 3024 return (DDI_SUCCESS);
2704 3025 }
2705 3026
2706 3027 static void
2707 3028 mptsas_alloc_reply_args(mptsas_t *mpt)
2708 3029 {
2709 3030 if (mpt->m_replyh_args == NULL) {
2710 3031 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2711 3032 mpt->m_max_replies, KM_SLEEP);
3033 + } else {
3034 + bzero(mpt->m_replyh_args, sizeof (m_replyh_arg_t) *
3035 + mpt->m_max_replies);
2712 3036 }
2713 3037 }
2714 3038
2715 3039 static int
2716 3040 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2717 3041 {
2718 3042 mptsas_cache_frames_t *frames = NULL;
2719 3043 if (cmd->cmd_extra_frames == NULL) {
2720 3044 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2721 3045 if (frames == NULL) {
2722 3046 return (DDI_FAILURE);
2723 3047 }
2724 3048 cmd->cmd_extra_frames = frames;
2725 3049 }
2726 3050 return (DDI_SUCCESS);
2727 3051 }
2728 3052
2729 3053 static void
2730 3054 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2731 3055 {
2732 3056 if (cmd->cmd_extra_frames) {
2733 3057 kmem_cache_free(mpt->m_cache_frames,
2734 3058 (void *)cmd->cmd_extra_frames);
2735 3059 cmd->cmd_extra_frames = NULL;
2736 3060 }
2737 3061 }
2738 3062
2739 3063 static void
2740 3064 mptsas_cfg_fini(mptsas_t *mpt)
2741 3065 {
2742 3066 NDBG0(("mptsas_cfg_fini"));
2743 3067 ddi_regs_map_free(&mpt->m_datap);
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2744 3068 }
2745 3069
2746 3070 static void
2747 3071 mptsas_hba_fini(mptsas_t *mpt)
2748 3072 {
2749 3073 NDBG0(("mptsas_hba_fini"));
2750 3074
2751 3075 /*
2752 3076 * Free up any allocated memory
2753 3077 */
2754 - mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2755 - &mpt->m_acc_req_frame_hdl);
3078 + if (mpt->m_dma_flags & MPTSAS_REQ_FRAME) {
3079 + mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
3080 + &mpt->m_acc_req_frame_hdl);
3081 + }
3082 +
3083 + if (mpt->m_dma_flags & MPTSAS_REQ_SENSE) {
3084 + rmfreemap(mpt->m_erqsense_map);
3085 + mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
3086 + &mpt->m_acc_req_sense_hdl);
3087 + }
2756 3088
2757 - mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2758 - &mpt->m_acc_reply_frame_hdl);
3089 + if (mpt->m_dma_flags & MPTSAS_REPLY_FRAME) {
3090 + mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
3091 + &mpt->m_acc_reply_frame_hdl);
3092 + }
2759 3093
2760 - mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2761 - &mpt->m_acc_free_queue_hdl);
3094 + if (mpt->m_dma_flags & MPTSAS_FREE_QUEUE) {
3095 + mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
3096 + &mpt->m_acc_free_queue_hdl);
3097 + }
2762 3098
2763 - mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2764 - &mpt->m_acc_post_queue_hdl);
3099 + mptsas_free_post_queue(mpt);
2765 3100
2766 3101 if (mpt->m_replyh_args != NULL) {
2767 3102 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2768 3103 * mpt->m_max_replies);
2769 3104 }
2770 3105 }
2771 3106
2772 3107 static int
2773 3108 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
2774 3109 {
2775 3110 int lun = 0;
2776 3111 char *sas_wwn = NULL;
2777 3112 int phynum = -1;
2778 3113 int reallen = 0;
2779 3114
2780 3115 /* Get the target num */
2781 3116 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
2782 3117 LUN_PROP, 0);
2783 3118
2784 3119 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
2785 3120 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
2786 3121 /*
2787 3122 * Stick in the address of form "pPHY,LUN"
2788 3123 */
2789 3124 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
2790 3125 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
2791 3126 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
2792 3127 == DDI_PROP_SUCCESS) {
2793 3128 /*
2794 3129 * Stick in the address of the form "wWWN,LUN"
2795 3130 */
2796 3131 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
2797 3132 ddi_prop_free(sas_wwn);
2798 3133 } else {
2799 3134 return (DDI_FAILURE);
2800 3135 }
2801 3136
2802 3137 ASSERT(reallen < len);
2803 3138 if (reallen >= len) {
2804 3139 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
2805 3140 "length too small, it needs to be %d bytes", reallen + 1);
2806 3141 }
2807 3142 return (DDI_SUCCESS);
2808 3143 }
2809 3144
2810 3145 /*
2811 3146 * tran_tgt_init(9E) - target device instance initialization
2812 3147 */
2813 3148 static int
2814 3149 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2815 3150 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2816 3151 {
2817 3152 #ifndef __lock_lint
2818 3153 _NOTE(ARGUNUSED(hba_tran))
2819 3154 #endif
2820 3155
2821 3156 /*
2822 3157 * At this point, the scsi_device structure already exists
2823 3158 * and has been initialized.
2824 3159 *
2825 3160 * Use this function to allocate target-private data structures,
2826 3161 * if needed by this HBA. Add revised flow-control and queue
2827 3162 * properties for child here, if desired and if you can tell they
2828 3163 * support tagged queueing by now.
2829 3164 */
2830 3165 mptsas_t *mpt;
2831 3166 int lun = sd->sd_address.a_lun;
2832 3167 mdi_pathinfo_t *pip = NULL;
2833 3168 mptsas_tgt_private_t *tgt_private = NULL;
2834 3169 mptsas_target_t *ptgt = NULL;
2835 3170 char *psas_wwn = NULL;
2836 3171 mptsas_phymask_t phymask = 0;
2837 3172 uint64_t sas_wwn = 0;
2838 3173 mptsas_target_addr_t addr;
2839 3174 mpt = SDEV2MPT(sd);
2840 3175
2841 3176 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
2842 3177
2843 3178 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
2844 3179 (void *)hba_dip, (void *)tgt_dip, lun));
2845 3180
2846 3181 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
2847 3182 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
2848 3183 ddi_set_name_addr(tgt_dip, NULL);
2849 3184 return (DDI_FAILURE);
2850 3185 }
2851 3186 /*
2852 3187 * phymask is 0 means the virtual port for RAID
2853 3188 */
2854 3189 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
2855 3190 "phymask", 0);
2856 3191 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2857 3192 if ((pip = (void *)(sd->sd_private)) == NULL) {
2858 3193 /*
2859 3194 * Very bad news if this occurs. Somehow scsi_vhci has
2860 3195 * lost the pathinfo node for this target.
2861 3196 */
2862 3197 return (DDI_NOT_WELL_FORMED);
2863 3198 }
2864 3199
2865 3200 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
2866 3201 DDI_PROP_SUCCESS) {
2867 3202 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
2868 3203 return (DDI_FAILURE);
2869 3204 }
2870 3205
2871 3206 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
2872 3207 &psas_wwn) == MDI_SUCCESS) {
2873 3208 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2874 3209 sas_wwn = 0;
2875 3210 }
2876 3211 (void) mdi_prop_free(psas_wwn);
2877 3212 }
2878 3213 } else {
2879 3214 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
2880 3215 DDI_PROP_DONTPASS, LUN_PROP, 0);
2881 3216 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
2882 3217 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
2883 3218 DDI_PROP_SUCCESS) {
2884 3219 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2885 3220 sas_wwn = 0;
2886 3221 }
2887 3222 ddi_prop_free(psas_wwn);
2888 3223 } else {
2889 3224 sas_wwn = 0;
2890 3225 }
2891 3226 }
2892 3227
2893 3228 ASSERT((sas_wwn != 0) || (phymask != 0));
2894 3229 addr.mta_wwn = sas_wwn;
2895 3230 addr.mta_phymask = phymask;
2896 3231 mutex_enter(&mpt->m_mutex);
2897 3232 ptgt = refhash_lookup(mpt->m_targets, &addr);
2898 3233 mutex_exit(&mpt->m_mutex);
2899 3234 if (ptgt == NULL) {
2900 3235 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
2901 3236 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
2902 3237 sas_wwn);
2903 3238 return (DDI_FAILURE);
2904 3239 }
2905 3240 if (hba_tran->tran_tgt_private == NULL) {
2906 3241 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
2907 3242 KM_SLEEP);
2908 3243 tgt_private->t_lun = lun;
2909 3244 tgt_private->t_private = ptgt;
2910 3245 hba_tran->tran_tgt_private = tgt_private;
2911 3246 }
2912 3247
2913 3248 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2914 3249 return (DDI_SUCCESS);
2915 3250 }
2916 3251 mutex_enter(&mpt->m_mutex);
2917 3252
2918 3253 if (ptgt->m_deviceinfo &
2919 3254 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
2920 3255 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
2921 3256 uchar_t *inq89 = NULL;
2922 3257 int inq89_len = 0x238;
2923 3258 int reallen = 0;
2924 3259 int rval = 0;
2925 3260 struct sata_id *sid = NULL;
2926 3261 char model[SATA_ID_MODEL_LEN + 1];
2927 3262 char fw[SATA_ID_FW_LEN + 1];
2928 3263 char *vid, *pid;
2929 3264 int i;
2930 3265
2931 3266 mutex_exit(&mpt->m_mutex);
2932 3267 /*
2933 3268 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
2934 3269 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
2935 3270 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
2936 3271 */
2937 3272 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
2938 3273 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
2939 3274 inq89, inq89_len, &reallen, 1);
2940 3275
2941 3276 if (rval != 0) {
2942 3277 if (inq89 != NULL) {
2943 3278 kmem_free(inq89, inq89_len);
2944 3279 }
2945 3280
2946 3281 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
2947 3282 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
2948 3283 return (DDI_SUCCESS);
2949 3284 }
2950 3285 sid = (void *)(&inq89[60]);
2951 3286
2952 3287 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
2953 3288 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
2954 3289
2955 3290 model[SATA_ID_MODEL_LEN] = 0;
2956 3291 fw[SATA_ID_FW_LEN] = 0;
2957 3292
2958 3293 /*
2959 3294 * split model into into vid/pid
2960 3295 */
2961 3296 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++)
2962 3297 if ((*pid == ' ') || (*pid == '\t'))
2963 3298 break;
2964 3299 if (i < SATA_ID_MODEL_LEN) {
2965 3300 vid = model;
2966 3301 /*
2967 3302 * terminate vid, establish pid
2968 3303 */
2969 3304 *pid++ = 0;
2970 3305 } else {
2971 3306 /*
2972 3307 * vid will stay "ATA ", the rule is same
2973 3308 * as sata framework implementation.
2974 3309 */
2975 3310 vid = NULL;
2976 3311 /*
2977 3312 * model is all pid
2978 3313 */
2979 3314 pid = model;
2980 3315 }
2981 3316
2982 3317 /*
2983 3318 * override SCSA "inquiry-*" properties
2984 3319 */
2985 3320 if (vid)
2986 3321 (void) scsi_device_prop_update_inqstring(sd,
2987 3322 INQUIRY_VENDOR_ID, vid, strlen(vid));
2988 3323 if (pid)
2989 3324 (void) scsi_device_prop_update_inqstring(sd,
2990 3325 INQUIRY_PRODUCT_ID, pid, strlen(pid));
2991 3326 (void) scsi_device_prop_update_inqstring(sd,
2992 3327 INQUIRY_REVISION_ID, fw, strlen(fw));
2993 3328
2994 3329 if (inq89 != NULL) {
2995 3330 kmem_free(inq89, inq89_len);
2996 3331 }
2997 3332 } else {
2998 3333 mutex_exit(&mpt->m_mutex);
2999 3334 }
3000 3335
3001 3336 return (DDI_SUCCESS);
3002 3337 }
3003 3338 /*
3004 3339 * tran_tgt_free(9E) - target device instance deallocation
3005 3340 */
3006 3341 static void
3007 3342 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3008 3343 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3009 3344 {
3010 3345 #ifndef __lock_lint
3011 3346 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
3012 3347 #endif
3013 3348
3014 3349 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
3015 3350
3016 3351 if (tgt_private != NULL) {
3017 3352 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
3018 3353 hba_tran->tran_tgt_private = NULL;
3019 3354 }
3020 3355 }
3021 3356
3022 3357 /*
3023 3358 * scsi_pkt handling
3024 3359 *
3025 3360 * Visible to the external world via the transport structure.
3026 3361 */
3027 3362
3028 3363 /*
3029 3364 * Notes:
3030 3365 * - transport the command to the addressed SCSI target/lun device
3031 3366 * - normal operation is to schedule the command to be transported,
3032 3367 * and return TRAN_ACCEPT if this is successful.
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3033 3368 * - if NO_INTR, tran_start must poll device for command completion
3034 3369 */
3035 3370 static int
3036 3371 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
3037 3372 {
3038 3373 #ifndef __lock_lint
3039 3374 _NOTE(ARGUNUSED(ap))
3040 3375 #endif
3041 3376 mptsas_t *mpt = PKT2MPT(pkt);
3042 3377 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3043 - int rval;
3378 + int rval, start;
3379 + uint8_t pref;
3044 3380 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3381 + mptsas_tx_waitqueue_t *txwq;
3045 3382
3046 3383 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
3047 3384 ASSERT(ptgt);
3048 3385 if (ptgt == NULL)
3049 3386 return (TRAN_FATAL_ERROR);
3050 3387
3051 3388 /*
3052 3389 * prepare the pkt before taking mutex.
3053 3390 */
3054 3391 rval = mptsas_prepare_pkt(cmd);
3055 3392 if (rval != TRAN_ACCEPT) {
3056 3393 return (rval);
3057 3394 }
3058 3395
3059 3396 /*
3060 3397 * Send the command to target/lun, however your HBA requires it.
3061 3398 * If busy, return TRAN_BUSY; if there's some other formatting error
3062 3399 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
3063 3400 * return of TRAN_ACCEPT.
3064 3401 *
3065 3402 * Remember that access to shared resources, including the mptsas_t
3066 3403 * data structure and the HBA hardware registers, must be protected
3067 3404 * with mutexes, here and everywhere.
3068 3405 *
3069 3406 * Also remember that at interrupt time, you'll get an argument
3070 3407 * to the interrupt handler which is a pointer to your mptsas_t
3071 3408 * structure; you'll have to remember which commands are outstanding
3072 3409 * and which scsi_pkt is the currently-running command so the
3073 3410 * interrupt handler can refer to the pkt to set completion
3074 3411 * status, call the target driver back through pkt_comp, etc.
3075 3412 *
3076 3413 * If the instance lock is held by other thread, don't spin to wait
3077 3414 * for it. Instead, queue the cmd and next time when the instance lock
3078 3415 * is not held, accept all the queued cmd. A extra tx_waitq is
3079 3416 * introduced to protect the queue.
3080 3417 *
3081 3418 * The polled cmd will not be queud and accepted as usual.
3082 3419 *
|
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3083 3420 * Under the tx_waitq mutex, record whether a thread is draining
3084 3421 * the tx_waitq. An IO requesting thread that finds the instance
3085 3422 * mutex contended appends to the tx_waitq and while holding the
3086 3423 * tx_wait mutex, if the draining flag is not set, sets it and then
3087 3424 * proceeds to spin for the instance mutex. This scheme ensures that
3088 3425 * the last cmd in a burst be processed.
3089 3426 *
3090 3427 * we enable this feature only when the helper threads are enabled,
3091 3428 * at which we think the loads are heavy.
3092 3429 *
3093 - * per instance mutex m_tx_waitq_mutex is introduced to protect the
3094 - * m_tx_waitqtail, m_tx_waitq, m_tx_draining.
3430 + * per instance, per queue mutex m_tx_waitq[i].txwq_mutex is
3431 + * introduced to protect the txwq_qtail, txwq_cmdq, txwq_len
3095 3432 */
3096 3433
3097 - if (mpt->m_doneq_thread_n) {
3098 - if (mutex_tryenter(&mpt->m_mutex) != 0) {
3099 - rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3100 - mutex_exit(&mpt->m_mutex);
3101 - } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3102 - mutex_enter(&mpt->m_mutex);
3103 - rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3104 - mutex_exit(&mpt->m_mutex);
3105 - } else {
3106 - mutex_enter(&mpt->m_tx_waitq_mutex);
3107 - /*
3108 - * ptgt->m_dr_flag is protected by m_mutex or
3109 - * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex
3110 - * is acquired.
3111 - */
3112 - if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3113 - if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3114 - /*
3115 - * The command should be allowed to
3116 - * retry by returning TRAN_BUSY to
3117 - * to stall the I/O's which come from
3118 - * scsi_vhci since the device/path is
3119 - * in unstable state now.
3120 - */
3121 - mutex_exit(&mpt->m_tx_waitq_mutex);
3122 - return (TRAN_BUSY);
3123 - } else {
3124 - /*
3125 - * The device is offline, just fail the
3126 - * command by returning
3127 - * TRAN_FATAL_ERROR.
3128 - */
3129 - mutex_exit(&mpt->m_tx_waitq_mutex);
3130 - return (TRAN_FATAL_ERROR);
3434 + if (mpt->m_txwq_enabled == TRUE) {
3435 + int gotmtx = 0;
3436 +
3437 + if (mpt->m_txwq_allow_q_jumping) {
3438 + gotmtx = mutex_tryenter(&mpt->m_mutex);
3439 + }
3440 + if (gotmtx == 0) {
3441 + /* We didn't get the mutex or didn't try */
3442 + if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3443 + mutex_enter(&mpt->m_mutex);
3444 + /* Polled commands queue jump */
3445 + mptsas_accept_tx_waitqs(mpt);
3446 + } else {
3447 + rval = mptsas_check_targ_intxtion(
3448 + cmd->cmd_tgt_addr,
3449 + cmd->cmd_pkt_flags);
3450 + if (rval != TRAN_ACCEPT) {
3451 + return (rval);
3131 3452 }
3132 - }
3133 - if (mpt->m_tx_draining) {
3453 +
3134 3454 cmd->cmd_flags |= CFLAG_TXQ;
3135 - *mpt->m_tx_waitqtail = cmd;
3136 - mpt->m_tx_waitqtail = &cmd->cmd_linkp;
3137 - mutex_exit(&mpt->m_tx_waitq_mutex);
3138 - } else { /* drain the queue */
3139 - mpt->m_tx_draining = 1;
3140 - mutex_exit(&mpt->m_tx_waitq_mutex);
3141 - mutex_enter(&mpt->m_mutex);
3142 - rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3143 - mutex_exit(&mpt->m_mutex);
3455 + pref = mpt->m_pref_tx_waitq;
3456 + txwq = &mpt->m_tx_waitq[pref];
3457 +
3458 + if (mutex_tryenter(&txwq->txwq_mutex) == 0) {
3459 + txwq = &mpt->m_tx_waitq[pref^1];
3460 + mutex_enter(&txwq->txwq_mutex);
3461 + } else {
3462 + pref ^= 1;
3463 + mpt->m_pref_tx_waitq = pref;
3464 + }
3465 +
3466 + *txwq->txwq_qtail = cmd;
3467 + txwq->txwq_qtail = &cmd->cmd_linkp;
3468 + txwq->txwq_len++;
3469 + if (!txwq->txwq_draining) {
3470 + cv_signal(&txwq->txwq_cv);
3471 + }
3472 + mutex_exit(&txwq->txwq_mutex);
3473 + return (rval);
3144 3474 }
3145 3475 }
3146 3476 } else {
3147 3477 mutex_enter(&mpt->m_mutex);
3148 - /*
3149 - * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3150 - * in this case, m_mutex is acquired.
3151 - */
3152 - if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3153 - if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3154 - /*
3155 - * commands should be allowed to retry by
3156 - * returning TRAN_BUSY to stall the I/O's
3157 - * which come from scsi_vhci since the device/
3158 - * path is in unstable state now.
3159 - */
3160 - mutex_exit(&mpt->m_mutex);
3161 - return (TRAN_BUSY);
3162 - } else {
3163 - /*
3164 - * The device is offline, just fail the
3165 - * command by returning TRAN_FATAL_ERROR.
3166 - */
3167 - mutex_exit(&mpt->m_mutex);
3168 - return (TRAN_FATAL_ERROR);
3169 - }
3170 - }
3171 - rval = mptsas_accept_pkt(mpt, cmd);
3478 + }
3479 + rval = mptsas_check_targ_intxtion(cmd->cmd_tgt_addr,
3480 + cmd->cmd_pkt_flags);
3481 + if (rval != TRAN_ACCEPT) {
3172 3482 mutex_exit(&mpt->m_mutex);
3483 + return (rval);
3484 + }
3485 +
3486 + start = mptsas_accept_pkt(mpt, cmd, &rval);
3487 + mutex_exit(&mpt->m_mutex);
3488 + if (start) {
3489 + (void) mptsas_start_cmd(mpt, cmd);
3173 3490 }
3174 3491
3175 3492 return (rval);
3176 3493 }
3177 3494
3178 -/*
3179 - * Accept all the queued cmds(if any) before accept the current one.
3180 - */
3181 3495 static int
3182 -mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3496 +mptsas_check_targ_intxtion(mptsas_target_t *ptgt, int cmd_pkt_flags)
3183 3497 {
3184 - int rval;
3185 - mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3186 -
3187 - ASSERT(mutex_owned(&mpt->m_mutex));
3188 3498 /*
3189 - * The call to mptsas_accept_tx_waitq() must always be performed
3190 - * because that is where mpt->m_tx_draining is cleared.
3191 - */
3192 - mutex_enter(&mpt->m_tx_waitq_mutex);
3193 - mptsas_accept_tx_waitq(mpt);
3194 - mutex_exit(&mpt->m_tx_waitq_mutex);
3195 - /*
3196 - * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3197 - * in this case, m_mutex is acquired.
3499 + * ptgt->m_dr_flag is a variable that is only ever changed by
3500 + * direct write under the main m_mutex.
3501 + * It doesn't need a mutex hold to protect this read.
3198 3502 */
3503 +
3199 3504 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3200 - if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3505 + if (cmd_pkt_flags & FLAG_NOQUEUE) {
3201 3506 /*
3202 3507 * The command should be allowed to retry by returning
3203 3508 * TRAN_BUSY to stall the I/O's which come from
3204 3509 * scsi_vhci since the device/path is in unstable state
3205 3510 * now.
3206 3511 */
3207 3512 return (TRAN_BUSY);
3208 3513 } else {
3209 3514 /*
3210 3515 * The device is offline, just fail the command by
3211 3516 * return TRAN_FATAL_ERROR.
3212 3517 */
3213 3518 return (TRAN_FATAL_ERROR);
3214 3519 }
3215 3520 }
3216 - rval = mptsas_accept_pkt(mpt, cmd);
3521 + return (TRAN_ACCEPT);
3522 +}
3217 3523
3218 - return (rval);
3524 +/*
3525 + * Note that this function has a side effect of releasing the
3526 + * per target mutex.
3527 + */
3528 +static void
3529 +mptsas_offline_target_direct(mptsas_t *mpt, mptsas_target_t *ptgt)
3530 +{
3531 + char phy_mask_name[MPTSAS_MAX_PHYS];
3532 + mptsas_phymask_t phymask = ptgt->m_addr.mta_phymask;
3533 + dev_info_t *parent;
3534 +
3535 + ASSERT(mutex_owned(&mpt->m_mutex));
3536 +
3537 + ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
3538 + bzero(phy_mask_name, MPTSAS_MAX_PHYS);
3539 + (void) sprintf(phy_mask_name, "%x", phymask);
3540 + parent = scsi_hba_iport_find(mpt->m_dip, phy_mask_name);
3541 +
3542 + if (parent != NULL) {
3543 + mptsas_offline_target(mpt, ptgt,
3544 + ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED ?
3545 + MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE :
3546 + MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE,
3547 + parent);
3548 + } else {
3549 + mptsas_log(mpt, CE_WARN, "Failed to find an "
3550 + "iport for \"%s\", should not happen!",
3551 + phy_mask_name);
3552 + }
3219 3553 }
3220 3554
3555 +/*
3556 + * In order to be efficient with the m_mutex (which can be dropped before
3557 + * calling mptsas_start_cmd()) indicate if start_cmd should be called via the
3558 + * returned value (FALSE or TRUE). Caller is then responsible for doing the
3559 + * right thing with the m_mutex.
3560 + */
3221 3561 static int
3222 -mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3562 +mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd, int *tran_rval)
3223 3563 {
3224 3564 int rval = TRAN_ACCEPT;
3225 3565 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3226 3566
3227 3567 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3228 3568
3229 3569 ASSERT(mutex_owned(&mpt->m_mutex));
3230 3570
3231 3571 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3232 3572 rval = mptsas_prepare_pkt(cmd);
3233 3573 if (rval != TRAN_ACCEPT) {
3234 3574 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3235 - return (rval);
3575 + goto set_tranrval;
3236 3576 }
3237 3577 }
3238 3578
3239 3579 /*
3240 - * reset the throttle if we were draining
3580 + * If the command came from the tx wait q it may have slipped
3581 + * by the check for dr_flag before being added to the queue.
3582 + * Fail here with abort status.
3241 3583 */
3242 - if ((ptgt->m_t_ncmds == 0) &&
3243 - (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3244 - NDBG23(("reset throttle"));
3245 - ASSERT(ptgt->m_reset_delay == 0);
3246 - mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3584 + if (cmd->cmd_flags & CFLAG_TXQ) {
3585 + rval = mptsas_check_targ_intxtion(cmd->cmd_tgt_addr,
3586 + cmd->cmd_pkt_flags);
3587 + if (rval != TRAN_ACCEPT) {
3588 + mptsas_set_pkt_reason(mpt, cmd, CMD_ABORTED,
3589 + STAT_ABORTED);
3590 + mptsas_doneq_add(mpt, cmd);
3591 + mptsas_doneq_empty(mpt);
3592 + goto set_tranrval;
3593 + }
3247 3594 }
3248 -
3249 3595 /*
3250 3596 * If HBA is being reset, the DevHandles are being re-initialized,
3251 3597 * which means that they could be invalid even if the target is still
3252 3598 * attached. Check if being reset and if DevHandle is being
3253 3599 * re-initialized. If this is the case, return BUSY so the I/O can be
3254 3600 * retried later.
3255 3601 */
3256 3602 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) {
3257 3603 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
3258 3604 if (cmd->cmd_flags & CFLAG_TXQ) {
3259 3605 mptsas_doneq_add(mpt, cmd);
3260 3606 mptsas_doneq_empty(mpt);
3261 - return (rval);
3262 3607 } else {
3263 - return (TRAN_BUSY);
3608 + rval = TRAN_BUSY;
3264 3609 }
3610 + goto set_tranrval;
3611 + }
3612 +
3613 + mutex_enter(&ptgt->m_t_mutex);
3614 + /*
3615 + * reset the throttle if we were draining
3616 + */
3617 + if ((ptgt->m_t_ncmds == 0) &&
3618 + (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3619 + NDBG23(("reset throttle"));
3620 + ASSERT(ptgt->m_reset_delay == 0);
3621 + mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3265 3622 }
3266 3623
3267 3624 /*
3268 3625 * If device handle has already been invalidated, just
3269 - * fail the command. In theory, command from scsi_vhci
3270 - * client is impossible send down command with invalid
3626 + * fail the command. In theory, for a command from scsi_vhci
3627 + * client it's impossible to receive a command with an invalid
3271 3628 * devhdl since devhdl is set after path offline, target
3272 - * driver is not suppose to select a offlined path.
3629 + * driver is not supposed to select an offlined path.
3273 3630 */
3274 3631 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3275 - NDBG20(("rejecting command, it might because invalid devhdl "
3632 + NDBG3(("rejecting command, it might because invalid devhdl "
3276 3633 "request."));
3634 + mutex_exit(&ptgt->m_t_mutex);
3277 3635 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3278 3636 if (cmd->cmd_flags & CFLAG_TXQ) {
3279 3637 mptsas_doneq_add(mpt, cmd);
3280 3638 mptsas_doneq_empty(mpt);
3281 - return (rval);
3282 3639 } else {
3283 - return (TRAN_FATAL_ERROR);
3640 + rval = TRAN_FATAL_ERROR;
3284 3641 }
3642 + goto set_tranrval;
3285 3643 }
3286 3644 /*
3287 3645 * The first case is the normal case. mpt gets a command from the
3288 3646 * target driver and starts it.
3289 3647 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3290 3648 * commands is m_max_requests - 2.
3291 3649 */
3292 3650 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
3293 3651 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
3294 3652 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3295 - (ptgt->m_reset_delay == 0) &&
3653 + (ptgt->m_reset_delay == 0) && (mpt->m_polled_intr == 0) &&
3296 3654 (ptgt->m_t_nwait == 0) &&
3297 3655 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3298 - if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3299 - (void) mptsas_start_cmd(mpt, cmd);
3656 + ASSERT((cmd->cmd_flags & CFLAG_CMDIOC) == 0);
3657 + if (mptsas_save_cmd_to_slot(mpt, cmd) == TRUE) {
3658 + ptgt->m_t_ncmds++;
3659 + mutex_exit(&ptgt->m_t_mutex);
3660 + cmd->cmd_active_expiration = 0;
3661 + *tran_rval = rval;
3662 + return (TRUE);
3300 3663 } else {
3664 + mutex_exit(&ptgt->m_t_mutex);
3301 3665 mptsas_waitq_add(mpt, cmd);
3302 3666 }
3303 3667 } else {
3668 + mutex_exit(&ptgt->m_t_mutex);
3304 3669 /*
3305 3670 * Add this pkt to the work queue
3306 3671 */
3307 3672 mptsas_waitq_add(mpt, cmd);
3308 3673
3309 3674 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3310 3675 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3311 3676
3312 3677 /*
3313 3678 * Only flush the doneq if this is not a TM
3314 3679 * cmd. For TM cmds the flushing of the
3315 3680 * doneq will be done in those routines.
3316 3681 */
3317 3682 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3318 3683 mptsas_doneq_empty(mpt);
3319 3684 }
3320 3685 }
3321 3686 }
3322 - return (rval);
3687 +set_tranrval:
3688 + *tran_rval = rval;
3689 + return (FALSE);
3323 3690 }
3324 3691
3325 -int
3326 -mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3692 +static void
3693 +mptsas_retry_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3327 3694 {
3328 - mptsas_slots_t *slots = mpt->m_active;
3329 - uint_t slot, start_rotor;
3330 - mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3695 + int rval;
3331 3696
3332 - ASSERT(MUTEX_HELD(&mpt->m_mutex));
3697 + cmd->cmd_pkt_flags |= FLAG_HEAD;
3698 + cmd->cmd_flags |= CFLAG_RETRY;
3699 + cmd->cmd_flags &= ~CFLAG_TXQ;
3700 + if (mptsas_accept_pkt(mpt, cmd, &rval)) {
3701 + (void) mptsas_start_cmd(mpt, cmd);
3702 + }
3703 +
3704 + /*
3705 + * If there was a problem clear the retry flag so that the
3706 + * command will be completed with error rather than get lost!
3707 + */
3708 + if (rval != TRAN_ACCEPT)
3709 + cmd->cmd_flags &= ~CFLAG_RETRY;
3710 +}
3711 +
3712 +static int
3713 +mptsas_save_cmd_to_slot(mptsas_t *mpt, mptsas_cmd_t *cmd)
3714 +{
3715 + mptsas_slots_t *slots = mpt->m_active;
3716 + uint_t slot, start_rotor, rotor, n_normal;
3333 3717
3334 3718 /*
3335 3719 * Account for reserved TM request slot and reserved SMID of 0.
3336 3720 */
3337 3721 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2));
3338 3722
3339 3723 /*
3340 3724 * Find the next available slot, beginning at m_rotor. If no slot is
3341 3725 * available, we'll return FALSE to indicate that. This mechanism
3342 3726 * considers only the normal slots, not the reserved slot 0 nor the
3343 3727 * task management slot m_n_normal + 1. The rotor is left to point to
3344 3728 * the normal slot after the one we select, unless we select the last
3345 3729 * normal slot in which case it returns to slot 1.
3346 3730 */
3347 - start_rotor = slots->m_rotor;
3731 + start_rotor = rotor = slots->m_rotor;
3732 + n_normal = slots->m_n_normal;
3348 3733 do {
3349 - slot = slots->m_rotor++;
3350 - if (slots->m_rotor > slots->m_n_normal)
3351 - slots->m_rotor = 1;
3734 + slot = rotor++;
3735 + if (rotor > n_normal)
3736 + rotor = 1;
3352 3737
3353 - if (slots->m_rotor == start_rotor)
3738 + if (rotor == start_rotor)
3354 3739 break;
3355 3740 } while (slots->m_slot[slot] != NULL);
3741 + slots->m_rotor = rotor;
3356 3742
3357 3743 if (slots->m_slot[slot] != NULL)
3358 3744 return (FALSE);
3359 3745
3360 3746 ASSERT(slot != 0 && slot <= slots->m_n_normal);
3361 3747
3362 3748 cmd->cmd_slot = slot;
3363 3749 slots->m_slot[slot] = cmd;
3364 - mpt->m_ncmds++;
3750 + atomic_inc_32(&mpt->m_ncmds);
3365 3751
3366 3752 /*
3367 - * only increment per target ncmds if this is not a
3368 - * command that has no target associated with it (i.e. a
3369 - * event acknoledgment)
3753 + * Distribute the commands amongst the reply queues (Interrupt vectors).
3754 + * Stick to 0 for polled.
3370 3755 */
3371 - if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3372 - ptgt->m_t_ncmds++;
3756 + if (!(cmd->cmd_pkt_flags & FLAG_NOINTR) &&
3757 + !(cmd->cmd_flags & (CFLAG_PASSTHRU|CFLAG_CONFIG|CFLAG_FW_DIAG)) &&
3758 + (mpt->m_post_reply_qcount > 1)) {
3759 + cmd->cmd_rpqidx = slot % mpt->m_post_reply_qcount;
3760 + }
3761 + atomic_inc_32(&mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds);
3762 + return (TRUE);
3763 +}
3764 +
3765 +int
3766 +mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3767 +{
3768 + mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3769 +
3770 + ASSERT(MUTEX_HELD(&mpt->m_mutex));
3771 +
3772 + if (!mptsas_save_cmd_to_slot(mpt, cmd)) {
3773 + return (FALSE);
3373 3774 }
3374 - cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time;
3375 3775
3376 3776 /*
3377 - * If initial timout is less than or equal to one tick, bump
3378 - * the timeout by a tick so that command doesn't timeout before
3379 - * its allotted time.
3777 + * only increment per target ncmds if this is not a
3778 + * command that has no target associated with it (i.e. a
3779 + * event acknoledgement)
3380 3780 */
3381 - if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) {
3382 - cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick;
3781 + if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3782 + /*
3783 + * Expiration time is set in mptsas_start_cmd
3784 + */
3785 + mutex_enter(&ptgt->m_t_mutex);
3786 + ptgt->m_t_ncmds++;
3787 + mutex_exit(&ptgt->m_t_mutex);
3788 + cmd->cmd_active_expiration = 0;
3789 + } else {
3790 + /*
3791 + * Initialize expiration time for passthrough commands,
3792 + */
3793 + cmd->cmd_active_expiration = gethrtime() +
3794 + (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC;
3383 3795 }
3384 3796 return (TRUE);
3385 3797 }
3386 3798
3387 3799 /*
3388 3800 * prepare the pkt:
3389 3801 * the pkt may have been resubmitted or just reused so
3390 3802 * initialize some fields and do some checks.
3391 3803 */
3392 3804 static int
3393 3805 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3394 3806 {
3395 3807 struct scsi_pkt *pkt = CMD2PKT(cmd);
3396 3808
3397 3809 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3398 3810
3399 3811 /*
3400 3812 * Reinitialize some fields that need it; the packet may
3401 3813 * have been resubmitted
3402 3814 */
3403 3815 pkt->pkt_reason = CMD_CMPLT;
3404 3816 pkt->pkt_state = 0;
3405 3817 pkt->pkt_statistics = 0;
3406 3818 pkt->pkt_resid = 0;
3407 3819 cmd->cmd_age = 0;
3408 3820 cmd->cmd_pkt_flags = pkt->pkt_flags;
3409 3821
3410 3822 /*
3411 3823 * zero status byte.
3412 3824 */
3413 3825 *(pkt->pkt_scbp) = 0;
3414 3826
3415 3827 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3416 3828 pkt->pkt_resid = cmd->cmd_dmacount;
3417 3829
3418 3830 /*
3419 3831 * consistent packets need to be sync'ed first
3420 3832 * (only for data going out)
3421 3833 */
3422 3834 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3423 3835 (cmd->cmd_flags & CFLAG_DMASEND)) {
3424 3836 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3425 3837 DDI_DMA_SYNC_FORDEV);
3426 3838 }
3427 3839 }
3428 3840
3429 3841 cmd->cmd_flags =
3430 3842 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3431 3843 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3432 3844
3433 3845 return (TRAN_ACCEPT);
3434 3846 }
3435 3847
3436 3848 /*
3437 3849 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3438 3850 *
3439 3851 * One of three possibilities:
3440 3852 * - allocate scsi_pkt
3441 3853 * - allocate scsi_pkt and DMA resources
3442 3854 * - allocate DMA resources to an already-allocated pkt
3443 3855 */
3444 3856 static struct scsi_pkt *
3445 3857 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3446 3858 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3447 3859 int (*callback)(), caddr_t arg)
3448 3860 {
3449 3861 mptsas_cmd_t *cmd, *new_cmd;
3450 3862 mptsas_t *mpt = ADDR2MPT(ap);
3451 3863 int failure = 1;
3452 3864 uint_t oldcookiec;
3453 3865 mptsas_target_t *ptgt = NULL;
3454 3866 int rval;
3455 3867 mptsas_tgt_private_t *tgt_private;
3456 3868 int kf;
3457 3869
3458 3870 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3459 3871
3460 3872 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3461 3873 tran_tgt_private;
3462 3874 ASSERT(tgt_private != NULL);
3463 3875 if (tgt_private == NULL) {
3464 3876 return (NULL);
3465 3877 }
3466 3878 ptgt = tgt_private->t_private;
3467 3879 ASSERT(ptgt != NULL);
3468 3880 if (ptgt == NULL)
3469 3881 return (NULL);
3470 3882 ap->a_target = ptgt->m_devhdl;
3471 3883 ap->a_lun = tgt_private->t_lun;
3472 3884
3473 3885 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3474 3886 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3475 3887 statuslen *= 100; tgtlen *= 4;
3476 3888 #endif
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3477 3889 NDBG3(("mptsas_scsi_init_pkt:\n"
3478 3890 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3479 3891 ap->a_target, (void *)pkt, (void *)bp,
3480 3892 cmdlen, statuslen, tgtlen, flags));
3481 3893
3482 3894 /*
3483 3895 * Allocate the new packet.
3484 3896 */
3485 3897 if (pkt == NULL) {
3486 3898 ddi_dma_handle_t save_dma_handle;
3487 - ddi_dma_handle_t save_arq_dma_handle;
3488 - struct buf *save_arq_bp;
3489 - ddi_dma_cookie_t save_arqcookie;
3490 3899
3491 3900 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3492 3901
3493 3902 if (cmd) {
3494 3903 save_dma_handle = cmd->cmd_dmahandle;
3495 - save_arq_dma_handle = cmd->cmd_arqhandle;
3496 - save_arq_bp = cmd->cmd_arq_buf;
3497 - save_arqcookie = cmd->cmd_arqcookie;
3498 3904 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3499 3905 cmd->cmd_dmahandle = save_dma_handle;
3500 - cmd->cmd_arqhandle = save_arq_dma_handle;
3501 - cmd->cmd_arq_buf = save_arq_bp;
3502 - cmd->cmd_arqcookie = save_arqcookie;
3503 3906
3504 3907 pkt = (void *)((uchar_t *)cmd +
3505 3908 sizeof (struct mptsas_cmd));
3506 3909 pkt->pkt_ha_private = (opaque_t)cmd;
3507 3910 pkt->pkt_address = *ap;
3508 3911 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3509 3912 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3510 3913 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3511 3914 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3512 3915 cmd->cmd_cdblen = (uchar_t)cmdlen;
3513 3916 cmd->cmd_scblen = statuslen;
3514 3917 cmd->cmd_rqslen = SENSE_LENGTH;
3515 3918 cmd->cmd_tgt_addr = ptgt;
3516 3919 failure = 0;
3517 3920 }
3518 3921
3519 3922 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) ||
3520 3923 (tgtlen > PKT_PRIV_LEN) ||
3521 3924 (statuslen > EXTCMDS_STATUS_SIZE)) {
3522 3925 if (failure == 0) {
3523 3926 /*
3524 3927 * if extern alloc fails, all will be
3525 3928 * deallocated, including cmd
3526 3929 */
3527 3930 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3528 3931 cmdlen, tgtlen, statuslen, kf);
3529 3932 }
3530 3933 if (failure) {
3531 3934 /*
3532 3935 * if extern allocation fails, it will
3533 3936 * deallocate the new pkt as well
3534 3937 */
3535 3938 return (NULL);
3536 3939 }
3537 3940 }
3538 3941 new_cmd = cmd;
3539 3942
3540 3943 } else {
3541 3944 cmd = PKT2CMD(pkt);
3542 3945 new_cmd = NULL;
3543 3946 }
3544 3947
3545 3948
3546 3949 /* grab cmd->cmd_cookiec here as oldcookiec */
3547 3950
3548 3951 oldcookiec = cmd->cmd_cookiec;
3549 3952
3550 3953 /*
3551 3954 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3552 3955 * greater than 0 and we'll need to grab the next dma window
3553 3956 */
3554 3957 /*
3555 3958 * SLM-not doing extra command frame right now; may add later
3556 3959 */
3557 3960
3558 3961 if (cmd->cmd_nwin > 0) {
3559 3962
3560 3963 /*
3561 3964 * Make sure we havn't gone past the the total number
3562 3965 * of windows
3563 3966 */
3564 3967 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3565 3968 return (NULL);
3566 3969 }
3567 3970 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3568 3971 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3569 3972 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3570 3973 return (NULL);
3571 3974 }
3572 3975 goto get_dma_cookies;
3573 3976 }
3574 3977
3575 3978
3576 3979 if (flags & PKT_XARQ) {
3577 3980 cmd->cmd_flags |= CFLAG_XARQ;
3578 3981 }
3579 3982
3580 3983 /*
3581 3984 * DMA resource allocation. This version assumes your
3582 3985 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3583 3986 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3584 3987 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3585 3988 */
3586 3989 if (bp && (bp->b_bcount != 0) &&
3587 3990 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3588 3991
3589 3992 int cnt, dma_flags;
3590 3993 mptti_t *dmap; /* ptr to the S/G list */
3591 3994
3592 3995 /*
3593 3996 * Set up DMA memory and position to the next DMA segment.
3594 3997 */
3595 3998 ASSERT(cmd->cmd_dmahandle != NULL);
3596 3999
3597 4000 if (bp->b_flags & B_READ) {
3598 4001 dma_flags = DDI_DMA_READ;
3599 4002 cmd->cmd_flags &= ~CFLAG_DMASEND;
3600 4003 } else {
3601 4004 dma_flags = DDI_DMA_WRITE;
3602 4005 cmd->cmd_flags |= CFLAG_DMASEND;
3603 4006 }
3604 4007 if (flags & PKT_CONSISTENT) {
3605 4008 cmd->cmd_flags |= CFLAG_CMDIOPB;
3606 4009 dma_flags |= DDI_DMA_CONSISTENT;
3607 4010 }
3608 4011
3609 4012 if (flags & PKT_DMA_PARTIAL) {
3610 4013 dma_flags |= DDI_DMA_PARTIAL;
3611 4014 }
3612 4015
3613 4016 /*
3614 4017 * workaround for byte hole issue on psycho and
3615 4018 * schizo pre 2.1
3616 4019 */
3617 4020 if ((bp->b_flags & B_READ) && ((bp->b_flags &
3618 4021 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3619 4022 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3620 4023 dma_flags |= DDI_DMA_CONSISTENT;
3621 4024 }
3622 4025
3623 4026 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3624 4027 dma_flags, callback, arg,
3625 4028 &cmd->cmd_cookie, &cmd->cmd_cookiec);
3626 4029 if (rval == DDI_DMA_PARTIAL_MAP) {
3627 4030 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
3628 4031 &cmd->cmd_nwin);
3629 4032 cmd->cmd_winindex = 0;
3630 4033 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
3631 4034 cmd->cmd_winindex, &cmd->cmd_dma_offset,
3632 4035 &cmd->cmd_dma_len, &cmd->cmd_cookie,
3633 4036 &cmd->cmd_cookiec);
3634 4037 } else if (rval && (rval != DDI_DMA_MAPPED)) {
3635 4038 switch (rval) {
3636 4039 case DDI_DMA_NORESOURCES:
3637 4040 bioerror(bp, 0);
3638 4041 break;
3639 4042 case DDI_DMA_BADATTR:
3640 4043 case DDI_DMA_NOMAPPING:
3641 4044 bioerror(bp, EFAULT);
3642 4045 break;
3643 4046 case DDI_DMA_TOOBIG:
3644 4047 default:
3645 4048 bioerror(bp, EINVAL);
3646 4049 break;
3647 4050 }
3648 4051 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3649 4052 if (new_cmd) {
3650 4053 mptsas_scsi_destroy_pkt(ap, pkt);
3651 4054 }
3652 4055 return ((struct scsi_pkt *)NULL);
3653 4056 }
3654 4057
3655 4058 get_dma_cookies:
3656 4059 cmd->cmd_flags |= CFLAG_DMAVALID;
3657 4060 ASSERT(cmd->cmd_cookiec > 0);
3658 4061
3659 4062 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3660 4063 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3661 4064 cmd->cmd_cookiec);
3662 4065 bioerror(bp, EINVAL);
3663 4066 if (new_cmd) {
3664 4067 mptsas_scsi_destroy_pkt(ap, pkt);
3665 4068 }
3666 4069 return ((struct scsi_pkt *)NULL);
3667 4070 }
3668 4071
3669 4072 /*
3670 4073 * Allocate extra SGL buffer if needed.
3671 4074 */
3672 4075 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3673 4076 (cmd->cmd_extra_frames == NULL)) {
3674 4077 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3675 4078 DDI_FAILURE) {
3676 4079 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3677 4080 "failed");
3678 4081 bioerror(bp, ENOMEM);
3679 4082 if (new_cmd) {
3680 4083 mptsas_scsi_destroy_pkt(ap, pkt);
3681 4084 }
3682 4085 return ((struct scsi_pkt *)NULL);
3683 4086 }
3684 4087 }
3685 4088
3686 4089 /*
3687 4090 * Always use scatter-gather transfer
3688 4091 * Use the loop below to store physical addresses of
3689 4092 * DMA segments, from the DMA cookies, into your HBA's
3690 4093 * scatter-gather list.
3691 4094 * We need to ensure we have enough kmem alloc'd
3692 4095 * for the sg entries since we are no longer using an
3693 4096 * array inside mptsas_cmd_t.
3694 4097 *
3695 4098 * We check cmd->cmd_cookiec against oldcookiec so
3696 4099 * the scatter-gather list is correctly allocated
3697 4100 */
3698 4101
3699 4102 if (oldcookiec != cmd->cmd_cookiec) {
3700 4103 if (cmd->cmd_sg != (mptti_t *)NULL) {
3701 4104 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3702 4105 oldcookiec);
3703 4106 cmd->cmd_sg = NULL;
3704 4107 }
3705 4108 }
3706 4109
3707 4110 if (cmd->cmd_sg == (mptti_t *)NULL) {
3708 4111 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3709 4112 cmd->cmd_cookiec), kf);
3710 4113
3711 4114 if (cmd->cmd_sg == (mptti_t *)NULL) {
3712 4115 mptsas_log(mpt, CE_WARN,
3713 4116 "unable to kmem_alloc enough memory "
3714 4117 "for scatter/gather list");
3715 4118 /*
3716 4119 * if we have an ENOMEM condition we need to behave
3717 4120 * the same way as the rest of this routine
3718 4121 */
3719 4122
3720 4123 bioerror(bp, ENOMEM);
3721 4124 if (new_cmd) {
3722 4125 mptsas_scsi_destroy_pkt(ap, pkt);
3723 4126 }
3724 4127 return ((struct scsi_pkt *)NULL);
3725 4128 }
3726 4129 }
3727 4130
3728 4131 dmap = cmd->cmd_sg;
3729 4132
3730 4133 ASSERT(cmd->cmd_cookie.dmac_size != 0);
3731 4134
3732 4135 /*
3733 4136 * store the first segment into the S/G list
3734 4137 */
3735 4138 dmap->count = cmd->cmd_cookie.dmac_size;
3736 4139 dmap->addr.address64.Low = (uint32_t)
3737 4140 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3738 4141 dmap->addr.address64.High = (uint32_t)
3739 4142 (cmd->cmd_cookie.dmac_laddress >> 32);
3740 4143
3741 4144 /*
3742 4145 * dmacount counts the size of the dma for this window
3743 4146 * (if partial dma is being used). totaldmacount
3744 4147 * keeps track of the total amount of dma we have
3745 4148 * transferred for all the windows (needed to calculate
3746 4149 * the resid value below).
3747 4150 */
3748 4151 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3749 4152 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3750 4153
3751 4154 /*
3752 4155 * We already stored the first DMA scatter gather segment,
3753 4156 * start at 1 if we need to store more.
3754 4157 */
3755 4158 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
3756 4159 /*
3757 4160 * Get next DMA cookie
3758 4161 */
3759 4162 ddi_dma_nextcookie(cmd->cmd_dmahandle,
3760 4163 &cmd->cmd_cookie);
3761 4164 dmap++;
3762 4165
3763 4166 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
3764 4167 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3765 4168
3766 4169 /*
3767 4170 * store the segment parms into the S/G list
3768 4171 */
3769 4172 dmap->count = cmd->cmd_cookie.dmac_size;
3770 4173 dmap->addr.address64.Low = (uint32_t)
3771 4174 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
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3772 4175 dmap->addr.address64.High = (uint32_t)
3773 4176 (cmd->cmd_cookie.dmac_laddress >> 32);
3774 4177 }
3775 4178
3776 4179 /*
3777 4180 * If this was partially allocated we set the resid
3778 4181 * the amount of data NOT transferred in this window
3779 4182 * If there is only one window, the resid will be 0
3780 4183 */
3781 4184 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
3782 - NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount));
4185 + NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.",
4186 + cmd->cmd_dmacount));
3783 4187 }
3784 4188 return (pkt);
3785 4189 }
3786 4190
3787 4191 /*
3788 4192 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
3789 4193 *
3790 4194 * Notes:
3791 4195 * - also frees DMA resources if allocated
3792 4196 * - implicit DMA synchonization
3793 4197 */
3794 4198 static void
3795 4199 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
3796 4200 {
3797 4201 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3798 4202 mptsas_t *mpt = ADDR2MPT(ap);
3799 4203
3800 4204 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
3801 4205 ap->a_target, (void *)pkt));
3802 4206
3803 4207 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3804 4208 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
3805 4209 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3806 4210 }
3807 4211
3808 4212 if (cmd->cmd_sg) {
3809 4213 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
3810 4214 cmd->cmd_sg = NULL;
3811 4215 }
3812 4216
3813 4217 mptsas_free_extra_sgl_frame(mpt, cmd);
3814 4218
3815 4219 if ((cmd->cmd_flags &
3816 4220 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
3817 4221 CFLAG_SCBEXTERN)) == 0) {
3818 4222 cmd->cmd_flags = CFLAG_FREE;
3819 4223 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
3820 4224 } else {
3821 4225 mptsas_pkt_destroy_extern(mpt, cmd);
3822 4226 }
3823 4227 }
3824 4228
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3825 4229 /*
3826 4230 * kmem cache constructor and destructor:
3827 4231 * When constructing, we bzero the cmd and allocate the dma handle
3828 4232 * When destructing, just free the dma handle
3829 4233 */
3830 4234 static int
3831 4235 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
3832 4236 {
3833 4237 mptsas_cmd_t *cmd = buf;
3834 4238 mptsas_t *mpt = cdrarg;
3835 - struct scsi_address ap;
3836 - uint_t cookiec;
3837 - ddi_dma_attr_t arq_dma_attr;
3838 4239 int (*callback)(caddr_t);
3839 4240
3840 4241 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3841 4242
3842 4243 NDBG4(("mptsas_kmem_cache_constructor"));
3843 4244
3844 - ap.a_hba_tran = mpt->m_tran;
3845 - ap.a_target = 0;
3846 - ap.a_lun = 0;
3847 -
3848 4245 /*
3849 4246 * allocate a dma handle
3850 4247 */
3851 4248 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
3852 4249 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
3853 4250 cmd->cmd_dmahandle = NULL;
3854 4251 return (-1);
3855 4252 }
3856 -
3857 - cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL,
3858 - SENSE_LENGTH, B_READ, callback, NULL);
3859 - if (cmd->cmd_arq_buf == NULL) {
3860 - ddi_dma_free_handle(&cmd->cmd_dmahandle);
3861 - cmd->cmd_dmahandle = NULL;
3862 - return (-1);
3863 - }
3864 -
3865 - /*
3866 - * allocate a arq handle
3867 - */
3868 - arq_dma_attr = mpt->m_msg_dma_attr;
3869 - arq_dma_attr.dma_attr_sgllen = 1;
3870 - if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback,
3871 - NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) {
3872 - ddi_dma_free_handle(&cmd->cmd_dmahandle);
3873 - scsi_free_consistent_buf(cmd->cmd_arq_buf);
3874 - cmd->cmd_dmahandle = NULL;
3875 - cmd->cmd_arqhandle = NULL;
3876 - return (-1);
3877 - }
3878 -
3879 - if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle,
3880 - cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3881 - callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) {
3882 - ddi_dma_free_handle(&cmd->cmd_dmahandle);
3883 - ddi_dma_free_handle(&cmd->cmd_arqhandle);
3884 - scsi_free_consistent_buf(cmd->cmd_arq_buf);
3885 - cmd->cmd_dmahandle = NULL;
3886 - cmd->cmd_arqhandle = NULL;
3887 - cmd->cmd_arq_buf = NULL;
3888 - return (-1);
3889 - }
3890 -
3891 4253 return (0);
3892 4254 }
3893 4255
3894 4256 static void
3895 4257 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
3896 4258 {
3897 4259 #ifndef __lock_lint
3898 4260 _NOTE(ARGUNUSED(cdrarg))
3899 4261 #endif
3900 4262 mptsas_cmd_t *cmd = buf;
3901 4263
3902 4264 NDBG4(("mptsas_kmem_cache_destructor"));
3903 4265
3904 - if (cmd->cmd_arqhandle) {
3905 - (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle);
3906 - ddi_dma_free_handle(&cmd->cmd_arqhandle);
3907 - cmd->cmd_arqhandle = NULL;
3908 - }
3909 - if (cmd->cmd_arq_buf) {
3910 - scsi_free_consistent_buf(cmd->cmd_arq_buf);
3911 - cmd->cmd_arq_buf = NULL;
3912 - }
3913 4266 if (cmd->cmd_dmahandle) {
3914 4267 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3915 4268 cmd->cmd_dmahandle = NULL;
3916 4269 }
3917 4270 }
3918 4271
3919 4272 static int
3920 4273 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
3921 4274 {
3922 4275 mptsas_cache_frames_t *p = buf;
3923 4276 mptsas_t *mpt = cdrarg;
3924 4277 ddi_dma_attr_t frame_dma_attr;
3925 4278 size_t mem_size, alloc_len;
3926 4279 ddi_dma_cookie_t cookie;
3927 4280 uint_t ncookie;
3928 4281 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
3929 4282 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3930 4283
3931 4284 frame_dma_attr = mpt->m_msg_dma_attr;
3932 4285 frame_dma_attr.dma_attr_align = 0x10;
3933 4286 frame_dma_attr.dma_attr_sgllen = 1;
3934 4287
3935 4288 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
3936 4289 &p->m_dma_hdl) != DDI_SUCCESS) {
3937 4290 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
3938 4291 " extra SGL.");
3939 4292 return (DDI_FAILURE);
3940 4293 }
3941 4294
3942 4295 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
3943 4296
3944 4297 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
3945 4298 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
3946 4299 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
3947 4300 ddi_dma_free_handle(&p->m_dma_hdl);
3948 4301 p->m_dma_hdl = NULL;
3949 4302 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
3950 4303 " extra SGL.");
3951 4304 return (DDI_FAILURE);
3952 4305 }
3953 4306
3954 4307 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
3955 4308 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
3956 4309 &cookie, &ncookie) != DDI_DMA_MAPPED) {
3957 4310 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3958 4311 ddi_dma_free_handle(&p->m_dma_hdl);
3959 4312 p->m_dma_hdl = NULL;
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3960 4313 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
3961 4314 " extra SGL");
3962 4315 return (DDI_FAILURE);
3963 4316 }
3964 4317
3965 4318 /*
3966 4319 * Store the SGL memory address. This chip uses this
3967 4320 * address to dma to and from the driver. The second
3968 4321 * address is the address mpt uses to fill in the SGL.
3969 4322 */
3970 - p->m_phys_addr = cookie.dmac_address;
4323 + p->m_phys_addr = cookie.dmac_laddress;
3971 4324
3972 4325 return (DDI_SUCCESS);
3973 4326 }
3974 4327
3975 4328 static void
3976 4329 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
3977 4330 {
3978 4331 #ifndef __lock_lint
3979 4332 _NOTE(ARGUNUSED(cdrarg))
3980 4333 #endif
3981 4334 mptsas_cache_frames_t *p = buf;
3982 4335 if (p->m_dma_hdl != NULL) {
3983 4336 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
3984 4337 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3985 4338 ddi_dma_free_handle(&p->m_dma_hdl);
3986 4339 p->m_phys_addr = NULL;
3987 4340 p->m_frames_addr = NULL;
3988 4341 p->m_dma_hdl = NULL;
3989 4342 p->m_acc_hdl = NULL;
3990 4343 }
3991 4344
3992 4345 }
3993 4346
3994 4347 /*
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3995 4348 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
3996 4349 * for non-standard length cdb, pkt_private, status areas
3997 4350 * if allocation fails, then deallocate all external space and the pkt
3998 4351 */
3999 4352 /* ARGSUSED */
4000 4353 static int
4001 4354 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
4002 4355 int cmdlen, int tgtlen, int statuslen, int kf)
4003 4356 {
4004 4357 caddr_t cdbp, scbp, tgt;
4005 - int (*callback)(caddr_t) = (kf == KM_SLEEP) ?
4006 - DDI_DMA_SLEEP : DDI_DMA_DONTWAIT;
4007 - struct scsi_address ap;
4008 4358 size_t senselength;
4009 - ddi_dma_attr_t ext_arq_dma_attr;
4010 - uint_t cookiec;
4011 4359
4012 4360 NDBG3(("mptsas_pkt_alloc_extern: "
4013 4361 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
4014 4362 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
4015 4363
4016 4364 tgt = cdbp = scbp = NULL;
4017 4365 cmd->cmd_scblen = statuslen;
4018 4366 cmd->cmd_privlen = (uchar_t)tgtlen;
4019 4367
4020 4368 if (cmdlen > sizeof (cmd->cmd_cdb)) {
4021 4369 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
4022 4370 goto fail;
4023 4371 }
4024 4372 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
4025 4373 cmd->cmd_flags |= CFLAG_CDBEXTERN;
4026 4374 }
4027 4375 if (tgtlen > PKT_PRIV_LEN) {
4028 4376 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
4029 4377 goto fail;
4030 4378 }
4031 4379 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
4032 4380 cmd->cmd_pkt->pkt_private = tgt;
4033 4381 }
4034 4382 if (statuslen > EXTCMDS_STATUS_SIZE) {
|
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4035 4383 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
4036 4384 goto fail;
4037 4385 }
4038 4386 cmd->cmd_flags |= CFLAG_SCBEXTERN;
4039 4387 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
4040 4388
4041 4389 /* allocate sense data buf for DMA */
4042 4390
4043 4391 senselength = statuslen - MPTSAS_GET_ITEM_OFF(
4044 4392 struct scsi_arq_status, sts_sensedata);
4045 - cmd->cmd_rqslen = (uchar_t)senselength;
4046 -
4047 - ap.a_hba_tran = mpt->m_tran;
4048 - ap.a_target = 0;
4049 - ap.a_lun = 0;
4050 -
4051 - cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap,
4052 - (struct buf *)NULL, senselength, B_READ,
4053 - callback, NULL);
4054 -
4055 - if (cmd->cmd_ext_arq_buf == NULL) {
4056 - goto fail;
4057 - }
4058 - /*
4059 - * allocate a extern arq handle and bind the buf
4060 - */
4061 - ext_arq_dma_attr = mpt->m_msg_dma_attr;
4062 - ext_arq_dma_attr.dma_attr_sgllen = 1;
4063 - if ((ddi_dma_alloc_handle(mpt->m_dip,
4064 - &ext_arq_dma_attr, callback,
4065 - NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) {
4066 - goto fail;
4067 - }
4068 -
4069 - if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle,
4070 - cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
4071 - callback, NULL, &cmd->cmd_ext_arqcookie,
4072 - &cookiec)
4073 - != DDI_SUCCESS) {
4074 - goto fail;
4393 + if (senselength > mpt->m_req_sense_size) {
4394 + unsigned long i;
4395 + cmd->cmd_extrqslen = (uint16_t)senselength;
4396 + cmd->cmd_extrqschunks = (senselength +
4397 + (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size;
4398 + i = rmalloc_wait(mpt->m_erqsense_map,
4399 + cmd->cmd_extrqschunks);
4400 + ASSERT(i != 0);
4401 + cmd->cmd_extrqsidx = i - 1;
4402 + cmd->cmd_arq_buf = mpt->m_extreq_sense +
4403 + (cmd->cmd_extrqsidx * mpt->m_req_sense_size);
4404 + } else {
4405 + cmd->cmd_rqslen = (uchar_t)senselength;
4075 4406 }
4076 - cmd->cmd_flags |= CFLAG_EXTARQBUFVALID;
4077 4407 }
4078 4408 return (0);
4079 4409 fail:
4080 4410 mptsas_pkt_destroy_extern(mpt, cmd);
4081 4411 return (1);
4082 4412 }
4083 4413
4084 4414 /*
4085 4415 * deallocate external pkt space and deallocate the pkt
4086 4416 */
4087 4417 static void
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4088 4418 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
4089 4419 {
4090 4420 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
4091 4421
4092 4422 if (cmd->cmd_flags & CFLAG_FREE) {
4093 4423 mptsas_log(mpt, CE_PANIC,
4094 4424 "mptsas_pkt_destroy_extern: freeing free packet");
4095 4425 _NOTE(NOT_REACHED)
4096 4426 /* NOTREACHED */
4097 4427 }
4428 + if (cmd->cmd_extrqslen != 0) {
4429 + rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
4430 + cmd->cmd_extrqsidx + 1);
4431 + }
4098 4432 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
4099 4433 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
4100 4434 }
4101 4435 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4102 4436 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4103 - if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4104 - (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4105 - }
4106 - if (cmd->cmd_ext_arqhandle) {
4107 - ddi_dma_free_handle(&cmd->cmd_ext_arqhandle);
4108 - cmd->cmd_ext_arqhandle = NULL;
4109 - }
4110 - if (cmd->cmd_ext_arq_buf)
4111 - scsi_free_consistent_buf(cmd->cmd_ext_arq_buf);
4112 4437 }
4113 4438 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4114 4439 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4115 4440 }
4116 4441 cmd->cmd_flags = CFLAG_FREE;
4117 4442 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4118 4443 }
4119 4444
4120 4445 /*
4121 4446 * tran_sync_pkt(9E) - explicit DMA synchronization
4122 4447 */
4123 4448 /*ARGSUSED*/
4124 4449 static void
4125 4450 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4126 4451 {
4127 4452 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4128 4453
4129 4454 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4130 4455 ap->a_target, (void *)pkt));
4131 4456
4132 4457 if (cmd->cmd_dmahandle) {
4133 4458 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4134 4459 (cmd->cmd_flags & CFLAG_DMASEND) ?
4135 4460 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4136 4461 }
4137 4462 }
4138 4463
4139 4464 /*
4140 4465 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4141 4466 */
4142 4467 /*ARGSUSED*/
4143 4468 static void
4144 4469 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4145 4470 {
4146 4471 mptsas_cmd_t *cmd = PKT2CMD(pkt);
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4147 4472 mptsas_t *mpt = ADDR2MPT(ap);
4148 4473
4149 4474 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4150 4475 ap->a_target, (void *)pkt));
4151 4476
4152 4477 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4153 4478 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4154 4479 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4155 4480 }
4156 4481
4157 - if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4158 - (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4159 - cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID;
4160 - }
4161 -
4162 4482 mptsas_free_extra_sgl_frame(mpt, cmd);
4163 4483 }
4164 4484
4165 4485 static void
4166 4486 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4167 4487 {
4168 4488 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4169 4489 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4170 4490 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4171 4491 DDI_DMA_SYNC_FORCPU);
4172 4492 }
4173 4493 (*pkt->pkt_comp)(pkt);
4174 4494 }
4175 4495
4176 4496 static void
4177 -mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
4178 - pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4497 +mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4498 + ddi_acc_handle_t acc_hdl, uint_t cookiec,
4499 + uint32_t end_flags)
4179 4500 {
4180 - uint_t cookiec;
4501 + pMpi2SGESimple64_t sge;
4181 4502 mptti_t *dmap;
4182 4503 uint32_t flags;
4504 +
4505 + dmap = cmd->cmd_sg;
4506 +
4507 + sge = (pMpi2SGESimple64_t)(&frame->SGL);
4508 + while (cookiec--) {
4509 + ddi_put32(acc_hdl, &sge->Address.Low,
4510 + dmap->addr.address64.Low);
4511 + ddi_put32(acc_hdl, &sge->Address.High,
4512 + dmap->addr.address64.High);
4513 + ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count);
4514 + flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4515 + flags |= ((uint32_t)
4516 + (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4517 + MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4518 + MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4519 + MPI2_SGE_FLAGS_SHIFT);
4520 +
4521 + /*
4522 + * If this is the last cookie, we set the flags
4523 + * to indicate so
4524 + */
4525 + if (cookiec == 0) {
4526 + flags |= end_flags;
4527 + }
4528 + if (cmd->cmd_flags & CFLAG_DMASEND) {
4529 + flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4530 + MPI2_SGE_FLAGS_SHIFT);
4531 + } else {
4532 + flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4533 + MPI2_SGE_FLAGS_SHIFT);
4534 + }
4535 + ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4536 + dmap++;
4537 + sge++;
4538 + }
4539 +}
4540 +
4541 +static void
4542 +mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4543 + pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4544 +{
4183 4545 pMpi2SGESimple64_t sge;
4184 4546 pMpi2SGEChain64_t sgechain;
4185 - ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
4547 + uint64_t nframe_phys_addr;
4548 + uint_t cookiec;
4549 + mptti_t *dmap;
4550 + uint32_t flags;
4551 + int i, j, k, l, frames, sgemax;
4552 + int temp, maxframe_sges;
4553 + uint8_t chainflags;
4554 + uint16_t chainlength;
4555 + mptsas_cache_frames_t *p;
4556 +
4557 + cookiec = cmd->cmd_cookiec;
4186 4558
4187 4559 /*
4188 - * Save the number of entries in the DMA
4189 - * Scatter/Gather list
4560 + * Hereby we start to deal with multiple frames.
4561 + * The process is as follows:
4562 + * 1. Determine how many frames are needed for SGL element
4563 + * storage; Note that all frames are stored in contiguous
4564 + * memory space and in 64-bit DMA mode each element is
4565 + * 3 double-words (12 bytes) long.
4566 + * 2. Fill up the main frame. We need to do this separately
4567 + * since it contains the SCSI IO request header and needs
4568 + * dedicated processing. Note that the last 4 double-words
4569 + * of the SCSI IO header is for SGL element storage
4570 + * (MPI2_SGE_IO_UNION).
4571 + * 3. Fill the chain element in the main frame, so the DMA
4572 + * engine can use the following frames.
4573 + * 4. Enter a loop to fill the remaining frames. Note that the
4574 + * last frame contains no chain element. The remaining
4575 + * frames go into the mpt SGL buffer allocated on the fly,
4576 + * not immediately following the main message frame, as in
4577 + * Gen1.
4578 + * Some restrictions:
4579 + * 1. For 64-bit DMA, the simple element and chain element
4580 + * are both of 3 double-words (12 bytes) in size, even
4581 + * though all frames are stored in the first 4G of mem
4582 + * range and the higher 32-bits of the address are always 0.
4583 + * 2. On some controllers (like the 1064/1068), a frame can
4584 + * hold SGL elements with the last 1 or 2 double-words
4585 + * (4 or 8 bytes) un-used. On these controllers, we should
4586 + * recognize that there's not enough room for another SGL
4587 + * element and move the sge pointer to the next frame.
4190 4588 */
4191 - cookiec = cmd->cmd_cookiec;
4192 4589
4193 - NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec));
4590 + /*
4591 + * Sgemax is the number of SGE's that will fit
4592 + * each extra frame and frames is total
4593 + * number of frames we'll need. 1 sge entry per
4594 + * frame is reseverd for the chain element thus the -1 below.
4595 + */
4596 + sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) - 1);
4597 + maxframe_sges = MPTSAS_MAX_FRAME_SGES64(mpt);
4598 + temp = (cookiec - (maxframe_sges - 1)) / sgemax;
4194 4599
4195 4600 /*
4196 - * Set read/write bit in control.
4601 + * A little check to see if we need to round up the number
4602 + * of frames we need
4197 4603 */
4198 - if (cmd->cmd_flags & CFLAG_DMASEND) {
4199 - *control |= MPI2_SCSIIO_CONTROL_WRITE;
4604 + if ((cookiec - (maxframe_sges - 1)) - (temp * sgemax) > 1) {
4605 + frames = (temp + 1);
4200 4606 } else {
4201 - *control |= MPI2_SCSIIO_CONTROL_READ;
4607 + frames = temp;
4202 4608 }
4609 + dmap = cmd->cmd_sg;
4610 + sge = (pMpi2SGESimple64_t)(&frame->SGL);
4203 4611
4204 - ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
4612 + /*
4613 + * First fill in the main frame
4614 + */
4615 + j = maxframe_sges - 1;
4616 + mptsas_sge_mainframe(cmd, frame, acc_hdl, j,
4617 + ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4618 + MPI2_SGE_FLAGS_SHIFT));
4619 + dmap += j;
4620 + sge += j;
4621 + j++;
4622 +
4623 + /*
4624 + * Fill in the chain element in the main frame.
4625 + * About calculation on ChainOffset:
4626 + * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4627 + * in the end reserved for SGL element storage
4628 + * (MPI2_SGE_IO_UNION); we should count it in our
4629 + * calculation. See its definition in the header file.
4630 + * 2. Constant j is the counter of the current SGL element
4631 + * that will be processed, and (j - 1) is the number of
4632 + * SGL elements that have been processed (stored in the
4633 + * main frame).
4634 + * 3. ChainOffset value should be in units of double-words (4
4635 + * bytes) so the last value should be divided by 4.
4636 + */
4637 + ddi_put8(acc_hdl, &frame->ChainOffset,
4638 + (sizeof (MPI2_SCSI_IO_REQUEST) -
4639 + sizeof (MPI2_SGE_IO_UNION) +
4640 + (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4641 + sgechain = (pMpi2SGEChain64_t)sge;
4642 + chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4643 + MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4644 + MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4645 + ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4646 +
4647 + /*
4648 + * The size of the next frame is the accurate size of space
4649 + * (in bytes) used to store the SGL elements. j is the counter
4650 + * of SGL elements. (j - 1) is the number of SGL elements that
4651 + * have been processed (stored in frames).
4652 + */
4653 + if (frames >= 2) {
4654 + chainlength = mpt->m_req_frame_size /
4655 + sizeof (MPI2_SGE_SIMPLE64) *
4656 + sizeof (MPI2_SGE_SIMPLE64);
4657 + } else {
4658 + chainlength = ((cookiec - (j - 1)) *
4659 + sizeof (MPI2_SGE_SIMPLE64));
4660 + }
4661 +
4662 + p = cmd->cmd_extra_frames;
4663 +
4664 + ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4665 + ddi_put32(acc_hdl, &sgechain->Address.Low,
4666 + (p->m_phys_addr&0xffffffffull));
4667 + ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr>>32);
4205 4668
4206 4669 /*
4207 - * We have 2 cases here. First where we can fit all the
4208 - * SG elements into the main frame, and the case
4209 - * where we can't.
4210 - * If we have more cookies than we can attach to a frame
4211 - * we will need to use a chain element to point
4212 - * a location of memory where the rest of the S/G
4213 - * elements reside.
4670 + * If there are more than 2 frames left we have to
4671 + * fill in the next chain offset to the location of
4672 + * the chain element in the next frame.
4673 + * sgemax is the number of simple elements in an extra
4674 + * frame. Note that the value NextChainOffset should be
4675 + * in double-words (4 bytes).
4214 4676 */
4215 - if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
4216 - dmap = cmd->cmd_sg;
4217 - sge = (pMpi2SGESimple64_t)(&frame->SGL);
4218 - while (cookiec--) {
4219 - ddi_put32(acc_hdl,
4220 - &sge->Address.Low, dmap->addr.address64.Low);
4221 - ddi_put32(acc_hdl,
4222 - &sge->Address.High, dmap->addr.address64.High);
4223 - ddi_put32(acc_hdl, &sge->FlagsLength,
4224 - dmap->count);
4225 - flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4226 - flags |= ((uint32_t)
4227 - (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4228 - MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4229 - MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4230 - MPI2_SGE_FLAGS_SHIFT);
4677 + if (frames >= 2) {
4678 + ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4679 + (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4680 + } else {
4681 + ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4682 + }
4683 +
4684 + /*
4685 + * Jump to next frame;
4686 + * Starting here, chain buffers go into the per command SGL.
4687 + * This buffer is allocated when chain buffers are needed.
4688 + */
4689 + sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4690 + i = cookiec;
4691 +
4692 + /*
4693 + * Start filling in frames with SGE's. If we
4694 + * reach the end of frame and still have SGE's
4695 + * to fill we need to add a chain element and
4696 + * use another frame. j will be our counter
4697 + * for what cookie we are at and i will be
4698 + * the total cookiec. k is the current frame
4699 + */
4700 + for (k = 1; k <= frames; k++) {
4701 + for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4231 4702
4232 4703 /*
4233 - * If this is the last cookie, we set the flags
4234 - * to indicate so
4704 + * If we have reached the end of frame
4705 + * and we have more SGE's to fill in
4706 + * we have to fill the final entry
4707 + * with a chain element and then
4708 + * continue to the next frame
4235 4709 */
4236 - if (cookiec == 0) {
4237 - flags |=
4238 - ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
4239 - | MPI2_SGE_FLAGS_END_OF_BUFFER
4240 - | MPI2_SGE_FLAGS_END_OF_LIST) <<
4241 - MPI2_SGE_FLAGS_SHIFT);
4242 - }
4243 - if (cmd->cmd_flags & CFLAG_DMASEND) {
4244 - flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4245 - MPI2_SGE_FLAGS_SHIFT);
4246 - } else {
4247 - flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4248 - MPI2_SGE_FLAGS_SHIFT);
4710 + if ((l == (sgemax + 1)) && (k != frames)) {
4711 + sgechain = (pMpi2SGEChain64_t)sge;
4712 + j--;
4713 + chainflags = (
4714 + MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4715 + MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4716 + MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4717 + ddi_put8(p->m_acc_hdl,
4718 + &sgechain->Flags, chainflags);
4719 + /*
4720 + * k is the frame counter and (k + 1)
4721 + * is the number of the next frame.
4722 + * Note that frames are in contiguous
4723 + * memory space.
4724 + */
4725 + nframe_phys_addr = p->m_phys_addr +
4726 + (mpt->m_req_frame_size * k);
4727 + ddi_put32(p->m_acc_hdl,
4728 + &sgechain->Address.Low,
4729 + nframe_phys_addr&0xffffffffull);
4730 + ddi_put32(p->m_acc_hdl,
4731 + &sgechain->Address.High,
4732 + nframe_phys_addr>>32);
4733 +
4734 + /*
4735 + * If there are more than 2 frames left
4736 + * we have to next chain offset to
4737 + * the location of the chain element
4738 + * in the next frame and fill in the
4739 + * length of the next chain
4740 + */
4741 + if ((frames - k) >= 2) {
4742 + ddi_put8(p->m_acc_hdl,
4743 + &sgechain->NextChainOffset,
4744 + (sgemax *
4745 + sizeof (MPI2_SGE_SIMPLE64))
4746 + >> 2);
4747 + ddi_put16(p->m_acc_hdl,
4748 + &sgechain->Length,
4749 + mpt->m_req_frame_size /
4750 + sizeof (MPI2_SGE_SIMPLE64) *
4751 + sizeof (MPI2_SGE_SIMPLE64));
4752 + } else {
4753 + /*
4754 + * This is the last frame. Set
4755 + * the NextChainOffset to 0 and
4756 + * Length is the total size of
4757 + * all remaining simple elements
4758 + */
4759 + ddi_put8(p->m_acc_hdl,
4760 + &sgechain->NextChainOffset,
4761 + 0);
4762 + ddi_put16(p->m_acc_hdl,
4763 + &sgechain->Length,
4764 + (cookiec - j) *
4765 + sizeof (MPI2_SGE_SIMPLE64));
4766 + }
4767 +
4768 + /* Jump to the next frame */
4769 + sge = (pMpi2SGESimple64_t)
4770 + ((char *)p->m_frames_addr +
4771 + (int)mpt->m_req_frame_size * k);
4772 +
4773 + continue;
4249 4774 }
4250 - ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4251 - dmap++;
4252 - sge++;
4253 - }
4254 - } else {
4255 - /*
4256 - * Hereby we start to deal with multiple frames.
4257 - * The process is as follows:
4258 - * 1. Determine how many frames are needed for SGL element
4259 - * storage; Note that all frames are stored in contiguous
4260 - * memory space and in 64-bit DMA mode each element is
4261 - * 3 double-words (12 bytes) long.
4262 - * 2. Fill up the main frame. We need to do this separately
4263 - * since it contains the SCSI IO request header and needs
4264 - * dedicated processing. Note that the last 4 double-words
4265 - * of the SCSI IO header is for SGL element storage
4266 - * (MPI2_SGE_IO_UNION).
4267 - * 3. Fill the chain element in the main frame, so the DMA
4268 - * engine can use the following frames.
4269 - * 4. Enter a loop to fill the remaining frames. Note that the
4270 - * last frame contains no chain element. The remaining
4271 - * frames go into the mpt SGL buffer allocated on the fly,
4272 - * not immediately following the main message frame, as in
4273 - * Gen1.
4274 - * Some restrictions:
4275 - * 1. For 64-bit DMA, the simple element and chain element
4276 - * are both of 3 double-words (12 bytes) in size, even
4277 - * though all frames are stored in the first 4G of mem
4278 - * range and the higher 32-bits of the address are always 0.
4279 - * 2. On some controllers (like the 1064/1068), a frame can
4280 - * hold SGL elements with the last 1 or 2 double-words
4281 - * (4 or 8 bytes) un-used. On these controllers, we should
4282 - * recognize that there's not enough room for another SGL
4283 - * element and move the sge pointer to the next frame.
4284 - */
4285 - int i, j, k, l, frames, sgemax;
4286 - int temp;
4287 - uint8_t chainflags;
4288 - uint16_t chainlength;
4289 - mptsas_cache_frames_t *p;
4290 -
4291 - /*
4292 - * Sgemax is the number of SGE's that will fit
4293 - * each extra frame and frames is total
4294 - * number of frames we'll need. 1 sge entry per
4295 - * frame is reseverd for the chain element thus the -1 below.
4296 - */
4297 - sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4298 - - 1);
4299 - temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4300 -
4301 - /*
4302 - * A little check to see if we need to round up the number
4303 - * of frames we need
4304 - */
4305 - if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4306 - sgemax) > 1) {
4307 - frames = (temp + 1);
4308 - } else {
4309 - frames = temp;
4310 - }
4311 - dmap = cmd->cmd_sg;
4312 - sge = (pMpi2SGESimple64_t)(&frame->SGL);
4313 4775
4314 - /*
4315 - * First fill in the main frame
4316 - */
4317 - for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) {
4318 - ddi_put32(acc_hdl, &sge->Address.Low,
4776 + ddi_put32(p->m_acc_hdl,
4777 + &sge->Address.Low,
4319 4778 dmap->addr.address64.Low);
4320 - ddi_put32(acc_hdl, &sge->Address.High,
4779 + ddi_put32(p->m_acc_hdl,
4780 + &sge->Address.High,
4321 4781 dmap->addr.address64.High);
4322 - ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count);
4323 - flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4324 - flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4782 + ddi_put32(p->m_acc_hdl,
4783 + &sge->FlagsLength, dmap->count);
4784 + flags = ddi_get32(p->m_acc_hdl,
4785 + &sge->FlagsLength);
4786 + flags |= ((uint32_t)(
4787 + MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4325 4788 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4326 4789 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4327 4790 MPI2_SGE_FLAGS_SHIFT);
4328 4791
4329 4792 /*
4330 - * If this is the last SGE of this frame
4331 - * we set the end of list flag
4793 + * If we are at the end of the frame and
4794 + * there is another frame to fill in
4795 + * we set the last simple element as last
4796 + * element
4332 4797 */
4333 - if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) {
4798 + if ((l == sgemax) && (k != frames)) {
4334 4799 flags |= ((uint32_t)
4335 4800 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4336 4801 MPI2_SGE_FLAGS_SHIFT);
4337 4802 }
4803 +
4804 + /*
4805 + * If this is the final cookie we
4806 + * indicate it by setting the flags
4807 + */
4808 + if (j == i) {
4809 + flags |= ((uint32_t)
4810 + (MPI2_SGE_FLAGS_LAST_ELEMENT |
4811 + MPI2_SGE_FLAGS_END_OF_BUFFER |
4812 + MPI2_SGE_FLAGS_END_OF_LIST) <<
4813 + MPI2_SGE_FLAGS_SHIFT);
4814 + }
4338 4815 if (cmd->cmd_flags & CFLAG_DMASEND) {
4339 4816 flags |=
4340 4817 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4341 4818 MPI2_SGE_FLAGS_SHIFT);
4342 4819 } else {
4343 4820 flags |=
4344 4821 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4345 4822 MPI2_SGE_FLAGS_SHIFT);
4346 4823 }
4347 - ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4824 + ddi_put32(p->m_acc_hdl,
4825 + &sge->FlagsLength, flags);
4348 4826 dmap++;
4349 4827 sge++;
4350 4828 }
4829 + }
4351 4830
4352 - /*
4353 - * Fill in the chain element in the main frame.
4354 - * About calculation on ChainOffset:
4355 - * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4356 - * in the end reserved for SGL element storage
4357 - * (MPI2_SGE_IO_UNION); we should count it in our
4358 - * calculation. See its definition in the header file.
4359 - * 2. Constant j is the counter of the current SGL element
4360 - * that will be processed, and (j - 1) is the number of
4361 - * SGL elements that have been processed (stored in the
4362 - * main frame).
4363 - * 3. ChainOffset value should be in units of double-words (4
4364 - * bytes) so the last value should be divided by 4.
4365 - */
4366 - ddi_put8(acc_hdl, &frame->ChainOffset,
4367 - (sizeof (MPI2_SCSI_IO_REQUEST) -
4368 - sizeof (MPI2_SGE_IO_UNION) +
4369 - (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4370 - sgechain = (pMpi2SGEChain64_t)sge;
4371 - chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4372 - MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4373 - MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4374 - ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4831 + /*
4832 + * Sync DMA with the chain buffers that were just created
4833 + */
4834 + (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4835 +}
4375 4836
4376 - /*
4377 - * The size of the next frame is the accurate size of space
4378 - * (in bytes) used to store the SGL elements. j is the counter
4379 - * of SGL elements. (j - 1) is the number of SGL elements that
4380 - * have been processed (stored in frames).
4381 - */
4382 - if (frames >= 2) {
4383 - chainlength = mpt->m_req_frame_size /
4384 - sizeof (MPI2_SGE_SIMPLE64) *
4385 - sizeof (MPI2_SGE_SIMPLE64);
4386 - } else {
4387 - chainlength = ((cookiec - (j - 1)) *
4388 - sizeof (MPI2_SGE_SIMPLE64));
4389 - }
4837 +static void
4838 +mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4839 + ddi_acc_handle_t acc_hdl, uint_t cookiec,
4840 + uint8_t end_flag)
4841 +{
4842 + pMpi2IeeeSgeSimple64_t ieeesge;
4843 + mptti_t *dmap;
4844 + uint8_t flags;
4845 +
4846 + dmap = cmd->cmd_sg;
4390 4847
4391 - p = cmd->cmd_extra_frames;
4848 + NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec,
4849 + cmd->cmd_flags & CFLAG_DMASEND?"Out":"In"));
4392 4850
4393 - ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4394 - ddi_put32(acc_hdl, &sgechain->Address.Low,
4395 - p->m_phys_addr);
4396 - /* SGL is allocated in the first 4G mem range */
4397 - ddi_put32(acc_hdl, &sgechain->Address.High, 0);
4851 + ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4852 + while (cookiec--) {
4853 + ddi_put32(acc_hdl, &ieeesge->Address.Low,
4854 + dmap->addr.address64.Low);
4855 + ddi_put32(acc_hdl, &ieeesge->Address.High,
4856 + dmap->addr.address64.High);
4857 + ddi_put32(acc_hdl, &ieeesge->Length, dmap->count);
4858 + NDBG1(("mptsas_ieee_sge_mainframe: len=%d, high=0x%x",
4859 + dmap->count, dmap->addr.address64.High));
4860 + flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
4861 + MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4398 4862
4399 4863 /*
4400 - * If there are more than 2 frames left we have to
4401 - * fill in the next chain offset to the location of
4402 - * the chain element in the next frame.
4403 - * sgemax is the number of simple elements in an extra
4404 - * frame. Note that the value NextChainOffset should be
4405 - * in double-words (4 bytes).
4864 + * If this is the last cookie, we set the flags
4865 + * to indicate so
4406 4866 */
4407 - if (frames >= 2) {
4408 - ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4409 - (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4410 - } else {
4411 - ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4867 + if (cookiec == 0) {
4868 + flags |= end_flag;
4412 4869 }
4413 4870
4414 4871 /*
4415 - * Jump to next frame;
4416 - * Starting here, chain buffers go into the per command SGL.
4417 - * This buffer is allocated when chain buffers are needed.
4872 + * XXX: Hmmm, what about the direction based on
4873 + * cmd->cmd_flags & CFLAG_DMASEND?
4418 4874 */
4419 - sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4420 - i = cookiec;
4875 + ddi_put8(acc_hdl, &ieeesge->Flags, flags);
4876 + dmap++;
4877 + ieeesge++;
4878 + }
4879 +}
4421 4880
4422 - /*
4423 - * Start filling in frames with SGE's. If we
4424 - * reach the end of frame and still have SGE's
4425 - * to fill we need to add a chain element and
4426 - * use another frame. j will be our counter
4427 - * for what cookie we are at and i will be
4428 - * the total cookiec. k is the current frame
4429 - */
4430 - for (k = 1; k <= frames; k++) {
4431 - for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4881 +static void
4882 +mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4883 + pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4884 +{
4885 + pMpi2IeeeSgeSimple64_t ieeesge;
4886 + pMpi25IeeeSgeChain64_t ieeesgechain;
4887 + uint64_t nframe_phys_addr;
4888 + uint_t cookiec;
4889 + mptti_t *dmap;
4890 + uint8_t flags;
4891 + int i, j, k, l, frames, sgemax;
4892 + int temp, maxframe_sges;
4893 + uint8_t chainflags;
4894 + uint32_t chainlength;
4895 + mptsas_cache_frames_t *p;
4432 4896
4433 - /*
4434 - * If we have reached the end of frame
4435 - * and we have more SGE's to fill in
4436 - * we have to fill the final entry
4437 - * with a chain element and then
4438 - * continue to the next frame
4439 - */
4440 - if ((l == (sgemax + 1)) && (k != frames)) {
4441 - sgechain = (pMpi2SGEChain64_t)sge;
4442 - j--;
4443 - chainflags = (
4444 - MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4445 - MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4446 - MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4447 - ddi_put8(p->m_acc_hdl,
4448 - &sgechain->Flags, chainflags);
4449 - /*
4450 - * k is the frame counter and (k + 1)
4451 - * is the number of the next frame.
4452 - * Note that frames are in contiguous
4453 - * memory space.
4454 - */
4455 - ddi_put32(p->m_acc_hdl,
4456 - &sgechain->Address.Low,
4457 - (p->m_phys_addr +
4458 - (mpt->m_req_frame_size * k)));
4459 - ddi_put32(p->m_acc_hdl,
4460 - &sgechain->Address.High, 0);
4897 + cookiec = cmd->cmd_cookiec;
4461 4898
4462 - /*
4463 - * If there are more than 2 frames left
4464 - * we have to next chain offset to
4465 - * the location of the chain element
4466 - * in the next frame and fill in the
4467 - * length of the next chain
4468 - */
4469 - if ((frames - k) >= 2) {
4470 - ddi_put8(p->m_acc_hdl,
4471 - &sgechain->NextChainOffset,
4472 - (sgemax *
4473 - sizeof (MPI2_SGE_SIMPLE64))
4474 - >> 2);
4475 - ddi_put16(p->m_acc_hdl,
4476 - &sgechain->Length,
4477 - mpt->m_req_frame_size /
4478 - sizeof (MPI2_SGE_SIMPLE64) *
4479 - sizeof (MPI2_SGE_SIMPLE64));
4480 - } else {
4481 - /*
4482 - * This is the last frame. Set
4483 - * the NextChainOffset to 0 and
4484 - * Length is the total size of
4485 - * all remaining simple elements
4486 - */
4487 - ddi_put8(p->m_acc_hdl,
4488 - &sgechain->NextChainOffset,
4489 - 0);
4490 - ddi_put16(p->m_acc_hdl,
4491 - &sgechain->Length,
4492 - (cookiec - j) *
4493 - sizeof (MPI2_SGE_SIMPLE64));
4494 - }
4899 + NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec));
4495 4900
4496 - /* Jump to the next frame */
4497 - sge = (pMpi2SGESimple64_t)
4498 - ((char *)p->m_frames_addr +
4499 - (int)mpt->m_req_frame_size * k);
4901 + /*
4902 + * Hereby we start to deal with multiple frames.
4903 + * The process is as follows:
4904 + * 1. Determine how many frames are needed for SGL element
4905 + * storage; Note that all frames are stored in contiguous
4906 + * memory space and in 64-bit DMA mode each element is
4907 + * 4 double-words (16 bytes) long.
4908 + * 2. Fill up the main frame. We need to do this separately
4909 + * since it contains the SCSI IO request header and needs
4910 + * dedicated processing. Note that the last 4 double-words
4911 + * of the SCSI IO header is for SGL element storage
4912 + * (MPI2_SGE_IO_UNION).
4913 + * 3. Fill the chain element in the main frame, so the DMA
4914 + * engine can use the following frames.
4915 + * 4. Enter a loop to fill the remaining frames. Note that the
4916 + * last frame contains no chain element. The remaining
4917 + * frames go into the mpt SGL buffer allocated on the fly,
4918 + * not immediately following the main message frame, as in
4919 + * Gen1.
4920 + * Some restrictions:
4921 + * 1. For 64-bit DMA, the simple element and chain element
4922 + * are both of 4 double-words (16 bytes) in size, even
4923 + * though all frames are stored in the first 4G of mem
4924 + * range and the higher 32-bits of the address are always 0.
4925 + * 2. On some controllers (like the 1064/1068), a frame can
4926 + * hold SGL elements with the last 1 or 2 double-words
4927 + * (4 or 8 bytes) un-used. On these controllers, we should
4928 + * recognize that there's not enough room for another SGL
4929 + * element and move the sge pointer to the next frame.
4930 + */
4500 4931
4501 - continue;
4502 - }
4932 + /*
4933 + * Sgemax is the number of SGE's that will fit
4934 + * each extra frame and frames is total
4935 + * number of frames we'll need. 1 sge entry per
4936 + * frame is reseverd for the chain element thus the -1 below.
4937 + */
4938 + sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64))
4939 + - 1);
4940 + maxframe_sges = MPTSAS_MAX_FRAME_SGES64(mpt);
4941 + temp = (cookiec - (maxframe_sges - 1)) / sgemax;
4503 4942
4504 - ddi_put32(p->m_acc_hdl,
4505 - &sge->Address.Low,
4506 - dmap->addr.address64.Low);
4507 - ddi_put32(p->m_acc_hdl,
4508 - &sge->Address.High,
4509 - dmap->addr.address64.High);
4510 - ddi_put32(p->m_acc_hdl,
4511 - &sge->FlagsLength, dmap->count);
4512 - flags = ddi_get32(p->m_acc_hdl,
4513 - &sge->FlagsLength);
4514 - flags |= ((uint32_t)(
4515 - MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4516 - MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4517 - MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4518 - MPI2_SGE_FLAGS_SHIFT);
4943 + /*
4944 + * A little check to see if we need to round up the number
4945 + * of frames we need
4946 + */
4947 + if ((cookiec - (maxframe_sges - 1)) - (temp * sgemax) > 1) {
4948 + frames = (temp + 1);
4949 + } else {
4950 + frames = temp;
4951 + }
4952 + NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames));
4953 + dmap = cmd->cmd_sg;
4954 + ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4955 +
4956 + /*
4957 + * First fill in the main frame
4958 + */
4959 + j = maxframe_sges - 1;
4960 + mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0);
4961 + dmap += j;
4962 + ieeesge += j;
4963 + j++;
4964 +
4965 + /*
4966 + * Fill in the chain element in the main frame.
4967 + * About calculation on ChainOffset:
4968 + * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4969 + * in the end reserved for SGL element storage
4970 + * (MPI2_SGE_IO_UNION); we should count it in our
4971 + * calculation. See its definition in the header file.
4972 + * 2. Constant j is the counter of the current SGL element
4973 + * that will be processed, and (j - 1) is the number of
4974 + * SGL elements that have been processed (stored in the
4975 + * main frame).
4976 + * 3. ChainOffset value should be in units of quad-words (16
4977 + * bytes) so the last value should be divided by 16.
4978 + */
4979 + ddi_put8(acc_hdl, &frame->ChainOffset,
4980 + (sizeof (MPI2_SCSI_IO_REQUEST) -
4981 + sizeof (MPI2_SGE_IO_UNION) +
4982 + (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4983 + ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4984 + chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4985 + MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4986 + ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags);
4987 +
4988 + /*
4989 + * The size of the next frame is the accurate size of space
4990 + * (in bytes) used to store the SGL elements. j is the counter
4991 + * of SGL elements. (j - 1) is the number of SGL elements that
4992 + * have been processed (stored in frames).
4993 + */
4994 + if (frames >= 2) {
4995 + chainlength = mpt->m_req_frame_size /
4996 + sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4997 + sizeof (MPI2_IEEE_SGE_SIMPLE64);
4998 + } else {
4999 + chainlength = ((cookiec - (j - 1)) *
5000 + sizeof (MPI2_IEEE_SGE_SIMPLE64));
5001 + }
5002 +
5003 + p = cmd->cmd_extra_frames;
5004 +
5005 + ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength);
5006 + ddi_put32(acc_hdl, &ieeesgechain->Address.Low,
5007 + p->m_phys_addr&0xffffffffull);
5008 + ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr>>32);
5009 +
5010 + /*
5011 + * If there are more than 2 frames left we have to
5012 + * fill in the next chain offset to the location of
5013 + * the chain element in the next frame.
5014 + * sgemax is the number of simple elements in an extra
5015 + * frame. Note that the value NextChainOffset should be
5016 + * in double-words (4 bytes).
5017 + */
5018 + if (frames >= 2) {
5019 + ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset,
5020 + (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
5021 + } else {
5022 + ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0);
5023 + }
4519 5024
5025 + /*
5026 + * Jump to next frame;
5027 + * Starting here, chain buffers go into the per command SGL.
5028 + * This buffer is allocated when chain buffers are needed.
5029 + */
5030 + ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr;
5031 + i = cookiec;
5032 +
5033 + /*
5034 + * Start filling in frames with SGE's. If we
5035 + * reach the end of frame and still have SGE's
5036 + * to fill we need to add a chain element and
5037 + * use another frame. j will be our counter
5038 + * for what cookie we are at and i will be
5039 + * the total cookiec. k is the current frame
5040 + */
5041 + for (k = 1; k <= frames; k++) {
5042 + for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
5043 +
5044 + /*
5045 + * If we have reached the end of frame
5046 + * and we have more SGE's to fill in
5047 + * we have to fill the final entry
5048 + * with a chain element and then
5049 + * continue to the next frame
5050 + */
5051 + if ((l == (sgemax + 1)) && (k != frames)) {
5052 + ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
5053 + j--;
5054 + chainflags =
5055 + MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
5056 + MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
5057 + ddi_put8(p->m_acc_hdl,
5058 + &ieeesgechain->Flags, chainflags);
4520 5059 /*
4521 - * If we are at the end of the frame and
4522 - * there is another frame to fill in
4523 - * we set the last simple element as last
4524 - * element
5060 + * k is the frame counter and (k + 1)
5061 + * is the number of the next frame.
5062 + * Note that frames are in contiguous
5063 + * memory space.
4525 5064 */
4526 - if ((l == sgemax) && (k != frames)) {
4527 - flags |= ((uint32_t)
4528 - (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4529 - MPI2_SGE_FLAGS_SHIFT);
4530 - }
5065 + nframe_phys_addr = p->m_phys_addr +
5066 + (mpt->m_req_frame_size * k);
5067 + ddi_put32(p->m_acc_hdl,
5068 + &ieeesgechain->Address.Low,
5069 + nframe_phys_addr&0xffffffffull);
5070 + ddi_put32(p->m_acc_hdl,
5071 + &ieeesgechain->Address.High,
5072 + nframe_phys_addr>>32);
4531 5073
4532 5074 /*
4533 - * If this is the final cookie we
4534 - * indicate it by setting the flags
5075 + * If there are more than 2 frames left
5076 + * we have to next chain offset to
5077 + * the location of the chain element
5078 + * in the next frame and fill in the
5079 + * length of the next chain
4535 5080 */
4536 - if (j == i) {
4537 - flags |= ((uint32_t)
4538 - (MPI2_SGE_FLAGS_LAST_ELEMENT |
4539 - MPI2_SGE_FLAGS_END_OF_BUFFER |
4540 - MPI2_SGE_FLAGS_END_OF_LIST) <<
4541 - MPI2_SGE_FLAGS_SHIFT);
4542 - }
4543 - if (cmd->cmd_flags & CFLAG_DMASEND) {
4544 - flags |=
4545 - (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4546 - MPI2_SGE_FLAGS_SHIFT);
5081 + if ((frames - k) >= 2) {
5082 + ddi_put8(p->m_acc_hdl,
5083 + &ieeesgechain->NextChainOffset,
5084 + (sgemax *
5085 + sizeof (MPI2_IEEE_SGE_SIMPLE64))
5086 + >> 4);
5087 + ddi_put32(p->m_acc_hdl,
5088 + &ieeesgechain->Length,
5089 + mpt->m_req_frame_size /
5090 + sizeof (MPI2_IEEE_SGE_SIMPLE64) *
5091 + sizeof (MPI2_IEEE_SGE_SIMPLE64));
4547 5092 } else {
4548 - flags |=
4549 - (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4550 - MPI2_SGE_FLAGS_SHIFT);
5093 + /*
5094 + * This is the last frame. Set
5095 + * the NextChainOffset to 0 and
5096 + * Length is the total size of
5097 + * all remaining simple elements
5098 + */
5099 + ddi_put8(p->m_acc_hdl,
5100 + &ieeesgechain->NextChainOffset,
5101 + 0);
5102 + ddi_put32(p->m_acc_hdl,
5103 + &ieeesgechain->Length,
5104 + (cookiec - j) *
5105 + sizeof (MPI2_IEEE_SGE_SIMPLE64));
4551 5106 }
4552 - ddi_put32(p->m_acc_hdl,
4553 - &sge->FlagsLength, flags);
4554 - dmap++;
4555 - sge++;
5107 +
5108 + /* Jump to the next frame */
5109 + ieeesge = (pMpi2IeeeSgeSimple64_t)
5110 + ((char *)p->m_frames_addr +
5111 + (int)mpt->m_req_frame_size * k);
5112 +
5113 + continue;
5114 + }
5115 +
5116 + ddi_put32(p->m_acc_hdl,
5117 + &ieeesge->Address.Low,
5118 + dmap->addr.address64.Low);
5119 + ddi_put32(p->m_acc_hdl,
5120 + &ieeesge->Address.High,
5121 + dmap->addr.address64.High);
5122 + ddi_put32(p->m_acc_hdl,
5123 + &ieeesge->Length, dmap->count);
5124 + flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
5125 + MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
5126 +
5127 + /*
5128 + * If we are at the end of the frame and
5129 + * there is another frame to fill in
5130 + * do we need to do anything?
5131 + * if ((l == sgemax) && (k != frames)) {
5132 + * }
5133 + */
5134 +
5135 + /*
5136 + * If this is the final cookie set end of list.
5137 + */
5138 + if (j == i) {
5139 + flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
4556 5140 }
5141 +
5142 + ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags);
5143 + dmap++;
5144 + ieeesge++;
4557 5145 }
5146 + }
4558 5147
4559 - /*
4560 - * Sync DMA with the chain buffers that were just created
4561 - */
4562 - (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
5148 + /*
5149 + * Sync DMA with the chain buffers that were just created
5150 + */
5151 + (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
5152 +}
5153 +
5154 +static void
5155 +mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
5156 + pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
5157 +{
5158 + ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
5159 +
5160 + NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec));
5161 +
5162 + /*
5163 + * Set read/write bit in control.
5164 + */
5165 + if (cmd->cmd_flags & CFLAG_DMASEND) {
5166 + *control |= MPI2_SCSIIO_CONTROL_WRITE;
5167 + } else {
5168 + *control |= MPI2_SCSIIO_CONTROL_READ;
5169 + }
5170 +
5171 + ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
5172 +
5173 + /*
5174 + * We have 4 cases here. First where we can fit all the
5175 + * SG elements into the main frame, and the case
5176 + * where we can't. The SG element is also different when using
5177 + * MPI2.5 interface.
5178 + * If we have more cookies than we can attach to a frame
5179 + * we will need to use a chain element to point
5180 + * a location of memory where the rest of the S/G
5181 + * elements reside.
5182 + */
5183 + if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
5184 + if (mpt->m_MPI25) {
5185 + mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl,
5186 + cmd->cmd_cookiec,
5187 + MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
5188 + } else {
5189 + mptsas_sge_mainframe(cmd, frame, acc_hdl,
5190 + cmd->cmd_cookiec,
5191 + ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
5192 + | MPI2_SGE_FLAGS_END_OF_BUFFER
5193 + | MPI2_SGE_FLAGS_END_OF_LIST) <<
5194 + MPI2_SGE_FLAGS_SHIFT));
5195 + }
5196 + } else {
5197 + if (mpt->m_MPI25) {
5198 + mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl);
5199 + } else {
5200 + mptsas_sge_chain(mpt, cmd, frame, acc_hdl);
5201 + }
4563 5202 }
4564 5203 }
4565 5204
4566 5205 /*
4567 5206 * Interrupt handling
4568 5207 * Utility routine. Poll for status of a command sent to HBA
4569 5208 * without interrupts (a FLAG_NOINTR command).
4570 5209 */
4571 5210 int
4572 5211 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
4573 5212 {
4574 - int rval = TRUE;
5213 + int rval = TRUE;
5214 + uint32_t int_mask;
4575 5215
4576 - NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
5216 + NDBG5(("mptsas_poll: cmd=0x%p, flags 0x%x", (void *)poll_cmd,
5217 + poll_cmd->cmd_flags));
5218 +
5219 + /*
5220 + * Get the current interrupt mask and disable interrupts. When
5221 + * re-enabling ints, set mask to saved value.
5222 + */
5223 + int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
5224 + MPTSAS_DISABLE_INTR(mpt);
5225 +
5226 + mpt->m_polled_intr = 1;
4577 5227
4578 5228 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
4579 5229 mptsas_restart_hba(mpt);
4580 5230 }
4581 5231
4582 5232 /*
4583 5233 * Wait, using drv_usecwait(), long enough for the command to
4584 5234 * reasonably return from the target if the target isn't
4585 5235 * "dead". A polled command may well be sent from scsi_poll, and
4586 5236 * there are retries built in to scsi_poll if the transport
4587 5237 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
4588 5238 * and retries the transport up to scsi_poll_busycnt times
4589 5239 * (currently 60) if
4590 5240 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
4591 5241 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
4592 5242 *
4593 5243 * limit the waiting to avoid a hang in the event that the
4594 5244 * cmd never gets started but we are still receiving interrupts
4595 5245 */
4596 5246 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
4597 5247 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
4598 5248 NDBG5(("mptsas_poll: command incomplete"));
4599 5249 rval = FALSE;
4600 5250 break;
4601 5251 }
4602 5252 }
4603 5253
4604 5254 if (rval == FALSE) {
4605 5255
4606 5256 /*
4607 5257 * this isn't supposed to happen, the hba must be wedged
4608 5258 * Mark this cmd as a timeout.
4609 5259 */
4610 5260 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
4611 5261 (STAT_TIMEOUT|STAT_ABORTED));
4612 5262
4613 5263 if (poll_cmd->cmd_queued == FALSE) {
4614 5264
4615 5265 NDBG5(("mptsas_poll: not on waitq"));
4616 5266
4617 5267 poll_cmd->cmd_pkt->pkt_state |=
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4618 5268 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
4619 5269 } else {
4620 5270
4621 5271 /* find and remove it from the waitq */
4622 5272 NDBG5(("mptsas_poll: delete from waitq"));
4623 5273 mptsas_waitq_delete(mpt, poll_cmd);
4624 5274 }
4625 5275
4626 5276 }
4627 5277 mptsas_fma_check(mpt, poll_cmd);
5278 +
5279 + /*
5280 + * Clear polling flag, re-enable interrupts.
5281 + */
5282 + mpt->m_polled_intr = 0;
5283 + ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
5284 +
5285 + /*
5286 + * If there are queued cmd, start them now.
5287 + */
5288 + if (mpt->m_waitq != NULL) {
5289 + mptsas_restart_waitq(mpt);
5290 + }
5291 +
4628 5292 NDBG5(("mptsas_poll: done"));
4629 5293 return (rval);
4630 5294 }
4631 5295
4632 5296 /*
4633 5297 * Used for polling cmds and TM function
4634 5298 */
4635 5299 static int
4636 5300 mptsas_wait_intr(mptsas_t *mpt, int polltime)
4637 5301 {
4638 - int cnt;
5302 + int cnt, rval = FALSE;
4639 5303 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
4640 - uint32_t int_mask;
5304 + mptsas_reply_pqueue_t *rpqp;
4641 5305
4642 5306 NDBG5(("mptsas_wait_intr"));
4643 -
4644 - mpt->m_polled_intr = 1;
5307 + ASSERT(mutex_owned(&mpt->m_mutex));
4645 5308
4646 5309 /*
4647 - * Get the current interrupt mask and disable interrupts. When
4648 - * re-enabling ints, set mask to saved value.
5310 + * Keep polling for at least (polltime * 1000) seconds
4649 5311 */
4650 - int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
4651 - MPTSAS_DISABLE_INTR(mpt);
5312 + rpqp = mpt->m_rep_post_queues;
4652 5313
4653 5314 /*
4654 - * Keep polling for at least (polltime * 1000) seconds
5315 + * Drop the main mutex and grab the mutex for reply queue 0
4655 5316 */
5317 + mutex_exit(&mpt->m_mutex);
5318 + mutex_enter(&rpqp->rpq_mutex);
4656 5319 for (cnt = 0; cnt < polltime; cnt++) {
4657 5320 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
4658 5321 DDI_DMA_SYNC_FORCPU);
4659 5322
5323 + /*
5324 + * Polled requests should only come back through
5325 + * the first interrupt.
5326 + */
4660 5327 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
4661 - MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5328 + MPTSAS_GET_NEXT_REPLY(rpqp, rpqp->rpq_index);
4662 5329
4663 5330 if (ddi_get32(mpt->m_acc_post_queue_hdl,
4664 5331 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
4665 5332 ddi_get32(mpt->m_acc_post_queue_hdl,
4666 5333 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
4667 5334 drv_usecwait(1000);
4668 5335 continue;
4669 5336 }
4670 5337
4671 5338 /*
4672 5339 * The reply is valid, process it according to its
4673 5340 * type.
4674 5341 */
4675 - mptsas_process_intr(mpt, reply_desc_union);
4676 -
4677 - if (++mpt->m_post_index == mpt->m_post_queue_depth) {
4678 - mpt->m_post_index = 0;
4679 - }
5342 + mptsas_process_intr(mpt, rpqp, reply_desc_union);
4680 5343
4681 5344 /*
4682 - * Update the global reply index
5345 + * Clear the reply descriptor for re-use.
4683 5346 */
4684 - ddi_put32(mpt->m_datap,
4685 - &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
4686 - mpt->m_polled_intr = 0;
5347 + ddi_put64(mpt->m_acc_post_queue_hdl,
5348 + &((uint64_t *)(void *)rpqp->rpq_queue)[rpqp->rpq_index],
5349 + 0xFFFFFFFFFFFFFFFF);
5350 + (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5351 + DDI_DMA_SYNC_FORDEV);
5352 +
5353 + if (++rpqp->rpq_index == mpt->m_post_queue_depth) {
5354 + rpqp->rpq_index = 0;
5355 + }
4687 5356
4688 5357 /*
4689 - * Re-enable interrupts and quit.
5358 + * Update the reply index
4690 5359 */
4691 - ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
4692 - int_mask);
4693 - return (TRUE);
4694 -
5360 + ddi_put32(mpt->m_datap,
5361 + &mpt->m_reg->ReplyPostHostIndex, rpqp->rpq_index);
5362 + rval = TRUE;
5363 + break;
4695 5364 }
4696 5365
4697 - /*
4698 - * Clear polling flag, re-enable interrupts and quit.
4699 - */
4700 - mpt->m_polled_intr = 0;
4701 - ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
4702 - return (FALSE);
5366 + mutex_exit(&rpqp->rpq_mutex);
5367 + mutex_enter(&mpt->m_mutex);
5368 +
5369 + return (rval);
4703 5370 }
4704 5371
4705 5372 static void
4706 5373 mptsas_handle_scsi_io_success(mptsas_t *mpt,
5374 + mptsas_reply_pqueue_t *rpqp,
4707 5375 pMpi2ReplyDescriptorsUnion_t reply_desc)
4708 5376 {
4709 5377 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
4710 5378 uint16_t SMID;
4711 5379 mptsas_slots_t *slots = mpt->m_active;
4712 5380 mptsas_cmd_t *cmd = NULL;
4713 5381 struct scsi_pkt *pkt;
4714 5382
4715 - ASSERT(mutex_owned(&mpt->m_mutex));
4716 -
4717 5383 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
4718 5384 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID);
4719 5385
4720 5386 /*
4721 5387 * This is a success reply so just complete the IO. First, do a sanity
4722 5388 * check on the SMID. The final slot is used for TM requests, which
4723 5389 * would not come into this reply handler.
4724 5390 */
4725 5391 if ((SMID == 0) || (SMID > slots->m_n_normal)) {
4726 5392 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
4727 5393 SMID);
4728 5394 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4729 5395 return;
4730 5396 }
4731 5397
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4732 5398 cmd = slots->m_slot[SMID];
4733 5399
4734 5400 /*
4735 5401 * print warning and return if the slot is empty
4736 5402 */
4737 5403 if (cmd == NULL) {
4738 5404 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
4739 5405 "in slot %d", SMID);
4740 5406 return;
4741 5407 }
5408 + ASSERT(cmd->cmd_rpqidx == rpqp->rpq_num);
4742 5409
4743 5410 pkt = CMD2PKT(cmd);
4744 5411 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
4745 5412 STATE_GOT_STATUS);
4746 5413 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4747 5414 pkt->pkt_state |= STATE_XFERRED_DATA;
4748 5415 }
4749 5416 pkt->pkt_resid = 0;
4750 5417
4751 5418 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
4752 5419 cmd->cmd_flags |= CFLAG_FINISHED;
4753 5420 cv_broadcast(&mpt->m_passthru_cv);
4754 5421 return;
4755 - } else {
4756 - mptsas_remove_cmd(mpt, cmd);
5422 + }
5423 + if (!(cmd->cmd_flags & CFLAG_TM_CMD)) {
5424 + if (cmd->cmd_flags & CFLAG_CMDIOC) {
5425 + mutex_enter(&mpt->m_mutex);
5426 + mptsas_remove_cmd(mpt, cmd);
5427 + mutex_exit(&mpt->m_mutex);
5428 + } else {
5429 +#ifdef MPTSAS_DEBUG
5430 + /*
5431 + * In order to test timeout for a command set
5432 + * mptsas_test_timeout via mdb to avoid completion
5433 + * processing here.
5434 + */
5435 + if (mptsas_test_timeout) {
5436 + mptsas_test_timeout = 0;
5437 + return;
5438 + }
5439 +#endif
5440 + /*
5441 + * This is the normal path, avoid grabbing
5442 + * the m_mutex.
5443 + */
5444 + mptsas_remove_cmd_nomtx(mpt, cmd);
5445 + }
4757 5446 }
4758 5447
4759 5448 if (cmd->cmd_flags & CFLAG_RETRY) {
4760 5449 /*
4761 5450 * The target returned QFULL or busy, do not add tihs
4762 5451 * pkt to the doneq since the hba will retry
4763 5452 * this cmd.
4764 5453 *
4765 5454 * The pkt has already been resubmitted in
4766 5455 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4767 5456 * Remove this cmd_flag here.
4768 5457 */
4769 5458 cmd->cmd_flags &= ~CFLAG_RETRY;
4770 5459 } else {
4771 - mptsas_doneq_add(mpt, cmd);
5460 + mptsas_rpdoneq_add(mpt, rpqp, cmd);
4772 5461 }
4773 5462 }
4774 5463
4775 5464 static void
4776 5465 mptsas_handle_address_reply(mptsas_t *mpt,
4777 5466 pMpi2ReplyDescriptorsUnion_t reply_desc)
4778 5467 {
4779 5468 pMpi2AddressReplyDescriptor_t address_reply;
4780 5469 pMPI2DefaultReply_t reply;
4781 5470 mptsas_fw_diagnostic_buffer_t *pBuffer;
4782 - uint32_t reply_addr;
5471 + uint32_t reply_addr, reply_frame_dma_baseaddr;
4783 5472 uint16_t SMID, iocstatus;
4784 5473 mptsas_slots_t *slots = mpt->m_active;
4785 5474 mptsas_cmd_t *cmd = NULL;
4786 5475 uint8_t function, buffer_type;
4787 5476 m_replyh_arg_t *args;
4788 5477 int reply_frame_no;
4789 5478
4790 5479 ASSERT(mutex_owned(&mpt->m_mutex));
4791 5480
4792 5481 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
4793 5482 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl,
4794 5483 &address_reply->ReplyFrameAddress);
4795 5484 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID);
4796 5485
4797 5486 /*
4798 5487 * If reply frame is not in the proper range we should ignore this
4799 5488 * message and exit the interrupt handler.
4800 5489 */
4801 - if ((reply_addr < mpt->m_reply_frame_dma_addr) ||
4802 - (reply_addr >= (mpt->m_reply_frame_dma_addr +
5490 + reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xfffffffful;
5491 + if ((reply_addr < reply_frame_dma_baseaddr) ||
5492 + (reply_addr >= (reply_frame_dma_baseaddr +
4803 5493 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
4804 - ((reply_addr - mpt->m_reply_frame_dma_addr) %
5494 + ((reply_addr - reply_frame_dma_baseaddr) %
4805 5495 mpt->m_reply_frame_size != 0)) {
4806 5496 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
4807 5497 "address 0x%x\n", reply_addr);
4808 5498 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4809 5499 return;
4810 5500 }
4811 5501
4812 5502 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
4813 5503 DDI_DMA_SYNC_FORCPU);
4814 5504 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
4815 - mpt->m_reply_frame_dma_addr));
5505 + reply_frame_dma_baseaddr));
4816 5506 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
4817 5507
5508 + NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x",
5509 + function, reply_addr));
5510 +
4818 5511 /*
4819 5512 * don't get slot information and command for events since these values
4820 5513 * don't exist
4821 5514 */
4822 5515 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
4823 5516 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
4824 5517 /*
4825 5518 * This could be a TM reply, which use the last allocated SMID,
4826 5519 * so allow for that.
4827 5520 */
4828 5521 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) {
4829 5522 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
4830 5523 "%d\n", SMID);
4831 5524 ddi_fm_service_impact(mpt->m_dip,
4832 5525 DDI_SERVICE_UNAFFECTED);
4833 5526 return;
4834 5527 }
4835 5528
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4836 5529 cmd = slots->m_slot[SMID];
4837 5530
4838 5531 /*
4839 5532 * print warning and return if the slot is empty
4840 5533 */
4841 5534 if (cmd == NULL) {
4842 5535 mptsas_log(mpt, CE_WARN, "?NULL command for address "
4843 5536 "reply in slot %d", SMID);
4844 5537 return;
4845 5538 }
4846 - if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
4847 - (cmd->cmd_flags & CFLAG_CONFIG) ||
4848 - (cmd->cmd_flags & CFLAG_FW_DIAG)) {
5539 + if ((cmd->cmd_flags &
5540 + (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
4849 5541 cmd->cmd_rfm = reply_addr;
4850 5542 cmd->cmd_flags |= CFLAG_FINISHED;
4851 5543 cv_broadcast(&mpt->m_passthru_cv);
4852 5544 cv_broadcast(&mpt->m_config_cv);
4853 5545 cv_broadcast(&mpt->m_fw_diag_cv);
4854 5546 return;
4855 5547 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
4856 5548 mptsas_remove_cmd(mpt, cmd);
4857 5549 }
4858 5550 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
4859 5551 }
4860 5552 /*
4861 5553 * Depending on the function, we need to handle
4862 5554 * the reply frame (and cmd) differently.
4863 5555 */
4864 5556 switch (function) {
4865 5557 case MPI2_FUNCTION_SCSI_IO_REQUEST:
4866 5558 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
4867 5559 break;
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4868 5560 case MPI2_FUNCTION_SCSI_TASK_MGMT:
4869 5561 cmd->cmd_rfm = reply_addr;
4870 5562 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
4871 5563 cmd);
4872 5564 break;
4873 5565 case MPI2_FUNCTION_FW_DOWNLOAD:
4874 5566 cmd->cmd_flags |= CFLAG_FINISHED;
4875 5567 cv_signal(&mpt->m_fw_cv);
4876 5568 break;
4877 5569 case MPI2_FUNCTION_EVENT_NOTIFICATION:
4878 - reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) /
5570 + reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) /
4879 5571 mpt->m_reply_frame_size;
4880 5572 args = &mpt->m_replyh_args[reply_frame_no];
4881 5573 args->mpt = (void *)mpt;
4882 5574 args->rfm = reply_addr;
4883 5575
4884 5576 /*
4885 5577 * Record the event if its type is enabled in
4886 5578 * this mpt instance by ioctl.
4887 5579 */
4888 5580 mptsas_record_event(args);
4889 5581
4890 5582 /*
4891 5583 * Handle time critical events
4892 5584 * NOT_RESPONDING/ADDED only now
4893 5585 */
4894 5586 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
4895 5587 /*
4896 5588 * Would not return main process,
4897 5589 * just let taskq resolve ack action
4898 5590 * and ack would be sent in taskq thread
4899 5591 */
4900 5592 NDBG20(("send mptsas_handle_event_sync success"));
4901 5593 }
4902 5594
4903 5595 if (mpt->m_in_reset) {
4904 5596 NDBG20(("dropping event received during reset"));
4905 5597 return;
4906 5598 }
4907 5599
4908 5600 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
4909 5601 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
4910 5602 mptsas_log(mpt, CE_WARN, "No memory available"
4911 5603 "for dispatch taskq");
4912 5604 /*
4913 5605 * Return the reply frame to the free queue.
4914 5606 */
4915 5607 ddi_put32(mpt->m_acc_free_queue_hdl,
4916 5608 &((uint32_t *)(void *)
4917 5609 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
4918 5610 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4919 5611 DDI_DMA_SYNC_FORDEV);
4920 5612 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
4921 5613 mpt->m_free_index = 0;
4922 5614 }
4923 5615
4924 5616 ddi_put32(mpt->m_datap,
4925 5617 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
4926 5618 }
4927 5619 return;
4928 5620 case MPI2_FUNCTION_DIAG_BUFFER_POST:
4929 5621 /*
4930 5622 * If SMID is 0, this implies that the reply is due to a
4931 5623 * release function with a status that the buffer has been
4932 5624 * released. Set the buffer flags accordingly.
4933 5625 */
4934 5626 if (SMID == 0) {
4935 5627 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
4936 5628 &reply->IOCStatus);
4937 5629 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
4938 5630 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
4939 5631 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
4940 5632 pBuffer =
4941 5633 &mpt->m_fw_diag_buffer_list[buffer_type];
4942 5634 pBuffer->valid_data = TRUE;
4943 5635 pBuffer->owned_by_firmware = FALSE;
4944 5636 pBuffer->immediate = FALSE;
4945 5637 }
4946 5638 } else {
4947 5639 /*
4948 5640 * Normal handling of diag post reply with SMID.
4949 5641 */
4950 5642 cmd = slots->m_slot[SMID];
4951 5643
4952 5644 /*
4953 5645 * print warning and return if the slot is empty
4954 5646 */
4955 5647 if (cmd == NULL) {
4956 5648 mptsas_log(mpt, CE_WARN, "?NULL command for "
4957 5649 "address reply in slot %d", SMID);
4958 5650 return;
4959 5651 }
4960 5652 cmd->cmd_rfm = reply_addr;
4961 5653 cmd->cmd_flags |= CFLAG_FINISHED;
4962 5654 cv_broadcast(&mpt->m_fw_diag_cv);
4963 5655 }
4964 5656 return;
4965 5657 default:
4966 5658 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
4967 5659 break;
4968 5660 }
4969 5661
4970 5662 /*
4971 5663 * Return the reply frame to the free queue.
4972 5664 */
4973 5665 ddi_put32(mpt->m_acc_free_queue_hdl,
4974 5666 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
4975 5667 reply_addr);
4976 5668 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4977 5669 DDI_DMA_SYNC_FORDEV);
4978 5670 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
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4979 5671 mpt->m_free_index = 0;
4980 5672 }
4981 5673 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
4982 5674 mpt->m_free_index);
4983 5675
4984 5676 if (cmd->cmd_flags & CFLAG_FW_CMD)
4985 5677 return;
4986 5678
4987 5679 if (cmd->cmd_flags & CFLAG_RETRY) {
4988 5680 /*
4989 - * The target returned QFULL or busy, do not add tihs
5681 + * The target returned QFULL or busy, do not add this
4990 5682 * pkt to the doneq since the hba will retry
4991 5683 * this cmd.
4992 5684 *
4993 5685 * The pkt has already been resubmitted in
4994 5686 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4995 5687 * Remove this cmd_flag here.
4996 5688 */
4997 5689 cmd->cmd_flags &= ~CFLAG_RETRY;
4998 5690 } else {
4999 5691 mptsas_doneq_add(mpt, cmd);
5000 5692 }
5001 5693 }
5002 5694
5695 +#ifdef MPTSAS_DEBUG
5696 +static uint8_t mptsas_last_sense[256];
5697 +#endif
5698 +
5003 5699 static void
5004 5700 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
5005 5701 mptsas_cmd_t *cmd)
5006 5702 {
5007 5703 uint8_t scsi_status, scsi_state;
5008 - uint16_t ioc_status;
5704 + uint16_t ioc_status, cmd_rqs_len;
5009 5705 uint32_t xferred, sensecount, responsedata, loginfo = 0;
5010 5706 struct scsi_pkt *pkt;
5011 5707 struct scsi_arq_status *arqstat;
5012 - struct buf *bp;
5013 5708 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5014 5709 uint8_t *sensedata = NULL;
5015 -
5016 - if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
5017 - (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
5018 - bp = cmd->cmd_ext_arq_buf;
5019 - } else {
5020 - bp = cmd->cmd_arq_buf;
5021 - }
5710 + uint64_t sas_wwn;
5711 + uint8_t phy;
5712 + char wwn_str[MPTSAS_WWN_STRLEN];
5022 5713
5023 5714 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
5024 5715 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5025 5716 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
5026 5717 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
5027 5718 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
5028 5719 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
5029 5720 &reply->ResponseInfo);
5030 5721
5031 5722 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
5723 + sas_wwn = ptgt->m_addr.mta_wwn;
5724 + phy = ptgt->m_phynum;
5725 + if (sas_wwn == 0) {
5726 + (void) sprintf(wwn_str, "p%x", phy);
5727 + } else {
5728 + (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
5729 + }
5032 5730 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
5033 5731 &reply->IOCLogInfo);
5034 5732 mptsas_log(mpt, CE_NOTE,
5035 - "?Log info 0x%x received for target %d.\n"
5733 + "?Log info 0x%x received for target %d %s.\n"
5036 5734 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5037 - loginfo, Tgt(cmd), scsi_status, ioc_status,
5735 + loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status,
5038 5736 scsi_state);
5039 5737 }
5040 5738
5041 5739 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5042 5740 scsi_status, ioc_status, scsi_state));
5043 5741
5044 5742 pkt = CMD2PKT(cmd);
5045 5743 *(pkt->pkt_scbp) = scsi_status;
5046 5744
5047 5745 if (loginfo == 0x31170000) {
5048 5746 /*
5049 5747 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
5050 5748 * 0x31170000 comes, that means the device missing delay
5051 5749 * is in progressing, the command need retry later.
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5052 5750 */
5053 5751 *(pkt->pkt_scbp) = STATUS_BUSY;
5054 5752 return;
5055 5753 }
5056 5754
5057 5755 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
5058 5756 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
5059 5757 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
5060 5758 pkt->pkt_reason = CMD_INCOMPLETE;
5061 5759 pkt->pkt_state |= STATE_GOT_BUS;
5760 + mutex_enter(&ptgt->m_t_mutex);
5062 5761 if (ptgt->m_reset_delay == 0) {
5063 5762 mptsas_set_throttle(mpt, ptgt,
5064 5763 DRAIN_THROTTLE);
5065 5764 }
5765 + mutex_exit(&ptgt->m_t_mutex);
5066 5766 return;
5067 5767 }
5068 5768
5069 5769 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
5070 5770 responsedata &= 0x000000FF;
5071 5771 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
5072 5772 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
5073 5773 pkt->pkt_reason = CMD_TLR_OFF;
5074 5774 return;
5075 5775 }
5076 5776 }
5077 5777
5078 5778
5079 5779 switch (scsi_status) {
5080 5780 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5781 + (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
5782 + DDI_DMA_SYNC_FORCPU);
5081 5783 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5082 5784 arqstat = (void*)(pkt->pkt_scbp);
5083 5785 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5084 5786 (pkt->pkt_scbp));
5085 5787 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5086 5788 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5087 5789 if (cmd->cmd_flags & CFLAG_XARQ) {
5088 5790 pkt->pkt_state |= STATE_XARQ_DONE;
5089 5791 }
5090 5792 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5091 5793 pkt->pkt_state |= STATE_XFERRED_DATA;
5092 5794 }
5093 5795 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5094 5796 arqstat->sts_rqpkt_state = pkt->pkt_state;
5095 5797 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5096 5798 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5097 5799 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5098 -
5099 - bcopy((uchar_t *)bp->b_un.b_addr, sensedata,
5800 +#ifdef MPTSAS_DEBUG
5801 + bcopy((uchar_t *)cmd->cmd_arq_buf, mptsas_last_sense,
5802 + cmd->cmd_rqslen);
5803 +#endif
5804 + if (cmd->cmd_extrqslen != 0) {
5805 + cmd_rqs_len = cmd->cmd_extrqslen;
5806 + } else {
5807 + cmd_rqs_len = cmd->cmd_rqslen;
5808 + }
5809 + bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata,
5100 5810 ((cmd->cmd_rqslen >= sensecount) ? sensecount :
5101 - cmd->cmd_rqslen));
5102 - arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount);
5811 + cmd_rqs_len));
5812 + arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount);
5103 5813 cmd->cmd_flags |= CFLAG_CMDARQ;
5104 5814 /*
5105 5815 * Set proper status for pkt if autosense was valid
5106 5816 */
5107 5817 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5108 5818 struct scsi_status zero_status = { 0 };
5109 5819 arqstat->sts_rqpkt_status = zero_status;
5110 5820 }
5111 5821
5112 5822 /*
5113 5823 * ASC=0x47 is parity error
5114 5824 * ASC=0x48 is initiator detected error received
5115 5825 */
5116 5826 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5117 5827 ((scsi_sense_asc(sensedata) == 0x47) ||
5118 5828 (scsi_sense_asc(sensedata) == 0x48))) {
5119 5829 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5120 5830 }
5121 5831
5122 5832 /*
5123 5833 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5124 5834 * ASC/ASCQ=0x25/0x00 means invalid lun
5125 5835 */
5126 5836 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5127 5837 (scsi_sense_asc(sensedata) == 0x3F) &&
5128 5838 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5129 5839 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5130 5840 (scsi_sense_asc(sensedata) == 0x25) &&
5131 5841 (scsi_sense_ascq(sensedata) == 0x00))) {
5132 5842 mptsas_topo_change_list_t *topo_node = NULL;
5133 5843
5134 5844 topo_node = kmem_zalloc(
5135 5845 sizeof (mptsas_topo_change_list_t),
5136 5846 KM_NOSLEEP);
5137 5847 if (topo_node == NULL) {
5138 5848 mptsas_log(mpt, CE_NOTE, "No memory"
5139 5849 "resource for handle SAS dynamic"
5140 5850 "reconfigure.\n");
5141 5851 break;
5142 5852 }
5143 5853 topo_node->mpt = mpt;
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5144 5854 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5145 5855 topo_node->un.phymask = ptgt->m_addr.mta_phymask;
5146 5856 topo_node->devhdl = ptgt->m_devhdl;
5147 5857 topo_node->object = (void *)ptgt;
5148 5858 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5149 5859
5150 5860 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5151 5861 mptsas_handle_dr,
5152 5862 (void *)topo_node,
5153 5863 DDI_NOSLEEP)) != DDI_SUCCESS) {
5864 + kmem_free(topo_node,
5865 + sizeof (mptsas_topo_change_list_t));
5154 5866 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5155 5867 "for handle SAS dynamic reconfigure"
5156 5868 "failed. \n");
5157 5869 }
5158 5870 }
5159 5871 break;
5160 5872 case MPI2_SCSI_STATUS_GOOD:
5161 5873 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5162 5874 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5163 5875 pkt->pkt_reason = CMD_DEV_GONE;
5164 5876 pkt->pkt_state |= STATE_GOT_BUS;
5877 + mutex_enter(&ptgt->m_t_mutex);
5165 5878 if (ptgt->m_reset_delay == 0) {
5166 5879 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5167 5880 }
5881 + mutex_exit(&ptgt->m_t_mutex);
5168 5882 NDBG31(("lost disk for target%d, command:%x",
5169 5883 Tgt(cmd), pkt->pkt_cdbp[0]));
5170 5884 break;
5171 5885 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5172 5886 NDBG31(("data overrun: xferred=%d", xferred));
5173 5887 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5174 5888 pkt->pkt_reason = CMD_DATA_OVR;
5175 5889 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5176 5890 | STATE_SENT_CMD | STATE_GOT_STATUS
5177 5891 | STATE_XFERRED_DATA);
5178 5892 pkt->pkt_resid = 0;
5179 5893 break;
5180 5894 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5181 5895 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
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5182 5896 NDBG31(("data underrun: xferred=%d", xferred));
5183 5897 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5184 5898 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5185 5899 | STATE_SENT_CMD | STATE_GOT_STATUS);
5186 5900 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5187 5901 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5188 5902 pkt->pkt_state |= STATE_XFERRED_DATA;
5189 5903 }
5190 5904 break;
5191 5905 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5192 - mptsas_set_pkt_reason(mpt,
5193 - cmd, CMD_RESET, STAT_BUS_RESET);
5906 + if (cmd->cmd_active_expiration <= gethrtime()) {
5907 + /*
5908 + * When timeout requested, propagate
5909 + * proper reason and statistics to
5910 + * target drivers.
5911 + */
5912 + mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT,
5913 + STAT_BUS_RESET | STAT_TIMEOUT);
5914 + } else {
5915 + mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
5916 + STAT_BUS_RESET);
5917 + }
5194 5918 break;
5195 5919 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5196 5920 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5197 5921 mptsas_set_pkt_reason(mpt,
5198 5922 cmd, CMD_RESET, STAT_DEV_RESET);
5199 5923 break;
5200 5924 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5201 5925 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5202 5926 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5203 5927 mptsas_set_pkt_reason(mpt,
5204 5928 cmd, CMD_TERMINATED, STAT_TERMINATED);
5205 5929 break;
5206 5930 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5207 5931 case MPI2_IOCSTATUS_BUSY:
5208 5932 /*
5209 5933 * set throttles to drain
5210 5934 */
5211 5935 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
5212 5936 ptgt = refhash_next(mpt->m_targets, ptgt)) {
5213 - mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5937 + mptsas_set_throttle_mtx(mpt, ptgt,
5938 + DRAIN_THROTTLE);
5214 5939 }
5215 5940
5216 5941 /*
5217 5942 * retry command
5218 5943 */
5219 - cmd->cmd_flags |= CFLAG_RETRY;
5220 - cmd->cmd_pkt_flags |= FLAG_HEAD;
5221 -
5222 - (void) mptsas_accept_pkt(mpt, cmd);
5944 + mptsas_retry_pkt(mpt, cmd);
5223 5945 break;
5224 5946 default:
5225 5947 mptsas_log(mpt, CE_WARN,
5226 5948 "unknown ioc_status = %x\n", ioc_status);
5227 5949 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5228 5950 "count = %x, scsi_status = %x", scsi_state,
5229 5951 xferred, scsi_status);
5230 5952 break;
5231 5953 }
5232 5954 break;
5233 5955 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5234 5956 mptsas_handle_qfull(mpt, cmd);
5235 5957 break;
5236 5958 case MPI2_SCSI_STATUS_BUSY:
5237 5959 NDBG31(("scsi_status busy received"));
5238 5960 break;
5239 5961 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5240 5962 NDBG31(("scsi_status reservation conflict received"));
5241 5963 break;
5242 5964 default:
5243 5965 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5244 5966 scsi_status, ioc_status);
5245 5967 mptsas_log(mpt, CE_WARN,
5246 5968 "mptsas_process_intr: invalid scsi status\n");
5247 5969 break;
5248 5970 }
5249 5971 }
5250 5972
5251 5973 static void
5252 5974 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5253 5975 mptsas_cmd_t *cmd)
5254 5976 {
5255 5977 uint8_t task_type;
5256 5978 uint16_t ioc_status;
5257 5979 uint32_t log_info;
5258 5980 uint16_t dev_handle;
5259 5981 struct scsi_pkt *pkt = CMD2PKT(cmd);
5260 5982
5261 5983 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5262 5984 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5263 5985 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5264 5986 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5265 5987
5266 5988 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5267 5989 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5268 5990 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5269 5991 task_type, ioc_status, log_info, dev_handle);
5270 5992 pkt->pkt_reason = CMD_INCOMPLETE;
5271 5993 return;
5272 5994 }
5273 5995
5274 5996 switch (task_type) {
5275 5997 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5276 5998 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5277 5999 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5278 6000 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5279 6001 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5280 6002 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5281 6003 break;
5282 6004 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5283 6005 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5284 6006 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5285 6007 /*
5286 6008 * Check for invalid DevHandle of 0 in case application
5287 6009 * sends bad command. DevHandle of 0 could cause problems.
5288 6010 */
5289 6011 if (dev_handle == 0) {
5290 6012 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5291 6013 " DevHandle of 0.");
5292 6014 } else {
5293 6015 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5294 6016 task_type);
5295 6017 }
|
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63 lines elided |
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5296 6018 break;
5297 6019 default:
5298 6020 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5299 6021 task_type);
5300 6022 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5301 6023 break;
5302 6024 }
5303 6025 }
5304 6026
5305 6027 static void
5306 -mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
6028 +mptsas_doneq_thread(mptsas_thread_arg_t *arg)
5307 6029 {
5308 6030 mptsas_t *mpt = arg->mpt;
5309 - uint64_t t = arg->t;
6031 + uint32_t t = arg->t;
5310 6032 mptsas_cmd_t *cmd;
5311 6033 struct scsi_pkt *pkt;
5312 6034 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
5313 6035
5314 6036 mutex_enter(&item->mutex);
5315 6037 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5316 - if (!item->doneq) {
6038 + if (!item->dlist.dl_q) {
5317 6039 cv_wait(&item->cv, &item->mutex);
5318 6040 }
5319 6041 pkt = NULL;
5320 6042 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5321 6043 cmd->cmd_flags |= CFLAG_COMPLETED;
5322 6044 pkt = CMD2PKT(cmd);
5323 6045 }
5324 6046 mutex_exit(&item->mutex);
5325 6047 if (pkt) {
5326 6048 mptsas_pkt_comp(pkt, cmd);
5327 6049 }
5328 6050 mutex_enter(&item->mutex);
5329 6051 }
5330 6052 mutex_exit(&item->mutex);
5331 - mutex_enter(&mpt->m_doneq_mutex);
6053 + mutex_enter(&mpt->m_qthread_mutex);
5332 6054 mpt->m_doneq_thread_n--;
5333 - cv_broadcast(&mpt->m_doneq_thread_cv);
5334 - mutex_exit(&mpt->m_doneq_mutex);
6055 + cv_broadcast(&mpt->m_qthread_cv);
6056 + mutex_exit(&mpt->m_qthread_mutex);
5335 6057 }
5336 6058
5337 6059
5338 6060 /*
5339 6061 * mpt interrupt handler.
5340 6062 */
5341 6063 static uint_t
5342 6064 mptsas_intr(caddr_t arg1, caddr_t arg2)
5343 6065 {
5344 6066 mptsas_t *mpt = (void *)arg1;
6067 + mptsas_reply_pqueue_t *rpqp;
6068 + int reply_q = (int)(uintptr_t)arg2;
5345 6069 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5346 - uchar_t did_reply = FALSE;
6070 + int found = 0, i, rpqidx;
6071 + size_t dma_sync_len;
6072 + off_t dma_sync_offset;
6073 + uint32_t istat;
5347 6074
5348 - NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
6075 + NDBG18(("mptsas_intr: arg1 0x%p reply_q 0x%d", (void *)arg1, reply_q));
5349 6076
5350 - mutex_enter(&mpt->m_mutex);
6077 + rpqp = &mpt->m_rep_post_queues[reply_q];
5351 6078
5352 6079 /*
5353 6080 * If interrupts are shared by two channels then check whether this
5354 6081 * interrupt is genuinely for this channel by making sure first the
5355 6082 * chip is in high power state.
5356 6083 */
5357 6084 if ((mpt->m_options & MPTSAS_OPT_PM) &&
5358 6085 (mpt->m_power_level != PM_LEVEL_D0)) {
5359 - mutex_exit(&mpt->m_mutex);
6086 + mpt->m_unclaimed_pm_interrupt_count++;
6087 + return (DDI_INTR_UNCLAIMED);
6088 + }
6089 +
6090 + istat = MPTSAS_GET_ISTAT(mpt);
6091 + if (!(istat & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)) {
6092 + NDBG18(("Interrupt bit not set, istat 0x%x", istat));
6093 + mpt->m_unclaimed_no_interrupt_count++;
6094 + /*
6095 + * Really need a good definition of when this is valid.
6096 + * It appears not to be if you have multiple reply post
6097 + * queues, there may be a better way - need LSI info.
6098 + * For now just count them.
6099 + */
6100 +#if 0
5360 6101 return (DDI_INTR_UNCLAIMED);
6102 +#endif
5361 6103 }
5362 6104
5363 6105 /*
5364 6106 * If polling, interrupt was triggered by some shared interrupt because
5365 6107 * IOC interrupts are disabled during polling, so polling routine will
5366 6108 * handle any replies. Considering this, if polling is happening,
5367 6109 * return with interrupt unclaimed.
5368 6110 */
5369 6111 if (mpt->m_polled_intr) {
5370 - mutex_exit(&mpt->m_mutex);
5371 - mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
6112 + mptsas_log(mpt, CE_WARN,
6113 + "Unclaimed interrupt, rpq %d (Polling), istat 0x%x",
6114 + reply_q, istat);
6115 + mpt->m_unclaimed_polled_interrupt_count++;
5372 6116 return (DDI_INTR_UNCLAIMED);
5373 6117 }
5374 6118
5375 6119 /*
5376 - * Read the istat register.
6120 + * At the moment this is the only place the mutex is grabbed.
6121 + * So it should never fail!
5377 6122 */
5378 - if ((INTPENDING(mpt)) != 0) {
5379 - /*
5380 - * read fifo until empty.
5381 - */
6123 + if (mutex_tryenter(&rpqp->rpq_mutex) == 0) {
6124 + mutex_enter(&rpqp->rpq_mutex);
6125 + rpqp->rpq_intr_mutexbusy++;
6126 + }
6127 +
6128 + dma_sync_len = mpt->m_post_queue_depth * 8;
6129 + dma_sync_offset = dma_sync_len * reply_q;
6130 + (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl,
6131 + dma_sync_offset, dma_sync_len, DDI_DMA_SYNC_FORCPU);
6132 +
6133 + /*
6134 + * Go around the reply queue and process each descriptor until
6135 + * we get to the next unused one.
6136 + * It seems to be an occupational hazard that we get interrupts
6137 + * with nothing to do. These are counted below.
6138 + */
6139 + rpqidx = rpqp->rpq_index;
5382 6140 #ifndef __lock_lint
5383 - _NOTE(CONSTCOND)
6141 + _NOTE(CONSTCOND)
5384 6142 #endif
5385 - while (TRUE) {
5386 - (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5387 - DDI_DMA_SYNC_FORCPU);
5388 - reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5389 - MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
6143 + while (TRUE) {
6144 + reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
6145 + MPTSAS_GET_NEXT_REPLY(rpqp, rpqidx);
5390 6146
5391 - if (ddi_get32(mpt->m_acc_post_queue_hdl,
5392 - &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5393 - ddi_get32(mpt->m_acc_post_queue_hdl,
5394 - &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5395 - break;
5396 - }
6147 + if (ddi_get32(mpt->m_acc_post_queue_hdl,
6148 + &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
6149 + ddi_get32(mpt->m_acc_post_queue_hdl,
6150 + &reply_desc_union->Words.High) == 0xFFFFFFFF) {
6151 + break;
6152 + }
5397 6153
5398 - /*
5399 - * The reply is valid, process it according to its
5400 - * type. Also, set a flag for updating the reply index
5401 - * after they've all been processed.
5402 - */
5403 - did_reply = TRUE;
6154 + found++;
5404 6155
5405 - mptsas_process_intr(mpt, reply_desc_union);
6156 + ASSERT(ddi_get8(mpt->m_acc_post_queue_hdl,
6157 + &reply_desc_union->Default.MSIxIndex) == reply_q);
5406 6158
5407 - /*
5408 - * Increment post index and roll over if needed.
5409 - */
5410 - if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5411 - mpt->m_post_index = 0;
5412 - }
5413 - }
6159 + /*
6160 + * Process it according to its type.
6161 + */
6162 + mptsas_process_intr(mpt, rpqp, reply_desc_union);
5414 6163
5415 6164 /*
5416 - * Update the global reply index if at least one reply was
5417 - * processed.
6165 + * Clear the reply descriptor for re-use.
5418 6166 */
5419 - if (did_reply) {
5420 - ddi_put32(mpt->m_datap,
5421 - &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
6167 + ddi_put64(mpt->m_acc_post_queue_hdl,
6168 + &((uint64_t *)(void *)rpqp->rpq_queue)[rpqidx],
6169 + 0xFFFFFFFFFFFFFFFF);
6170 +
6171 + /*
6172 + * Increment post index and roll over if needed.
6173 + */
6174 + if (++rpqidx == mpt->m_post_queue_depth) {
6175 + rpqidx = 0;
5422 6176 }
5423 - } else {
5424 - mutex_exit(&mpt->m_mutex);
6177 + }
6178 +
6179 + if (found == 0) {
6180 + rpqp->rpq_intr_unclaimed++;
6181 + mutex_exit(&rpqp->rpq_mutex);
6182 + mpt->m_unclaimed_nocmd_interrupt_count++;
5425 6183 return (DDI_INTR_UNCLAIMED);
5426 6184 }
5427 - NDBG1(("mptsas_intr complete"));
6185 + rpqp->rpq_index = rpqidx;
6186 +
6187 + rpqp->rpq_intr_count++;
6188 + NDBG18(("mptsas_intr complete(%d), did %d loops", reply_q, found));
6189 +
6190 + (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl,
6191 + dma_sync_offset, dma_sync_len, DDI_DMA_SYNC_FORDEV);
6192 +
6193 + mpt->m_interrupt_count++;
6194 +
6195 + /*
6196 + * Update the reply index if at least one reply was processed.
6197 + * For more than 8 reply queues on SAS3 controllers we have to do
6198 + * things a little different. See Chapter 20 in the MPI 2.5 spec.
6199 + */
6200 + if (mpt->m_post_reply_qcount > 8) {
6201 + /*
6202 + * The offsets from the base are multiples of 0x10.
6203 + * We are indexing into 32 bit quantities so calculate
6204 + * the index for that.
6205 + */
6206 + i = (reply_q&~0x7) >> 1;
6207 + ddi_put32(mpt->m_datap,
6208 + &mpt->m_reg->SuppReplyPostHostIndex[i],
6209 + rpqp->rpq_index |
6210 + ((reply_q&0x7)<<MPI2_RPHI_MSIX_INDEX_SHIFT));
6211 + (void) ddi_get32(mpt->m_datap,
6212 + &mpt->m_reg->SuppReplyPostHostIndex[i]);
6213 + } else {
6214 + ddi_put32(mpt->m_datap,
6215 + &mpt->m_reg->ReplyPostHostIndex,
6216 + rpqp->rpq_index | (reply_q<<MPI2_RPHI_MSIX_INDEX_SHIFT));
6217 + (void) ddi_get32(mpt->m_datap,
6218 + &mpt->m_reg->ReplyPostHostIndex);
6219 + }
5428 6220
5429 6221 /*
5430 6222 * If no helper threads are created, process the doneq in ISR. If
5431 6223 * helpers are created, use the doneq length as a metric to measure the
5432 6224 * load on the interrupt CPU. If it is long enough, which indicates the
5433 6225 * load is heavy, then we deliver the IO completions to the helpers.
5434 6226 * This measurement has some limitations, although it is simple and
5435 6227 * straightforward and works well for most of the cases at present.
6228 + * To always use the threads set mptsas_doneq_length_threshold_prop
6229 + * to zero in the mpt_sas3.conf file.
6230 + *
6231 + * Check the current reply queue done queue.
5436 6232 */
5437 - if (!mpt->m_doneq_thread_n ||
5438 - (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) {
5439 - mptsas_doneq_empty(mpt);
5440 - } else {
5441 - mptsas_deliver_doneq_thread(mpt);
6233 + if (rpqp->rpq_dlist.dl_len) {
6234 + if (!mpt->m_doneq_thread_n ||
6235 + (rpqp->rpq_dlist.dl_len <= mpt->m_doneq_length_threshold)) {
6236 + mptsas_rpdoneq_empty(rpqp);
6237 + } else {
6238 + mptsas_deliver_doneq_thread(mpt, &rpqp->rpq_dlist);
6239 + }
6240 + }
6241 +
6242 + mutex_exit(&rpqp->rpq_mutex);
6243 +
6244 + /*
6245 + * Check the main done queue. If we find something
6246 + * grab the mutex and check again before processing.
6247 + */
6248 + if (mpt->m_dlist.dl_len) {
6249 + mutex_enter(&mpt->m_mutex);
6250 + if (mpt->m_dlist.dl_len) {
6251 + if (!mpt->m_doneq_thread_n ||
6252 + (mpt->m_dlist.dl_len <=
6253 + mpt->m_doneq_length_threshold)) {
6254 + mptsas_doneq_empty(mpt);
6255 + } else {
6256 + mptsas_deliver_doneq_thread(mpt, &mpt->m_dlist);
6257 + }
6258 + }
6259 + mutex_exit(&mpt->m_mutex);
5442 6260 }
5443 6261
5444 6262 /*
5445 6263 * If there are queued cmd, start them now.
5446 6264 */
5447 6265 if (mpt->m_waitq != NULL) {
5448 - mptsas_restart_waitq(mpt);
6266 + mutex_enter(&mpt->m_mutex);
6267 + if (mpt->m_waitq != NULL && mpt->m_polled_intr == 0) {
6268 + mptsas_restart_waitq(mpt);
6269 + }
6270 + mutex_exit(&mpt->m_mutex);
5449 6271 }
5450 -
5451 - mutex_exit(&mpt->m_mutex);
5452 6272 return (DDI_INTR_CLAIMED);
5453 6273 }
5454 6274
5455 6275 static void
5456 -mptsas_process_intr(mptsas_t *mpt,
6276 +mptsas_process_intr(mptsas_t *mpt, mptsas_reply_pqueue_t *rpqp,
5457 6277 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
5458 6278 {
5459 6279 uint8_t reply_type;
5460 6280
5461 - ASSERT(mutex_owned(&mpt->m_mutex));
6281 + /*
6282 + * Should get here with the reply queue mutex held, but not
6283 + * the main mpt mutex. Want to avoid grabbing that during
6284 + * normal operations if possible.
6285 + */
6286 + ASSERT(mutex_owned(&rpqp->rpq_mutex));
5462 6287
5463 6288 /*
5464 6289 * The reply is valid, process it according to its
5465 6290 * type. Also, set a flag for updated the reply index
5466 6291 * after they've all been processed.
5467 6292 */
5468 6293 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
5469 6294 &reply_desc_union->Default.ReplyFlags);
6295 + NDBG18(("mptsas_process_intr(rpq %d) reply_type 0x%x", rpqp->rpq_num,
6296 + reply_type));
5470 6297 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
5471 - if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
5472 - mptsas_handle_scsi_io_success(mpt, reply_desc_union);
6298 + if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
6299 + reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) {
6300 + mptsas_handle_scsi_io_success(mpt, rpqp, reply_desc_union);
5473 6301 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
6302 + mutex_enter(&mpt->m_mutex);
5474 6303 mptsas_handle_address_reply(mpt, reply_desc_union);
6304 + mutex_exit(&mpt->m_mutex);
5475 6305 } else {
5476 6306 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
5477 6307 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5478 6308 }
5479 -
5480 - /*
5481 - * Clear the reply descriptor for re-use and increment
5482 - * index.
5483 - */
5484 - ddi_put64(mpt->m_acc_post_queue_hdl,
5485 - &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
5486 - 0xFFFFFFFFFFFFFFFF);
5487 - (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5488 - DDI_DMA_SYNC_FORDEV);
5489 6309 }
5490 6310
5491 6311 /*
5492 6312 * handle qfull condition
5493 6313 */
5494 6314 static void
5495 6315 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
5496 6316 {
5497 6317 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5498 6318
6319 + mutex_enter(&ptgt->m_t_mutex);
5499 6320 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
5500 6321 (ptgt->m_qfull_retries == 0)) {
5501 6322 /*
5502 6323 * We have exhausted the retries on QFULL, or,
5503 6324 * the target driver has indicated that it
5504 6325 * wants to handle QFULL itself by setting
5505 6326 * qfull-retries capability to 0. In either case
5506 6327 * we want the target driver's QFULL handling
5507 6328 * to kick in. We do this by having pkt_reason
5508 6329 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
5509 6330 */
5510 6331 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5511 6332 } else {
5512 6333 if (ptgt->m_reset_delay == 0) {
5513 6334 ptgt->m_t_throttle =
5514 6335 max((ptgt->m_t_ncmds - 2), 0);
5515 6336 }
6337 + mutex_exit(&ptgt->m_t_mutex);
5516 6338
5517 - cmd->cmd_pkt_flags |= FLAG_HEAD;
5518 6339 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
5519 - cmd->cmd_flags |= CFLAG_RETRY;
5520 6340
5521 - (void) mptsas_accept_pkt(mpt, cmd);
6341 + mptsas_retry_pkt(mpt, cmd);
5522 6342
6343 + mutex_enter(&ptgt->m_t_mutex);
5523 6344 /*
5524 6345 * when target gives queue full status with no commands
5525 6346 * outstanding (m_t_ncmds == 0), throttle is set to 0
5526 6347 * (HOLD_THROTTLE), and the queue full handling start
5527 6348 * (see psarc/1994/313); if there are commands outstanding,
5528 6349 * throttle is set to (m_t_ncmds - 2)
5529 6350 */
5530 6351 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
5531 6352 /*
5532 6353 * By setting throttle to QFULL_THROTTLE, we
5533 6354 * avoid submitting new commands and in
5534 6355 * mptsas_restart_cmd find out slots which need
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5535 6356 * their throttles to be cleared.
5536 6357 */
5537 6358 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
5538 6359 if (mpt->m_restart_cmd_timeid == 0) {
5539 6360 mpt->m_restart_cmd_timeid =
5540 6361 timeout(mptsas_restart_cmd, mpt,
5541 6362 ptgt->m_qfull_retry_interval);
5542 6363 }
5543 6364 }
5544 6365 }
6366 + mutex_exit(&ptgt->m_t_mutex);
5545 6367 }
5546 6368
5547 6369 mptsas_phymask_t
5548 6370 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
5549 6371 {
5550 6372 mptsas_phymask_t phy_mask = 0;
5551 6373 uint8_t i = 0;
5552 6374
5553 - NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
6375 + NDBG20(("mptsas3%d physport_to_phymask enter", mpt->m_instance));
5554 6376
5555 6377 ASSERT(mutex_owned(&mpt->m_mutex));
5556 6378
5557 6379 /*
5558 6380 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
5559 6381 */
5560 6382 if (physport == 0xFF) {
5561 6383 return (0);
5562 6384 }
5563 6385
5564 6386 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
5565 6387 if (mpt->m_phy_info[i].attached_devhdl &&
5566 6388 (mpt->m_phy_info[i].phy_mask != 0) &&
5567 6389 (mpt->m_phy_info[i].port_num == physport)) {
5568 6390 phy_mask = mpt->m_phy_info[i].phy_mask;
5569 6391 break;
5570 6392 }
5571 6393 }
5572 - NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
6394 + NDBG20(("mptsas3%d physport_to_phymask:physport :%x phymask :%x, ",
5573 6395 mpt->m_instance, physport, phy_mask));
5574 6396 return (phy_mask);
5575 6397 }
5576 6398
5577 6399 /*
5578 6400 * mpt free device handle after device gone, by use of passthrough
5579 6401 */
5580 6402 static int
5581 6403 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
5582 6404 {
5583 6405 Mpi2SasIoUnitControlRequest_t req;
5584 6406 Mpi2SasIoUnitControlReply_t rep;
5585 6407 int ret;
5586 6408
5587 6409 ASSERT(mutex_owned(&mpt->m_mutex));
5588 6410
5589 6411 /*
5590 6412 * Need to compose a SAS IO Unit Control request message
5591 6413 * and call mptsas_do_passthru() function
5592 6414 */
5593 6415 bzero(&req, sizeof (req));
5594 6416 bzero(&rep, sizeof (rep));
5595 6417
5596 6418 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
5597 6419 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
5598 6420 req.DevHandle = LE_16(devhdl);
5599 6421
5600 6422 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
5601 6423 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
5602 6424 if (ret != 0) {
5603 6425 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5604 6426 "Control error %d", ret);
5605 6427 return (DDI_FAILURE);
5606 6428 }
5607 6429
5608 6430 /* do passthrough success, check the ioc status */
5609 6431 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
5610 6432 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5611 6433 "Control IOCStatus %d", LE_16(rep.IOCStatus));
5612 6434 return (DDI_FAILURE);
5613 6435 }
5614 6436
5615 6437 return (DDI_SUCCESS);
|
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33 lines elided |
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5616 6438 }
5617 6439
5618 6440 static void
5619 6441 mptsas_update_phymask(mptsas_t *mpt)
5620 6442 {
5621 6443 mptsas_phymask_t mask = 0, phy_mask;
5622 6444 char *phy_mask_name;
5623 6445 uint8_t current_port;
5624 6446 int i, j;
5625 6447
5626 - NDBG20(("mptsas%d update phymask ", mpt->m_instance));
6448 + NDBG20(("mptsas3%d update phymask ", mpt->m_instance));
5627 6449
5628 6450 ASSERT(mutex_owned(&mpt->m_mutex));
5629 6451
5630 6452 (void) mptsas_get_sas_io_unit_page(mpt);
5631 6453
5632 6454 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5633 6455
5634 6456 for (i = 0; i < mpt->m_num_phys; i++) {
5635 6457 phy_mask = 0x00;
5636 6458
5637 6459 if (mpt->m_phy_info[i].attached_devhdl == 0)
5638 6460 continue;
5639 6461
5640 6462 bzero(phy_mask_name, sizeof (phy_mask_name));
5641 6463
5642 6464 current_port = mpt->m_phy_info[i].port_num;
5643 6465
5644 6466 if ((mask & (1 << i)) != 0)
5645 6467 continue;
5646 6468
5647 6469 for (j = 0; j < mpt->m_num_phys; j++) {
5648 6470 if (mpt->m_phy_info[j].attached_devhdl &&
5649 6471 (mpt->m_phy_info[j].port_num == current_port)) {
5650 6472 phy_mask |= (1 << j);
5651 6473 }
5652 6474 }
5653 6475 mask = mask | phy_mask;
5654 6476
5655 6477 for (j = 0; j < mpt->m_num_phys; j++) {
5656 6478 if ((phy_mask >> j) & 0x01) {
5657 6479 mpt->m_phy_info[j].phy_mask = phy_mask;
5658 6480 }
5659 6481 }
5660 6482
5661 6483 (void) sprintf(phy_mask_name, "%x", phy_mask);
|
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5662 6484
5663 6485 mutex_exit(&mpt->m_mutex);
5664 6486 /*
5665 6487 * register a iport, if the port has already been existed
5666 6488 * SCSA will do nothing and just return.
5667 6489 */
5668 6490 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
5669 6491 mutex_enter(&mpt->m_mutex);
5670 6492 }
5671 6493 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5672 - NDBG20(("mptsas%d update phymask return", mpt->m_instance));
6494 + NDBG20(("mptsas3%d update phymask return", mpt->m_instance));
5673 6495 }
5674 6496
5675 6497 /*
5676 6498 * mptsas_handle_dr is a task handler for DR, the DR action includes:
5677 6499 * 1. Directly attched Device Added/Removed.
5678 6500 * 2. Expander Device Added/Removed.
5679 6501 * 3. Indirectly Attached Device Added/Expander.
5680 6502 * 4. LUNs of a existing device status change.
5681 6503 * 5. RAID volume created/deleted.
5682 6504 * 6. Member of RAID volume is released because of RAID deletion.
5683 6505 * 7. Physical disks are removed because of RAID creation.
5684 6506 */
5685 6507 static void
5686 6508 mptsas_handle_dr(void *args) {
5687 6509 mptsas_topo_change_list_t *topo_node = NULL;
5688 6510 mptsas_topo_change_list_t *save_node = NULL;
5689 6511 mptsas_t *mpt;
5690 6512 dev_info_t *parent = NULL;
5691 6513 mptsas_phymask_t phymask = 0;
5692 - char *phy_mask_name;
6514 + char phy_mask_name[MPTSAS_MAX_PHYS];
5693 6515 uint8_t flags = 0, physport = 0xff;
5694 6516 uint8_t port_update = 0;
5695 6517 uint_t event;
5696 6518
5697 6519 topo_node = (mptsas_topo_change_list_t *)args;
5698 6520
5699 6521 mpt = topo_node->mpt;
5700 6522 event = topo_node->event;
5701 6523 flags = topo_node->flags;
5702 6524
5703 - phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5704 -
5705 - NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
6525 + NDBG20(("mptsas3%d handle_dr enter", mpt->m_instance));
5706 6526
5707 6527 switch (event) {
5708 6528 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
5709 6529 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
5710 6530 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
5711 6531 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
5712 6532 /*
5713 6533 * Direct attached or expander attached device added
5714 6534 * into system or a Phys Disk that is being unhidden.
5715 6535 */
5716 6536 port_update = 1;
5717 6537 }
5718 6538 break;
5719 6539 case MPTSAS_DR_EVENT_RECONFIG_SMP:
5720 6540 /*
5721 6541 * New expander added into system, it must be the head
5722 6542 * of topo_change_list_t
5723 6543 */
5724 6544 port_update = 1;
5725 6545 break;
5726 6546 default:
5727 6547 port_update = 0;
5728 6548 break;
5729 6549 }
5730 6550 /*
5731 6551 * All cases port_update == 1 may cause initiator port form change
5732 6552 */
5733 6553 mutex_enter(&mpt->m_mutex);
5734 6554 if (mpt->m_port_chng && port_update) {
5735 6555 /*
5736 6556 * mpt->m_port_chng flag indicates some PHYs of initiator
|
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21 lines elided |
↑ open up ↑ |
5737 6557 * port have changed to online. So when expander added or
5738 6558 * directly attached device online event come, we force to
5739 6559 * update port information by issueing SAS IO Unit Page and
5740 6560 * update PHYMASKs.
5741 6561 */
5742 6562 (void) mptsas_update_phymask(mpt);
5743 6563 mpt->m_port_chng = 0;
5744 6564
5745 6565 }
5746 6566 mutex_exit(&mpt->m_mutex);
6567 +
5747 6568 while (topo_node) {
5748 6569 phymask = 0;
6570 + flags = topo_node->flags;
6571 + event = topo_node->event;
6572 + if (event == MPTSAS_DR_EVENT_REMOVE_HANDLE) {
6573 + goto handle_topo_change;
6574 + }
6575 + if ((event == MPTSAS_DR_EVENT_RECONFIG_TARGET) &&
6576 + (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6577 + /*
6578 + * There is no any field in IR_CONFIG_CHANGE
6579 + * event indicate physport/phynum, let's get
6580 + * parent after SAS Device Page0 request.
6581 + */
6582 + goto handle_topo_change;
6583 + }
6584 +
5749 6585 if (parent == NULL) {
5750 6586 physport = topo_node->un.physport;
5751 - event = topo_node->event;
5752 - flags = topo_node->flags;
5753 6587 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
5754 6588 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
5755 6589 /*
5756 6590 * For all offline events, phymask is known
5757 6591 */
5758 6592 phymask = topo_node->un.phymask;
5759 6593 goto find_parent;
5760 6594 }
5761 - if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
5762 - goto handle_topo_change;
5763 - }
5764 6595 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
5765 6596 phymask = topo_node->un.phymask;
5766 6597 goto find_parent;
5767 6598 }
5768 6599
5769 - if ((flags ==
5770 - MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
5771 - (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
5772 - /*
5773 - * There is no any field in IR_CONFIG_CHANGE
5774 - * event indicate physport/phynum, let's get
5775 - * parent after SAS Device Page0 request.
5776 - */
5777 - goto handle_topo_change;
5778 - }
5779 -
5780 6600 mutex_enter(&mpt->m_mutex);
5781 6601 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
5782 6602 /*
5783 6603 * If the direct attached device added or a
5784 6604 * phys disk is being unhidden, argument
5785 6605 * physport actually is PHY#, so we have to get
5786 6606 * phymask according PHY#.
5787 6607 */
5788 6608 physport = mpt->m_phy_info[physport].port_num;
5789 6609 }
5790 6610
5791 6611 /*
5792 6612 * Translate physport to phymask so that we can search
5793 6613 * parent dip.
5794 6614 */
5795 - phymask = mptsas_physport_to_phymask(mpt,
5796 - physport);
6615 + phymask = mptsas_physport_to_phymask(mpt, physport);
5797 6616 mutex_exit(&mpt->m_mutex);
5798 6617
5799 6618 find_parent:
5800 6619 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
5801 6620 /*
5802 6621 * For RAID topology change node, write the iport name
5803 6622 * as v0.
5804 6623 */
5805 6624 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5806 6625 (void) sprintf(phy_mask_name, "v0");
5807 6626 } else {
5808 6627 /*
5809 - * phymask can bo 0 if the drive has been
6628 + * phymask can be 0 if the drive has been
5810 6629 * pulled by the time an add event is
5811 6630 * processed. If phymask is 0, just skip this
5812 6631 * event and continue.
5813 6632 */
5814 6633 if (phymask == 0) {
5815 - mutex_enter(&mpt->m_mutex);
5816 6634 save_node = topo_node;
5817 6635 topo_node = topo_node->next;
5818 6636 ASSERT(save_node);
5819 6637 kmem_free(save_node,
5820 6638 sizeof (mptsas_topo_change_list_t));
5821 - mutex_exit(&mpt->m_mutex);
5822 -
5823 6639 parent = NULL;
5824 6640 continue;
5825 6641 }
5826 6642 (void) sprintf(phy_mask_name, "%x", phymask);
5827 6643 }
5828 6644 parent = scsi_hba_iport_find(mpt->m_dip,
5829 6645 phy_mask_name);
5830 6646 if (parent == NULL) {
5831 6647 mptsas_log(mpt, CE_WARN, "Failed to find an "
5832 - "iport, should not happen!");
5833 - goto out;
6648 + "iport for \"%s\", should not happen!",
6649 + phy_mask_name);
6650 + save_node = topo_node;
6651 + topo_node = topo_node->next;
6652 + ASSERT(save_node);
6653 + kmem_free(save_node,
6654 + sizeof (mptsas_topo_change_list_t));
6655 + continue;
5834 6656 }
5835 6657
5836 6658 }
5837 - ASSERT(parent);
5838 -handle_topo_change:
6659 + ASSERT(parent);
6660 +handle_topo_change:
6661 +
6662 + mutex_enter(&mpt->m_mutex);
6663 + /*
6664 + * If HBA is being reset, don't perform operations depending
6665 + * on the IOC. We must free the topo list, however.
6666 + */
6667 + if (!mpt->m_in_reset)
6668 + mptsas_handle_topo_change(topo_node, parent);
6669 + else
6670 + NDBG20(("skipping topo change received during reset"));
6671 + mutex_exit(&mpt->m_mutex);
6672 + save_node = topo_node;
6673 + topo_node = topo_node->next;
6674 + ASSERT(save_node);
6675 + kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
6676 +
6677 + if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6678 + (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
6679 + (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
6680 + /*
6681 + * If direct attached device associated, make sure
6682 + * reset the parent before start the next one. But
6683 + * all devices associated with expander shares the
6684 + * parent. Also, reset parent if this is for RAID.
6685 + */
6686 + parent = NULL;
6687 + }
6688 + }
6689 +}
6690 +
6691 +static void
6692 +mptsas_offline_target(mptsas_t *mpt, mptsas_target_t *ptgt,
6693 + uint8_t topo_flags, dev_info_t *parent)
6694 +{
6695 + uint64_t sas_wwn = 0;
6696 + uint8_t phy;
6697 + char wwn_str[MPTSAS_WWN_STRLEN];
6698 + uint16_t devhdl;
6699 + int circ = 0, circ1 = 0;
6700 + int rval = 0;
6701 +
6702 + sas_wwn = ptgt->m_addr.mta_wwn;
6703 + phy = ptgt->m_phynum;
6704 + devhdl = ptgt->m_devhdl;
6705 +
6706 + if (sas_wwn) {
6707 + (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
6708 + } else {
6709 + (void) sprintf(wwn_str, "p%x", phy);
6710 + }
6711 +
6712 + /*
6713 + * Abort all outstanding command on the device
6714 + */
6715 + rval = mptsas_do_scsi_reset(mpt, devhdl);
6716 + if (rval) {
6717 + NDBG20(("mptsas3%d: mptsas_offline_target: reset target "
6718 + "before offline devhdl:%x, phymask:%x, rval:%x",
6719 + mpt->m_instance, ptgt->m_devhdl,
6720 + ptgt->m_addr.mta_phymask, rval));
6721 + }
6722 +
6723 + mutex_exit(&mpt->m_mutex);
6724 +
6725 + ndi_devi_enter(scsi_vhci_dip, &circ);
6726 + ndi_devi_enter(parent, &circ1);
6727 + rval = mptsas_offline_targetdev(parent, wwn_str);
6728 + ndi_devi_exit(parent, circ1);
6729 + ndi_devi_exit(scsi_vhci_dip, circ);
6730 + NDBG20(("mptsas3%d: mptsas_offline_target %s devhdl:%x, "
6731 + "phymask:%x, rval:%x", mpt->m_instance, wwn_str,
6732 + ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval));
6733 +
6734 + /*
6735 + * Clear parent's props for SMHBA support
6736 + */
6737 + if (topo_flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6738 + if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6739 + SCSI_ADDR_PROP_ATTACHED_PORT, "") !=
6740 + DDI_PROP_SUCCESS) {
6741 + (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6742 + SCSI_ADDR_PROP_ATTACHED_PORT);
6743 + mptsas_log(mpt, CE_WARN, "mptsas attached port "
6744 + "prop update failed");
6745 + }
6746 + if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6747 + MPTSAS_NUM_PHYS, 0) != DDI_PROP_SUCCESS) {
6748 + (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6749 + MPTSAS_NUM_PHYS);
6750 + mptsas_log(mpt, CE_WARN, "mptsas num phys "
6751 + "prop update failed");
6752 + }
6753 + if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6754 + MPTSAS_VIRTUAL_PORT, 1) != DDI_PROP_SUCCESS) {
6755 + (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6756 + MPTSAS_VIRTUAL_PORT);
6757 + mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6758 + "prop update failed");
6759 + }
6760 + }
5839 6761
5840 - mutex_enter(&mpt->m_mutex);
6762 + mutex_enter(&mpt->m_mutex);
6763 + ptgt->m_led_status = 0;
6764 + (void) mptsas_flush_led_status(mpt, ptgt);
6765 + if (rval == DDI_SUCCESS) {
6766 + mutex_destroy(&ptgt->m_t_mutex);
6767 + refhash_remove(mpt->m_targets, ptgt);
6768 + ptgt = NULL;
6769 + } else {
5841 6770 /*
5842 - * If HBA is being reset, don't perform operations depending
5843 - * on the IOC. We must free the topo list, however.
5844 - */
5845 - if (!mpt->m_in_reset)
5846 - mptsas_handle_topo_change(topo_node, parent);
5847 - else
5848 - NDBG20(("skipping topo change received during reset"));
5849 - save_node = topo_node;
5850 - topo_node = topo_node->next;
5851 - ASSERT(save_node);
5852 - kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
5853 - mutex_exit(&mpt->m_mutex);
5854 -
5855 - if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
5856 - (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
5857 - (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
5858 - /*
5859 - * If direct attached device associated, make sure
5860 - * reset the parent before start the next one. But
5861 - * all devices associated with expander shares the
5862 - * parent. Also, reset parent if this is for RAID.
5863 - */
5864 - parent = NULL;
5865 - }
6771 + * clean DR_INTRANSITION flag to allow I/O down to
6772 + * PHCI driver since failover finished.
6773 + * Invalidate the devhdl
6774 + */
6775 + ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6776 + ptgt->m_tgt_unconfigured = 0;
6777 + ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
5866 6778 }
5867 -out:
5868 - kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5869 6779 }
5870 6780
5871 6781 static void
5872 6782 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
5873 6783 dev_info_t *parent)
5874 6784 {
5875 6785 mptsas_target_t *ptgt = NULL;
5876 6786 mptsas_smp_t *psmp = NULL;
5877 6787 mptsas_t *mpt = (void *)topo_node->mpt;
5878 6788 uint16_t devhdl;
5879 6789 uint16_t attached_devhdl;
5880 - uint64_t sas_wwn = 0;
5881 6790 int rval = 0;
5882 6791 uint32_t page_address;
5883 - uint8_t phy, flags;
5884 - char *addr = NULL;
6792 + uint8_t flags;
5885 6793 dev_info_t *lundip;
5886 6794 int circ = 0, circ1 = 0;
5887 6795 char attached_wwnstr[MPTSAS_WWN_STRLEN];
5888 6796
5889 - NDBG20(("mptsas%d handle_topo_change enter", mpt->m_instance));
6797 + NDBG20(("mptsas3%d handle_topo_change enter, devhdl 0x%x,"
6798 + "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl,
6799 + topo_node->event, topo_node->flags));
5890 6800
5891 6801 ASSERT(mutex_owned(&mpt->m_mutex));
5892 6802
5893 6803 switch (topo_node->event) {
5894 6804 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
5895 6805 {
5896 6806 char *phy_mask_name;
5897 6807 mptsas_phymask_t phymask = 0;
5898 6808
5899 6809 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5900 6810 /*
5901 6811 * Get latest RAID info.
5902 6812 */
5903 6813 (void) mptsas_get_raid_info(mpt);
5904 6814 ptgt = refhash_linear_search(mpt->m_targets,
5905 6815 mptsas_target_eval_devhdl, &topo_node->devhdl);
5906 6816 if (ptgt == NULL)
5907 6817 break;
5908 6818 } else {
5909 6819 ptgt = (void *)topo_node->object;
5910 6820 }
5911 6821
5912 6822 if (ptgt == NULL) {
5913 6823 /*
5914 6824 * If a Phys Disk was deleted, RAID info needs to be
5915 6825 * updated to reflect the new topology.
5916 6826 */
5917 6827 (void) mptsas_get_raid_info(mpt);
5918 6828
5919 6829 /*
5920 6830 * Get sas device page 0 by DevHandle to make sure if
5921 6831 * SSP/SATA end device exist.
5922 6832 */
5923 6833 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
5924 6834 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
5925 6835 topo_node->devhdl;
5926 6836
5927 6837 rval = mptsas_get_target_device_info(mpt, page_address,
5928 6838 &devhdl, &ptgt);
5929 6839 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
5930 6840 mptsas_log(mpt, CE_NOTE,
5931 6841 "mptsas_handle_topo_change: target %d is "
5932 6842 "not a SAS/SATA device. \n",
5933 6843 topo_node->devhdl);
5934 6844 } else if (rval == DEV_INFO_FAIL_ALLOC) {
5935 6845 mptsas_log(mpt, CE_NOTE,
5936 6846 "mptsas_handle_topo_change: could not "
5937 6847 "allocate memory. \n");
5938 6848 }
5939 6849 /*
5940 6850 * If rval is DEV_INFO_PHYS_DISK than there is nothing
5941 6851 * else to do, just leave.
5942 6852 */
5943 6853 if (rval != DEV_INFO_SUCCESS) {
5944 6854 return;
5945 6855 }
5946 6856 }
5947 6857
5948 6858 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
5949 6859
5950 6860 mutex_exit(&mpt->m_mutex);
5951 6861 flags = topo_node->flags;
5952 6862
5953 6863 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
5954 6864 phymask = ptgt->m_addr.mta_phymask;
5955 6865 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5956 6866 (void) sprintf(phy_mask_name, "%x", phymask);
5957 6867 parent = scsi_hba_iport_find(mpt->m_dip,
5958 6868 phy_mask_name);
5959 6869 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5960 6870 if (parent == NULL) {
5961 6871 mptsas_log(mpt, CE_WARN, "Failed to find a "
5962 6872 "iport for PD, should not happen!");
5963 6873 mutex_enter(&mpt->m_mutex);
5964 6874 break;
5965 6875 }
5966 6876 }
5967 6877
5968 6878 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5969 6879 ndi_devi_enter(parent, &circ1);
5970 6880 (void) mptsas_config_raid(parent, topo_node->devhdl,
5971 6881 &lundip);
5972 6882 ndi_devi_exit(parent, circ1);
5973 6883 } else {
5974 6884 /*
5975 6885 * hold nexus for bus configure
5976 6886 */
5977 6887 ndi_devi_enter(scsi_vhci_dip, &circ);
5978 6888 ndi_devi_enter(parent, &circ1);
5979 6889 rval = mptsas_config_target(parent, ptgt);
5980 6890 /*
5981 6891 * release nexus for bus configure
5982 6892 */
5983 6893 ndi_devi_exit(parent, circ1);
5984 6894 ndi_devi_exit(scsi_vhci_dip, circ);
5985 6895
5986 6896 /*
5987 6897 * Add parent's props for SMHBA support
5988 6898 */
5989 6899 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
5990 6900 bzero(attached_wwnstr,
5991 6901 sizeof (attached_wwnstr));
5992 6902 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
5993 6903 ptgt->m_addr.mta_wwn);
5994 6904 if (ddi_prop_update_string(DDI_DEV_T_NONE,
5995 6905 parent,
5996 6906 SCSI_ADDR_PROP_ATTACHED_PORT,
5997 6907 attached_wwnstr)
5998 6908 != DDI_PROP_SUCCESS) {
5999 6909 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6000 6910 parent,
6001 6911 SCSI_ADDR_PROP_ATTACHED_PORT);
6002 6912 mptsas_log(mpt, CE_WARN, "Failed to"
6003 6913 "attached-port props");
6004 6914 return;
6005 6915 }
6006 6916 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6007 6917 MPTSAS_NUM_PHYS, 1) !=
6008 6918 DDI_PROP_SUCCESS) {
6009 6919 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6010 6920 parent, MPTSAS_NUM_PHYS);
6011 6921 mptsas_log(mpt, CE_WARN, "Failed to"
6012 6922 " create num-phys props");
6013 6923 return;
6014 6924 }
6015 6925
6016 6926 /*
6017 6927 * Update PHY info for smhba
6018 6928 */
6019 6929 mutex_enter(&mpt->m_mutex);
6020 6930 if (mptsas_smhba_phy_init(mpt)) {
6021 6931 mutex_exit(&mpt->m_mutex);
6022 6932 mptsas_log(mpt, CE_WARN, "mptsas phy"
6023 6933 " update failed");
6024 6934 return;
6025 6935 }
6026 6936 mutex_exit(&mpt->m_mutex);
6027 6937
6028 6938 /*
6029 6939 * topo_node->un.physport is really the PHY#
6030 6940 * for direct attached devices
6031 6941 */
6032 6942 mptsas_smhba_set_one_phy_props(mpt, parent,
6033 6943 topo_node->un.physport, &attached_devhdl);
6034 6944
6035 6945 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6036 6946 MPTSAS_VIRTUAL_PORT, 0) !=
6037 6947 DDI_PROP_SUCCESS) {
6038 6948 (void) ddi_prop_remove(DDI_DEV_T_NONE,
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6039 6949 parent, MPTSAS_VIRTUAL_PORT);
6040 6950 mptsas_log(mpt, CE_WARN,
6041 6951 "mptsas virtual-port"
6042 6952 "port prop update failed");
6043 6953 return;
6044 6954 }
6045 6955 }
6046 6956 }
6047 6957 mutex_enter(&mpt->m_mutex);
6048 6958
6049 - NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
6959 + NDBG20(("mptsas3%d handle_topo_change to online devhdl:%x, "
6050 6960 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
6051 6961 ptgt->m_addr.mta_phymask));
6052 6962 break;
6053 6963 }
6054 6964 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
6055 6965 {
6056 6966 devhdl = topo_node->devhdl;
6057 6967 ptgt = refhash_linear_search(mpt->m_targets,
6058 6968 mptsas_target_eval_devhdl, &devhdl);
6059 6969 if (ptgt == NULL)
6060 6970 break;
6061 6971
6062 - sas_wwn = ptgt->m_addr.mta_wwn;
6063 - phy = ptgt->m_phynum;
6064 -
6065 - addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
6066 -
6067 - if (sas_wwn) {
6068 - (void) sprintf(addr, "w%016"PRIx64, sas_wwn);
6069 - } else {
6070 - (void) sprintf(addr, "p%x", phy);
6071 - }
6072 6972 ASSERT(ptgt->m_devhdl == devhdl);
6073 6973
6074 6974 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
6075 6975 (topo_node->flags ==
6076 6976 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6077 6977 /*
6078 6978 * Get latest RAID info if RAID volume status changes
6079 6979 * or Phys Disk status changes
6080 6980 */
6081 6981 (void) mptsas_get_raid_info(mpt);
6082 6982 }
6083 - /*
6084 - * Abort all outstanding command on the device
6085 - */
6086 - rval = mptsas_do_scsi_reset(mpt, devhdl);
6087 - if (rval) {
6088 - NDBG20(("mptsas%d handle_topo_change to reset target "
6089 - "before offline devhdl:%x, phymask:%x, rval:%x",
6090 - mpt->m_instance, ptgt->m_devhdl,
6091 - ptgt->m_addr.mta_phymask, rval));
6092 - }
6093 -
6094 - mutex_exit(&mpt->m_mutex);
6095 -
6096 - ndi_devi_enter(scsi_vhci_dip, &circ);
6097 - ndi_devi_enter(parent, &circ1);
6098 - rval = mptsas_offline_target(parent, addr);
6099 - ndi_devi_exit(parent, circ1);
6100 - ndi_devi_exit(scsi_vhci_dip, circ);
6101 - NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6102 - "phymask:%x, rval:%x", mpt->m_instance,
6103 - ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval));
6104 -
6105 - kmem_free(addr, SCSI_MAXNAMELEN);
6106 -
6107 - /*
6108 - * Clear parent's props for SMHBA support
6109 - */
6110 - flags = topo_node->flags;
6111 - if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6112 - bzero(attached_wwnstr, sizeof (attached_wwnstr));
6113 - if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6114 - SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6115 - DDI_PROP_SUCCESS) {
6116 - (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6117 - SCSI_ADDR_PROP_ATTACHED_PORT);
6118 - mptsas_log(mpt, CE_WARN, "mptsas attached port "
6119 - "prop update failed");
6120 - break;
6121 - }
6122 - if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6123 - MPTSAS_NUM_PHYS, 0) !=
6124 - DDI_PROP_SUCCESS) {
6125 - (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6126 - MPTSAS_NUM_PHYS);
6127 - mptsas_log(mpt, CE_WARN, "mptsas num phys "
6128 - "prop update failed");
6129 - break;
6130 - }
6131 - if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6132 - MPTSAS_VIRTUAL_PORT, 1) !=
6133 - DDI_PROP_SUCCESS) {
6134 - (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6135 - MPTSAS_VIRTUAL_PORT);
6136 - mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6137 - "prop update failed");
6138 - break;
6139 - }
6140 - }
6141 6983
6142 - mutex_enter(&mpt->m_mutex);
6143 - ptgt->m_led_status = 0;
6144 - (void) mptsas_flush_led_status(mpt, ptgt);
6145 - if (rval == DDI_SUCCESS) {
6146 - refhash_remove(mpt->m_targets, ptgt);
6147 - ptgt = NULL;
6148 - } else {
6149 - /*
6150 - * clean DR_INTRANSITION flag to allow I/O down to
6151 - * PHCI driver since failover finished.
6152 - * Invalidate the devhdl
6153 - */
6154 - ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6155 - ptgt->m_tgt_unconfigured = 0;
6156 - mutex_enter(&mpt->m_tx_waitq_mutex);
6157 - ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6158 - mutex_exit(&mpt->m_tx_waitq_mutex);
6159 - }
6984 + mptsas_offline_target(mpt, ptgt, topo_node->flags, parent);
6160 6985
6161 6986 /*
6162 6987 * Send SAS IO Unit Control to free the dev handle
6163 6988 */
6164 6989 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6165 6990 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6166 6991 rval = mptsas_free_devhdl(mpt, devhdl);
6167 6992
6168 - NDBG20(("mptsas%d handle_topo_change to remove "
6993 + NDBG20(("mptsas3%d handle_topo_change to remove "
6169 6994 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6170 6995 rval));
6171 6996 }
6172 6997
6173 6998 break;
6174 6999 }
6175 - case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
7000 + case MPTSAS_DR_EVENT_REMOVE_HANDLE:
6176 7001 {
6177 7002 devhdl = topo_node->devhdl;
7003 +
6178 7004 /*
6179 - * If this is the remove handle event, do a reset first.
7005 + * Do a reset first.
6180 7006 */
6181 - if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6182 - rval = mptsas_do_scsi_reset(mpt, devhdl);
6183 - if (rval) {
6184 - NDBG20(("mpt%d reset target before remove "
6185 - "devhdl:%x, rval:%x", mpt->m_instance,
6186 - devhdl, rval));
6187 - }
6188 - }
7007 + rval = mptsas_do_scsi_reset(mpt, devhdl);
7008 + NDBG20(("mpt%d reset target before remove "
7009 + "devhdl:%x, rval:%x", mpt->m_instance, devhdl, rval));
6189 7010
6190 7011 /*
6191 7012 * Send SAS IO Unit Control to free the dev handle
6192 7013 */
6193 7014 rval = mptsas_free_devhdl(mpt, devhdl);
6194 - NDBG20(("mptsas%d handle_topo_change to remove "
7015 + NDBG20(("mptsas3%d handle_topo_change to remove "
6195 7016 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6196 7017 rval));
6197 7018 break;
6198 7019 }
6199 7020 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6200 7021 {
6201 7022 mptsas_smp_t smp;
6202 7023 dev_info_t *smpdip;
6203 7024
6204 7025 devhdl = topo_node->devhdl;
6205 7026
6206 7027 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6207 7028 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6208 7029 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6209 7030 if (rval != DDI_SUCCESS) {
6210 7031 mptsas_log(mpt, CE_WARN, "failed to online smp, "
6211 7032 "handle %x", devhdl);
6212 7033 return;
6213 7034 }
6214 7035
6215 7036 psmp = mptsas_smp_alloc(mpt, &smp);
6216 7037 if (psmp == NULL) {
6217 7038 return;
6218 7039 }
6219 7040
6220 7041 mutex_exit(&mpt->m_mutex);
6221 7042 ndi_devi_enter(parent, &circ1);
6222 7043 (void) mptsas_online_smp(parent, psmp, &smpdip);
6223 7044 ndi_devi_exit(parent, circ1);
6224 7045
6225 7046 mutex_enter(&mpt->m_mutex);
6226 7047 break;
6227 7048 }
6228 7049 case MPTSAS_DR_EVENT_OFFLINE_SMP:
6229 7050 {
6230 7051 devhdl = topo_node->devhdl;
6231 7052 uint32_t dev_info;
6232 7053
6233 7054 psmp = refhash_linear_search(mpt->m_smp_targets,
6234 7055 mptsas_smp_eval_devhdl, &devhdl);
6235 7056 if (psmp == NULL)
6236 7057 break;
6237 7058 /*
6238 7059 * The mptsas_smp_t data is released only if the dip is offlined
6239 7060 * successfully.
6240 7061 */
6241 7062 mutex_exit(&mpt->m_mutex);
6242 7063
6243 7064 ndi_devi_enter(parent, &circ1);
6244 7065 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6245 7066 ndi_devi_exit(parent, circ1);
6246 7067
6247 7068 dev_info = psmp->m_deviceinfo;
6248 7069 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6249 7070 DEVINFO_DIRECT_ATTACHED) {
6250 7071 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6251 7072 MPTSAS_VIRTUAL_PORT, 1) !=
6252 7073 DDI_PROP_SUCCESS) {
6253 7074 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6254 7075 MPTSAS_VIRTUAL_PORT);
6255 7076 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6256 7077 "prop update failed");
6257 7078 return;
6258 7079 }
6259 7080 /*
6260 7081 * Check whether the smp connected to the iport,
6261 7082 */
6262 7083 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6263 7084 MPTSAS_NUM_PHYS, 0) !=
6264 7085 DDI_PROP_SUCCESS) {
6265 7086 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6266 7087 MPTSAS_NUM_PHYS);
6267 7088 mptsas_log(mpt, CE_WARN, "mptsas num phys"
6268 7089 "prop update failed");
6269 7090 return;
6270 7091 }
6271 7092 /*
6272 7093 * Clear parent's attached-port props
6273 7094 */
6274 7095 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6275 7096 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6276 7097 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
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6277 7098 DDI_PROP_SUCCESS) {
6278 7099 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6279 7100 SCSI_ADDR_PROP_ATTACHED_PORT);
6280 7101 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6281 7102 "prop update failed");
6282 7103 return;
6283 7104 }
6284 7105 }
6285 7106
6286 7107 mutex_enter(&mpt->m_mutex);
6287 - NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
7108 + NDBG20(("mptsas3%d handle_topo_change to remove devhdl:%x, "
6288 7109 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6289 7110 if (rval == DDI_SUCCESS) {
6290 7111 refhash_remove(mpt->m_smp_targets, psmp);
6291 7112 } else {
6292 7113 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6293 7114 }
6294 7115
6295 7116 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6296 7117
6297 7118 break;
6298 7119 }
6299 7120 default:
6300 7121 return;
6301 7122 }
6302 7123 }
6303 7124
6304 7125 /*
6305 7126 * Record the event if its type is enabled in mpt instance by ioctl.
6306 7127 */
6307 7128 static void
6308 7129 mptsas_record_event(void *args)
6309 7130 {
6310 7131 m_replyh_arg_t *replyh_arg;
6311 7132 pMpi2EventNotificationReply_t eventreply;
6312 7133 uint32_t event, rfm;
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6313 7134 mptsas_t *mpt;
6314 7135 int i, j;
6315 7136 uint16_t event_data_len;
6316 7137 boolean_t sendAEN = FALSE;
6317 7138
6318 7139 replyh_arg = (m_replyh_arg_t *)args;
6319 7140 rfm = replyh_arg->rfm;
6320 7141 mpt = replyh_arg->mpt;
6321 7142
6322 7143 eventreply = (pMpi2EventNotificationReply_t)
6323 - (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
7144 + (mpt->m_reply_frame + (rfm -
7145 + (mpt->m_reply_frame_dma_addr&0xfffffffful)));
6324 7146 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6325 7147
6326 7148
6327 7149 /*
6328 7150 * Generate a system event to let anyone who cares know that a
6329 7151 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
6330 7152 * event mask is set to.
6331 7153 */
6332 7154 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6333 7155 sendAEN = TRUE;
6334 7156 }
6335 7157
6336 7158 /*
6337 7159 * Record the event only if it is not masked. Determine which dword
6338 7160 * and bit of event mask to test.
6339 7161 */
6340 7162 i = (uint8_t)(event / 32);
6341 7163 j = (uint8_t)(event % 32);
6342 7164 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6343 7165 i = mpt->m_event_index;
6344 7166 mpt->m_events[i].Type = event;
6345 7167 mpt->m_events[i].Number = ++mpt->m_event_number;
6346 7168 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
6347 7169 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
6348 7170 &eventreply->EventDataLength);
6349 7171
6350 7172 if (event_data_len > 0) {
6351 7173 /*
6352 7174 * Limit data to size in m_event entry
6353 7175 */
6354 7176 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
6355 7177 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
6356 7178 }
6357 7179 for (j = 0; j < event_data_len; j++) {
6358 7180 mpt->m_events[i].Data[j] =
6359 7181 ddi_get32(mpt->m_acc_reply_frame_hdl,
6360 7182 &(eventreply->EventData[j]));
6361 7183 }
6362 7184
6363 7185 /*
6364 7186 * check for index wrap-around
6365 7187 */
6366 7188 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
6367 7189 i = 0;
6368 7190 }
6369 7191 mpt->m_event_index = (uint8_t)i;
6370 7192
6371 7193 /*
6372 7194 * Set flag to send the event.
6373 7195 */
6374 7196 sendAEN = TRUE;
6375 7197 }
6376 7198 }
6377 7199
6378 7200 /*
6379 7201 * Generate a system event if flag is set to let anyone who cares know
6380 7202 * that an event has occurred.
6381 7203 */
6382 7204 if (sendAEN) {
6383 7205 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
6384 7206 "SAS", NULL, NULL, DDI_NOSLEEP);
6385 7207 }
6386 7208 }
6387 7209
6388 7210 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
6389 7211 /*
6390 7212 * handle sync events from ioc in interrupt
6391 7213 * return value:
6392 7214 * DDI_SUCCESS: The event is handled by this func
6393 7215 * DDI_FAILURE: Event is not handled
6394 7216 */
6395 7217 static int
6396 7218 mptsas_handle_event_sync(void *args)
6397 7219 {
6398 7220 m_replyh_arg_t *replyh_arg;
6399 7221 pMpi2EventNotificationReply_t eventreply;
6400 7222 uint32_t event, rfm;
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6401 7223 mptsas_t *mpt;
6402 7224 uint_t iocstatus;
6403 7225
6404 7226 replyh_arg = (m_replyh_arg_t *)args;
6405 7227 rfm = replyh_arg->rfm;
6406 7228 mpt = replyh_arg->mpt;
6407 7229
6408 7230 ASSERT(mutex_owned(&mpt->m_mutex));
6409 7231
6410 7232 eventreply = (pMpi2EventNotificationReply_t)
6411 - (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
7233 + (mpt->m_reply_frame + (rfm -
7234 + (mpt->m_reply_frame_dma_addr&0xfffffffful)));
6412 7235 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6413 7236
6414 7237 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
6415 7238 &eventreply->IOCStatus)) {
6416 7239 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
6417 7240 mptsas_log(mpt, CE_WARN,
6418 - "!mptsas_handle_event_sync: IOCStatus=0x%x, "
6419 - "IOCLogInfo=0x%x", iocstatus,
7241 + "!mptsas_handle_event_sync: event 0x%x, "
7242 + "IOCStatus=0x%x, "
7243 + "IOCLogInfo=0x%x", event, iocstatus,
6420 7244 ddi_get32(mpt->m_acc_reply_frame_hdl,
6421 7245 &eventreply->IOCLogInfo));
6422 7246 } else {
6423 7247 mptsas_log(mpt, CE_WARN,
6424 - "mptsas_handle_event_sync: IOCStatus=0x%x, "
6425 - "IOCLogInfo=0x%x", iocstatus,
7248 + "mptsas_handle_event_sync: event 0x%x, "
7249 + "IOCStatus=0x%x, "
7250 + "(IOCLogInfo=0x%x)", event, iocstatus,
6426 7251 ddi_get32(mpt->m_acc_reply_frame_hdl,
6427 7252 &eventreply->IOCLogInfo));
6428 7253 }
6429 7254 }
6430 7255
6431 7256 /*
6432 7257 * figure out what kind of event we got and handle accordingly
6433 7258 */
6434 7259 switch (event) {
6435 7260 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
6436 7261 {
6437 7262 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
6438 7263 uint8_t num_entries, expstatus, phy;
6439 7264 uint8_t phystatus, physport, state, i;
6440 7265 uint8_t start_phy_num, link_rate;
6441 7266 uint16_t dev_handle, reason_code;
6442 7267 uint16_t enc_handle, expd_handle;
6443 7268 char string[80], curr[80], prev[80];
6444 7269 mptsas_topo_change_list_t *topo_head = NULL;
6445 7270 mptsas_topo_change_list_t *topo_tail = NULL;
6446 7271 mptsas_topo_change_list_t *topo_node = NULL;
6447 7272 mptsas_target_t *ptgt;
6448 7273 mptsas_smp_t *psmp;
6449 7274 uint8_t flags = 0, exp_flag;
6450 7275 smhba_info_t *pSmhba = NULL;
6451 7276
6452 7277 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
6453 7278
6454 7279 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
6455 7280 eventreply->EventData;
6456 7281
6457 7282 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6458 7283 &sas_topo_change_list->EnclosureHandle);
6459 7284 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6460 7285 &sas_topo_change_list->ExpanderDevHandle);
6461 7286 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6462 7287 &sas_topo_change_list->NumEntries);
6463 7288 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
6464 7289 &sas_topo_change_list->StartPhyNum);
6465 7290 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6466 7291 &sas_topo_change_list->ExpStatus);
6467 7292 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
6468 7293 &sas_topo_change_list->PhysicalPort);
6469 7294
6470 7295 string[0] = 0;
6471 7296 if (expd_handle) {
6472 7297 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
6473 7298 switch (expstatus) {
6474 7299 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
6475 7300 (void) sprintf(string, " added");
6476 7301 /*
6477 7302 * New expander device added
6478 7303 */
6479 7304 mpt->m_port_chng = 1;
6480 7305 topo_node = kmem_zalloc(
6481 7306 sizeof (mptsas_topo_change_list_t),
6482 7307 KM_SLEEP);
6483 7308 topo_node->mpt = mpt;
6484 7309 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
6485 7310 topo_node->un.physport = physport;
6486 7311 topo_node->devhdl = expd_handle;
6487 7312 topo_node->flags = flags;
6488 7313 topo_node->object = NULL;
6489 7314 if (topo_head == NULL) {
6490 7315 topo_head = topo_tail = topo_node;
6491 7316 } else {
6492 7317 topo_tail->next = topo_node;
6493 7318 topo_tail = topo_node;
6494 7319 }
6495 7320 break;
6496 7321 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
6497 7322 (void) sprintf(string, " not responding, "
6498 7323 "removed");
6499 7324 psmp = refhash_linear_search(mpt->m_smp_targets,
6500 7325 mptsas_smp_eval_devhdl, &expd_handle);
6501 7326 if (psmp == NULL)
6502 7327 break;
6503 7328
6504 7329 topo_node = kmem_zalloc(
6505 7330 sizeof (mptsas_topo_change_list_t),
6506 7331 KM_SLEEP);
6507 7332 topo_node->mpt = mpt;
6508 7333 topo_node->un.phymask =
6509 7334 psmp->m_addr.mta_phymask;
6510 7335 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
6511 7336 topo_node->devhdl = expd_handle;
6512 7337 topo_node->flags = flags;
6513 7338 topo_node->object = NULL;
6514 7339 if (topo_head == NULL) {
6515 7340 topo_head = topo_tail = topo_node;
6516 7341 } else {
6517 7342 topo_tail->next = topo_node;
6518 7343 topo_tail = topo_node;
6519 7344 }
6520 7345 break;
6521 7346 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
6522 7347 break;
6523 7348 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
6524 7349 (void) sprintf(string, " not responding, "
6525 7350 "delaying removal");
6526 7351 break;
6527 7352 default:
6528 7353 break;
6529 7354 }
6530 7355 } else {
6531 7356 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
6532 7357 }
6533 7358
6534 7359 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
6535 7360 enc_handle, expd_handle, string));
6536 7361 for (i = 0; i < num_entries; i++) {
6537 7362 phy = i + start_phy_num;
6538 7363 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6539 7364 &sas_topo_change_list->PHY[i].PhyStatus);
6540 7365 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6541 7366 &sas_topo_change_list->PHY[i].AttachedDevHandle);
6542 7367 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
6543 7368 /*
6544 7369 * Filter out processing of Phy Vacant Status unless
6545 7370 * the reason code is "Not Responding". Process all
6546 7371 * other combinations of Phy Status and Reason Codes.
6547 7372 */
6548 7373 if ((phystatus &
6549 7374 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
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6550 7375 (reason_code !=
6551 7376 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
6552 7377 continue;
6553 7378 }
6554 7379 curr[0] = 0;
6555 7380 prev[0] = 0;
6556 7381 string[0] = 0;
6557 7382 switch (reason_code) {
6558 7383 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
6559 7384 {
6560 - NDBG20(("mptsas%d phy %d physical_port %d "
7385 + NDBG20(("mptsas3%d phy %d physical_port %d "
6561 7386 "dev_handle %d added", mpt->m_instance, phy,
6562 7387 physport, dev_handle));
6563 7388 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6564 7389 &sas_topo_change_list->PHY[i].LinkRate);
6565 7390 state = (link_rate &
6566 7391 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6567 7392 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6568 7393 switch (state) {
6569 7394 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6570 7395 (void) sprintf(curr, "is disabled");
6571 7396 break;
6572 7397 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6573 7398 (void) sprintf(curr, "is offline, "
6574 7399 "failed speed negotiation");
6575 7400 break;
6576 7401 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6577 7402 (void) sprintf(curr, "SATA OOB "
6578 7403 "complete");
6579 7404 break;
6580 7405 case SMP_RESET_IN_PROGRESS:
6581 7406 (void) sprintf(curr, "SMP reset in "
6582 7407 "progress");
6583 7408 break;
6584 7409 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6585 7410 (void) sprintf(curr, "is online at "
|
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15 lines elided |
↑ open up ↑ |
6586 7411 "1.5 Gbps");
6587 7412 break;
6588 7413 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6589 7414 (void) sprintf(curr, "is online at 3.0 "
6590 7415 "Gbps");
6591 7416 break;
6592 7417 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6593 7418 (void) sprintf(curr, "is online at 6.0 "
6594 7419 "Gbps");
6595 7420 break;
7421 + case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7422 + (void) sprintf(curr,
7423 + "is online at 12.0 Gbps");
7424 + break;
6596 7425 default:
6597 7426 (void) sprintf(curr, "state is "
6598 7427 "unknown");
6599 7428 break;
6600 7429 }
6601 7430 /*
6602 7431 * New target device added into the system.
6603 7432 * Set association flag according to if an
6604 7433 * expander is used or not.
6605 7434 */
6606 7435 exp_flag =
6607 7436 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6608 7437 if (flags ==
6609 7438 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6610 7439 flags = exp_flag;
6611 7440 }
6612 7441 topo_node = kmem_zalloc(
6613 7442 sizeof (mptsas_topo_change_list_t),
6614 7443 KM_SLEEP);
6615 7444 topo_node->mpt = mpt;
6616 7445 topo_node->event =
6617 7446 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6618 7447 if (expd_handle == 0) {
6619 7448 /*
6620 7449 * Per MPI 2, if expander dev handle
6621 7450 * is 0, it's a directly attached
6622 7451 * device. So driver use PHY to decide
6623 7452 * which iport is associated
6624 7453 */
6625 7454 physport = phy;
6626 7455 mpt->m_port_chng = 1;
6627 7456 }
6628 7457 topo_node->un.physport = physport;
6629 7458 topo_node->devhdl = dev_handle;
6630 7459 topo_node->flags = flags;
6631 7460 topo_node->object = NULL;
|
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6632 7461 if (topo_head == NULL) {
6633 7462 topo_head = topo_tail = topo_node;
6634 7463 } else {
6635 7464 topo_tail->next = topo_node;
6636 7465 topo_tail = topo_node;
6637 7466 }
6638 7467 break;
6639 7468 }
6640 7469 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
6641 7470 {
6642 - NDBG20(("mptsas%d phy %d physical_port %d "
7471 + NDBG20(("mptsas3%d phy %d physical_port %d "
6643 7472 "dev_handle %d removed", mpt->m_instance,
6644 7473 phy, physport, dev_handle));
6645 7474 /*
6646 7475 * Set association flag according to if an
6647 7476 * expander is used or not.
6648 7477 */
6649 7478 exp_flag =
6650 7479 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6651 7480 if (flags ==
6652 7481 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6653 7482 flags = exp_flag;
6654 7483 }
6655 7484 /*
6656 7485 * Target device is removed from the system
6657 7486 * Before the device is really offline from
6658 7487 * from system.
6659 7488 */
6660 7489 ptgt = refhash_linear_search(mpt->m_targets,
6661 7490 mptsas_target_eval_devhdl, &dev_handle);
6662 7491 /*
|
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10 lines elided |
↑ open up ↑ |
6663 7492 * If ptgt is NULL here, it means that the
6664 7493 * DevHandle is not in the hash table. This is
6665 7494 * reasonable sometimes. For example, if a
6666 7495 * disk was pulled, then added, then pulled
6667 7496 * again, the disk will not have been put into
6668 7497 * the hash table because the add event will
6669 7498 * have an invalid phymask. BUT, this does not
6670 7499 * mean that the DevHandle is invalid. The
6671 7500 * controller will still have a valid DevHandle
6672 7501 * that must be removed. To do this, use the
6673 - * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
7502 + * MPTSAS_DR_EVENT_REMOVE_HANDLE event.
6674 7503 */
6675 7504 if (ptgt == NULL) {
6676 7505 topo_node = kmem_zalloc(
6677 7506 sizeof (mptsas_topo_change_list_t),
6678 7507 KM_SLEEP);
6679 7508 topo_node->mpt = mpt;
6680 7509 topo_node->un.phymask = 0;
6681 7510 topo_node->event =
6682 - MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
7511 + MPTSAS_DR_EVENT_REMOVE_HANDLE;
6683 7512 topo_node->devhdl = dev_handle;
6684 7513 topo_node->flags = flags;
6685 7514 topo_node->object = NULL;
6686 7515 if (topo_head == NULL) {
6687 7516 topo_head = topo_tail =
6688 7517 topo_node;
6689 7518 } else {
6690 7519 topo_tail->next = topo_node;
6691 7520 topo_tail = topo_node;
6692 7521 }
6693 7522 break;
6694 7523 }
6695 7524
6696 7525 /*
6697 7526 * Update DR flag immediately avoid I/O failure
6698 - * before failover finish. Pay attention to the
6699 - * mutex protect, we need grab m_tx_waitq_mutex
6700 - * during set m_dr_flag because we won't add
6701 - * the following command into waitq, instead,
7527 + * before failover finish. We won't add
7528 + * any following commands into waitq, instead,
6702 7529 * we need return TRAN_BUSY in the tran_start
6703 7530 * context.
6704 7531 */
6705 - mutex_enter(&mpt->m_tx_waitq_mutex);
6706 7532 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6707 - mutex_exit(&mpt->m_tx_waitq_mutex);
6708 7533
6709 7534 topo_node = kmem_zalloc(
6710 7535 sizeof (mptsas_topo_change_list_t),
6711 7536 KM_SLEEP);
6712 7537 topo_node->mpt = mpt;
6713 7538 topo_node->un.phymask =
6714 7539 ptgt->m_addr.mta_phymask;
6715 7540 topo_node->event =
6716 7541 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6717 7542 topo_node->devhdl = dev_handle;
6718 7543 topo_node->flags = flags;
6719 7544 topo_node->object = NULL;
6720 7545 if (topo_head == NULL) {
6721 7546 topo_head = topo_tail = topo_node;
6722 7547 } else {
6723 7548 topo_tail->next = topo_node;
6724 7549 topo_tail = topo_node;
6725 7550 }
6726 7551 break;
6727 7552 }
6728 7553 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
6729 7554 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6730 7555 &sas_topo_change_list->PHY[i].LinkRate);
6731 7556 state = (link_rate &
6732 7557 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6733 7558 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6734 7559 pSmhba = &mpt->m_phy_info[i].smhba_info;
6735 7560 pSmhba->negotiated_link_rate = state;
6736 7561 switch (state) {
6737 7562 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6738 7563 (void) sprintf(curr, "is disabled");
6739 7564 mptsas_smhba_log_sysevent(mpt,
6740 7565 ESC_SAS_PHY_EVENT,
6741 7566 SAS_PHY_REMOVE,
6742 7567 &mpt->m_phy_info[i].smhba_info);
6743 7568 mpt->m_phy_info[i].smhba_info.
6744 7569 negotiated_link_rate
6745 7570 = 0x1;
6746 7571 break;
6747 7572 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6748 7573 (void) sprintf(curr, "is offline, "
6749 7574 "failed speed negotiation");
6750 7575 mptsas_smhba_log_sysevent(mpt,
6751 7576 ESC_SAS_PHY_EVENT,
6752 7577 SAS_PHY_OFFLINE,
6753 7578 &mpt->m_phy_info[i].smhba_info);
6754 7579 break;
6755 7580 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6756 7581 (void) sprintf(curr, "SATA OOB "
6757 7582 "complete");
6758 7583 break;
6759 7584 case SMP_RESET_IN_PROGRESS:
6760 7585 (void) sprintf(curr, "SMP reset in "
6761 7586 "progress");
6762 7587 break;
6763 7588 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6764 7589 (void) sprintf(curr, "is online at "
6765 7590 "1.5 Gbps");
6766 7591 if ((expd_handle == 0) &&
6767 7592 (enc_handle == 1)) {
6768 7593 mpt->m_port_chng = 1;
6769 7594 }
6770 7595 mptsas_smhba_log_sysevent(mpt,
6771 7596 ESC_SAS_PHY_EVENT,
6772 7597 SAS_PHY_ONLINE,
6773 7598 &mpt->m_phy_info[i].smhba_info);
6774 7599 break;
6775 7600 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6776 7601 (void) sprintf(curr, "is online at 3.0 "
6777 7602 "Gbps");
6778 7603 if ((expd_handle == 0) &&
6779 7604 (enc_handle == 1)) {
6780 7605 mpt->m_port_chng = 1;
6781 7606 }
6782 7607 mptsas_smhba_log_sysevent(mpt,
6783 7608 ESC_SAS_PHY_EVENT,
6784 7609 SAS_PHY_ONLINE,
6785 7610 &mpt->m_phy_info[i].smhba_info);
6786 7611 break;
6787 7612 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6788 7613 (void) sprintf(curr, "is online at "
|
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71 lines elided |
↑ open up ↑ |
6789 7614 "6.0 Gbps");
6790 7615 if ((expd_handle == 0) &&
6791 7616 (enc_handle == 1)) {
6792 7617 mpt->m_port_chng = 1;
6793 7618 }
6794 7619 mptsas_smhba_log_sysevent(mpt,
6795 7620 ESC_SAS_PHY_EVENT,
6796 7621 SAS_PHY_ONLINE,
6797 7622 &mpt->m_phy_info[i].smhba_info);
6798 7623 break;
7624 + case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7625 + (void) sprintf(curr, "is online at "
7626 + "12.0 Gbps");
7627 + if ((expd_handle == 0) &&
7628 + (enc_handle == 1)) {
7629 + mpt->m_port_chng = 1;
7630 + }
7631 + mptsas_smhba_log_sysevent(mpt,
7632 + ESC_SAS_PHY_EVENT,
7633 + SAS_PHY_ONLINE,
7634 + &mpt->m_phy_info[i].smhba_info);
7635 + break;
6799 7636 default:
6800 7637 (void) sprintf(curr, "state is "
6801 7638 "unknown");
6802 7639 break;
6803 7640 }
6804 7641
6805 7642 state = (link_rate &
6806 7643 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
6807 7644 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
6808 7645 switch (state) {
6809 7646 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6810 7647 (void) sprintf(prev, ", was disabled");
6811 7648 break;
6812 7649 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6813 7650 (void) sprintf(prev, ", was offline, "
6814 7651 "failed speed negotiation");
6815 7652 break;
6816 7653 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6817 7654 (void) sprintf(prev, ", was SATA OOB "
6818 7655 "complete");
6819 7656 break;
6820 7657 case SMP_RESET_IN_PROGRESS:
6821 7658 (void) sprintf(prev, ", was SMP reset "
6822 7659 "in progress");
6823 7660 break;
6824 7661 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6825 7662 (void) sprintf(prev, ", was online at "
|
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↑ open up ↑ |
6826 7663 "1.5 Gbps");
6827 7664 break;
6828 7665 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6829 7666 (void) sprintf(prev, ", was online at "
6830 7667 "3.0 Gbps");
6831 7668 break;
6832 7669 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6833 7670 (void) sprintf(prev, ", was online at "
6834 7671 "6.0 Gbps");
6835 7672 break;
7673 + case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7674 + (void) sprintf(prev, ", was online at "
7675 + "12.0 Gbps");
7676 + break;
6836 7677 default:
6837 7678 break;
6838 7679 }
6839 7680 (void) sprintf(&string[strlen(string)], "link "
6840 7681 "changed, ");
6841 7682 break;
6842 7683 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
6843 7684 continue;
6844 7685 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
6845 7686 (void) sprintf(&string[strlen(string)],
6846 7687 "target not responding, delaying "
6847 7688 "removal");
6848 7689 break;
6849 7690 }
6850 - NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
7691 + NDBG20(("mptsas3%d phy %d DevHandle %x, %s%s%s\n",
6851 7692 mpt->m_instance, phy, dev_handle, string, curr,
6852 7693 prev));
6853 7694 }
6854 7695 if (topo_head != NULL) {
6855 7696 /*
6856 7697 * Launch DR taskq to handle topology change
6857 7698 */
6858 7699 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
6859 7700 mptsas_handle_dr, (void *)topo_head,
6860 7701 DDI_NOSLEEP)) != DDI_SUCCESS) {
7702 + while (topo_head != NULL) {
7703 + topo_node = topo_head;
7704 + topo_head = topo_head->next;
7705 + kmem_free(topo_node,
7706 + sizeof (mptsas_topo_change_list_t));
7707 + }
6861 7708 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
6862 7709 "for handle SAS DR event failed. \n");
6863 7710 }
6864 7711 }
6865 7712 break;
6866 7713 }
6867 7714 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
6868 7715 {
6869 7716 Mpi2EventDataIrConfigChangeList_t *irChangeList;
6870 7717 mptsas_topo_change_list_t *topo_head = NULL;
6871 7718 mptsas_topo_change_list_t *topo_tail = NULL;
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6872 7719 mptsas_topo_change_list_t *topo_node = NULL;
6873 7720 mptsas_target_t *ptgt;
6874 7721 uint8_t num_entries, i, reason;
6875 7722 uint16_t volhandle, diskhandle;
6876 7723
6877 7724 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
6878 7725 eventreply->EventData;
6879 7726 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6880 7727 &irChangeList->NumElements);
6881 7728
6882 - NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
7729 + NDBG20(("mptsas3%d IR_CONFIGURATION_CHANGE_LIST event received",
6883 7730 mpt->m_instance));
6884 7731
6885 7732 for (i = 0; i < num_entries; i++) {
6886 7733 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
6887 7734 &irChangeList->ConfigElement[i].ReasonCode);
6888 7735 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6889 7736 &irChangeList->ConfigElement[i].VolDevHandle);
6890 7737 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6891 7738 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
6892 7739
6893 7740 switch (reason) {
6894 7741 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
6895 7742 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
6896 7743 {
6897 7744 NDBG20(("mptsas %d volume added\n",
6898 7745 mpt->m_instance));
6899 7746
6900 7747 topo_node = kmem_zalloc(
6901 7748 sizeof (mptsas_topo_change_list_t),
6902 7749 KM_SLEEP);
6903 7750
6904 7751 topo_node->mpt = mpt;
6905 7752 topo_node->event =
6906 7753 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6907 7754 topo_node->un.physport = 0xff;
6908 7755 topo_node->devhdl = volhandle;
6909 7756 topo_node->flags =
6910 7757 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
6911 7758 topo_node->object = NULL;
6912 7759 if (topo_head == NULL) {
6913 7760 topo_head = topo_tail = topo_node;
6914 7761 } else {
6915 7762 topo_tail->next = topo_node;
6916 7763 topo_tail = topo_node;
6917 7764 }
6918 7765 break;
6919 7766 }
6920 7767 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
6921 7768 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
6922 7769 {
6923 7770 NDBG20(("mptsas %d volume deleted\n",
6924 7771 mpt->m_instance));
6925 7772 ptgt = refhash_linear_search(mpt->m_targets,
6926 7773 mptsas_target_eval_devhdl, &volhandle);
6927 7774 if (ptgt == NULL)
|
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↑ open up ↑ |
6928 7775 break;
6929 7776
6930 7777 /*
6931 7778 * Clear any flags related to volume
6932 7779 */
6933 7780 (void) mptsas_delete_volume(mpt, volhandle);
6934 7781
6935 7782 /*
6936 7783 * Update DR flag immediately avoid I/O failure
6937 7784 */
6938 - mutex_enter(&mpt->m_tx_waitq_mutex);
6939 7785 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6940 - mutex_exit(&mpt->m_tx_waitq_mutex);
6941 7786
6942 7787 topo_node = kmem_zalloc(
6943 7788 sizeof (mptsas_topo_change_list_t),
6944 7789 KM_SLEEP);
6945 7790 topo_node->mpt = mpt;
6946 7791 topo_node->un.phymask =
6947 7792 ptgt->m_addr.mta_phymask;
6948 7793 topo_node->event =
6949 7794 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6950 7795 topo_node->devhdl = volhandle;
6951 7796 topo_node->flags =
6952 7797 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
6953 7798 topo_node->object = (void *)ptgt;
6954 7799 if (topo_head == NULL) {
6955 7800 topo_head = topo_tail = topo_node;
6956 7801 } else {
6957 7802 topo_tail->next = topo_node;
6958 7803 topo_tail = topo_node;
6959 7804 }
6960 7805 break;
6961 7806 }
6962 7807 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
|
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12 lines elided |
↑ open up ↑ |
6963 7808 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
6964 7809 {
6965 7810 ptgt = refhash_linear_search(mpt->m_targets,
6966 7811 mptsas_target_eval_devhdl, &diskhandle);
6967 7812 if (ptgt == NULL)
6968 7813 break;
6969 7814
6970 7815 /*
6971 7816 * Update DR flag immediately avoid I/O failure
6972 7817 */
6973 - mutex_enter(&mpt->m_tx_waitq_mutex);
6974 7818 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6975 - mutex_exit(&mpt->m_tx_waitq_mutex);
6976 7819
6977 7820 topo_node = kmem_zalloc(
6978 7821 sizeof (mptsas_topo_change_list_t),
6979 7822 KM_SLEEP);
6980 7823 topo_node->mpt = mpt;
6981 7824 topo_node->un.phymask =
6982 7825 ptgt->m_addr.mta_phymask;
6983 7826 topo_node->event =
6984 7827 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6985 7828 topo_node->devhdl = diskhandle;
6986 7829 topo_node->flags =
6987 7830 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
6988 7831 topo_node->object = (void *)ptgt;
6989 7832 if (topo_head == NULL) {
6990 7833 topo_head = topo_tail = topo_node;
6991 7834 } else {
6992 7835 topo_tail->next = topo_node;
6993 7836 topo_tail = topo_node;
6994 7837 }
6995 7838 break;
6996 7839 }
6997 7840 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
6998 7841 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
6999 7842 {
7000 7843 /*
7001 7844 * The physical drive is released by a IR
7002 7845 * volume. But we cannot get the the physport
7003 7846 * or phynum from the event data, so we only
7004 7847 * can get the physport/phynum after SAS
7005 7848 * Device Page0 request for the devhdl.
7006 7849 */
7007 7850 topo_node = kmem_zalloc(
7008 7851 sizeof (mptsas_topo_change_list_t),
7009 7852 KM_SLEEP);
7010 7853 topo_node->mpt = mpt;
7011 7854 topo_node->un.phymask = 0;
7012 7855 topo_node->event =
7013 7856 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7014 7857 topo_node->devhdl = diskhandle;
7015 7858 topo_node->flags =
7016 7859 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7017 7860 topo_node->object = NULL;
7018 7861 mpt->m_port_chng = 1;
7019 7862 if (topo_head == NULL) {
7020 7863 topo_head = topo_tail = topo_node;
7021 7864 } else {
7022 7865 topo_tail->next = topo_node;
7023 7866 topo_tail = topo_node;
7024 7867 }
7025 7868 break;
7026 7869 }
7027 7870 default:
7028 7871 break;
|
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43 lines elided |
↑ open up ↑ |
7029 7872 }
7030 7873 }
7031 7874
7032 7875 if (topo_head != NULL) {
7033 7876 /*
7034 7877 * Launch DR taskq to handle topology change
7035 7878 */
7036 7879 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7037 7880 mptsas_handle_dr, (void *)topo_head,
7038 7881 DDI_NOSLEEP)) != DDI_SUCCESS) {
7882 + while (topo_head != NULL) {
7883 + topo_node = topo_head;
7884 + topo_head = topo_head->next;
7885 + kmem_free(topo_node,
7886 + sizeof (mptsas_topo_change_list_t));
7887 + }
7039 7888 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7040 7889 "for handle SAS DR event failed. \n");
7041 7890 }
7042 7891 }
7043 7892 break;
7044 7893 }
7045 7894 default:
7046 7895 return (DDI_FAILURE);
7047 7896 }
7048 7897
7049 7898 return (DDI_SUCCESS);
7050 7899 }
7051 7900
7052 7901 /*
7053 7902 * handle events from ioc
7054 7903 */
7055 7904 static void
7056 7905 mptsas_handle_event(void *args)
7057 7906 {
7058 7907 m_replyh_arg_t *replyh_arg;
7059 7908 pMpi2EventNotificationReply_t eventreply;
7060 7909 uint32_t event, iocloginfo, rfm;
7061 7910 uint32_t status;
7062 7911 uint8_t port;
7063 7912 mptsas_t *mpt;
7064 7913 uint_t iocstatus;
7065 7914
7066 7915 replyh_arg = (m_replyh_arg_t *)args;
7067 7916 rfm = replyh_arg->rfm;
7068 7917 mpt = replyh_arg->mpt;
7069 7918
7070 7919 mutex_enter(&mpt->m_mutex);
|
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22 lines elided |
↑ open up ↑ |
7071 7920 /*
7072 7921 * If HBA is being reset, drop incoming event.
7073 7922 */
7074 7923 if (mpt->m_in_reset) {
7075 7924 NDBG20(("dropping event received prior to reset"));
7076 7925 mutex_exit(&mpt->m_mutex);
7077 7926 return;
7078 7927 }
7079 7928
7080 7929 eventreply = (pMpi2EventNotificationReply_t)
7081 - (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
7930 + (mpt->m_reply_frame + (rfm -
7931 + (mpt->m_reply_frame_dma_addr&0xfffffffful)));
7082 7932 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7083 7933
7084 7934 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7085 7935 &eventreply->IOCStatus)) {
7086 7936 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7087 7937 mptsas_log(mpt, CE_WARN,
7088 7938 "!mptsas_handle_event: IOCStatus=0x%x, "
7089 7939 "IOCLogInfo=0x%x", iocstatus,
7090 7940 ddi_get32(mpt->m_acc_reply_frame_hdl,
7091 7941 &eventreply->IOCLogInfo));
7092 7942 } else {
7093 7943 mptsas_log(mpt, CE_WARN,
7094 7944 "mptsas_handle_event: IOCStatus=0x%x, "
7095 7945 "IOCLogInfo=0x%x", iocstatus,
7096 7946 ddi_get32(mpt->m_acc_reply_frame_hdl,
7097 7947 &eventreply->IOCLogInfo));
7098 7948 }
7099 7949 }
7100 7950
7101 7951 /*
7102 7952 * figure out what kind of event we got and handle accordingly
7103 7953 */
|
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12 lines elided |
↑ open up ↑ |
7104 7954 switch (event) {
7105 7955 case MPI2_EVENT_LOG_ENTRY_ADDED:
7106 7956 break;
7107 7957 case MPI2_EVENT_LOG_DATA:
7108 7958 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7109 7959 &eventreply->IOCLogInfo);
7110 7960 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7111 7961 iocloginfo));
7112 7962 break;
7113 7963 case MPI2_EVENT_STATE_CHANGE:
7114 - NDBG20(("mptsas%d state change.", mpt->m_instance));
7964 + NDBG20(("mptsas3%d state change.", mpt->m_instance));
7115 7965 break;
7116 7966 case MPI2_EVENT_HARD_RESET_RECEIVED:
7117 - NDBG20(("mptsas%d event change.", mpt->m_instance));
7967 + NDBG20(("mptsas3%d event change.", mpt->m_instance));
7118 7968 break;
7119 7969 case MPI2_EVENT_SAS_DISCOVERY:
7120 7970 {
7121 7971 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7122 7972 char string[80];
7123 7973 uint8_t rc;
7124 7974
7125 7975 sasdiscovery =
7126 7976 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7127 7977
7128 7978 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7129 7979 &sasdiscovery->ReasonCode);
7130 7980 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7131 7981 &sasdiscovery->PhysicalPort);
7132 7982 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7133 7983 &sasdiscovery->DiscoveryStatus);
7134 7984
7135 7985 string[0] = 0;
7136 7986 switch (rc) {
7137 7987 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7138 7988 (void) sprintf(string, "STARTING");
7139 7989 break;
7140 7990 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7141 7991 (void) sprintf(string, "COMPLETED");
7142 7992 break;
7143 7993 default:
|
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16 lines elided |
↑ open up ↑ |
7144 7994 (void) sprintf(string, "UNKNOWN");
7145 7995 break;
7146 7996 }
7147 7997
7148 7998 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7149 7999 port, status));
7150 8000
7151 8001 break;
7152 8002 }
7153 8003 case MPI2_EVENT_EVENT_CHANGE:
7154 - NDBG20(("mptsas%d event change.", mpt->m_instance));
8004 + NDBG20(("mptsas3%d event change.", mpt->m_instance));
7155 8005 break;
7156 8006 case MPI2_EVENT_TASK_SET_FULL:
7157 8007 {
7158 8008 pMpi2EventDataTaskSetFull_t taskfull;
7159 8009
7160 8010 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7161 8011
7162 - NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
8012 + NDBG20(("TASK_SET_FULL received for mptsas3%d, depth %d\n",
7163 8013 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7164 8014 &taskfull->CurrentDepth)));
7165 8015 break;
7166 8016 }
7167 8017 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7168 8018 {
7169 8019 /*
7170 8020 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7171 8021 * in mptsas_handle_event_sync() of interrupt context
7172 8022 */
7173 8023 break;
7174 8024 }
7175 8025 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7176 8026 {
7177 8027 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
7178 8028 uint8_t rc;
7179 8029 char string[80];
7180 8030
7181 8031 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7182 8032 eventreply->EventData;
7183 8033
7184 8034 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7185 8035 &encstatus->ReasonCode);
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↑ open up ↑ |
7186 8036 switch (rc) {
7187 8037 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7188 8038 (void) sprintf(string, "added");
7189 8039 break;
7190 8040 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7191 8041 (void) sprintf(string, ", not responding");
7192 8042 break;
7193 8043 default:
7194 8044 break;
7195 8045 }
7196 - NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure %x%s\n",
7197 - mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
8046 + NDBG20(("mptsas3%d ENCLOSURE STATUS CHANGE for enclosure "
8047 + "%x%s\n", mpt->m_instance,
8048 + ddi_get16(mpt->m_acc_reply_frame_hdl,
7198 8049 &encstatus->EnclosureHandle), string));
7199 8050 break;
7200 8051 }
7201 8052
7202 8053 /*
7203 8054 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7204 8055 * mptsas_handle_event_sync,in here just send ack message.
7205 8056 */
7206 8057 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7207 8058 {
7208 8059 pMpi2EventDataSasDeviceStatusChange_t statuschange;
7209 8060 uint8_t rc;
7210 8061 uint16_t devhdl;
7211 8062 uint64_t wwn = 0;
7212 8063 uint32_t wwn_lo, wwn_hi;
7213 8064
7214 8065 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7215 8066 eventreply->EventData;
7216 8067 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7217 8068 &statuschange->ReasonCode);
7218 8069 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7219 8070 (uint32_t *)(void *)&statuschange->SASAddress);
7220 8071 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7221 8072 (uint32_t *)(void *)&statuschange->SASAddress + 1);
7222 8073 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7223 8074 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7224 8075 &statuschange->DevHandle);
7225 8076
7226 8077 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7227 8078 wwn));
7228 8079
7229 8080 switch (rc) {
7230 8081 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7231 8082 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7232 8083 ddi_get8(mpt->m_acc_reply_frame_hdl,
7233 8084 &statuschange->ASC),
7234 8085 ddi_get8(mpt->m_acc_reply_frame_hdl,
7235 8086 &statuschange->ASCQ)));
7236 8087 break;
7237 8088
7238 8089 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7239 8090 NDBG20(("Device not supported"));
7240 8091 break;
7241 8092
7242 8093 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7243 8094 NDBG20(("IOC internally generated the Target Reset "
7244 8095 "for devhdl:%x", devhdl));
7245 8096 break;
7246 8097
7247 8098 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7248 8099 NDBG20(("IOC's internally generated Target Reset "
7249 8100 "completed for devhdl:%x", devhdl));
7250 8101 break;
7251 8102
7252 8103 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7253 8104 NDBG20(("IOC internally generated Abort Task"));
7254 8105 break;
7255 8106
7256 8107 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7257 8108 NDBG20(("IOC's internally generated Abort Task "
7258 8109 "completed"));
7259 8110 break;
7260 8111
7261 8112 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7262 8113 NDBG20(("IOC internally generated Abort Task Set"));
7263 8114 break;
7264 8115
7265 8116 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7266 8117 NDBG20(("IOC internally generated Clear Task Set"));
7267 8118 break;
7268 8119
7269 8120 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7270 8121 NDBG20(("IOC internally generated Query Task"));
7271 8122 break;
7272 8123
7273 8124 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7274 8125 NDBG20(("Device sent an Asynchronous Notification"));
7275 8126 break;
7276 8127
7277 8128 default:
7278 8129 break;
7279 8130 }
7280 8131 break;
7281 8132 }
7282 8133 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7283 8134 {
7284 8135 /*
7285 8136 * IR TOPOLOGY CHANGE LIST Event has already been handled
7286 8137 * in mpt_handle_event_sync() of interrupt context
7287 8138 */
7288 8139 break;
7289 8140 }
7290 8141 case MPI2_EVENT_IR_OPERATION_STATUS:
7291 8142 {
7292 8143 Mpi2EventDataIrOperationStatus_t *irOpStatus;
7293 8144 char reason_str[80];
7294 8145 uint8_t rc, percent;
7295 8146 uint16_t handle;
7296 8147
7297 8148 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
7298 8149 eventreply->EventData;
7299 8150 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7300 8151 &irOpStatus->RAIDOperation);
7301 8152 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
7302 8153 &irOpStatus->PercentComplete);
7303 8154 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7304 8155 &irOpStatus->VolDevHandle);
7305 8156
7306 8157 switch (rc) {
7307 8158 case MPI2_EVENT_IR_RAIDOP_RESYNC:
7308 8159 (void) sprintf(reason_str, "resync");
7309 8160 break;
7310 8161 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
7311 8162 (void) sprintf(reason_str, "online capacity "
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7312 8163 "expansion");
7313 8164 break;
7314 8165 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
7315 8166 (void) sprintf(reason_str, "consistency check");
7316 8167 break;
7317 8168 default:
7318 8169 (void) sprintf(reason_str, "unknown reason %x",
7319 8170 rc);
7320 8171 }
7321 8172
7322 - NDBG20(("mptsas%d raid operational status: (%s)"
8173 + NDBG20(("mptsas3%d raid operational status: (%s)"
7323 8174 "\thandle(0x%04x), percent complete(%d)\n",
7324 8175 mpt->m_instance, reason_str, handle, percent));
7325 8176 break;
7326 8177 }
7327 8178 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
7328 8179 {
7329 8180 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
7330 8181 uint8_t phy_num;
7331 8182 uint8_t primitive;
7332 8183
7333 8184 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
7334 8185 eventreply->EventData;
7335 8186
7336 8187 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7337 8188 &sas_broadcast->PhyNum);
7338 8189 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
7339 8190 &sas_broadcast->Primitive);
7340 8191
7341 8192 switch (primitive) {
7342 8193 case MPI2_EVENT_PRIMITIVE_CHANGE:
7343 8194 mptsas_smhba_log_sysevent(mpt,
7344 8195 ESC_SAS_HBA_PORT_BROADCAST,
7345 8196 SAS_PORT_BROADCAST_CHANGE,
7346 8197 &mpt->m_phy_info[phy_num].smhba_info);
7347 8198 break;
7348 8199 case MPI2_EVENT_PRIMITIVE_SES:
7349 8200 mptsas_smhba_log_sysevent(mpt,
7350 8201 ESC_SAS_HBA_PORT_BROADCAST,
7351 8202 SAS_PORT_BROADCAST_SES,
7352 8203 &mpt->m_phy_info[phy_num].smhba_info);
7353 8204 break;
7354 8205 case MPI2_EVENT_PRIMITIVE_EXPANDER:
7355 8206 mptsas_smhba_log_sysevent(mpt,
7356 8207 ESC_SAS_HBA_PORT_BROADCAST,
7357 8208 SAS_PORT_BROADCAST_D01_4,
7358 8209 &mpt->m_phy_info[phy_num].smhba_info);
7359 8210 break;
7360 8211 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
7361 8212 mptsas_smhba_log_sysevent(mpt,
7362 8213 ESC_SAS_HBA_PORT_BROADCAST,
7363 8214 SAS_PORT_BROADCAST_D04_7,
7364 8215 &mpt->m_phy_info[phy_num].smhba_info);
7365 8216 break;
7366 8217 case MPI2_EVENT_PRIMITIVE_RESERVED3:
7367 8218 mptsas_smhba_log_sysevent(mpt,
7368 8219 ESC_SAS_HBA_PORT_BROADCAST,
7369 8220 SAS_PORT_BROADCAST_D16_7,
7370 8221 &mpt->m_phy_info[phy_num].smhba_info);
7371 8222 break;
7372 8223 case MPI2_EVENT_PRIMITIVE_RESERVED4:
7373 8224 mptsas_smhba_log_sysevent(mpt,
7374 8225 ESC_SAS_HBA_PORT_BROADCAST,
7375 8226 SAS_PORT_BROADCAST_D29_7,
7376 8227 &mpt->m_phy_info[phy_num].smhba_info);
7377 8228 break;
7378 8229 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
7379 8230 mptsas_smhba_log_sysevent(mpt,
7380 8231 ESC_SAS_HBA_PORT_BROADCAST,
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7381 8232 SAS_PORT_BROADCAST_D24_0,
7382 8233 &mpt->m_phy_info[phy_num].smhba_info);
7383 8234 break;
7384 8235 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
7385 8236 mptsas_smhba_log_sysevent(mpt,
7386 8237 ESC_SAS_HBA_PORT_BROADCAST,
7387 8238 SAS_PORT_BROADCAST_D27_4,
7388 8239 &mpt->m_phy_info[phy_num].smhba_info);
7389 8240 break;
7390 8241 default:
7391 - NDBG20(("mptsas%d: unknown BROADCAST PRIMITIVE"
8242 + NDBG16(("mptsas3%d: unknown BROADCAST PRIMITIVE"
7392 8243 " %x received",
7393 8244 mpt->m_instance, primitive));
7394 8245 break;
7395 8246 }
7396 - NDBG20(("mptsas%d sas broadcast primitive: "
8247 + NDBG16(("mptsas3%d sas broadcast primitive: "
7397 8248 "\tprimitive(0x%04x), phy(%d) complete\n",
7398 8249 mpt->m_instance, primitive, phy_num));
7399 8250 break;
7400 8251 }
7401 8252 case MPI2_EVENT_IR_VOLUME:
7402 8253 {
7403 8254 Mpi2EventDataIrVolume_t *irVolume;
7404 8255 uint16_t devhandle;
7405 8256 uint32_t state;
7406 8257 int config, vol;
7407 8258 uint8_t found = FALSE;
7408 8259
7409 8260 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
7410 8261 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7411 8262 &irVolume->NewValue);
7412 8263 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7413 8264 &irVolume->VolDevHandle);
7414 8265
7415 8266 NDBG20(("EVENT_IR_VOLUME event is received"));
7416 8267
7417 8268 /*
7418 8269 * Get latest RAID info and then find the DevHandle for this
7419 8270 * event in the configuration. If the DevHandle is not found
7420 8271 * just exit the event.
7421 8272 */
7422 8273 (void) mptsas_get_raid_info(mpt);
7423 8274 for (config = 0; (config < mpt->m_num_raid_configs) &&
7424 8275 (!found); config++) {
7425 8276 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
7426 8277 if (mpt->m_raidconfig[config].m_raidvol[vol].
7427 8278 m_raidhandle == devhandle) {
7428 8279 found = TRUE;
7429 8280 break;
7430 8281 }
7431 8282 }
7432 8283 }
7433 8284 if (!found) {
7434 8285 break;
7435 8286 }
7436 8287
7437 8288 switch (irVolume->ReasonCode) {
7438 8289 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
7439 8290 {
7440 8291 uint32_t i;
7441 8292 mpt->m_raidconfig[config].m_raidvol[vol].m_settings =
7442 8293 state;
7443 8294
7444 8295 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
7445 8296 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
7446 8297 ", auto-config of hot-swap drives is %s"
7447 8298 ", write caching is %s"
7448 8299 ", hot-spare pool mask is %02x\n",
7449 8300 vol, state &
7450 8301 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
7451 8302 ? "disabled" : "enabled",
7452 8303 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
7453 8304 ? "controlled by member disks" :
7454 8305 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
7455 8306 ? "disabled" :
7456 8307 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
7457 8308 ? "enabled" :
7458 8309 "incorrectly set",
7459 8310 (state >> 16) & 0xff);
7460 8311 break;
7461 8312 }
7462 8313 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
7463 8314 {
7464 8315 mpt->m_raidconfig[config].m_raidvol[vol].m_state =
7465 8316 (uint8_t)state;
7466 8317
7467 8318 mptsas_log(mpt, CE_NOTE,
7468 8319 "Volume %d is now %s\n", vol,
7469 8320 state == MPI2_RAID_VOL_STATE_OPTIMAL
7470 8321 ? "optimal" :
7471 8322 state == MPI2_RAID_VOL_STATE_DEGRADED
7472 8323 ? "degraded" :
7473 8324 state == MPI2_RAID_VOL_STATE_ONLINE
7474 8325 ? "online" :
7475 8326 state == MPI2_RAID_VOL_STATE_INITIALIZING
7476 8327 ? "initializing" :
7477 8328 state == MPI2_RAID_VOL_STATE_FAILED
7478 8329 ? "failed" :
7479 8330 state == MPI2_RAID_VOL_STATE_MISSING
7480 8331 ? "missing" :
7481 8332 "state unknown");
7482 8333 break;
7483 8334 }
7484 8335 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
7485 8336 {
7486 8337 mpt->m_raidconfig[config].m_raidvol[vol].
7487 8338 m_statusflags = state;
7488 8339
7489 8340 mptsas_log(mpt, CE_NOTE,
7490 8341 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
7491 8342 vol,
7492 8343 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
7493 8344 ? ", enabled" : ", disabled",
7494 8345 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
7495 8346 ? ", quiesced" : "",
7496 8347 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
7497 8348 ? ", inactive" : ", active",
7498 8349 state &
7499 8350 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
7500 8351 ? ", bad block table is full" : "",
7501 8352 state &
7502 8353 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
7503 8354 ? ", resync in progress" : "",
7504 8355 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
7505 8356 ? ", background initialization in progress" : "",
7506 8357 state &
7507 8358 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
7508 8359 ? ", capacity expansion in progress" : "",
7509 8360 state &
7510 8361 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
7511 8362 ? ", consistency check in progress" : "",
7512 8363 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
7513 8364 ? ", data scrub in progress" : "");
7514 8365 break;
7515 8366 }
7516 8367 default:
7517 8368 break;
7518 8369 }
7519 8370 break;
7520 8371 }
7521 8372 case MPI2_EVENT_IR_PHYSICAL_DISK:
7522 8373 {
7523 8374 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
7524 8375 uint16_t devhandle, enchandle, slot;
7525 8376 uint32_t status, state;
7526 8377 uint8_t physdisknum, reason;
7527 8378
7528 8379 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
7529 8380 eventreply->EventData;
7530 8381 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
7531 8382 &irPhysDisk->PhysDiskNum);
7532 8383 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7533 8384 &irPhysDisk->PhysDiskDevHandle);
7534 8385 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7535 8386 &irPhysDisk->EnclosureHandle);
7536 8387 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
7537 8388 &irPhysDisk->Slot);
7538 8389 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7539 8390 &irPhysDisk->NewValue);
7540 8391 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7541 8392 &irPhysDisk->ReasonCode);
7542 8393
7543 8394 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
7544 8395
7545 8396 switch (reason) {
7546 8397 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
7547 8398 mptsas_log(mpt, CE_NOTE,
7548 8399 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7549 8400 "for enclosure with handle 0x%x is now in hot "
7550 8401 "spare pool %d",
7551 8402 physdisknum, devhandle, slot, enchandle,
7552 8403 (state >> 16) & 0xff);
7553 8404 break;
7554 8405
7555 8406 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
7556 8407 status = state;
7557 8408 mptsas_log(mpt, CE_NOTE,
7558 8409 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7559 8410 "for enclosure with handle 0x%x is now "
7560 8411 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
7561 8412 enchandle,
7562 8413 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
7563 8414 ? ", inactive" : ", active",
7564 8415 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
7565 8416 ? ", out of sync" : "",
7566 8417 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
7567 8418 ? ", quiesced" : "",
7568 8419 status &
7569 8420 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
7570 8421 ? ", write cache enabled" : "",
7571 8422 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
7572 8423 ? ", capacity expansion target" : "");
7573 8424 break;
7574 8425
7575 8426 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
7576 8427 mptsas_log(mpt, CE_NOTE,
7577 8428 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7578 8429 "for enclosure with handle 0x%x is now %s\n",
7579 8430 physdisknum, devhandle, slot, enchandle,
7580 8431 state == MPI2_RAID_PD_STATE_OPTIMAL
7581 8432 ? "optimal" :
7582 8433 state == MPI2_RAID_PD_STATE_REBUILDING
7583 8434 ? "rebuilding" :
7584 8435 state == MPI2_RAID_PD_STATE_DEGRADED
7585 8436 ? "degraded" :
7586 8437 state == MPI2_RAID_PD_STATE_HOT_SPARE
7587 8438 ? "a hot spare" :
7588 8439 state == MPI2_RAID_PD_STATE_ONLINE
7589 8440 ? "online" :
7590 8441 state == MPI2_RAID_PD_STATE_OFFLINE
7591 8442 ? "offline" :
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7592 8443 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
7593 8444 ? "not compatible" :
7594 8445 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
7595 8446 ? "not configured" :
7596 8447 "state unknown");
7597 8448 break;
7598 8449 }
7599 8450 break;
7600 8451 }
7601 8452 default:
7602 - NDBG20(("mptsas%d: unknown event %x received",
8453 + NDBG20(("mptsas3%d: unknown event %x received",
7603 8454 mpt->m_instance, event));
7604 8455 break;
7605 8456 }
7606 8457
7607 8458 /*
7608 8459 * Return the reply frame to the free queue.
7609 8460 */
7610 8461 ddi_put32(mpt->m_acc_free_queue_hdl,
7611 8462 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
7612 8463 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
7613 8464 DDI_DMA_SYNC_FORDEV);
7614 8465 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
7615 8466 mpt->m_free_index = 0;
7616 8467 }
7617 8468 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
7618 8469 mpt->m_free_index);
7619 8470 mutex_exit(&mpt->m_mutex);
7620 8471 }
7621 8472
7622 8473 /*
7623 8474 * invoked from timeout() to restart qfull cmds with throttle == 0
7624 8475 */
7625 8476 static void
7626 8477 mptsas_restart_cmd(void *arg)
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7627 8478 {
7628 8479 mptsas_t *mpt = arg;
7629 8480 mptsas_target_t *ptgt = NULL;
7630 8481
7631 8482 mutex_enter(&mpt->m_mutex);
7632 8483
7633 8484 mpt->m_restart_cmd_timeid = 0;
7634 8485
7635 8486 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
7636 8487 ptgt = refhash_next(mpt->m_targets, ptgt)) {
8488 + mutex_enter(&ptgt->m_t_mutex);
7637 8489 if (ptgt->m_reset_delay == 0) {
7638 8490 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
7639 8491 mptsas_set_throttle(mpt, ptgt,
7640 8492 MAX_THROTTLE);
7641 8493 }
7642 8494 }
8495 + mutex_exit(&ptgt->m_t_mutex);
7643 8496 }
7644 8497 mptsas_restart_hba(mpt);
7645 8498 mutex_exit(&mpt->m_mutex);
7646 8499 }
7647 8500
8501 +/*
8502 + * Assume some checks have been done prior to calling this
8503 + * function so we don't need to consider taking the m_mutex.
8504 + */
8505 +static void
8506 +mptsas_remove_cmd_nomtx(mptsas_t *mpt, mptsas_cmd_t *cmd)
8507 +{
8508 + int slot;
8509 + mptsas_slots_t *slots = mpt->m_active;
8510 + mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8511 +
8512 + ASSERT(cmd != NULL);
8513 + ASSERT(cmd->cmd_queued == FALSE);
8514 + ASSERT((cmd->cmd_flags & CFLAG_CMDIOC) == 0);
8515 +
8516 + slot = cmd->cmd_slot;
8517 +
8518 + /*
8519 + * remove the cmd.
8520 + */
8521 + if (cmd == slots->m_slot[slot]) {
8522 + NDBG31(("mptsas_remove_cmd_nomtx: removing cmd=0x%p, flags "
8523 + "0x%x", (void *)cmd, cmd->cmd_flags));
8524 + slots->m_slot[slot] = NULL;
8525 + ASSERT(mpt->m_ncmds != 0);
8526 + atomic_dec_32(&mpt->m_ncmds);
8527 + ASSERT(mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds != 0);
8528 + atomic_dec_32(
8529 + &mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds);
8530 +
8531 + /*
8532 + * Decrement per target ncmds, we know this is not an
8533 + * IOC cmd and it therefore has a target associated with it.
8534 + */
8535 + mutex_enter(&ptgt->m_t_mutex);
8536 + ASSERT(ptgt->m_t_ncmds != 0);
8537 + ptgt->m_t_ncmds--;
8538 +
8539 + /*
8540 + * reset throttle if we just ran an untagged command
8541 + * to a tagged target
8542 + */
8543 + if ((ptgt->m_t_ncmds == 0) &&
8544 + ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
8545 + mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8546 + }
8547 +
8548 + /*
8549 + * Remove this command from the active queue.
8550 + */
8551 + if (cmd->cmd_active_expiration != 0) {
8552 + TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd,
8553 + cmd_active_link);
8554 + cmd->cmd_active_expiration = 0;
8555 + }
8556 + mutex_exit(&ptgt->m_t_mutex);
8557 + }
8558 +
8559 + ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
8560 +}
8561 +
7648 8562 void
7649 8563 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7650 8564 {
7651 8565 int slot;
7652 8566 mptsas_slots_t *slots = mpt->m_active;
7653 - int t;
7654 8567 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7655 8568
7656 8569 ASSERT(cmd != NULL);
7657 8570 ASSERT(cmd->cmd_queued == FALSE);
7658 8571
7659 8572 /*
7660 8573 * Task Management cmds are removed in their own routines. Also,
7661 8574 * we don't want to modify timeout based on TM cmds.
7662 8575 */
7663 8576 if (cmd->cmd_flags & CFLAG_TM_CMD) {
7664 8577 return;
7665 8578 }
7666 8579
7667 - t = Tgt(cmd);
7668 8580 slot = cmd->cmd_slot;
7669 8581
7670 8582 /*
7671 8583 * remove the cmd.
7672 8584 */
7673 8585 if (cmd == slots->m_slot[slot]) {
7674 - NDBG31(("mptsas_remove_cmd: removing cmd=0x%p", (void *)cmd));
8586 + NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags 0x%x",
8587 + (void *)cmd, cmd->cmd_flags));
7675 8588 slots->m_slot[slot] = NULL;
7676 - mpt->m_ncmds--;
8589 + ASSERT(mpt->m_ncmds != 0);
8590 + atomic_dec_32(&mpt->m_ncmds);
8591 + ASSERT(mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds != 0);
8592 + atomic_dec_32(
8593 + &mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds);
7677 8594
7678 8595 /*
7679 8596 * only decrement per target ncmds if command
7680 8597 * has a target associated with it.
7681 8598 */
7682 8599 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
8600 + mutex_enter(&ptgt->m_t_mutex);
8601 + ASSERT(ptgt->m_t_ncmds != 0);
7683 8602 ptgt->m_t_ncmds--;
8603 +
7684 8604 /*
7685 8605 * reset throttle if we just ran an untagged command
7686 8606 * to a tagged target
7687 8607 */
7688 8608 if ((ptgt->m_t_ncmds == 0) &&
7689 8609 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
7690 8610 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
7691 8611 }
8612 +
8613 + /*
8614 + * Remove this command from the active queue.
8615 + */
8616 + if (cmd->cmd_active_expiration != 0) {
8617 + TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd,
8618 + cmd_active_link);
8619 + cmd->cmd_active_expiration = 0;
8620 + }
8621 + mutex_exit(&ptgt->m_t_mutex);
7692 8622 }
7693 8623
7694 8624 }
7695 8625
7696 8626 /*
7697 8627 * This is all we need to do for ioc commands.
7698 8628 */
7699 8629 if (cmd->cmd_flags & CFLAG_CMDIOC) {
7700 8630 mptsas_return_to_pool(mpt, cmd);
7701 8631 return;
7702 8632 }
7703 8633
7704 - /*
7705 - * Figure out what to set tag Q timeout for...
7706 - *
7707 - * Optimize: If we have duplicate's of same timeout
7708 - * we're using, then we'll use it again until we run
7709 - * out of duplicates. This should be the normal case
7710 - * for block and raw I/O.
7711 - * If no duplicates, we have to scan through tag que and
7712 - * find the longest timeout value and use it. This is
7713 - * going to take a while...
7714 - * Add 1 to m_n_normal to account for TM request.
7715 - */
7716 - if (cmd->cmd_pkt->pkt_time == ptgt->m_timebase) {
7717 - if (--(ptgt->m_dups) == 0) {
7718 - if (ptgt->m_t_ncmds) {
7719 - mptsas_cmd_t *ssp;
7720 - uint_t n = 0;
7721 - ushort_t nslots = (slots->m_n_normal + 1);
7722 - ushort_t i;
7723 - /*
7724 - * This crude check assumes we don't do
7725 - * this too often which seems reasonable
7726 - * for block and raw I/O.
7727 - */
7728 - for (i = 0; i < nslots; i++) {
7729 - ssp = slots->m_slot[i];
7730 - if (ssp && (Tgt(ssp) == t) &&
7731 - (ssp->cmd_pkt->pkt_time > n)) {
7732 - n = ssp->cmd_pkt->pkt_time;
7733 - ptgt->m_dups = 1;
7734 - } else if (ssp && (Tgt(ssp) == t) &&
7735 - (ssp->cmd_pkt->pkt_time == n)) {
7736 - ptgt->m_dups++;
7737 - }
7738 - }
7739 - ptgt->m_timebase = n;
7740 - } else {
7741 - ptgt->m_dups = 0;
7742 - ptgt->m_timebase = 0;
7743 - }
7744 - }
7745 - }
7746 - ptgt->m_timeout = ptgt->m_timebase;
7747 -
7748 8634 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
7749 8635 }
7750 8636
7751 8637 /*
7752 8638 * accept all cmds on the tx_waitq if any and then
7753 8639 * start a fresh request from the top of the device queue.
7754 8640 *
7755 8641 * since there are always cmds queued on the tx_waitq, and rare cmds on
7756 8642 * the instance waitq, so this function should not be invoked in the ISR,
7757 8643 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the
7758 8644 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU.
7759 8645 */
7760 8646 static void
7761 8647 mptsas_restart_hba(mptsas_t *mpt)
7762 8648 {
7763 8649 ASSERT(mutex_owned(&mpt->m_mutex));
7764 8650
7765 - mutex_enter(&mpt->m_tx_waitq_mutex);
7766 - if (mpt->m_tx_waitq) {
7767 - mptsas_accept_tx_waitq(mpt);
7768 - }
7769 - mutex_exit(&mpt->m_tx_waitq_mutex);
8651 + mptsas_accept_tx_waitqs(mpt);
7770 8652 mptsas_restart_waitq(mpt);
7771 8653 }
7772 8654
7773 8655 /*
7774 8656 * start a fresh request from the top of the device queue
7775 8657 */
7776 8658 static void
7777 8659 mptsas_restart_waitq(mptsas_t *mpt)
7778 8660 {
7779 8661 mptsas_cmd_t *cmd, *next_cmd;
7780 8662 mptsas_target_t *ptgt = NULL;
7781 8663
7782 8664 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt));
7783 8665
7784 8666 ASSERT(mutex_owned(&mpt->m_mutex));
7785 8667
7786 8668 /*
7787 8669 * If there is a reset delay, don't start any cmds. Otherwise, start
7788 8670 * as many cmds as possible.
7789 8671 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
7790 8672 * commands is m_max_requests - 2.
7791 8673 */
7792 8674 cmd = mpt->m_waitq;
7793 8675
7794 8676 while (cmd != NULL) {
7795 8677 next_cmd = cmd->cmd_linkp;
7796 8678 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
7797 8679 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7798 8680 /*
7799 8681 * passthru command get slot need
7800 8682 * set CFLAG_PREPARED.
7801 8683 */
7802 8684 cmd->cmd_flags |= CFLAG_PREPARED;
7803 8685 mptsas_waitq_delete(mpt, cmd);
7804 8686 mptsas_start_passthru(mpt, cmd);
7805 8687 }
7806 8688 cmd = next_cmd;
7807 8689 continue;
7808 8690 }
7809 8691 if (cmd->cmd_flags & CFLAG_CONFIG) {
7810 8692 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7811 8693 /*
7812 8694 * Send the config page request and delete it
7813 8695 * from the waitq.
7814 8696 */
7815 8697 cmd->cmd_flags |= CFLAG_PREPARED;
7816 8698 mptsas_waitq_delete(mpt, cmd);
7817 8699 mptsas_start_config_page_access(mpt, cmd);
7818 8700 }
7819 8701 cmd = next_cmd;
7820 8702 continue;
7821 8703 }
7822 8704 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
7823 8705 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7824 8706 /*
7825 8707 * Send the FW Diag request and delete if from
7826 8708 * the waitq.
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7827 8709 */
7828 8710 cmd->cmd_flags |= CFLAG_PREPARED;
7829 8711 mptsas_waitq_delete(mpt, cmd);
7830 8712 mptsas_start_diag(mpt, cmd);
7831 8713 }
7832 8714 cmd = next_cmd;
7833 8715 continue;
7834 8716 }
7835 8717
7836 8718 ptgt = cmd->cmd_tgt_addr;
7837 - if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) &&
7838 - (ptgt->m_t_ncmds == 0)) {
7839 - mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8719 + if (ptgt) {
8720 + mutex_enter(&ptgt->m_t_mutex);
8721 + if ((ptgt->m_t_throttle == DRAIN_THROTTLE) &&
8722 + (ptgt->m_t_ncmds == 0)) {
8723 + mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8724 + }
8725 + if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
8726 + (ptgt->m_reset_delay == 0) &&
8727 + (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
8728 + mutex_exit(&ptgt->m_t_mutex);
8729 +
8730 + if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8731 + mptsas_waitq_delete(mpt, cmd);
8732 + mutex_exit(&mpt->m_mutex);
8733 + (void) mptsas_start_cmd(mpt, cmd);
8734 + mutex_enter(&mpt->m_mutex);
8735 + cmd = mpt->m_waitq;
8736 + continue;
8737 + }
8738 + } else {
8739 + mutex_exit(&ptgt->m_t_mutex);
8740 + }
7840 8741 }
7841 - if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
7842 - (ptgt && (ptgt->m_reset_delay == 0)) &&
7843 - (ptgt && (ptgt->m_t_ncmds <
7844 - ptgt->m_t_throttle))) {
7845 - if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7846 - mptsas_waitq_delete(mpt, cmd);
8742 + cmd = next_cmd;
8743 + }
8744 +}
8745 +
8746 +/*
8747 + * Cmds are queued if scsi_start() doesn't get the m_mutex lock(no wait)
8748 + * or if the decision has been made to always do that. Setting
8749 + * mptsas_allow_txq_jumping to zero will allow higher performance on
8750 + * a heavily loaded system as there is less disruption to the flow here.
8751 + * There are 2 threads that handle one queue each. The idea is that
8752 + * they take it in turn to grab the m_mutex to run the mptsas_accept_pkt()
8753 + * function and then drop it while the cmd is started in mptsas_start_cmd().
8754 + */
8755 +static void
8756 +mptsas_tx_waitq_thread(mptsas_thread_arg_t *arg)
8757 +{
8758 + mptsas_t *mpt = arg->mpt;
8759 + mptsas_tx_waitqueue_t *txwq = &mpt->m_tx_waitq[arg->t];
8760 +
8761 + mutex_enter(&txwq->txwq_mutex);
8762 + while (txwq->txwq_active) {
8763 + mptsas_drain_tx_waitq(mpt, txwq);
8764 + if (txwq->txwq_wdrain) {
8765 + cv_signal(&txwq->txwq_drain_cv);
8766 + }
8767 + cv_wait(&txwq->txwq_cv, &txwq->txwq_mutex);
8768 + }
8769 + mutex_exit(&txwq->txwq_mutex);
8770 + mutex_enter(&mpt->m_qthread_mutex);
8771 + mpt->m_txwq_thread_n--;
8772 + cv_broadcast(&mpt->m_qthread_cv);
8773 + mutex_exit(&mpt->m_qthread_mutex);
8774 +}
8775 +
8776 +/*
8777 + * Set the draining flag, disconnect the list and process one at a time
8778 + * so that the cmds are sent in order.
8779 + */
8780 +static void
8781 +mptsas_drain_tx_waitq(mptsas_t *mpt, mptsas_tx_waitqueue_t *txwq)
8782 +{
8783 + mptsas_cmd_t *cmd, *ncmd;
8784 + int rval, start;
8785 +#ifdef MPTSAS_DEBUG
8786 + uint32_t qlen;
8787 +#endif
8788 +
8789 + txwq->txwq_draining = TRUE;
8790 +#ifndef __lock_lint
8791 + _NOTE(CONSTCOND)
8792 +#endif
8793 + while (TRUE) {
8794 +
8795 + /*
8796 + * A Bus Reset could occur at any time but it will have to
8797 + * wait for the main mutex before flushing the tx_waitq.
8798 + * Pull all commands at once, then follow the list in order to
8799 + * reduce txwq_mutex hold time. If there is a Bus Reset at
8800 + * some point the commands will get to the waitq and then be
8801 + * flushed.
8802 + */
8803 + cmd = txwq->txwq_cmdq;
8804 +
8805 + if (cmd == NULL) {
8806 + txwq->txwq_draining = FALSE;
8807 + return;
8808 + }
8809 + txwq->txwq_cmdq = NULL;
8810 + txwq->txwq_qtail = &txwq->txwq_cmdq;
8811 +#ifdef MPTSAS_DEBUG
8812 + qlen = txwq->txwq_len;
8813 +#endif
8814 + txwq->txwq_len = 0;
8815 + mutex_exit(&txwq->txwq_mutex);
8816 +
8817 + while (cmd) {
8818 + ncmd = cmd->cmd_linkp;
8819 + cmd->cmd_linkp = NULL;
8820 + mutex_enter(&mpt->m_mutex);
8821 + start = mptsas_accept_pkt(mpt, cmd, &rval);
8822 + mutex_exit(&mpt->m_mutex);
8823 + if (start) {
7847 8824 (void) mptsas_start_cmd(mpt, cmd);
7848 8825 }
8826 + if (rval != TRAN_ACCEPT)
8827 + cmn_err(CE_WARN,
8828 + "mpt: mptsas_drain_tx_waitq: failed "
8829 + "(rval=0x%x) to accept cmd 0x%p on queue\n",
8830 + rval, (void *)cmd);
8831 + cmd = ncmd;
8832 +#ifdef MPTSAS_DEBUG
8833 + qlen--;
8834 +#endif
7849 8835 }
7850 - cmd = next_cmd;
8836 + ASSERT(qlen == 0);
8837 + mutex_enter(&txwq->txwq_mutex);
7851 8838 }
7852 8839 }
8840 +
7853 8841 /*
7854 - * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait).
7855 - * Accept all those queued cmds before new cmd is accept so that the
7856 - * cmds are sent in order.
8842 + * Stop the drain threads from picking up a new list.
8843 + * Optionally wait for the current list being processed to drain through.
8844 + * Add to and processing the tx waitq is now on hold until unblock is called.
7857 8845 */
7858 8846 static void
7859 -mptsas_accept_tx_waitq(mptsas_t *mpt)
8847 +mptsas_block_tx_waitqs(mptsas_t *mpt, int wait)
7860 8848 {
7861 - mptsas_cmd_t *cmd;
8849 + int i;
8850 + uint8_t wdrain = 0;
8851 + mptsas_tx_waitqueue_t *txwq;
7862 8852
7863 8853 ASSERT(mutex_owned(&mpt->m_mutex));
7864 - ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex));
8854 +
8855 + if (mpt->m_txwq_thread_n == 0) {
8856 + return;
8857 + }
7865 8858
7866 8859 /*
7867 - * A Bus Reset could occur at any time and flush the tx_waitq,
7868 - * so we cannot count on the tx_waitq to contain even one cmd.
7869 - * And when the m_tx_waitq_mutex is released and run
7870 - * mptsas_accept_pkt(), the tx_waitq may be flushed.
8860 + * Turn off the use of the tx wait queues by scsi_start().
8861 + * This is just a dynamic flag no need for a mutex.
7871 8862 */
7872 - cmd = mpt->m_tx_waitq;
7873 - for (;;) {
7874 - if ((cmd = mpt->m_tx_waitq) == NULL) {
7875 - mpt->m_tx_draining = 0;
7876 - break;
7877 - }
7878 - if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) {
7879 - mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8863 + mpt->m_txwq_enabled = BLOCKED;
8864 +
8865 + for (i = 0; i < NUM_TX_WAITQ; i++) {
8866 + txwq = &mpt->m_tx_waitq[i];
8867 + mutex_enter(&txwq->txwq_mutex);
8868 + txwq->txwq_wdrain = TRUE;
8869 + if (txwq->txwq_draining && wait)
8870 + wdrain |= (1<<i);
8871 + mutex_exit(&txwq->txwq_mutex);
8872 + }
8873 +
8874 + if (wdrain) {
8875 + /*
8876 + * Because the threads disconnect the entire queue each time
8877 + * round in order to drain to completely drain we have to
8878 + * drop the main mutex otherwise the drain threads get stuck.
8879 + */
8880 + mutex_exit(&mpt->m_mutex);
8881 + for (i = 0; i < NUM_TX_WAITQ; i++) {
8882 + if (wdrain & (1<<i)) {
8883 + txwq = &mpt->m_tx_waitq[i];
8884 + mutex_enter(&txwq->txwq_mutex);
8885 + while (txwq->txwq_draining) {
8886 + cv_wait(&txwq->txwq_drain_cv,
8887 + &txwq->txwq_mutex);
8888 + }
8889 + mutex_exit(&txwq->txwq_mutex);
8890 + }
7880 8891 }
7881 - cmd->cmd_linkp = NULL;
7882 - mutex_exit(&mpt->m_tx_waitq_mutex);
7883 - if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT)
7884 - cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed "
7885 - "to accept cmd on queue\n");
7886 - mutex_enter(&mpt->m_tx_waitq_mutex);
8892 + mutex_enter(&mpt->m_mutex);
7887 8893 }
7888 8894 }
7889 8895
8896 +static void
8897 +mptsas_unblock_tx_waitqs(mptsas_t *mpt)
8898 +{
8899 + int i;
8900 + mptsas_tx_waitqueue_t *txwq;
8901 +
8902 + if (mpt->m_txwq_thread_n == 0) {
8903 + return;
8904 + }
8905 +
8906 + for (i = 0; i < NUM_TX_WAITQ; i++) {
8907 + txwq = &mpt->m_tx_waitq[i];
8908 + mutex_enter(&txwq->txwq_mutex);
8909 + txwq->txwq_wdrain = FALSE;
8910 + cv_signal(&txwq->txwq_cv);
8911 + mutex_exit(&txwq->txwq_mutex);
8912 + }
8913 +
8914 + mpt->m_txwq_enabled = FALSE;
8915 +}
8916 +
8917 +static void
8918 +mptsas_accept_tx_waitqs(mptsas_t *mpt)
8919 +{
8920 + /*
8921 + * Block with drain and unblock will leave us in a state where
8922 + * we have the main mutex, there is nothing on the tx wait queues
8923 + * and they are not in use until watch notices high activity again.
8924 + */
8925 + mptsas_block_tx_waitqs(mpt, 1);
8926 + mptsas_unblock_tx_waitqs(mpt);
8927 +}
7890 8928
7891 8929 /*
7892 8930 * mpt tag type lookup
7893 8931 */
7894 8932 static char mptsas_tag_lookup[] =
7895 8933 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
7896 8934
7897 8935 static int
7898 8936 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7899 8937 {
7900 8938 struct scsi_pkt *pkt = CMD2PKT(cmd);
7901 8939 uint32_t control = 0;
7902 - int n;
7903 - caddr_t mem;
8940 + caddr_t mem, arsbuf;
7904 8941 pMpi2SCSIIORequest_t io_request;
7905 8942 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
7906 8943 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
7907 8944 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7908 - uint16_t SMID, io_flags = 0;
7909 - uint32_t request_desc_low, request_desc_high;
8945 + uint16_t SMID, io_flags = 0, ars_size;
8946 + uint8_t MSIidx;
8947 + uint64_t request_desc;
8948 + uint32_t ars_dmaaddrlow;
8949 + mptsas_cmd_t *c;
7910 8950
7911 - NDBG1(("mptsas_start_cmd: cmd=0x%p", (void *)cmd));
8951 + NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd,
8952 + cmd->cmd_flags));
7912 8953
7913 8954 /*
7914 8955 * Set SMID and increment index. Rollover to 1 instead of 0 if index
7915 8956 * is at the max. 0 is an invalid SMID, so we call the first index 1.
7916 8957 */
7917 8958 SMID = cmd->cmd_slot;
8959 + MSIidx = cmd->cmd_rpqidx;
7918 8960
7919 8961 /*
7920 8962 * It is possible for back to back device reset to
7921 8963 * happen before the reset delay has expired. That's
7922 8964 * ok, just let the device reset go out on the bus.
7923 8965 */
7924 8966 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
7925 8967 ASSERT(ptgt->m_reset_delay == 0);
7926 8968 }
7927 8969
7928 8970 /*
7929 8971 * if a non-tagged cmd is submitted to an active tagged target
7930 8972 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
7931 8973 * to be untagged
7932 8974 */
8975 + mutex_enter(&ptgt->m_t_mutex);
7933 8976 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
7934 8977 (ptgt->m_t_ncmds > 1) &&
7935 8978 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
7936 8979 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
7937 8980 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
7938 8981 NDBG23(("target=%d, untagged cmd, start draining\n",
7939 8982 ptgt->m_devhdl));
7940 8983
7941 8984 if (ptgt->m_reset_delay == 0) {
7942 8985 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
7943 8986 }
8987 + mutex_exit(&ptgt->m_t_mutex);
7944 8988
8989 + mutex_enter(&mpt->m_mutex);
7945 8990 mptsas_remove_cmd(mpt, cmd);
7946 8991 cmd->cmd_pkt_flags |= FLAG_HEAD;
7947 8992 mptsas_waitq_add(mpt, cmd);
8993 + mutex_exit(&mpt->m_mutex);
8994 + } else {
8995 + mutex_exit(&ptgt->m_t_mutex);
7948 8996 }
7949 8997 return (DDI_FAILURE);
7950 8998 }
7951 8999
7952 9000 /*
7953 9001 * Set correct tag bits.
7954 9002 */
7955 9003 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
7956 9004 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
7957 9005 FLAG_TAGMASK) >> 12)]) {
7958 9006 case MSG_SIMPLE_QTAG:
7959 9007 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
7960 9008 break;
7961 9009 case MSG_HEAD_QTAG:
7962 9010 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
7963 9011 break;
7964 9012 case MSG_ORDERED_QTAG:
7965 9013 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
7966 9014 break;
7967 9015 default:
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7968 9016 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
7969 9017 break;
7970 9018 }
7971 9019 } else {
7972 9020 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
7973 9021 ptgt->m_t_throttle = 1;
7974 9022 }
7975 9023 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
7976 9024 }
7977 9025
9026 + /*
9027 + * Set timeout.
9028 + */
9029 + cmd->cmd_active_expiration =
9030 + gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC;
9031 +
9032 + c = TAILQ_FIRST(&ptgt->m_active_cmdq);
9033 + if (c == NULL ||
9034 + c->cmd_active_expiration < cmd->cmd_active_expiration) {
9035 + /*
9036 + * Common case is that this is the last pending expiration
9037 + * (or queue is empty). Insert at head of the queue.
9038 + */
9039 + TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link);
9040 + } else {
9041 + /*
9042 + * Queue is not empty and first element expires later than
9043 + * this command. Search for element expiring sooner.
9044 + */
9045 + while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) {
9046 + if (c->cmd_active_expiration <
9047 + cmd->cmd_active_expiration) {
9048 + TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link);
9049 + break;
9050 + }
9051 + }
9052 + if (c == NULL) {
9053 + /*
9054 + * No element found expiring sooner, append to
9055 + * non-empty queue.
9056 + */
9057 + TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd,
9058 + cmd_active_link);
9059 + }
9060 + }
9061 +
9062 + mutex_exit(&ptgt->m_t_mutex);
9063 +
7978 9064 if (cmd->cmd_pkt_flags & FLAG_TLR) {
7979 9065 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
7980 9066 }
7981 9067
7982 9068 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
7983 9069 io_request = (pMpi2SCSIIORequest_t)mem;
7984 -
9070 + if (cmd->cmd_extrqslen != 0) {
9071 + /*
9072 + * Mapping of the buffer was done in mptsas_pkt_alloc_extern().
9073 + * Calculate the DMA address with the same offset.
9074 + */
9075 + arsbuf = cmd->cmd_arq_buf;
9076 + ars_size = cmd->cmd_extrqslen;
9077 + ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
9078 + ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
9079 + 0xffffffffull;
9080 + } else {
9081 + arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1));
9082 + cmd->cmd_arq_buf = arsbuf;
9083 + ars_size = mpt->m_req_sense_size;
9084 + ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
9085 + (mpt->m_req_sense_size * (SMID-1))) &
9086 + 0xffffffffull;
9087 + }
7985 9088 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
9089 + bzero(arsbuf, ars_size);
9090 +
7986 9091 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
7987 9092 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
7988 9093 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
7989 9094 MPI2_FUNCTION_SCSI_IO_REQUEST);
7990 9095
7991 9096 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
7992 9097 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
7993 9098
7994 9099 io_flags = cmd->cmd_cdblen;
9100 + if (mptsas3_use_fastpath &&
9101 + ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) {
9102 + io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH;
9103 + request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
9104 + } else {
9105 + request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
9106 + }
7995 9107 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
7996 9108 /*
7997 9109 * setup the Scatter/Gather DMA list for this request
7998 9110 */
7999 9111 if (cmd->cmd_cookiec > 0) {
8000 9112 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
8001 9113 } else {
8002 9114 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
8003 9115 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
8004 9116 MPI2_SGE_FLAGS_END_OF_BUFFER |
8005 9117 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
8006 9118 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
8007 9119 }
8008 9120
8009 9121 /*
8010 9122 * save ARQ information
8011 9123 */
8012 9124 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen);
8013 - if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
8014 - (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
8015 - ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8016 - cmd->cmd_ext_arqcookie.dmac_address);
8017 - } else {
8018 - ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8019 - cmd->cmd_arqcookie.dmac_address);
8020 - }
9125 + ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow);
8021 9126
8022 9127 ddi_put32(acc_hdl, &io_request->Control, control);
8023 9128
8024 - NDBG31(("starting message=0x%p, with cmd=0x%p",
8025 - (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd));
9129 + NDBG31(("starting message=%d(0x%p), with cmd=0x%p",
9130 + SMID, (void *)io_request, (void *)cmd));
8026 9131
8027 9132 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
8028 9133
8029 9134 /*
8030 9135 * Build request descriptor and write it to the request desc post reg.
8031 9136 */
8032 - request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
8033 - request_desc_high = ptgt->m_devhdl << 16;
8034 - MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
8035 -
8036 - /*
8037 - * Start timeout.
8038 - */
8039 -#ifdef MPTSAS_TEST
8040 - /*
8041 - * Temporarily set timebase = 0; needed for
8042 - * timeout torture test.
8043 - */
8044 - if (mptsas_test_timeouts) {
8045 - ptgt->m_timebase = 0;
8046 - }
8047 -#endif
8048 - n = pkt->pkt_time - ptgt->m_timebase;
8049 -
8050 - if (n == 0) {
8051 - (ptgt->m_dups)++;
8052 - ptgt->m_timeout = ptgt->m_timebase;
8053 - } else if (n > 0) {
8054 - ptgt->m_timeout =
8055 - ptgt->m_timebase = pkt->pkt_time;
8056 - ptgt->m_dups = 1;
8057 - } else if (n < 0) {
8058 - ptgt->m_timeout = ptgt->m_timebase;
8059 - }
8060 -#ifdef MPTSAS_TEST
8061 - /*
8062 - * Set back to a number higher than
8063 - * mptsas_scsi_watchdog_tick
8064 - * so timeouts will happen in mptsas_watchsubr
8065 - */
8066 - if (mptsas_test_timeouts) {
8067 - ptgt->m_timebase = 60;
8068 - }
8069 -#endif
9137 + request_desc |= (SMID << 16) + (MSIidx << 8);
9138 + request_desc |= ((uint64_t)ptgt->m_devhdl << 48);
9139 + MPTSAS_START_CMD(mpt, request_desc);
8070 9140
9141 +#if 0
9142 + /* Is this of any benefit here, what is it going to catch? */
8071 9143 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8072 9144 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8073 9145 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8074 9146 return (DDI_FAILURE);
8075 9147 }
9148 +#endif
8076 9149 return (DDI_SUCCESS);
8077 9150 }
8078 9151
8079 9152 /*
8080 - * Select a helper thread to handle current doneq
9153 + * Select a helper thread to handle given doneq.
9154 + * Note that we don't require to have the main m_mutex here, but worst case
9155 + * is that we wont follow the thread rotation to the letter.
9156 + * However must ensure we have the mutex that covers the source dlist when
9157 + * we actually hand off.
8081 9158 */
8082 9159 static void
8083 -mptsas_deliver_doneq_thread(mptsas_t *mpt)
9160 +mptsas_deliver_doneq_thread(mptsas_t *mpt, mptsas_done_list_t *dlist)
8084 9161 {
8085 - uint64_t t, i;
9162 + uint32_t t, i, j = mpt->m_doneq_next_thread;
8086 9163 uint32_t min = 0xffffffff;
8087 9164 mptsas_doneq_thread_list_t *item;
8088 9165
9166 + /*
9167 + * No need to take indivudual list mutex's during the loop.
9168 + * We are only reading values and the worst that will happen is that
9169 + * we pick the wrong thread.
9170 + */
8089 9171 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8090 - item = &mpt->m_doneq_thread_id[i];
9172 + item = &mpt->m_doneq_thread_id[j];
9173 +
8091 9174 /*
8092 9175 * If the completed command on help thread[i] less than
8093 - * doneq_thread_threshold, then pick the thread[i]. Otherwise
9176 + * doneq_thread_threshold, then pick the thread[j]. Otherwise
8094 9177 * pick a thread which has least completed command.
8095 9178 */
8096 -
8097 - mutex_enter(&item->mutex);
8098 - if (item->len < mpt->m_doneq_thread_threshold) {
8099 - t = i;
8100 - mutex_exit(&item->mutex);
9179 + if (item->dlist.dl_len < mpt->m_doneq_thread_threshold) {
9180 + t = j;
8101 9181 break;
8102 9182 }
8103 - if (item->len < min) {
8104 - min = item->len;
8105 - t = i;
9183 + if (item->dlist.dl_len < min) {
9184 + min = item->dlist.dl_len;
9185 + t = j;
8106 9186 }
8107 - mutex_exit(&item->mutex);
9187 + if (++j == mpt->m_doneq_thread_n) {
9188 + j = 0;
9189 + }
9190 + }
9191 + item = &mpt->m_doneq_thread_id[t];
9192 + mutex_enter(&item->mutex);
9193 + mptsas_doneq_mv(dlist, item);
9194 + cv_signal(&item->cv);
9195 + mutex_exit(&item->mutex);
9196 +
9197 + /*
9198 + * Next time start at the next thread.
9199 + * This will minimize the potential of grabing a lock
9200 + * for a thread that is busy, either on a very busy systems
9201 + * or on one that is configured to do all command completion
9202 + * processing through threads.
9203 + */
9204 + if (++t == mpt->m_doneq_thread_n) {
9205 + t = 0;
8108 9206 }
8109 - mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8110 - mptsas_doneq_mv(mpt, t);
8111 - cv_signal(&mpt->m_doneq_thread_id[t].cv);
8112 - mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
9207 + mpt->m_doneq_next_thread = (uint16_t)t;
8113 9208 }
8114 9209
8115 9210 /*
8116 - * move the current global doneq to the doneq of thead[t]
9211 + * move one doneq to another.
8117 9212 */
8118 9213 static void
8119 -mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
9214 +mptsas_doneq_mv(mptsas_done_list_t *from, mptsas_doneq_thread_list_t *item)
8120 9215 {
9216 + mptsas_done_list_t *to = &item->dlist;
8121 9217 mptsas_cmd_t *cmd;
8122 - mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8123 9218
8124 - ASSERT(mutex_owned(&item->mutex));
8125 - while ((cmd = mpt->m_doneq) != NULL) {
8126 - if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8127 - mpt->m_donetail = &mpt->m_doneq;
8128 - }
8129 - cmd->cmd_linkp = NULL;
8130 - *item->donetail = cmd;
8131 - item->donetail = &cmd->cmd_linkp;
8132 - mpt->m_doneq_len--;
8133 - item->len++;
9219 + if ((cmd = from->dl_q) != NULL) {
9220 + *to->dl_tail = cmd;
9221 + to->dl_tail = from->dl_tail;
9222 + to->dl_len += from->dl_len;
9223 + from->dl_q = NULL;
9224 + from->dl_tail = &from->dl_q;
9225 + from->dl_len = 0;
8134 9226 }
8135 9227 }
8136 9228
8137 9229 void
8138 9230 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8139 9231 {
8140 9232 struct scsi_pkt *pkt = CMD2PKT(cmd);
8141 9233
8142 9234 /* Check all acc and dma handles */
8143 9235 if ((mptsas_check_acc_handle(mpt->m_datap) !=
8144 9236 DDI_SUCCESS) ||
8145 9237 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8146 9238 DDI_SUCCESS) ||
9239 + (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
9240 + DDI_SUCCESS) ||
8147 9241 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8148 9242 DDI_SUCCESS) ||
8149 9243 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8150 9244 DDI_SUCCESS) ||
8151 9245 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8152 9246 DDI_SUCCESS) ||
8153 9247 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8154 9248 DDI_SUCCESS) ||
8155 9249 (mptsas_check_acc_handle(mpt->m_config_handle) !=
8156 9250 DDI_SUCCESS)) {
8157 9251 ddi_fm_service_impact(mpt->m_dip,
8158 9252 DDI_SERVICE_UNAFFECTED);
8159 9253 ddi_fm_acc_err_clear(mpt->m_config_handle,
8160 9254 DDI_FME_VER0);
8161 9255 pkt->pkt_reason = CMD_TRAN_ERR;
8162 9256 pkt->pkt_statistics = 0;
8163 9257 }
8164 9258 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8165 9259 DDI_SUCCESS) ||
9260 + (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
9261 + DDI_SUCCESS) ||
8166 9262 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8167 9263 DDI_SUCCESS) ||
8168 9264 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8169 9265 DDI_SUCCESS) ||
8170 9266 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8171 9267 DDI_SUCCESS) ||
8172 9268 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8173 9269 DDI_SUCCESS)) {
8174 9270 ddi_fm_service_impact(mpt->m_dip,
8175 9271 DDI_SERVICE_UNAFFECTED);
8176 9272 pkt->pkt_reason = CMD_TRAN_ERR;
8177 9273 pkt->pkt_statistics = 0;
8178 9274 }
8179 9275 if (cmd->cmd_dmahandle &&
8180 9276 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8181 9277 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8182 9278 pkt->pkt_reason = CMD_TRAN_ERR;
8183 9279 pkt->pkt_statistics = 0;
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8184 9280 }
8185 9281 if ((cmd->cmd_extra_frames &&
8186 9282 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8187 9283 DDI_SUCCESS) ||
8188 9284 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8189 9285 DDI_SUCCESS)))) {
8190 9286 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8191 9287 pkt->pkt_reason = CMD_TRAN_ERR;
8192 9288 pkt->pkt_statistics = 0;
8193 9289 }
8194 - if (cmd->cmd_arqhandle &&
8195 - (mptsas_check_dma_handle(cmd->cmd_arqhandle) != DDI_SUCCESS)) {
8196 - ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8197 - pkt->pkt_reason = CMD_TRAN_ERR;
8198 - pkt->pkt_statistics = 0;
8199 - }
8200 - if (cmd->cmd_ext_arqhandle &&
8201 - (mptsas_check_dma_handle(cmd->cmd_ext_arqhandle) != DDI_SUCCESS)) {
8202 - ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8203 - pkt->pkt_reason = CMD_TRAN_ERR;
8204 - pkt->pkt_statistics = 0;
8205 - }
8206 9290 }
8207 9291
8208 9292 /*
8209 9293 * These routines manipulate the queue of commands that
8210 9294 * are waiting for their completion routines to be called.
8211 9295 * The queue is usually in FIFO order but on an MP system
8212 9296 * it's possible for the completion routines to get out
8213 9297 * of order. If that's a problem you need to add a global
8214 9298 * mutex around the code that calls the completion routine
8215 9299 * in the interrupt handler.
8216 9300 */
8217 9301 static void
8218 9302 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8219 9303 {
8220 9304 struct scsi_pkt *pkt = CMD2PKT(cmd);
8221 9305
8222 9306 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd));
8223 9307
8224 9308 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8225 9309 cmd->cmd_linkp = NULL;
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8226 9310 cmd->cmd_flags |= CFLAG_FINISHED;
8227 9311 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8228 9312
8229 9313 mptsas_fma_check(mpt, cmd);
8230 9314
8231 9315 /*
8232 9316 * only add scsi pkts that have completion routines to
8233 9317 * the doneq. no intr cmds do not have callbacks.
8234 9318 */
8235 9319 if (pkt && (pkt->pkt_comp)) {
8236 - *mpt->m_donetail = cmd;
8237 - mpt->m_donetail = &cmd->cmd_linkp;
8238 - mpt->m_doneq_len++;
9320 + *mpt->m_dlist.dl_tail = cmd;
9321 + mpt->m_dlist.dl_tail = &cmd->cmd_linkp;
9322 + mpt->m_dlist.dl_len++;
9323 + }
9324 +}
9325 +
9326 +static void
9327 +mptsas_rpdoneq_add(mptsas_t *mpt, mptsas_reply_pqueue_t *rpqp,
9328 + mptsas_cmd_t *cmd)
9329 +{
9330 + struct scsi_pkt *pkt = CMD2PKT(cmd);
9331 +
9332 + NDBG31(("mptsas_rpdoneq_add: cmd=0x%p", (void *)cmd));
9333 +
9334 + ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
9335 + cmd->cmd_linkp = NULL;
9336 + cmd->cmd_flags |= CFLAG_FINISHED;
9337 + cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
9338 +
9339 + mptsas_fma_check(mpt, cmd);
9340 +
9341 + /*
9342 + * only add scsi pkts that have completion routines to
9343 + * the doneq. no intr cmds do not have callbacks.
9344 + */
9345 + if (pkt && (pkt->pkt_comp)) {
9346 + *rpqp->rpq_dlist.dl_tail = cmd;
9347 + rpqp->rpq_dlist.dl_tail = &cmd->cmd_linkp;
9348 + rpqp->rpq_dlist.dl_len++;
8239 9349 }
8240 9350 }
8241 9351
8242 9352 static mptsas_cmd_t *
8243 9353 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8244 9354 {
8245 9355 mptsas_cmd_t *cmd;
8246 9356 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8247 9357
8248 9358 /* pop one off the done queue */
8249 - if ((cmd = item->doneq) != NULL) {
9359 + if ((cmd = item->dlist.dl_q) != NULL) {
8250 9360 /* if the queue is now empty fix the tail pointer */
8251 9361 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
8252 - if ((item->doneq = cmd->cmd_linkp) == NULL) {
8253 - item->donetail = &item->doneq;
9362 + if ((item->dlist.dl_q = cmd->cmd_linkp) == NULL) {
9363 + item->dlist.dl_tail = &item->dlist.dl_q;
8254 9364 }
8255 9365 cmd->cmd_linkp = NULL;
8256 - item->len--;
9366 + item->dlist.dl_len--;
8257 9367 }
8258 9368 return (cmd);
8259 9369 }
8260 9370
8261 9371 static void
8262 9372 mptsas_doneq_empty(mptsas_t *mpt)
8263 9373 {
8264 - if (mpt->m_doneq && !mpt->m_in_callback) {
9374 + if (mpt->m_dlist.dl_q) {
8265 9375 mptsas_cmd_t *cmd, *next;
8266 9376 struct scsi_pkt *pkt;
8267 9377
8268 - mpt->m_in_callback = 1;
8269 - cmd = mpt->m_doneq;
8270 - mpt->m_doneq = NULL;
8271 - mpt->m_donetail = &mpt->m_doneq;
8272 - mpt->m_doneq_len = 0;
9378 + cmd = mpt->m_dlist.dl_q;
9379 + mpt->m_dlist.dl_q = NULL;
9380 + mpt->m_dlist.dl_tail = &mpt->m_dlist.dl_q;
9381 + mpt->m_dlist.dl_len = 0;
8273 9382
8274 9383 mutex_exit(&mpt->m_mutex);
8275 9384 /*
8276 9385 * run the completion routines of all the
8277 9386 * completed commands
8278 9387 */
8279 9388 while (cmd != NULL) {
8280 9389 next = cmd->cmd_linkp;
8281 9390 cmd->cmd_linkp = NULL;
8282 9391 /* run this command's completion routine */
8283 9392 cmd->cmd_flags |= CFLAG_COMPLETED;
8284 9393 pkt = CMD2PKT(cmd);
8285 9394 mptsas_pkt_comp(pkt, cmd);
8286 9395 cmd = next;
8287 9396 }
8288 9397 mutex_enter(&mpt->m_mutex);
8289 - mpt->m_in_callback = 0;
9398 + }
9399 +}
9400 +
9401 +static void
9402 +mptsas_rpdoneq_empty(mptsas_reply_pqueue_t *rpqp)
9403 +{
9404 + if (rpqp->rpq_dlist.dl_q) {
9405 + mptsas_cmd_t *cmd, *next;
9406 + struct scsi_pkt *pkt;
9407 +
9408 + cmd = rpqp->rpq_dlist.dl_q;
9409 + rpqp->rpq_dlist.dl_q = NULL;
9410 + rpqp->rpq_dlist.dl_tail = &rpqp->rpq_dlist.dl_q;
9411 + rpqp->rpq_dlist.dl_len = 0;
9412 +
9413 + mutex_exit(&rpqp->rpq_mutex);
9414 + /*
9415 + * run the completion routines of all the
9416 + * completed commands
9417 + */
9418 + while (cmd != NULL) {
9419 + next = cmd->cmd_linkp;
9420 + cmd->cmd_linkp = NULL;
9421 + /* run this command's completion routine */
9422 + cmd->cmd_flags |= CFLAG_COMPLETED;
9423 + pkt = CMD2PKT(cmd);
9424 + mptsas_pkt_comp(pkt, cmd);
9425 + cmd = next;
9426 + }
9427 + mutex_enter(&rpqp->rpq_mutex);
8290 9428 }
8291 9429 }
8292 9430
8293 9431 /*
8294 9432 * These routines manipulate the target's queue of pending requests
8295 9433 */
8296 9434 void
8297 9435 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8298 9436 {
8299 9437 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
8300 9438 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8301 9439 cmd->cmd_queued = TRUE;
8302 9440 if (ptgt)
8303 9441 ptgt->m_t_nwait++;
8304 9442 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
8305 9443 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
8306 9444 mpt->m_waitqtail = &cmd->cmd_linkp;
8307 9445 }
8308 9446 mpt->m_waitq = cmd;
8309 9447 } else {
8310 9448 cmd->cmd_linkp = NULL;
8311 9449 *(mpt->m_waitqtail) = cmd;
8312 9450 mpt->m_waitqtail = &cmd->cmd_linkp;
8313 9451 }
8314 9452 }
8315 9453
8316 9454 static mptsas_cmd_t *
8317 9455 mptsas_waitq_rm(mptsas_t *mpt)
8318 9456 {
8319 9457 mptsas_cmd_t *cmd;
8320 9458 mptsas_target_t *ptgt;
8321 9459 NDBG7(("mptsas_waitq_rm"));
8322 9460
8323 9461 MPTSAS_WAITQ_RM(mpt, cmd);
8324 9462
8325 9463 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
8326 9464 if (cmd) {
8327 9465 ptgt = cmd->cmd_tgt_addr;
8328 9466 if (ptgt) {
8329 9467 ptgt->m_t_nwait--;
8330 9468 ASSERT(ptgt->m_t_nwait >= 0);
8331 9469 }
8332 9470 }
8333 9471 return (cmd);
8334 9472 }
8335 9473
8336 9474 /*
8337 9475 * remove specified cmd from the middle of the wait queue.
8338 9476 */
8339 9477 static void
8340 9478 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8341 9479 {
8342 9480 mptsas_cmd_t *prevp = mpt->m_waitq;
8343 9481 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8344 9482
8345 9483 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8346 9484 (void *)mpt, (void *)cmd));
8347 9485 if (ptgt) {
8348 9486 ptgt->m_t_nwait--;
8349 9487 ASSERT(ptgt->m_t_nwait >= 0);
8350 9488 }
8351 9489
8352 9490 if (prevp == cmd) {
8353 9491 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
8354 9492 mpt->m_waitqtail = &mpt->m_waitq;
8355 9493
8356 9494 cmd->cmd_linkp = NULL;
8357 9495 cmd->cmd_queued = FALSE;
8358 9496 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8359 9497 (void *)mpt, (void *)cmd));
8360 9498 return;
8361 9499 }
8362 9500
8363 9501 while (prevp != NULL) {
8364 9502 if (prevp->cmd_linkp == cmd) {
8365 9503 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8366 9504 mpt->m_waitqtail = &prevp->cmd_linkp;
8367 9505
8368 9506 cmd->cmd_linkp = NULL;
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8369 9507 cmd->cmd_queued = FALSE;
8370 9508 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8371 9509 (void *)mpt, (void *)cmd));
8372 9510 return;
8373 9511 }
8374 9512 prevp = prevp->cmd_linkp;
8375 9513 }
8376 9514 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
8377 9515 }
8378 9516
8379 -static mptsas_cmd_t *
8380 -mptsas_tx_waitq_rm(mptsas_t *mpt)
8381 -{
8382 - mptsas_cmd_t *cmd;
8383 - NDBG7(("mptsas_tx_waitq_rm"));
8384 -
8385 - MPTSAS_TX_WAITQ_RM(mpt, cmd);
8386 -
8387 - NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd));
8388 -
8389 - return (cmd);
8390 -}
8391 -
8392 -/*
8393 - * remove specified cmd from the middle of the tx_waitq.
8394 - */
8395 -static void
8396 -mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8397 -{
8398 - mptsas_cmd_t *prevp = mpt->m_tx_waitq;
8399 -
8400 - NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8401 - (void *)mpt, (void *)cmd));
8402 -
8403 - if (prevp == cmd) {
8404 - if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL)
8405 - mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8406 -
8407 - cmd->cmd_linkp = NULL;
8408 - cmd->cmd_queued = FALSE;
8409 - NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8410 - (void *)mpt, (void *)cmd));
8411 - return;
8412 - }
8413 -
8414 - while (prevp != NULL) {
8415 - if (prevp->cmd_linkp == cmd) {
8416 - if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8417 - mpt->m_tx_waitqtail = &prevp->cmd_linkp;
8418 -
8419 - cmd->cmd_linkp = NULL;
8420 - cmd->cmd_queued = FALSE;
8421 - NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8422 - (void *)mpt, (void *)cmd));
8423 - return;
8424 - }
8425 - prevp = prevp->cmd_linkp;
8426 - }
8427 - cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch");
8428 -}
8429 -
8430 9517 /*
8431 9518 * device and bus reset handling
8432 9519 *
8433 9520 * Notes:
8434 9521 * - RESET_ALL: reset the controller
8435 9522 * - RESET_TARGET: reset the target specified in scsi_address
8436 9523 */
8437 9524 static int
8438 9525 mptsas_scsi_reset(struct scsi_address *ap, int level)
8439 9526 {
8440 9527 mptsas_t *mpt = ADDR2MPT(ap);
8441 9528 int rval;
8442 9529 mptsas_tgt_private_t *tgt_private;
8443 9530 mptsas_target_t *ptgt = NULL;
8444 9531
8445 9532 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
8446 9533 ptgt = tgt_private->t_private;
8447 9534 if (ptgt == NULL) {
8448 9535 return (FALSE);
8449 9536 }
8450 9537 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
8451 9538 level));
8452 9539
8453 9540 mutex_enter(&mpt->m_mutex);
8454 9541 /*
8455 9542 * if we are not in panic set up a reset delay for this target
8456 9543 */
8457 9544 if (!ddi_in_panic()) {
8458 9545 mptsas_setup_bus_reset_delay(mpt);
8459 9546 } else {
8460 9547 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
8461 9548 }
8462 9549 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
8463 9550 mutex_exit(&mpt->m_mutex);
8464 9551
8465 9552 /*
8466 9553 * The transport layer expect to only see TRUE and
8467 9554 * FALSE. Therefore, we will adjust the return value
8468 9555 * if mptsas_do_scsi_reset returns FAILED.
8469 9556 */
8470 9557 if (rval == FAILED)
8471 9558 rval = FALSE;
8472 9559 return (rval);
8473 9560 }
8474 9561
8475 9562 static int
8476 9563 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
8477 9564 {
8478 9565 int rval = FALSE;
8479 9566 uint8_t config, disk;
8480 9567
8481 9568 ASSERT(mutex_owned(&mpt->m_mutex));
8482 9569
8483 9570 if (mptsas_debug_resets) {
8484 9571 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
8485 9572 devhdl);
8486 9573 }
8487 9574
8488 9575 /*
8489 9576 * Issue a Target Reset message to the target specified but not to a
8490 9577 * disk making up a raid volume. Just look through the RAID config
8491 9578 * Phys Disk list of DevHandles. If the target's DevHandle is in this
8492 9579 * list, then don't reset this target.
8493 9580 */
8494 9581 for (config = 0; config < mpt->m_num_raid_configs; config++) {
8495 9582 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
8496 9583 if (devhdl == mpt->m_raidconfig[config].
8497 9584 m_physdisk_devhdl[disk]) {
8498 9585 return (TRUE);
8499 9586 }
8500 9587 }
8501 9588 }
8502 9589
8503 9590 rval = mptsas_ioc_task_management(mpt,
8504 9591 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
8505 9592
8506 9593 mptsas_doneq_empty(mpt);
8507 9594 return (rval);
8508 9595 }
8509 9596
8510 9597 static int
8511 9598 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
8512 9599 void (*callback)(caddr_t), caddr_t arg)
8513 9600 {
8514 9601 mptsas_t *mpt = ADDR2MPT(ap);
8515 9602
8516 9603 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
8517 9604
8518 9605 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
8519 9606 &mpt->m_mutex, &mpt->m_reset_notify_listf));
8520 9607 }
8521 9608
8522 9609 static int
8523 9610 mptsas_get_name(struct scsi_device *sd, char *name, int len)
8524 9611 {
8525 9612 dev_info_t *lun_dip = NULL;
8526 9613
8527 9614 ASSERT(sd != NULL);
8528 9615 ASSERT(name != NULL);
8529 9616 lun_dip = sd->sd_dev;
8530 9617 ASSERT(lun_dip != NULL);
8531 9618
8532 9619 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
8533 9620 return (1);
8534 9621 } else {
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8535 9622 return (0);
8536 9623 }
8537 9624 }
8538 9625
8539 9626 static int
8540 9627 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
8541 9628 {
8542 9629 return (mptsas_get_name(sd, name, len));
8543 9630 }
8544 9631
8545 -void
9632 +static void
8546 9633 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
8547 9634 {
8548 9635
8549 9636 NDBG25(("mptsas_set_throttle: throttle=%x", what));
8550 9637
8551 9638 /*
8552 9639 * if the bus is draining/quiesced, no changes to the throttles
8553 9640 * are allowed. Not allowing change of throttles during draining
8554 9641 * limits error recovery but will reduce draining time
8555 9642 *
8556 9643 * all throttles should have been set to HOLD_THROTTLE
8557 9644 */
8558 9645 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
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8559 9646 return;
8560 9647 }
8561 9648
8562 9649 if (what == HOLD_THROTTLE) {
8563 9650 ptgt->m_t_throttle = HOLD_THROTTLE;
8564 9651 } else if (ptgt->m_reset_delay == 0) {
8565 9652 ptgt->m_t_throttle = what;
8566 9653 }
8567 9654 }
8568 9655
9656 +static void
9657 +mptsas_set_throttle_mtx(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
9658 +{
9659 + if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
9660 + return;
9661 + }
9662 +
9663 + mutex_enter(&ptgt->m_t_mutex);
9664 + mptsas_set_throttle(mpt, ptgt, what);
9665 + mutex_exit(&ptgt->m_t_mutex);
9666 +}
9667 +
9668 +/*
9669 + * Find all commands in the tx_waitq's for target and lun (if lun not -1),
9670 + * remove them from the queues and return the linked list.
9671 + */
9672 +static mptsas_cmd_t *
9673 +mptsas_strip_targetlun_from_txwqs(mptsas_t *mpt, ushort_t target, int lun)
9674 +{
9675 + mptsas_cmd_t *cmd, *clist, **tailp, **prev_tailp;
9676 + mptsas_tx_waitqueue_t *txwq;
9677 + int i;
9678 +
9679 + clist = NULL;
9680 + tailp = &clist;
9681 +
9682 + for (i = 0; i < NUM_TX_WAITQ; i++) {
9683 + txwq = &mpt->m_tx_waitq[i];
9684 + mutex_enter(&txwq->txwq_mutex);
9685 + prev_tailp = &txwq->txwq_cmdq;
9686 + cmd = txwq->txwq_cmdq;
9687 + while (cmd != NULL) {
9688 + if (Tgt(cmd) == target &&
9689 + (lun == -1 || (Lun(cmd) == lun))) {
9690 + *prev_tailp = cmd->cmd_linkp;
9691 + *tailp = cmd;
9692 + tailp = &cmd->cmd_linkp;
9693 + cmd = cmd->cmd_linkp;
9694 + *tailp = NULL;
9695 + } else {
9696 + prev_tailp = &cmd->cmd_linkp;
9697 + cmd = cmd->cmd_linkp;
9698 + }
9699 + }
9700 + txwq->txwq_qtail = prev_tailp;
9701 + mutex_exit(&txwq->txwq_mutex);
9702 + }
9703 + return (clist);
9704 +}
9705 +
8569 9706 /*
8570 9707 * Clean up from a device reset.
8571 9708 * For the case of target reset, this function clears the waitq of all
8572 9709 * commands for a particular target. For the case of abort task set, this
8573 9710 * function clears the waitq of all commonds for a particular target/lun.
8574 9711 */
8575 9712 static void
8576 9713 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
8577 9714 {
8578 9715 mptsas_slots_t *slots = mpt->m_active;
8579 9716 mptsas_cmd_t *cmd, *next_cmd;
8580 9717 int slot;
8581 9718 uchar_t reason;
8582 9719 uint_t stat;
9720 + hrtime_t timestamp;
8583 9721
8584 9722 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
8585 9723
9724 + timestamp = gethrtime();
9725 +
8586 9726 /*
8587 9727 * Make sure the I/O Controller has flushed all cmds
8588 9728 * that are associated with this target for a target reset
8589 9729 * and target/lun for abort task set.
8590 9730 * Account for TM requests, which use the last SMID.
8591 9731 */
8592 9732 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
8593 9733 if ((cmd = slots->m_slot[slot]) == NULL)
8594 9734 continue;
8595 9735 reason = CMD_RESET;
8596 9736 stat = STAT_DEV_RESET;
8597 9737 switch (tasktype) {
8598 9738 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
8599 9739 if (Tgt(cmd) == target) {
9740 + if (cmd->cmd_active_expiration <= timestamp) {
9741 + /*
9742 + * When timeout requested, propagate
9743 + * proper reason and statistics to
9744 + * target drivers.
9745 + */
9746 + reason = CMD_TIMEOUT;
9747 + stat |= STAT_TIMEOUT;
9748 + }
8600 9749 NDBG25(("mptsas_flush_target discovered non-"
8601 9750 "NULL cmd in slot %d, tasktype 0x%x", slot,
8602 9751 tasktype));
8603 9752 mptsas_dump_cmd(mpt, cmd);
8604 9753 mptsas_remove_cmd(mpt, cmd);
8605 9754 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
8606 9755 mptsas_doneq_add(mpt, cmd);
8607 9756 }
8608 9757 break;
8609 9758 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
8610 9759 reason = CMD_ABORTED;
8611 9760 stat = STAT_ABORTED;
8612 9761 /*FALLTHROUGH*/
8613 9762 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
8614 9763 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9764 + if (cmd->cmd_active_expiration <= timestamp) {
9765 + stat |= STAT_TIMEOUT;
9766 + }
8615 9767
8616 9768 NDBG25(("mptsas_flush_target discovered non-"
8617 9769 "NULL cmd in slot %d, tasktype 0x%x", slot,
8618 9770 tasktype));
8619 9771 mptsas_dump_cmd(mpt, cmd);
8620 9772 mptsas_remove_cmd(mpt, cmd);
8621 - mptsas_set_pkt_reason(mpt, cmd, reason,
8622 - stat);
9773 + mptsas_set_pkt_reason(mpt, cmd, reason, stat);
8623 9774 mptsas_doneq_add(mpt, cmd);
8624 9775 }
8625 9776 break;
8626 9777 default:
8627 9778 break;
8628 9779 }
8629 9780 }
8630 9781
8631 9782 /*
8632 9783 * Flush the waitq and tx_waitq of this target's cmds
8633 9784 */
8634 9785 cmd = mpt->m_waitq;
8635 9786
8636 9787 reason = CMD_RESET;
8637 9788 stat = STAT_DEV_RESET;
8638 9789
8639 9790 switch (tasktype) {
8640 9791 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
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8641 9792 while (cmd != NULL) {
8642 9793 next_cmd = cmd->cmd_linkp;
8643 9794 if (Tgt(cmd) == target) {
8644 9795 mptsas_waitq_delete(mpt, cmd);
8645 9796 mptsas_set_pkt_reason(mpt, cmd,
8646 9797 reason, stat);
8647 9798 mptsas_doneq_add(mpt, cmd);
8648 9799 }
8649 9800 cmd = next_cmd;
8650 9801 }
8651 - mutex_enter(&mpt->m_tx_waitq_mutex);
8652 - cmd = mpt->m_tx_waitq;
9802 + cmd = mptsas_strip_targetlun_from_txwqs(mpt, target, -1);
8653 9803 while (cmd != NULL) {
8654 9804 next_cmd = cmd->cmd_linkp;
8655 - if (Tgt(cmd) == target) {
8656 - mptsas_tx_waitq_delete(mpt, cmd);
8657 - mutex_exit(&mpt->m_tx_waitq_mutex);
8658 - mptsas_set_pkt_reason(mpt, cmd,
8659 - reason, stat);
8660 - mptsas_doneq_add(mpt, cmd);
8661 - mutex_enter(&mpt->m_tx_waitq_mutex);
8662 - }
9805 + mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9806 + mptsas_doneq_add(mpt, cmd);
8663 9807 cmd = next_cmd;
8664 9808 }
8665 - mutex_exit(&mpt->m_tx_waitq_mutex);
8666 9809 break;
8667 9810 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
8668 9811 reason = CMD_ABORTED;
8669 9812 stat = STAT_ABORTED;
8670 9813 /*FALLTHROUGH*/
8671 9814 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
8672 9815 while (cmd != NULL) {
8673 9816 next_cmd = cmd->cmd_linkp;
8674 9817 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8675 9818 mptsas_waitq_delete(mpt, cmd);
8676 9819 mptsas_set_pkt_reason(mpt, cmd,
8677 9820 reason, stat);
8678 9821 mptsas_doneq_add(mpt, cmd);
8679 9822 }
8680 9823 cmd = next_cmd;
8681 9824 }
8682 - mutex_enter(&mpt->m_tx_waitq_mutex);
8683 - cmd = mpt->m_tx_waitq;
9825 + cmd = mptsas_strip_targetlun_from_txwqs(mpt, target, lun);
8684 9826 while (cmd != NULL) {
8685 9827 next_cmd = cmd->cmd_linkp;
8686 - if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8687 - mptsas_tx_waitq_delete(mpt, cmd);
8688 - mutex_exit(&mpt->m_tx_waitq_mutex);
8689 - mptsas_set_pkt_reason(mpt, cmd,
8690 - reason, stat);
8691 - mptsas_doneq_add(mpt, cmd);
8692 - mutex_enter(&mpt->m_tx_waitq_mutex);
8693 - }
9828 + mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9829 + mptsas_doneq_add(mpt, cmd);
8694 9830 cmd = next_cmd;
8695 9831 }
8696 - mutex_exit(&mpt->m_tx_waitq_mutex);
8697 9832 break;
8698 9833 default:
8699 9834 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
8700 9835 tasktype);
8701 9836 break;
8702 9837 }
8703 9838 }
8704 9839
8705 9840 /*
8706 9841 * Clean up hba state, abort all outstanding command and commands in waitq
8707 9842 * reset timeout of all targets.
8708 9843 */
8709 9844 static void
8710 9845 mptsas_flush_hba(mptsas_t *mpt)
8711 9846 {
8712 9847 mptsas_slots_t *slots = mpt->m_active;
8713 - mptsas_cmd_t *cmd;
8714 - int slot;
9848 + mptsas_cmd_t *cmd, *ncmd;
9849 + int slot, i;
8715 9850
8716 9851 NDBG25(("mptsas_flush_hba"));
8717 9852
8718 9853 /*
8719 9854 * The I/O Controller should have already sent back
8720 9855 * all commands via the scsi I/O reply frame. Make
8721 9856 * sure all commands have been flushed.
8722 9857 * Account for TM request, which use the last SMID.
8723 9858 */
8724 9859 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
8725 9860 if ((cmd = slots->m_slot[slot]) == NULL)
8726 9861 continue;
8727 9862
8728 9863 if (cmd->cmd_flags & CFLAG_CMDIOC) {
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8729 9864 /*
8730 9865 * Need to make sure to tell everyone that might be
8731 9866 * waiting on this command that it's going to fail. If
8732 9867 * we get here, this command will never timeout because
8733 9868 * the active command table is going to be re-allocated,
8734 9869 * so there will be nothing to check against a time out.
8735 9870 * Instead, mark the command as failed due to reset.
8736 9871 */
8737 9872 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
8738 9873 STAT_BUS_RESET);
8739 - if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
8740 - (cmd->cmd_flags & CFLAG_CONFIG) ||
8741 - (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9874 + if ((cmd->cmd_flags &
9875 + (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
8742 9876 cmd->cmd_flags |= CFLAG_FINISHED;
8743 9877 cv_broadcast(&mpt->m_passthru_cv);
8744 9878 cv_broadcast(&mpt->m_config_cv);
8745 9879 cv_broadcast(&mpt->m_fw_diag_cv);
8746 9880 }
8747 9881 continue;
8748 9882 }
8749 9883
8750 9884 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
8751 9885 slot));
8752 9886 mptsas_dump_cmd(mpt, cmd);
8753 9887
8754 9888 mptsas_remove_cmd(mpt, cmd);
8755 9889 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8756 9890 mptsas_doneq_add(mpt, cmd);
8757 9891 }
8758 9892
8759 9893 /*
8760 9894 * Flush the waitq.
8761 9895 */
8762 9896 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
8763 9897 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8764 9898 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
8765 9899 (cmd->cmd_flags & CFLAG_CONFIG) ||
8766 9900 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
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8767 9901 cmd->cmd_flags |= CFLAG_FINISHED;
8768 9902 cv_broadcast(&mpt->m_passthru_cv);
8769 9903 cv_broadcast(&mpt->m_config_cv);
8770 9904 cv_broadcast(&mpt->m_fw_diag_cv);
8771 9905 } else {
8772 9906 mptsas_doneq_add(mpt, cmd);
8773 9907 }
8774 9908 }
8775 9909
8776 9910 /*
8777 - * Flush the tx_waitq
9911 + * Flush the tx_waitqs
8778 9912 */
8779 - mutex_enter(&mpt->m_tx_waitq_mutex);
8780 - while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) {
8781 - mutex_exit(&mpt->m_tx_waitq_mutex);
8782 - mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8783 - mptsas_doneq_add(mpt, cmd);
8784 - mutex_enter(&mpt->m_tx_waitq_mutex);
9913 + for (i = 0; i < NUM_TX_WAITQ; i++) {
9914 + mutex_enter(&mpt->m_tx_waitq[i].txwq_mutex);
9915 + cmd = mpt->m_tx_waitq[i].txwq_cmdq;
9916 + mpt->m_tx_waitq[i].txwq_cmdq = NULL;
9917 + mpt->m_tx_waitq[i].txwq_qtail = &mpt->m_tx_waitq[i].txwq_cmdq;
9918 + mutex_exit(&mpt->m_tx_waitq[i].txwq_mutex);
9919 + while (cmd != NULL) {
9920 + ncmd = cmd->cmd_linkp;
9921 + mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
9922 + STAT_BUS_RESET);
9923 + mptsas_doneq_add(mpt, cmd);
9924 + cmd = ncmd;
9925 + }
8785 9926 }
8786 - mutex_exit(&mpt->m_tx_waitq_mutex);
8787 9927
8788 9928 /*
8789 9929 * Drain the taskqs prior to reallocating resources.
8790 9930 */
8791 9931 mutex_exit(&mpt->m_mutex);
8792 9932 ddi_taskq_wait(mpt->m_event_taskq);
8793 9933 ddi_taskq_wait(mpt->m_dr_taskq);
8794 9934 mutex_enter(&mpt->m_mutex);
8795 9935 }
8796 9936
8797 9937 /*
8798 9938 * set pkt_reason and OR in pkt_statistics flag
8799 9939 */
8800 9940 static void
8801 9941 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
8802 9942 uint_t stat)
8803 9943 {
8804 9944 #ifndef __lock_lint
8805 9945 _NOTE(ARGUNUSED(mpt))
8806 9946 #endif
8807 9947
8808 9948 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
8809 9949 (void *)cmd, reason, stat));
8810 9950
8811 9951 if (cmd) {
8812 9952 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
8813 9953 cmd->cmd_pkt->pkt_reason = reason;
8814 9954 }
8815 9955 cmd->cmd_pkt->pkt_statistics |= stat;
8816 9956 }
8817 9957 }
8818 9958
8819 9959 static void
8820 9960 mptsas_start_watch_reset_delay()
8821 9961 {
8822 9962 NDBG22(("mptsas_start_watch_reset_delay"));
8823 9963
8824 9964 mutex_enter(&mptsas_global_mutex);
8825 9965 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
8826 9966 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
8827 9967 drv_usectohz((clock_t)
8828 9968 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
8829 9969 ASSERT(mptsas_reset_watch != NULL);
8830 9970 }
8831 9971 mutex_exit(&mptsas_global_mutex);
8832 9972 }
8833 9973
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8834 9974 static void
8835 9975 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
8836 9976 {
8837 9977 mptsas_target_t *ptgt = NULL;
8838 9978
8839 9979 ASSERT(MUTEX_HELD(&mpt->m_mutex));
8840 9980
8841 9981 NDBG22(("mptsas_setup_bus_reset_delay"));
8842 9982 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
8843 9983 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9984 + mutex_enter(&ptgt->m_t_mutex);
8844 9985 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
8845 9986 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
9987 + mutex_exit(&ptgt->m_t_mutex);
8846 9988 }
8847 9989
8848 9990 mptsas_start_watch_reset_delay();
8849 9991 }
8850 9992
8851 9993 /*
8852 9994 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
8853 9995 * mpt instance for active reset delays
8854 9996 */
8855 9997 static void
8856 9998 mptsas_watch_reset_delay(void *arg)
8857 9999 {
8858 10000 #ifndef __lock_lint
8859 10001 _NOTE(ARGUNUSED(arg))
8860 10002 #endif
8861 10003
8862 10004 mptsas_t *mpt;
8863 10005 int not_done = 0;
8864 10006
8865 10007 NDBG22(("mptsas_watch_reset_delay"));
8866 10008
8867 10009 mutex_enter(&mptsas_global_mutex);
8868 10010 mptsas_reset_watch = 0;
8869 10011 mutex_exit(&mptsas_global_mutex);
8870 10012 rw_enter(&mptsas_global_rwlock, RW_READER);
8871 10013 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
8872 10014 if (mpt->m_tran == 0) {
8873 10015 continue;
8874 10016 }
8875 10017 mutex_enter(&mpt->m_mutex);
8876 10018 not_done += mptsas_watch_reset_delay_subr(mpt);
8877 10019 mutex_exit(&mpt->m_mutex);
8878 10020 }
8879 10021 rw_exit(&mptsas_global_rwlock);
8880 10022
8881 10023 if (not_done) {
8882 10024 mptsas_start_watch_reset_delay();
8883 10025 }
8884 10026 }
8885 10027
8886 10028 static int
8887 10029 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
8888 10030 {
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8889 10031 int done = 0;
8890 10032 int restart = 0;
8891 10033 mptsas_target_t *ptgt = NULL;
8892 10034
8893 10035 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
8894 10036
8895 10037 ASSERT(mutex_owned(&mpt->m_mutex));
8896 10038
8897 10039 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
8898 10040 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10041 + mutex_enter(&ptgt->m_t_mutex);
8899 10042 if (ptgt->m_reset_delay != 0) {
8900 10043 ptgt->m_reset_delay -=
8901 10044 MPTSAS_WATCH_RESET_DELAY_TICK;
8902 10045 if (ptgt->m_reset_delay <= 0) {
8903 10046 ptgt->m_reset_delay = 0;
8904 10047 mptsas_set_throttle(mpt, ptgt,
8905 10048 MAX_THROTTLE);
8906 10049 restart++;
8907 10050 } else {
8908 10051 done = -1;
8909 10052 }
8910 10053 }
10054 + mutex_exit(&ptgt->m_t_mutex);
8911 10055 }
8912 10056
8913 10057 if (restart > 0) {
8914 10058 mptsas_restart_hba(mpt);
8915 10059 }
8916 10060 return (done);
8917 10061 }
8918 10062
8919 10063 #ifdef MPTSAS_TEST
8920 10064 static void
8921 10065 mptsas_test_reset(mptsas_t *mpt, int target)
8922 10066 {
8923 10067 mptsas_target_t *ptgt = NULL;
8924 10068
8925 10069 if (mptsas_rtest == target) {
8926 10070 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
8927 10071 mptsas_rtest = -1;
8928 10072 }
8929 10073 if (mptsas_rtest == -1) {
8930 10074 NDBG22(("mptsas_test_reset success"));
8931 10075 }
8932 10076 }
8933 10077 }
8934 10078 #endif
8935 10079
8936 10080 /*
8937 10081 * abort handling:
8938 10082 *
8939 10083 * Notes:
8940 10084 * - if pkt is not NULL, abort just that command
8941 10085 * - if pkt is NULL, abort all outstanding commands for target
8942 10086 */
8943 10087 static int
8944 10088 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
8945 10089 {
8946 10090 mptsas_t *mpt = ADDR2MPT(ap);
8947 10091 int rval;
8948 10092 mptsas_tgt_private_t *tgt_private;
8949 10093 int target, lun;
8950 10094
8951 10095 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
8952 10096 tran_tgt_private;
8953 10097 ASSERT(tgt_private != NULL);
8954 10098 target = tgt_private->t_private->m_devhdl;
8955 10099 lun = tgt_private->t_lun;
8956 10100
8957 10101 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
8958 10102
8959 10103 mutex_enter(&mpt->m_mutex);
8960 10104 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
8961 10105 mutex_exit(&mpt->m_mutex);
8962 10106 return (rval);
8963 10107 }
8964 10108
8965 10109 static int
8966 10110 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
8967 10111 {
8968 10112 mptsas_cmd_t *sp = NULL;
8969 10113 mptsas_slots_t *slots = mpt->m_active;
8970 10114 int rval = FALSE;
8971 10115
8972 10116 ASSERT(mutex_owned(&mpt->m_mutex));
8973 10117
8974 10118 /*
8975 10119 * Abort the command pkt on the target/lun in ap. If pkt is
8976 10120 * NULL, abort all outstanding commands on that target/lun.
8977 10121 * If you can abort them, return 1, else return 0.
8978 10122 * Each packet that's aborted should be sent back to the target
8979 10123 * driver through the callback routine, with pkt_reason set to
8980 10124 * CMD_ABORTED.
8981 10125 *
8982 10126 * abort cmd pkt on HBA hardware; clean out of outstanding
8983 10127 * command lists, etc.
8984 10128 */
8985 10129 if (pkt != NULL) {
8986 10130 /* abort the specified packet */
8987 10131 sp = PKT2CMD(pkt);
8988 10132
8989 10133 if (sp->cmd_queued) {
8990 10134 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
8991 10135 (void *)sp));
8992 10136 mptsas_waitq_delete(mpt, sp);
8993 10137 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
8994 10138 STAT_ABORTED);
8995 10139 mptsas_doneq_add(mpt, sp);
8996 10140 rval = TRUE;
8997 10141 goto done;
8998 10142 }
8999 10143
9000 10144 /*
9001 10145 * Have mpt firmware abort this command
9002 10146 */
9003 10147
9004 10148 if (slots->m_slot[sp->cmd_slot] != NULL) {
9005 10149 rval = mptsas_ioc_task_management(mpt,
9006 10150 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
9007 10151 lun, NULL, 0, 0);
9008 10152
9009 10153 /*
9010 10154 * The transport layer expects only TRUE and FALSE.
9011 10155 * Therefore, if mptsas_ioc_task_management returns
9012 10156 * FAILED we will return FALSE.
9013 10157 */
9014 10158 if (rval == FAILED)
9015 10159 rval = FALSE;
9016 10160 goto done;
9017 10161 }
9018 10162 }
9019 10163
9020 10164 /*
9021 10165 * If pkt is NULL then abort task set
9022 10166 */
9023 10167 rval = mptsas_ioc_task_management(mpt,
9024 10168 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
9025 10169
9026 10170 /*
9027 10171 * The transport layer expects only TRUE and FALSE.
9028 10172 * Therefore, if mptsas_ioc_task_management returns
9029 10173 * FAILED we will return FALSE.
9030 10174 */
9031 10175 if (rval == FAILED)
9032 10176 rval = FALSE;
9033 10177
9034 10178 #ifdef MPTSAS_TEST
9035 10179 if (rval && mptsas_test_stop) {
9036 10180 debug_enter("mptsas_do_scsi_abort");
9037 10181 }
9038 10182 #endif
9039 10183
9040 10184 done:
9041 10185 mptsas_doneq_empty(mpt);
9042 10186 return (rval);
9043 10187 }
9044 10188
9045 10189 /*
9046 10190 * capability handling:
9047 10191 * (*tran_getcap). Get the capability named, and return its value.
9048 10192 */
9049 10193 static int
9050 10194 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
9051 10195 {
9052 10196 mptsas_t *mpt = ADDR2MPT(ap);
9053 10197 int ckey;
9054 10198 int rval = FALSE;
9055 10199
9056 10200 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
9057 10201 ap->a_target, cap, tgtonly));
9058 10202
9059 10203 mutex_enter(&mpt->m_mutex);
9060 10204
9061 10205 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9062 10206 mutex_exit(&mpt->m_mutex);
9063 10207 return (UNDEFINED);
9064 10208 }
9065 10209
9066 10210 switch (ckey) {
9067 10211 case SCSI_CAP_DMA_MAX:
9068 10212 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9069 10213 break;
9070 10214 case SCSI_CAP_ARQ:
9071 10215 rval = TRUE;
9072 10216 break;
9073 10217 case SCSI_CAP_MSG_OUT:
9074 10218 case SCSI_CAP_PARITY:
9075 10219 case SCSI_CAP_UNTAGGED_QING:
9076 10220 rval = TRUE;
9077 10221 break;
9078 10222 case SCSI_CAP_TAGGED_QING:
9079 10223 rval = TRUE;
9080 10224 break;
9081 10225 case SCSI_CAP_RESET_NOTIFICATION:
9082 10226 rval = TRUE;
9083 10227 break;
9084 10228 case SCSI_CAP_LINKED_CMDS:
9085 10229 rval = FALSE;
9086 10230 break;
9087 10231 case SCSI_CAP_QFULL_RETRIES:
9088 10232 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9089 10233 tran_tgt_private))->t_private->m_qfull_retries;
9090 10234 break;
9091 10235 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9092 10236 rval = drv_hztousec(((mptsas_tgt_private_t *)
9093 10237 (ap->a_hba_tran->tran_tgt_private))->
9094 10238 t_private->m_qfull_retry_interval) / 1000;
9095 10239 break;
9096 10240 case SCSI_CAP_CDB_LEN:
9097 10241 rval = CDB_GROUP4;
9098 10242 break;
9099 10243 case SCSI_CAP_INTERCONNECT_TYPE:
9100 10244 rval = INTERCONNECT_SAS;
9101 10245 break;
9102 10246 case SCSI_CAP_TRAN_LAYER_RETRIES:
9103 10247 if (mpt->m_ioc_capabilities &
9104 10248 MPI2_IOCFACTS_CAPABILITY_TLR)
9105 10249 rval = TRUE;
9106 10250 else
9107 10251 rval = FALSE;
9108 10252 break;
9109 10253 default:
9110 10254 rval = UNDEFINED;
9111 10255 break;
9112 10256 }
9113 10257
9114 10258 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9115 10259
9116 10260 mutex_exit(&mpt->m_mutex);
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9117 10261 return (rval);
9118 10262 }
9119 10263
9120 10264 /*
9121 10265 * (*tran_setcap). Set the capability named to the value given.
9122 10266 */
9123 10267 static int
9124 10268 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9125 10269 {
9126 10270 mptsas_t *mpt = ADDR2MPT(ap);
10271 + mptsas_target_t *ptgt;
9127 10272 int ckey;
9128 10273 int rval = FALSE;
9129 10274
9130 10275 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9131 10276 ap->a_target, cap, value, tgtonly));
9132 10277
9133 10278 if (!tgtonly) {
9134 10279 return (rval);
9135 10280 }
9136 10281
9137 10282 mutex_enter(&mpt->m_mutex);
9138 10283
9139 10284 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9140 10285 mutex_exit(&mpt->m_mutex);
9141 10286 return (UNDEFINED);
9142 10287 }
9143 10288
9144 10289 switch (ckey) {
9145 10290 case SCSI_CAP_DMA_MAX:
9146 10291 case SCSI_CAP_MSG_OUT:
9147 10292 case SCSI_CAP_PARITY:
9148 10293 case SCSI_CAP_INITIATOR_ID:
9149 10294 case SCSI_CAP_LINKED_CMDS:
9150 10295 case SCSI_CAP_UNTAGGED_QING:
9151 10296 case SCSI_CAP_RESET_NOTIFICATION:
9152 10297 /*
9153 10298 * None of these are settable via
9154 10299 * the capability interface.
9155 10300 */
9156 10301 break;
9157 10302 case SCSI_CAP_ARQ:
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9158 10303 /*
9159 10304 * We cannot turn off arq so return false if asked to
9160 10305 */
9161 10306 if (value) {
9162 10307 rval = TRUE;
9163 10308 } else {
9164 10309 rval = FALSE;
9165 10310 }
9166 10311 break;
9167 10312 case SCSI_CAP_TAGGED_QING:
9168 - mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *)
9169 - (ap->a_hba_tran->tran_tgt_private))->t_private,
9170 - MAX_THROTTLE);
10313 + ptgt = ((mptsas_tgt_private_t *)
10314 + (ap->a_hba_tran->tran_tgt_private))->t_private;
10315 + mptsas_set_throttle_mtx(mpt, ptgt, MAX_THROTTLE);
9171 10316 rval = TRUE;
9172 10317 break;
9173 10318 case SCSI_CAP_QFULL_RETRIES:
9174 10319 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9175 10320 t_private->m_qfull_retries = (uchar_t)value;
9176 10321 rval = TRUE;
9177 10322 break;
9178 10323 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9179 10324 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9180 10325 t_private->m_qfull_retry_interval =
9181 10326 drv_usectohz(value * 1000);
9182 10327 rval = TRUE;
9183 10328 break;
9184 10329 default:
9185 10330 rval = UNDEFINED;
9186 10331 break;
9187 10332 }
9188 10333 mutex_exit(&mpt->m_mutex);
9189 10334 return (rval);
9190 10335 }
9191 10336
9192 10337 /*
9193 10338 * Utility routine for mptsas_ifsetcap/ifgetcap
9194 10339 */
9195 10340 /*ARGSUSED*/
9196 10341 static int
9197 10342 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9198 10343 {
9199 10344 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9200 10345
9201 10346 if (!cap)
9202 10347 return (FALSE);
9203 10348
9204 10349 *cidxp = scsi_hba_lookup_capstr(cap);
9205 10350 return (TRUE);
9206 10351 }
9207 10352
9208 10353 static int
9209 10354 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9210 10355 {
9211 10356 mptsas_slots_t *old_active = mpt->m_active;
9212 10357 mptsas_slots_t *new_active;
9213 10358 size_t size;
9214 10359
9215 10360 /*
9216 10361 * if there are active commands, then we cannot
9217 10362 * change size of active slots array.
9218 10363 */
9219 10364 ASSERT(mpt->m_ncmds == 0);
9220 10365
9221 10366 size = MPTSAS_SLOTS_SIZE(mpt);
9222 10367 new_active = kmem_zalloc(size, flag);
9223 10368 if (new_active == NULL) {
9224 10369 NDBG1(("new active alloc failed"));
9225 10370 return (-1);
9226 10371 }
9227 10372 /*
9228 10373 * Since SMID 0 is reserved and the TM slot is reserved, the
9229 10374 * number of slots that can be used at any one time is
9230 10375 * m_max_requests - 2.
9231 10376 */
9232 10377 new_active->m_n_normal = (mpt->m_max_requests - 2);
9233 10378 new_active->m_size = size;
9234 10379 new_active->m_rotor = 1;
9235 10380 if (old_active)
9236 10381 mptsas_free_active_slots(mpt);
9237 10382 mpt->m_active = new_active;
9238 10383
9239 10384 return (0);
9240 10385 }
9241 10386
9242 10387 static void
9243 10388 mptsas_free_active_slots(mptsas_t *mpt)
9244 10389 {
9245 10390 mptsas_slots_t *active = mpt->m_active;
9246 10391 size_t size;
9247 10392
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9248 10393 if (active == NULL)
9249 10394 return;
9250 10395 size = active->m_size;
9251 10396 kmem_free(active, size);
9252 10397 mpt->m_active = NULL;
9253 10398 }
9254 10399
9255 10400 /*
9256 10401 * Error logging, printing, and debug print routines.
9257 10402 */
9258 -static char *mptsas_label = "mpt_sas";
10403 +static char *mptsas_label = "mpt_sas3";
9259 10404
9260 10405 /*PRINTFLIKE3*/
9261 10406 void
9262 10407 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
9263 10408 {
9264 10409 dev_info_t *dev;
9265 10410 va_list ap;
9266 10411
9267 10412 if (mpt) {
9268 10413 dev = mpt->m_dip;
9269 10414 } else {
9270 10415 dev = 0;
9271 10416 }
9272 10417
9273 10418 mutex_enter(&mptsas_log_mutex);
9274 10419
9275 10420 va_start(ap, fmt);
9276 10421 (void) vsprintf(mptsas_log_buf, fmt, ap);
9277 10422 va_end(ap);
9278 10423
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9279 10424 if (level == CE_CONT) {
9280 10425 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
9281 10426 } else {
9282 10427 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
9283 10428 }
9284 10429
9285 10430 mutex_exit(&mptsas_log_mutex);
9286 10431 }
9287 10432
9288 10433 #ifdef MPTSAS_DEBUG
10434 +/*
10435 + * Use a circular buffer to log messages to private memory.
10436 + * No mutexes, so there is the opportunity for this to miss lines.
10437 + * But it's fast and does not hold up the proceedings too much.
10438 + */
10439 +static char mptsas_dbglog_bufs[32][256];
10440 +static uint32_t mptsas_dbglog_idx = 1;
10441 +
10442 +/*PRINTFLIKE1*/
10443 +void
10444 +mptsas_debug_log(char *fmt, ...)
10445 +{
10446 + va_list ap;
10447 + uint32_t idx;
10448 +
10449 + if (!mptsas_dbglog_idx) {
10450 + return;
10451 + }
10452 + idx = (mptsas_dbglog_idx++) & 0x1f;
10453 +
10454 + va_start(ap, fmt);
10455 + (void) vsnprintf(mptsas_dbglog_bufs[idx],
10456 + sizeof (mptsas_dbglog_bufs[0]), fmt, ap);
10457 + va_end(ap);
10458 +}
10459 +
9289 10460 /*PRINTFLIKE1*/
9290 10461 void
9291 10462 mptsas_printf(char *fmt, ...)
9292 10463 {
9293 10464 dev_info_t *dev = 0;
9294 10465 va_list ap;
9295 10466
9296 10467 mutex_enter(&mptsas_log_mutex);
9297 10468
9298 10469 va_start(ap, fmt);
9299 10470 (void) vsprintf(mptsas_log_buf, fmt, ap);
9300 10471 va_end(ap);
9301 10472
9302 10473 #ifdef PROM_PRINTF
9303 10474 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
9304 10475 #else
9305 - scsi_log(dev, mptsas_label, SCSI_DEBUG, "%s\n", mptsas_log_buf);
10476 + scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf);
9306 10477 #endif
9307 10478 mutex_exit(&mptsas_log_mutex);
9308 10479 }
9309 10480 #endif
9310 10481
9311 10482 /*
9312 10483 * timeout handling
9313 10484 */
9314 10485 static void
9315 10486 mptsas_watch(void *arg)
9316 10487 {
9317 10488 #ifndef __lock_lint
9318 10489 _NOTE(ARGUNUSED(arg))
9319 10490 #endif
9320 10491
9321 10492 mptsas_t *mpt;
9322 10493 uint32_t doorbell;
9323 10494
9324 10495 NDBG30(("mptsas_watch"));
9325 10496
9326 10497 rw_enter(&mptsas_global_rwlock, RW_READER);
9327 10498 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
9328 10499
9329 10500 mutex_enter(&mpt->m_mutex);
9330 10501
9331 10502 /* Skip device if not powered on */
9332 10503 if (mpt->m_options & MPTSAS_OPT_PM) {
9333 10504 if (mpt->m_power_level == PM_LEVEL_D0) {
9334 10505 (void) pm_busy_component(mpt->m_dip, 0);
9335 10506 mpt->m_busy = 1;
9336 10507 } else {
9337 10508 mutex_exit(&mpt->m_mutex);
9338 10509 continue;
9339 10510 }
9340 10511 }
9341 10512
9342 10513 /*
9343 10514 * Check if controller is in a FAULT state. If so, reset it.
9344 10515 */
9345 10516 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
9346 10517 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
9347 10518 doorbell &= MPI2_DOORBELL_DATA_MASK;
9348 10519 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
9349 10520 "code: %04x", doorbell);
9350 10521 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
9351 10522 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
9352 10523 mptsas_log(mpt, CE_WARN, "Reset failed"
9353 10524 "after fault was detected");
9354 10525 }
9355 10526 }
9356 10527
9357 10528 /*
9358 10529 * For now, always call mptsas_watchsubr.
9359 10530 */
9360 10531 mptsas_watchsubr(mpt);
9361 10532
9362 10533 if (mpt->m_options & MPTSAS_OPT_PM) {
9363 10534 mpt->m_busy = 0;
9364 10535 (void) pm_idle_component(mpt->m_dip, 0);
9365 10536 }
9366 10537
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9367 10538 mutex_exit(&mpt->m_mutex);
9368 10539 }
9369 10540 rw_exit(&mptsas_global_rwlock);
9370 10541
9371 10542 mutex_enter(&mptsas_global_mutex);
9372 10543 if (mptsas_timeouts_enabled)
9373 10544 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
9374 10545 mutex_exit(&mptsas_global_mutex);
9375 10546 }
9376 10547
10548 +int mptsas_monitor_for_txwqs = 1;
9377 10549 static void
9378 10550 mptsas_watchsubr(mptsas_t *mpt)
9379 10551 {
9380 10552 int i;
9381 10553 mptsas_cmd_t *cmd;
9382 10554 mptsas_target_t *ptgt = NULL;
10555 + hrtime_t timestamp = gethrtime();
10556 + boolean_t restart_hba = B_FALSE;
9383 10557
9384 10558 ASSERT(MUTEX_HELD(&mpt->m_mutex));
9385 10559
9386 - NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
10560 + NDBG30(("mptsas_watchsubr: mpt=0x%p, ncmds %d, nstarted %d",
10561 + (void *)mpt, mpt->m_ncmds, mpt->m_ncstarted));
9387 10562
9388 -#ifdef MPTSAS_TEST
9389 - if (mptsas_enable_untagged) {
9390 - mptsas_test_untagged++;
10563 + mpt->m_lncstarted = mpt->m_ncstarted;
10564 + if (mpt->m_txwq_thread_n != 0 && mpt->m_txwq_enabled != BLOCKED &&
10565 + mptsas_monitor_for_txwqs) {
10566 + i = mpt->m_ncstarted/mptsas_scsi_watchdog_tick;
10567 + if (i > mpt->m_txwq_thread_threshold) {
10568 + mpt->m_txwq_enabled = TRUE;
10569 + } else if (i < (mpt->m_txwq_thread_threshold>>1)) {
10570 + mpt->m_txwq_enabled = FALSE;
10571 + }
9391 10572 }
9392 -#endif
10573 + mpt->m_ncstarted = 0;
9393 10574
9394 10575 /*
9395 10576 * Check for commands stuck in active slot
9396 10577 * Account for TM requests, which use the last SMID.
9397 10578 */
9398 10579 for (i = 0; i <= mpt->m_active->m_n_normal; i++) {
9399 10580 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
9400 - if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
9401 - cmd->cmd_active_timeout -=
9402 - mptsas_scsi_watchdog_tick;
9403 - if (cmd->cmd_active_timeout <= 0) {
10581 + if (cmd->cmd_active_expiration <= timestamp) {
10582 + if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
9404 10583 /*
9405 10584 * There seems to be a command stuck
9406 10585 * in the active slot. Drain throttle.
9407 10586 */
9408 - mptsas_set_throttle(mpt,
9409 - cmd->cmd_tgt_addr,
10587 + ptgt = cmd->cmd_tgt_addr;
10588 + mptsas_set_throttle_mtx(mpt, ptgt,
9410 10589 DRAIN_THROTTLE);
9411 - }
9412 - }
9413 - if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9414 - (cmd->cmd_flags & CFLAG_CONFIG) ||
9415 - (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9416 - cmd->cmd_active_timeout -=
9417 - mptsas_scsi_watchdog_tick;
9418 - if (cmd->cmd_active_timeout <= 0) {
10590 + } else if (cmd->cmd_flags &
10591 + (CFLAG_PASSTHRU | CFLAG_CONFIG |
10592 + CFLAG_FW_DIAG)) {
9419 10593 /*
9420 10594 * passthrough command timeout
9421 10595 */
9422 10596 cmd->cmd_flags |= (CFLAG_FINISHED |
9423 10597 CFLAG_TIMEOUT);
9424 10598 cv_broadcast(&mpt->m_passthru_cv);
9425 10599 cv_broadcast(&mpt->m_config_cv);
9426 10600 cv_broadcast(&mpt->m_fw_diag_cv);
9427 10601 }
9428 10602 }
9429 10603 }
9430 10604 }
9431 10605
9432 10606 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9433 10607 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10608 + mutex_enter(&ptgt->m_t_mutex);
9434 10609 /*
9435 10610 * If we were draining due to a qfull condition,
9436 10611 * go back to full throttle.
9437 10612 */
9438 10613 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
9439 10614 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
9440 10615 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
9441 10616 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9442 - mptsas_restart_hba(mpt);
10617 + restart_hba = B_TRUE;
9443 10618 }
9444 10619
9445 - if ((ptgt->m_t_ncmds > 0) &&
9446 - (ptgt->m_timebase)) {
9447 -
9448 - if (ptgt->m_timebase <=
9449 - mptsas_scsi_watchdog_tick) {
9450 - ptgt->m_timebase +=
9451 - mptsas_scsi_watchdog_tick;
9452 - continue;
9453 - }
10620 + cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq);
10621 + if (cmd != NULL) {
10622 + if (cmd->cmd_active_expiration <= timestamp) {
10623 + /*
10624 + * Earliest command timeout expired.
10625 + * Drain throttle.
10626 + */
10627 + mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
9454 10628
9455 - ptgt->m_timeout -= mptsas_scsi_watchdog_tick;
10629 + /*
10630 + * Check for remaining commands.
10631 + */
10632 + cmd = TAILQ_FIRST(&ptgt->m_active_cmdq);
10633 + if (cmd->cmd_active_expiration > timestamp) {
10634 + /*
10635 + * Wait for remaining commands to
10636 + * complete or time out.
10637 + */
10638 + NDBG23(("command timed out, "
10639 + "pending drain"));
10640 + } else {
10641 + mutex_exit(&ptgt->m_t_mutex);
9456 10642
9457 - if (ptgt->m_timeout < 0) {
9458 - mptsas_cmd_timeout(mpt, ptgt->m_devhdl);
9459 - continue;
9460 - }
10643 + /*
10644 + * All command timeouts expired.
10645 + */
10646 + mptsas_log(mpt, CE_NOTE,
10647 + "Timeout of %d seconds "
10648 + "expired with %d commands on "
10649 + "target %d lun %d.",
10650 + cmd->cmd_pkt->pkt_time,
10651 + ptgt->m_t_ncmds,
10652 + ptgt->m_devhdl, Lun(cmd));
9461 10653
9462 - if ((ptgt->m_timeout) <=
9463 - mptsas_scsi_watchdog_tick) {
10654 + mptsas_cmd_timeout(mpt, ptgt);
10655 + continue;
10656 + }
10657 + } else if (cmd->cmd_active_expiration <= timestamp +
10658 + (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) {
9464 10659 NDBG23(("pending timeout"));
9465 - mptsas_set_throttle(mpt, ptgt,
9466 - DRAIN_THROTTLE);
10660 + mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
9467 10661 }
9468 10662 }
10663 + mutex_exit(&ptgt->m_t_mutex);
10664 + }
10665 + if (restart_hba == B_TRUE) {
10666 + mptsas_restart_hba(mpt);
9469 10667 }
9470 10668 }
9471 10669
9472 10670 /*
9473 10671 * timeout recovery
9474 10672 */
9475 10673 static void
9476 -mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl)
10674 +mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt)
9477 10675 {
10676 + uint16_t devhdl;
10677 + uint64_t sas_wwn;
10678 + uint8_t phy;
10679 + char wwn_str[MPTSAS_WWN_STRLEN];
10680 +
10681 + devhdl = ptgt->m_devhdl;
10682 + sas_wwn = ptgt->m_addr.mta_wwn;
10683 + phy = ptgt->m_phynum;
10684 + if (sas_wwn == 0) {
10685 + (void) sprintf(wwn_str, "p%x", phy);
10686 + } else {
10687 + (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
10688 + }
9478 10689
9479 10690 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
9480 10691 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
9481 - "Target %d", devhdl);
10692 + "target %d %s, enclosure %u .", devhdl, wwn_str,
10693 + ptgt->m_enclosure);
9482 10694
9483 10695 /*
9484 - * If the current target is not the target passed in,
9485 - * try to reset that target.
10696 + * Abort all outstanding commands on the device.
9486 10697 */
9487 10698 NDBG29(("mptsas_cmd_timeout: device reset"));
9488 10699 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
9489 10700 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
9490 10701 "recovery failed!", devhdl);
9491 10702 }
9492 10703 }
9493 10704
9494 10705 /*
9495 10706 * Device / Hotplug control
9496 10707 */
9497 10708 static int
9498 10709 mptsas_scsi_quiesce(dev_info_t *dip)
9499 10710 {
9500 10711 mptsas_t *mpt;
9501 10712 scsi_hba_tran_t *tran;
9502 10713
9503 10714 tran = ddi_get_driver_private(dip);
9504 10715 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
9505 10716 return (-1);
9506 10717
9507 10718 return (mptsas_quiesce_bus(mpt));
9508 10719 }
9509 10720
9510 10721 static int
9511 10722 mptsas_scsi_unquiesce(dev_info_t *dip)
9512 10723 {
9513 10724 mptsas_t *mpt;
9514 10725 scsi_hba_tran_t *tran;
9515 10726
9516 10727 tran = ddi_get_driver_private(dip);
9517 10728 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
9518 10729 return (-1);
9519 10730
9520 10731 return (mptsas_unquiesce_bus(mpt));
9521 10732 }
9522 10733
9523 10734 static int
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9524 10735 mptsas_quiesce_bus(mptsas_t *mpt)
9525 10736 {
9526 10737 mptsas_target_t *ptgt = NULL;
9527 10738
9528 10739 NDBG28(("mptsas_quiesce_bus"));
9529 10740 mutex_enter(&mpt->m_mutex);
9530 10741
9531 10742 /* Set all the throttles to zero */
9532 10743 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9533 10744 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9534 - mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10745 + mptsas_set_throttle_mtx(mpt, ptgt, HOLD_THROTTLE);
9535 10746 }
9536 10747
9537 10748 /* If there are any outstanding commands in the queue */
9538 10749 if (mpt->m_ncmds) {
9539 10750 mpt->m_softstate |= MPTSAS_SS_DRAINING;
9540 10751 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
9541 10752 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
9542 10753 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
9543 10754 /*
9544 10755 * Quiesce has been interrupted
9545 10756 */
9546 10757 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
9547 10758 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9548 10759 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9549 - mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10760 + mptsas_set_throttle_mtx(mpt, ptgt,
10761 + MAX_THROTTLE);
9550 10762 }
9551 10763 mptsas_restart_hba(mpt);
9552 10764 if (mpt->m_quiesce_timeid != 0) {
9553 10765 timeout_id_t tid = mpt->m_quiesce_timeid;
9554 10766 mpt->m_quiesce_timeid = 0;
9555 10767 mutex_exit(&mpt->m_mutex);
9556 10768 (void) untimeout(tid);
9557 10769 return (-1);
9558 10770 }
9559 10771 mutex_exit(&mpt->m_mutex);
9560 10772 return (-1);
9561 10773 } else {
9562 10774 /* Bus has been quiesced */
9563 10775 ASSERT(mpt->m_quiesce_timeid == 0);
9564 10776 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
9565 10777 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
9566 10778 mutex_exit(&mpt->m_mutex);
9567 10779 return (0);
9568 10780 }
9569 10781 }
9570 10782 /* Bus was not busy - QUIESCED */
9571 10783 mutex_exit(&mpt->m_mutex);
9572 10784
9573 10785 return (0);
9574 10786 }
9575 10787
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9576 10788 static int
9577 10789 mptsas_unquiesce_bus(mptsas_t *mpt)
9578 10790 {
9579 10791 mptsas_target_t *ptgt = NULL;
9580 10792
9581 10793 NDBG28(("mptsas_unquiesce_bus"));
9582 10794 mutex_enter(&mpt->m_mutex);
9583 10795 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
9584 10796 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9585 10797 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9586 - mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10798 + mptsas_set_throttle_mtx(mpt, ptgt, MAX_THROTTLE);
9587 10799 }
9588 10800 mptsas_restart_hba(mpt);
9589 10801 mutex_exit(&mpt->m_mutex);
9590 10802 return (0);
9591 10803 }
9592 10804
9593 10805 static void
9594 10806 mptsas_ncmds_checkdrain(void *arg)
9595 10807 {
9596 10808 mptsas_t *mpt = arg;
9597 10809 mptsas_target_t *ptgt = NULL;
9598 10810
9599 10811 mutex_enter(&mpt->m_mutex);
9600 10812 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
9601 10813 mpt->m_quiesce_timeid = 0;
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9602 10814 if (mpt->m_ncmds == 0) {
9603 10815 /* Command queue has been drained */
9604 10816 cv_signal(&mpt->m_cv);
9605 10817 } else {
9606 10818 /*
9607 10819 * The throttle may have been reset because
9608 10820 * of a SCSI bus reset
9609 10821 */
9610 10822 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9611 10823 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9612 - mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10824 + mptsas_set_throttle_mtx(mpt, ptgt,
10825 + HOLD_THROTTLE);
9613 10826 }
9614 10827
9615 10828 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
9616 10829 mpt, (MPTSAS_QUIESCE_TIMEOUT *
9617 10830 drv_usectohz(1000000)));
9618 10831 }
9619 10832 }
9620 10833 mutex_exit(&mpt->m_mutex);
9621 10834 }
9622 10835
9623 10836 /*ARGSUSED*/
9624 10837 static void
9625 10838 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
9626 10839 {
9627 10840 int i;
9628 10841 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
9629 10842 char buf[128];
9630 10843
9631 10844 buf[0] = '\0';
9632 10845 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
9633 10846 Tgt(cmd), Lun(cmd)));
9634 10847 (void) sprintf(&buf[0], "\tcdb=[");
9635 10848 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
9636 10849 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
9637 10850 }
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9638 10851 (void) sprintf(&buf[strlen(buf)], " ]");
9639 10852 NDBG25(("?%s\n", buf));
9640 10853 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
9641 10854 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
9642 10855 cmd->cmd_pkt->pkt_state));
9643 10856 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
9644 10857 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
9645 10858 }
9646 10859
9647 10860 static void
10861 +mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10862 + pMpi2SGESimple64_t sgep)
10863 +{
10864 + uint32_t sge_flags;
10865 + uint32_t data_size, dataout_size;
10866 + ddi_dma_cookie_t data_cookie;
10867 + ddi_dma_cookie_t dataout_cookie;
10868 +
10869 + data_size = pt->data_size;
10870 + dataout_size = pt->dataout_size;
10871 + data_cookie = pt->data_cookie;
10872 + dataout_cookie = pt->dataout_cookie;
10873 +
10874 + if (dataout_size) {
10875 + sge_flags = dataout_size |
10876 + ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10877 + MPI2_SGE_FLAGS_END_OF_BUFFER |
10878 + MPI2_SGE_FLAGS_HOST_TO_IOC |
10879 + MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10880 + MPI2_SGE_FLAGS_SHIFT);
10881 + ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10882 + ddi_put32(acc_hdl, &sgep->Address.Low,
10883 + (uint32_t)(dataout_cookie.dmac_laddress & 0xffffffffull));
10884 + ddi_put32(acc_hdl, &sgep->Address.High,
10885 + (uint32_t)(dataout_cookie.dmac_laddress >> 32));
10886 + sgep++;
10887 + }
10888 + sge_flags = data_size;
10889 + sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10890 + MPI2_SGE_FLAGS_LAST_ELEMENT |
10891 + MPI2_SGE_FLAGS_END_OF_BUFFER |
10892 + MPI2_SGE_FLAGS_END_OF_LIST |
10893 + MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10894 + MPI2_SGE_FLAGS_SHIFT);
10895 + if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10896 + sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
10897 + MPI2_SGE_FLAGS_SHIFT);
10898 + } else {
10899 + sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
10900 + MPI2_SGE_FLAGS_SHIFT);
10901 + }
10902 + ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10903 + ddi_put32(acc_hdl, &sgep->Address.Low,
10904 + (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull));
10905 + ddi_put32(acc_hdl, &sgep->Address.High,
10906 + (uint32_t)(data_cookie.dmac_laddress >> 32));
10907 +}
10908 +
10909 +static void
10910 +mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10911 + pMpi2IeeeSgeSimple64_t ieeesgep)
10912 +{
10913 + uint8_t sge_flags;
10914 + uint32_t data_size, dataout_size;
10915 + ddi_dma_cookie_t data_cookie;
10916 + ddi_dma_cookie_t dataout_cookie;
10917 +
10918 + data_size = pt->data_size;
10919 + dataout_size = pt->dataout_size;
10920 + data_cookie = pt->data_cookie;
10921 + dataout_cookie = pt->dataout_cookie;
10922 +
10923 + sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
10924 + MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
10925 + if (dataout_size) {
10926 + ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size);
10927 + ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10928 + (uint32_t)(dataout_cookie.dmac_laddress &
10929 + 0xffffffffull));
10930 + ddi_put32(acc_hdl, &ieeesgep->Address.High,
10931 + (uint32_t)(dataout_cookie.dmac_laddress >> 32));
10932 + ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10933 + ieeesgep++;
10934 + }
10935 + sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
10936 + ddi_put32(acc_hdl, &ieeesgep->Length, data_size);
10937 + ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10938 + (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull));
10939 + ddi_put32(acc_hdl, &ieeesgep->Address.High,
10940 + (uint32_t)(data_cookie.dmac_laddress >> 32));
10941 + ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10942 +}
10943 +
10944 +static void
9648 10945 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
9649 10946 {
9650 10947 caddr_t memp;
9651 10948 pMPI2RequestHeader_t request_hdrp;
9652 10949 struct scsi_pkt *pkt = cmd->cmd_pkt;
9653 10950 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
9654 - uint32_t request_size, data_size, dataout_size;
9655 - uint32_t direction;
9656 - ddi_dma_cookie_t data_cookie;
9657 - ddi_dma_cookie_t dataout_cookie;
9658 - uint32_t request_desc_low, request_desc_high = 0;
9659 - uint32_t i, sense_bufp;
10951 + uint32_t request_size;
10952 + uint64_t request_desc = 0;
10953 + uint64_t sense_bufp;
9660 10954 uint8_t desc_type;
9661 10955 uint8_t *request, function;
9662 10956 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
9663 10957 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
9664 10958
9665 10959 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
9666 10960
9667 10961 request = pt->request;
9668 - direction = pt->direction;
9669 10962 request_size = pt->request_size;
9670 - data_size = pt->data_size;
9671 - dataout_size = pt->dataout_size;
9672 - data_cookie = pt->data_cookie;
9673 - dataout_cookie = pt->dataout_cookie;
9674 10963
9675 10964 /*
9676 10965 * Store the passthrough message in memory location
9677 10966 * corresponding to our slot number
9678 10967 */
9679 10968 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot);
9680 10969 request_hdrp = (pMPI2RequestHeader_t)memp;
9681 10970 bzero(memp, mpt->m_req_frame_size);
9682 10971
9683 - for (i = 0; i < request_size; i++) {
9684 - bcopy(request + i, memp + i, 1);
9685 - }
10972 + bcopy(request, memp, request_size);
9686 10973
9687 - if (data_size || dataout_size) {
9688 - pMpi2SGESimple64_t sgep;
9689 - uint32_t sge_flags;
9690 -
9691 - sgep = (pMpi2SGESimple64_t)((uint8_t *)request_hdrp +
9692 - request_size);
9693 - if (dataout_size) {
9694 -
9695 - sge_flags = dataout_size |
9696 - ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
9697 - MPI2_SGE_FLAGS_END_OF_BUFFER |
9698 - MPI2_SGE_FLAGS_HOST_TO_IOC |
9699 - MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
9700 - MPI2_SGE_FLAGS_SHIFT);
9701 - ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
9702 - ddi_put32(acc_hdl, &sgep->Address.Low,
9703 - (uint32_t)(dataout_cookie.dmac_laddress &
9704 - 0xffffffffull));
9705 - ddi_put32(acc_hdl, &sgep->Address.High,
9706 - (uint32_t)(dataout_cookie.dmac_laddress
9707 - >> 32));
9708 - sgep++;
9709 - }
9710 - sge_flags = data_size;
9711 - sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
9712 - MPI2_SGE_FLAGS_LAST_ELEMENT |
9713 - MPI2_SGE_FLAGS_END_OF_BUFFER |
9714 - MPI2_SGE_FLAGS_END_OF_LIST |
9715 - MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
9716 - MPI2_SGE_FLAGS_SHIFT);
9717 - if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
9718 - sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
9719 - MPI2_SGE_FLAGS_SHIFT);
9720 - } else {
9721 - sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
9722 - MPI2_SGE_FLAGS_SHIFT);
9723 - }
9724 - ddi_put32(acc_hdl, &sgep->FlagsLength,
9725 - sge_flags);
9726 - ddi_put32(acc_hdl, &sgep->Address.Low,
9727 - (uint32_t)(data_cookie.dmac_laddress &
9728 - 0xffffffffull));
9729 - ddi_put32(acc_hdl, &sgep->Address.High,
9730 - (uint32_t)(data_cookie.dmac_laddress >> 32));
10974 + NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, "
10975 + "size=%d, in %d, out %d", request_hdrp->Function,
10976 + request_hdrp->MsgFlags, request_size,
10977 + pt->data_size, pt->dataout_size));
10978 +
10979 + /*
10980 + * Add an SGE, even if the length is zero.
10981 + */
10982 + if (mpt->m_MPI25 && pt->simple == 0) {
10983 + mptsas_passthru_ieee_sge(acc_hdl, pt,
10984 + (pMpi2IeeeSgeSimple64_t)
10985 + ((uint8_t *)request_hdrp + pt->sgl_offset));
10986 + } else {
10987 + mptsas_passthru_sge(acc_hdl, pt,
10988 + (pMpi2SGESimple64_t)
10989 + ((uint8_t *)request_hdrp + pt->sgl_offset));
9731 10990 }
9732 10991
9733 10992 function = request_hdrp->Function;
9734 10993 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
9735 10994 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
9736 10995 pMpi2SCSIIORequest_t scsi_io_req;
9737 10996
10997 + NDBG15(("mptsas_start_passthru: Is SCSI IO Req"));
9738 10998 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
9739 10999 /*
9740 11000 * Put SGE for data and data_out buffer at the end of
9741 11001 * scsi_io_request message header.(64 bytes in total)
9742 11002 * Following above SGEs, the residual space will be
9743 11003 * used by sense data.
9744 11004 */
9745 11005 ddi_put8(acc_hdl,
9746 11006 &scsi_io_req->SenseBufferLength,
9747 11007 (uint8_t)(request_size - 64));
9748 11008
9749 - sense_bufp = mpt->m_req_frame_dma_addr +
9750 - (mpt->m_req_frame_size * cmd->cmd_slot);
11009 + sense_bufp = (uint32_t)(mpt->m_req_frame_dma_addr +
11010 + (mpt->m_req_frame_size * cmd->cmd_slot) & 0xffffffffull);
9751 11011 sense_bufp += 64;
9752 11012 ddi_put32(acc_hdl,
9753 11013 &scsi_io_req->SenseBufferLowAddress, sense_bufp);
9754 11014
9755 11015 /*
9756 11016 * Set SGLOffset0 value
9757 11017 */
9758 11018 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
9759 11019 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
9760 11020
9761 11021 /*
9762 11022 * Setup descriptor info. RAID passthrough must use the
9763 11023 * default request descriptor which is already set, so if this
9764 11024 * is a SCSI IO request, change the descriptor to SCSI IO.
9765 11025 */
9766 11026 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
9767 11027 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
9768 - request_desc_high = (ddi_get16(acc_hdl,
9769 - &scsi_io_req->DevHandle) << 16);
11028 + request_desc = (((uint64_t)ddi_get16(acc_hdl,
11029 + &scsi_io_req->DevHandle)) << 48);
9770 11030 }
9771 11031 }
9772 11032
9773 11033 /*
9774 11034 * We must wait till the message has been completed before
9775 11035 * beginning the next message so we wait for this one to
9776 11036 * finish.
9777 11037 */
9778 11038 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
9779 - request_desc_low = (cmd->cmd_slot << 16) + desc_type;
11039 + request_desc |= ((cmd->cmd_slot << 16) | desc_type);
9780 11040 cmd->cmd_rfm = NULL;
9781 - MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
11041 + MPTSAS_START_CMD(mpt, request_desc);
9782 11042 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
9783 11043 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
9784 11044 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
9785 11045 }
9786 11046 }
9787 11047
11048 +typedef void (mps_pre_f)(mptsas_t *, mptsas_pt_request_t *);
11049 +static mps_pre_f mpi_pre_ioc_facts;
11050 +static mps_pre_f mpi_pre_port_facts;
11051 +static mps_pre_f mpi_pre_fw_download;
11052 +static mps_pre_f mpi_pre_fw_25_download;
11053 +static mps_pre_f mpi_pre_fw_upload;
11054 +static mps_pre_f mpi_pre_fw_25_upload;
11055 +static mps_pre_f mpi_pre_sata_passthrough;
11056 +static mps_pre_f mpi_pre_smp_passthrough;
11057 +static mps_pre_f mpi_pre_config;
11058 +static mps_pre_f mpi_pre_sas_io_unit_control;
11059 +static mps_pre_f mpi_pre_scsi_io_req;
11060 +
11061 +/*
11062 + * Prepare the pt for a SAS2 FW_DOWNLOAD request.
11063 + */
11064 +static void
11065 +mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
11066 +{
11067 + pMpi2FWDownloadTCSGE_t tcsge;
11068 + pMpi2FWDownloadRequest req;
11069 +
11070 + /*
11071 + * If SAS3, call separate function.
11072 + */
11073 + if (mpt->m_MPI25) {
11074 + mpi_pre_fw_25_download(mpt, pt);
11075 + return;
11076 + }
11077 +
11078 + /*
11079 + * User requests should come in with the Transaction
11080 + * context element where the SGL will go. Putting the
11081 + * SGL after that seems to work, but don't really know
11082 + * why. Other drivers tend to create an extra SGL and
11083 + * refer to the TCE through that.
11084 + */
11085 + req = (pMpi2FWDownloadRequest)pt->request;
11086 + tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL;
11087 + if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
11088 + tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
11089 + mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
11090 + }
11091 +
11092 + pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) +
11093 + sizeof (*tcsge);
11094 + if (pt->request_size != pt->sgl_offset)
11095 + NDBG15(("mpi_pre_fw_download(): Incorrect req size, "
11096 + "0x%x, should be 0x%x, dataoutsz 0x%x",
11097 + (int)pt->request_size, (int)pt->sgl_offset,
11098 + (int)pt->dataout_size));
11099 + if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY))
11100 + NDBG15(("mpi_pre_fw_download(): Incorrect rep size, "
11101 + "0x%x, should be 0x%x", pt->data_size,
11102 + (int)sizeof (MPI2_FW_DOWNLOAD_REPLY)));
11103 +}
11104 +
11105 +/*
11106 + * Prepare the pt for a SAS3 FW_DOWNLOAD request.
11107 + */
11108 +static void
11109 +mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
11110 +{
11111 + pMpi2FWDownloadTCSGE_t tcsge;
11112 + pMpi2FWDownloadRequest req2;
11113 + pMpi25FWDownloadRequest req25;
11114 +
11115 + /*
11116 + * User requests should come in with the Transaction
11117 + * context element where the SGL will go. The new firmware
11118 + * Doesn't use TCE and has space in the main request for
11119 + * this information. So move to the right place.
11120 + */
11121 + req2 = (pMpi2FWDownloadRequest)pt->request;
11122 + req25 = (pMpi25FWDownloadRequest)pt->request;
11123 + tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL;
11124 + if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
11125 + tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
11126 + mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
11127 + }
11128 + req25->ImageOffset = tcsge->ImageOffset;
11129 + req25->ImageSize = tcsge->ImageSize;
11130 +
11131 + pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL);
11132 + if (pt->request_size != pt->sgl_offset)
11133 + NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, "
11134 + "0x%x, should be 0x%x, dataoutsz 0x%x",
11135 + pt->request_size, pt->sgl_offset,
11136 + pt->dataout_size));
11137 + if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY))
11138 + NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, "
11139 + "0x%x, should be 0x%x", pt->data_size,
11140 + (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
11141 +}
11142 +
11143 +/*
11144 + * Prepare the pt for a SAS2 FW_UPLOAD request.
11145 + */
11146 +static void
11147 +mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
11148 +{
11149 + pMpi2FWUploadTCSGE_t tcsge;
11150 + pMpi2FWUploadRequest_t req;
11151 +
11152 + /*
11153 + * If SAS3, call separate function.
11154 + */
11155 + if (mpt->m_MPI25) {
11156 + mpi_pre_fw_25_upload(mpt, pt);
11157 + return;
11158 + }
11159 +
11160 + /*
11161 + * User requests should come in with the Transaction
11162 + * context element where the SGL will go. Putting the
11163 + * SGL after that seems to work, but don't really know
11164 + * why. Other drivers tend to create an extra SGL and
11165 + * refer to the TCE through that.
11166 + */
11167 + req = (pMpi2FWUploadRequest_t)pt->request;
11168 + tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL;
11169 + if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
11170 + tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
11171 + mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
11172 + }
11173 +
11174 + pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) +
11175 + sizeof (*tcsge);
11176 + if (pt->request_size != pt->sgl_offset)
11177 + NDBG15(("mpi_pre_fw_upload(): Incorrect req size, "
11178 + "0x%x, should be 0x%x, dataoutsz 0x%x",
11179 + pt->request_size, pt->sgl_offset,
11180 + pt->dataout_size));
11181 + if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY))
11182 + NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, "
11183 + "0x%x, should be 0x%x", pt->data_size,
11184 + (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
11185 +}
11186 +
11187 +/*
11188 + * Prepare the pt a SAS3 FW_UPLOAD request.
11189 + */
11190 +static void
11191 +mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
11192 +{
11193 + pMpi2FWUploadTCSGE_t tcsge;
11194 + pMpi2FWUploadRequest_t req2;
11195 + pMpi25FWUploadRequest_t req25;
11196 +
11197 + /*
11198 + * User requests should come in with the Transaction
11199 + * context element where the SGL will go. The new firmware
11200 + * Doesn't use TCE and has space in the main request for
11201 + * this information. So move to the right place.
11202 + */
11203 + req2 = (pMpi2FWUploadRequest_t)pt->request;
11204 + req25 = (pMpi25FWUploadRequest_t)pt->request;
11205 + tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL;
11206 + if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
11207 + tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
11208 + mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
11209 + }
11210 + req25->ImageOffset = tcsge->ImageOffset;
11211 + req25->ImageSize = tcsge->ImageSize;
11212 +
11213 + pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL);
11214 + if (pt->request_size != pt->sgl_offset)
11215 + NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, "
11216 + "0x%x, should be 0x%x, dataoutsz 0x%x",
11217 + pt->request_size, pt->sgl_offset,
11218 + pt->dataout_size));
11219 + if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY))
11220 + NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, "
11221 + "0x%x, should be 0x%x", pt->data_size,
11222 + (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
11223 +}
11224 +
11225 +/*
11226 + * Prepare the pt for an IOC_FACTS request.
11227 + */
11228 +static void
11229 +mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
11230 +{
11231 +#ifndef __lock_lint
11232 + _NOTE(ARGUNUSED(mpt))
11233 +#endif
11234 + if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST))
11235 + NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, "
11236 + "0x%x, should be 0x%x, dataoutsz 0x%x",
11237 + pt->request_size,
11238 + (int)sizeof (MPI2_IOC_FACTS_REQUEST),
11239 + pt->dataout_size));
11240 + if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY))
11241 + NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, "
11242 + "0x%x, should be 0x%x", pt->data_size,
11243 + (int)sizeof (MPI2_IOC_FACTS_REPLY)));
11244 + pt->sgl_offset = (uint16_t)pt->request_size;
11245 +}
11246 +
11247 +/*
11248 + * Prepare the pt for a PORT_FACTS request.
11249 + */
11250 +static void
11251 +mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
11252 +{
11253 +#ifndef __lock_lint
11254 + _NOTE(ARGUNUSED(mpt))
11255 +#endif
11256 + if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST))
11257 + NDBG15(("mpi_pre_port_facts(): Incorrect req size, "
11258 + "0x%x, should be 0x%x, dataoutsz 0x%x",
11259 + pt->request_size,
11260 + (int)sizeof (MPI2_PORT_FACTS_REQUEST),
11261 + pt->dataout_size));
11262 + if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY))
11263 + NDBG15(("mpi_pre_port_facts(): Incorrect rep size, "
11264 + "0x%x, should be 0x%x", pt->data_size,
11265 + (int)sizeof (MPI2_PORT_FACTS_REPLY)));
11266 + pt->sgl_offset = (uint16_t)pt->request_size;
11267 +}
11268 +
11269 +/*
11270 + * Prepare pt for a SATA_PASSTHROUGH request.
11271 + */
11272 +static void
11273 +mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
11274 +{
11275 +#ifndef __lock_lint
11276 + _NOTE(ARGUNUSED(mpt))
11277 +#endif
11278 + pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL);
11279 + if (pt->request_size != pt->sgl_offset)
11280 + NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, "
11281 + "0x%x, should be 0x%x, dataoutsz 0x%x",
11282 + pt->request_size, pt->sgl_offset,
11283 + pt->dataout_size));
11284 + if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY))
11285 + NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, "
11286 + "0x%x, should be 0x%x", pt->data_size,
11287 + (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY)));
11288 +}
11289 +
11290 +static void
11291 +mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
11292 +{
11293 +#ifndef __lock_lint
11294 + _NOTE(ARGUNUSED(mpt))
11295 +#endif
11296 + pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL);
11297 + if (pt->request_size != pt->sgl_offset)
11298 + NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, "
11299 + "0x%x, should be 0x%x, dataoutsz 0x%x",
11300 + pt->request_size, pt->sgl_offset,
11301 + pt->dataout_size));
11302 + if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY))
11303 + NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, "
11304 + "0x%x, should be 0x%x", pt->data_size,
11305 + (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY)));
11306 +}
11307 +
11308 +/*
11309 + * Prepare pt for a CONFIG request.
11310 + */
11311 +static void
11312 +mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt)
11313 +{
11314 +#ifndef __lock_lint
11315 + _NOTE(ARGUNUSED(mpt))
11316 +#endif
11317 + pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE);
11318 + if (pt->request_size != pt->sgl_offset)
11319 + NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
11320 + "should be 0x%x, dataoutsz 0x%x", pt->request_size,
11321 + pt->sgl_offset, pt->dataout_size));
11322 + if (pt->data_size != sizeof (MPI2_CONFIG_REPLY))
11323 + NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
11324 + "should be 0x%x", pt->data_size,
11325 + (int)sizeof (MPI2_CONFIG_REPLY)));
11326 + pt->simple = 1;
11327 +}
11328 +
11329 +/*
11330 + * Prepare pt for a SCSI_IO_REQ request.
11331 + */
11332 +static void
11333 +mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt)
11334 +{
11335 +#ifndef __lock_lint
11336 + _NOTE(ARGUNUSED(mpt))
11337 +#endif
11338 + pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL);
11339 + if (pt->request_size != pt->sgl_offset)
11340 + NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
11341 + "should be 0x%x, dataoutsz 0x%x", pt->request_size,
11342 + pt->sgl_offset,
11343 + pt->dataout_size));
11344 + if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY))
11345 + NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
11346 + "should be 0x%x", pt->data_size,
11347 + (int)sizeof (MPI2_SCSI_IO_REPLY)));
11348 +}
11349 +
11350 +/*
11351 + * Prepare the mps_command for a SAS_IO_UNIT_CONTROL request.
11352 + */
11353 +static void
11354 +mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt)
11355 +{
11356 +#ifndef __lock_lint
11357 + _NOTE(ARGUNUSED(mpt))
11358 +#endif
11359 + pt->sgl_offset = (uint16_t)pt->request_size;
11360 +}
11361 +
11362 +/*
11363 + * A set of functions to prepare an mps_command for the various
11364 + * supported requests.
11365 + */
11366 +struct mps_func {
11367 + U8 Function;
11368 + char *Name;
11369 + mps_pre_f *f_pre;
11370 +} mps_func_list[] = {
11371 + { MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS", mpi_pre_ioc_facts },
11372 + { MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS", mpi_pre_port_facts },
11373 + { MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD", mpi_pre_fw_download },
11374 + { MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD", mpi_pre_fw_upload },
11375 + { MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH",
11376 + mpi_pre_sata_passthrough },
11377 + { MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH",
11378 + mpi_pre_smp_passthrough},
11379 + { MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST",
11380 + mpi_pre_scsi_io_req},
11381 + { MPI2_FUNCTION_CONFIG, "CONFIG", mpi_pre_config},
11382 + { MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL",
11383 + mpi_pre_sas_io_unit_control },
11384 + { 0xFF, NULL, NULL } /* list end */
11385 +};
11386 +
11387 +static void
11388 +mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt)
11389 +{
11390 + pMPI2RequestHeader_t hdr;
11391 + struct mps_func *f;
11392 +
11393 + hdr = (pMPI2RequestHeader_t)pt->request;
11394 +
11395 + for (f = mps_func_list; f->f_pre != NULL; f++) {
11396 + if (hdr->Function == f->Function) {
11397 + f->f_pre(mpt, pt);
11398 + NDBG15(("mptsas_prep_sgl_offset: Function %s,"
11399 + " sgl_offset 0x%x", f->Name,
11400 + pt->sgl_offset));
11401 + return;
11402 + }
11403 + }
11404 + NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x,"
11405 + " returning req_size 0x%x for sgl_offset",
11406 + hdr->Function, pt->request_size));
11407 + pt->sgl_offset = (uint16_t)pt->request_size;
11408 +}
9788 11409
9789 11410
9790 11411 static int
9791 11412 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
9792 11413 uint8_t *data, uint32_t request_size, uint32_t reply_size,
9793 - uint32_t data_size, uint32_t direction, uint8_t *dataout,
11414 + uint32_t data_size, uint8_t direction, uint8_t *dataout,
9794 11415 uint32_t dataout_size, short timeout, int mode)
9795 11416 {
9796 11417 mptsas_pt_request_t pt;
9797 11418 mptsas_dma_alloc_state_t data_dma_state;
9798 11419 mptsas_dma_alloc_state_t dataout_dma_state;
9799 11420 caddr_t memp;
9800 11421 mptsas_cmd_t *cmd = NULL;
9801 11422 struct scsi_pkt *pkt;
9802 11423 uint32_t reply_len = 0, sense_len = 0;
9803 11424 pMPI2RequestHeader_t request_hdrp;
9804 11425 pMPI2RequestHeader_t request_msg;
9805 11426 pMPI2DefaultReply_t reply_msg;
9806 11427 Mpi2SCSIIOReply_t rep_msg;
9807 11428 int i, status = 0, pt_flags = 0, rv = 0;
9808 11429 int rvalue;
9809 11430 uint8_t function;
9810 11431
9811 11432 ASSERT(mutex_owned(&mpt->m_mutex));
9812 11433
9813 11434 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
9814 11435 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
9815 11436 request_msg = kmem_zalloc(request_size, KM_SLEEP);
9816 11437
9817 11438 mutex_exit(&mpt->m_mutex);
9818 11439 /*
9819 11440 * copy in the request buffer since it could be used by
9820 11441 * another thread when the pt request into waitq
9821 11442 */
9822 11443 if (ddi_copyin(request, request_msg, request_size, mode)) {
9823 11444 mutex_enter(&mpt->m_mutex);
9824 11445 status = EFAULT;
9825 11446 mptsas_log(mpt, CE_WARN, "failed to copy request data");
9826 11447 goto out;
9827 11448 }
9828 11449 mutex_enter(&mpt->m_mutex);
9829 11450
9830 11451 function = request_msg->Function;
9831 11452 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
9832 11453 pMpi2SCSITaskManagementRequest_t task;
9833 11454 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
9834 11455 mptsas_setup_bus_reset_delay(mpt);
9835 11456 rv = mptsas_ioc_task_management(mpt, task->TaskType,
9836 11457 task->DevHandle, (int)task->LUN[1], reply, reply_size,
9837 11458 mode);
9838 11459
9839 11460 if (rv != TRUE) {
9840 11461 status = EIO;
9841 11462 mptsas_log(mpt, CE_WARN, "task management failed");
9842 11463 }
9843 11464 goto out;
9844 11465 }
9845 11466
9846 11467 if (data_size != 0) {
9847 11468 data_dma_state.size = data_size;
9848 11469 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
9849 11470 status = ENOMEM;
9850 11471 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
9851 11472 "resource");
9852 11473 goto out;
9853 11474 }
9854 11475 pt_flags |= MPTSAS_DATA_ALLOCATED;
9855 11476 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
9856 11477 mutex_exit(&mpt->m_mutex);
9857 11478 for (i = 0; i < data_size; i++) {
9858 11479 if (ddi_copyin(data + i, (uint8_t *)
9859 11480 data_dma_state.memp + i, 1, mode)) {
|
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56 lines elided |
↑ open up ↑ |
9860 11481 mutex_enter(&mpt->m_mutex);
9861 11482 status = EFAULT;
9862 11483 mptsas_log(mpt, CE_WARN, "failed to "
9863 11484 "copy read data");
9864 11485 goto out;
9865 11486 }
9866 11487 }
9867 11488 mutex_enter(&mpt->m_mutex);
9868 11489 }
9869 11490 }
11491 + else
11492 + bzero(&data_dma_state, sizeof (data_dma_state));
9870 11493
9871 11494 if (dataout_size != 0) {
9872 11495 dataout_dma_state.size = dataout_size;
9873 11496 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
9874 11497 status = ENOMEM;
9875 11498 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
9876 11499 "resource");
9877 11500 goto out;
9878 11501 }
9879 11502 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
9880 11503 mutex_exit(&mpt->m_mutex);
9881 11504 for (i = 0; i < dataout_size; i++) {
9882 11505 if (ddi_copyin(dataout + i, (uint8_t *)
|
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3 lines elided |
↑ open up ↑ |
9883 11506 dataout_dma_state.memp + i, 1, mode)) {
9884 11507 mutex_enter(&mpt->m_mutex);
9885 11508 mptsas_log(mpt, CE_WARN, "failed to copy out"
9886 11509 " data");
9887 11510 status = EFAULT;
9888 11511 goto out;
9889 11512 }
9890 11513 }
9891 11514 mutex_enter(&mpt->m_mutex);
9892 11515 }
11516 + else
11517 + bzero(&dataout_dma_state, sizeof (dataout_dma_state));
9893 11518
9894 11519 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
9895 11520 status = EAGAIN;
9896 11521 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
9897 11522 goto out;
9898 11523 }
9899 11524 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
9900 11525
9901 11526 bzero((caddr_t)cmd, sizeof (*cmd));
9902 11527 bzero((caddr_t)pkt, scsi_pkt_size());
9903 11528 bzero((caddr_t)&pt, sizeof (pt));
9904 11529
9905 11530 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
9906 11531
9907 11532 pt.request = (uint8_t *)request_msg;
9908 11533 pt.direction = direction;
11534 + pt.simple = 0;
9909 11535 pt.request_size = request_size;
9910 11536 pt.data_size = data_size;
9911 11537 pt.dataout_size = dataout_size;
9912 11538 pt.data_cookie = data_dma_state.cookie;
9913 11539 pt.dataout_cookie = dataout_dma_state.cookie;
11540 + mptsas_prep_sgl_offset(mpt, &pt);
9914 11541
9915 11542 /*
9916 11543 * Form a blank cmd/pkt to store the acknowledgement message
9917 11544 */
9918 11545 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
9919 11546 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
9920 11547 pkt->pkt_ha_private = (opaque_t)&pt;
9921 11548 pkt->pkt_flags = FLAG_HEAD;
9922 11549 pkt->pkt_time = timeout;
9923 11550 cmd->cmd_pkt = pkt;
9924 11551 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
9925 11552
9926 11553 /*
9927 11554 * Save the command in a slot
9928 11555 */
9929 11556 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
9930 11557 /*
9931 11558 * Once passthru command get slot, set cmd_flags
9932 11559 * CFLAG_PREPARED.
9933 11560 */
9934 11561 cmd->cmd_flags |= CFLAG_PREPARED;
9935 11562 mptsas_start_passthru(mpt, cmd);
9936 11563 } else {
9937 11564 mptsas_waitq_add(mpt, cmd);
9938 11565 }
9939 11566
9940 11567 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
9941 11568 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
9942 11569 }
9943 11570
9944 11571 if (cmd->cmd_flags & CFLAG_PREPARED) {
9945 11572 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
9946 11573 cmd->cmd_slot);
9947 11574 request_hdrp = (pMPI2RequestHeader_t)memp;
9948 11575 }
9949 11576
9950 11577 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
9951 11578 status = ETIMEDOUT;
9952 11579 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
9953 11580 pt_flags |= MPTSAS_CMD_TIMEOUT;
9954 11581 goto out;
9955 11582 }
9956 11583
9957 11584 if (cmd->cmd_rfm) {
9958 11585 /*
9959 11586 * cmd_rfm is zero means the command reply is a CONTEXT
|
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36 lines elided |
↑ open up ↑ |
9960 11587 * reply and no PCI Write to post the free reply SMFA
9961 11588 * because no reply message frame is used.
9962 11589 * cmd_rfm is non-zero means the reply is a ADDRESS
9963 11590 * reply and reply message frame is used.
9964 11591 */
9965 11592 pt_flags |= MPTSAS_ADDRESS_REPLY;
9966 11593 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
9967 11594 DDI_DMA_SYNC_FORCPU);
9968 11595 reply_msg = (pMPI2DefaultReply_t)
9969 11596 (mpt->m_reply_frame + (cmd->cmd_rfm -
9970 - mpt->m_reply_frame_dma_addr));
11597 + (mpt->m_reply_frame_dma_addr&0xfffffffful)));
9971 11598 }
9972 11599
9973 11600 mptsas_fma_check(mpt, cmd);
9974 11601 if (pkt->pkt_reason == CMD_TRAN_ERR) {
9975 11602 status = EAGAIN;
9976 11603 mptsas_log(mpt, CE_WARN, "passthru fma error");
9977 11604 goto out;
9978 11605 }
9979 11606 if (pkt->pkt_reason == CMD_RESET) {
9980 11607 status = EAGAIN;
9981 11608 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
9982 11609 goto out;
9983 11610 }
9984 11611
9985 11612 if (pkt->pkt_reason == CMD_INCOMPLETE) {
9986 11613 status = EIO;
9987 11614 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
9988 11615 goto out;
9989 11616 }
9990 11617
9991 11618 mutex_exit(&mpt->m_mutex);
9992 11619 if (cmd->cmd_flags & CFLAG_PREPARED) {
9993 11620 function = request_hdrp->Function;
9994 11621 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
9995 11622 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
9996 11623 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
9997 11624 sense_len = reply_size - reply_len;
9998 11625 } else {
9999 11626 reply_len = reply_size;
10000 11627 sense_len = 0;
10001 11628 }
10002 11629
10003 11630 for (i = 0; i < reply_len; i++) {
10004 11631 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
10005 11632 mode)) {
10006 11633 mutex_enter(&mpt->m_mutex);
10007 11634 status = EFAULT;
10008 11635 mptsas_log(mpt, CE_WARN, "failed to copy out "
10009 11636 "reply data");
10010 11637 goto out;
10011 11638 }
10012 11639 }
10013 11640 for (i = 0; i < sense_len; i++) {
10014 11641 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
10015 11642 reply + reply_len + i, 1, mode)) {
10016 11643 mutex_enter(&mpt->m_mutex);
10017 11644 status = EFAULT;
10018 11645 mptsas_log(mpt, CE_WARN, "failed to copy out "
10019 11646 "sense data");
10020 11647 goto out;
10021 11648 }
10022 11649 }
10023 11650 }
10024 11651
10025 11652 if (data_size) {
10026 11653 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10027 11654 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
10028 11655 DDI_DMA_SYNC_FORCPU);
10029 11656 for (i = 0; i < data_size; i++) {
10030 11657 if (ddi_copyout((uint8_t *)(
10031 11658 data_dma_state.memp + i), data + i, 1,
10032 11659 mode)) {
10033 11660 mutex_enter(&mpt->m_mutex);
10034 11661 status = EFAULT;
10035 11662 mptsas_log(mpt, CE_WARN, "failed to "
10036 11663 "copy out the reply data");
10037 11664 goto out;
10038 11665 }
10039 11666 }
10040 11667 }
10041 11668 }
10042 11669 mutex_enter(&mpt->m_mutex);
10043 11670 out:
10044 11671 /*
10045 11672 * Put the reply frame back on the free queue, increment the free
10046 11673 * index, and write the new index to the free index register. But only
10047 11674 * if this reply is an ADDRESS reply.
10048 11675 */
10049 11676 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
10050 11677 ddi_put32(mpt->m_acc_free_queue_hdl,
10051 11678 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10052 11679 cmd->cmd_rfm);
10053 11680 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10054 11681 DDI_DMA_SYNC_FORDEV);
10055 11682 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10056 11683 mpt->m_free_index = 0;
10057 11684 }
10058 11685 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10059 11686 mpt->m_free_index);
10060 11687 }
10061 11688 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10062 11689 mptsas_remove_cmd(mpt, cmd);
10063 11690 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10064 11691 }
10065 11692 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
10066 11693 mptsas_return_to_pool(mpt, cmd);
10067 11694 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
10068 11695 if (mptsas_check_dma_handle(data_dma_state.handle) !=
10069 11696 DDI_SUCCESS) {
10070 11697 ddi_fm_service_impact(mpt->m_dip,
10071 11698 DDI_SERVICE_UNAFFECTED);
10072 11699 status = EFAULT;
10073 11700 }
10074 11701 mptsas_dma_free(&data_dma_state);
10075 11702 }
10076 11703 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
10077 11704 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
10078 11705 DDI_SUCCESS) {
10079 11706 ddi_fm_service_impact(mpt->m_dip,
10080 11707 DDI_SERVICE_UNAFFECTED);
10081 11708 status = EFAULT;
10082 11709 }
10083 11710 mptsas_dma_free(&dataout_dma_state);
10084 11711 }
10085 11712 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
10086 11713 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
10087 11714 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
10088 11715 }
10089 11716 }
10090 11717 if (request_msg)
10091 11718 kmem_free(request_msg, request_size);
10092 11719
10093 11720 return (status);
10094 11721 }
10095 11722
10096 11723 static int
10097 11724 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
10098 11725 {
10099 11726 /*
10100 11727 * If timeout is 0, set timeout to default of 60 seconds.
10101 11728 */
10102 11729 if (data->Timeout == 0) {
10103 11730 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
10104 11731 }
10105 11732
10106 11733 if (((data->DataSize == 0) &&
10107 11734 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
10108 11735 ((data->DataSize != 0) &&
10109 11736 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
10110 11737 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
10111 11738 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
10112 11739 (data->DataOutSize != 0))))) {
10113 11740 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
10114 11741 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
10115 11742 } else {
|
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135 lines elided |
↑ open up ↑ |
10116 11743 data->DataOutSize = 0;
10117 11744 }
10118 11745 /*
10119 11746 * Send passthru request messages
10120 11747 */
10121 11748 return (mptsas_do_passthru(mpt,
10122 11749 (uint8_t *)((uintptr_t)data->PtrRequest),
10123 11750 (uint8_t *)((uintptr_t)data->PtrReply),
10124 11751 (uint8_t *)((uintptr_t)data->PtrData),
10125 11752 data->RequestSize, data->ReplySize,
10126 - data->DataSize, data->DataDirection,
11753 + data->DataSize, (uint8_t)data->DataDirection,
10127 11754 (uint8_t *)((uintptr_t)data->PtrDataOut),
10128 11755 data->DataOutSize, data->Timeout, mode));
10129 11756 } else {
10130 11757 return (EINVAL);
10131 11758 }
10132 11759 }
10133 11760
10134 11761 static uint8_t
10135 11762 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
10136 11763 {
10137 11764 uint8_t index;
10138 11765
10139 11766 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
10140 11767 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
10141 11768 return (index);
10142 11769 }
10143 11770 }
10144 11771
|
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8 lines elided |
↑ open up ↑ |
10145 11772 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
10146 11773 }
10147 11774
10148 11775 static void
10149 11776 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
10150 11777 {
10151 11778 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
10152 11779 pMpi2DiagReleaseRequest_t pDiag_release_msg;
10153 11780 struct scsi_pkt *pkt = cmd->cmd_pkt;
10154 11781 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
10155 - uint32_t request_desc_low, i;
11782 + uint32_t i;
11783 + uint64_t request_desc;
10156 11784
10157 11785 ASSERT(mutex_owned(&mpt->m_mutex));
10158 11786
10159 11787 /*
10160 11788 * Form the diag message depending on the post or release function.
10161 11789 */
10162 11790 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
10163 11791 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
10164 11792 (mpt->m_req_frame + (mpt->m_req_frame_size *
10165 11793 cmd->cmd_slot));
10166 11794 bzero(pDiag_post_msg, mpt->m_req_frame_size);
10167 11795 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
10168 11796 diag->function);
10169 11797 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
10170 11798 diag->pBuffer->buffer_type);
10171 11799 ddi_put8(mpt->m_acc_req_frame_hdl,
10172 11800 &pDiag_post_msg->ExtendedType,
10173 11801 diag->pBuffer->extended_type);
10174 11802 ddi_put32(mpt->m_acc_req_frame_hdl,
10175 11803 &pDiag_post_msg->BufferLength,
10176 11804 diag->pBuffer->buffer_data.size);
10177 11805 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
10178 11806 i++) {
10179 11807 ddi_put32(mpt->m_acc_req_frame_hdl,
10180 11808 &pDiag_post_msg->ProductSpecific[i],
10181 11809 diag->pBuffer->product_specific[i]);
10182 11810 }
10183 11811 ddi_put32(mpt->m_acc_req_frame_hdl,
10184 11812 &pDiag_post_msg->BufferAddress.Low,
10185 11813 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10186 11814 & 0xffffffffull));
10187 11815 ddi_put32(mpt->m_acc_req_frame_hdl,
10188 11816 &pDiag_post_msg->BufferAddress.High,
10189 11817 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10190 11818 >> 32));
10191 11819 } else {
10192 11820 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
10193 11821 (mpt->m_req_frame + (mpt->m_req_frame_size *
10194 11822 cmd->cmd_slot));
10195 11823 bzero(pDiag_release_msg, mpt->m_req_frame_size);
10196 11824 ddi_put8(mpt->m_acc_req_frame_hdl,
10197 11825 &pDiag_release_msg->Function, diag->function);
|
↓ open down ↓ |
32 lines elided |
↑ open up ↑ |
10198 11826 ddi_put8(mpt->m_acc_req_frame_hdl,
10199 11827 &pDiag_release_msg->BufferType,
10200 11828 diag->pBuffer->buffer_type);
10201 11829 }
10202 11830
10203 11831 /*
10204 11832 * Send the message
10205 11833 */
10206 11834 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
10207 11835 DDI_DMA_SYNC_FORDEV);
10208 - request_desc_low = (cmd->cmd_slot << 16) +
11836 + request_desc = (cmd->cmd_slot << 16) |
10209 11837 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10210 11838 cmd->cmd_rfm = NULL;
10211 - MPTSAS_START_CMD(mpt, request_desc_low, 0);
11839 + MPTSAS_START_CMD(mpt, request_desc);
10212 11840 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
10213 11841 DDI_SUCCESS) ||
10214 11842 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
10215 11843 DDI_SUCCESS)) {
10216 11844 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10217 11845 }
10218 11846 }
10219 11847
10220 11848 static int
10221 11849 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
10222 11850 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
10223 11851 {
10224 11852 mptsas_diag_request_t diag;
10225 11853 int status, slot_num, post_flags = 0;
10226 11854 mptsas_cmd_t *cmd = NULL;
10227 11855 struct scsi_pkt *pkt;
10228 11856 pMpi2DiagBufferPostReply_t reply;
10229 11857 uint16_t iocstatus;
10230 11858 uint32_t iocloginfo, transfer_length;
10231 11859
10232 11860 /*
10233 11861 * If buffer is not enabled, just leave.
10234 11862 */
10235 11863 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
10236 11864 if (!pBuffer->enabled) {
10237 11865 status = DDI_FAILURE;
10238 11866 goto out;
10239 11867 }
10240 11868
10241 11869 /*
10242 11870 * Clear some flags initially.
10243 11871 */
10244 11872 pBuffer->force_release = FALSE;
10245 11873 pBuffer->valid_data = FALSE;
10246 11874 pBuffer->owned_by_firmware = FALSE;
10247 11875
10248 11876 /*
10249 11877 * Get a cmd buffer from the cmd buffer pool
10250 11878 */
10251 11879 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10252 11880 status = DDI_FAILURE;
10253 11881 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
10254 11882 goto out;
10255 11883 }
10256 11884 post_flags |= MPTSAS_REQUEST_POOL_CMD;
10257 11885
10258 11886 bzero((caddr_t)cmd, sizeof (*cmd));
10259 11887 bzero((caddr_t)pkt, scsi_pkt_size());
10260 11888
10261 11889 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10262 11890
10263 11891 diag.pBuffer = pBuffer;
10264 11892 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
10265 11893
10266 11894 /*
10267 11895 * Form a blank cmd/pkt to store the acknowledgement message
10268 11896 */
10269 11897 pkt->pkt_ha_private = (opaque_t)&diag;
10270 11898 pkt->pkt_flags = FLAG_HEAD;
10271 11899 pkt->pkt_time = 60;
10272 11900 cmd->cmd_pkt = pkt;
10273 11901 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10274 11902
10275 11903 /*
10276 11904 * Save the command in a slot
10277 11905 */
10278 11906 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10279 11907 /*
10280 11908 * Once passthru command get slot, set cmd_flags
10281 11909 * CFLAG_PREPARED.
10282 11910 */
10283 11911 cmd->cmd_flags |= CFLAG_PREPARED;
10284 11912 mptsas_start_diag(mpt, cmd);
10285 11913 } else {
10286 11914 mptsas_waitq_add(mpt, cmd);
10287 11915 }
10288 11916
10289 11917 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10290 11918 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10291 11919 }
10292 11920
10293 11921 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10294 11922 status = DDI_FAILURE;
10295 11923 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
10296 11924 goto out;
10297 11925 }
10298 11926
|
↓ open down ↓ |
77 lines elided |
↑ open up ↑ |
10299 11927 /*
10300 11928 * cmd_rfm points to the reply message if a reply was given. Check the
10301 11929 * IOCStatus to make sure everything went OK with the FW diag request
10302 11930 * and set buffer flags.
10303 11931 */
10304 11932 if (cmd->cmd_rfm) {
10305 11933 post_flags |= MPTSAS_ADDRESS_REPLY;
10306 11934 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10307 11935 DDI_DMA_SYNC_FORCPU);
10308 11936 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
10309 - (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
11937 + (cmd->cmd_rfm -
11938 + (mpt->m_reply_frame_dma_addr&0xfffffffful)));
10310 11939
10311 11940 /*
10312 11941 * Get the reply message data
10313 11942 */
10314 11943 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10315 11944 &reply->IOCStatus);
10316 11945 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10317 11946 &reply->IOCLogInfo);
10318 11947 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
10319 11948 &reply->TransferLength);
10320 11949
10321 11950 /*
10322 11951 * If post failed quit.
10323 11952 */
10324 11953 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
10325 11954 status = DDI_FAILURE;
10326 11955 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
10327 11956 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
10328 11957 iocloginfo, transfer_length));
10329 11958 goto out;
10330 11959 }
10331 11960
10332 11961 /*
10333 11962 * Post was successful.
10334 11963 */
10335 11964 pBuffer->valid_data = TRUE;
10336 11965 pBuffer->owned_by_firmware = TRUE;
10337 11966 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10338 11967 status = DDI_SUCCESS;
10339 11968 }
10340 11969
10341 11970 out:
10342 11971 /*
10343 11972 * Put the reply frame back on the free queue, increment the free
10344 11973 * index, and write the new index to the free index register. But only
10345 11974 * if this reply is an ADDRESS reply.
10346 11975 */
10347 11976 if (post_flags & MPTSAS_ADDRESS_REPLY) {
10348 11977 ddi_put32(mpt->m_acc_free_queue_hdl,
10349 11978 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10350 11979 cmd->cmd_rfm);
10351 11980 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10352 11981 DDI_DMA_SYNC_FORDEV);
10353 11982 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10354 11983 mpt->m_free_index = 0;
10355 11984 }
10356 11985 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10357 11986 mpt->m_free_index);
10358 11987 }
10359 11988 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10360 11989 mptsas_remove_cmd(mpt, cmd);
10361 11990 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10362 11991 }
10363 11992 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
10364 11993 mptsas_return_to_pool(mpt, cmd);
10365 11994 }
10366 11995
10367 11996 return (status);
10368 11997 }
10369 11998
10370 11999 static int
10371 12000 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
10372 12001 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
10373 12002 uint32_t diag_type)
10374 12003 {
10375 12004 mptsas_diag_request_t diag;
10376 12005 int status, slot_num, rel_flags = 0;
10377 12006 mptsas_cmd_t *cmd = NULL;
10378 12007 struct scsi_pkt *pkt;
10379 12008 pMpi2DiagReleaseReply_t reply;
10380 12009 uint16_t iocstatus;
10381 12010 uint32_t iocloginfo;
10382 12011
10383 12012 /*
10384 12013 * If buffer is not enabled, just leave.
10385 12014 */
10386 12015 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
10387 12016 if (!pBuffer->enabled) {
10388 12017 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
10389 12018 "by the IOC");
10390 12019 status = DDI_FAILURE;
10391 12020 goto out;
10392 12021 }
10393 12022
10394 12023 /*
10395 12024 * Clear some flags initially.
10396 12025 */
10397 12026 pBuffer->force_release = FALSE;
10398 12027 pBuffer->valid_data = FALSE;
10399 12028 pBuffer->owned_by_firmware = FALSE;
10400 12029
10401 12030 /*
10402 12031 * Get a cmd buffer from the cmd buffer pool
10403 12032 */
10404 12033 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10405 12034 status = DDI_FAILURE;
10406 12035 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
10407 12036 "Diag");
10408 12037 goto out;
10409 12038 }
10410 12039 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
10411 12040
10412 12041 bzero((caddr_t)cmd, sizeof (*cmd));
10413 12042 bzero((caddr_t)pkt, scsi_pkt_size());
10414 12043
10415 12044 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10416 12045
10417 12046 diag.pBuffer = pBuffer;
10418 12047 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
10419 12048
10420 12049 /*
10421 12050 * Form a blank cmd/pkt to store the acknowledgement message
10422 12051 */
10423 12052 pkt->pkt_ha_private = (opaque_t)&diag;
10424 12053 pkt->pkt_flags = FLAG_HEAD;
10425 12054 pkt->pkt_time = 60;
10426 12055 cmd->cmd_pkt = pkt;
10427 12056 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10428 12057
10429 12058 /*
10430 12059 * Save the command in a slot
10431 12060 */
10432 12061 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10433 12062 /*
10434 12063 * Once passthru command get slot, set cmd_flags
10435 12064 * CFLAG_PREPARED.
10436 12065 */
10437 12066 cmd->cmd_flags |= CFLAG_PREPARED;
10438 12067 mptsas_start_diag(mpt, cmd);
10439 12068 } else {
10440 12069 mptsas_waitq_add(mpt, cmd);
10441 12070 }
10442 12071
10443 12072 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10444 12073 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10445 12074 }
10446 12075
10447 12076 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10448 12077 status = DDI_FAILURE;
10449 12078 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
10450 12079 goto out;
10451 12080 }
10452 12081
|
↓ open down ↓ |
133 lines elided |
↑ open up ↑ |
10453 12082 /*
10454 12083 * cmd_rfm points to the reply message if a reply was given. Check the
10455 12084 * IOCStatus to make sure everything went OK with the FW diag request
10456 12085 * and set buffer flags.
10457 12086 */
10458 12087 if (cmd->cmd_rfm) {
10459 12088 rel_flags |= MPTSAS_ADDRESS_REPLY;
10460 12089 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10461 12090 DDI_DMA_SYNC_FORCPU);
10462 12091 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
10463 - (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
12092 + (cmd->cmd_rfm -
12093 + (mpt->m_reply_frame_dma_addr&0xfffffffful)));
10464 12094
10465 12095 /*
10466 12096 * Get the reply message data
10467 12097 */
10468 12098 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10469 12099 &reply->IOCStatus);
10470 12100 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10471 12101 &reply->IOCLogInfo);
10472 12102
10473 12103 /*
10474 12104 * If release failed quit.
10475 12105 */
10476 12106 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
10477 12107 pBuffer->owned_by_firmware) {
10478 12108 status = DDI_FAILURE;
10479 12109 NDBG13(("release FW Diag Buffer failed: "
10480 12110 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
10481 12111 iocloginfo));
10482 12112 goto out;
10483 12113 }
10484 12114
10485 12115 /*
10486 12116 * Release was successful.
10487 12117 */
10488 12118 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10489 12119 status = DDI_SUCCESS;
10490 12120
10491 12121 /*
10492 12122 * If this was for an UNREGISTER diag type command, clear the
10493 12123 * unique ID.
10494 12124 */
10495 12125 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
10496 12126 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
10497 12127 }
10498 12128 }
10499 12129
10500 12130 out:
10501 12131 /*
10502 12132 * Put the reply frame back on the free queue, increment the free
10503 12133 * index, and write the new index to the free index register. But only
10504 12134 * if this reply is an ADDRESS reply.
10505 12135 */
10506 12136 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
10507 12137 ddi_put32(mpt->m_acc_free_queue_hdl,
10508 12138 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10509 12139 cmd->cmd_rfm);
10510 12140 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10511 12141 DDI_DMA_SYNC_FORDEV);
10512 12142 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10513 12143 mpt->m_free_index = 0;
10514 12144 }
10515 12145 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10516 12146 mpt->m_free_index);
10517 12147 }
10518 12148 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10519 12149 mptsas_remove_cmd(mpt, cmd);
10520 12150 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10521 12151 }
10522 12152 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
10523 12153 mptsas_return_to_pool(mpt, cmd);
10524 12154 }
10525 12155
10526 12156 return (status);
10527 12157 }
10528 12158
10529 12159 static int
10530 12160 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
10531 12161 uint32_t *return_code)
10532 12162 {
10533 12163 mptsas_fw_diagnostic_buffer_t *pBuffer;
10534 12164 uint8_t extended_type, buffer_type, i;
10535 12165 uint32_t buffer_size;
10536 12166 uint32_t unique_id;
10537 12167 int status;
10538 12168
10539 12169 ASSERT(mutex_owned(&mpt->m_mutex));
10540 12170
10541 12171 extended_type = diag_register->ExtendedType;
10542 12172 buffer_type = diag_register->BufferType;
10543 12173 buffer_size = diag_register->RequestedBufferSize;
10544 12174 unique_id = diag_register->UniqueId;
10545 12175
10546 12176 /*
10547 12177 * Check for valid buffer type
10548 12178 */
10549 12179 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
10550 12180 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10551 12181 return (DDI_FAILURE);
10552 12182 }
10553 12183
10554 12184 /*
10555 12185 * Get the current buffer and look up the unique ID. The unique ID
10556 12186 * should not be found. If it is, the ID is already in use.
10557 12187 */
10558 12188 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10559 12189 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
10560 12190 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10561 12191 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10562 12192 return (DDI_FAILURE);
10563 12193 }
10564 12194
10565 12195 /*
10566 12196 * The buffer's unique ID should not be registered yet, and the given
10567 12197 * unique ID cannot be 0.
10568 12198 */
10569 12199 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
10570 12200 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
10571 12201 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10572 12202 return (DDI_FAILURE);
10573 12203 }
10574 12204
10575 12205 /*
10576 12206 * If this buffer is already posted as immediate, just change owner.
10577 12207 */
10578 12208 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
10579 12209 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
10580 12210 pBuffer->immediate = FALSE;
10581 12211 pBuffer->unique_id = unique_id;
10582 12212 return (DDI_SUCCESS);
10583 12213 }
10584 12214
10585 12215 /*
10586 12216 * Post a new buffer after checking if it's enabled. The DMA buffer
10587 12217 * that is allocated will be contiguous (sgl_len = 1).
10588 12218 */
10589 12219 if (!pBuffer->enabled) {
10590 12220 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
10591 12221 return (DDI_FAILURE);
10592 12222 }
10593 12223 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
10594 12224 pBuffer->buffer_data.size = buffer_size;
10595 12225 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
10596 12226 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
10597 12227 "diag buffer: size = %d bytes", buffer_size);
10598 12228 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
10599 12229 return (DDI_FAILURE);
10600 12230 }
10601 12231
10602 12232 /*
10603 12233 * Copy the given info to the diag buffer and post the buffer.
10604 12234 */
10605 12235 pBuffer->buffer_type = buffer_type;
10606 12236 pBuffer->immediate = FALSE;
10607 12237 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
10608 12238 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
10609 12239 i++) {
10610 12240 pBuffer->product_specific[i] =
10611 12241 diag_register->ProductSpecific[i];
10612 12242 }
10613 12243 }
10614 12244 pBuffer->extended_type = extended_type;
10615 12245 pBuffer->unique_id = unique_id;
10616 12246 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
10617 12247
10618 12248 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
10619 12249 DDI_SUCCESS) {
10620 12250 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
10621 12251 "mptsas_diag_register.");
10622 12252 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10623 12253 status = DDI_FAILURE;
10624 12254 }
10625 12255
10626 12256 /*
10627 12257 * In case there was a failure, free the DMA buffer.
10628 12258 */
10629 12259 if (status == DDI_FAILURE) {
10630 12260 mptsas_dma_free(&pBuffer->buffer_data);
10631 12261 }
10632 12262
10633 12263 return (status);
10634 12264 }
10635 12265
10636 12266 static int
10637 12267 mptsas_diag_unregister(mptsas_t *mpt,
10638 12268 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
10639 12269 {
10640 12270 mptsas_fw_diagnostic_buffer_t *pBuffer;
10641 12271 uint8_t i;
10642 12272 uint32_t unique_id;
10643 12273 int status;
10644 12274
10645 12275 ASSERT(mutex_owned(&mpt->m_mutex));
10646 12276
10647 12277 unique_id = diag_unregister->UniqueId;
10648 12278
10649 12279 /*
10650 12280 * Get the current buffer and look up the unique ID. The unique ID
10651 12281 * should be there.
10652 12282 */
10653 12283 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10654 12284 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10655 12285 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10656 12286 return (DDI_FAILURE);
10657 12287 }
10658 12288
10659 12289 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10660 12290
10661 12291 /*
10662 12292 * Try to release the buffer from FW before freeing it. If release
10663 12293 * fails, don't free the DMA buffer in case FW tries to access it
10664 12294 * later. If buffer is not owned by firmware, can't release it.
10665 12295 */
10666 12296 if (!pBuffer->owned_by_firmware) {
10667 12297 status = DDI_SUCCESS;
10668 12298 } else {
10669 12299 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
10670 12300 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
10671 12301 }
10672 12302
10673 12303 /*
10674 12304 * At this point, return the current status no matter what happens with
10675 12305 * the DMA buffer.
10676 12306 */
10677 12307 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
10678 12308 if (status == DDI_SUCCESS) {
10679 12309 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
10680 12310 DDI_SUCCESS) {
10681 12311 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
10682 12312 "in mptsas_diag_unregister.");
10683 12313 ddi_fm_service_impact(mpt->m_dip,
10684 12314 DDI_SERVICE_UNAFFECTED);
10685 12315 }
10686 12316 mptsas_dma_free(&pBuffer->buffer_data);
10687 12317 }
10688 12318
10689 12319 return (status);
10690 12320 }
10691 12321
10692 12322 static int
10693 12323 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
10694 12324 uint32_t *return_code)
10695 12325 {
10696 12326 mptsas_fw_diagnostic_buffer_t *pBuffer;
10697 12327 uint8_t i;
10698 12328 uint32_t unique_id;
10699 12329
10700 12330 ASSERT(mutex_owned(&mpt->m_mutex));
10701 12331
10702 12332 unique_id = diag_query->UniqueId;
10703 12333
10704 12334 /*
10705 12335 * If ID is valid, query on ID.
10706 12336 * If ID is invalid, query on buffer type.
10707 12337 */
10708 12338 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
10709 12339 i = diag_query->BufferType;
10710 12340 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
10711 12341 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10712 12342 return (DDI_FAILURE);
10713 12343 }
10714 12344 } else {
10715 12345 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10716 12346 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10717 12347 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10718 12348 return (DDI_FAILURE);
10719 12349 }
10720 12350 }
10721 12351
10722 12352 /*
10723 12353 * Fill query structure with the diag buffer info.
10724 12354 */
10725 12355 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10726 12356 diag_query->BufferType = pBuffer->buffer_type;
10727 12357 diag_query->ExtendedType = pBuffer->extended_type;
10728 12358 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
10729 12359 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
10730 12360 i++) {
10731 12361 diag_query->ProductSpecific[i] =
10732 12362 pBuffer->product_specific[i];
10733 12363 }
10734 12364 }
10735 12365 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
10736 12366 diag_query->DriverAddedBufferSize = 0;
10737 12367 diag_query->UniqueId = pBuffer->unique_id;
10738 12368 diag_query->ApplicationFlags = 0;
10739 12369 diag_query->DiagnosticFlags = 0;
10740 12370
10741 12371 /*
10742 12372 * Set/Clear application flags
10743 12373 */
10744 12374 if (pBuffer->immediate) {
10745 12375 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
10746 12376 } else {
10747 12377 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
10748 12378 }
10749 12379 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
10750 12380 diag_query->ApplicationFlags |=
10751 12381 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
10752 12382 } else {
10753 12383 diag_query->ApplicationFlags &=
10754 12384 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
10755 12385 }
10756 12386 if (pBuffer->owned_by_firmware) {
10757 12387 diag_query->ApplicationFlags |=
10758 12388 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
10759 12389 } else {
10760 12390 diag_query->ApplicationFlags &=
10761 12391 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
10762 12392 }
10763 12393
10764 12394 return (DDI_SUCCESS);
10765 12395 }
10766 12396
10767 12397 static int
10768 12398 mptsas_diag_read_buffer(mptsas_t *mpt,
10769 12399 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
10770 12400 uint32_t *return_code, int ioctl_mode)
10771 12401 {
10772 12402 mptsas_fw_diagnostic_buffer_t *pBuffer;
10773 12403 uint8_t i, *pData;
10774 12404 uint32_t unique_id, byte;
10775 12405 int status;
10776 12406
10777 12407 ASSERT(mutex_owned(&mpt->m_mutex));
10778 12408
10779 12409 unique_id = diag_read_buffer->UniqueId;
10780 12410
10781 12411 /*
10782 12412 * Get the current buffer and look up the unique ID. The unique ID
10783 12413 * should be there.
10784 12414 */
10785 12415 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10786 12416 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10787 12417 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10788 12418 return (DDI_FAILURE);
10789 12419 }
10790 12420
10791 12421 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10792 12422
10793 12423 /*
10794 12424 * Make sure requested read is within limits
10795 12425 */
10796 12426 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
10797 12427 pBuffer->buffer_data.size) {
10798 12428 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10799 12429 return (DDI_FAILURE);
10800 12430 }
10801 12431
10802 12432 /*
10803 12433 * Copy the requested data from DMA to the diag_read_buffer. The DMA
10804 12434 * buffer that was allocated is one contiguous buffer.
10805 12435 */
10806 12436 pData = (uint8_t *)(pBuffer->buffer_data.memp +
10807 12437 diag_read_buffer->StartingOffset);
10808 12438 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
10809 12439 DDI_DMA_SYNC_FORCPU);
10810 12440 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
10811 12441 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
10812 12442 != 0) {
10813 12443 return (DDI_FAILURE);
10814 12444 }
10815 12445 }
10816 12446 diag_read_buffer->Status = 0;
10817 12447
10818 12448 /*
10819 12449 * Set or clear the Force Release flag.
10820 12450 */
10821 12451 if (pBuffer->force_release) {
10822 12452 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
10823 12453 } else {
10824 12454 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
10825 12455 }
10826 12456
10827 12457 /*
10828 12458 * If buffer is to be reregistered, make sure it's not already owned by
10829 12459 * firmware first.
10830 12460 */
10831 12461 status = DDI_SUCCESS;
10832 12462 if (!pBuffer->owned_by_firmware) {
10833 12463 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
10834 12464 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
10835 12465 return_code);
10836 12466 }
10837 12467 }
10838 12468
10839 12469 return (status);
10840 12470 }
10841 12471
10842 12472 static int
10843 12473 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
10844 12474 uint32_t *return_code)
10845 12475 {
10846 12476 mptsas_fw_diagnostic_buffer_t *pBuffer;
10847 12477 uint8_t i;
10848 12478 uint32_t unique_id;
10849 12479 int status;
10850 12480
10851 12481 ASSERT(mutex_owned(&mpt->m_mutex));
10852 12482
10853 12483 unique_id = diag_release->UniqueId;
10854 12484
10855 12485 /*
10856 12486 * Get the current buffer and look up the unique ID. The unique ID
10857 12487 * should be there.
10858 12488 */
10859 12489 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10860 12490 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10861 12491 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10862 12492 return (DDI_FAILURE);
10863 12493 }
10864 12494
10865 12495 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10866 12496
10867 12497 /*
10868 12498 * If buffer is not owned by firmware, it's already been released.
10869 12499 */
10870 12500 if (!pBuffer->owned_by_firmware) {
10871 12501 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
10872 12502 return (DDI_FAILURE);
10873 12503 }
10874 12504
10875 12505 /*
10876 12506 * Release the buffer.
10877 12507 */
10878 12508 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
10879 12509 MPTSAS_FW_DIAG_TYPE_RELEASE);
10880 12510 return (status);
10881 12511 }
10882 12512
10883 12513 static int
10884 12514 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
10885 12515 uint32_t length, uint32_t *return_code, int ioctl_mode)
10886 12516 {
10887 12517 mptsas_fw_diag_register_t diag_register;
10888 12518 mptsas_fw_diag_unregister_t diag_unregister;
10889 12519 mptsas_fw_diag_query_t diag_query;
10890 12520 mptsas_diag_read_buffer_t diag_read_buffer;
10891 12521 mptsas_fw_diag_release_t diag_release;
10892 12522 int status = DDI_SUCCESS;
10893 12523 uint32_t original_return_code, read_buf_len;
10894 12524
10895 12525 ASSERT(mutex_owned(&mpt->m_mutex));
10896 12526
10897 12527 original_return_code = *return_code;
10898 12528 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10899 12529
10900 12530 switch (action) {
10901 12531 case MPTSAS_FW_DIAG_TYPE_REGISTER:
10902 12532 if (!length) {
10903 12533 *return_code =
10904 12534 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10905 12535 status = DDI_FAILURE;
10906 12536 break;
10907 12537 }
10908 12538 if (ddi_copyin(diag_action, &diag_register,
10909 12539 sizeof (diag_register), ioctl_mode) != 0) {
10910 12540 return (DDI_FAILURE);
10911 12541 }
10912 12542 status = mptsas_diag_register(mpt, &diag_register,
10913 12543 return_code);
10914 12544 break;
10915 12545
10916 12546 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
10917 12547 if (length < sizeof (diag_unregister)) {
10918 12548 *return_code =
10919 12549 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10920 12550 status = DDI_FAILURE;
10921 12551 break;
10922 12552 }
10923 12553 if (ddi_copyin(diag_action, &diag_unregister,
10924 12554 sizeof (diag_unregister), ioctl_mode) != 0) {
10925 12555 return (DDI_FAILURE);
10926 12556 }
10927 12557 status = mptsas_diag_unregister(mpt, &diag_unregister,
10928 12558 return_code);
10929 12559 break;
10930 12560
10931 12561 case MPTSAS_FW_DIAG_TYPE_QUERY:
10932 12562 if (length < sizeof (diag_query)) {
10933 12563 *return_code =
10934 12564 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10935 12565 status = DDI_FAILURE;
10936 12566 break;
10937 12567 }
10938 12568 if (ddi_copyin(diag_action, &diag_query,
10939 12569 sizeof (diag_query), ioctl_mode) != 0) {
10940 12570 return (DDI_FAILURE);
10941 12571 }
10942 12572 status = mptsas_diag_query(mpt, &diag_query,
10943 12573 return_code);
10944 12574 if (status == DDI_SUCCESS) {
10945 12575 if (ddi_copyout(&diag_query, diag_action,
10946 12576 sizeof (diag_query), ioctl_mode) != 0) {
10947 12577 return (DDI_FAILURE);
10948 12578 }
10949 12579 }
10950 12580 break;
10951 12581
10952 12582 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
10953 12583 if (ddi_copyin(diag_action, &diag_read_buffer,
10954 12584 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
10955 12585 return (DDI_FAILURE);
10956 12586 }
10957 12587 read_buf_len = sizeof (diag_read_buffer) -
10958 12588 sizeof (diag_read_buffer.DataBuffer) +
10959 12589 diag_read_buffer.BytesToRead;
10960 12590 if (length < read_buf_len) {
10961 12591 *return_code =
10962 12592 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10963 12593 status = DDI_FAILURE;
10964 12594 break;
10965 12595 }
10966 12596 status = mptsas_diag_read_buffer(mpt,
10967 12597 &diag_read_buffer, diag_action +
10968 12598 sizeof (diag_read_buffer) - 4, return_code,
10969 12599 ioctl_mode);
10970 12600 if (status == DDI_SUCCESS) {
10971 12601 if (ddi_copyout(&diag_read_buffer, diag_action,
10972 12602 sizeof (diag_read_buffer) - 4, ioctl_mode)
10973 12603 != 0) {
10974 12604 return (DDI_FAILURE);
10975 12605 }
10976 12606 }
10977 12607 break;
10978 12608
10979 12609 case MPTSAS_FW_DIAG_TYPE_RELEASE:
10980 12610 if (length < sizeof (diag_release)) {
10981 12611 *return_code =
10982 12612 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10983 12613 status = DDI_FAILURE;
10984 12614 break;
10985 12615 }
10986 12616 if (ddi_copyin(diag_action, &diag_release,
10987 12617 sizeof (diag_release), ioctl_mode) != 0) {
10988 12618 return (DDI_FAILURE);
10989 12619 }
10990 12620 status = mptsas_diag_release(mpt, &diag_release,
10991 12621 return_code);
10992 12622 break;
10993 12623
10994 12624 default:
10995 12625 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10996 12626 status = DDI_FAILURE;
10997 12627 break;
10998 12628 }
10999 12629
11000 12630 if ((status == DDI_FAILURE) &&
11001 12631 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
11002 12632 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
11003 12633 status = DDI_SUCCESS;
11004 12634 }
11005 12635
11006 12636 return (status);
11007 12637 }
11008 12638
11009 12639 static int
11010 12640 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
11011 12641 {
11012 12642 int status;
11013 12643 mptsas_diag_action_t driver_data;
11014 12644
11015 12645 ASSERT(mutex_owned(&mpt->m_mutex));
11016 12646
11017 12647 /*
11018 12648 * Copy the user data to a driver data buffer.
11019 12649 */
11020 12650 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
11021 12651 mode) == 0) {
11022 12652 /*
11023 12653 * Send diag action request if Action is valid
11024 12654 */
11025 12655 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
11026 12656 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
11027 12657 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
11028 12658 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
11029 12659 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
11030 12660 status = mptsas_do_diag_action(mpt, driver_data.Action,
11031 12661 (void *)(uintptr_t)driver_data.PtrDiagAction,
11032 12662 driver_data.Length, &driver_data.ReturnCode,
11033 12663 mode);
11034 12664 if (status == DDI_SUCCESS) {
11035 12665 if (ddi_copyout(&driver_data.ReturnCode,
11036 12666 &user_data->ReturnCode,
11037 12667 sizeof (user_data->ReturnCode), mode)
11038 12668 != 0) {
11039 12669 status = EFAULT;
11040 12670 } else {
11041 12671 status = 0;
11042 12672 }
11043 12673 } else {
11044 12674 status = EIO;
11045 12675 }
11046 12676 } else {
11047 12677 status = EINVAL;
11048 12678 }
11049 12679 } else {
11050 12680 status = EFAULT;
11051 12681 }
11052 12682
11053 12683 return (status);
11054 12684 }
11055 12685
11056 12686 /*
11057 12687 * This routine handles the "event query" ioctl.
11058 12688 */
11059 12689 static int
11060 12690 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
11061 12691 int *rval)
11062 12692 {
11063 12693 int status;
11064 12694 mptsas_event_query_t driverdata;
11065 12695 uint8_t i;
11066 12696
11067 12697 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
11068 12698
11069 12699 mutex_enter(&mpt->m_mutex);
11070 12700 for (i = 0; i < 4; i++) {
11071 12701 driverdata.Types[i] = mpt->m_event_mask[i];
11072 12702 }
11073 12703 mutex_exit(&mpt->m_mutex);
11074 12704
11075 12705 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
11076 12706 status = EFAULT;
11077 12707 } else {
11078 12708 *rval = MPTIOCTL_STATUS_GOOD;
11079 12709 status = 0;
11080 12710 }
11081 12711
11082 12712 return (status);
11083 12713 }
11084 12714
11085 12715 /*
11086 12716 * This routine handles the "event enable" ioctl.
11087 12717 */
11088 12718 static int
11089 12719 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
11090 12720 int *rval)
11091 12721 {
11092 12722 int status;
11093 12723 mptsas_event_enable_t driverdata;
11094 12724 uint8_t i;
11095 12725
11096 12726 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11097 12727 mutex_enter(&mpt->m_mutex);
11098 12728 for (i = 0; i < 4; i++) {
11099 12729 mpt->m_event_mask[i] = driverdata.Types[i];
11100 12730 }
11101 12731 mutex_exit(&mpt->m_mutex);
11102 12732
11103 12733 *rval = MPTIOCTL_STATUS_GOOD;
11104 12734 status = 0;
11105 12735 } else {
11106 12736 status = EFAULT;
11107 12737 }
11108 12738 return (status);
11109 12739 }
11110 12740
11111 12741 /*
11112 12742 * This routine handles the "event report" ioctl.
11113 12743 */
11114 12744 static int
11115 12745 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
11116 12746 int *rval)
11117 12747 {
11118 12748 int status;
11119 12749 mptsas_event_report_t driverdata;
11120 12750
11121 12751 mutex_enter(&mpt->m_mutex);
11122 12752
11123 12753 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
11124 12754 mode) == 0) {
11125 12755 if (driverdata.Size >= sizeof (mpt->m_events)) {
11126 12756 if (ddi_copyout(mpt->m_events, data->Events,
11127 12757 sizeof (mpt->m_events), mode) != 0) {
11128 12758 status = EFAULT;
11129 12759 } else {
11130 12760 if (driverdata.Size > sizeof (mpt->m_events)) {
11131 12761 driverdata.Size =
11132 12762 sizeof (mpt->m_events);
11133 12763 if (ddi_copyout(&driverdata.Size,
11134 12764 &data->Size,
11135 12765 sizeof (driverdata.Size),
11136 12766 mode) != 0) {
11137 12767 status = EFAULT;
11138 12768 } else {
11139 12769 *rval = MPTIOCTL_STATUS_GOOD;
11140 12770 status = 0;
11141 12771 }
11142 12772 } else {
11143 12773 *rval = MPTIOCTL_STATUS_GOOD;
11144 12774 status = 0;
11145 12775 }
11146 12776 }
11147 12777 } else {
11148 12778 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11149 12779 status = 0;
11150 12780 }
11151 12781 } else {
11152 12782 status = EFAULT;
11153 12783 }
11154 12784
11155 12785 mutex_exit(&mpt->m_mutex);
11156 12786 return (status);
11157 12787 }
11158 12788
11159 12789 static void
11160 12790 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11161 12791 {
11162 12792 int *reg_data;
11163 12793 uint_t reglen;
11164 12794
11165 12795 /*
11166 12796 * Lookup the 'reg' property and extract the other data
11167 12797 */
11168 12798 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11169 12799 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11170 12800 DDI_PROP_SUCCESS) {
11171 12801 /*
11172 12802 * Extract the PCI data from the 'reg' property first DWORD.
11173 12803 * The entry looks like the following:
11174 12804 * First DWORD:
11175 12805 * Bits 0 - 7 8-bit Register number
11176 12806 * Bits 8 - 10 3-bit Function number
11177 12807 * Bits 11 - 15 5-bit Device number
11178 12808 * Bits 16 - 23 8-bit Bus number
11179 12809 * Bits 24 - 25 2-bit Address Space type identifier
11180 12810 *
11181 12811 */
11182 12812 adapter_data->PciInformation.u.bits.BusNumber =
11183 12813 (reg_data[0] & 0x00FF0000) >> 16;
11184 12814 adapter_data->PciInformation.u.bits.DeviceNumber =
11185 12815 (reg_data[0] & 0x0000F800) >> 11;
11186 12816 adapter_data->PciInformation.u.bits.FunctionNumber =
11187 12817 (reg_data[0] & 0x00000700) >> 8;
11188 12818 ddi_prop_free((void *)reg_data);
11189 12819 } else {
11190 12820 /*
11191 12821 * If we can't determine the PCI data then we fill in FF's for
11192 12822 * the data to indicate this.
11193 12823 */
11194 12824 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
11195 12825 adapter_data->MpiPortNumber = 0xFFFFFFFF;
11196 12826 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
11197 12827 }
11198 12828
11199 12829 /*
11200 12830 * Saved in the mpt->m_fwversion
|
↓ open down ↓ |
727 lines elided |
↑ open up ↑ |
11201 12831 */
11202 12832 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
11203 12833 }
11204 12834
11205 12835 static void
11206 12836 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11207 12837 {
11208 12838 char *driver_verstr = MPTSAS_MOD_STRING;
11209 12839
11210 12840 mptsas_lookup_pci_data(mpt, adapter_data);
11211 - adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS2;
12841 + adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS3;
11212 12842 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
11213 12843 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
11214 12844 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
11215 12845 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
11216 12846 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
11217 12847 adapter_data->BiosVersion = 0;
11218 12848 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
11219 12849 }
11220 12850
11221 12851 static void
11222 12852 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
11223 12853 {
11224 12854 int *reg_data, i;
11225 12855 uint_t reglen;
11226 12856
11227 12857 /*
11228 12858 * Lookup the 'reg' property and extract the other data
11229 12859 */
11230 12860 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11231 12861 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11232 12862 DDI_PROP_SUCCESS) {
11233 12863 /*
11234 12864 * Extract the PCI data from the 'reg' property first DWORD.
11235 12865 * The entry looks like the following:
11236 12866 * First DWORD:
11237 12867 * Bits 8 - 10 3-bit Function number
11238 12868 * Bits 11 - 15 5-bit Device number
11239 12869 * Bits 16 - 23 8-bit Bus number
11240 12870 */
11241 12871 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
11242 12872 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
11243 12873 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
11244 12874 ddi_prop_free((void *)reg_data);
11245 12875 } else {
11246 12876 /*
11247 12877 * If we can't determine the PCI info then we fill in FF's for
11248 12878 * the data to indicate this.
11249 12879 */
11250 12880 pci_info->BusNumber = 0xFFFFFFFF;
11251 12881 pci_info->DeviceNumber = 0xFF;
11252 12882 pci_info->FunctionNumber = 0xFF;
11253 12883 }
11254 12884
11255 12885 /*
11256 12886 * Now get the interrupt vector and the pci header. The vector can
11257 12887 * only be 0 right now. The header is the first 256 bytes of config
11258 12888 * space.
11259 12889 */
11260 12890 pci_info->InterruptVector = 0;
11261 12891 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
11262 12892 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
11263 12893 i);
11264 12894 }
11265 12895 }
11266 12896
11267 12897 static int
11268 12898 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
11269 12899 {
11270 12900 int status = 0;
11271 12901 mptsas_reg_access_t driverdata;
11272 12902
11273 12903 mutex_enter(&mpt->m_mutex);
11274 12904 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11275 12905 switch (driverdata.Command) {
11276 12906 /*
11277 12907 * IO access is not supported.
11278 12908 */
11279 12909 case REG_IO_READ:
11280 12910 case REG_IO_WRITE:
11281 12911 mptsas_log(mpt, CE_WARN, "IO access is not "
11282 12912 "supported. Use memory access.");
11283 12913 status = EINVAL;
11284 12914 break;
11285 12915
11286 12916 case REG_MEM_READ:
11287 12917 driverdata.RegData = ddi_get32(mpt->m_datap,
11288 12918 (uint32_t *)(void *)mpt->m_reg +
11289 12919 driverdata.RegOffset);
11290 12920 if (ddi_copyout(&driverdata.RegData,
11291 12921 &data->RegData,
11292 12922 sizeof (driverdata.RegData), mode) != 0) {
11293 12923 mptsas_log(mpt, CE_WARN, "Register "
11294 12924 "Read Failed");
11295 12925 status = EFAULT;
11296 12926 }
11297 12927 break;
11298 12928
11299 12929 case REG_MEM_WRITE:
11300 12930 ddi_put32(mpt->m_datap,
11301 12931 (uint32_t *)(void *)mpt->m_reg +
11302 12932 driverdata.RegOffset,
11303 12933 driverdata.RegData);
11304 12934 break;
11305 12935
11306 12936 default:
11307 12937 status = EINVAL;
11308 12938 break;
11309 12939 }
11310 12940 } else {
11311 12941 status = EFAULT;
11312 12942 }
11313 12943
11314 12944 mutex_exit(&mpt->m_mutex);
11315 12945 return (status);
11316 12946 }
11317 12947
11318 12948 static int
11319 12949 led_control(mptsas_t *mpt, intptr_t data, int mode)
11320 12950 {
11321 12951 int ret = 0;
11322 12952 mptsas_led_control_t lc;
11323 12953 mptsas_target_t *ptgt;
11324 12954
11325 12955 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
11326 12956 return (EFAULT);
11327 12957 }
11328 12958
11329 12959 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
11330 12960 lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
11331 12961 lc.Led < MPTSAS_LEDCTL_LED_MIN ||
11332 12962 lc.Led > MPTSAS_LEDCTL_LED_MAX ||
11333 12963 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 &&
11334 12964 lc.LedStatus != 1)) {
11335 12965 return (EINVAL);
11336 12966 }
11337 12967
11338 12968 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) ||
11339 12969 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0))
11340 12970 return (EACCES);
11341 12971
11342 12972 /* Locate the target we're interrogating... */
11343 12973 mutex_enter(&mpt->m_mutex);
11344 12974 ptgt = refhash_linear_search(mpt->m_targets,
11345 12975 mptsas_target_eval_slot, &lc);
11346 12976 if (ptgt == NULL) {
11347 12977 /* We could not find a target for that enclosure/slot. */
11348 12978 mutex_exit(&mpt->m_mutex);
11349 12979 return (ENOENT);
11350 12980 }
11351 12981
11352 12982 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
11353 12983 /* Update our internal LED state. */
11354 12984 ptgt->m_led_status &= ~(1 << (lc.Led - 1));
11355 12985 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1);
11356 12986
11357 12987 /* Flush it to the controller. */
11358 12988 ret = mptsas_flush_led_status(mpt, ptgt);
11359 12989 mutex_exit(&mpt->m_mutex);
11360 12990 return (ret);
11361 12991 }
11362 12992
11363 12993 /* Return our internal LED state. */
11364 12994 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1;
11365 12995 mutex_exit(&mpt->m_mutex);
11366 12996
11367 12997 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
11368 12998 return (EFAULT);
11369 12999 }
11370 13000
11371 13001 return (0);
11372 13002 }
11373 13003
11374 13004 static int
11375 13005 get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
11376 13006 {
11377 13007 uint16_t i = 0;
11378 13008 uint16_t count = 0;
11379 13009 int ret = 0;
11380 13010 mptsas_target_t *ptgt;
11381 13011 mptsas_disk_info_t *di;
11382 13012 STRUCT_DECL(mptsas_get_disk_info, gdi);
11383 13013
11384 13014 if ((mode & FREAD) == 0)
11385 13015 return (EACCES);
11386 13016
11387 13017 STRUCT_INIT(gdi, get_udatamodel());
11388 13018
11389 13019 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
11390 13020 mode) != 0) {
11391 13021 return (EFAULT);
11392 13022 }
11393 13023
11394 13024 /* Find out how many targets there are. */
11395 13025 mutex_enter(&mpt->m_mutex);
11396 13026 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
11397 13027 ptgt = refhash_next(mpt->m_targets, ptgt)) {
11398 13028 count++;
11399 13029 }
11400 13030 mutex_exit(&mpt->m_mutex);
11401 13031
11402 13032 /*
11403 13033 * If we haven't been asked to copy out information on each target,
11404 13034 * then just return the count.
11405 13035 */
11406 13036 STRUCT_FSET(gdi, DiskCount, count);
11407 13037 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
11408 13038 goto copy_out;
11409 13039
11410 13040 /*
11411 13041 * If we haven't been given a large enough buffer to copy out into,
11412 13042 * let the caller know.
11413 13043 */
11414 13044 if (STRUCT_FGET(gdi, DiskInfoArraySize) <
11415 13045 count * sizeof (mptsas_disk_info_t)) {
11416 13046 ret = ENOSPC;
11417 13047 goto copy_out;
11418 13048 }
11419 13049
11420 13050 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
11421 13051
11422 13052 mutex_enter(&mpt->m_mutex);
11423 13053 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
11424 13054 ptgt = refhash_next(mpt->m_targets, ptgt)) {
11425 13055 if (i >= count) {
11426 13056 /*
11427 13057 * The number of targets changed while we weren't
11428 13058 * looking, so give up.
11429 13059 */
11430 13060 refhash_rele(mpt->m_targets, ptgt);
11431 13061 mutex_exit(&mpt->m_mutex);
11432 13062 kmem_free(di, count * sizeof (mptsas_disk_info_t));
11433 13063 return (EAGAIN);
11434 13064 }
11435 13065 di[i].Instance = mpt->m_instance;
11436 13066 di[i].Enclosure = ptgt->m_enclosure;
11437 13067 di[i].Slot = ptgt->m_slot_num;
11438 13068 di[i].SasAddress = ptgt->m_addr.mta_wwn;
11439 13069 i++;
11440 13070 }
11441 13071 mutex_exit(&mpt->m_mutex);
11442 13072 STRUCT_FSET(gdi, DiskCount, i);
11443 13073
11444 13074 /* Copy out the disk information to the caller. */
11445 13075 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
11446 13076 i * sizeof (mptsas_disk_info_t), mode) != 0) {
11447 13077 ret = EFAULT;
11448 13078 }
11449 13079
11450 13080 kmem_free(di, count * sizeof (mptsas_disk_info_t));
11451 13081
11452 13082 copy_out:
11453 13083 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
11454 13084 mode) != 0) {
11455 13085 ret = EFAULT;
11456 13086 }
11457 13087
11458 13088 return (ret);
11459 13089 }
11460 13090
11461 13091 static int
11462 13092 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
11463 13093 int *rval)
11464 13094 {
11465 13095 int status = 0;
11466 13096 mptsas_t *mpt;
11467 13097 mptsas_update_flash_t flashdata;
11468 13098 mptsas_pass_thru_t passthru_data;
11469 13099 mptsas_adapter_data_t adapter_data;
11470 13100 mptsas_pci_info_t pci_info;
11471 13101 int copylen;
11472 13102
11473 13103 int iport_flag = 0;
11474 13104 dev_info_t *dip = NULL;
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11475 13105 mptsas_phymask_t phymask = 0;
11476 13106 struct devctl_iocdata *dcp = NULL;
11477 13107 char *addr = NULL;
11478 13108 mptsas_target_t *ptgt = NULL;
11479 13109
11480 13110 *rval = MPTIOCTL_STATUS_GOOD;
11481 13111 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
11482 13112 return (EPERM);
11483 13113 }
11484 13114
11485 - mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
13115 + mpt = ddi_get_soft_state(mptsas3_state, MINOR2INST(getminor(dev)));
11486 13116 if (mpt == NULL) {
11487 13117 /*
11488 13118 * Called from iport node, get the states
11489 13119 */
11490 13120 iport_flag = 1;
11491 13121 dip = mptsas_get_dip_from_dev(dev, &phymask);
11492 13122 if (dip == NULL) {
11493 13123 return (ENXIO);
11494 13124 }
11495 13125 mpt = DIP2MPT(dip);
11496 13126 }
11497 13127 /* Make sure power level is D0 before accessing registers */
11498 13128 mutex_enter(&mpt->m_mutex);
11499 13129 if (mpt->m_options & MPTSAS_OPT_PM) {
11500 13130 (void) pm_busy_component(mpt->m_dip, 0);
11501 13131 if (mpt->m_power_level != PM_LEVEL_D0) {
11502 13132 mutex_exit(&mpt->m_mutex);
11503 13133 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
11504 13134 DDI_SUCCESS) {
11505 13135 mptsas_log(mpt, CE_WARN,
11506 - "mptsas%d: mptsas_ioctl: Raise power "
13136 + "mptsas3%d: mptsas_ioctl: Raise power "
11507 13137 "request failed.", mpt->m_instance);
11508 13138 (void) pm_idle_component(mpt->m_dip, 0);
11509 13139 return (ENXIO);
11510 13140 }
11511 13141 } else {
11512 13142 mutex_exit(&mpt->m_mutex);
11513 13143 }
11514 13144 } else {
11515 13145 mutex_exit(&mpt->m_mutex);
11516 13146 }
11517 13147
11518 13148 if (iport_flag) {
11519 13149 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
11520 13150 if (status != 0) {
11521 13151 goto out;
11522 13152 }
11523 13153 /*
11524 13154 * The following code control the OK2RM LED, it doesn't affect
11525 13155 * the ioctl return status.
11526 13156 */
11527 13157 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
11528 13158 (cmd == DEVCTL_DEVICE_OFFLINE)) {
11529 13159 if (ndi_dc_allochdl((void *)data, &dcp) !=
11530 13160 NDI_SUCCESS) {
11531 13161 goto out;
11532 13162 }
11533 13163 addr = ndi_dc_getaddr(dcp);
11534 13164 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
11535 13165 if (ptgt == NULL) {
11536 13166 NDBG14(("mptsas_ioctl led control: tgt %s not "
11537 13167 "found", addr));
11538 13168 ndi_dc_freehdl(dcp);
11539 13169 goto out;
11540 13170 }
11541 13171 mutex_enter(&mpt->m_mutex);
11542 13172 if (cmd == DEVCTL_DEVICE_ONLINE) {
11543 13173 ptgt->m_tgt_unconfigured = 0;
11544 13174 } else if (cmd == DEVCTL_DEVICE_OFFLINE) {
11545 13175 ptgt->m_tgt_unconfigured = 1;
11546 13176 }
11547 13177 if (cmd == DEVCTL_DEVICE_OFFLINE) {
11548 13178 ptgt->m_led_status |=
11549 13179 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
11550 13180 } else {
11551 13181 ptgt->m_led_status &=
11552 13182 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
11553 13183 }
11554 13184 (void) mptsas_flush_led_status(mpt, ptgt);
11555 13185 mutex_exit(&mpt->m_mutex);
11556 13186 ndi_dc_freehdl(dcp);
11557 13187 }
11558 13188 goto out;
11559 13189 }
11560 13190 switch (cmd) {
11561 13191 case MPTIOCTL_GET_DISK_INFO:
11562 13192 status = get_disk_info(mpt, data, mode);
11563 13193 break;
11564 13194 case MPTIOCTL_LED_CONTROL:
11565 13195 status = led_control(mpt, data, mode);
11566 13196 break;
11567 13197 case MPTIOCTL_UPDATE_FLASH:
11568 13198 if (ddi_copyin((void *)data, &flashdata,
11569 13199 sizeof (struct mptsas_update_flash), mode)) {
11570 13200 status = EFAULT;
11571 13201 break;
11572 13202 }
11573 13203
11574 13204 mutex_enter(&mpt->m_mutex);
11575 13205 if (mptsas_update_flash(mpt,
11576 13206 (caddr_t)(long)flashdata.PtrBuffer,
11577 13207 flashdata.ImageSize, flashdata.ImageType, mode)) {
11578 13208 status = EFAULT;
11579 13209 }
11580 13210
11581 13211 /*
11582 13212 * Reset the chip to start using the new
11583 13213 * firmware. Reset if failed also.
11584 13214 */
11585 13215 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
11586 13216 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
11587 13217 status = EFAULT;
11588 13218 }
11589 13219 mutex_exit(&mpt->m_mutex);
11590 13220 break;
11591 13221 case MPTIOCTL_PASS_THRU:
11592 13222 /*
11593 13223 * The user has requested to pass through a command to
11594 13224 * be executed by the MPT firmware. Call our routine
11595 13225 * which does this. Only allow one passthru IOCTL at
11596 13226 * one time. Other threads will block on
11597 13227 * m_passthru_mutex, which is of adaptive variant.
11598 13228 */
11599 13229 if (ddi_copyin((void *)data, &passthru_data,
11600 13230 sizeof (mptsas_pass_thru_t), mode)) {
11601 13231 status = EFAULT;
11602 13232 break;
11603 13233 }
11604 13234 mutex_enter(&mpt->m_passthru_mutex);
11605 13235 mutex_enter(&mpt->m_mutex);
11606 13236 status = mptsas_pass_thru(mpt, &passthru_data, mode);
11607 13237 mutex_exit(&mpt->m_mutex);
11608 13238 mutex_exit(&mpt->m_passthru_mutex);
11609 13239
11610 13240 break;
11611 13241 case MPTIOCTL_GET_ADAPTER_DATA:
11612 13242 /*
11613 13243 * The user has requested to read adapter data. Call
11614 13244 * our routine which does this.
11615 13245 */
11616 13246 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
11617 13247 if (ddi_copyin((void *)data, (void *)&adapter_data,
11618 13248 sizeof (mptsas_adapter_data_t), mode)) {
11619 13249 status = EFAULT;
11620 13250 break;
11621 13251 }
11622 13252 if (adapter_data.StructureLength >=
11623 13253 sizeof (mptsas_adapter_data_t)) {
11624 13254 adapter_data.StructureLength = (uint32_t)
11625 13255 sizeof (mptsas_adapter_data_t);
11626 13256 copylen = sizeof (mptsas_adapter_data_t);
11627 13257 mutex_enter(&mpt->m_mutex);
11628 13258 mptsas_read_adapter_data(mpt, &adapter_data);
11629 13259 mutex_exit(&mpt->m_mutex);
11630 13260 } else {
11631 13261 adapter_data.StructureLength = (uint32_t)
11632 13262 sizeof (mptsas_adapter_data_t);
11633 13263 copylen = sizeof (adapter_data.StructureLength);
11634 13264 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11635 13265 }
11636 13266 if (ddi_copyout((void *)(&adapter_data), (void *)data,
11637 13267 copylen, mode) != 0) {
11638 13268 status = EFAULT;
11639 13269 }
11640 13270 break;
11641 13271 case MPTIOCTL_GET_PCI_INFO:
11642 13272 /*
11643 13273 * The user has requested to read pci info. Call
11644 13274 * our routine which does this.
11645 13275 */
11646 13276 bzero(&pci_info, sizeof (mptsas_pci_info_t));
11647 13277 mutex_enter(&mpt->m_mutex);
11648 13278 mptsas_read_pci_info(mpt, &pci_info);
11649 13279 mutex_exit(&mpt->m_mutex);
11650 13280 if (ddi_copyout((void *)(&pci_info), (void *)data,
11651 13281 sizeof (mptsas_pci_info_t), mode) != 0) {
11652 13282 status = EFAULT;
11653 13283 }
11654 13284 break;
11655 13285 case MPTIOCTL_RESET_ADAPTER:
11656 13286 mutex_enter(&mpt->m_mutex);
11657 13287 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
11658 13288 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
11659 13289 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
11660 13290 "failed");
11661 13291 status = EFAULT;
11662 13292 }
11663 13293 mutex_exit(&mpt->m_mutex);
11664 13294 break;
11665 13295 case MPTIOCTL_DIAG_ACTION:
11666 13296 /*
11667 13297 * The user has done a diag buffer action. Call our
11668 13298 * routine which does this. Only allow one diag action
11669 13299 * at one time.
11670 13300 */
11671 13301 mutex_enter(&mpt->m_mutex);
11672 13302 if (mpt->m_diag_action_in_progress) {
11673 13303 mutex_exit(&mpt->m_mutex);
11674 13304 return (EBUSY);
11675 13305 }
11676 13306 mpt->m_diag_action_in_progress = 1;
11677 13307 status = mptsas_diag_action(mpt,
11678 13308 (mptsas_diag_action_t *)data, mode);
11679 13309 mpt->m_diag_action_in_progress = 0;
11680 13310 mutex_exit(&mpt->m_mutex);
11681 13311 break;
11682 13312 case MPTIOCTL_EVENT_QUERY:
11683 13313 /*
11684 13314 * The user has done an event query. Call our routine
11685 13315 * which does this.
11686 13316 */
11687 13317 status = mptsas_event_query(mpt,
11688 13318 (mptsas_event_query_t *)data, mode, rval);
11689 13319 break;
11690 13320 case MPTIOCTL_EVENT_ENABLE:
11691 13321 /*
11692 13322 * The user has done an event enable. Call our routine
11693 13323 * which does this.
11694 13324 */
11695 13325 status = mptsas_event_enable(mpt,
11696 13326 (mptsas_event_enable_t *)data, mode, rval);
11697 13327 break;
11698 13328 case MPTIOCTL_EVENT_REPORT:
11699 13329 /*
11700 13330 * The user has done an event report. Call our routine
11701 13331 * which does this.
11702 13332 */
11703 13333 status = mptsas_event_report(mpt,
11704 13334 (mptsas_event_report_t *)data, mode, rval);
11705 13335 break;
11706 13336 case MPTIOCTL_REG_ACCESS:
11707 13337 /*
11708 13338 * The user has requested register access. Call our
11709 13339 * routine which does this.
11710 13340 */
11711 13341 status = mptsas_reg_access(mpt,
11712 13342 (mptsas_reg_access_t *)data, mode);
11713 13343 break;
11714 13344 default:
11715 13345 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
11716 13346 rval);
11717 13347 break;
11718 13348 }
11719 13349
11720 13350 out:
11721 13351 return (status);
11722 13352 }
11723 13353
11724 13354 int
11725 13355 mptsas_restart_ioc(mptsas_t *mpt)
11726 13356 {
11727 13357 int rval = DDI_SUCCESS;
11728 13358 mptsas_target_t *ptgt = NULL;
11729 13359
11730 13360 ASSERT(mutex_owned(&mpt->m_mutex));
11731 13361
11732 13362 /*
11733 13363 * Set a flag telling I/O path that we're processing a reset. This is
11734 13364 * needed because after the reset is complete, the hash table still
11735 13365 * needs to be rebuilt. If I/Os are started before the hash table is
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219 lines elided |
↑ open up ↑ |
11736 13366 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
11737 13367 * so that they can be retried.
11738 13368 */
11739 13369 mpt->m_in_reset = TRUE;
11740 13370
11741 13371 /*
11742 13372 * Set all throttles to HOLD
11743 13373 */
11744 13374 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
11745 13375 ptgt = refhash_next(mpt->m_targets, ptgt)) {
11746 - mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
13376 + mptsas_set_throttle_mtx(mpt, ptgt, HOLD_THROTTLE);
11747 13377 }
11748 13378
11749 13379 /*
11750 13380 * Disable interrupts
11751 13381 */
11752 13382 MPTSAS_DISABLE_INTR(mpt);
11753 13383
11754 13384 /*
11755 13385 * Abort all commands: outstanding commands, commands in waitq and
11756 13386 * tx_waitq.
11757 13387 */
11758 13388 mptsas_flush_hba(mpt);
11759 13389
11760 13390 /*
11761 13391 * Reinitialize the chip.
11762 13392 */
11763 13393 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
11764 13394 rval = DDI_FAILURE;
11765 13395 }
11766 13396
11767 13397 /*
11768 13398 * Enable interrupts again
11769 13399 */
11770 13400 MPTSAS_ENABLE_INTR(mpt);
11771 13401
11772 13402 /*
11773 13403 * If mptsas_init_chip was successful, update the driver data.
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17 lines elided |
↑ open up ↑ |
11774 13404 */
11775 13405 if (rval == DDI_SUCCESS) {
11776 13406 mptsas_update_driver_data(mpt);
11777 13407 }
11778 13408
11779 13409 /*
11780 13410 * Reset the throttles
11781 13411 */
11782 13412 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
11783 13413 ptgt = refhash_next(mpt->m_targets, ptgt)) {
11784 - mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
13414 + mptsas_set_throttle_mtx(mpt, ptgt, MAX_THROTTLE);
11785 13415 }
11786 13416
11787 13417 mptsas_doneq_empty(mpt);
11788 13418 mptsas_restart_hba(mpt);
11789 13419
11790 13420 if (rval != DDI_SUCCESS) {
11791 13421 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
11792 13422 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
11793 13423 }
11794 13424
11795 13425 /*
11796 13426 * Clear the reset flag so that I/Os can continue.
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2 lines elided |
↑ open up ↑ |
11797 13427 */
11798 13428 mpt->m_in_reset = FALSE;
11799 13429
11800 13430 return (rval);
11801 13431 }
11802 13432
11803 13433 static int
11804 13434 mptsas_init_chip(mptsas_t *mpt, int first_time)
11805 13435 {
11806 13436 ddi_dma_cookie_t cookie;
11807 - uint32_t i;
13437 + mptsas_reply_pqueue_t *rpqp;
13438 + uint32_t i, j;
11808 13439 int rval;
11809 13440
11810 13441 /*
11811 13442 * Check to see if the firmware image is valid
11812 13443 */
11813 13444 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
11814 13445 MPI2_DIAG_FLASH_BAD_SIG) {
11815 13446 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
11816 13447 goto fail;
11817 13448 }
11818 13449
11819 13450 /*
11820 13451 * Reset the chip
11821 13452 */
11822 13453 rval = mptsas_ioc_reset(mpt, first_time);
11823 13454 if (rval == MPTSAS_RESET_FAIL) {
11824 13455 mptsas_log(mpt, CE_WARN, "hard reset failed!");
11825 13456 goto fail;
11826 13457 }
11827 13458
11828 13459 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
11829 13460 goto mur;
11830 13461 }
11831 13462 /*
11832 13463 * Setup configuration space
11833 13464 */
11834 13465 if (mptsas_config_space_init(mpt) == FALSE) {
11835 13466 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
11836 13467 "failed!");
11837 13468 goto fail;
11838 13469 }
11839 13470
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22 lines elided |
↑ open up ↑ |
11840 13471 /*
11841 13472 * IOC facts can change after a diag reset so all buffers that are
11842 13473 * based on these numbers must be de-allocated and re-allocated. Get
11843 13474 * new IOC facts each time chip is initialized.
11844 13475 */
11845 13476 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
11846 13477 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
11847 13478 goto fail;
11848 13479 }
11849 13480
13481 + /*
13482 + * Now we know chip MSIX capabilitites and it's not been done
13483 + * previously register interrupts accordingly. Need to know this
13484 + * information before allocating the reply frames below.
13485 + */
13486 + if (mpt->m_intr_cnt == 0) {
13487 + if (mptsas_register_intrs(mpt) == FALSE)
13488 + goto fail;
13489 + }
13490 +
11850 13491 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT,
11851 13492 mptsas_target_addr_hash, mptsas_target_addr_cmp,
11852 13493 mptsas_target_free, sizeof (mptsas_target_t),
11853 13494 offsetof(mptsas_target_t, m_link),
11854 13495 offsetof(mptsas_target_t, m_addr), KM_SLEEP);
11855 13496
11856 13497 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
11857 13498 goto fail;
11858 13499 }
11859 13500 /*
11860 13501 * Allocate request message frames, reply free queue, reply descriptor
11861 13502 * post queue, and reply message frames using latest IOC facts.
11862 13503 */
11863 13504 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
11864 13505 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
11865 13506 goto fail;
11866 13507 }
13508 + if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) {
13509 + mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed");
13510 + goto fail;
13511 + }
11867 13512 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
11868 13513 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
11869 13514 goto fail;
11870 13515 }
11871 13516 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
11872 13517 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
11873 13518 goto fail;
11874 13519 }
11875 13520 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
11876 13521 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
11877 13522 goto fail;
11878 13523 }
11879 13524
11880 13525 mur:
11881 13526 /*
|
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5 lines elided |
↑ open up ↑ |
11882 13527 * Re-Initialize ioc to operational state
11883 13528 */
11884 13529 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
11885 13530 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
11886 13531 goto fail;
11887 13532 }
11888 13533
11889 13534 mptsas_alloc_reply_args(mpt);
11890 13535
11891 13536 /*
11892 - * Initialize reply post index. Reply free index is initialized after
11893 - * the next loop.
11894 - */
11895 - mpt->m_post_index = 0;
11896 -
11897 - /*
11898 13537 * Initialize the Reply Free Queue with the physical addresses of our
11899 13538 * reply frames.
11900 13539 */
11901 - cookie.dmac_address = mpt->m_reply_frame_dma_addr;
13540 + cookie.dmac_address = mpt->m_reply_frame_dma_addr&0xfffffffful;
11902 13541 for (i = 0; i < mpt->m_max_replies; i++) {
11903 13542 ddi_put32(mpt->m_acc_free_queue_hdl,
11904 13543 &((uint32_t *)(void *)mpt->m_free_queue)[i],
11905 13544 cookie.dmac_address);
11906 13545 cookie.dmac_address += mpt->m_reply_frame_size;
11907 13546 }
11908 13547 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11909 13548 DDI_DMA_SYNC_FORDEV);
11910 13549
11911 13550 /*
11912 13551 * Initialize the reply free index to one past the last frame on the
11913 13552 * queue. This will signify that the queue is empty to start with.
11914 13553 */
11915 13554 mpt->m_free_index = i;
11916 13555 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
11917 13556
11918 13557 /*
11919 - * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
13558 + * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's
13559 + * and the indexes to 0.
11920 13560 */
11921 - for (i = 0; i < mpt->m_post_queue_depth; i++) {
11922 - ddi_put64(mpt->m_acc_post_queue_hdl,
11923 - &((uint64_t *)(void *)mpt->m_post_queue)[i],
11924 - 0xFFFFFFFFFFFFFFFF);
13561 + rpqp = mpt->m_rep_post_queues;
13562 + for (j = 0; j < mpt->m_post_reply_qcount; j++) {
13563 + for (i = 0; i < mpt->m_post_queue_depth; i++) {
13564 + ddi_put64(mpt->m_acc_post_queue_hdl,
13565 + &((uint64_t *)(void *)rpqp->rpq_queue)[i],
13566 + 0xFFFFFFFFFFFFFFFF);
13567 + }
13568 + rpqp->rpq_index = 0;
13569 + rpqp++;
11925 13570 }
11926 13571 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
11927 13572 DDI_DMA_SYNC_FORDEV);
11928 13573
11929 13574 /*
13575 + * Initialise all the reply post queue indexes.
13576 + */
13577 + for (j = 0; j < mpt->m_post_reply_qcount; j++) {
13578 + ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyPostHostIndex,
13579 + j << MPI2_RPHI_MSIX_INDEX_SHIFT);
13580 + }
13581 +
13582 + /*
11930 13583 * Enable ports
11931 13584 */
11932 13585 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
11933 13586 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
11934 13587 goto fail;
11935 13588 }
11936 13589
11937 13590 /*
11938 13591 * enable events
11939 13592 */
11940 13593 if (mptsas_ioc_enable_event_notification(mpt)) {
13594 + mptsas_log(mpt, CE_WARN,
13595 + "mptsas_ioc_enable_event_notification failed");
11941 13596 goto fail;
11942 13597 }
11943 13598
11944 13599 /*
11945 13600 * We need checks in attach and these.
11946 13601 * chip_init is called in mult. places
11947 13602 */
11948 13603
11949 13604 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
11950 13605 DDI_SUCCESS) ||
13606 + (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
13607 + DDI_SUCCESS) ||
11951 13608 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
11952 13609 DDI_SUCCESS) ||
11953 13610 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
11954 13611 DDI_SUCCESS) ||
11955 13612 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
11956 13613 DDI_SUCCESS) ||
11957 13614 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
11958 13615 DDI_SUCCESS)) {
11959 13616 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11960 13617 goto fail;
11961 13618 }
11962 13619
11963 13620 /* Check all acc handles */
11964 13621 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
11965 13622 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
11966 13623 DDI_SUCCESS) ||
13624 + (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
13625 + DDI_SUCCESS) ||
11967 13626 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
11968 13627 DDI_SUCCESS) ||
11969 13628 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
11970 13629 DDI_SUCCESS) ||
11971 13630 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
11972 13631 DDI_SUCCESS) ||
11973 13632 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
11974 13633 DDI_SUCCESS) ||
11975 13634 (mptsas_check_acc_handle(mpt->m_config_handle) !=
11976 13635 DDI_SUCCESS)) {
11977 13636 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11978 13637 goto fail;
11979 13638 }
11980 13639
11981 13640 return (DDI_SUCCESS);
11982 13641
11983 13642 fail:
11984 13643 return (DDI_FAILURE);
11985 13644 }
11986 13645
11987 13646 static int
11988 13647 mptsas_get_pci_cap(mptsas_t *mpt)
11989 13648 {
11990 13649 ushort_t caps_ptr, cap, cap_count;
11991 13650
11992 13651 if (mpt->m_config_handle == NULL)
11993 13652 return (FALSE);
11994 13653 /*
11995 13654 * Check if capabilities list is supported and if so,
11996 13655 * get initial capabilities pointer and clear bits 0,1.
11997 13656 */
11998 13657 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
11999 13658 & PCI_STAT_CAP) {
12000 13659 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12001 13660 PCI_CONF_CAP_PTR), 4);
12002 13661 } else {
12003 13662 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
12004 13663 }
12005 13664
12006 13665 /*
12007 13666 * Walk capabilities if supported.
12008 13667 */
12009 13668 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
12010 13669
12011 13670 /*
12012 13671 * Check that we haven't exceeded the maximum number of
12013 13672 * capabilities and that the pointer is in a valid range.
12014 13673 */
12015 13674 if (++cap_count > 48) {
12016 13675 mptsas_log(mpt, CE_WARN,
12017 13676 "too many device capabilities.\n");
12018 13677 break;
12019 13678 }
12020 13679 if (caps_ptr < 64) {
12021 13680 mptsas_log(mpt, CE_WARN,
12022 13681 "capabilities pointer 0x%x out of range.\n",
12023 13682 caps_ptr);
12024 13683 break;
|
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↑ open up ↑ |
12025 13684 }
12026 13685
12027 13686 /*
12028 13687 * Get next capability and check that it is valid.
12029 13688 * For now, we only support power management.
12030 13689 */
12031 13690 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
12032 13691 switch (cap) {
12033 13692 case PCI_CAP_ID_PM:
12034 13693 mptsas_log(mpt, CE_NOTE,
12035 - "?mptsas%d supports power management.\n",
13694 + "?mptsas3%d supports power management.\n",
12036 13695 mpt->m_instance);
12037 13696 mpt->m_options |= MPTSAS_OPT_PM;
12038 13697
12039 13698 /* Save PMCSR offset */
12040 13699 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
12041 13700 break;
13701 + case PCI_CAP_ID_MSI:
13702 + mptsas_log(mpt, CE_NOTE,
13703 + "?mptsas3%d supports MSI.\n",
13704 + mpt->m_instance);
13705 + mpt->m_options |= MPTSAS_OPT_MSI;
13706 + break;
13707 + case PCI_CAP_ID_MSI_X:
13708 + mptsas_log(mpt, CE_NOTE,
13709 + "?mptsas3%d supports MSI-X.\n",
13710 + mpt->m_instance);
13711 + mpt->m_options |= MPTSAS_OPT_MSI_X;
13712 + break;
12042 13713 /*
12043 13714 * The following capabilities are valid. Any others
12044 13715 * will cause a message to be logged.
12045 13716 */
12046 13717 case PCI_CAP_ID_VPD:
12047 - case PCI_CAP_ID_MSI:
12048 13718 case PCI_CAP_ID_PCIX:
12049 13719 case PCI_CAP_ID_PCI_E:
12050 - case PCI_CAP_ID_MSI_X:
12051 13720 break;
12052 13721 default:
12053 13722 mptsas_log(mpt, CE_NOTE,
12054 - "?mptsas%d unrecognized capability "
13723 + "?mptsas3%d unrecognized capability "
12055 13724 "0x%x.\n", mpt->m_instance, cap);
12056 13725 break;
12057 13726 }
12058 13727
12059 13728 /*
12060 13729 * Get next capabilities pointer and clear bits 0,1.
12061 13730 */
12062 13731 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12063 13732 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
12064 13733 }
12065 13734 return (TRUE);
12066 13735 }
12067 13736
12068 13737 static int
12069 13738 mptsas_init_pm(mptsas_t *mpt)
|
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5 lines elided |
↑ open up ↑ |
12070 13739 {
12071 13740 char pmc_name[16];
12072 13741 char *pmc[] = {
12073 13742 NULL,
12074 13743 "0=Off (PCI D3 State)",
12075 13744 "3=On (PCI D0 State)",
12076 13745 NULL
12077 13746 };
12078 13747 uint16_t pmcsr_stat;
12079 13748
12080 - if (mptsas_get_pci_cap(mpt) == FALSE) {
12081 - return (DDI_FAILURE);
12082 - }
12083 13749 /*
12084 13750 * If PCI's capability does not support PM, then don't need
12085 13751 * to registe the pm-components
12086 13752 */
12087 13753 if (!(mpt->m_options & MPTSAS_OPT_PM))
12088 13754 return (DDI_SUCCESS);
12089 13755 /*
12090 13756 * If power management is supported by this chip, create
12091 13757 * pm-components property for the power management framework
12092 13758 */
12093 - (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
13759 + (void) sprintf(pmc_name, "NAME=mptsas3%d", mpt->m_instance);
12094 13760 pmc[0] = pmc_name;
12095 13761 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
12096 13762 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
12097 13763 mpt->m_options &= ~MPTSAS_OPT_PM;
12098 13764 mptsas_log(mpt, CE_WARN,
12099 - "mptsas%d: pm-component property creation failed.",
13765 + "mptsas3%d: pm-component property creation failed.",
12100 13766 mpt->m_instance);
12101 13767 return (DDI_FAILURE);
12102 13768 }
12103 13769
12104 13770 /*
12105 13771 * Power on device.
12106 13772 */
12107 13773 (void) pm_busy_component(mpt->m_dip, 0);
12108 13774 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
12109 13775 mpt->m_pmcsr_offset);
12110 13776 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
12111 - mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
13777 + mptsas_log(mpt, CE_WARN, "mptsas3%d: Power up the device",
12112 13778 mpt->m_instance);
12113 13779 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
12114 13780 PCI_PMCSR_D0);
12115 13781 }
12116 13782 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
12117 13783 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
12118 13784 return (DDI_FAILURE);
12119 13785 }
12120 13786 mpt->m_power_level = PM_LEVEL_D0;
12121 13787 /*
12122 13788 * Set pm idle delay.
12123 13789 */
12124 13790 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
12125 13791 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
12126 13792
12127 13793 return (DDI_SUCCESS);
12128 13794 }
12129 13795
12130 13796 static int
12131 13797 mptsas_register_intrs(mptsas_t *mpt)
12132 13798 {
12133 13799 dev_info_t *dip;
12134 13800 int intr_types;
12135 13801
12136 13802 dip = mpt->m_dip;
12137 13803
|
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16 lines elided |
↑ open up ↑ |
12138 13804 /* Get supported interrupt types */
12139 13805 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
12140 13806 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
12141 13807 "failed\n");
12142 13808 return (FALSE);
12143 13809 }
12144 13810
12145 13811 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
12146 13812
12147 13813 /*
13814 + * Try MSIX first.
13815 + */
13816 + if (mptsas_enable_msix && (intr_types & DDI_INTR_TYPE_MSIX)) {
13817 + if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSIX) == DDI_SUCCESS) {
13818 + NDBG6(("Using MSI-X interrupt type"));
13819 + mpt->m_intr_type = DDI_INTR_TYPE_MSIX;
13820 + return (TRUE);
13821 + }
13822 + }
13823 +
13824 + /*
12148 13825 * Try MSI, but fall back to FIXED
12149 13826 */
12150 13827 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
12151 13828 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
12152 - NDBG0(("Using MSI interrupt type"));
13829 + NDBG6(("Using MSI interrupt type"));
12153 13830 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
12154 13831 return (TRUE);
12155 13832 }
12156 13833 }
12157 13834 if (intr_types & DDI_INTR_TYPE_FIXED) {
12158 13835 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
12159 - NDBG0(("Using FIXED interrupt type"));
13836 + NDBG6(("Using FIXED interrupt type"));
12160 13837 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
12161 13838 return (TRUE);
12162 13839 } else {
12163 - NDBG0(("FIXED interrupt registration failed"));
13840 + NDBG6(("FIXED interrupt registration failed"));
12164 13841 return (FALSE);
12165 13842 }
12166 13843 }
12167 13844
12168 13845 return (FALSE);
12169 13846 }
12170 13847
12171 13848 static void
12172 13849 mptsas_unregister_intrs(mptsas_t *mpt)
12173 13850 {
12174 13851 mptsas_rem_intrs(mpt);
12175 13852 }
12176 13853
12177 13854 /*
12178 13855 * mptsas_add_intrs:
12179 13856 *
12180 13857 * Register FIXED or MSI interrupts.
12181 13858 */
12182 13859 static int
12183 13860 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
12184 13861 {
12185 13862 dev_info_t *dip = mpt->m_dip;
12186 13863 int avail, actual, count = 0;
12187 13864 int i, flag, ret;
12188 13865
12189 13866 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
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↑ open up ↑ |
12190 13867
12191 13868 /* Get number of interrupts */
12192 13869 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
12193 13870 if ((ret != DDI_SUCCESS) || (count <= 0)) {
12194 13871 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
12195 13872 "ret %d count %d\n", ret, count);
12196 13873
12197 13874 return (DDI_FAILURE);
12198 13875 }
12199 13876
12200 - /* Get number of available interrupts */
13877 + /* Get number of interrupts available to this device */
12201 13878 ret = ddi_intr_get_navail(dip, intr_type, &avail);
12202 13879 if ((ret != DDI_SUCCESS) || (avail == 0)) {
12203 13880 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
12204 13881 "ret %d avail %d\n", ret, avail);
12205 13882
12206 13883 return (DDI_FAILURE);
12207 13884 }
12208 13885
12209 - if (avail < count) {
13886 + if (count < avail) {
12210 13887 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
12211 13888 "navail() returned %d", count, avail);
12212 13889 }
12213 13890
12214 - /* Mpt only have one interrupt routine */
12215 - if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
12216 - count = 1;
13891 + NDBG6(("mptsas_add_intrs:count %d, avail %d", count, avail));
13892 +
13893 + if (intr_type == DDI_INTR_TYPE_MSIX) {
13894 + if (!mptsas3_max_msix_intrs) {
13895 + return (DDI_FAILURE);
13896 + }
13897 +
13898 + /*
13899 + * Restrict the number of interrupts, firstly by
13900 + * the number returned from the IOCInfo, then by
13901 + * overall restriction.
13902 + */
13903 + if (avail > mpt->m_max_msix_vectors) {
13904 + avail = mpt->m_max_msix_vectors?
13905 + mpt->m_max_msix_vectors:1;
13906 + NDBG6(("mptsas_add_intrs: mmmv avail %d", avail));
13907 + }
13908 + if (avail > mptsas3_max_msix_intrs) {
13909 + avail = mptsas3_max_msix_intrs;
13910 + NDBG6(("mptsas_add_intrs: m3mmi avail %d", avail));
13911 + }
13912 + }
13913 + if (intr_type == DDI_INTR_TYPE_MSI) {
13914 + NDBG6(("mptsas_add_intrs: MSI avail %d", avail));
13915 + avail = 1;
12217 13916 }
12218 13917
12219 13918 /* Allocate an array of interrupt handles */
12220 - mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
13919 + mpt->m_intr_size = avail * sizeof (ddi_intr_handle_t);
12221 13920 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
12222 13921
12223 13922 flag = DDI_INTR_ALLOC_NORMAL;
12224 13923
12225 13924 /* call ddi_intr_alloc() */
12226 13925 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
12227 - count, &actual, flag);
13926 + avail, &actual, flag);
12228 13927
12229 13928 if ((ret != DDI_SUCCESS) || (actual == 0)) {
12230 13929 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
12231 13930 ret);
12232 13931 kmem_free(mpt->m_htable, mpt->m_intr_size);
12233 13932 return (DDI_FAILURE);
12234 13933 }
12235 13934
13935 + NDBG6(("mptsas_add_intrs: actual %d, avail %d", actual, avail));
12236 13936 /* use interrupt count returned or abort? */
12237 - if (actual < count) {
12238 - mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
12239 - count, actual);
13937 + if (actual < avail) {
13938 + mptsas_log(mpt, CE_NOTE,
13939 + "Interrupts requested: %d, received: %d\n",
13940 + avail, actual);
12240 13941 }
12241 13942
12242 - mpt->m_intr_cnt = actual;
12243 -
12244 13943 /*
12245 13944 * Get priority for first msi, assume remaining are all the same
12246 13945 */
12247 13946 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
12248 13947 &mpt->m_intr_pri)) != DDI_SUCCESS) {
12249 13948 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
12250 13949
12251 13950 /* Free already allocated intr */
12252 13951 for (i = 0; i < actual; i++) {
12253 13952 (void) ddi_intr_free(mpt->m_htable[i]);
12254 13953 }
12255 13954
12256 13955 kmem_free(mpt->m_htable, mpt->m_intr_size);
12257 13956 return (DDI_FAILURE);
12258 13957 }
12259 13958
12260 13959 /* Test for high level mutex */
12261 13960 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
12262 13961 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
12263 13962 "Hi level interrupt not supported\n");
12264 13963
12265 13964 /* Free already allocated intr */
12266 13965 for (i = 0; i < actual; i++) {
12267 13966 (void) ddi_intr_free(mpt->m_htable[i]);
12268 13967 }
12269 13968
12270 13969 kmem_free(mpt->m_htable, mpt->m_intr_size);
12271 13970 return (DDI_FAILURE);
12272 13971 }
12273 13972
12274 13973 /* Call ddi_intr_add_handler() */
12275 13974 for (i = 0; i < actual; i++) {
12276 13975 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
12277 13976 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
12278 13977 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
12279 13978 "failed %d\n", ret);
12280 13979
12281 13980 /* Free already allocated intr */
12282 13981 for (i = 0; i < actual; i++) {
12283 13982 (void) ddi_intr_free(mpt->m_htable[i]);
12284 13983 }
12285 13984
12286 13985 kmem_free(mpt->m_htable, mpt->m_intr_size);
12287 13986 return (DDI_FAILURE);
12288 13987 }
12289 13988 }
12290 13989
12291 13990 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
12292 13991 != DDI_SUCCESS) {
12293 13992 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
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12294 13993
12295 13994 /* Free already allocated intr */
12296 13995 for (i = 0; i < actual; i++) {
12297 13996 (void) ddi_intr_free(mpt->m_htable[i]);
12298 13997 }
12299 13998
12300 13999 kmem_free(mpt->m_htable, mpt->m_intr_size);
12301 14000 return (DDI_FAILURE);
12302 14001 }
12303 14002
14003 + mpt->m_intr_cnt = actual;
14004 +
12304 14005 /*
12305 14006 * Enable interrupts
12306 14007 */
12307 14008 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12308 14009 /* Call ddi_intr_block_enable() for MSI interrupts */
12309 14010 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
12310 14011 } else {
12311 14012 /* Call ddi_intr_enable for MSI or FIXED interrupts */
12312 14013 for (i = 0; i < mpt->m_intr_cnt; i++) {
12313 14014 (void) ddi_intr_enable(mpt->m_htable[i]);
12314 14015 }
12315 14016 }
14017 +
14018 + switch (intr_type) {
14019 + case DDI_INTR_TYPE_MSIX:
14020 + mptsas_log(mpt, CE_NOTE, "?Using %d MSI-X interrupt(s) "
14021 + "(Available sys %d, mpt %d, Requested %d)\n",
14022 + actual, count, mpt->m_max_msix_vectors, avail);
14023 + break;
14024 + case DDI_INTR_TYPE_MSI:
14025 + mptsas_log(mpt, CE_NOTE, "Using single MSI interrupt\n");
14026 + break;
14027 + case DDI_INTR_TYPE_FIXED:
14028 + default:
14029 + mptsas_log(mpt, CE_NOTE, "Using single fixed interrupt\n");
14030 + break;
14031 + }
14032 +
12316 14033 return (DDI_SUCCESS);
12317 14034 }
12318 14035
12319 14036 /*
12320 14037 * mptsas_rem_intrs:
12321 14038 *
12322 14039 * Unregister FIXED or MSI interrupts
12323 14040 */
12324 14041 static void
12325 14042 mptsas_rem_intrs(mptsas_t *mpt)
12326 14043 {
12327 14044 int i;
12328 14045
12329 14046 NDBG6(("mptsas_rem_intrs"));
12330 14047
12331 14048 /* Disable all interrupts */
12332 14049 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12333 14050 /* Call ddi_intr_block_disable() */
12334 14051 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
12335 14052 } else {
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12336 14053 for (i = 0; i < mpt->m_intr_cnt; i++) {
12337 14054 (void) ddi_intr_disable(mpt->m_htable[i]);
12338 14055 }
12339 14056 }
12340 14057
12341 14058 /* Call ddi_intr_remove_handler() */
12342 14059 for (i = 0; i < mpt->m_intr_cnt; i++) {
12343 14060 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
12344 14061 (void) ddi_intr_free(mpt->m_htable[i]);
12345 14062 }
12346 -
12347 14063 kmem_free(mpt->m_htable, mpt->m_intr_size);
14064 + mpt->m_intr_cnt = 0;
12348 14065 }
12349 14066
12350 14067 /*
12351 14068 * The IO fault service error handling callback function
12352 14069 */
12353 14070 /*ARGSUSED*/
12354 14071 static int
12355 14072 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
12356 14073 {
12357 14074 /*
12358 14075 * as the driver can always deal with an error in any dma or
12359 14076 * access handle, we can just return the fme_status value.
12360 14077 */
12361 14078 pci_ereport_post(dip, err, NULL);
12362 14079 return (err->fme_status);
12363 14080 }
12364 14081
12365 14082 /*
12366 14083 * mptsas_fm_init - initialize fma capabilities and register with IO
12367 14084 * fault services.
12368 14085 */
12369 14086 static void
12370 14087 mptsas_fm_init(mptsas_t *mpt)
12371 14088 {
12372 14089 /*
12373 14090 * Need to change iblock to priority for new MSI intr
12374 14091 */
12375 14092 ddi_iblock_cookie_t fm_ibc;
12376 14093
12377 14094 /* Only register with IO Fault Services if we have some capability */
12378 14095 if (mpt->m_fm_capabilities) {
12379 14096 /* Adjust access and dma attributes for FMA */
12380 14097 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
12381 14098 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12382 14099 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12383 14100
12384 14101 /*
12385 14102 * Register capabilities with IO Fault Services.
12386 14103 * mpt->m_fm_capabilities will be updated to indicate
12387 14104 * capabilities actually supported (not requested.)
12388 14105 */
12389 14106 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
12390 14107
12391 14108 /*
12392 14109 * Initialize pci ereport capabilities if ereport
12393 14110 * capable (should always be.)
12394 14111 */
12395 14112 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12396 14113 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12397 14114 pci_ereport_setup(mpt->m_dip);
12398 14115 }
12399 14116
12400 14117 /*
12401 14118 * Register error callback if error callback capable.
12402 14119 */
12403 14120 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12404 14121 ddi_fm_handler_register(mpt->m_dip,
12405 14122 mptsas_fm_error_cb, (void *) mpt);
12406 14123 }
12407 14124 }
12408 14125 }
12409 14126
12410 14127 /*
12411 14128 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
12412 14129 * fault services.
12413 14130 *
12414 14131 */
12415 14132 static void
12416 14133 mptsas_fm_fini(mptsas_t *mpt)
12417 14134 {
12418 14135 /* Only unregister FMA capabilities if registered */
12419 14136 if (mpt->m_fm_capabilities) {
12420 14137
12421 14138 /*
12422 14139 * Un-register error callback if error callback capable.
12423 14140 */
12424 14141
12425 14142 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12426 14143 ddi_fm_handler_unregister(mpt->m_dip);
12427 14144 }
12428 14145
12429 14146 /*
12430 14147 * Release any resources allocated by pci_ereport_setup()
12431 14148 */
12432 14149
12433 14150 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12434 14151 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12435 14152 pci_ereport_teardown(mpt->m_dip);
12436 14153 }
12437 14154
12438 14155 /* Unregister from IO Fault Services */
12439 14156 ddi_fm_fini(mpt->m_dip);
12440 14157
12441 14158 /* Adjust access and dma attributes for FMA */
12442 14159 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
12443 14160 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12444 14161 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12445 14162
12446 14163 }
12447 14164 }
12448 14165
12449 14166 int
12450 14167 mptsas_check_acc_handle(ddi_acc_handle_t handle)
12451 14168 {
12452 14169 ddi_fm_error_t de;
12453 14170
12454 14171 if (handle == NULL)
12455 14172 return (DDI_FAILURE);
12456 14173 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
12457 14174 return (de.fme_status);
12458 14175 }
12459 14176
12460 14177 int
12461 14178 mptsas_check_dma_handle(ddi_dma_handle_t handle)
12462 14179 {
12463 14180 ddi_fm_error_t de;
12464 14181
12465 14182 if (handle == NULL)
12466 14183 return (DDI_FAILURE);
12467 14184 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
12468 14185 return (de.fme_status);
12469 14186 }
12470 14187
12471 14188 void
12472 14189 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
12473 14190 {
12474 14191 uint64_t ena;
12475 14192 char buf[FM_MAX_CLASS];
12476 14193
12477 14194 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
12478 14195 ena = fm_ena_generate(0, FM_ENA_FMT1);
12479 14196 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
12480 14197 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
12481 14198 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
12482 14199 }
12483 14200 }
12484 14201
12485 14202 static int
12486 14203 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
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12487 14204 uint16_t *dev_handle, mptsas_target_t **pptgt)
12488 14205 {
12489 14206 int rval;
12490 14207 uint32_t dev_info;
12491 14208 uint64_t sas_wwn;
12492 14209 mptsas_phymask_t phymask;
12493 14210 uint8_t physport, phynum, config, disk;
12494 14211 uint64_t devicename;
12495 14212 uint16_t pdev_hdl;
12496 14213 mptsas_target_t *tmp_tgt = NULL;
12497 - uint16_t bay_num, enclosure;
14214 + uint16_t bay_num, enclosure, io_flags;
12498 14215
12499 14216 ASSERT(*pptgt == NULL);
12500 14217
12501 14218 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
12502 14219 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
12503 - &bay_num, &enclosure);
14220 + &bay_num, &enclosure, &io_flags);
12504 14221 if (rval != DDI_SUCCESS) {
12505 14222 rval = DEV_INFO_FAIL_PAGE0;
12506 14223 return (rval);
12507 14224 }
12508 14225
12509 14226 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
12510 14227 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
12511 14228 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
12512 14229 rval = DEV_INFO_WRONG_DEVICE_TYPE;
12513 14230 return (rval);
12514 14231 }
12515 14232
12516 14233 /*
12517 14234 * Check if the dev handle is for a Phys Disk. If so, set return value
12518 14235 * and exit. Don't add Phys Disks to hash.
12519 14236 */
12520 14237 for (config = 0; config < mpt->m_num_raid_configs; config++) {
12521 14238 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
12522 14239 if (*dev_handle == mpt->m_raidconfig[config].
12523 14240 m_physdisk_devhdl[disk]) {
12524 14241 rval = DEV_INFO_PHYS_DISK;
12525 14242 return (rval);
12526 14243 }
12527 14244 }
12528 14245 }
12529 14246
12530 14247 /*
12531 14248 * Get SATA Device Name from SAS device page0 for
12532 14249 * sata device, if device name doesn't exist, set mta_wwn to
12533 14250 * 0 for direct attached SATA. For the device behind the expander
12534 14251 * we still can use STP address assigned by expander.
12535 14252 */
12536 14253 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
12537 14254 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
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12538 14255 mutex_exit(&mpt->m_mutex);
12539 14256 /* alloc a tmp_tgt to send the cmd */
12540 14257 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target),
12541 14258 KM_SLEEP);
12542 14259 tmp_tgt->m_devhdl = *dev_handle;
12543 14260 tmp_tgt->m_deviceinfo = dev_info;
12544 14261 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
12545 14262 tmp_tgt->m_qfull_retry_interval =
12546 14263 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
12547 14264 tmp_tgt->m_t_throttle = MAX_THROTTLE;
14265 + mutex_init(&tmp_tgt->m_t_mutex, NULL, MUTEX_DRIVER, NULL);
12548 14266 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
14267 + mutex_destroy(&tmp_tgt->m_t_mutex);
12549 14268 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
12550 14269 mutex_enter(&mpt->m_mutex);
12551 14270 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
12552 14271 sas_wwn = devicename;
12553 14272 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
12554 14273 sas_wwn = 0;
12555 14274 }
12556 14275 }
12557 14276
12558 14277 phymask = mptsas_physport_to_phymask(mpt, physport);
12559 14278 *pptgt = mptsas_tgt_alloc(mpt, *dev_handle, sas_wwn,
12560 14279 dev_info, phymask, phynum);
12561 14280 if (*pptgt == NULL) {
12562 14281 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
12563 14282 "structure!");
12564 14283 rval = DEV_INFO_FAIL_ALLOC;
12565 14284 return (rval);
12566 14285 }
14286 + (*pptgt)->m_io_flags = io_flags;
12567 14287 (*pptgt)->m_enclosure = enclosure;
12568 14288 (*pptgt)->m_slot_num = bay_num;
12569 14289 return (DEV_INFO_SUCCESS);
12570 14290 }
12571 14291
12572 14292 uint64_t
12573 14293 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
12574 14294 {
12575 14295 uint64_t sata_guid = 0, *pwwn = NULL;
12576 14296 int target = ptgt->m_devhdl;
12577 14297 uchar_t *inq83 = NULL;
12578 14298 int inq83_len = 0xFF;
12579 14299 uchar_t *dblk = NULL;
12580 14300 int inq83_retry = 3;
12581 14301 int rval = DDI_FAILURE;
12582 14302
12583 14303 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
12584 14304
12585 14305 inq83_retry:
12586 14306 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
12587 14307 inq83_len, NULL, 1);
12588 14308 if (rval != DDI_SUCCESS) {
12589 14309 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
12590 14310 "0x83 for target:%x, lun:%x failed!", target, lun);
12591 14311 goto out;
12592 14312 }
12593 14313 /* According to SAT2, the first descriptor is logic unit name */
12594 14314 dblk = &inq83[4];
12595 14315 if ((dblk[1] & 0x30) != 0) {
12596 14316 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
12597 14317 goto out;
12598 14318 }
12599 14319 pwwn = (uint64_t *)(void *)(&dblk[4]);
12600 14320 if ((dblk[4] & 0xf0) == 0x50) {
12601 14321 sata_guid = BE_64(*pwwn);
12602 14322 goto out;
12603 14323 } else if (dblk[4] == 'A') {
12604 14324 NDBG20(("SATA drive has no NAA format GUID."));
12605 14325 goto out;
12606 14326 } else {
12607 14327 /* The data is not ready, wait and retry */
12608 14328 inq83_retry--;
12609 14329 if (inq83_retry <= 0) {
12610 14330 goto out;
12611 14331 }
12612 14332 NDBG20(("The GUID is not ready, retry..."));
12613 14333 delay(1 * drv_usectohz(1000000));
12614 14334 goto inq83_retry;
12615 14335 }
12616 14336 out:
12617 14337 kmem_free(inq83, inq83_len);
12618 14338 return (sata_guid);
12619 14339 }
12620 14340
12621 14341 static int
12622 14342 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
12623 14343 unsigned char *buf, int len, int *reallen, uchar_t evpd)
12624 14344 {
12625 14345 uchar_t cdb[CDB_GROUP0];
12626 14346 struct scsi_address ap;
12627 14347 struct buf *data_bp = NULL;
12628 14348 int resid = 0;
12629 14349 int ret = DDI_FAILURE;
12630 14350
12631 14351 ASSERT(len <= 0xffff);
12632 14352
12633 14353 ap.a_target = MPTSAS_INVALID_DEVHDL;
12634 14354 ap.a_lun = (uchar_t)(lun);
12635 14355 ap.a_hba_tran = mpt->m_tran;
12636 14356
12637 14357 data_bp = scsi_alloc_consistent_buf(&ap,
12638 14358 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
12639 14359 if (data_bp == NULL) {
12640 14360 return (ret);
12641 14361 }
12642 14362 bzero(cdb, CDB_GROUP0);
12643 14363 cdb[0] = SCMD_INQUIRY;
12644 14364 cdb[1] = evpd;
12645 14365 cdb[2] = page;
12646 14366 cdb[3] = (len & 0xff00) >> 8;
12647 14367 cdb[4] = (len & 0x00ff);
12648 14368 cdb[5] = 0;
12649 14369
12650 14370 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
12651 14371 &resid);
12652 14372 if (ret == DDI_SUCCESS) {
12653 14373 if (reallen) {
12654 14374 *reallen = len - resid;
12655 14375 }
12656 14376 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
12657 14377 }
12658 14378 if (data_bp) {
12659 14379 scsi_free_consistent_buf(data_bp);
12660 14380 }
12661 14381 return (ret);
12662 14382 }
12663 14383
12664 14384 static int
12665 14385 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
12666 14386 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
12667 14387 int *resid)
12668 14388 {
12669 14389 struct scsi_pkt *pktp = NULL;
12670 14390 scsi_hba_tran_t *tran_clone = NULL;
12671 14391 mptsas_tgt_private_t *tgt_private = NULL;
12672 14392 int ret = DDI_FAILURE;
12673 14393
12674 14394 /*
12675 14395 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
12676 14396 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
12677 14397 * to simulate the cmds from sd
12678 14398 */
12679 14399 tran_clone = kmem_alloc(
12680 14400 sizeof (scsi_hba_tran_t), KM_SLEEP);
12681 14401 if (tran_clone == NULL) {
12682 14402 goto out;
12683 14403 }
12684 14404 bcopy((caddr_t)mpt->m_tran,
12685 14405 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
12686 14406 tgt_private = kmem_alloc(
12687 14407 sizeof (mptsas_tgt_private_t), KM_SLEEP);
12688 14408 if (tgt_private == NULL) {
12689 14409 goto out;
12690 14410 }
12691 14411 tgt_private->t_lun = ap->a_lun;
12692 14412 tgt_private->t_private = ptgt;
12693 14413 tran_clone->tran_tgt_private = tgt_private;
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12694 14414 ap->a_hba_tran = tran_clone;
12695 14415
12696 14416 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
12697 14417 data_bp, cdblen, sizeof (struct scsi_arq_status),
12698 14418 0, PKT_CONSISTENT, NULL, NULL);
12699 14419 if (pktp == NULL) {
12700 14420 goto out;
12701 14421 }
12702 14422 bcopy(cdb, pktp->pkt_cdbp, cdblen);
12703 14423 pktp->pkt_flags = FLAG_NOPARITY;
14424 + pktp->pkt_time = mptsas_scsi_pkt_time;
12704 14425 if (scsi_poll(pktp) < 0) {
12705 14426 goto out;
12706 14427 }
12707 14428 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
12708 14429 goto out;
12709 14430 }
12710 14431 if (resid != NULL) {
12711 14432 *resid = pktp->pkt_resid;
12712 14433 }
12713 14434
12714 14435 ret = DDI_SUCCESS;
12715 14436 out:
12716 14437 if (pktp) {
12717 14438 scsi_destroy_pkt(pktp);
12718 14439 }
12719 14440 if (tran_clone) {
12720 14441 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
12721 14442 }
12722 14443 if (tgt_private) {
12723 14444 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
12724 14445 }
12725 14446 return (ret);
12726 14447 }
12727 14448 static int
12728 14449 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
12729 14450 {
12730 14451 char *cp = NULL;
12731 14452 char *ptr = NULL;
12732 14453 size_t s = 0;
12733 14454 char *wwid_str = NULL;
12734 14455 char *lun_str = NULL;
12735 14456 long lunnum;
12736 14457 long phyid = -1;
12737 14458 int rc = DDI_FAILURE;
12738 14459
12739 14460 ptr = name;
12740 14461 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
12741 14462 ptr++;
12742 14463 if ((cp = strchr(ptr, ',')) == NULL) {
12743 14464 return (DDI_FAILURE);
12744 14465 }
12745 14466
12746 14467 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12747 14468 s = (uintptr_t)cp - (uintptr_t)ptr;
12748 14469
12749 14470 bcopy(ptr, wwid_str, s);
12750 14471 wwid_str[s] = '\0';
12751 14472
12752 14473 ptr = ++cp;
12753 14474
12754 14475 if ((cp = strchr(ptr, '\0')) == NULL) {
12755 14476 goto out;
12756 14477 }
12757 14478 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12758 14479 s = (uintptr_t)cp - (uintptr_t)ptr;
12759 14480
12760 14481 bcopy(ptr, lun_str, s);
12761 14482 lun_str[s] = '\0';
12762 14483
12763 14484 if (name[0] == 'p') {
12764 14485 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
12765 14486 } else {
12766 14487 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
12767 14488 }
12768 14489 if (rc != DDI_SUCCESS)
12769 14490 goto out;
12770 14491
12771 14492 if (phyid != -1) {
12772 14493 ASSERT(phyid < MPTSAS_MAX_PHYS);
12773 14494 *phy = (uint8_t)phyid;
12774 14495 }
12775 14496 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
12776 14497 if (rc != 0)
12777 14498 goto out;
12778 14499
12779 14500 *lun = (int)lunnum;
12780 14501 rc = DDI_SUCCESS;
12781 14502 out:
12782 14503 if (wwid_str)
12783 14504 kmem_free(wwid_str, SCSI_MAXNAMELEN);
12784 14505 if (lun_str)
12785 14506 kmem_free(lun_str, SCSI_MAXNAMELEN);
12786 14507
12787 14508 return (rc);
12788 14509 }
12789 14510
12790 14511 /*
12791 14512 * mptsas_parse_smp_name() is to parse sas wwn string
12792 14513 * which format is "wWWN"
12793 14514 */
12794 14515 static int
12795 14516 mptsas_parse_smp_name(char *name, uint64_t *wwn)
12796 14517 {
12797 14518 char *ptr = name;
12798 14519
12799 14520 if (*ptr != 'w') {
12800 14521 return (DDI_FAILURE);
12801 14522 }
12802 14523
12803 14524 ptr++;
12804 14525 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
12805 14526 return (DDI_FAILURE);
12806 14527 }
12807 14528 return (DDI_SUCCESS);
12808 14529 }
12809 14530
12810 14531 static int
12811 14532 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
12812 14533 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
12813 14534 {
12814 14535 int ret = NDI_FAILURE;
12815 14536 int circ = 0;
12816 14537 int circ1 = 0;
12817 14538 mptsas_t *mpt;
12818 14539 char *ptr = NULL;
12819 14540 char *devnm = NULL;
12820 14541 uint64_t wwid = 0;
12821 14542 uint8_t phy = 0xFF;
12822 14543 int lun = 0;
12823 14544 uint_t mflags = flag;
12824 14545 int bconfig = TRUE;
12825 14546
12826 14547 if (scsi_hba_iport_unit_address(pdip) == 0) {
12827 14548 return (DDI_FAILURE);
12828 14549 }
12829 14550
12830 14551 mpt = DIP2MPT(pdip);
12831 14552 if (!mpt) {
12832 14553 return (DDI_FAILURE);
12833 14554 }
12834 14555 /*
12835 14556 * Hold the nexus across the bus_config
12836 14557 */
12837 14558 ndi_devi_enter(scsi_vhci_dip, &circ);
12838 14559 ndi_devi_enter(pdip, &circ1);
12839 14560 switch (op) {
12840 14561 case BUS_CONFIG_ONE:
12841 14562 /* parse wwid/target name out of name given */
12842 14563 if ((ptr = strchr((char *)arg, '@')) == NULL) {
12843 14564 ret = NDI_FAILURE;
12844 14565 break;
12845 14566 }
12846 14567 ptr++;
12847 14568 if (strncmp((char *)arg, "smp", 3) == 0) {
12848 14569 /*
12849 14570 * This is a SMP target device
12850 14571 */
12851 14572 ret = mptsas_parse_smp_name(ptr, &wwid);
12852 14573 if (ret != DDI_SUCCESS) {
12853 14574 ret = NDI_FAILURE;
12854 14575 break;
12855 14576 }
12856 14577 ret = mptsas_config_smp(pdip, wwid, childp);
12857 14578 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
12858 14579 /*
12859 14580 * OBP could pass down a non-canonical form
12860 14581 * bootpath without LUN part when LUN is 0.
12861 14582 * So driver need adjust the string.
12862 14583 */
12863 14584 if (strchr(ptr, ',') == NULL) {
12864 14585 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12865 14586 (void) sprintf(devnm, "%s,0", (char *)arg);
12866 14587 ptr = strchr(devnm, '@');
12867 14588 ptr++;
12868 14589 }
12869 14590
12870 14591 /*
12871 14592 * The device path is wWWID format and the device
12872 14593 * is not SMP target device.
12873 14594 */
12874 14595 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
12875 14596 if (ret != DDI_SUCCESS) {
12876 14597 ret = NDI_FAILURE;
12877 14598 break;
12878 14599 }
12879 14600 *childp = NULL;
12880 14601 if (ptr[0] == 'w') {
12881 14602 ret = mptsas_config_one_addr(pdip, wwid,
12882 14603 lun, childp);
12883 14604 } else if (ptr[0] == 'p') {
12884 14605 ret = mptsas_config_one_phy(pdip, phy, lun,
12885 14606 childp);
12886 14607 }
12887 14608
12888 14609 /*
12889 14610 * If this is CD/DVD device in OBP path, the
12890 14611 * ndi_busop_bus_config can be skipped as config one
12891 14612 * operation is done above.
12892 14613 */
12893 14614 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
12894 14615 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
12895 14616 (strncmp((char *)arg, "disk", 4) == 0)) {
12896 14617 bconfig = FALSE;
12897 14618 ndi_hold_devi(*childp);
12898 14619 }
12899 14620 } else {
12900 14621 ret = NDI_FAILURE;
12901 14622 break;
12902 14623 }
12903 14624
12904 14625 /*
12905 14626 * DDI group instructed us to use this flag.
12906 14627 */
12907 14628 mflags |= NDI_MDI_FALLBACK;
12908 14629 break;
12909 14630 case BUS_CONFIG_DRIVER:
12910 14631 case BUS_CONFIG_ALL:
12911 14632 mptsas_config_all(pdip);
12912 14633 ret = NDI_SUCCESS;
12913 14634 break;
12914 14635 }
12915 14636
12916 14637 if ((ret == NDI_SUCCESS) && bconfig) {
12917 14638 ret = ndi_busop_bus_config(pdip, mflags, op,
12918 14639 (devnm == NULL) ? arg : devnm, childp, 0);
12919 14640 }
12920 14641
12921 14642 ndi_devi_exit(pdip, circ1);
12922 14643 ndi_devi_exit(scsi_vhci_dip, circ);
12923 14644 if (devnm != NULL)
12924 14645 kmem_free(devnm, SCSI_MAXNAMELEN);
12925 14646 return (ret);
12926 14647 }
12927 14648
12928 14649 static int
12929 14650 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
12930 14651 mptsas_target_t *ptgt)
12931 14652 {
12932 14653 int rval = DDI_FAILURE;
12933 14654 struct scsi_inquiry *sd_inq = NULL;
12934 14655 mptsas_t *mpt = DIP2MPT(pdip);
12935 14656
12936 14657 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
12937 14658
12938 14659 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
12939 14660 SUN_INQSIZE, 0, (uchar_t)0);
12940 14661
12941 14662 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
12942 14663 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
12943 14664 } else {
12944 14665 rval = DDI_FAILURE;
12945 14666 }
12946 14667
12947 14668 kmem_free(sd_inq, SUN_INQSIZE);
12948 14669 return (rval);
12949 14670 }
12950 14671
12951 14672 static int
12952 14673 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
12953 14674 dev_info_t **lundip)
12954 14675 {
12955 14676 int rval;
12956 14677 mptsas_t *mpt = DIP2MPT(pdip);
12957 14678 int phymask;
12958 14679 mptsas_target_t *ptgt = NULL;
12959 14680
12960 14681 /*
12961 14682 * Get the physical port associated to the iport
12962 14683 */
12963 14684 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
12964 14685 "phymask", 0);
12965 14686
12966 14687 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
12967 14688 if (ptgt == NULL) {
12968 14689 /*
12969 14690 * didn't match any device by searching
12970 14691 */
12971 14692 return (DDI_FAILURE);
12972 14693 }
12973 14694 /*
12974 14695 * If the LUN already exists and the status is online,
12975 14696 * we just return the pointer to dev_info_t directly.
12976 14697 * For the mdi_pathinfo node, we'll handle it in
12977 14698 * mptsas_create_virt_lun()
12978 14699 * TODO should be also in mptsas_handle_dr
12979 14700 */
12980 14701
12981 14702 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
12982 14703 if (*lundip != NULL) {
12983 14704 /*
12984 14705 * TODO Another senario is, we hotplug the same disk
12985 14706 * on the same slot, the devhdl changed, is this
12986 14707 * possible?
12987 14708 * tgt_private->t_private != ptgt
12988 14709 */
12989 14710 if (sasaddr != ptgt->m_addr.mta_wwn) {
12990 14711 /*
12991 14712 * The device has changed although the devhdl is the
12992 14713 * same (Enclosure mapping mode, change drive on the
12993 14714 * same slot)
12994 14715 */
12995 14716 return (DDI_FAILURE);
12996 14717 }
12997 14718 return (DDI_SUCCESS);
12998 14719 }
12999 14720
13000 14721 if (phymask == 0) {
13001 14722 /*
13002 14723 * Configure IR volume
13003 14724 */
13004 14725 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
13005 14726 return (rval);
13006 14727 }
13007 14728 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13008 14729
13009 14730 return (rval);
13010 14731 }
13011 14732
13012 14733 static int
13013 14734 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
13014 14735 dev_info_t **lundip)
13015 14736 {
13016 14737 int rval;
13017 14738 mptsas_t *mpt = DIP2MPT(pdip);
13018 14739 mptsas_phymask_t phymask;
13019 14740 mptsas_target_t *ptgt = NULL;
13020 14741
13021 14742 /*
13022 14743 * Get the physical port associated to the iport
13023 14744 */
13024 14745 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13025 14746 "phymask", 0);
13026 14747
13027 14748 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
13028 14749 if (ptgt == NULL) {
13029 14750 /*
13030 14751 * didn't match any device by searching
13031 14752 */
13032 14753 return (DDI_FAILURE);
13033 14754 }
13034 14755
13035 14756 /*
13036 14757 * If the LUN already exists and the status is online,
13037 14758 * we just return the pointer to dev_info_t directly.
13038 14759 * For the mdi_pathinfo node, we'll handle it in
13039 14760 * mptsas_create_virt_lun().
13040 14761 */
13041 14762
13042 14763 *lundip = mptsas_find_child_phy(pdip, phy);
13043 14764 if (*lundip != NULL) {
13044 14765 return (DDI_SUCCESS);
13045 14766 }
13046 14767
13047 14768 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13048 14769
13049 14770 return (rval);
13050 14771 }
13051 14772
13052 14773 static int
13053 14774 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
13054 14775 uint8_t *lun_addr_type)
13055 14776 {
13056 14777 uint32_t lun_idx = 0;
13057 14778
13058 14779 ASSERT(lun_num != NULL);
13059 14780 ASSERT(lun_addr_type != NULL);
13060 14781
13061 14782 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13062 14783 /* determine report luns addressing type */
13063 14784 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
13064 14785 /*
13065 14786 * Vendors in the field have been found to be concatenating
13066 14787 * bus/target/lun to equal the complete lun value instead
13067 14788 * of switching to flat space addressing
13068 14789 */
13069 14790 /* 00b - peripheral device addressing method */
13070 14791 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
13071 14792 /* FALLTHRU */
13072 14793 /* 10b - logical unit addressing method */
13073 14794 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
13074 14795 /* FALLTHRU */
13075 14796 /* 01b - flat space addressing method */
13076 14797 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
13077 14798 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
13078 14799 *lun_addr_type = (buf[lun_idx] &
13079 14800 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
13080 14801 *lun_num = (buf[lun_idx] & 0x3F) << 8;
13081 14802 *lun_num |= buf[lun_idx + 1];
13082 14803 return (DDI_SUCCESS);
13083 14804 default:
13084 14805 return (DDI_FAILURE);
13085 14806 }
13086 14807 }
13087 14808
13088 14809 static int
13089 14810 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
13090 14811 {
13091 14812 struct buf *repluns_bp = NULL;
13092 14813 struct scsi_address ap;
13093 14814 uchar_t cdb[CDB_GROUP5];
13094 14815 int ret = DDI_FAILURE;
13095 14816 int retry = 0;
13096 14817 int lun_list_len = 0;
13097 14818 uint16_t lun_num = 0;
13098 14819 uint8_t lun_addr_type = 0;
13099 14820 uint32_t lun_cnt = 0;
13100 14821 uint32_t lun_total = 0;
13101 14822 dev_info_t *cdip = NULL;
13102 14823 uint16_t *saved_repluns = NULL;
13103 14824 char *buffer = NULL;
13104 14825 int buf_len = 128;
13105 14826 mptsas_t *mpt = DIP2MPT(pdip);
13106 14827 uint64_t sas_wwn = 0;
13107 14828 uint8_t phy = 0xFF;
13108 14829 uint32_t dev_info = 0;
13109 14830
13110 14831 mutex_enter(&mpt->m_mutex);
13111 14832 sas_wwn = ptgt->m_addr.mta_wwn;
13112 14833 phy = ptgt->m_phynum;
13113 14834 dev_info = ptgt->m_deviceinfo;
13114 14835 mutex_exit(&mpt->m_mutex);
13115 14836
13116 14837 if (sas_wwn == 0) {
13117 14838 /*
13118 14839 * It's a SATA without Device Name
13119 14840 * So don't try multi-LUNs
13120 14841 */
13121 14842 if (mptsas_find_child_phy(pdip, phy)) {
13122 14843 return (DDI_SUCCESS);
13123 14844 } else {
13124 14845 /*
13125 14846 * need configure and create node
13126 14847 */
13127 14848 return (DDI_FAILURE);
13128 14849 }
13129 14850 }
13130 14851
13131 14852 /*
13132 14853 * WWN (SAS address or Device Name exist)
13133 14854 */
13134 14855 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13135 14856 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13136 14857 /*
13137 14858 * SATA device with Device Name
13138 14859 * So don't try multi-LUNs
13139 14860 */
13140 14861 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
13141 14862 return (DDI_SUCCESS);
13142 14863 } else {
13143 14864 return (DDI_FAILURE);
13144 14865 }
13145 14866 }
13146 14867
13147 14868 do {
13148 14869 ap.a_target = MPTSAS_INVALID_DEVHDL;
13149 14870 ap.a_lun = 0;
13150 14871 ap.a_hba_tran = mpt->m_tran;
13151 14872 repluns_bp = scsi_alloc_consistent_buf(&ap,
13152 14873 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
13153 14874 if (repluns_bp == NULL) {
13154 14875 retry++;
13155 14876 continue;
13156 14877 }
13157 14878 bzero(cdb, CDB_GROUP5);
13158 14879 cdb[0] = SCMD_REPORT_LUNS;
13159 14880 cdb[6] = (buf_len & 0xff000000) >> 24;
13160 14881 cdb[7] = (buf_len & 0x00ff0000) >> 16;
13161 14882 cdb[8] = (buf_len & 0x0000ff00) >> 8;
13162 14883 cdb[9] = (buf_len & 0x000000ff);
13163 14884
13164 14885 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
13165 14886 repluns_bp, NULL);
13166 14887 if (ret != DDI_SUCCESS) {
13167 14888 scsi_free_consistent_buf(repluns_bp);
13168 14889 retry++;
13169 14890 continue;
13170 14891 }
13171 14892 lun_list_len = BE_32(*(int *)((void *)(
13172 14893 repluns_bp->b_un.b_addr)));
13173 14894 if (buf_len >= lun_list_len + 8) {
13174 14895 ret = DDI_SUCCESS;
13175 14896 break;
13176 14897 }
13177 14898 scsi_free_consistent_buf(repluns_bp);
13178 14899 buf_len = lun_list_len + 8;
13179 14900
13180 14901 } while (retry < 3);
13181 14902
13182 14903 if (ret != DDI_SUCCESS)
13183 14904 return (ret);
13184 14905 buffer = (char *)repluns_bp->b_un.b_addr;
13185 14906 /*
13186 14907 * find out the number of luns returned by the SCSI ReportLun call
13187 14908 * and allocate buffer space
13188 14909 */
13189 14910 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13190 14911 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
13191 14912 if (saved_repluns == NULL) {
13192 14913 scsi_free_consistent_buf(repluns_bp);
13193 14914 return (DDI_FAILURE);
13194 14915 }
13195 14916 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
13196 14917 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
13197 14918 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
13198 14919 continue;
13199 14920 }
13200 14921 saved_repluns[lun_cnt] = lun_num;
13201 14922 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num))
13202 14923 ret = DDI_SUCCESS;
13203 14924 else
13204 14925 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
13205 14926 ptgt);
13206 14927 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
13207 14928 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
13208 14929 MPTSAS_DEV_GONE);
13209 14930 }
13210 14931 }
13211 14932 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
13212 14933 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
13213 14934 scsi_free_consistent_buf(repluns_bp);
13214 14935 return (DDI_SUCCESS);
13215 14936 }
13216 14937
13217 14938 static int
13218 14939 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
13219 14940 {
13220 14941 int rval = DDI_FAILURE;
13221 14942 struct scsi_inquiry *sd_inq = NULL;
13222 14943 mptsas_t *mpt = DIP2MPT(pdip);
13223 14944 mptsas_target_t *ptgt = NULL;
13224 14945
13225 14946 mutex_enter(&mpt->m_mutex);
13226 14947 ptgt = refhash_linear_search(mpt->m_targets,
13227 14948 mptsas_target_eval_devhdl, &target);
13228 14949 mutex_exit(&mpt->m_mutex);
13229 14950 if (ptgt == NULL) {
13230 14951 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
13231 14952 "not found.", target);
13232 14953 return (rval);
13233 14954 }
13234 14955
13235 14956 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
13236 14957 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
13237 14958 SUN_INQSIZE, 0, (uchar_t)0);
13238 14959
13239 14960 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
13240 14961 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
13241 14962 0);
13242 14963 } else {
13243 14964 rval = DDI_FAILURE;
13244 14965 }
13245 14966
13246 14967 kmem_free(sd_inq, SUN_INQSIZE);
13247 14968 return (rval);
13248 14969 }
13249 14970
13250 14971 /*
13251 14972 * configure all RAID volumes for virtual iport
13252 14973 */
13253 14974 static void
13254 14975 mptsas_config_all_viport(dev_info_t *pdip)
13255 14976 {
13256 14977 mptsas_t *mpt = DIP2MPT(pdip);
13257 14978 int config, vol;
13258 14979 int target;
13259 14980 dev_info_t *lundip = NULL;
13260 14981
13261 14982 /*
13262 14983 * Get latest RAID info and search for any Volume DevHandles. If any
13263 14984 * are found, configure the volume.
13264 14985 */
13265 14986 mutex_enter(&mpt->m_mutex);
13266 14987 for (config = 0; config < mpt->m_num_raid_configs; config++) {
13267 14988 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
13268 14989 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid
13269 14990 == 1) {
13270 14991 target = mpt->m_raidconfig[config].
13271 14992 m_raidvol[vol].m_raidhandle;
13272 14993 mutex_exit(&mpt->m_mutex);
13273 14994 (void) mptsas_config_raid(pdip, target,
13274 14995 &lundip);
13275 14996 mutex_enter(&mpt->m_mutex);
13276 14997 }
13277 14998 }
13278 14999 }
13279 15000 mutex_exit(&mpt->m_mutex);
13280 15001 }
13281 15002
13282 15003 static void
13283 15004 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
13284 15005 int lun_cnt, mptsas_target_t *ptgt)
13285 15006 {
13286 15007 dev_info_t *child = NULL, *savechild = NULL;
13287 15008 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13288 15009 uint64_t sas_wwn, wwid;
13289 15010 uint8_t phy;
13290 15011 int lun;
13291 15012 int i;
13292 15013 int find;
13293 15014 char *addr;
13294 15015 char *nodename;
13295 15016 mptsas_t *mpt = DIP2MPT(pdip);
13296 15017
13297 15018 mutex_enter(&mpt->m_mutex);
13298 15019 wwid = ptgt->m_addr.mta_wwn;
13299 15020 mutex_exit(&mpt->m_mutex);
13300 15021
13301 15022 child = ddi_get_child(pdip);
13302 15023 while (child) {
13303 15024 find = 0;
13304 15025 savechild = child;
13305 15026 child = ddi_get_next_sibling(child);
13306 15027
13307 15028 nodename = ddi_node_name(savechild);
13308 15029 if (strcmp(nodename, "smp") == 0) {
13309 15030 continue;
13310 15031 }
13311 15032
13312 15033 addr = ddi_get_name_addr(savechild);
13313 15034 if (addr == NULL) {
13314 15035 continue;
13315 15036 }
13316 15037
13317 15038 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
13318 15039 DDI_SUCCESS) {
13319 15040 continue;
13320 15041 }
13321 15042
13322 15043 if (wwid == sas_wwn) {
13323 15044 for (i = 0; i < lun_cnt; i++) {
13324 15045 if (repluns[i] == lun) {
13325 15046 find = 1;
13326 15047 break;
13327 15048 }
13328 15049 }
13329 15050 } else {
13330 15051 continue;
13331 15052 }
13332 15053 if (find == 0) {
13333 15054 /*
13334 15055 * The lun has not been there already
13335 15056 */
13336 15057 (void) mptsas_offline_lun(pdip, savechild, NULL,
13337 15058 NDI_DEVI_REMOVE);
13338 15059 }
13339 15060 }
13340 15061
13341 15062 pip = mdi_get_next_client_path(pdip, NULL);
13342 15063 while (pip) {
13343 15064 find = 0;
13344 15065 savepip = pip;
13345 15066 addr = MDI_PI(pip)->pi_addr;
13346 15067
13347 15068 pip = mdi_get_next_client_path(pdip, pip);
13348 15069
13349 15070 if (addr == NULL) {
13350 15071 continue;
13351 15072 }
13352 15073
13353 15074 if (mptsas_parse_address(addr, &sas_wwn, &phy,
13354 15075 &lun) != DDI_SUCCESS) {
13355 15076 continue;
13356 15077 }
13357 15078
13358 15079 if (sas_wwn == wwid) {
13359 15080 for (i = 0; i < lun_cnt; i++) {
13360 15081 if (repluns[i] == lun) {
13361 15082 find = 1;
13362 15083 break;
13363 15084 }
13364 15085 }
13365 15086 } else {
13366 15087 continue;
13367 15088 }
13368 15089
13369 15090 if (find == 0) {
13370 15091 /*
13371 15092 * The lun has not been there already
13372 15093 */
13373 15094 (void) mptsas_offline_lun(pdip, NULL, savepip,
13374 15095 NDI_DEVI_REMOVE);
13375 15096 }
13376 15097 }
13377 15098 }
13378 15099
13379 15100 void
13380 15101 mptsas_update_hashtab(struct mptsas *mpt)
13381 15102 {
13382 15103 uint32_t page_address;
13383 15104 int rval = 0;
13384 15105 uint16_t dev_handle;
13385 15106 mptsas_target_t *ptgt = NULL;
13386 15107 mptsas_smp_t smp_node;
13387 15108
13388 15109 /*
13389 15110 * Get latest RAID info.
13390 15111 */
13391 15112 (void) mptsas_get_raid_info(mpt);
13392 15113
13393 15114 dev_handle = mpt->m_smp_devhdl;
13394 15115 for (; mpt->m_done_traverse_smp == 0; ) {
13395 15116 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
13396 15117 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
13397 15118 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
13398 15119 != DDI_SUCCESS) {
13399 15120 break;
13400 15121 }
13401 15122 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
13402 15123 (void) mptsas_smp_alloc(mpt, &smp_node);
13403 15124 }
13404 15125
13405 15126 /*
13406 15127 * Config target devices
13407 15128 */
13408 15129 dev_handle = mpt->m_dev_handle;
13409 15130
13410 15131 /*
13411 15132 * Do loop to get sas device page 0 by GetNextHandle till the
13412 15133 * the last handle. If the sas device is a SATA/SSP target,
13413 15134 * we try to config it.
13414 15135 */
13415 15136 for (; mpt->m_done_traverse_dev == 0; ) {
13416 15137 ptgt = NULL;
13417 15138 page_address =
13418 15139 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
13419 15140 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
13420 15141 (uint32_t)dev_handle;
13421 15142 rval = mptsas_get_target_device_info(mpt, page_address,
13422 15143 &dev_handle, &ptgt);
13423 15144 if ((rval == DEV_INFO_FAIL_PAGE0) ||
13424 15145 (rval == DEV_INFO_FAIL_ALLOC)) {
13425 15146 break;
13426 15147 }
13427 15148
13428 15149 mpt->m_dev_handle = dev_handle;
13429 15150 }
13430 15151
13431 15152 }
13432 15153
13433 15154 void
13434 15155 mptsas_update_driver_data(struct mptsas *mpt)
13435 15156 {
13436 15157 mptsas_target_t *tp;
13437 15158 mptsas_smp_t *sp;
13438 15159
13439 15160 ASSERT(MUTEX_HELD(&mpt->m_mutex));
13440 15161
13441 15162 /*
13442 15163 * TODO after hard reset, update the driver data structures
13443 15164 * 1. update port/phymask mapping table mpt->m_phy_info
13444 15165 * 2. invalid all the entries in hash table
13445 15166 * m_devhdl = 0xffff and m_deviceinfo = 0
13446 15167 * 3. call sas_device_page/expander_page to update hash table
13447 15168 */
13448 15169 mptsas_update_phymask(mpt);
13449 15170 /*
13450 15171 * Invalid the existing entries
13451 15172 *
13452 15173 * XXX - It seems like we should just delete everything here. We are
13453 15174 * holding the lock and are about to refresh all the targets in both
13454 15175 * hashes anyway. Given the path we're in, what outstanding async
13455 15176 * event could possibly be trying to reference one of these things
13456 15177 * without taking the lock, and how would that be useful anyway?
13457 15178 */
13458 15179 for (tp = refhash_first(mpt->m_targets); tp != NULL;
13459 15180 tp = refhash_next(mpt->m_targets, tp)) {
13460 15181 tp->m_devhdl = MPTSAS_INVALID_DEVHDL;
13461 15182 tp->m_deviceinfo = 0;
13462 15183 tp->m_dr_flag = MPTSAS_DR_INACTIVE;
13463 15184 }
13464 15185 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
13465 15186 sp = refhash_next(mpt->m_smp_targets, sp)) {
13466 15187 sp->m_devhdl = MPTSAS_INVALID_DEVHDL;
13467 15188 sp->m_deviceinfo = 0;
13468 15189 }
13469 15190 mpt->m_done_traverse_dev = 0;
13470 15191 mpt->m_done_traverse_smp = 0;
13471 15192 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
13472 15193 mptsas_update_hashtab(mpt);
13473 15194 }
13474 15195
13475 15196 static void
13476 15197 mptsas_config_all(dev_info_t *pdip)
13477 15198 {
13478 15199 dev_info_t *smpdip = NULL;
13479 15200 mptsas_t *mpt = DIP2MPT(pdip);
13480 15201 int phymask = 0;
13481 15202 mptsas_phymask_t phy_mask;
13482 15203 mptsas_target_t *ptgt = NULL;
13483 15204 mptsas_smp_t *psmp;
13484 15205
13485 15206 /*
13486 15207 * Get the phymask associated to the iport
13487 15208 */
13488 15209 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13489 15210 "phymask", 0);
13490 15211
13491 15212 /*
13492 15213 * Enumerate RAID volumes here (phymask == 0).
13493 15214 */
13494 15215 if (phymask == 0) {
13495 15216 mptsas_config_all_viport(pdip);
13496 15217 return;
13497 15218 }
13498 15219
13499 15220 mutex_enter(&mpt->m_mutex);
13500 15221
13501 15222 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) {
13502 15223 mptsas_update_hashtab(mpt);
13503 15224 }
13504 15225
13505 15226 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL;
13506 15227 psmp = refhash_next(mpt->m_smp_targets, psmp)) {
13507 15228 phy_mask = psmp->m_addr.mta_phymask;
13508 15229 if (phy_mask == phymask) {
13509 15230 smpdip = NULL;
13510 15231 mutex_exit(&mpt->m_mutex);
13511 15232 (void) mptsas_online_smp(pdip, psmp, &smpdip);
13512 15233 mutex_enter(&mpt->m_mutex);
13513 15234 }
13514 15235 }
13515 15236
13516 15237 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
13517 15238 ptgt = refhash_next(mpt->m_targets, ptgt)) {
13518 15239 phy_mask = ptgt->m_addr.mta_phymask;
13519 15240 if (phy_mask == phymask) {
13520 15241 mutex_exit(&mpt->m_mutex);
13521 15242 (void) mptsas_config_target(pdip, ptgt);
13522 15243 mutex_enter(&mpt->m_mutex);
13523 15244 }
13524 15245 }
13525 15246 mutex_exit(&mpt->m_mutex);
13526 15247 }
13527 15248
13528 15249 static int
13529 15250 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
13530 15251 {
13531 15252 int rval = DDI_FAILURE;
13532 15253 dev_info_t *tdip;
13533 15254
13534 15255 rval = mptsas_config_luns(pdip, ptgt);
13535 15256 if (rval != DDI_SUCCESS) {
13536 15257 /*
13537 15258 * The return value means the SCMD_REPORT_LUNS
13538 15259 * did not execute successfully. The target maybe
13539 15260 * doesn't support such command.
13540 15261 */
13541 15262 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
|
↓ open down ↓ |
828 lines elided |
↑ open up ↑ |
13542 15263 }
13543 15264 return (rval);
13544 15265 }
13545 15266
13546 15267 /*
13547 15268 * Return fail if not all the childs/paths are freed.
13548 15269 * if there is any path under the HBA, the return value will be always fail
13549 15270 * because we didn't call mdi_pi_free for path
13550 15271 */
13551 15272 static int
13552 -mptsas_offline_target(dev_info_t *pdip, char *name)
15273 +mptsas_offline_targetdev(dev_info_t *pdip, char *name)
13553 15274 {
13554 15275 dev_info_t *child = NULL, *prechild = NULL;
13555 15276 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13556 15277 int tmp_rval, rval = DDI_SUCCESS;
13557 15278 char *addr, *cp;
13558 15279 size_t s;
13559 15280 mptsas_t *mpt = DIP2MPT(pdip);
13560 15281
13561 15282 child = ddi_get_child(pdip);
13562 15283 while (child) {
13563 15284 addr = ddi_get_name_addr(child);
13564 15285 prechild = child;
13565 15286 child = ddi_get_next_sibling(child);
13566 15287
13567 15288 if (addr == NULL) {
13568 15289 continue;
13569 15290 }
13570 15291 if ((cp = strchr(addr, ',')) == NULL) {
13571 15292 continue;
13572 15293 }
13573 15294
13574 15295 s = (uintptr_t)cp - (uintptr_t)addr;
13575 15296
13576 15297 if (strncmp(addr, name, s) != 0) {
|
↓ open down ↓ |
14 lines elided |
↑ open up ↑ |
13577 15298 continue;
13578 15299 }
13579 15300
13580 15301 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
13581 15302 NDI_DEVI_REMOVE);
13582 15303 if (tmp_rval != DDI_SUCCESS) {
13583 15304 rval = DDI_FAILURE;
13584 15305 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
13585 15306 prechild, MPTSAS_DEV_GONE) !=
13586 15307 DDI_PROP_SUCCESS) {
13587 - mptsas_log(mpt, CE_WARN, "mptsas driver "
15308 + mptsas_log(mpt, CE_WARN,
13588 15309 "unable to create property for "
13589 15310 "SAS %s (MPTSAS_DEV_GONE)", addr);
13590 15311 }
13591 15312 }
13592 15313 }
13593 15314
13594 15315 pip = mdi_get_next_client_path(pdip, NULL);
13595 15316 while (pip) {
13596 15317 addr = MDI_PI(pip)->pi_addr;
13597 15318 savepip = pip;
13598 15319 pip = mdi_get_next_client_path(pdip, pip);
13599 15320 if (addr == NULL) {
13600 15321 continue;
13601 15322 }
13602 15323
13603 15324 if ((cp = strchr(addr, ',')) == NULL) {
13604 15325 continue;
13605 15326 }
13606 15327
13607 15328 s = (uintptr_t)cp - (uintptr_t)addr;
13608 15329
13609 15330 if (strncmp(addr, name, s) != 0) {
13610 15331 continue;
13611 15332 }
13612 15333
13613 15334 (void) mptsas_offline_lun(pdip, NULL, savepip,
13614 15335 NDI_DEVI_REMOVE);
13615 15336 /*
13616 15337 * driver will not invoke mdi_pi_free, so path will not
13617 15338 * be freed forever, return DDI_FAILURE.
13618 15339 */
13619 15340 rval = DDI_FAILURE;
13620 15341 }
13621 15342 return (rval);
13622 15343 }
13623 15344
13624 15345 static int
13625 15346 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
13626 15347 mdi_pathinfo_t *rpip, uint_t flags)
13627 15348 {
13628 15349 int rval = DDI_FAILURE;
13629 15350 char *devname;
13630 15351 dev_info_t *cdip, *parent;
13631 15352
13632 15353 if (rpip != NULL) {
13633 15354 parent = scsi_vhci_dip;
13634 15355 cdip = mdi_pi_get_client(rpip);
13635 15356 } else if (rdip != NULL) {
13636 15357 parent = pdip;
13637 15358 cdip = rdip;
13638 15359 } else {
13639 15360 return (DDI_FAILURE);
13640 15361 }
13641 15362
13642 15363 /*
13643 15364 * Make sure node is attached otherwise
13644 15365 * it won't have related cache nodes to
13645 15366 * clean up. i_ddi_devi_attached is
13646 15367 * similiar to i_ddi_node_state(cdip) >=
13647 15368 * DS_ATTACHED.
13648 15369 */
13649 15370 if (i_ddi_devi_attached(cdip)) {
13650 15371
13651 15372 /* Get full devname */
13652 15373 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
13653 15374 (void) ddi_deviname(cdip, devname);
13654 15375 /* Clean cache */
13655 15376 (void) devfs_clean(parent, devname + 1,
13656 15377 DV_CLEAN_FORCE);
13657 15378 kmem_free(devname, MAXNAMELEN + 1);
13658 15379 }
13659 15380 if (rpip != NULL) {
13660 15381 if (MDI_PI_IS_OFFLINE(rpip)) {
13661 15382 rval = DDI_SUCCESS;
13662 15383 } else {
13663 15384 rval = mdi_pi_offline(rpip, 0);
13664 15385 }
13665 15386 } else {
13666 15387 rval = ndi_devi_offline(cdip, flags);
13667 15388 }
13668 15389
13669 15390 return (rval);
13670 15391 }
13671 15392
13672 15393 static dev_info_t *
13673 15394 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
13674 15395 {
13675 15396 dev_info_t *child = NULL;
13676 15397 char *smp_wwn = NULL;
13677 15398
13678 15399 child = ddi_get_child(parent);
13679 15400 while (child) {
13680 15401 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
13681 15402 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
13682 15403 != DDI_SUCCESS) {
13683 15404 child = ddi_get_next_sibling(child);
13684 15405 continue;
13685 15406 }
13686 15407
13687 15408 if (strcmp(smp_wwn, str_wwn) == 0) {
13688 15409 ddi_prop_free(smp_wwn);
13689 15410 break;
13690 15411 }
13691 15412 child = ddi_get_next_sibling(child);
13692 15413 ddi_prop_free(smp_wwn);
13693 15414 }
13694 15415 return (child);
13695 15416 }
13696 15417
13697 15418 static int
13698 15419 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
13699 15420 {
13700 15421 int rval = DDI_FAILURE;
13701 15422 char *devname;
13702 15423 char wwn_str[MPTSAS_WWN_STRLEN];
13703 15424 dev_info_t *cdip;
13704 15425
13705 15426 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
13706 15427
13707 15428 cdip = mptsas_find_smp_child(pdip, wwn_str);
13708 15429
13709 15430 if (cdip == NULL)
13710 15431 return (DDI_SUCCESS);
13711 15432
13712 15433 /*
13713 15434 * Make sure node is attached otherwise
13714 15435 * it won't have related cache nodes to
13715 15436 * clean up. i_ddi_devi_attached is
13716 15437 * similiar to i_ddi_node_state(cdip) >=
13717 15438 * DS_ATTACHED.
13718 15439 */
13719 15440 if (i_ddi_devi_attached(cdip)) {
13720 15441
13721 15442 /* Get full devname */
13722 15443 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
13723 15444 (void) ddi_deviname(cdip, devname);
13724 15445 /* Clean cache */
13725 15446 (void) devfs_clean(pdip, devname + 1,
13726 15447 DV_CLEAN_FORCE);
13727 15448 kmem_free(devname, MAXNAMELEN + 1);
13728 15449 }
13729 15450
13730 15451 rval = ndi_devi_offline(cdip, flags);
13731 15452
13732 15453 return (rval);
13733 15454 }
13734 15455
13735 15456 static dev_info_t *
13736 15457 mptsas_find_child(dev_info_t *pdip, char *name)
13737 15458 {
13738 15459 dev_info_t *child = NULL;
13739 15460 char *rname = NULL;
13740 15461 int rval = DDI_FAILURE;
13741 15462
13742 15463 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13743 15464
13744 15465 child = ddi_get_child(pdip);
13745 15466 while (child) {
13746 15467 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
13747 15468 if (rval != DDI_SUCCESS) {
13748 15469 child = ddi_get_next_sibling(child);
13749 15470 bzero(rname, SCSI_MAXNAMELEN);
13750 15471 continue;
13751 15472 }
13752 15473
13753 15474 if (strcmp(rname, name) == 0) {
13754 15475 break;
13755 15476 }
13756 15477 child = ddi_get_next_sibling(child);
13757 15478 bzero(rname, SCSI_MAXNAMELEN);
13758 15479 }
13759 15480
13760 15481 kmem_free(rname, SCSI_MAXNAMELEN);
13761 15482
13762 15483 return (child);
13763 15484 }
13764 15485
13765 15486
13766 15487 static dev_info_t *
13767 15488 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
13768 15489 {
13769 15490 dev_info_t *child = NULL;
13770 15491 char *name = NULL;
13771 15492 char *addr = NULL;
13772 15493
13773 15494 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13774 15495 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13775 15496 (void) sprintf(name, "%016"PRIx64, sasaddr);
13776 15497 (void) sprintf(addr, "w%s,%x", name, lun);
13777 15498 child = mptsas_find_child(pdip, addr);
13778 15499 kmem_free(name, SCSI_MAXNAMELEN);
13779 15500 kmem_free(addr, SCSI_MAXNAMELEN);
13780 15501 return (child);
13781 15502 }
13782 15503
13783 15504 static dev_info_t *
13784 15505 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
13785 15506 {
13786 15507 dev_info_t *child;
13787 15508 char *addr;
13788 15509
13789 15510 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13790 15511 (void) sprintf(addr, "p%x,0", phy);
13791 15512 child = mptsas_find_child(pdip, addr);
13792 15513 kmem_free(addr, SCSI_MAXNAMELEN);
13793 15514 return (child);
13794 15515 }
13795 15516
13796 15517 static mdi_pathinfo_t *
13797 15518 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
13798 15519 {
13799 15520 mdi_pathinfo_t *path;
13800 15521 char *addr = NULL;
13801 15522
13802 15523 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13803 15524 (void) sprintf(addr, "p%x,0", phy);
13804 15525 path = mdi_pi_find(pdip, NULL, addr);
13805 15526 kmem_free(addr, SCSI_MAXNAMELEN);
13806 15527 return (path);
13807 15528 }
13808 15529
13809 15530 static mdi_pathinfo_t *
13810 15531 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
13811 15532 {
13812 15533 mdi_pathinfo_t *path;
13813 15534 char *name = NULL;
13814 15535 char *addr = NULL;
13815 15536
13816 15537 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13817 15538 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13818 15539 (void) sprintf(name, "%016"PRIx64, sasaddr);
13819 15540 (void) sprintf(addr, "w%s,%x", name, lun);
13820 15541 path = mdi_pi_find(parent, NULL, addr);
13821 15542 kmem_free(name, SCSI_MAXNAMELEN);
13822 15543 kmem_free(addr, SCSI_MAXNAMELEN);
13823 15544
13824 15545 return (path);
13825 15546 }
13826 15547
13827 15548 static int
13828 15549 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
13829 15550 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
13830 15551 {
13831 15552 int i = 0;
13832 15553 uchar_t *inq83 = NULL;
13833 15554 int inq83_len1 = 0xFF;
13834 15555 int inq83_len = 0;
13835 15556 int rval = DDI_FAILURE;
13836 15557 ddi_devid_t devid;
13837 15558 char *guid = NULL;
13838 15559 int target = ptgt->m_devhdl;
13839 15560 mdi_pathinfo_t *pip = NULL;
13840 15561 mptsas_t *mpt = DIP2MPT(pdip);
13841 15562
13842 15563 /*
13843 15564 * For DVD/CD ROM and tape devices and optical
13844 15565 * devices, we won't try to enumerate them under
13845 15566 * scsi_vhci, so no need to try page83
13846 15567 */
13847 15568 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
13848 15569 sd_inq->inq_dtype == DTYPE_OPTICAL ||
13849 15570 sd_inq->inq_dtype == DTYPE_ESI))
13850 15571 goto create_lun;
13851 15572
13852 15573 /*
13853 15574 * The LCA returns good SCSI status, but corrupt page 83 data the first
13854 15575 * time it is queried. The solution is to keep trying to request page83
13855 15576 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
13856 15577 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
13857 15578 * give up to get VPD page at this stage and fail the enumeration.
13858 15579 */
13859 15580
13860 15581 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
13861 15582
13862 15583 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
13863 15584 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13864 15585 inq83_len1, &inq83_len, 1);
13865 15586 if (rval != 0) {
13866 15587 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13867 15588 "0x83 for target:%x, lun:%x failed!", target, lun);
13868 15589 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
13869 15590 goto create_lun;
13870 15591 goto out;
13871 15592 }
13872 15593 /*
13873 15594 * create DEVID from inquiry data
13874 15595 */
13875 15596 if ((rval = ddi_devid_scsi_encode(
13876 15597 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
13877 15598 sizeof (struct scsi_inquiry), NULL, 0, inq83,
13878 15599 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
13879 15600 /*
13880 15601 * extract GUID from DEVID
13881 15602 */
13882 15603 guid = ddi_devid_to_guid(devid);
13883 15604
13884 15605 /*
13885 15606 * Do not enable MPXIO if the strlen(guid) is greater
13886 15607 * than MPTSAS_MAX_GUID_LEN, this constrain would be
13887 15608 * handled by framework later.
13888 15609 */
13889 15610 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
13890 15611 ddi_devid_free_guid(guid);
13891 15612 guid = NULL;
13892 15613 if (mpt->m_mpxio_enable == TRUE) {
13893 15614 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
13894 15615 "lun:%x doesn't have a valid GUID, "
13895 15616 "multipathing for this drive is "
13896 15617 "not enabled", target, lun);
13897 15618 }
13898 15619 }
13899 15620
13900 15621 /*
13901 15622 * devid no longer needed
13902 15623 */
13903 15624 ddi_devid_free(devid);
13904 15625 break;
13905 15626 } else if (rval == DDI_NOT_WELL_FORMED) {
13906 15627 /*
13907 15628 * return value of ddi_devid_scsi_encode equal to
13908 15629 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
13909 15630 * to retry inquiry page 0x83 and get GUID.
13910 15631 */
13911 15632 NDBG20(("Not well formed devid, retry..."));
13912 15633 delay(1 * drv_usectohz(1000000));
13913 15634 continue;
13914 15635 } else {
13915 15636 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
13916 15637 "path target:%x, lun:%x", target, lun);
13917 15638 rval = DDI_FAILURE;
13918 15639 goto create_lun;
13919 15640 }
13920 15641 }
13921 15642
13922 15643 if (i == mptsas_inq83_retry_timeout) {
13923 15644 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
13924 15645 "for path target:%x, lun:%x", target, lun);
13925 15646 }
13926 15647
13927 15648 rval = DDI_FAILURE;
13928 15649
13929 15650 create_lun:
13930 15651 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
13931 15652 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
13932 15653 ptgt, lun);
13933 15654 }
13934 15655 if (rval != DDI_SUCCESS) {
13935 15656 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
13936 15657 ptgt, lun);
13937 15658
13938 15659 }
13939 15660 out:
13940 15661 if (guid != NULL) {
13941 15662 /*
13942 15663 * guid no longer needed
13943 15664 */
13944 15665 ddi_devid_free_guid(guid);
13945 15666 }
13946 15667 if (inq83 != NULL)
13947 15668 kmem_free(inq83, inq83_len1);
13948 15669 return (rval);
13949 15670 }
13950 15671
13951 15672 static int
13952 15673 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
13953 15674 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
|
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356 lines elided |
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13954 15675 {
13955 15676 int target;
13956 15677 char *nodename = NULL;
13957 15678 char **compatible = NULL;
13958 15679 int ncompatible = 0;
13959 15680 int mdi_rtn = MDI_FAILURE;
13960 15681 int rval = DDI_FAILURE;
13961 15682 char *old_guid = NULL;
13962 15683 mptsas_t *mpt = DIP2MPT(pdip);
13963 15684 char *lun_addr = NULL;
13964 - char *wwn_str = NULL;
13965 - char *attached_wwn_str = NULL;
15685 + char wwn_str[MPTSAS_WWN_STRLEN];
13966 15686 char *component = NULL;
13967 15687 uint8_t phy = 0xFF;
13968 15688 uint64_t sas_wwn;
13969 15689 int64_t lun64 = 0;
13970 15690 uint32_t devinfo;
13971 15691 uint16_t dev_hdl;
13972 15692 uint16_t pdev_hdl;
13973 15693 uint64_t dev_sas_wwn;
13974 15694 uint64_t pdev_sas_wwn;
13975 15695 uint32_t pdev_info;
13976 15696 uint8_t physport;
13977 15697 uint8_t phy_id;
13978 15698 uint32_t page_address;
13979 - uint16_t bay_num, enclosure;
15699 + uint16_t bay_num, enclosure, io_flags;
13980 15700 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
13981 15701 uint32_t dev_info;
13982 15702
13983 15703 mutex_enter(&mpt->m_mutex);
13984 15704 target = ptgt->m_devhdl;
13985 15705 sas_wwn = ptgt->m_addr.mta_wwn;
13986 15706 devinfo = ptgt->m_deviceinfo;
13987 15707 phy = ptgt->m_phynum;
13988 15708 mutex_exit(&mpt->m_mutex);
13989 15709
13990 15710 if (sas_wwn) {
13991 15711 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
13992 15712 } else {
13993 15713 *pip = mptsas_find_path_phy(pdip, phy);
13994 15714 }
13995 15715
13996 15716 if (*pip != NULL) {
13997 15717 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
13998 15718 ASSERT(*lun_dip != NULL);
13999 15719 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
14000 15720 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
14001 15721 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
14002 15722 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
14003 15723 /*
14004 15724 * Same path back online again.
14005 15725 */
14006 15726 (void) ddi_prop_free(old_guid);
14007 15727 if ((!MDI_PI_IS_ONLINE(*pip)) &&
14008 15728 (!MDI_PI_IS_STANDBY(*pip)) &&
14009 15729 (ptgt->m_tgt_unconfigured == 0)) {
14010 15730 rval = mdi_pi_online(*pip, 0);
14011 15731 mutex_enter(&mpt->m_mutex);
14012 15732 ptgt->m_led_status = 0;
14013 15733 (void) mptsas_flush_led_status(mpt,
14014 15734 ptgt);
14015 15735 mutex_exit(&mpt->m_mutex);
14016 15736 } else {
14017 15737 rval = DDI_SUCCESS;
14018 15738 }
14019 15739 if (rval != DDI_SUCCESS) {
14020 15740 mptsas_log(mpt, CE_WARN, "path:target: "
14021 15741 "%x, lun:%x online failed!", target,
14022 15742 lun);
14023 15743 *pip = NULL;
14024 15744 *lun_dip = NULL;
14025 15745 }
14026 15746 return (rval);
14027 15747 } else {
14028 15748 /*
14029 15749 * The GUID of the LUN has changed which maybe
14030 15750 * because customer mapped another volume to the
14031 15751 * same LUN.
14032 15752 */
14033 15753 mptsas_log(mpt, CE_WARN, "The GUID of the "
14034 15754 "target:%x, lun:%x was changed, maybe "
14035 15755 "because someone mapped another volume "
14036 15756 "to the same LUN", target, lun);
14037 15757 (void) ddi_prop_free(old_guid);
14038 15758 if (!MDI_PI_IS_OFFLINE(*pip)) {
14039 15759 rval = mdi_pi_offline(*pip, 0);
14040 15760 if (rval != MDI_SUCCESS) {
14041 15761 mptsas_log(mpt, CE_WARN, "path:"
14042 15762 "target:%x, lun:%x offline "
14043 15763 "failed!", target, lun);
14044 15764 *pip = NULL;
14045 15765 *lun_dip = NULL;
14046 15766 return (DDI_FAILURE);
14047 15767 }
14048 15768 }
14049 15769 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
14050 15770 mptsas_log(mpt, CE_WARN, "path:target:"
14051 15771 "%x, lun:%x free failed!", target,
14052 15772 lun);
14053 15773 *pip = NULL;
14054 15774 *lun_dip = NULL;
14055 15775 return (DDI_FAILURE);
14056 15776 }
14057 15777 }
14058 15778 } else {
14059 15779 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
14060 15780 "property for path:target:%x, lun:%x", target, lun);
14061 15781 *pip = NULL;
14062 15782 *lun_dip = NULL;
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14063 15783 return (DDI_FAILURE);
14064 15784 }
14065 15785 }
14066 15786 scsi_hba_nodename_compatible_get(inq, NULL,
14067 15787 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
14068 15788
14069 15789 /*
14070 15790 * if nodename can't be determined then print a message and skip it
14071 15791 */
14072 15792 if (nodename == NULL) {
14073 - mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
15793 + mptsas_log(mpt, CE_WARN, "found no compatible "
14074 15794 "driver for target%d lun %d dtype:0x%02x", target, lun,
14075 15795 inq->inq_dtype);
14076 15796 return (DDI_FAILURE);
14077 15797 }
14078 15798
14079 - wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14080 15799 /* The property is needed by MPAPI */
14081 15800 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14082 15801
14083 15802 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14084 15803 if (guid) {
14085 15804 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
14086 15805 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14087 15806 } else {
14088 15807 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
14089 15808 (void) sprintf(wwn_str, "p%x", phy);
14090 15809 }
14091 15810
14092 15811 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
14093 15812 guid, lun_addr, compatible, ncompatible,
14094 15813 0, pip);
14095 15814 if (mdi_rtn == MDI_SUCCESS) {
14096 15815
14097 15816 if (mdi_prop_update_string(*pip, MDI_GUID,
14098 15817 guid) != DDI_SUCCESS) {
14099 - mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15818 + mptsas_log(mpt, CE_WARN, "unable to "
14100 15819 "create prop for target %d lun %d (MDI_GUID)",
14101 15820 target, lun);
14102 15821 mdi_rtn = MDI_FAILURE;
14103 15822 goto virt_create_done;
14104 15823 }
14105 15824
14106 15825 if (mdi_prop_update_int(*pip, LUN_PROP,
14107 15826 lun) != DDI_SUCCESS) {
14108 - mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15827 + mptsas_log(mpt, CE_WARN, "unable to "
14109 15828 "create prop for target %d lun %d (LUN_PROP)",
14110 15829 target, lun);
14111 15830 mdi_rtn = MDI_FAILURE;
14112 15831 goto virt_create_done;
14113 15832 }
14114 15833 lun64 = (int64_t)lun;
14115 15834 if (mdi_prop_update_int64(*pip, LUN64_PROP,
14116 15835 lun64) != DDI_SUCCESS) {
14117 - mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15836 + mptsas_log(mpt, CE_WARN, "unable to "
14118 15837 "create prop for target %d (LUN64_PROP)",
14119 15838 target);
14120 15839 mdi_rtn = MDI_FAILURE;
14121 15840 goto virt_create_done;
14122 15841 }
14123 15842 if (mdi_prop_update_string_array(*pip, "compatible",
14124 15843 compatible, ncompatible) !=
14125 15844 DDI_PROP_SUCCESS) {
14126 - mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15845 + mptsas_log(mpt, CE_WARN, "unable to "
14127 15846 "create prop for target %d lun %d (COMPATIBLE)",
14128 15847 target, lun);
14129 15848 mdi_rtn = MDI_FAILURE;
14130 15849 goto virt_create_done;
14131 15850 }
14132 15851 if (sas_wwn && (mdi_prop_update_string(*pip,
14133 15852 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
14134 - mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15853 + mptsas_log(mpt, CE_WARN, "unable to "
14135 15854 "create prop for target %d lun %d "
14136 15855 "(target-port)", target, lun);
14137 15856 mdi_rtn = MDI_FAILURE;
14138 15857 goto virt_create_done;
14139 15858 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
14140 15859 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
14141 15860 /*
14142 15861 * Direct attached SATA device without DeviceName
14143 15862 */
14144 - mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15863 + mptsas_log(mpt, CE_WARN, "unable to "
14145 15864 "create prop for SAS target %d lun %d "
14146 15865 "(sata-phy)", target, lun);
14147 15866 mdi_rtn = MDI_FAILURE;
14148 15867 goto virt_create_done;
14149 15868 }
14150 15869 mutex_enter(&mpt->m_mutex);
14151 15870
14152 15871 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14153 15872 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14154 15873 (uint32_t)ptgt->m_devhdl;
14155 15874 rval = mptsas_get_sas_device_page0(mpt, page_address,
14156 15875 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
14157 - &phy_id, &pdev_hdl, &bay_num, &enclosure);
15876 + &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
14158 15877 if (rval != DDI_SUCCESS) {
14159 15878 mutex_exit(&mpt->m_mutex);
14160 15879 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14161 15880 "parent device for handle %d", page_address);
14162 15881 mdi_rtn = MDI_FAILURE;
14163 15882 goto virt_create_done;
14164 15883 }
14165 15884
14166 15885 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14167 15886 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14168 15887 rval = mptsas_get_sas_device_page0(mpt, page_address,
14169 15888 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
14170 - &phy_id, &pdev_hdl, &bay_num, &enclosure);
15889 + &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
14171 15890 if (rval != DDI_SUCCESS) {
14172 15891 mutex_exit(&mpt->m_mutex);
14173 15892 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14174 15893 "device info for handle %d", page_address);
14175 15894 mdi_rtn = MDI_FAILURE;
14176 15895 goto virt_create_done;
14177 15896 }
14178 15897
14179 15898 mutex_exit(&mpt->m_mutex);
14180 15899
14181 15900 /*
14182 15901 * If this device direct attached to the controller
14183 15902 * set the attached-port to the base wwid
14184 15903 */
14185 15904 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14186 15905 != DEVINFO_DIRECT_ATTACHED) {
14187 15906 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14188 15907 pdev_sas_wwn);
14189 15908 } else {
14190 15909 /*
14191 15910 * Update the iport's attached-port to guid
14192 15911 */
14193 15912 if (sas_wwn == 0) {
14194 15913 (void) sprintf(wwn_str, "p%x", phy);
14195 15914 } else {
14196 15915 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14197 15916 }
14198 15917 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14199 15918 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14200 15919 DDI_PROP_SUCCESS) {
14201 15920 mptsas_log(mpt, CE_WARN,
14202 15921 "mptsas unable to create "
14203 15922 "property for iport target-port"
14204 15923 " %s (sas_wwn)",
14205 15924 wwn_str);
14206 15925 mdi_rtn = MDI_FAILURE;
|
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26 lines elided |
↑ open up ↑ |
14207 15926 goto virt_create_done;
14208 15927 }
14209 15928
14210 15929 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14211 15930 mpt->un.m_base_wwid);
14212 15931 }
14213 15932
14214 15933 if (mdi_prop_update_string(*pip,
14215 15934 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14216 15935 DDI_PROP_SUCCESS) {
14217 - mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15936 + mptsas_log(mpt, CE_WARN, "unable to create "
14218 15937 "property for iport attached-port %s (sas_wwn)",
14219 - attached_wwn_str);
15938 + pdev_wwn_str);
14220 15939 mdi_rtn = MDI_FAILURE;
14221 15940 goto virt_create_done;
14222 15941 }
14223 15942
14224 15943
14225 15944 if (inq->inq_dtype == 0) {
14226 15945 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14227 15946 /*
14228 15947 * set obp path for pathinfo
14229 15948 */
14230 15949 (void) snprintf(component, MAXPATHLEN,
14231 15950 "disk@%s", lun_addr);
14232 15951
14233 15952 if (mdi_pi_pathname_obp_set(*pip, component) !=
14234 15953 DDI_SUCCESS) {
14235 - mptsas_log(mpt, CE_WARN, "mpt_sas driver "
15954 + mptsas_log(mpt, CE_WARN,
14236 15955 "unable to set obp-path for object %s",
14237 15956 component);
14238 15957 mdi_rtn = MDI_FAILURE;
14239 15958 goto virt_create_done;
14240 15959 }
14241 15960 }
14242 15961
14243 15962 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
14244 15963 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14245 15964 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14246 15965 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
14247 15966 "pm-capable", 1)) !=
14248 15967 DDI_PROP_SUCCESS) {
14249 - mptsas_log(mpt, CE_WARN, "mptsas driver"
15968 + mptsas_log(mpt, CE_WARN,
14250 15969 "failed to create pm-capable "
14251 15970 "property, target %d", target);
14252 15971 mdi_rtn = MDI_FAILURE;
14253 15972 goto virt_create_done;
14254 15973 }
14255 15974 }
14256 15975 /*
14257 15976 * Create the phy-num property
14258 15977 */
14259 15978 if (mdi_prop_update_int(*pip, "phy-num",
14260 15979 ptgt->m_phynum) != DDI_SUCCESS) {
14261 - mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15980 + mptsas_log(mpt, CE_WARN, "unable to "
14262 15981 "create phy-num property for target %d lun %d",
14263 15982 target, lun);
14264 15983 mdi_rtn = MDI_FAILURE;
14265 15984 goto virt_create_done;
14266 15985 }
14267 15986 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
14268 15987 mdi_rtn = mdi_pi_online(*pip, 0);
14269 15988 if (mdi_rtn == MDI_SUCCESS) {
14270 15989 mutex_enter(&mpt->m_mutex);
14271 15990 ptgt->m_led_status = 0;
14272 15991 (void) mptsas_flush_led_status(mpt, ptgt);
14273 15992 mutex_exit(&mpt->m_mutex);
14274 15993 }
14275 15994 if (mdi_rtn == MDI_NOT_SUPPORTED) {
14276 15995 mdi_rtn = MDI_FAILURE;
14277 15996 }
14278 15997 virt_create_done:
14279 15998 if (*pip && mdi_rtn != MDI_SUCCESS) {
|
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8 lines elided |
↑ open up ↑ |
14280 15999 (void) mdi_pi_free(*pip, 0);
14281 16000 *pip = NULL;
14282 16001 *lun_dip = NULL;
14283 16002 }
14284 16003 }
14285 16004
14286 16005 scsi_hba_nodename_compatible_free(nodename, compatible);
14287 16006 if (lun_addr != NULL) {
14288 16007 kmem_free(lun_addr, SCSI_MAXNAMELEN);
14289 16008 }
14290 - if (wwn_str != NULL) {
14291 - kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14292 - }
14293 16009 if (component != NULL) {
14294 16010 kmem_free(component, MAXPATHLEN);
14295 16011 }
14296 16012
14297 16013 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14298 16014 }
14299 16015
14300 16016 static int
14301 16017 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
14302 16018 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14303 16019 {
14304 16020 int target;
14305 16021 int rval;
14306 16022 int ndi_rtn = NDI_FAILURE;
14307 16023 uint64_t be_sas_wwn;
14308 16024 char *nodename = NULL;
14309 16025 char **compatible = NULL;
14310 16026 int ncompatible = 0;
14311 16027 int instance = 0;
14312 16028 mptsas_t *mpt = DIP2MPT(pdip);
14313 - char *wwn_str = NULL;
14314 - char *component = NULL;
14315 - char *attached_wwn_str = NULL;
16029 + char wwn_str[MPTSAS_WWN_STRLEN];
16030 + char component[MAXPATHLEN];
14316 16031 uint8_t phy = 0xFF;
14317 16032 uint64_t sas_wwn;
14318 16033 uint32_t devinfo;
14319 16034 uint16_t dev_hdl;
14320 16035 uint16_t pdev_hdl;
14321 16036 uint64_t pdev_sas_wwn;
14322 16037 uint64_t dev_sas_wwn;
14323 16038 uint32_t pdev_info;
14324 16039 uint8_t physport;
14325 16040 uint8_t phy_id;
14326 16041 uint32_t page_address;
14327 - uint16_t bay_num, enclosure;
16042 + uint16_t bay_num, enclosure, io_flags;
14328 16043 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
14329 16044 uint32_t dev_info;
14330 16045 int64_t lun64 = 0;
14331 16046
14332 16047 mutex_enter(&mpt->m_mutex);
14333 16048 target = ptgt->m_devhdl;
14334 16049 sas_wwn = ptgt->m_addr.mta_wwn;
14335 16050 devinfo = ptgt->m_deviceinfo;
14336 16051 phy = ptgt->m_phynum;
14337 16052 mutex_exit(&mpt->m_mutex);
14338 16053
14339 16054 /*
14340 16055 * generate compatible property with binding-set "mpt"
14341 16056 */
14342 16057 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
14343 16058 &nodename, &compatible, &ncompatible);
14344 16059
14345 16060 /*
14346 16061 * if nodename can't be determined then print a message and skip it
14347 16062 */
14348 16063 if (nodename == NULL) {
14349 16064 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
14350 16065 "for target %d lun %d", target, lun);
14351 16066 return (DDI_FAILURE);
14352 16067 }
14353 16068
14354 16069 ndi_rtn = ndi_devi_alloc(pdip, nodename,
14355 16070 DEVI_SID_NODEID, lun_dip);
14356 16071
14357 16072 /*
14358 16073 * if lun alloc success, set props
14359 16074 */
14360 16075 if (ndi_rtn == NDI_SUCCESS) {
14361 16076
14362 16077 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14363 16078 *lun_dip, LUN_PROP, lun) !=
14364 16079 DDI_PROP_SUCCESS) {
14365 16080 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14366 16081 "property for target %d lun %d (LUN_PROP)",
14367 16082 target, lun);
14368 16083 ndi_rtn = NDI_FAILURE;
14369 16084 goto phys_create_done;
14370 16085 }
14371 16086
14372 16087 lun64 = (int64_t)lun;
14373 16088 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
14374 16089 *lun_dip, LUN64_PROP, lun64) !=
14375 16090 DDI_PROP_SUCCESS) {
14376 16091 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14377 16092 "property for target %d lun64 %d (LUN64_PROP)",
14378 16093 target, lun);
14379 16094 ndi_rtn = NDI_FAILURE;
14380 16095 goto phys_create_done;
14381 16096 }
14382 16097 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
14383 16098 *lun_dip, "compatible", compatible, ncompatible)
14384 16099 != DDI_PROP_SUCCESS) {
14385 16100 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14386 16101 "property for target %d lun %d (COMPATIBLE)",
14387 16102 target, lun);
|
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50 lines elided |
↑ open up ↑ |
14388 16103 ndi_rtn = NDI_FAILURE;
14389 16104 goto phys_create_done;
14390 16105 }
14391 16106
14392 16107 /*
14393 16108 * We need the SAS WWN for non-multipath devices, so
14394 16109 * we'll use the same property as that multipathing
14395 16110 * devices need to present for MPAPI. If we don't have
14396 16111 * a WWN (e.g. parallel SCSI), don't create the prop.
14397 16112 */
14398 - wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14399 16113 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14400 16114 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
14401 16115 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
14402 16116 != DDI_PROP_SUCCESS) {
14403 16117 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14404 16118 "create property for SAS target %d lun %d "
14405 16119 "(target-port)", target, lun);
14406 16120 ndi_rtn = NDI_FAILURE;
14407 16121 goto phys_create_done;
14408 16122 }
14409 16123
14410 16124 be_sas_wwn = BE_64(sas_wwn);
14411 16125 if (sas_wwn && ndi_prop_update_byte_array(
14412 16126 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
14413 16127 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
14414 16128 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14415 16129 "create property for SAS target %d lun %d "
14416 16130 "(port-wwn)", target, lun);
14417 16131 ndi_rtn = NDI_FAILURE;
14418 16132 goto phys_create_done;
14419 16133 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
14420 16134 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
14421 16135 DDI_PROP_SUCCESS)) {
14422 16136 /*
14423 16137 * Direct attached SATA device without DeviceName
14424 16138 */
14425 16139 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14426 16140 "create property for SAS target %d lun %d "
14427 16141 "(sata-phy)", target, lun);
14428 16142 ndi_rtn = NDI_FAILURE;
14429 16143 goto phys_create_done;
14430 16144 }
14431 16145
14432 16146 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14433 16147 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
14434 16148 mptsas_log(mpt, CE_WARN, "mptsas unable to"
14435 16149 "create property for SAS target %d lun %d"
14436 16150 " (SAS_PROP)", target, lun);
14437 16151 ndi_rtn = NDI_FAILURE;
14438 16152 goto phys_create_done;
14439 16153 }
14440 16154 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
14441 16155 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
14442 16156 mptsas_log(mpt, CE_WARN, "mptsas unable "
14443 16157 "to create guid property for target %d "
14444 16158 "lun %d", target, lun);
14445 16159 ndi_rtn = NDI_FAILURE;
14446 16160 goto phys_create_done;
14447 16161 }
14448 16162
14449 16163 /*
14450 16164 * The following code is to set properties for SM-HBA support,
14451 16165 * it doesn't apply to RAID volumes
14452 16166 */
14453 16167 if (ptgt->m_addr.mta_phymask == 0)
|
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↑ open up ↑ |
14454 16168 goto phys_raid_lun;
14455 16169
14456 16170 mutex_enter(&mpt->m_mutex);
14457 16171
14458 16172 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14459 16173 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14460 16174 (uint32_t)ptgt->m_devhdl;
14461 16175 rval = mptsas_get_sas_device_page0(mpt, page_address,
14462 16176 &dev_hdl, &dev_sas_wwn, &dev_info,
14463 16177 &physport, &phy_id, &pdev_hdl,
14464 - &bay_num, &enclosure);
16178 + &bay_num, &enclosure, &io_flags);
14465 16179 if (rval != DDI_SUCCESS) {
14466 16180 mutex_exit(&mpt->m_mutex);
14467 16181 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14468 16182 "parent device for handle %d.", page_address);
14469 16183 ndi_rtn = NDI_FAILURE;
14470 16184 goto phys_create_done;
14471 16185 }
14472 16186
14473 16187 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14474 16188 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14475 16189 rval = mptsas_get_sas_device_page0(mpt, page_address,
14476 - &dev_hdl, &pdev_sas_wwn, &pdev_info,
14477 - &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
16190 + &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
16191 + &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
14478 16192 if (rval != DDI_SUCCESS) {
14479 16193 mutex_exit(&mpt->m_mutex);
14480 16194 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14481 16195 "device for handle %d.", page_address);
14482 16196 ndi_rtn = NDI_FAILURE;
14483 16197 goto phys_create_done;
14484 16198 }
14485 16199
14486 16200 mutex_exit(&mpt->m_mutex);
14487 16201
14488 16202 /*
14489 16203 * If this device direct attached to the controller
14490 16204 * set the attached-port to the base wwid
14491 16205 */
14492 16206 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14493 16207 != DEVINFO_DIRECT_ATTACHED) {
14494 16208 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14495 16209 pdev_sas_wwn);
14496 16210 } else {
14497 16211 /*
14498 16212 * Update the iport's attached-port to guid
14499 16213 */
14500 16214 if (sas_wwn == 0) {
14501 16215 (void) sprintf(wwn_str, "p%x", phy);
14502 16216 } else {
14503 16217 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14504 16218 }
14505 16219 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14506 16220 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14507 16221 DDI_PROP_SUCCESS) {
14508 16222 mptsas_log(mpt, CE_WARN,
14509 16223 "mptsas unable to create "
14510 16224 "property for iport target-port"
14511 16225 " %s (sas_wwn)",
14512 16226 wwn_str);
14513 16227 ndi_rtn = NDI_FAILURE;
14514 16228 goto phys_create_done;
14515 16229 }
14516 16230
|
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29 lines elided |
↑ open up ↑ |
14517 16231 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14518 16232 mpt->un.m_base_wwid);
14519 16233 }
14520 16234
14521 16235 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14522 16236 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14523 16237 DDI_PROP_SUCCESS) {
14524 16238 mptsas_log(mpt, CE_WARN,
14525 16239 "mptsas unable to create "
14526 16240 "property for iport attached-port %s (sas_wwn)",
14527 - attached_wwn_str);
16241 + pdev_wwn_str);
14528 16242 ndi_rtn = NDI_FAILURE;
14529 16243 goto phys_create_done;
14530 16244 }
14531 16245
14532 16246 if (IS_SATA_DEVICE(dev_info)) {
14533 16247 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14534 16248 *lun_dip, MPTSAS_VARIANT, "sata") !=
14535 16249 DDI_PROP_SUCCESS) {
14536 16250 mptsas_log(mpt, CE_WARN,
14537 16251 "mptsas unable to create "
14538 16252 "property for device variant ");
14539 16253 ndi_rtn = NDI_FAILURE;
14540 16254 goto phys_create_done;
14541 16255 }
14542 16256 }
14543 16257
14544 16258 if (IS_ATAPI_DEVICE(dev_info)) {
14545 16259 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14546 16260 *lun_dip, MPTSAS_VARIANT, "atapi") !=
14547 16261 DDI_PROP_SUCCESS) {
14548 16262 mptsas_log(mpt, CE_WARN,
14549 16263 "mptsas unable to create "
14550 16264 "property for device variant ");
14551 16265 ndi_rtn = NDI_FAILURE;
14552 16266 goto phys_create_done;
14553 16267 }
14554 16268 }
14555 16269
|
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18 lines elided |
↑ open up ↑ |
14556 16270 phys_raid_lun:
14557 16271 /*
14558 16272 * if this is a SAS controller, and the target is a SATA
14559 16273 * drive, set the 'pm-capable' property for sd and if on
14560 16274 * an OPL platform, also check if this is an ATAPI
14561 16275 * device.
14562 16276 */
14563 16277 instance = ddi_get_instance(mpt->m_dip);
14564 16278 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14565 16279 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14566 - NDBG2(("mptsas%d: creating pm-capable property, "
16280 + NDBG2(("mptsas3%d: creating pm-capable property, "
14567 16281 "target %d", instance, target));
14568 16282
14569 16283 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
14570 16284 *lun_dip, "pm-capable", 1)) !=
14571 16285 DDI_PROP_SUCCESS) {
14572 16286 mptsas_log(mpt, CE_WARN, "mptsas "
14573 16287 "failed to create pm-capable "
14574 16288 "property, target %d", target);
14575 16289 ndi_rtn = NDI_FAILURE;
14576 16290 goto phys_create_done;
14577 16291 }
14578 16292
14579 16293 }
14580 16294
14581 16295 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
14582 16296 /*
14583 16297 * add 'obp-path' properties for devinfo
14584 16298 */
14585 16299 bzero(wwn_str, sizeof (wwn_str));
14586 16300 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14587 - component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14588 16301 if (guid) {
14589 16302 (void) snprintf(component, MAXPATHLEN,
14590 16303 "disk@w%s,%x", wwn_str, lun);
14591 16304 } else {
14592 16305 (void) snprintf(component, MAXPATHLEN,
14593 16306 "disk@p%x,%x", phy, lun);
14594 16307 }
14595 16308 if (ddi_pathname_obp_set(*lun_dip, component)
14596 16309 != DDI_SUCCESS) {
14597 16310 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
14598 16311 "unable to set obp-path for SAS "
14599 16312 "object %s", component);
14600 16313 ndi_rtn = NDI_FAILURE;
|
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3 lines elided |
↑ open up ↑ |
14601 16314 goto phys_create_done;
14602 16315 }
14603 16316 }
14604 16317 /*
14605 16318 * Create the phy-num property for non-raid disk
14606 16319 */
14607 16320 if (ptgt->m_addr.mta_phymask != 0) {
14608 16321 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14609 16322 *lun_dip, "phy-num", ptgt->m_phynum) !=
14610 16323 DDI_PROP_SUCCESS) {
14611 - mptsas_log(mpt, CE_WARN, "mptsas driver "
16324 + mptsas_log(mpt, CE_WARN,
14612 16325 "failed to create phy-num property for "
14613 16326 "target %d", target);
14614 16327 ndi_rtn = NDI_FAILURE;
14615 16328 goto phys_create_done;
14616 16329 }
14617 16330 }
14618 16331 phys_create_done:
14619 16332 /*
14620 16333 * If props were setup ok, online the lun
14621 16334 */
14622 16335 if (ndi_rtn == NDI_SUCCESS) {
14623 16336 /*
14624 16337 * Try to online the new node
14625 16338 */
14626 16339 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
14627 16340 }
14628 16341 if (ndi_rtn == NDI_SUCCESS) {
|
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7 lines elided |
↑ open up ↑ |
14629 16342 mutex_enter(&mpt->m_mutex);
14630 16343 ptgt->m_led_status = 0;
14631 16344 (void) mptsas_flush_led_status(mpt, ptgt);
14632 16345 mutex_exit(&mpt->m_mutex);
14633 16346 }
14634 16347
14635 16348 /*
14636 16349 * If success set rtn flag, else unwire alloc'd lun
14637 16350 */
14638 16351 if (ndi_rtn != NDI_SUCCESS) {
14639 - NDBG12(("mptsas driver unable to online "
16352 + NDBG12(("unable to online "
14640 16353 "target %d lun %d", target, lun));
14641 16354 ndi_prop_remove_all(*lun_dip);
14642 16355 (void) ndi_devi_free(*lun_dip);
14643 16356 *lun_dip = NULL;
14644 16357 }
14645 16358 }
14646 16359
14647 16360 scsi_hba_nodename_compatible_free(nodename, compatible);
14648 16361
14649 - if (wwn_str != NULL) {
14650 - kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14651 - }
14652 - if (component != NULL) {
14653 - kmem_free(component, MAXPATHLEN);
14654 - }
14655 -
14656 -
14657 16362 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14658 16363 }
14659 16364
14660 16365 static int
14661 16366 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
14662 16367 {
14663 16368 mptsas_t *mpt = DIP2MPT(pdip);
14664 16369 struct smp_device smp_sd;
14665 16370
14666 16371 /* XXX An HBA driver should not be allocating an smp_device. */
14667 16372 bzero(&smp_sd, sizeof (struct smp_device));
14668 16373 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
14669 16374 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
14670 16375
14671 16376 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
14672 16377 return (NDI_FAILURE);
14673 16378 return (NDI_SUCCESS);
14674 16379 }
14675 16380
14676 16381 static int
14677 16382 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
14678 16383 {
14679 16384 mptsas_t *mpt = DIP2MPT(pdip);
14680 16385 mptsas_smp_t *psmp = NULL;
14681 16386 int rval;
14682 16387 int phymask;
14683 16388
14684 16389 /*
14685 16390 * Get the physical port associated to the iport
14686 16391 * PHYMASK TODO
14687 16392 */
14688 16393 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14689 16394 "phymask", 0);
14690 16395 /*
14691 16396 * Find the smp node in hash table with specified sas address and
14692 16397 * physical port
14693 16398 */
14694 16399 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
14695 16400 if (psmp == NULL) {
14696 16401 return (DDI_FAILURE);
14697 16402 }
14698 16403
14699 16404 rval = mptsas_online_smp(pdip, psmp, smp_dip);
14700 16405
14701 16406 return (rval);
14702 16407 }
14703 16408
14704 16409 static int
14705 16410 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
14706 16411 dev_info_t **smp_dip)
14707 16412 {
14708 16413 char wwn_str[MPTSAS_WWN_STRLEN];
14709 16414 char attached_wwn_str[MPTSAS_WWN_STRLEN];
14710 16415 int ndi_rtn = NDI_FAILURE;
14711 16416 int rval = 0;
14712 16417 mptsas_smp_t dev_info;
14713 16418 uint32_t page_address;
14714 16419 mptsas_t *mpt = DIP2MPT(pdip);
14715 16420 uint16_t dev_hdl;
14716 16421 uint64_t sas_wwn;
|
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50 lines elided |
↑ open up ↑ |
14717 16422 uint64_t smp_sas_wwn;
14718 16423 uint8_t physport;
14719 16424 uint8_t phy_id;
14720 16425 uint16_t pdev_hdl;
14721 16426 uint8_t numphys = 0;
14722 16427 uint16_t i = 0;
14723 16428 char phymask[MPTSAS_MAX_PHYS];
14724 16429 char *iport = NULL;
14725 16430 mptsas_phymask_t phy_mask = 0;
14726 16431 uint16_t attached_devhdl;
14727 - uint16_t bay_num, enclosure;
16432 + uint16_t bay_num, enclosure, io_flags;
14728 16433
14729 16434 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
14730 16435
14731 16436 /*
14732 16437 * Probe smp device, prevent the node of removed device from being
14733 16438 * configured succesfully
14734 16439 */
14735 16440 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) {
14736 16441 return (DDI_FAILURE);
14737 16442 }
14738 16443
14739 16444 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
14740 16445 return (DDI_SUCCESS);
14741 16446 }
14742 16447
14743 16448 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
14744 16449
14745 16450 /*
14746 16451 * if lun alloc success, set props
14747 16452 */
14748 16453 if (ndi_rtn == NDI_SUCCESS) {
14749 16454 /*
14750 16455 * Set the flavor of the child to be SMP flavored
14751 16456 */
14752 16457 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
14753 16458
14754 16459 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14755 16460 *smp_dip, SMP_WWN, wwn_str) !=
14756 16461 DDI_PROP_SUCCESS) {
14757 16462 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14758 16463 "property for smp device %s (sas_wwn)",
14759 16464 wwn_str);
14760 16465 ndi_rtn = NDI_FAILURE;
14761 16466 goto smp_create_done;
14762 16467 }
14763 16468 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn);
14764 16469 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14765 16470 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
14766 16471 DDI_PROP_SUCCESS) {
14767 16472 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14768 16473 "property for iport target-port %s (sas_wwn)",
14769 16474 wwn_str);
14770 16475 ndi_rtn = NDI_FAILURE;
14771 16476 goto smp_create_done;
14772 16477 }
14773 16478
14774 16479 mutex_enter(&mpt->m_mutex);
14775 16480
14776 16481 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
14777 16482 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
14778 16483 rval = mptsas_get_sas_expander_page0(mpt, page_address,
14779 16484 &dev_info);
14780 16485 if (rval != DDI_SUCCESS) {
14781 16486 mutex_exit(&mpt->m_mutex);
14782 16487 mptsas_log(mpt, CE_WARN,
14783 16488 "mptsas unable to get expander "
|
↓ open down ↓ |
46 lines elided |
↑ open up ↑ |
14784 16489 "parent device info for %x", page_address);
14785 16490 ndi_rtn = NDI_FAILURE;
14786 16491 goto smp_create_done;
14787 16492 }
14788 16493
14789 16494 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
14790 16495 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14791 16496 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14792 16497 (uint32_t)dev_info.m_pdevhdl;
14793 16498 rval = mptsas_get_sas_device_page0(mpt, page_address,
14794 - &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo,
14795 - &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
16499 + &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport,
16500 + &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
14796 16501 if (rval != DDI_SUCCESS) {
14797 16502 mutex_exit(&mpt->m_mutex);
14798 16503 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14799 16504 "device info for %x", page_address);
14800 16505 ndi_rtn = NDI_FAILURE;
14801 16506 goto smp_create_done;
14802 16507 }
14803 16508
14804 16509 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14805 16510 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14806 16511 (uint32_t)dev_info.m_devhdl;
14807 16512 rval = mptsas_get_sas_device_page0(mpt, page_address,
14808 16513 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
14809 - &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
16514 + &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure,
16515 + &io_flags);
14810 16516 if (rval != DDI_SUCCESS) {
14811 16517 mutex_exit(&mpt->m_mutex);
14812 16518 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14813 16519 "device info for %x", page_address);
14814 16520 ndi_rtn = NDI_FAILURE;
14815 16521 goto smp_create_done;
14816 16522 }
14817 16523 mutex_exit(&mpt->m_mutex);
14818 16524
14819 16525 /*
14820 16526 * If this smp direct attached to the controller
14821 16527 * set the attached-port to the base wwid
14822 16528 */
14823 16529 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14824 16530 != DEVINFO_DIRECT_ATTACHED) {
14825 16531 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
14826 16532 sas_wwn);
14827 16533 } else {
14828 16534 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
14829 16535 mpt->un.m_base_wwid);
14830 16536 }
14831 16537
14832 16538 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14833 16539 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
14834 16540 DDI_PROP_SUCCESS) {
14835 16541 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14836 16542 "property for smp attached-port %s (sas_wwn)",
14837 16543 attached_wwn_str);
14838 16544 ndi_rtn = NDI_FAILURE;
14839 16545 goto smp_create_done;
14840 16546 }
14841 16547
14842 16548 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14843 16549 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
14844 16550 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14845 16551 "create property for SMP %s (SMP_PROP) ",
14846 16552 wwn_str);
14847 16553 ndi_rtn = NDI_FAILURE;
14848 16554 goto smp_create_done;
14849 16555 }
14850 16556
14851 16557 /*
14852 16558 * check the smp to see whether it direct
14853 16559 * attached to the controller
14854 16560 */
14855 16561 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14856 16562 != DEVINFO_DIRECT_ATTACHED) {
14857 16563 goto smp_create_done;
14858 16564 }
14859 16565 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
14860 16566 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
14861 16567 if (numphys > 0) {
14862 16568 goto smp_create_done;
14863 16569 }
14864 16570 /*
14865 16571 * this iport is an old iport, we need to
14866 16572 * reconfig the props for it.
14867 16573 */
14868 16574 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
14869 16575 MPTSAS_VIRTUAL_PORT, 0) !=
14870 16576 DDI_PROP_SUCCESS) {
14871 16577 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14872 16578 MPTSAS_VIRTUAL_PORT);
14873 16579 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
14874 16580 "prop update failed");
14875 16581 goto smp_create_done;
14876 16582 }
14877 16583
14878 16584 mutex_enter(&mpt->m_mutex);
14879 16585 numphys = 0;
14880 16586 iport = ddi_get_name_addr(pdip);
14881 16587 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
14882 16588 bzero(phymask, sizeof (phymask));
14883 16589 (void) sprintf(phymask,
14884 16590 "%x", mpt->m_phy_info[i].phy_mask);
14885 16591 if (strcmp(phymask, iport) == 0) {
14886 16592 phy_mask = mpt->m_phy_info[i].phy_mask;
14887 16593 break;
14888 16594 }
14889 16595 }
14890 16596
14891 16597 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
14892 16598 if ((phy_mask >> i) & 0x01) {
14893 16599 numphys++;
14894 16600 }
14895 16601 }
14896 16602 /*
14897 16603 * Update PHY info for smhba
14898 16604 */
14899 16605 if (mptsas_smhba_phy_init(mpt)) {
14900 16606 mutex_exit(&mpt->m_mutex);
14901 16607 mptsas_log(mpt, CE_WARN, "mptsas phy update "
14902 16608 "failed");
14903 16609 goto smp_create_done;
14904 16610 }
14905 16611 mutex_exit(&mpt->m_mutex);
14906 16612
14907 16613 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask,
14908 16614 &attached_devhdl);
14909 16615
14910 16616 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
14911 16617 MPTSAS_NUM_PHYS, numphys) !=
14912 16618 DDI_PROP_SUCCESS) {
14913 16619 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14914 16620 MPTSAS_NUM_PHYS);
14915 16621 mptsas_log(mpt, CE_WARN, "mptsas update "
14916 16622 "num phys props failed");
14917 16623 goto smp_create_done;
14918 16624 }
14919 16625 /*
14920 16626 * Add parent's props for SMHBA support
14921 16627 */
14922 16628 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
14923 16629 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14924 16630 DDI_PROP_SUCCESS) {
14925 16631 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14926 16632 SCSI_ADDR_PROP_ATTACHED_PORT);
14927 16633 mptsas_log(mpt, CE_WARN, "mptsas update iport"
14928 16634 "attached-port failed");
14929 16635 goto smp_create_done;
14930 16636 }
14931 16637
14932 16638 smp_create_done:
14933 16639 /*
14934 16640 * If props were setup ok, online the lun
14935 16641 */
14936 16642 if (ndi_rtn == NDI_SUCCESS) {
14937 16643 /*
14938 16644 * Try to online the new node
14939 16645 */
14940 16646 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
14941 16647 }
14942 16648
14943 16649 /*
14944 16650 * If success set rtn flag, else unwire alloc'd lun
14945 16651 */
14946 16652 if (ndi_rtn != NDI_SUCCESS) {
14947 16653 NDBG12(("mptsas unable to online "
14948 16654 "SMP target %s", wwn_str));
14949 16655 ndi_prop_remove_all(*smp_dip);
14950 16656 (void) ndi_devi_free(*smp_dip);
14951 16657 }
14952 16658 }
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14953 16659
14954 16660 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14955 16661 }
14956 16662
14957 16663 /* smp transport routine */
14958 16664 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
14959 16665 {
14960 16666 uint64_t wwn;
14961 16667 Mpi2SmpPassthroughRequest_t req;
14962 16668 Mpi2SmpPassthroughReply_t rep;
14963 - uint32_t direction = 0;
16669 + uint8_t direction = 0;
14964 16670 mptsas_t *mpt;
14965 16671 int ret;
14966 16672 uint64_t tmp64;
14967 16673
14968 16674 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
14969 16675 smp_a_hba_tran->smp_tran_hba_private;
14970 16676
14971 16677 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
14972 16678 /*
14973 16679 * Need to compose a SMP request message
14974 16680 * and call mptsas_do_passthru() function
14975 16681 */
14976 16682 bzero(&req, sizeof (req));
14977 16683 bzero(&rep, sizeof (rep));
14978 16684 req.PassthroughFlags = 0;
14979 16685 req.PhysicalPort = 0xff;
14980 16686 req.ChainOffset = 0;
14981 16687 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
14982 16688
14983 16689 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
14984 16690 smp_pkt->smp_pkt_reason = ERANGE;
14985 16691 return (DDI_FAILURE);
14986 16692 }
14987 16693 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
14988 16694
14989 16695 req.MsgFlags = 0;
14990 16696 tmp64 = LE_64(wwn);
14991 16697 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
14992 16698 if (smp_pkt->smp_pkt_rspsize > 0) {
14993 16699 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
14994 16700 }
14995 16701 if (smp_pkt->smp_pkt_reqsize > 0) {
14996 16702 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
14997 16703 }
14998 16704
14999 16705 mutex_enter(&mpt->m_mutex);
15000 16706 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
15001 16707 (uint8_t *)smp_pkt->smp_pkt_rsp,
15002 16708 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
15003 16709 smp_pkt->smp_pkt_rspsize - 4, direction,
15004 16710 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
15005 16711 smp_pkt->smp_pkt_timeout, FKIOCTL);
15006 16712 mutex_exit(&mpt->m_mutex);
15007 16713 if (ret != 0) {
15008 16714 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
15009 16715 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
15010 16716 return (DDI_FAILURE);
15011 16717 }
15012 16718 /* do passthrough success, check the smp status */
15013 16719 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15014 16720 switch (LE_16(rep.IOCStatus)) {
15015 16721 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
15016 16722 smp_pkt->smp_pkt_reason = ENODEV;
15017 16723 break;
15018 16724 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
15019 16725 smp_pkt->smp_pkt_reason = EOVERFLOW;
15020 16726 break;
15021 16727 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
15022 16728 smp_pkt->smp_pkt_reason = EIO;
15023 16729 break;
15024 16730 default:
15025 16731 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
15026 16732 "status:%x", LE_16(rep.IOCStatus));
15027 16733 smp_pkt->smp_pkt_reason = EIO;
15028 16734 break;
15029 16735 }
15030 16736 return (DDI_FAILURE);
15031 16737 }
15032 16738 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
15033 16739 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
15034 16740 rep.SASStatus);
15035 16741 smp_pkt->smp_pkt_reason = EIO;
15036 16742 return (DDI_FAILURE);
15037 16743 }
15038 16744
15039 16745 return (DDI_SUCCESS);
15040 16746 }
15041 16747
15042 16748 /*
15043 16749 * If we didn't get a match, we need to get sas page0 for each device, and
15044 16750 * untill we get a match. If failed, return NULL
15045 16751 */
15046 16752 static mptsas_target_t *
15047 16753 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy)
15048 16754 {
15049 16755 int i, j = 0;
15050 16756 int rval = 0;
15051 16757 uint16_t cur_handle;
15052 16758 uint32_t page_address;
15053 16759 mptsas_target_t *ptgt = NULL;
15054 16760
15055 16761 /*
15056 16762 * PHY named device must be direct attached and attaches to
15057 16763 * narrow port, if the iport is not parent of the device which
15058 16764 * we are looking for.
15059 16765 */
15060 16766 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15061 16767 if ((1 << i) & phymask)
15062 16768 j++;
15063 16769 }
15064 16770
15065 16771 if (j > 1)
15066 16772 return (NULL);
15067 16773
15068 16774 /*
15069 16775 * Must be a narrow port and single device attached to the narrow port
15070 16776 * So the physical port num of device which is equal to the iport's
15071 16777 * port num is the device what we are looking for.
15072 16778 */
15073 16779
15074 16780 if (mpt->m_phy_info[phy].phy_mask != phymask)
15075 16781 return (NULL);
15076 16782
15077 16783 mutex_enter(&mpt->m_mutex);
15078 16784
15079 16785 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn,
15080 16786 &phy);
15081 16787 if (ptgt != NULL) {
15082 16788 mutex_exit(&mpt->m_mutex);
15083 16789 return (ptgt);
15084 16790 }
15085 16791
15086 16792 if (mpt->m_done_traverse_dev) {
15087 16793 mutex_exit(&mpt->m_mutex);
15088 16794 return (NULL);
15089 16795 }
15090 16796
15091 16797 /* If didn't get a match, come here */
15092 16798 cur_handle = mpt->m_dev_handle;
15093 16799 for (; ; ) {
15094 16800 ptgt = NULL;
15095 16801 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15096 16802 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15097 16803 rval = mptsas_get_target_device_info(mpt, page_address,
15098 16804 &cur_handle, &ptgt);
15099 16805 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15100 16806 (rval == DEV_INFO_FAIL_ALLOC)) {
15101 16807 break;
15102 16808 }
15103 16809 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15104 16810 (rval == DEV_INFO_PHYS_DISK)) {
15105 16811 continue;
15106 16812 }
15107 16813 mpt->m_dev_handle = cur_handle;
15108 16814
15109 16815 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) {
15110 16816 break;
15111 16817 }
15112 16818 }
15113 16819
15114 16820 mutex_exit(&mpt->m_mutex);
15115 16821 return (ptgt);
15116 16822 }
15117 16823
15118 16824 /*
15119 16825 * The ptgt->m_addr.mta_wwn contains the wwid for each disk.
15120 16826 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
15121 16827 * If we didn't get a match, we need to get sas page0 for each device, and
15122 16828 * untill we get a match
15123 16829 * If failed, return NULL
15124 16830 */
15125 16831 static mptsas_target_t *
15126 16832 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
15127 16833 {
15128 16834 int rval = 0;
15129 16835 uint16_t cur_handle;
15130 16836 uint32_t page_address;
15131 16837 mptsas_target_t *tmp_tgt = NULL;
15132 16838 mptsas_target_addr_t addr;
15133 16839
15134 16840 addr.mta_wwn = wwid;
15135 16841 addr.mta_phymask = phymask;
15136 16842 mutex_enter(&mpt->m_mutex);
15137 16843 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
15138 16844 if (tmp_tgt != NULL) {
15139 16845 mutex_exit(&mpt->m_mutex);
15140 16846 return (tmp_tgt);
15141 16847 }
15142 16848
15143 16849 if (phymask == 0) {
15144 16850 /*
15145 16851 * It's IR volume
15146 16852 */
15147 16853 rval = mptsas_get_raid_info(mpt);
15148 16854 if (rval) {
15149 16855 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
15150 16856 }
15151 16857 mutex_exit(&mpt->m_mutex);
15152 16858 return (tmp_tgt);
15153 16859 }
15154 16860
15155 16861 if (mpt->m_done_traverse_dev) {
15156 16862 mutex_exit(&mpt->m_mutex);
15157 16863 return (NULL);
15158 16864 }
15159 16865
15160 16866 /* If didn't get a match, come here */
15161 16867 cur_handle = mpt->m_dev_handle;
15162 16868 for (;;) {
15163 16869 tmp_tgt = NULL;
15164 16870 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15165 16871 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
15166 16872 rval = mptsas_get_target_device_info(mpt, page_address,
15167 16873 &cur_handle, &tmp_tgt);
15168 16874 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15169 16875 (rval == DEV_INFO_FAIL_ALLOC)) {
15170 16876 tmp_tgt = NULL;
15171 16877 break;
15172 16878 }
15173 16879 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15174 16880 (rval == DEV_INFO_PHYS_DISK)) {
15175 16881 continue;
15176 16882 }
15177 16883 mpt->m_dev_handle = cur_handle;
15178 16884 if ((tmp_tgt->m_addr.mta_wwn) &&
15179 16885 (tmp_tgt->m_addr.mta_wwn == wwid) &&
15180 16886 (tmp_tgt->m_addr.mta_phymask == phymask)) {
15181 16887 break;
15182 16888 }
15183 16889 }
15184 16890
15185 16891 mutex_exit(&mpt->m_mutex);
15186 16892 return (tmp_tgt);
15187 16893 }
15188 16894
15189 16895 static mptsas_smp_t *
15190 16896 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
15191 16897 {
15192 16898 int rval = 0;
15193 16899 uint16_t cur_handle;
15194 16900 uint32_t page_address;
15195 16901 mptsas_smp_t smp_node, *psmp = NULL;
15196 16902 mptsas_target_addr_t addr;
15197 16903
15198 16904 addr.mta_wwn = wwid;
15199 16905 addr.mta_phymask = phymask;
15200 16906 mutex_enter(&mpt->m_mutex);
15201 16907 psmp = refhash_lookup(mpt->m_smp_targets, &addr);
15202 16908 if (psmp != NULL) {
15203 16909 mutex_exit(&mpt->m_mutex);
15204 16910 return (psmp);
15205 16911 }
15206 16912
15207 16913 if (mpt->m_done_traverse_smp) {
15208 16914 mutex_exit(&mpt->m_mutex);
15209 16915 return (NULL);
15210 16916 }
15211 16917
15212 16918 /* If didn't get a match, come here */
15213 16919 cur_handle = mpt->m_smp_devhdl;
15214 16920 for (;;) {
15215 16921 psmp = NULL;
15216 16922 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
15217 16923 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15218 16924 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15219 16925 &smp_node);
15220 16926 if (rval != DDI_SUCCESS) {
15221 16927 break;
15222 16928 }
15223 16929 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
15224 16930 psmp = mptsas_smp_alloc(mpt, &smp_node);
15225 16931 ASSERT(psmp);
15226 16932 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) &&
15227 16933 (psmp->m_addr.mta_phymask == phymask)) {
15228 16934 break;
15229 16935 }
15230 16936 }
15231 16937
15232 16938 mutex_exit(&mpt->m_mutex);
15233 16939 return (psmp);
15234 16940 }
15235 16941
15236 16942 mptsas_target_t *
15237 16943 mptsas_tgt_alloc(mptsas_t *mpt, uint16_t devhdl, uint64_t wwid,
15238 16944 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum)
15239 16945 {
15240 16946 mptsas_target_t *tmp_tgt = NULL;
15241 16947 mptsas_target_addr_t addr;
15242 16948
15243 16949 addr.mta_wwn = wwid;
15244 16950 addr.mta_phymask = phymask;
15245 16951 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
15246 16952 if (tmp_tgt != NULL) {
15247 16953 NDBG20(("Hash item already exist"));
15248 16954 tmp_tgt->m_deviceinfo = devinfo;
15249 16955 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */
15250 16956 return (tmp_tgt);
15251 16957 }
15252 16958 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
15253 16959 if (tmp_tgt == NULL) {
15254 16960 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
15255 16961 return (NULL);
15256 16962 }
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15257 16963 tmp_tgt->m_devhdl = devhdl;
15258 16964 tmp_tgt->m_addr.mta_wwn = wwid;
15259 16965 tmp_tgt->m_deviceinfo = devinfo;
15260 16966 tmp_tgt->m_addr.mta_phymask = phymask;
15261 16967 tmp_tgt->m_phynum = phynum;
15262 16968 /* Initialized the tgt structure */
15263 16969 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
15264 16970 tmp_tgt->m_qfull_retry_interval =
15265 16971 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
15266 16972 tmp_tgt->m_t_throttle = MAX_THROTTLE;
16973 + mutex_init(&tmp_tgt->m_t_mutex, NULL, MUTEX_DRIVER, NULL);
16974 + TAILQ_INIT(&tmp_tgt->m_active_cmdq);
15267 16975
15268 16976 refhash_insert(mpt->m_targets, tmp_tgt);
15269 16977
15270 16978 return (tmp_tgt);
15271 16979 }
15272 16980
16981 +static void
16982 +mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst)
16983 +{
16984 + dst->m_devhdl = src->m_devhdl;
16985 + dst->m_deviceinfo = src->m_deviceinfo;
16986 + dst->m_pdevhdl = src->m_pdevhdl;
16987 + dst->m_pdevinfo = src->m_pdevinfo;
16988 +}
16989 +
15273 16990 static mptsas_smp_t *
15274 16991 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data)
15275 16992 {
15276 16993 mptsas_target_addr_t addr;
15277 16994 mptsas_smp_t *ret_data;
15278 16995
15279 16996 addr.mta_wwn = data->m_addr.mta_wwn;
15280 16997 addr.mta_phymask = data->m_addr.mta_phymask;
15281 16998 ret_data = refhash_lookup(mpt->m_smp_targets, &addr);
16999 + /*
17000 + * If there's already a matching SMP target, update its fields
17001 + * in place. Since the address is not changing, it's safe to do
17002 + * this. We cannot just bcopy() here because the structure we've
17003 + * been given has invalid hash links.
17004 + */
15282 17005 if (ret_data != NULL) {
15283 - bcopy(data, ret_data, sizeof (mptsas_smp_t)); /* XXX - dupl */
17006 + mptsas_smp_target_copy(data, ret_data);
15284 17007 return (ret_data);
15285 17008 }
15286 17009
15287 17010 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
15288 17011 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15289 17012 refhash_insert(mpt->m_smp_targets, ret_data);
15290 17013 return (ret_data);
15291 17014 }
15292 17015
15293 17016 /*
15294 17017 * Functions for SGPIO LED support
15295 17018 */
15296 17019 static dev_info_t *
15297 17020 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
15298 17021 {
15299 17022 dev_info_t *dip;
15300 17023 int prop;
15301 17024 dip = e_ddi_hold_devi_by_dev(dev, 0);
15302 17025 if (dip == NULL)
15303 17026 return (dip);
15304 17027 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
15305 17028 "phymask", 0);
15306 17029 *phymask = (mptsas_phymask_t)prop;
15307 17030 ddi_release_devi(dip);
15308 17031 return (dip);
15309 17032 }
15310 17033 static mptsas_target_t *
15311 17034 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
15312 17035 {
15313 17036 uint8_t phynum;
15314 17037 uint64_t wwn;
15315 17038 int lun;
15316 17039 mptsas_target_t *ptgt = NULL;
15317 17040
15318 17041 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
15319 17042 return (NULL);
15320 17043 }
15321 17044 if (addr[0] == 'w') {
15322 17045 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
15323 17046 } else {
15324 17047 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
15325 17048 }
15326 17049 return (ptgt);
15327 17050 }
15328 17051
15329 17052 static int
15330 17053 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt)
15331 17054 {
15332 17055 uint32_t slotstatus = 0;
15333 17056
15334 17057 /* Build an MPI2 Slot Status based on our view of the world */
15335 17058 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
15336 17059 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
15337 17060 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
15338 17061 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
15339 17062 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
15340 17063 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
15341 17064
15342 17065 /* Write it to the controller */
15343 17066 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
15344 17067 slotstatus, ptgt->m_slot_num));
15345 17068 return (mptsas_send_sep(mpt, ptgt, &slotstatus,
15346 17069 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
15347 17070 }
15348 17071
15349 17072 /*
15350 17073 * send sep request, use enclosure/slot addressing
15351 17074 */
15352 17075 static int
15353 17076 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
15354 17077 uint32_t *status, uint8_t act)
15355 17078 {
15356 17079 Mpi2SepRequest_t req;
15357 17080 Mpi2SepReply_t rep;
15358 17081 int ret;
15359 17082
15360 17083 ASSERT(mutex_owned(&mpt->m_mutex));
15361 17084
15362 17085 /*
15363 17086 * We only support SEP control of directly-attached targets, in which
15364 17087 * case the "SEP" we're talking to is a virtual one contained within
15365 17088 * the HBA itself. This is necessary because DA targets typically have
15366 17089 * no other mechanism for LED control. Targets for which a separate
15367 17090 * enclosure service processor exists should be controlled via ses(7d)
15368 17091 * or sgen(7d). Furthermore, since such requests can time out, they
15369 17092 * should be made in user context rather than in response to
15370 17093 * asynchronous fabric changes.
15371 17094 *
15372 17095 * In addition, we do not support this operation for RAID volumes,
15373 17096 * since there is no slot associated with them.
15374 17097 */
15375 17098 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) ||
15376 17099 ptgt->m_addr.mta_phymask == 0) {
15377 17100 return (ENOTTY);
15378 17101 }
15379 17102
15380 17103 bzero(&req, sizeof (req));
15381 17104 bzero(&rep, sizeof (rep));
15382 17105
15383 17106 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
15384 17107 req.Action = act;
15385 17108 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
15386 17109 req.EnclosureHandle = LE_16(ptgt->m_enclosure);
15387 17110 req.Slot = LE_16(ptgt->m_slot_num);
15388 17111 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
15389 17112 req.SlotStatus = LE_32(*status);
15390 17113 }
15391 17114 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
15392 17115 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
15393 17116 if (ret != 0) {
15394 17117 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
15395 17118 "Processor Request message error %d", ret);
15396 17119 return (ret);
15397 17120 }
15398 17121 /* do passthrough success, check the ioc status */
15399 17122 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15400 17123 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
15401 17124 "status:%x loginfo %x", act, LE_16(rep.IOCStatus),
15402 17125 LE_32(rep.IOCLogInfo));
15403 17126 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) {
15404 17127 case MPI2_IOCSTATUS_INVALID_FUNCTION:
15405 17128 case MPI2_IOCSTATUS_INVALID_VPID:
15406 17129 case MPI2_IOCSTATUS_INVALID_FIELD:
15407 17130 case MPI2_IOCSTATUS_INVALID_STATE:
15408 17131 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
15409 17132 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
15410 17133 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
15411 17134 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
15412 17135 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
15413 17136 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
15414 17137 return (EINVAL);
15415 17138 case MPI2_IOCSTATUS_BUSY:
15416 17139 return (EBUSY);
15417 17140 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
15418 17141 return (EAGAIN);
15419 17142 case MPI2_IOCSTATUS_INVALID_SGL:
15420 17143 case MPI2_IOCSTATUS_INTERNAL_ERROR:
15421 17144 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
15422 17145 default:
15423 17146 return (EIO);
15424 17147 }
15425 17148 }
15426 17149 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
15427 17150 *status = LE_32(rep.SlotStatus);
15428 17151 }
15429 17152
15430 17153 return (0);
15431 17154 }
15432 17155
15433 17156 int
15434 17157 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
15435 17158 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
15436 17159 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
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15437 17160 {
15438 17161 ddi_dma_cookie_t new_cookie;
15439 17162 size_t alloc_len;
15440 17163 uint_t ncookie;
15441 17164
15442 17165 if (cookiep == NULL)
15443 17166 cookiep = &new_cookie;
15444 17167
15445 17168 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
15446 17169 NULL, dma_hdp) != DDI_SUCCESS) {
15447 - dma_hdp = NULL;
15448 17170 return (FALSE);
15449 17171 }
15450 17172
15451 17173 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
15452 17174 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
15453 17175 acc_hdp) != DDI_SUCCESS) {
15454 17176 ddi_dma_free_handle(dma_hdp);
15455 - dma_hdp = NULL;
15456 17177 return (FALSE);
15457 17178 }
15458 17179
15459 17180 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
15460 17181 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
15461 17182 cookiep, &ncookie) != DDI_DMA_MAPPED) {
15462 17183 (void) ddi_dma_mem_free(acc_hdp);
15463 17184 ddi_dma_free_handle(dma_hdp);
15464 - dma_hdp = NULL;
15465 17185 return (FALSE);
15466 17186 }
15467 17187
15468 17188 return (TRUE);
15469 17189 }
15470 17190
15471 17191 void
15472 17192 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
15473 17193 {
15474 17194 if (*dma_hdp == NULL)
15475 17195 return;
15476 17196
15477 17197 (void) ddi_dma_unbind_handle(*dma_hdp);
15478 17198 (void) ddi_dma_mem_free(acc_hdp);
15479 17199 ddi_dma_free_handle(dma_hdp);
15480 - dma_hdp = NULL;
15481 17200 }
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