1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 25 * Copyright (c) 2014, Joyent, Inc. All rights reserved. 26 */ 27 28 /* 29 * Copyright (c) 2000 to 2010, LSI Corporation. 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms of all code within 33 * this file that is exclusively owned by LSI, with or without 34 * modification, is permitted provided that, in addition to the CDDL 1.0 35 * License requirements, the following conditions are met: 36 * 37 * Neither the name of the author nor the names of its contributors may be 38 * used to endorse or promote products derived from this software without 39 * specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 42 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 43 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 44 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 45 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 47 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 48 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 49 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 52 * DAMAGE. 53 */ 54 55 /* 56 * mptsas - This is a driver based on LSI Logic's MPT2.0 interface. 57 * 58 */ 59 60 #if defined(lint) || defined(DEBUG) 61 #define MPTSAS_DEBUG 62 #endif 63 64 /* 65 * standard header files. 66 */ 67 #include <sys/note.h> 68 #include <sys/scsi/scsi.h> 69 #include <sys/pci.h> 70 #include <sys/file.h> 71 #include <sys/policy.h> 72 #include <sys/model.h> 73 #include <sys/sysevent.h> 74 #include <sys/sysevent/eventdefs.h> 75 #include <sys/sysevent/dr.h> 76 #include <sys/sata/sata_defs.h> 77 #include <sys/scsi/generic/sas.h> 78 #include <sys/scsi/impl/scsi_sas.h> 79 80 #pragma pack(1) 81 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h> 82 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h> 83 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h> 85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h> 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h> 87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h> 89 #pragma pack() 90 91 /* 92 * private header files. 93 * 94 */ 95 #include <sys/scsi/impl/scsi_reset_notify.h> 96 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h> 97 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 98 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h> 99 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h> 100 #include <sys/raidioctl.h> 101 102 #include <sys/fs/dv_node.h> /* devfs_clean */ 103 104 /* 105 * FMA header files 106 */ 107 #include <sys/ddifm.h> 108 #include <sys/fm/protocol.h> 109 #include <sys/fm/util.h> 110 #include <sys/fm/io/ddi.h> 111 112 /* 113 * autoconfiguration data and routines. 114 */ 115 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 116 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 117 static int mptsas_power(dev_info_t *dip, int component, int level); 118 119 /* 120 * cb_ops function 121 */ 122 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 123 cred_t *credp, int *rval); 124 #ifdef __sparc 125 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd); 126 #else /* __sparc */ 127 static int mptsas_quiesce(dev_info_t *devi); 128 #endif /* __sparc */ 129 130 /* 131 * Resource initilaization for hardware 132 */ 133 static void mptsas_setup_cmd_reg(mptsas_t *mpt); 134 static void mptsas_disable_bus_master(mptsas_t *mpt); 135 static void mptsas_hba_fini(mptsas_t *mpt); 136 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp); 137 static int mptsas_hba_setup(mptsas_t *mpt); 138 static void mptsas_hba_teardown(mptsas_t *mpt); 139 static int mptsas_config_space_init(mptsas_t *mpt); 140 static void mptsas_config_space_fini(mptsas_t *mpt); 141 static void mptsas_iport_register(mptsas_t *mpt); 142 static int mptsas_smp_setup(mptsas_t *mpt); 143 static void mptsas_smp_teardown(mptsas_t *mpt); 144 static int mptsas_cache_create(mptsas_t *mpt); 145 static void mptsas_cache_destroy(mptsas_t *mpt); 146 static int mptsas_alloc_request_frames(mptsas_t *mpt); 147 static int mptsas_alloc_reply_frames(mptsas_t *mpt); 148 static int mptsas_alloc_free_queue(mptsas_t *mpt); 149 static int mptsas_alloc_post_queue(mptsas_t *mpt); 150 static void mptsas_alloc_reply_args(mptsas_t *mpt); 151 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 152 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 153 static int mptsas_init_chip(mptsas_t *mpt, int first_time); 154 155 /* 156 * SCSA function prototypes 157 */ 158 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt); 159 static int mptsas_scsi_reset(struct scsi_address *ap, int level); 160 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt); 161 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly); 162 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, 163 int tgtonly); 164 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt); 165 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap, 166 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 167 int tgtlen, int flags, int (*callback)(), caddr_t arg); 168 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt); 169 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap, 170 struct scsi_pkt *pkt); 171 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 172 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 173 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 174 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 175 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 176 void (*callback)(caddr_t), caddr_t arg); 177 static int mptsas_get_name(struct scsi_device *sd, char *name, int len); 178 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len); 179 static int mptsas_scsi_quiesce(dev_info_t *dip); 180 static int mptsas_scsi_unquiesce(dev_info_t *dip); 181 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags, 182 ddi_bus_config_op_t op, void *arg, dev_info_t **childp); 183 184 /* 185 * SMP functions 186 */ 187 static int mptsas_smp_start(struct smp_pkt *smp_pkt); 188 189 /* 190 * internal function prototypes. 191 */ 192 static void mptsas_list_add(mptsas_t *mpt); 193 static void mptsas_list_del(mptsas_t *mpt); 194 195 static int mptsas_quiesce_bus(mptsas_t *mpt); 196 static int mptsas_unquiesce_bus(mptsas_t *mpt); 197 198 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size); 199 static void mptsas_free_handshake_msg(mptsas_t *mpt); 200 201 static void mptsas_ncmds_checkdrain(void *arg); 202 203 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd); 204 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 205 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 206 static void mptsas_accept_tx_waitq(mptsas_t *mpt); 207 208 static int mptsas_do_detach(dev_info_t *dev); 209 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl); 210 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, 211 struct scsi_pkt *pkt); 212 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp); 213 214 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd); 215 static void mptsas_handle_event(void *args); 216 static int mptsas_handle_event_sync(void *args); 217 static void mptsas_handle_dr(void *args); 218 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 219 dev_info_t *pdip); 220 221 static void mptsas_restart_cmd(void *); 222 223 static void mptsas_flush_hba(mptsas_t *mpt); 224 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, 225 uint8_t tasktype); 226 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, 227 uchar_t reason, uint_t stat); 228 229 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2); 230 static void mptsas_process_intr(mptsas_t *mpt, 231 pMpi2ReplyDescriptorsUnion_t reply_desc_union); 232 static void mptsas_handle_scsi_io_success(mptsas_t *mpt, 233 pMpi2ReplyDescriptorsUnion_t reply_desc); 234 static void mptsas_handle_address_reply(mptsas_t *mpt, 235 pMpi2ReplyDescriptorsUnion_t reply_desc); 236 static int mptsas_wait_intr(mptsas_t *mpt, int polltime); 237 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, 238 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl); 239 240 static void mptsas_watch(void *arg); 241 static void mptsas_watchsubr(mptsas_t *mpt); 242 static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl); 243 244 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd); 245 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 246 uint8_t *data, uint32_t request_size, uint32_t reply_size, 247 uint32_t data_size, uint32_t direction, uint8_t *dataout, 248 uint32_t dataout_size, short timeout, int mode); 249 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl); 250 251 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, 252 uint32_t unique_id); 253 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd); 254 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt, 255 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code); 256 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt, 257 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 258 uint32_t diag_type); 259 static int mptsas_diag_register(mptsas_t *mpt, 260 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code); 261 static int mptsas_diag_unregister(mptsas_t *mpt, 262 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code); 263 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 264 uint32_t *return_code); 265 static int mptsas_diag_read_buffer(mptsas_t *mpt, 266 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 267 uint32_t *return_code, int ioctl_mode); 268 static int mptsas_diag_release(mptsas_t *mpt, 269 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code); 270 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, 271 uint8_t *diag_action, uint32_t length, uint32_t *return_code, 272 int ioctl_mode); 273 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data, 274 int mode); 275 276 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 277 int cmdlen, int tgtlen, int statuslen, int kf); 278 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd); 279 280 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags); 281 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg); 282 283 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg, 284 int kmflags); 285 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg); 286 287 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 288 mptsas_cmd_t *cmd); 289 static void mptsas_check_task_mgt(mptsas_t *mpt, 290 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd); 291 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 292 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 293 int *resid); 294 295 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag); 296 static void mptsas_free_active_slots(mptsas_t *mpt); 297 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 298 299 static void mptsas_restart_hba(mptsas_t *mpt); 300 static void mptsas_restart_waitq(mptsas_t *mpt); 301 302 static void mptsas_deliver_doneq_thread(mptsas_t *mpt); 303 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 304 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t); 305 306 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t); 307 static void mptsas_doneq_empty(mptsas_t *mpt); 308 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg); 309 310 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt); 311 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 312 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt); 313 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 314 315 316 static void mptsas_start_watch_reset_delay(); 317 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt); 318 static void mptsas_watch_reset_delay(void *arg); 319 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt); 320 321 /* 322 * helper functions 323 */ 324 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 325 326 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name); 327 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy); 328 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, 329 int lun); 330 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr, 331 int lun); 332 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy); 333 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn); 334 335 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, 336 int *lun); 337 static int mptsas_parse_smp_name(char *name, uint64_t *wwn); 338 339 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, 340 mptsas_phymask_t phymask, uint8_t phy); 341 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, 342 mptsas_phymask_t phymask, uint64_t wwid); 343 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, 344 mptsas_phymask_t phymask, uint64_t wwid); 345 346 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, 347 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd); 348 349 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 350 uint16_t *handle, mptsas_target_t **pptgt); 351 static void mptsas_update_phymask(mptsas_t *mpt); 352 353 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt, 354 uint32_t *status, uint8_t cmd); 355 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev, 356 mptsas_phymask_t *phymask); 357 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, 358 mptsas_phymask_t phymask); 359 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt); 360 361 362 /* 363 * Enumeration / DR functions 364 */ 365 static void mptsas_config_all(dev_info_t *pdip); 366 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 367 dev_info_t **lundip); 368 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 369 dev_info_t **lundip); 370 371 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt); 372 static int mptsas_offline_target(dev_info_t *pdip, char *name); 373 374 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target, 375 dev_info_t **dip); 376 377 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt); 378 static int mptsas_probe_lun(dev_info_t *pdip, int lun, 379 dev_info_t **dip, mptsas_target_t *ptgt); 380 381 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 382 dev_info_t **dip, mptsas_target_t *ptgt, int lun); 383 384 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 385 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun); 386 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 387 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, 388 int lun); 389 390 static void mptsas_offline_missed_luns(dev_info_t *pdip, 391 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt); 392 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 393 mdi_pathinfo_t *rpip, uint_t flags); 394 395 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, 396 dev_info_t **smp_dip); 397 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 398 uint_t flags); 399 400 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, 401 int mode, int *rval); 402 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, 403 int mode, int *rval); 404 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, 405 int mode, int *rval); 406 static void mptsas_record_event(void *args); 407 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, 408 int mode); 409 410 mptsas_target_t *mptsas_tgt_alloc(mptsas_t *, uint16_t, uint64_t, 411 uint32_t, mptsas_phymask_t, uint8_t); 412 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *); 413 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 414 dev_info_t **smp_dip); 415 416 /* 417 * Power management functions 418 */ 419 static int mptsas_get_pci_cap(mptsas_t *mpt); 420 static int mptsas_init_pm(mptsas_t *mpt); 421 422 /* 423 * MPT MSI tunable: 424 * 425 * By default MSI is enabled on all supported platforms. 426 */ 427 boolean_t mptsas_enable_msi = B_TRUE; 428 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE; 429 430 static int mptsas_register_intrs(mptsas_t *); 431 static void mptsas_unregister_intrs(mptsas_t *); 432 static int mptsas_add_intrs(mptsas_t *, int); 433 static void mptsas_rem_intrs(mptsas_t *); 434 435 /* 436 * FMA Prototypes 437 */ 438 static void mptsas_fm_init(mptsas_t *mpt); 439 static void mptsas_fm_fini(mptsas_t *mpt); 440 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *); 441 442 extern pri_t minclsyspri, maxclsyspri; 443 444 /* 445 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is 446 * under this device that the paths to a physical device are created when 447 * MPxIO is used. 448 */ 449 extern dev_info_t *scsi_vhci_dip; 450 451 /* 452 * Tunable timeout value for Inquiry VPD page 0x83 453 * By default the value is 30 seconds. 454 */ 455 int mptsas_inq83_retry_timeout = 30; 456 457 /* 458 * This is used to allocate memory for message frame storage, not for 459 * data I/O DMA. All message frames must be stored in the first 4G of 460 * physical memory. 461 */ 462 ddi_dma_attr_t mptsas_dma_attrs = { 463 DMA_ATTR_V0, /* attribute layout version */ 464 0x0ull, /* address low - should be 0 (longlong) */ 465 0xffffffffull, /* address high - 32-bit max range */ 466 0x00ffffffull, /* count max - max DMA object size */ 467 4, /* allocation alignment requirements */ 468 0x78, /* burstsizes - binary encoded values */ 469 1, /* minxfer - gran. of DMA engine */ 470 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 471 0xffffffffull, /* max segment size (DMA boundary) */ 472 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 473 512, /* granularity - device transfer size */ 474 0 /* flags, set to 0 */ 475 }; 476 477 /* 478 * This is used for data I/O DMA memory allocation. (full 64-bit DMA 479 * physical addresses are supported.) 480 */ 481 ddi_dma_attr_t mptsas_dma_attrs64 = { 482 DMA_ATTR_V0, /* attribute layout version */ 483 0x0ull, /* address low - should be 0 (longlong) */ 484 0xffffffffffffffffull, /* address high - 64-bit max */ 485 0x00ffffffull, /* count max - max DMA object size */ 486 4, /* allocation alignment requirements */ 487 0x78, /* burstsizes - binary encoded values */ 488 1, /* minxfer - gran. of DMA engine */ 489 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 490 0xffffffffull, /* max segment size (DMA boundary) */ 491 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 492 512, /* granularity - device transfer size */ 493 DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */ 494 }; 495 496 ddi_device_acc_attr_t mptsas_dev_attr = { 497 DDI_DEVICE_ATTR_V1, 498 DDI_STRUCTURE_LE_ACC, 499 DDI_STRICTORDER_ACC, 500 DDI_DEFAULT_ACC 501 }; 502 503 static struct cb_ops mptsas_cb_ops = { 504 scsi_hba_open, /* open */ 505 scsi_hba_close, /* close */ 506 nodev, /* strategy */ 507 nodev, /* print */ 508 nodev, /* dump */ 509 nodev, /* read */ 510 nodev, /* write */ 511 mptsas_ioctl, /* ioctl */ 512 nodev, /* devmap */ 513 nodev, /* mmap */ 514 nodev, /* segmap */ 515 nochpoll, /* chpoll */ 516 ddi_prop_op, /* cb_prop_op */ 517 NULL, /* streamtab */ 518 D_MP, /* cb_flag */ 519 CB_REV, /* rev */ 520 nodev, /* aread */ 521 nodev /* awrite */ 522 }; 523 524 static struct dev_ops mptsas_ops = { 525 DEVO_REV, /* devo_rev, */ 526 0, /* refcnt */ 527 ddi_no_info, /* info */ 528 nulldev, /* identify */ 529 nulldev, /* probe */ 530 mptsas_attach, /* attach */ 531 mptsas_detach, /* detach */ 532 #ifdef __sparc 533 mptsas_reset, 534 #else 535 nodev, /* reset */ 536 #endif /* __sparc */ 537 &mptsas_cb_ops, /* driver operations */ 538 NULL, /* bus operations */ 539 mptsas_power, /* power management */ 540 #ifdef __sparc 541 ddi_quiesce_not_needed 542 #else 543 mptsas_quiesce /* quiesce */ 544 #endif /* __sparc */ 545 }; 546 547 548 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24" 549 550 static struct modldrv modldrv = { 551 &mod_driverops, /* Type of module. This one is a driver */ 552 MPTSAS_MOD_STRING, /* Name of the module. */ 553 &mptsas_ops, /* driver ops */ 554 }; 555 556 static struct modlinkage modlinkage = { 557 MODREV_1, &modldrv, NULL 558 }; 559 #define TARGET_PROP "target" 560 #define LUN_PROP "lun" 561 #define LUN64_PROP "lun64" 562 #define SAS_PROP "sas-mpt" 563 #define MDI_GUID "wwn" 564 #define NDI_GUID "guid" 565 #define MPTSAS_DEV_GONE "mptsas_dev_gone" 566 567 /* 568 * Local static data 569 */ 570 #if defined(MPTSAS_DEBUG) 571 uint32_t mptsas_debug_flags = 0; 572 #endif /* defined(MPTSAS_DEBUG) */ 573 uint32_t mptsas_debug_resets = 0; 574 575 static kmutex_t mptsas_global_mutex; 576 static void *mptsas_state; /* soft state ptr */ 577 static krwlock_t mptsas_global_rwlock; 578 579 static kmutex_t mptsas_log_mutex; 580 static char mptsas_log_buf[256]; 581 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf)) 582 583 static mptsas_t *mptsas_head, *mptsas_tail; 584 static clock_t mptsas_scsi_watchdog_tick; 585 static clock_t mptsas_tick; 586 static timeout_id_t mptsas_reset_watch; 587 static timeout_id_t mptsas_timeout_id; 588 static int mptsas_timeouts_enabled = 0; 589 /* 590 * warlock directives 591 */ 592 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \ 593 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status)) 594 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt)) 595 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address)) 596 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private)) 597 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private)) 598 599 /* 600 * SM - HBA statics 601 */ 602 char *mptsas_driver_rev = MPTSAS_MOD_STRING; 603 604 #ifdef MPTSAS_DEBUG 605 void debug_enter(char *); 606 #endif 607 608 /* 609 * Notes: 610 * - scsi_hba_init(9F) initializes SCSI HBA modules 611 * - must call scsi_hba_fini(9F) if modload() fails 612 */ 613 int 614 _init(void) 615 { 616 int status; 617 /* CONSTCOND */ 618 ASSERT(NO_COMPETING_THREADS); 619 620 NDBG0(("_init")); 621 622 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE, 623 MPTSAS_INITIAL_SOFT_SPACE); 624 if (status != 0) { 625 return (status); 626 } 627 628 if ((status = scsi_hba_init(&modlinkage)) != 0) { 629 ddi_soft_state_fini(&mptsas_state); 630 return (status); 631 } 632 633 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL); 634 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL); 635 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL); 636 637 if ((status = mod_install(&modlinkage)) != 0) { 638 mutex_destroy(&mptsas_log_mutex); 639 rw_destroy(&mptsas_global_rwlock); 640 mutex_destroy(&mptsas_global_mutex); 641 ddi_soft_state_fini(&mptsas_state); 642 scsi_hba_fini(&modlinkage); 643 } 644 645 return (status); 646 } 647 648 /* 649 * Notes: 650 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules 651 */ 652 int 653 _fini(void) 654 { 655 int status; 656 /* CONSTCOND */ 657 ASSERT(NO_COMPETING_THREADS); 658 659 NDBG0(("_fini")); 660 661 if ((status = mod_remove(&modlinkage)) == 0) { 662 ddi_soft_state_fini(&mptsas_state); 663 scsi_hba_fini(&modlinkage); 664 mutex_destroy(&mptsas_global_mutex); 665 rw_destroy(&mptsas_global_rwlock); 666 mutex_destroy(&mptsas_log_mutex); 667 } 668 return (status); 669 } 670 671 /* 672 * The loadable-module _info(9E) entry point 673 */ 674 int 675 _info(struct modinfo *modinfop) 676 { 677 /* CONSTCOND */ 678 ASSERT(NO_COMPETING_THREADS); 679 NDBG0(("mptsas _info")); 680 681 return (mod_info(&modlinkage, modinfop)); 682 } 683 684 static int 685 mptsas_target_eval_devhdl(const void *op, void *arg) 686 { 687 uint16_t dh = *(uint16_t *)arg; 688 const mptsas_target_t *tp = op; 689 690 return ((int)tp->m_devhdl - (int)dh); 691 } 692 693 static int 694 mptsas_target_eval_slot(const void *op, void *arg) 695 { 696 mptsas_led_control_t *lcp = arg; 697 const mptsas_target_t *tp = op; 698 699 if (tp->m_enclosure != lcp->Enclosure) 700 return ((int)tp->m_enclosure - (int)lcp->Enclosure); 701 702 return ((int)tp->m_slot_num - (int)lcp->Slot); 703 } 704 705 static int 706 mptsas_target_eval_nowwn(const void *op, void *arg) 707 { 708 uint8_t phy = *(uint8_t *)arg; 709 const mptsas_target_t *tp = op; 710 711 if (tp->m_addr.mta_wwn != 0) 712 return (-1); 713 714 return ((int)tp->m_phynum - (int)phy); 715 } 716 717 static int 718 mptsas_smp_eval_devhdl(const void *op, void *arg) 719 { 720 uint16_t dh = *(uint16_t *)arg; 721 const mptsas_smp_t *sp = op; 722 723 return ((int)sp->m_devhdl - (int)dh); 724 } 725 726 static uint64_t 727 mptsas_target_addr_hash(const void *tp) 728 { 729 const mptsas_target_addr_t *tap = tp; 730 731 return ((tap->mta_wwn & 0xffffffffffffULL) | 732 ((uint64_t)tap->mta_phymask << 48)); 733 } 734 735 static int 736 mptsas_target_addr_cmp(const void *a, const void *b) 737 { 738 const mptsas_target_addr_t *aap = a; 739 const mptsas_target_addr_t *bap = b; 740 741 if (aap->mta_wwn < bap->mta_wwn) 742 return (-1); 743 if (aap->mta_wwn > bap->mta_wwn) 744 return (1); 745 return ((int)bap->mta_phymask - (int)aap->mta_phymask); 746 } 747 748 static void 749 mptsas_target_free(void *op) 750 { 751 kmem_free(op, sizeof (mptsas_target_t)); 752 } 753 754 static void 755 mptsas_smp_free(void *op) 756 { 757 kmem_free(op, sizeof (mptsas_smp_t)); 758 } 759 760 static void 761 mptsas_destroy_hashes(mptsas_t *mpt) 762 { 763 mptsas_target_t *tp; 764 mptsas_smp_t *sp; 765 766 for (tp = refhash_first(mpt->m_targets); tp != NULL; 767 tp = refhash_next(mpt->m_targets, tp)) { 768 refhash_remove(mpt->m_targets, tp); 769 } 770 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 771 sp = refhash_next(mpt->m_smp_targets, sp)) { 772 refhash_remove(mpt->m_smp_targets, sp); 773 } 774 refhash_destroy(mpt->m_targets); 775 refhash_destroy(mpt->m_smp_targets); 776 mpt->m_targets = NULL; 777 mpt->m_smp_targets = NULL; 778 } 779 780 static int 781 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 782 { 783 dev_info_t *pdip; 784 mptsas_t *mpt; 785 scsi_hba_tran_t *hba_tran; 786 char *iport = NULL; 787 char phymask[MPTSAS_MAX_PHYS]; 788 mptsas_phymask_t phy_mask = 0; 789 int dynamic_port = 0; 790 uint32_t page_address; 791 char initiator_wwnstr[MPTSAS_WWN_STRLEN]; 792 int rval = DDI_FAILURE; 793 int i = 0; 794 uint8_t numphys = 0; 795 uint8_t phy_id; 796 uint8_t phy_port = 0; 797 uint16_t attached_devhdl = 0; 798 uint32_t dev_info; 799 uint64_t attached_sas_wwn; 800 uint16_t dev_hdl; 801 uint16_t pdev_hdl; 802 uint16_t bay_num, enclosure; 803 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 804 805 /* CONSTCOND */ 806 ASSERT(NO_COMPETING_THREADS); 807 808 switch (cmd) { 809 case DDI_ATTACH: 810 break; 811 812 case DDI_RESUME: 813 /* 814 * If this a scsi-iport node, nothing to do here. 815 */ 816 return (DDI_SUCCESS); 817 818 default: 819 return (DDI_FAILURE); 820 } 821 822 pdip = ddi_get_parent(dip); 823 824 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) == 825 NULL) { 826 cmn_err(CE_WARN, "Failed attach iport because fail to " 827 "get tran vector for the HBA node"); 828 return (DDI_FAILURE); 829 } 830 831 mpt = TRAN2MPT(hba_tran); 832 ASSERT(mpt != NULL); 833 if (mpt == NULL) 834 return (DDI_FAILURE); 835 836 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == 837 NULL) { 838 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to " 839 "get tran vector for the iport node"); 840 return (DDI_FAILURE); 841 } 842 843 /* 844 * Overwrite parent's tran_hba_private to iport's tran vector 845 */ 846 hba_tran->tran_hba_private = mpt; 847 848 ddi_report_dev(dip); 849 850 /* 851 * Get SAS address for initiator port according dev_handle 852 */ 853 iport = ddi_get_name_addr(dip); 854 if (iport && strncmp(iport, "v0", 2) == 0) { 855 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 856 MPTSAS_VIRTUAL_PORT, 1) != 857 DDI_PROP_SUCCESS) { 858 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 859 MPTSAS_VIRTUAL_PORT); 860 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 861 "prop update failed"); 862 return (DDI_FAILURE); 863 } 864 return (DDI_SUCCESS); 865 } 866 867 mutex_enter(&mpt->m_mutex); 868 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 869 bzero(phymask, sizeof (phymask)); 870 (void) sprintf(phymask, 871 "%x", mpt->m_phy_info[i].phy_mask); 872 if (strcmp(phymask, iport) == 0) { 873 break; 874 } 875 } 876 877 if (i == MPTSAS_MAX_PHYS) { 878 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port" 879 "seems not exist", iport); 880 mutex_exit(&mpt->m_mutex); 881 return (DDI_FAILURE); 882 } 883 884 phy_mask = mpt->m_phy_info[i].phy_mask; 885 886 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION) 887 dynamic_port = 1; 888 else 889 dynamic_port = 0; 890 891 /* 892 * Update PHY info for smhba 893 */ 894 if (mptsas_smhba_phy_init(mpt)) { 895 mutex_exit(&mpt->m_mutex); 896 mptsas_log(mpt, CE_WARN, "mptsas phy update " 897 "failed"); 898 return (DDI_FAILURE); 899 } 900 901 mutex_exit(&mpt->m_mutex); 902 903 numphys = 0; 904 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 905 if ((phy_mask >> i) & 0x01) { 906 numphys++; 907 } 908 } 909 910 bzero(initiator_wwnstr, sizeof (initiator_wwnstr)); 911 (void) sprintf(initiator_wwnstr, "w%016"PRIx64, 912 mpt->un.m_base_wwid); 913 914 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 915 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) != 916 DDI_PROP_SUCCESS) { 917 (void) ddi_prop_remove(DDI_DEV_T_NONE, 918 dip, SCSI_ADDR_PROP_INITIATOR_PORT); 919 mptsas_log(mpt, CE_WARN, "mptsas Initiator port " 920 "prop update failed"); 921 return (DDI_FAILURE); 922 } 923 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 924 MPTSAS_NUM_PHYS, numphys) != 925 DDI_PROP_SUCCESS) { 926 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS); 927 return (DDI_FAILURE); 928 } 929 930 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 931 "phymask", phy_mask) != 932 DDI_PROP_SUCCESS) { 933 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask"); 934 mptsas_log(mpt, CE_WARN, "mptsas phy mask " 935 "prop update failed"); 936 return (DDI_FAILURE); 937 } 938 939 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 940 "dynamic-port", dynamic_port) != 941 DDI_PROP_SUCCESS) { 942 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port"); 943 mptsas_log(mpt, CE_WARN, "mptsas dynamic port " 944 "prop update failed"); 945 return (DDI_FAILURE); 946 } 947 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 948 MPTSAS_VIRTUAL_PORT, 0) != 949 DDI_PROP_SUCCESS) { 950 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 951 MPTSAS_VIRTUAL_PORT); 952 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 953 "prop update failed"); 954 return (DDI_FAILURE); 955 } 956 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask, 957 &attached_devhdl); 958 959 mutex_enter(&mpt->m_mutex); 960 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 961 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl; 962 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 963 &attached_sas_wwn, &dev_info, &phy_port, &phy_id, 964 &pdev_hdl, &bay_num, &enclosure); 965 if (rval != DDI_SUCCESS) { 966 mptsas_log(mpt, CE_WARN, 967 "Failed to get device page0 for handle:%d", 968 attached_devhdl); 969 mutex_exit(&mpt->m_mutex); 970 return (DDI_FAILURE); 971 } 972 973 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 974 bzero(phymask, sizeof (phymask)); 975 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask); 976 if (strcmp(phymask, iport) == 0) { 977 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0], 978 "%x", 979 mpt->m_phy_info[i].phy_mask); 980 } 981 } 982 mutex_exit(&mpt->m_mutex); 983 984 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 985 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 986 attached_sas_wwn); 987 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 988 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 989 DDI_PROP_SUCCESS) { 990 (void) ddi_prop_remove(DDI_DEV_T_NONE, 991 dip, SCSI_ADDR_PROP_ATTACHED_PORT); 992 return (DDI_FAILURE); 993 } 994 995 /* Create kstats for each phy on this iport */ 996 997 mptsas_create_phy_stats(mpt, iport, dip); 998 999 /* 1000 * register sas hba iport with mdi (MPxIO/vhci) 1001 */ 1002 if (mdi_phci_register(MDI_HCI_CLASS_SCSI, 1003 dip, 0) == MDI_SUCCESS) { 1004 mpt->m_mpxio_enable = TRUE; 1005 } 1006 return (DDI_SUCCESS); 1007 } 1008 1009 /* 1010 * Notes: 1011 * Set up all device state and allocate data structures, 1012 * mutexes, condition variables, etc. for device operation. 1013 * Add interrupts needed. 1014 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE. 1015 */ 1016 static int 1017 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 1018 { 1019 mptsas_t *mpt = NULL; 1020 int instance, i, j; 1021 int doneq_thread_num; 1022 char intr_added = 0; 1023 char map_setup = 0; 1024 char config_setup = 0; 1025 char hba_attach_setup = 0; 1026 char smp_attach_setup = 0; 1027 char mutex_init_done = 0; 1028 char event_taskq_create = 0; 1029 char dr_taskq_create = 0; 1030 char doneq_thread_create = 0; 1031 scsi_hba_tran_t *hba_tran; 1032 uint_t mem_bar = MEM_SPACE; 1033 int rval = DDI_FAILURE; 1034 1035 /* CONSTCOND */ 1036 ASSERT(NO_COMPETING_THREADS); 1037 1038 if (scsi_hba_iport_unit_address(dip)) { 1039 return (mptsas_iport_attach(dip, cmd)); 1040 } 1041 1042 switch (cmd) { 1043 case DDI_ATTACH: 1044 break; 1045 1046 case DDI_RESUME: 1047 if ((hba_tran = ddi_get_driver_private(dip)) == NULL) 1048 return (DDI_FAILURE); 1049 1050 mpt = TRAN2MPT(hba_tran); 1051 1052 if (!mpt) { 1053 return (DDI_FAILURE); 1054 } 1055 1056 /* 1057 * Reset hardware and softc to "no outstanding commands" 1058 * Note that a check condition can result on first command 1059 * to a target. 1060 */ 1061 mutex_enter(&mpt->m_mutex); 1062 1063 /* 1064 * raise power. 1065 */ 1066 if (mpt->m_options & MPTSAS_OPT_PM) { 1067 mutex_exit(&mpt->m_mutex); 1068 (void) pm_busy_component(dip, 0); 1069 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0); 1070 if (rval == DDI_SUCCESS) { 1071 mutex_enter(&mpt->m_mutex); 1072 } else { 1073 /* 1074 * The pm_raise_power() call above failed, 1075 * and that can only occur if we were unable 1076 * to reset the hardware. This is probably 1077 * due to unhealty hardware, and because 1078 * important filesystems(such as the root 1079 * filesystem) could be on the attached disks, 1080 * it would not be a good idea to continue, 1081 * as we won't be entirely certain we are 1082 * writing correct data. So we panic() here 1083 * to not only prevent possible data corruption, 1084 * but to give developers or end users a hope 1085 * of identifying and correcting any problems. 1086 */ 1087 fm_panic("mptsas could not reset hardware " 1088 "during resume"); 1089 } 1090 } 1091 1092 mpt->m_suspended = 0; 1093 1094 /* 1095 * Reinitialize ioc 1096 */ 1097 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1098 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 1099 mutex_exit(&mpt->m_mutex); 1100 if (mpt->m_options & MPTSAS_OPT_PM) { 1101 (void) pm_idle_component(dip, 0); 1102 } 1103 fm_panic("mptsas init chip fail during resume"); 1104 } 1105 /* 1106 * mptsas_update_driver_data needs interrupts so enable them 1107 * first. 1108 */ 1109 MPTSAS_ENABLE_INTR(mpt); 1110 mptsas_update_driver_data(mpt); 1111 1112 /* start requests, if possible */ 1113 mptsas_restart_hba(mpt); 1114 1115 mutex_exit(&mpt->m_mutex); 1116 1117 /* 1118 * Restart watch thread 1119 */ 1120 mutex_enter(&mptsas_global_mutex); 1121 if (mptsas_timeout_id == 0) { 1122 mptsas_timeout_id = timeout(mptsas_watch, NULL, 1123 mptsas_tick); 1124 mptsas_timeouts_enabled = 1; 1125 } 1126 mutex_exit(&mptsas_global_mutex); 1127 1128 /* report idle status to pm framework */ 1129 if (mpt->m_options & MPTSAS_OPT_PM) { 1130 (void) pm_idle_component(dip, 0); 1131 } 1132 1133 return (DDI_SUCCESS); 1134 1135 default: 1136 return (DDI_FAILURE); 1137 1138 } 1139 1140 instance = ddi_get_instance(dip); 1141 1142 /* 1143 * Allocate softc information. 1144 */ 1145 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) { 1146 mptsas_log(NULL, CE_WARN, 1147 "mptsas%d: cannot allocate soft state", instance); 1148 goto fail; 1149 } 1150 1151 mpt = ddi_get_soft_state(mptsas_state, instance); 1152 1153 if (mpt == NULL) { 1154 mptsas_log(NULL, CE_WARN, 1155 "mptsas%d: cannot get soft state", instance); 1156 goto fail; 1157 } 1158 1159 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */ 1160 scsi_size_clean(dip); 1161 1162 mpt->m_dip = dip; 1163 mpt->m_instance = instance; 1164 1165 /* Make a per-instance copy of the structures */ 1166 mpt->m_io_dma_attr = mptsas_dma_attrs64; 1167 mpt->m_msg_dma_attr = mptsas_dma_attrs; 1168 mpt->m_reg_acc_attr = mptsas_dev_attr; 1169 mpt->m_dev_acc_attr = mptsas_dev_attr; 1170 1171 /* 1172 * Initialize FMA 1173 */ 1174 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip, 1175 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 1176 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 1177 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 1178 1179 mptsas_fm_init(mpt); 1180 1181 if (mptsas_alloc_handshake_msg(mpt, 1182 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) { 1183 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg."); 1184 goto fail; 1185 } 1186 1187 /* 1188 * Setup configuration space 1189 */ 1190 if (mptsas_config_space_init(mpt) == FALSE) { 1191 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed"); 1192 goto fail; 1193 } 1194 config_setup++; 1195 1196 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg, 1197 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) { 1198 mptsas_log(mpt, CE_WARN, "map setup failed"); 1199 goto fail; 1200 } 1201 map_setup++; 1202 1203 /* 1204 * A taskq is created for dealing with the event handler 1205 */ 1206 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq", 1207 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1208 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed"); 1209 goto fail; 1210 } 1211 event_taskq_create++; 1212 1213 /* 1214 * A taskq is created for dealing with dr events 1215 */ 1216 if ((mpt->m_dr_taskq = ddi_taskq_create(dip, 1217 "mptsas_dr_taskq", 1218 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1219 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery " 1220 "failed"); 1221 goto fail; 1222 } 1223 dr_taskq_create++; 1224 1225 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1226 0, "mptsas_doneq_thread_threshold_prop", 10); 1227 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1228 0, "mptsas_doneq_length_threshold_prop", 8); 1229 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1230 0, "mptsas_doneq_thread_n_prop", 8); 1231 1232 if (mpt->m_doneq_thread_n) { 1233 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL); 1234 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL); 1235 1236 mutex_enter(&mpt->m_doneq_mutex); 1237 mpt->m_doneq_thread_id = 1238 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t) 1239 * mpt->m_doneq_thread_n, KM_SLEEP); 1240 1241 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1242 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL, 1243 CV_DRIVER, NULL); 1244 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL, 1245 MUTEX_DRIVER, NULL); 1246 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1247 mpt->m_doneq_thread_id[j].flag |= 1248 MPTSAS_DONEQ_THREAD_ACTIVE; 1249 mpt->m_doneq_thread_id[j].arg.mpt = mpt; 1250 mpt->m_doneq_thread_id[j].arg.t = j; 1251 mpt->m_doneq_thread_id[j].threadp = 1252 thread_create(NULL, 0, mptsas_doneq_thread, 1253 &mpt->m_doneq_thread_id[j].arg, 1254 0, &p0, TS_RUN, minclsyspri); 1255 mpt->m_doneq_thread_id[j].donetail = 1256 &mpt->m_doneq_thread_id[j].doneq; 1257 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1258 } 1259 mutex_exit(&mpt->m_doneq_mutex); 1260 doneq_thread_create++; 1261 } 1262 1263 /* Initialize mutex used in interrupt handler */ 1264 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, 1265 DDI_INTR_PRI(mpt->m_intr_pri)); 1266 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL); 1267 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER, 1268 DDI_INTR_PRI(mpt->m_intr_pri)); 1269 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1270 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex, 1271 NULL, MUTEX_DRIVER, 1272 DDI_INTR_PRI(mpt->m_intr_pri)); 1273 } 1274 1275 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL); 1276 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL); 1277 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL); 1278 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL); 1279 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL); 1280 mutex_init_done++; 1281 1282 /* 1283 * Disable hardware interrupt since we're not ready to 1284 * handle it yet. 1285 */ 1286 MPTSAS_DISABLE_INTR(mpt); 1287 if (mptsas_register_intrs(mpt) == FALSE) 1288 goto fail; 1289 intr_added++; 1290 1291 mutex_enter(&mpt->m_mutex); 1292 /* 1293 * Initialize power management component 1294 */ 1295 if (mpt->m_options & MPTSAS_OPT_PM) { 1296 if (mptsas_init_pm(mpt)) { 1297 mutex_exit(&mpt->m_mutex); 1298 mptsas_log(mpt, CE_WARN, "mptsas pm initialization " 1299 "failed"); 1300 goto fail; 1301 } 1302 } 1303 1304 /* 1305 * Initialize chip using Message Unit Reset, if allowed 1306 */ 1307 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1308 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) { 1309 mutex_exit(&mpt->m_mutex); 1310 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed"); 1311 goto fail; 1312 } 1313 1314 /* 1315 * Fill in the phy_info structure and get the base WWID 1316 */ 1317 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) { 1318 mptsas_log(mpt, CE_WARN, 1319 "mptsas_get_manufacture_page5 failed!"); 1320 goto fail; 1321 } 1322 1323 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) { 1324 mptsas_log(mpt, CE_WARN, 1325 "mptsas_get_sas_io_unit_page_hndshk failed!"); 1326 goto fail; 1327 } 1328 1329 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) { 1330 mptsas_log(mpt, CE_WARN, 1331 "mptsas_get_manufacture_page0 failed!"); 1332 goto fail; 1333 } 1334 1335 mutex_exit(&mpt->m_mutex); 1336 1337 /* 1338 * Register the iport for multiple port HBA 1339 */ 1340 mptsas_iport_register(mpt); 1341 1342 /* 1343 * initialize SCSI HBA transport structure 1344 */ 1345 if (mptsas_hba_setup(mpt) == FALSE) 1346 goto fail; 1347 hba_attach_setup++; 1348 1349 if (mptsas_smp_setup(mpt) == FALSE) 1350 goto fail; 1351 smp_attach_setup++; 1352 1353 if (mptsas_cache_create(mpt) == FALSE) 1354 goto fail; 1355 1356 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 1357 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY); 1358 if (mpt->m_scsi_reset_delay == 0) { 1359 mptsas_log(mpt, CE_NOTE, 1360 "scsi_reset_delay of 0 is not recommended," 1361 " resetting to SCSI_DEFAULT_RESET_DELAY\n"); 1362 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY; 1363 } 1364 1365 /* 1366 * Initialize the wait and done FIFO queue 1367 */ 1368 mpt->m_donetail = &mpt->m_doneq; 1369 mpt->m_waitqtail = &mpt->m_waitq; 1370 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 1371 mpt->m_tx_draining = 0; 1372 1373 /* 1374 * ioc cmd queue initialize 1375 */ 1376 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq; 1377 mpt->m_dev_handle = 0xFFFF; 1378 1379 MPTSAS_ENABLE_INTR(mpt); 1380 1381 /* 1382 * enable event notification 1383 */ 1384 mutex_enter(&mpt->m_mutex); 1385 if (mptsas_ioc_enable_event_notification(mpt)) { 1386 mutex_exit(&mpt->m_mutex); 1387 goto fail; 1388 } 1389 mutex_exit(&mpt->m_mutex); 1390 1391 /* 1392 * Initialize PHY info for smhba 1393 */ 1394 if (mptsas_smhba_setup(mpt)) { 1395 mptsas_log(mpt, CE_WARN, "mptsas phy initialization " 1396 "failed"); 1397 goto fail; 1398 } 1399 1400 /* Check all dma handles allocated in attach */ 1401 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) 1402 != DDI_SUCCESS) || 1403 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) 1404 != DDI_SUCCESS) || 1405 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) 1406 != DDI_SUCCESS) || 1407 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) 1408 != DDI_SUCCESS) || 1409 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) 1410 != DDI_SUCCESS)) { 1411 goto fail; 1412 } 1413 1414 /* Check all acc handles allocated in attach */ 1415 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 1416 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) 1417 != DDI_SUCCESS) || 1418 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) 1419 != DDI_SUCCESS) || 1420 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) 1421 != DDI_SUCCESS) || 1422 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) 1423 != DDI_SUCCESS) || 1424 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) 1425 != DDI_SUCCESS) || 1426 (mptsas_check_acc_handle(mpt->m_config_handle) 1427 != DDI_SUCCESS)) { 1428 goto fail; 1429 } 1430 1431 /* 1432 * After this point, we are not going to fail the attach. 1433 */ 1434 /* 1435 * used for mptsas_watch 1436 */ 1437 mptsas_list_add(mpt); 1438 1439 mutex_enter(&mptsas_global_mutex); 1440 if (mptsas_timeouts_enabled == 0) { 1441 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY, 1442 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK); 1443 1444 mptsas_tick = mptsas_scsi_watchdog_tick * 1445 drv_usectohz((clock_t)1000000); 1446 1447 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 1448 mptsas_timeouts_enabled = 1; 1449 } 1450 mutex_exit(&mptsas_global_mutex); 1451 1452 /* Print message of HBA present */ 1453 ddi_report_dev(dip); 1454 1455 /* report idle status to pm framework */ 1456 if (mpt->m_options & MPTSAS_OPT_PM) { 1457 (void) pm_idle_component(dip, 0); 1458 } 1459 1460 return (DDI_SUCCESS); 1461 1462 fail: 1463 mptsas_log(mpt, CE_WARN, "attach failed"); 1464 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 1465 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 1466 if (mpt) { 1467 mutex_enter(&mptsas_global_mutex); 1468 1469 if (mptsas_timeout_id && (mptsas_head == NULL)) { 1470 timeout_id_t tid = mptsas_timeout_id; 1471 mptsas_timeouts_enabled = 0; 1472 mptsas_timeout_id = 0; 1473 mutex_exit(&mptsas_global_mutex); 1474 (void) untimeout(tid); 1475 mutex_enter(&mptsas_global_mutex); 1476 } 1477 mutex_exit(&mptsas_global_mutex); 1478 /* deallocate in reverse order */ 1479 mptsas_cache_destroy(mpt); 1480 1481 if (smp_attach_setup) { 1482 mptsas_smp_teardown(mpt); 1483 } 1484 if (hba_attach_setup) { 1485 mptsas_hba_teardown(mpt); 1486 } 1487 1488 if (mpt->m_targets) 1489 refhash_destroy(mpt->m_targets); 1490 if (mpt->m_smp_targets) 1491 refhash_destroy(mpt->m_smp_targets); 1492 1493 if (mpt->m_active) { 1494 mptsas_free_active_slots(mpt); 1495 } 1496 if (intr_added) { 1497 mptsas_unregister_intrs(mpt); 1498 } 1499 1500 if (doneq_thread_create) { 1501 mutex_enter(&mpt->m_doneq_mutex); 1502 doneq_thread_num = mpt->m_doneq_thread_n; 1503 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1504 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1505 mpt->m_doneq_thread_id[j].flag &= 1506 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1507 cv_signal(&mpt->m_doneq_thread_id[j].cv); 1508 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1509 } 1510 while (mpt->m_doneq_thread_n) { 1511 cv_wait(&mpt->m_doneq_thread_cv, 1512 &mpt->m_doneq_mutex); 1513 } 1514 for (j = 0; j < doneq_thread_num; j++) { 1515 cv_destroy(&mpt->m_doneq_thread_id[j].cv); 1516 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex); 1517 } 1518 kmem_free(mpt->m_doneq_thread_id, 1519 sizeof (mptsas_doneq_thread_list_t) 1520 * doneq_thread_num); 1521 mutex_exit(&mpt->m_doneq_mutex); 1522 cv_destroy(&mpt->m_doneq_thread_cv); 1523 mutex_destroy(&mpt->m_doneq_mutex); 1524 } 1525 if (event_taskq_create) { 1526 ddi_taskq_destroy(mpt->m_event_taskq); 1527 } 1528 if (dr_taskq_create) { 1529 ddi_taskq_destroy(mpt->m_dr_taskq); 1530 } 1531 if (mutex_init_done) { 1532 mutex_destroy(&mpt->m_tx_waitq_mutex); 1533 mutex_destroy(&mpt->m_passthru_mutex); 1534 mutex_destroy(&mpt->m_mutex); 1535 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1536 mutex_destroy( 1537 &mpt->m_phy_info[i].smhba_info.phy_mutex); 1538 } 1539 cv_destroy(&mpt->m_cv); 1540 cv_destroy(&mpt->m_passthru_cv); 1541 cv_destroy(&mpt->m_fw_cv); 1542 cv_destroy(&mpt->m_config_cv); 1543 cv_destroy(&mpt->m_fw_diag_cv); 1544 } 1545 1546 if (map_setup) { 1547 mptsas_cfg_fini(mpt); 1548 } 1549 if (config_setup) { 1550 mptsas_config_space_fini(mpt); 1551 } 1552 mptsas_free_handshake_msg(mpt); 1553 mptsas_hba_fini(mpt); 1554 1555 mptsas_fm_fini(mpt); 1556 ddi_soft_state_free(mptsas_state, instance); 1557 ddi_prop_remove_all(dip); 1558 } 1559 return (DDI_FAILURE); 1560 } 1561 1562 static int 1563 mptsas_suspend(dev_info_t *devi) 1564 { 1565 mptsas_t *mpt, *g; 1566 scsi_hba_tran_t *tran; 1567 1568 if (scsi_hba_iport_unit_address(devi)) { 1569 return (DDI_SUCCESS); 1570 } 1571 1572 if ((tran = ddi_get_driver_private(devi)) == NULL) 1573 return (DDI_SUCCESS); 1574 1575 mpt = TRAN2MPT(tran); 1576 if (!mpt) { 1577 return (DDI_SUCCESS); 1578 } 1579 1580 mutex_enter(&mpt->m_mutex); 1581 1582 if (mpt->m_suspended++) { 1583 mutex_exit(&mpt->m_mutex); 1584 return (DDI_SUCCESS); 1585 } 1586 1587 /* 1588 * Cancel timeout threads for this mpt 1589 */ 1590 if (mpt->m_quiesce_timeid) { 1591 timeout_id_t tid = mpt->m_quiesce_timeid; 1592 mpt->m_quiesce_timeid = 0; 1593 mutex_exit(&mpt->m_mutex); 1594 (void) untimeout(tid); 1595 mutex_enter(&mpt->m_mutex); 1596 } 1597 1598 if (mpt->m_restart_cmd_timeid) { 1599 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1600 mpt->m_restart_cmd_timeid = 0; 1601 mutex_exit(&mpt->m_mutex); 1602 (void) untimeout(tid); 1603 mutex_enter(&mpt->m_mutex); 1604 } 1605 1606 mutex_exit(&mpt->m_mutex); 1607 1608 (void) pm_idle_component(mpt->m_dip, 0); 1609 1610 /* 1611 * Cancel watch threads if all mpts suspended 1612 */ 1613 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1614 for (g = mptsas_head; g != NULL; g = g->m_next) { 1615 if (!g->m_suspended) 1616 break; 1617 } 1618 rw_exit(&mptsas_global_rwlock); 1619 1620 mutex_enter(&mptsas_global_mutex); 1621 if (g == NULL) { 1622 timeout_id_t tid; 1623 1624 mptsas_timeouts_enabled = 0; 1625 if (mptsas_timeout_id) { 1626 tid = mptsas_timeout_id; 1627 mptsas_timeout_id = 0; 1628 mutex_exit(&mptsas_global_mutex); 1629 (void) untimeout(tid); 1630 mutex_enter(&mptsas_global_mutex); 1631 } 1632 if (mptsas_reset_watch) { 1633 tid = mptsas_reset_watch; 1634 mptsas_reset_watch = 0; 1635 mutex_exit(&mptsas_global_mutex); 1636 (void) untimeout(tid); 1637 mutex_enter(&mptsas_global_mutex); 1638 } 1639 } 1640 mutex_exit(&mptsas_global_mutex); 1641 1642 mutex_enter(&mpt->m_mutex); 1643 1644 /* 1645 * If this mpt is not in full power(PM_LEVEL_D0), just return. 1646 */ 1647 if ((mpt->m_options & MPTSAS_OPT_PM) && 1648 (mpt->m_power_level != PM_LEVEL_D0)) { 1649 mutex_exit(&mpt->m_mutex); 1650 return (DDI_SUCCESS); 1651 } 1652 1653 /* Disable HBA interrupts in hardware */ 1654 MPTSAS_DISABLE_INTR(mpt); 1655 /* 1656 * Send RAID action system shutdown to sync IR 1657 */ 1658 mptsas_raid_action_system_shutdown(mpt); 1659 1660 mutex_exit(&mpt->m_mutex); 1661 1662 /* drain the taskq */ 1663 ddi_taskq_wait(mpt->m_event_taskq); 1664 ddi_taskq_wait(mpt->m_dr_taskq); 1665 1666 return (DDI_SUCCESS); 1667 } 1668 1669 #ifdef __sparc 1670 /*ARGSUSED*/ 1671 static int 1672 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd) 1673 { 1674 mptsas_t *mpt; 1675 scsi_hba_tran_t *tran; 1676 1677 /* 1678 * If this call is for iport, just return. 1679 */ 1680 if (scsi_hba_iport_unit_address(devi)) 1681 return (DDI_SUCCESS); 1682 1683 if ((tran = ddi_get_driver_private(devi)) == NULL) 1684 return (DDI_SUCCESS); 1685 1686 if ((mpt = TRAN2MPT(tran)) == NULL) 1687 return (DDI_SUCCESS); 1688 1689 /* 1690 * Send RAID action system shutdown to sync IR. Disable HBA 1691 * interrupts in hardware first. 1692 */ 1693 MPTSAS_DISABLE_INTR(mpt); 1694 mptsas_raid_action_system_shutdown(mpt); 1695 1696 return (DDI_SUCCESS); 1697 } 1698 #else /* __sparc */ 1699 /* 1700 * quiesce(9E) entry point. 1701 * 1702 * This function is called when the system is single-threaded at high 1703 * PIL with preemption disabled. Therefore, this function must not be 1704 * blocked. 1705 * 1706 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 1707 * DDI_FAILURE indicates an error condition and should almost never happen. 1708 */ 1709 static int 1710 mptsas_quiesce(dev_info_t *devi) 1711 { 1712 mptsas_t *mpt; 1713 scsi_hba_tran_t *tran; 1714 1715 /* 1716 * If this call is for iport, just return. 1717 */ 1718 if (scsi_hba_iport_unit_address(devi)) 1719 return (DDI_SUCCESS); 1720 1721 if ((tran = ddi_get_driver_private(devi)) == NULL) 1722 return (DDI_SUCCESS); 1723 1724 if ((mpt = TRAN2MPT(tran)) == NULL) 1725 return (DDI_SUCCESS); 1726 1727 /* Disable HBA interrupts in hardware */ 1728 MPTSAS_DISABLE_INTR(mpt); 1729 /* Send RAID action system shutdonw to sync IR */ 1730 mptsas_raid_action_system_shutdown(mpt); 1731 1732 return (DDI_SUCCESS); 1733 } 1734 #endif /* __sparc */ 1735 1736 /* 1737 * detach(9E). Remove all device allocations and system resources; 1738 * disable device interrupts. 1739 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem. 1740 */ 1741 static int 1742 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 1743 { 1744 /* CONSTCOND */ 1745 ASSERT(NO_COMPETING_THREADS); 1746 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd)); 1747 1748 switch (cmd) { 1749 case DDI_DETACH: 1750 return (mptsas_do_detach(devi)); 1751 1752 case DDI_SUSPEND: 1753 return (mptsas_suspend(devi)); 1754 1755 default: 1756 return (DDI_FAILURE); 1757 } 1758 /* NOTREACHED */ 1759 } 1760 1761 static int 1762 mptsas_do_detach(dev_info_t *dip) 1763 { 1764 mptsas_t *mpt; 1765 scsi_hba_tran_t *tran; 1766 int circ = 0; 1767 int circ1 = 0; 1768 mdi_pathinfo_t *pip = NULL; 1769 int i; 1770 int doneq_thread_num = 0; 1771 1772 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip)); 1773 1774 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL) 1775 return (DDI_FAILURE); 1776 1777 mpt = TRAN2MPT(tran); 1778 if (!mpt) { 1779 return (DDI_FAILURE); 1780 } 1781 /* 1782 * Still have pathinfo child, should not detach mpt driver 1783 */ 1784 if (scsi_hba_iport_unit_address(dip)) { 1785 if (mpt->m_mpxio_enable) { 1786 /* 1787 * MPxIO enabled for the iport 1788 */ 1789 ndi_devi_enter(scsi_vhci_dip, &circ1); 1790 ndi_devi_enter(dip, &circ); 1791 while (pip = mdi_get_next_client_path(dip, NULL)) { 1792 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) { 1793 continue; 1794 } 1795 ndi_devi_exit(dip, circ); 1796 ndi_devi_exit(scsi_vhci_dip, circ1); 1797 NDBG12(("detach failed because of " 1798 "outstanding path info")); 1799 return (DDI_FAILURE); 1800 } 1801 ndi_devi_exit(dip, circ); 1802 ndi_devi_exit(scsi_vhci_dip, circ1); 1803 (void) mdi_phci_unregister(dip, 0); 1804 } 1805 1806 ddi_prop_remove_all(dip); 1807 1808 return (DDI_SUCCESS); 1809 } 1810 1811 /* Make sure power level is D0 before accessing registers */ 1812 if (mpt->m_options & MPTSAS_OPT_PM) { 1813 (void) pm_busy_component(dip, 0); 1814 if (mpt->m_power_level != PM_LEVEL_D0) { 1815 if (pm_raise_power(dip, 0, PM_LEVEL_D0) != 1816 DDI_SUCCESS) { 1817 mptsas_log(mpt, CE_WARN, 1818 "mptsas%d: Raise power request failed.", 1819 mpt->m_instance); 1820 (void) pm_idle_component(dip, 0); 1821 return (DDI_FAILURE); 1822 } 1823 } 1824 } 1825 1826 /* 1827 * Send RAID action system shutdown to sync IR. After action, send a 1828 * Message Unit Reset. Since after that DMA resource will be freed, 1829 * set ioc to READY state will avoid HBA initiated DMA operation. 1830 */ 1831 mutex_enter(&mpt->m_mutex); 1832 MPTSAS_DISABLE_INTR(mpt); 1833 mptsas_raid_action_system_shutdown(mpt); 1834 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1835 (void) mptsas_ioc_reset(mpt, FALSE); 1836 mutex_exit(&mpt->m_mutex); 1837 mptsas_rem_intrs(mpt); 1838 ddi_taskq_destroy(mpt->m_event_taskq); 1839 ddi_taskq_destroy(mpt->m_dr_taskq); 1840 1841 if (mpt->m_doneq_thread_n) { 1842 mutex_enter(&mpt->m_doneq_mutex); 1843 doneq_thread_num = mpt->m_doneq_thread_n; 1844 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 1845 mutex_enter(&mpt->m_doneq_thread_id[i].mutex); 1846 mpt->m_doneq_thread_id[i].flag &= 1847 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1848 cv_signal(&mpt->m_doneq_thread_id[i].cv); 1849 mutex_exit(&mpt->m_doneq_thread_id[i].mutex); 1850 } 1851 while (mpt->m_doneq_thread_n) { 1852 cv_wait(&mpt->m_doneq_thread_cv, 1853 &mpt->m_doneq_mutex); 1854 } 1855 for (i = 0; i < doneq_thread_num; i++) { 1856 cv_destroy(&mpt->m_doneq_thread_id[i].cv); 1857 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex); 1858 } 1859 kmem_free(mpt->m_doneq_thread_id, 1860 sizeof (mptsas_doneq_thread_list_t) 1861 * doneq_thread_num); 1862 mutex_exit(&mpt->m_doneq_mutex); 1863 cv_destroy(&mpt->m_doneq_thread_cv); 1864 mutex_destroy(&mpt->m_doneq_mutex); 1865 } 1866 1867 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf); 1868 1869 mptsas_list_del(mpt); 1870 1871 /* 1872 * Cancel timeout threads for this mpt 1873 */ 1874 mutex_enter(&mpt->m_mutex); 1875 if (mpt->m_quiesce_timeid) { 1876 timeout_id_t tid = mpt->m_quiesce_timeid; 1877 mpt->m_quiesce_timeid = 0; 1878 mutex_exit(&mpt->m_mutex); 1879 (void) untimeout(tid); 1880 mutex_enter(&mpt->m_mutex); 1881 } 1882 1883 if (mpt->m_restart_cmd_timeid) { 1884 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1885 mpt->m_restart_cmd_timeid = 0; 1886 mutex_exit(&mpt->m_mutex); 1887 (void) untimeout(tid); 1888 mutex_enter(&mpt->m_mutex); 1889 } 1890 1891 mutex_exit(&mpt->m_mutex); 1892 1893 /* 1894 * last mpt? ... if active, CANCEL watch threads. 1895 */ 1896 mutex_enter(&mptsas_global_mutex); 1897 if (mptsas_head == NULL) { 1898 timeout_id_t tid; 1899 /* 1900 * Clear mptsas_timeouts_enable so that the watch thread 1901 * gets restarted on DDI_ATTACH 1902 */ 1903 mptsas_timeouts_enabled = 0; 1904 if (mptsas_timeout_id) { 1905 tid = mptsas_timeout_id; 1906 mptsas_timeout_id = 0; 1907 mutex_exit(&mptsas_global_mutex); 1908 (void) untimeout(tid); 1909 mutex_enter(&mptsas_global_mutex); 1910 } 1911 if (mptsas_reset_watch) { 1912 tid = mptsas_reset_watch; 1913 mptsas_reset_watch = 0; 1914 mutex_exit(&mptsas_global_mutex); 1915 (void) untimeout(tid); 1916 mutex_enter(&mptsas_global_mutex); 1917 } 1918 } 1919 mutex_exit(&mptsas_global_mutex); 1920 1921 /* 1922 * Delete Phy stats 1923 */ 1924 mptsas_destroy_phy_stats(mpt); 1925 1926 mptsas_destroy_hashes(mpt); 1927 1928 /* 1929 * Delete nt_active. 1930 */ 1931 mutex_enter(&mpt->m_mutex); 1932 mptsas_free_active_slots(mpt); 1933 mutex_exit(&mpt->m_mutex); 1934 1935 /* deallocate everything that was allocated in mptsas_attach */ 1936 mptsas_cache_destroy(mpt); 1937 1938 mptsas_hba_fini(mpt); 1939 mptsas_cfg_fini(mpt); 1940 1941 /* Lower the power informing PM Framework */ 1942 if (mpt->m_options & MPTSAS_OPT_PM) { 1943 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS) 1944 mptsas_log(mpt, CE_WARN, 1945 "!mptsas%d: Lower power request failed " 1946 "during detach, ignoring.", 1947 mpt->m_instance); 1948 } 1949 1950 mutex_destroy(&mpt->m_tx_waitq_mutex); 1951 mutex_destroy(&mpt->m_passthru_mutex); 1952 mutex_destroy(&mpt->m_mutex); 1953 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1954 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex); 1955 } 1956 cv_destroy(&mpt->m_cv); 1957 cv_destroy(&mpt->m_passthru_cv); 1958 cv_destroy(&mpt->m_fw_cv); 1959 cv_destroy(&mpt->m_config_cv); 1960 cv_destroy(&mpt->m_fw_diag_cv); 1961 1962 1963 mptsas_smp_teardown(mpt); 1964 mptsas_hba_teardown(mpt); 1965 1966 mptsas_config_space_fini(mpt); 1967 1968 mptsas_free_handshake_msg(mpt); 1969 1970 mptsas_fm_fini(mpt); 1971 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip)); 1972 ddi_prop_remove_all(dip); 1973 1974 return (DDI_SUCCESS); 1975 } 1976 1977 static void 1978 mptsas_list_add(mptsas_t *mpt) 1979 { 1980 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1981 1982 if (mptsas_head == NULL) { 1983 mptsas_head = mpt; 1984 } else { 1985 mptsas_tail->m_next = mpt; 1986 } 1987 mptsas_tail = mpt; 1988 rw_exit(&mptsas_global_rwlock); 1989 } 1990 1991 static void 1992 mptsas_list_del(mptsas_t *mpt) 1993 { 1994 mptsas_t *m; 1995 /* 1996 * Remove device instance from the global linked list 1997 */ 1998 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1999 if (mptsas_head == mpt) { 2000 m = mptsas_head = mpt->m_next; 2001 } else { 2002 for (m = mptsas_head; m != NULL; m = m->m_next) { 2003 if (m->m_next == mpt) { 2004 m->m_next = mpt->m_next; 2005 break; 2006 } 2007 } 2008 if (m == NULL) { 2009 mptsas_log(mpt, CE_PANIC, "Not in softc list!"); 2010 } 2011 } 2012 2013 if (mptsas_tail == mpt) { 2014 mptsas_tail = m; 2015 } 2016 rw_exit(&mptsas_global_rwlock); 2017 } 2018 2019 static int 2020 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size) 2021 { 2022 ddi_dma_attr_t task_dma_attrs; 2023 2024 task_dma_attrs = mpt->m_msg_dma_attr; 2025 task_dma_attrs.dma_attr_sgllen = 1; 2026 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size); 2027 2028 /* allocate Task Management ddi_dma resources */ 2029 if (mptsas_dma_addr_create(mpt, task_dma_attrs, 2030 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp, 2031 alloc_size, NULL) == FALSE) { 2032 return (DDI_FAILURE); 2033 } 2034 mpt->m_hshk_dma_size = alloc_size; 2035 2036 return (DDI_SUCCESS); 2037 } 2038 2039 static void 2040 mptsas_free_handshake_msg(mptsas_t *mpt) 2041 { 2042 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl); 2043 mpt->m_hshk_dma_size = 0; 2044 } 2045 2046 static int 2047 mptsas_hba_setup(mptsas_t *mpt) 2048 { 2049 scsi_hba_tran_t *hba_tran; 2050 int tran_flags; 2051 2052 /* Allocate a transport structure */ 2053 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip, 2054 SCSI_HBA_CANSLEEP); 2055 ASSERT(mpt->m_tran != NULL); 2056 2057 hba_tran->tran_hba_private = mpt; 2058 hba_tran->tran_tgt_private = NULL; 2059 2060 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init; 2061 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free; 2062 2063 hba_tran->tran_start = mptsas_scsi_start; 2064 hba_tran->tran_reset = mptsas_scsi_reset; 2065 hba_tran->tran_abort = mptsas_scsi_abort; 2066 hba_tran->tran_getcap = mptsas_scsi_getcap; 2067 hba_tran->tran_setcap = mptsas_scsi_setcap; 2068 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt; 2069 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt; 2070 2071 hba_tran->tran_dmafree = mptsas_scsi_dmafree; 2072 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt; 2073 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify; 2074 2075 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr; 2076 hba_tran->tran_get_name = mptsas_get_name; 2077 2078 hba_tran->tran_quiesce = mptsas_scsi_quiesce; 2079 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce; 2080 hba_tran->tran_bus_reset = NULL; 2081 2082 hba_tran->tran_add_eventcall = NULL; 2083 hba_tran->tran_get_eventcookie = NULL; 2084 hba_tran->tran_post_event = NULL; 2085 hba_tran->tran_remove_eventcall = NULL; 2086 2087 hba_tran->tran_bus_config = mptsas_bus_config; 2088 2089 hba_tran->tran_interconnect_type = INTERCONNECT_SAS; 2090 2091 /* 2092 * All children of the HBA are iports. We need tran was cloned. 2093 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be 2094 * inherited to iport's tran vector. 2095 */ 2096 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE); 2097 2098 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr, 2099 hba_tran, tran_flags) != DDI_SUCCESS) { 2100 mptsas_log(mpt, CE_WARN, "hba attach setup failed"); 2101 scsi_hba_tran_free(hba_tran); 2102 mpt->m_tran = NULL; 2103 return (FALSE); 2104 } 2105 return (TRUE); 2106 } 2107 2108 static void 2109 mptsas_hba_teardown(mptsas_t *mpt) 2110 { 2111 (void) scsi_hba_detach(mpt->m_dip); 2112 if (mpt->m_tran != NULL) { 2113 scsi_hba_tran_free(mpt->m_tran); 2114 mpt->m_tran = NULL; 2115 } 2116 } 2117 2118 static void 2119 mptsas_iport_register(mptsas_t *mpt) 2120 { 2121 int i, j; 2122 mptsas_phymask_t mask = 0x0; 2123 /* 2124 * initial value of mask is 0 2125 */ 2126 mutex_enter(&mpt->m_mutex); 2127 for (i = 0; i < mpt->m_num_phys; i++) { 2128 mptsas_phymask_t phy_mask = 0x0; 2129 char phy_mask_name[MPTSAS_MAX_PHYS]; 2130 uint8_t current_port; 2131 2132 if (mpt->m_phy_info[i].attached_devhdl == 0) 2133 continue; 2134 2135 bzero(phy_mask_name, sizeof (phy_mask_name)); 2136 2137 current_port = mpt->m_phy_info[i].port_num; 2138 2139 if ((mask & (1 << i)) != 0) 2140 continue; 2141 2142 for (j = 0; j < mpt->m_num_phys; j++) { 2143 if (mpt->m_phy_info[j].attached_devhdl && 2144 (mpt->m_phy_info[j].port_num == current_port)) { 2145 phy_mask |= (1 << j); 2146 } 2147 } 2148 mask = mask | phy_mask; 2149 2150 for (j = 0; j < mpt->m_num_phys; j++) { 2151 if ((phy_mask >> j) & 0x01) { 2152 mpt->m_phy_info[j].phy_mask = phy_mask; 2153 } 2154 } 2155 2156 (void) sprintf(phy_mask_name, "%x", phy_mask); 2157 2158 mutex_exit(&mpt->m_mutex); 2159 /* 2160 * register a iport 2161 */ 2162 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 2163 mutex_enter(&mpt->m_mutex); 2164 } 2165 mutex_exit(&mpt->m_mutex); 2166 /* 2167 * register a virtual port for RAID volume always 2168 */ 2169 (void) scsi_hba_iport_register(mpt->m_dip, "v0"); 2170 2171 } 2172 2173 static int 2174 mptsas_smp_setup(mptsas_t *mpt) 2175 { 2176 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip); 2177 ASSERT(mpt->m_smptran != NULL); 2178 mpt->m_smptran->smp_tran_hba_private = mpt; 2179 mpt->m_smptran->smp_tran_start = mptsas_smp_start; 2180 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) { 2181 mptsas_log(mpt, CE_WARN, "smp attach setup failed"); 2182 smp_hba_tran_free(mpt->m_smptran); 2183 mpt->m_smptran = NULL; 2184 return (FALSE); 2185 } 2186 /* 2187 * Initialize smp hash table 2188 */ 2189 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT, 2190 mptsas_target_addr_hash, mptsas_target_addr_cmp, 2191 mptsas_smp_free, sizeof (mptsas_smp_t), 2192 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr), 2193 KM_SLEEP); 2194 mpt->m_smp_devhdl = 0xFFFF; 2195 2196 return (TRUE); 2197 } 2198 2199 static void 2200 mptsas_smp_teardown(mptsas_t *mpt) 2201 { 2202 (void) smp_hba_detach(mpt->m_dip); 2203 if (mpt->m_smptran != NULL) { 2204 smp_hba_tran_free(mpt->m_smptran); 2205 mpt->m_smptran = NULL; 2206 } 2207 mpt->m_smp_devhdl = 0; 2208 } 2209 2210 static int 2211 mptsas_cache_create(mptsas_t *mpt) 2212 { 2213 int instance = mpt->m_instance; 2214 char buf[64]; 2215 2216 /* 2217 * create kmem cache for packets 2218 */ 2219 (void) sprintf(buf, "mptsas%d_cache", instance); 2220 mpt->m_kmem_cache = kmem_cache_create(buf, 2221 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8, 2222 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor, 2223 NULL, (void *)mpt, NULL, 0); 2224 2225 if (mpt->m_kmem_cache == NULL) { 2226 mptsas_log(mpt, CE_WARN, "creating kmem cache failed"); 2227 return (FALSE); 2228 } 2229 2230 /* 2231 * create kmem cache for extra SGL frames if SGL cannot 2232 * be accomodated into main request frame. 2233 */ 2234 (void) sprintf(buf, "mptsas%d_cache_frames", instance); 2235 mpt->m_cache_frames = kmem_cache_create(buf, 2236 sizeof (mptsas_cache_frames_t), 8, 2237 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor, 2238 NULL, (void *)mpt, NULL, 0); 2239 2240 if (mpt->m_cache_frames == NULL) { 2241 mptsas_log(mpt, CE_WARN, "creating cache for frames failed"); 2242 return (FALSE); 2243 } 2244 2245 return (TRUE); 2246 } 2247 2248 static void 2249 mptsas_cache_destroy(mptsas_t *mpt) 2250 { 2251 /* deallocate in reverse order */ 2252 if (mpt->m_cache_frames) { 2253 kmem_cache_destroy(mpt->m_cache_frames); 2254 mpt->m_cache_frames = NULL; 2255 } 2256 if (mpt->m_kmem_cache) { 2257 kmem_cache_destroy(mpt->m_kmem_cache); 2258 mpt->m_kmem_cache = NULL; 2259 } 2260 } 2261 2262 static int 2263 mptsas_power(dev_info_t *dip, int component, int level) 2264 { 2265 #ifndef __lock_lint 2266 _NOTE(ARGUNUSED(component)) 2267 #endif 2268 mptsas_t *mpt; 2269 int rval = DDI_SUCCESS; 2270 int polls = 0; 2271 uint32_t ioc_status; 2272 2273 if (scsi_hba_iport_unit_address(dip) != 0) 2274 return (DDI_SUCCESS); 2275 2276 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip)); 2277 if (mpt == NULL) { 2278 return (DDI_FAILURE); 2279 } 2280 2281 mutex_enter(&mpt->m_mutex); 2282 2283 /* 2284 * If the device is busy, don't lower its power level 2285 */ 2286 if (mpt->m_busy && (mpt->m_power_level > level)) { 2287 mutex_exit(&mpt->m_mutex); 2288 return (DDI_FAILURE); 2289 } 2290 switch (level) { 2291 case PM_LEVEL_D0: 2292 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance)); 2293 MPTSAS_POWER_ON(mpt); 2294 /* 2295 * Wait up to 30 seconds for IOC to come out of reset. 2296 */ 2297 while (((ioc_status = ddi_get32(mpt->m_datap, 2298 &mpt->m_reg->Doorbell)) & 2299 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 2300 if (polls++ > 3000) { 2301 break; 2302 } 2303 delay(drv_usectohz(10000)); 2304 } 2305 /* 2306 * If IOC is not in operational state, try to hard reset it. 2307 */ 2308 if ((ioc_status & MPI2_IOC_STATE_MASK) != 2309 MPI2_IOC_STATE_OPERATIONAL) { 2310 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 2311 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 2312 mptsas_log(mpt, CE_WARN, 2313 "mptsas_power: hard reset failed"); 2314 mutex_exit(&mpt->m_mutex); 2315 return (DDI_FAILURE); 2316 } 2317 } 2318 mpt->m_power_level = PM_LEVEL_D0; 2319 break; 2320 case PM_LEVEL_D3: 2321 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance)); 2322 MPTSAS_POWER_OFF(mpt); 2323 break; 2324 default: 2325 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.", 2326 mpt->m_instance, level); 2327 rval = DDI_FAILURE; 2328 break; 2329 } 2330 mutex_exit(&mpt->m_mutex); 2331 return (rval); 2332 } 2333 2334 /* 2335 * Initialize configuration space and figure out which 2336 * chip and revison of the chip the mpt driver is using. 2337 */ 2338 static int 2339 mptsas_config_space_init(mptsas_t *mpt) 2340 { 2341 NDBG0(("mptsas_config_space_init")); 2342 2343 if (mpt->m_config_handle != NULL) 2344 return (TRUE); 2345 2346 if (pci_config_setup(mpt->m_dip, 2347 &mpt->m_config_handle) != DDI_SUCCESS) { 2348 mptsas_log(mpt, CE_WARN, "cannot map configuration space."); 2349 return (FALSE); 2350 } 2351 2352 /* 2353 * This is a workaround for a XMITS ASIC bug which does not 2354 * drive the CBE upper bits. 2355 */ 2356 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) & 2357 PCI_STAT_PERROR) { 2358 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT, 2359 PCI_STAT_PERROR); 2360 } 2361 2362 mptsas_setup_cmd_reg(mpt); 2363 2364 /* 2365 * Get the chip device id: 2366 */ 2367 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID); 2368 2369 /* 2370 * Save the revision. 2371 */ 2372 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID); 2373 2374 /* 2375 * Save the SubSystem Vendor and Device IDs 2376 */ 2377 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID); 2378 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID); 2379 2380 /* 2381 * Set the latency timer to 0x40 as specified by the upa -> pci 2382 * bridge chip design team. This may be done by the sparc pci 2383 * bus nexus driver, but the driver should make sure the latency 2384 * timer is correct for performance reasons. 2385 */ 2386 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER, 2387 MPTSAS_LATENCY_TIMER); 2388 2389 (void) mptsas_get_pci_cap(mpt); 2390 return (TRUE); 2391 } 2392 2393 static void 2394 mptsas_config_space_fini(mptsas_t *mpt) 2395 { 2396 if (mpt->m_config_handle != NULL) { 2397 mptsas_disable_bus_master(mpt); 2398 pci_config_teardown(&mpt->m_config_handle); 2399 mpt->m_config_handle = NULL; 2400 } 2401 } 2402 2403 static void 2404 mptsas_setup_cmd_reg(mptsas_t *mpt) 2405 { 2406 ushort_t cmdreg; 2407 2408 /* 2409 * Set the command register to the needed values. 2410 */ 2411 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2412 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE | 2413 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE); 2414 cmdreg &= ~PCI_COMM_IO; 2415 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2416 } 2417 2418 static void 2419 mptsas_disable_bus_master(mptsas_t *mpt) 2420 { 2421 ushort_t cmdreg; 2422 2423 /* 2424 * Clear the master enable bit in the PCI command register. 2425 * This prevents any bus mastering activity like DMA. 2426 */ 2427 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2428 cmdreg &= ~PCI_COMM_ME; 2429 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2430 } 2431 2432 int 2433 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep) 2434 { 2435 ddi_dma_attr_t attrs; 2436 2437 attrs = mpt->m_io_dma_attr; 2438 attrs.dma_attr_sgllen = 1; 2439 2440 ASSERT(dma_statep != NULL); 2441 2442 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle, 2443 &dma_statep->accessp, &dma_statep->memp, dma_statep->size, 2444 &dma_statep->cookie) == FALSE) { 2445 return (DDI_FAILURE); 2446 } 2447 2448 return (DDI_SUCCESS); 2449 } 2450 2451 void 2452 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep) 2453 { 2454 ASSERT(dma_statep != NULL); 2455 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp); 2456 dma_statep->size = 0; 2457 } 2458 2459 int 2460 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()) 2461 { 2462 ddi_dma_attr_t attrs; 2463 ddi_dma_handle_t dma_handle; 2464 caddr_t memp; 2465 ddi_acc_handle_t accessp; 2466 int rval; 2467 2468 ASSERT(mutex_owned(&mpt->m_mutex)); 2469 2470 attrs = mpt->m_msg_dma_attr; 2471 attrs.dma_attr_sgllen = 1; 2472 attrs.dma_attr_granular = size; 2473 2474 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle, 2475 &accessp, &memp, size, NULL) == FALSE) { 2476 return (DDI_FAILURE); 2477 } 2478 2479 rval = (*callback) (mpt, memp, var, accessp); 2480 2481 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) || 2482 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) { 2483 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 2484 rval = DDI_FAILURE; 2485 } 2486 2487 mptsas_dma_addr_destroy(&dma_handle, &accessp); 2488 return (rval); 2489 2490 } 2491 2492 static int 2493 mptsas_alloc_request_frames(mptsas_t *mpt) 2494 { 2495 ddi_dma_attr_t frame_dma_attrs; 2496 caddr_t memp; 2497 ddi_dma_cookie_t cookie; 2498 size_t mem_size; 2499 2500 /* 2501 * re-alloc when it has already alloced 2502 */ 2503 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2504 &mpt->m_acc_req_frame_hdl); 2505 2506 /* 2507 * The size of the request frame pool is: 2508 * Number of Request Frames * Request Frame Size 2509 */ 2510 mem_size = mpt->m_max_requests * mpt->m_req_frame_size; 2511 2512 /* 2513 * set the DMA attributes. System Request Message Frames must be 2514 * aligned on a 16-byte boundry. 2515 */ 2516 frame_dma_attrs = mpt->m_msg_dma_attr; 2517 frame_dma_attrs.dma_attr_align = 16; 2518 frame_dma_attrs.dma_attr_sgllen = 1; 2519 2520 /* 2521 * allocate the request frame pool. 2522 */ 2523 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2524 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp, 2525 mem_size, &cookie) == FALSE) { 2526 return (DDI_FAILURE); 2527 } 2528 2529 /* 2530 * Store the request frame memory address. This chip uses this 2531 * address to dma to and from the driver's frame. The second 2532 * address is the address mpt uses to fill in the frame. 2533 */ 2534 mpt->m_req_frame_dma_addr = cookie.dmac_laddress; 2535 mpt->m_req_frame = memp; 2536 2537 /* 2538 * Clear the request frame pool. 2539 */ 2540 bzero(mpt->m_req_frame, mem_size); 2541 2542 return (DDI_SUCCESS); 2543 } 2544 2545 static int 2546 mptsas_alloc_reply_frames(mptsas_t *mpt) 2547 { 2548 ddi_dma_attr_t frame_dma_attrs; 2549 caddr_t memp; 2550 ddi_dma_cookie_t cookie; 2551 size_t mem_size; 2552 2553 /* 2554 * re-alloc when it has already alloced 2555 */ 2556 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2557 &mpt->m_acc_reply_frame_hdl); 2558 2559 /* 2560 * The size of the reply frame pool is: 2561 * Number of Reply Frames * Reply Frame Size 2562 */ 2563 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size; 2564 2565 /* 2566 * set the DMA attributes. System Reply Message Frames must be 2567 * aligned on a 4-byte boundry. This is the default. 2568 */ 2569 frame_dma_attrs = mpt->m_msg_dma_attr; 2570 frame_dma_attrs.dma_attr_sgllen = 1; 2571 2572 /* 2573 * allocate the reply frame pool 2574 */ 2575 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2576 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp, 2577 mem_size, &cookie) == FALSE) { 2578 return (DDI_FAILURE); 2579 } 2580 2581 /* 2582 * Store the reply frame memory address. This chip uses this 2583 * address to dma to and from the driver's frame. The second 2584 * address is the address mpt uses to process the frame. 2585 */ 2586 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress; 2587 mpt->m_reply_frame = memp; 2588 2589 /* 2590 * Clear the reply frame pool. 2591 */ 2592 bzero(mpt->m_reply_frame, mem_size); 2593 2594 return (DDI_SUCCESS); 2595 } 2596 2597 static int 2598 mptsas_alloc_free_queue(mptsas_t *mpt) 2599 { 2600 ddi_dma_attr_t frame_dma_attrs; 2601 caddr_t memp; 2602 ddi_dma_cookie_t cookie; 2603 size_t mem_size; 2604 2605 /* 2606 * re-alloc when it has already alloced 2607 */ 2608 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2609 &mpt->m_acc_free_queue_hdl); 2610 2611 /* 2612 * The reply free queue size is: 2613 * Reply Free Queue Depth * 4 2614 * The "4" is the size of one 32 bit address (low part of 64-bit 2615 * address) 2616 */ 2617 mem_size = mpt->m_free_queue_depth * 4; 2618 2619 /* 2620 * set the DMA attributes The Reply Free Queue must be aligned on a 2621 * 16-byte boundry. 2622 */ 2623 frame_dma_attrs = mpt->m_msg_dma_attr; 2624 frame_dma_attrs.dma_attr_align = 16; 2625 frame_dma_attrs.dma_attr_sgllen = 1; 2626 2627 /* 2628 * allocate the reply free queue 2629 */ 2630 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2631 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp, 2632 mem_size, &cookie) == FALSE) { 2633 return (DDI_FAILURE); 2634 } 2635 2636 /* 2637 * Store the reply free queue memory address. This chip uses this 2638 * address to read from the reply free queue. The second address 2639 * is the address mpt uses to manage the queue. 2640 */ 2641 mpt->m_free_queue_dma_addr = cookie.dmac_laddress; 2642 mpt->m_free_queue = memp; 2643 2644 /* 2645 * Clear the reply free queue memory. 2646 */ 2647 bzero(mpt->m_free_queue, mem_size); 2648 2649 return (DDI_SUCCESS); 2650 } 2651 2652 static int 2653 mptsas_alloc_post_queue(mptsas_t *mpt) 2654 { 2655 ddi_dma_attr_t frame_dma_attrs; 2656 caddr_t memp; 2657 ddi_dma_cookie_t cookie; 2658 size_t mem_size; 2659 2660 /* 2661 * re-alloc when it has already alloced 2662 */ 2663 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2664 &mpt->m_acc_post_queue_hdl); 2665 2666 /* 2667 * The reply descriptor post queue size is: 2668 * Reply Descriptor Post Queue Depth * 8 2669 * The "8" is the size of each descriptor (8 bytes or 64 bits). 2670 */ 2671 mem_size = mpt->m_post_queue_depth * 8; 2672 2673 /* 2674 * set the DMA attributes. The Reply Descriptor Post Queue must be 2675 * aligned on a 16-byte boundry. 2676 */ 2677 frame_dma_attrs = mpt->m_msg_dma_attr; 2678 frame_dma_attrs.dma_attr_align = 16; 2679 frame_dma_attrs.dma_attr_sgllen = 1; 2680 2681 /* 2682 * allocate the reply post queue 2683 */ 2684 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2685 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp, 2686 mem_size, &cookie) == FALSE) { 2687 return (DDI_FAILURE); 2688 } 2689 2690 /* 2691 * Store the reply descriptor post queue memory address. This chip 2692 * uses this address to write to the reply descriptor post queue. The 2693 * second address is the address mpt uses to manage the queue. 2694 */ 2695 mpt->m_post_queue_dma_addr = cookie.dmac_laddress; 2696 mpt->m_post_queue = memp; 2697 2698 /* 2699 * Clear the reply post queue memory. 2700 */ 2701 bzero(mpt->m_post_queue, mem_size); 2702 2703 return (DDI_SUCCESS); 2704 } 2705 2706 static void 2707 mptsas_alloc_reply_args(mptsas_t *mpt) 2708 { 2709 if (mpt->m_replyh_args == NULL) { 2710 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) * 2711 mpt->m_max_replies, KM_SLEEP); 2712 } 2713 } 2714 2715 static int 2716 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2717 { 2718 mptsas_cache_frames_t *frames = NULL; 2719 if (cmd->cmd_extra_frames == NULL) { 2720 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP); 2721 if (frames == NULL) { 2722 return (DDI_FAILURE); 2723 } 2724 cmd->cmd_extra_frames = frames; 2725 } 2726 return (DDI_SUCCESS); 2727 } 2728 2729 static void 2730 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2731 { 2732 if (cmd->cmd_extra_frames) { 2733 kmem_cache_free(mpt->m_cache_frames, 2734 (void *)cmd->cmd_extra_frames); 2735 cmd->cmd_extra_frames = NULL; 2736 } 2737 } 2738 2739 static void 2740 mptsas_cfg_fini(mptsas_t *mpt) 2741 { 2742 NDBG0(("mptsas_cfg_fini")); 2743 ddi_regs_map_free(&mpt->m_datap); 2744 } 2745 2746 static void 2747 mptsas_hba_fini(mptsas_t *mpt) 2748 { 2749 NDBG0(("mptsas_hba_fini")); 2750 2751 /* 2752 * Free up any allocated memory 2753 */ 2754 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2755 &mpt->m_acc_req_frame_hdl); 2756 2757 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2758 &mpt->m_acc_reply_frame_hdl); 2759 2760 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2761 &mpt->m_acc_free_queue_hdl); 2762 2763 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2764 &mpt->m_acc_post_queue_hdl); 2765 2766 if (mpt->m_replyh_args != NULL) { 2767 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 2768 * mpt->m_max_replies); 2769 } 2770 } 2771 2772 static int 2773 mptsas_name_child(dev_info_t *lun_dip, char *name, int len) 2774 { 2775 int lun = 0; 2776 char *sas_wwn = NULL; 2777 int phynum = -1; 2778 int reallen = 0; 2779 2780 /* Get the target num */ 2781 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS, 2782 LUN_PROP, 0); 2783 2784 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, 2785 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) { 2786 /* 2787 * Stick in the address of form "pPHY,LUN" 2788 */ 2789 reallen = snprintf(name, len, "p%x,%x", phynum, lun); 2790 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip, 2791 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn) 2792 == DDI_PROP_SUCCESS) { 2793 /* 2794 * Stick in the address of the form "wWWN,LUN" 2795 */ 2796 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun); 2797 ddi_prop_free(sas_wwn); 2798 } else { 2799 return (DDI_FAILURE); 2800 } 2801 2802 ASSERT(reallen < len); 2803 if (reallen >= len) { 2804 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter " 2805 "length too small, it needs to be %d bytes", reallen + 1); 2806 } 2807 return (DDI_SUCCESS); 2808 } 2809 2810 /* 2811 * tran_tgt_init(9E) - target device instance initialization 2812 */ 2813 static int 2814 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 2815 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 2816 { 2817 #ifndef __lock_lint 2818 _NOTE(ARGUNUSED(hba_tran)) 2819 #endif 2820 2821 /* 2822 * At this point, the scsi_device structure already exists 2823 * and has been initialized. 2824 * 2825 * Use this function to allocate target-private data structures, 2826 * if needed by this HBA. Add revised flow-control and queue 2827 * properties for child here, if desired and if you can tell they 2828 * support tagged queueing by now. 2829 */ 2830 mptsas_t *mpt; 2831 int lun = sd->sd_address.a_lun; 2832 mdi_pathinfo_t *pip = NULL; 2833 mptsas_tgt_private_t *tgt_private = NULL; 2834 mptsas_target_t *ptgt = NULL; 2835 char *psas_wwn = NULL; 2836 mptsas_phymask_t phymask = 0; 2837 uint64_t sas_wwn = 0; 2838 mptsas_target_addr_t addr; 2839 mpt = SDEV2MPT(sd); 2840 2841 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0); 2842 2843 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d", 2844 (void *)hba_dip, (void *)tgt_dip, lun)); 2845 2846 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 2847 (void) ndi_merge_node(tgt_dip, mptsas_name_child); 2848 ddi_set_name_addr(tgt_dip, NULL); 2849 return (DDI_FAILURE); 2850 } 2851 /* 2852 * phymask is 0 means the virtual port for RAID 2853 */ 2854 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0, 2855 "phymask", 0); 2856 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 2857 if ((pip = (void *)(sd->sd_private)) == NULL) { 2858 /* 2859 * Very bad news if this occurs. Somehow scsi_vhci has 2860 * lost the pathinfo node for this target. 2861 */ 2862 return (DDI_NOT_WELL_FORMED); 2863 } 2864 2865 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) != 2866 DDI_PROP_SUCCESS) { 2867 mptsas_log(mpt, CE_WARN, "Get lun property failed\n"); 2868 return (DDI_FAILURE); 2869 } 2870 2871 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT, 2872 &psas_wwn) == MDI_SUCCESS) { 2873 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 2874 sas_wwn = 0; 2875 } 2876 (void) mdi_prop_free(psas_wwn); 2877 } 2878 } else { 2879 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip, 2880 DDI_PROP_DONTPASS, LUN_PROP, 0); 2881 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip, 2882 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) == 2883 DDI_PROP_SUCCESS) { 2884 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 2885 sas_wwn = 0; 2886 } 2887 ddi_prop_free(psas_wwn); 2888 } else { 2889 sas_wwn = 0; 2890 } 2891 } 2892 2893 ASSERT((sas_wwn != 0) || (phymask != 0)); 2894 addr.mta_wwn = sas_wwn; 2895 addr.mta_phymask = phymask; 2896 mutex_enter(&mpt->m_mutex); 2897 ptgt = refhash_lookup(mpt->m_targets, &addr); 2898 mutex_exit(&mpt->m_mutex); 2899 if (ptgt == NULL) { 2900 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or " 2901 "gone already! phymask:%x, saswwn %"PRIx64, phymask, 2902 sas_wwn); 2903 return (DDI_FAILURE); 2904 } 2905 if (hba_tran->tran_tgt_private == NULL) { 2906 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t), 2907 KM_SLEEP); 2908 tgt_private->t_lun = lun; 2909 tgt_private->t_private = ptgt; 2910 hba_tran->tran_tgt_private = tgt_private; 2911 } 2912 2913 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 2914 return (DDI_SUCCESS); 2915 } 2916 mutex_enter(&mpt->m_mutex); 2917 2918 if (ptgt->m_deviceinfo & 2919 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 2920 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 2921 uchar_t *inq89 = NULL; 2922 int inq89_len = 0x238; 2923 int reallen = 0; 2924 int rval = 0; 2925 struct sata_id *sid = NULL; 2926 char model[SATA_ID_MODEL_LEN + 1]; 2927 char fw[SATA_ID_FW_LEN + 1]; 2928 char *vid, *pid; 2929 int i; 2930 2931 mutex_exit(&mpt->m_mutex); 2932 /* 2933 * According SCSI/ATA Translation -2 (SAT-2) revision 01a 2934 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY 2935 * DEVICE data or ATA IDENTIFY PACKET DEVICE data. 2936 */ 2937 inq89 = kmem_zalloc(inq89_len, KM_SLEEP); 2938 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89, 2939 inq89, inq89_len, &reallen, 1); 2940 2941 if (rval != 0) { 2942 if (inq89 != NULL) { 2943 kmem_free(inq89, inq89_len); 2944 } 2945 2946 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 2947 "0x89 for SATA target:%x failed!", ptgt->m_devhdl); 2948 return (DDI_SUCCESS); 2949 } 2950 sid = (void *)(&inq89[60]); 2951 2952 swab(sid->ai_model, model, SATA_ID_MODEL_LEN); 2953 swab(sid->ai_fw, fw, SATA_ID_FW_LEN); 2954 2955 model[SATA_ID_MODEL_LEN] = 0; 2956 fw[SATA_ID_FW_LEN] = 0; 2957 2958 /* 2959 * split model into into vid/pid 2960 */ 2961 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++) 2962 if ((*pid == ' ') || (*pid == '\t')) 2963 break; 2964 if (i < SATA_ID_MODEL_LEN) { 2965 vid = model; 2966 /* 2967 * terminate vid, establish pid 2968 */ 2969 *pid++ = 0; 2970 } else { 2971 /* 2972 * vid will stay "ATA ", the rule is same 2973 * as sata framework implementation. 2974 */ 2975 vid = NULL; 2976 /* 2977 * model is all pid 2978 */ 2979 pid = model; 2980 } 2981 2982 /* 2983 * override SCSA "inquiry-*" properties 2984 */ 2985 if (vid) 2986 (void) scsi_device_prop_update_inqstring(sd, 2987 INQUIRY_VENDOR_ID, vid, strlen(vid)); 2988 if (pid) 2989 (void) scsi_device_prop_update_inqstring(sd, 2990 INQUIRY_PRODUCT_ID, pid, strlen(pid)); 2991 (void) scsi_device_prop_update_inqstring(sd, 2992 INQUIRY_REVISION_ID, fw, strlen(fw)); 2993 2994 if (inq89 != NULL) { 2995 kmem_free(inq89, inq89_len); 2996 } 2997 } else { 2998 mutex_exit(&mpt->m_mutex); 2999 } 3000 3001 return (DDI_SUCCESS); 3002 } 3003 /* 3004 * tran_tgt_free(9E) - target device instance deallocation 3005 */ 3006 static void 3007 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 3008 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 3009 { 3010 #ifndef __lock_lint 3011 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd)) 3012 #endif 3013 3014 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private; 3015 3016 if (tgt_private != NULL) { 3017 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 3018 hba_tran->tran_tgt_private = NULL; 3019 } 3020 } 3021 3022 /* 3023 * scsi_pkt handling 3024 * 3025 * Visible to the external world via the transport structure. 3026 */ 3027 3028 /* 3029 * Notes: 3030 * - transport the command to the addressed SCSI target/lun device 3031 * - normal operation is to schedule the command to be transported, 3032 * and return TRAN_ACCEPT if this is successful. 3033 * - if NO_INTR, tran_start must poll device for command completion 3034 */ 3035 static int 3036 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt) 3037 { 3038 #ifndef __lock_lint 3039 _NOTE(ARGUNUSED(ap)) 3040 #endif 3041 mptsas_t *mpt = PKT2MPT(pkt); 3042 mptsas_cmd_t *cmd = PKT2CMD(pkt); 3043 int rval; 3044 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3045 3046 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt)); 3047 ASSERT(ptgt); 3048 if (ptgt == NULL) 3049 return (TRAN_FATAL_ERROR); 3050 3051 /* 3052 * prepare the pkt before taking mutex. 3053 */ 3054 rval = mptsas_prepare_pkt(cmd); 3055 if (rval != TRAN_ACCEPT) { 3056 return (rval); 3057 } 3058 3059 /* 3060 * Send the command to target/lun, however your HBA requires it. 3061 * If busy, return TRAN_BUSY; if there's some other formatting error 3062 * in the packet, return TRAN_BADPKT; otherwise, fall through to the 3063 * return of TRAN_ACCEPT. 3064 * 3065 * Remember that access to shared resources, including the mptsas_t 3066 * data structure and the HBA hardware registers, must be protected 3067 * with mutexes, here and everywhere. 3068 * 3069 * Also remember that at interrupt time, you'll get an argument 3070 * to the interrupt handler which is a pointer to your mptsas_t 3071 * structure; you'll have to remember which commands are outstanding 3072 * and which scsi_pkt is the currently-running command so the 3073 * interrupt handler can refer to the pkt to set completion 3074 * status, call the target driver back through pkt_comp, etc. 3075 * 3076 * If the instance lock is held by other thread, don't spin to wait 3077 * for it. Instead, queue the cmd and next time when the instance lock 3078 * is not held, accept all the queued cmd. A extra tx_waitq is 3079 * introduced to protect the queue. 3080 * 3081 * The polled cmd will not be queud and accepted as usual. 3082 * 3083 * Under the tx_waitq mutex, record whether a thread is draining 3084 * the tx_waitq. An IO requesting thread that finds the instance 3085 * mutex contended appends to the tx_waitq and while holding the 3086 * tx_wait mutex, if the draining flag is not set, sets it and then 3087 * proceeds to spin for the instance mutex. This scheme ensures that 3088 * the last cmd in a burst be processed. 3089 * 3090 * we enable this feature only when the helper threads are enabled, 3091 * at which we think the loads are heavy. 3092 * 3093 * per instance mutex m_tx_waitq_mutex is introduced to protect the 3094 * m_tx_waitqtail, m_tx_waitq, m_tx_draining. 3095 */ 3096 3097 if (mpt->m_doneq_thread_n) { 3098 if (mutex_tryenter(&mpt->m_mutex) != 0) { 3099 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3100 mutex_exit(&mpt->m_mutex); 3101 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3102 mutex_enter(&mpt->m_mutex); 3103 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3104 mutex_exit(&mpt->m_mutex); 3105 } else { 3106 mutex_enter(&mpt->m_tx_waitq_mutex); 3107 /* 3108 * ptgt->m_dr_flag is protected by m_mutex or 3109 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex 3110 * is acquired. 3111 */ 3112 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3113 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3114 /* 3115 * The command should be allowed to 3116 * retry by returning TRAN_BUSY to 3117 * to stall the I/O's which come from 3118 * scsi_vhci since the device/path is 3119 * in unstable state now. 3120 */ 3121 mutex_exit(&mpt->m_tx_waitq_mutex); 3122 return (TRAN_BUSY); 3123 } else { 3124 /* 3125 * The device is offline, just fail the 3126 * command by returning 3127 * TRAN_FATAL_ERROR. 3128 */ 3129 mutex_exit(&mpt->m_tx_waitq_mutex); 3130 return (TRAN_FATAL_ERROR); 3131 } 3132 } 3133 if (mpt->m_tx_draining) { 3134 cmd->cmd_flags |= CFLAG_TXQ; 3135 *mpt->m_tx_waitqtail = cmd; 3136 mpt->m_tx_waitqtail = &cmd->cmd_linkp; 3137 mutex_exit(&mpt->m_tx_waitq_mutex); 3138 } else { /* drain the queue */ 3139 mpt->m_tx_draining = 1; 3140 mutex_exit(&mpt->m_tx_waitq_mutex); 3141 mutex_enter(&mpt->m_mutex); 3142 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3143 mutex_exit(&mpt->m_mutex); 3144 } 3145 } 3146 } else { 3147 mutex_enter(&mpt->m_mutex); 3148 /* 3149 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3150 * in this case, m_mutex is acquired. 3151 */ 3152 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3153 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3154 /* 3155 * commands should be allowed to retry by 3156 * returning TRAN_BUSY to stall the I/O's 3157 * which come from scsi_vhci since the device/ 3158 * path is in unstable state now. 3159 */ 3160 mutex_exit(&mpt->m_mutex); 3161 return (TRAN_BUSY); 3162 } else { 3163 /* 3164 * The device is offline, just fail the 3165 * command by returning TRAN_FATAL_ERROR. 3166 */ 3167 mutex_exit(&mpt->m_mutex); 3168 return (TRAN_FATAL_ERROR); 3169 } 3170 } 3171 rval = mptsas_accept_pkt(mpt, cmd); 3172 mutex_exit(&mpt->m_mutex); 3173 } 3174 3175 return (rval); 3176 } 3177 3178 /* 3179 * Accept all the queued cmds(if any) before accept the current one. 3180 */ 3181 static int 3182 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3183 { 3184 int rval; 3185 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3186 3187 ASSERT(mutex_owned(&mpt->m_mutex)); 3188 /* 3189 * The call to mptsas_accept_tx_waitq() must always be performed 3190 * because that is where mpt->m_tx_draining is cleared. 3191 */ 3192 mutex_enter(&mpt->m_tx_waitq_mutex); 3193 mptsas_accept_tx_waitq(mpt); 3194 mutex_exit(&mpt->m_tx_waitq_mutex); 3195 /* 3196 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3197 * in this case, m_mutex is acquired. 3198 */ 3199 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3200 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3201 /* 3202 * The command should be allowed to retry by returning 3203 * TRAN_BUSY to stall the I/O's which come from 3204 * scsi_vhci since the device/path is in unstable state 3205 * now. 3206 */ 3207 return (TRAN_BUSY); 3208 } else { 3209 /* 3210 * The device is offline, just fail the command by 3211 * return TRAN_FATAL_ERROR. 3212 */ 3213 return (TRAN_FATAL_ERROR); 3214 } 3215 } 3216 rval = mptsas_accept_pkt(mpt, cmd); 3217 3218 return (rval); 3219 } 3220 3221 static int 3222 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3223 { 3224 int rval = TRAN_ACCEPT; 3225 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3226 3227 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd)); 3228 3229 ASSERT(mutex_owned(&mpt->m_mutex)); 3230 3231 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) { 3232 rval = mptsas_prepare_pkt(cmd); 3233 if (rval != TRAN_ACCEPT) { 3234 cmd->cmd_flags &= ~CFLAG_TRANFLAG; 3235 return (rval); 3236 } 3237 } 3238 3239 /* 3240 * reset the throttle if we were draining 3241 */ 3242 if ((ptgt->m_t_ncmds == 0) && 3243 (ptgt->m_t_throttle == DRAIN_THROTTLE)) { 3244 NDBG23(("reset throttle")); 3245 ASSERT(ptgt->m_reset_delay == 0); 3246 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 3247 } 3248 3249 /* 3250 * If HBA is being reset, the DevHandles are being re-initialized, 3251 * which means that they could be invalid even if the target is still 3252 * attached. Check if being reset and if DevHandle is being 3253 * re-initialized. If this is the case, return BUSY so the I/O can be 3254 * retried later. 3255 */ 3256 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) { 3257 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 3258 if (cmd->cmd_flags & CFLAG_TXQ) { 3259 mptsas_doneq_add(mpt, cmd); 3260 mptsas_doneq_empty(mpt); 3261 return (rval); 3262 } else { 3263 return (TRAN_BUSY); 3264 } 3265 } 3266 3267 /* 3268 * If device handle has already been invalidated, just 3269 * fail the command. In theory, command from scsi_vhci 3270 * client is impossible send down command with invalid 3271 * devhdl since devhdl is set after path offline, target 3272 * driver is not suppose to select a offlined path. 3273 */ 3274 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) { 3275 NDBG20(("rejecting command, it might because invalid devhdl " 3276 "request.")); 3277 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED); 3278 if (cmd->cmd_flags & CFLAG_TXQ) { 3279 mptsas_doneq_add(mpt, cmd); 3280 mptsas_doneq_empty(mpt); 3281 return (rval); 3282 } else { 3283 return (TRAN_FATAL_ERROR); 3284 } 3285 } 3286 /* 3287 * The first case is the normal case. mpt gets a command from the 3288 * target driver and starts it. 3289 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 3290 * commands is m_max_requests - 2. 3291 */ 3292 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 3293 (ptgt->m_t_throttle > HOLD_THROTTLE) && 3294 (ptgt->m_t_ncmds < ptgt->m_t_throttle) && 3295 (ptgt->m_reset_delay == 0) && 3296 (ptgt->m_t_nwait == 0) && 3297 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) { 3298 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 3299 (void) mptsas_start_cmd(mpt, cmd); 3300 } else { 3301 mptsas_waitq_add(mpt, cmd); 3302 } 3303 } else { 3304 /* 3305 * Add this pkt to the work queue 3306 */ 3307 mptsas_waitq_add(mpt, cmd); 3308 3309 if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3310 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME); 3311 3312 /* 3313 * Only flush the doneq if this is not a TM 3314 * cmd. For TM cmds the flushing of the 3315 * doneq will be done in those routines. 3316 */ 3317 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 3318 mptsas_doneq_empty(mpt); 3319 } 3320 } 3321 } 3322 return (rval); 3323 } 3324 3325 int 3326 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 3327 { 3328 mptsas_slots_t *slots = mpt->m_active; 3329 uint_t slot, start_rotor; 3330 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3331 3332 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 3333 3334 /* 3335 * Account for reserved TM request slot and reserved SMID of 0. 3336 */ 3337 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2)); 3338 3339 /* 3340 * Find the next available slot, beginning at m_rotor. If no slot is 3341 * available, we'll return FALSE to indicate that. This mechanism 3342 * considers only the normal slots, not the reserved slot 0 nor the 3343 * task management slot m_n_normal + 1. The rotor is left to point to 3344 * the normal slot after the one we select, unless we select the last 3345 * normal slot in which case it returns to slot 1. 3346 */ 3347 start_rotor = slots->m_rotor; 3348 do { 3349 slot = slots->m_rotor++; 3350 if (slots->m_rotor > slots->m_n_normal) 3351 slots->m_rotor = 1; 3352 3353 if (slots->m_rotor == start_rotor) 3354 break; 3355 } while (slots->m_slot[slot] != NULL); 3356 3357 if (slots->m_slot[slot] != NULL) 3358 return (FALSE); 3359 3360 ASSERT(slot != 0 && slot <= slots->m_n_normal); 3361 3362 cmd->cmd_slot = slot; 3363 slots->m_slot[slot] = cmd; 3364 mpt->m_ncmds++; 3365 3366 /* 3367 * only increment per target ncmds if this is not a 3368 * command that has no target associated with it (i.e. a 3369 * event acknoledgment) 3370 */ 3371 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 3372 ptgt->m_t_ncmds++; 3373 } 3374 cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time; 3375 3376 /* 3377 * If initial timout is less than or equal to one tick, bump 3378 * the timeout by a tick so that command doesn't timeout before 3379 * its allotted time. 3380 */ 3381 if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) { 3382 cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick; 3383 } 3384 return (TRUE); 3385 } 3386 3387 /* 3388 * prepare the pkt: 3389 * the pkt may have been resubmitted or just reused so 3390 * initialize some fields and do some checks. 3391 */ 3392 static int 3393 mptsas_prepare_pkt(mptsas_cmd_t *cmd) 3394 { 3395 struct scsi_pkt *pkt = CMD2PKT(cmd); 3396 3397 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd)); 3398 3399 /* 3400 * Reinitialize some fields that need it; the packet may 3401 * have been resubmitted 3402 */ 3403 pkt->pkt_reason = CMD_CMPLT; 3404 pkt->pkt_state = 0; 3405 pkt->pkt_statistics = 0; 3406 pkt->pkt_resid = 0; 3407 cmd->cmd_age = 0; 3408 cmd->cmd_pkt_flags = pkt->pkt_flags; 3409 3410 /* 3411 * zero status byte. 3412 */ 3413 *(pkt->pkt_scbp) = 0; 3414 3415 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3416 pkt->pkt_resid = cmd->cmd_dmacount; 3417 3418 /* 3419 * consistent packets need to be sync'ed first 3420 * (only for data going out) 3421 */ 3422 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 3423 (cmd->cmd_flags & CFLAG_DMASEND)) { 3424 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 3425 DDI_DMA_SYNC_FORDEV); 3426 } 3427 } 3428 3429 cmd->cmd_flags = 3430 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) | 3431 CFLAG_PREPARED | CFLAG_IN_TRANSPORT; 3432 3433 return (TRAN_ACCEPT); 3434 } 3435 3436 /* 3437 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command 3438 * 3439 * One of three possibilities: 3440 * - allocate scsi_pkt 3441 * - allocate scsi_pkt and DMA resources 3442 * - allocate DMA resources to an already-allocated pkt 3443 */ 3444 static struct scsi_pkt * 3445 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt, 3446 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags, 3447 int (*callback)(), caddr_t arg) 3448 { 3449 mptsas_cmd_t *cmd, *new_cmd; 3450 mptsas_t *mpt = ADDR2MPT(ap); 3451 int failure = 1; 3452 uint_t oldcookiec; 3453 mptsas_target_t *ptgt = NULL; 3454 int rval; 3455 mptsas_tgt_private_t *tgt_private; 3456 int kf; 3457 3458 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP; 3459 3460 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 3461 tran_tgt_private; 3462 ASSERT(tgt_private != NULL); 3463 if (tgt_private == NULL) { 3464 return (NULL); 3465 } 3466 ptgt = tgt_private->t_private; 3467 ASSERT(ptgt != NULL); 3468 if (ptgt == NULL) 3469 return (NULL); 3470 ap->a_target = ptgt->m_devhdl; 3471 ap->a_lun = tgt_private->t_lun; 3472 3473 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC); 3474 #ifdef MPTSAS_TEST_EXTRN_ALLOC 3475 statuslen *= 100; tgtlen *= 4; 3476 #endif 3477 NDBG3(("mptsas_scsi_init_pkt:\n" 3478 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x", 3479 ap->a_target, (void *)pkt, (void *)bp, 3480 cmdlen, statuslen, tgtlen, flags)); 3481 3482 /* 3483 * Allocate the new packet. 3484 */ 3485 if (pkt == NULL) { 3486 ddi_dma_handle_t save_dma_handle; 3487 ddi_dma_handle_t save_arq_dma_handle; 3488 struct buf *save_arq_bp; 3489 ddi_dma_cookie_t save_arqcookie; 3490 3491 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf); 3492 3493 if (cmd) { 3494 save_dma_handle = cmd->cmd_dmahandle; 3495 save_arq_dma_handle = cmd->cmd_arqhandle; 3496 save_arq_bp = cmd->cmd_arq_buf; 3497 save_arqcookie = cmd->cmd_arqcookie; 3498 bzero(cmd, sizeof (*cmd) + scsi_pkt_size()); 3499 cmd->cmd_dmahandle = save_dma_handle; 3500 cmd->cmd_arqhandle = save_arq_dma_handle; 3501 cmd->cmd_arq_buf = save_arq_bp; 3502 cmd->cmd_arqcookie = save_arqcookie; 3503 3504 pkt = (void *)((uchar_t *)cmd + 3505 sizeof (struct mptsas_cmd)); 3506 pkt->pkt_ha_private = (opaque_t)cmd; 3507 pkt->pkt_address = *ap; 3508 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private; 3509 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 3510 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb; 3511 cmd->cmd_pkt = (struct scsi_pkt *)pkt; 3512 cmd->cmd_cdblen = (uchar_t)cmdlen; 3513 cmd->cmd_scblen = statuslen; 3514 cmd->cmd_rqslen = SENSE_LENGTH; 3515 cmd->cmd_tgt_addr = ptgt; 3516 failure = 0; 3517 } 3518 3519 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) || 3520 (tgtlen > PKT_PRIV_LEN) || 3521 (statuslen > EXTCMDS_STATUS_SIZE)) { 3522 if (failure == 0) { 3523 /* 3524 * if extern alloc fails, all will be 3525 * deallocated, including cmd 3526 */ 3527 failure = mptsas_pkt_alloc_extern(mpt, cmd, 3528 cmdlen, tgtlen, statuslen, kf); 3529 } 3530 if (failure) { 3531 /* 3532 * if extern allocation fails, it will 3533 * deallocate the new pkt as well 3534 */ 3535 return (NULL); 3536 } 3537 } 3538 new_cmd = cmd; 3539 3540 } else { 3541 cmd = PKT2CMD(pkt); 3542 new_cmd = NULL; 3543 } 3544 3545 3546 /* grab cmd->cmd_cookiec here as oldcookiec */ 3547 3548 oldcookiec = cmd->cmd_cookiec; 3549 3550 /* 3551 * If the dma was broken up into PARTIAL transfers cmd_nwin will be 3552 * greater than 0 and we'll need to grab the next dma window 3553 */ 3554 /* 3555 * SLM-not doing extra command frame right now; may add later 3556 */ 3557 3558 if (cmd->cmd_nwin > 0) { 3559 3560 /* 3561 * Make sure we havn't gone past the the total number 3562 * of windows 3563 */ 3564 if (++cmd->cmd_winindex >= cmd->cmd_nwin) { 3565 return (NULL); 3566 } 3567 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex, 3568 &cmd->cmd_dma_offset, &cmd->cmd_dma_len, 3569 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) { 3570 return (NULL); 3571 } 3572 goto get_dma_cookies; 3573 } 3574 3575 3576 if (flags & PKT_XARQ) { 3577 cmd->cmd_flags |= CFLAG_XARQ; 3578 } 3579 3580 /* 3581 * DMA resource allocation. This version assumes your 3582 * HBA has some sort of bus-mastering or onboard DMA capability, with a 3583 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the 3584 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget. 3585 */ 3586 if (bp && (bp->b_bcount != 0) && 3587 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) { 3588 3589 int cnt, dma_flags; 3590 mptti_t *dmap; /* ptr to the S/G list */ 3591 3592 /* 3593 * Set up DMA memory and position to the next DMA segment. 3594 */ 3595 ASSERT(cmd->cmd_dmahandle != NULL); 3596 3597 if (bp->b_flags & B_READ) { 3598 dma_flags = DDI_DMA_READ; 3599 cmd->cmd_flags &= ~CFLAG_DMASEND; 3600 } else { 3601 dma_flags = DDI_DMA_WRITE; 3602 cmd->cmd_flags |= CFLAG_DMASEND; 3603 } 3604 if (flags & PKT_CONSISTENT) { 3605 cmd->cmd_flags |= CFLAG_CMDIOPB; 3606 dma_flags |= DDI_DMA_CONSISTENT; 3607 } 3608 3609 if (flags & PKT_DMA_PARTIAL) { 3610 dma_flags |= DDI_DMA_PARTIAL; 3611 } 3612 3613 /* 3614 * workaround for byte hole issue on psycho and 3615 * schizo pre 2.1 3616 */ 3617 if ((bp->b_flags & B_READ) && ((bp->b_flags & 3618 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) && 3619 ((uintptr_t)bp->b_un.b_addr & 0x7)) { 3620 dma_flags |= DDI_DMA_CONSISTENT; 3621 } 3622 3623 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp, 3624 dma_flags, callback, arg, 3625 &cmd->cmd_cookie, &cmd->cmd_cookiec); 3626 if (rval == DDI_DMA_PARTIAL_MAP) { 3627 (void) ddi_dma_numwin(cmd->cmd_dmahandle, 3628 &cmd->cmd_nwin); 3629 cmd->cmd_winindex = 0; 3630 (void) ddi_dma_getwin(cmd->cmd_dmahandle, 3631 cmd->cmd_winindex, &cmd->cmd_dma_offset, 3632 &cmd->cmd_dma_len, &cmd->cmd_cookie, 3633 &cmd->cmd_cookiec); 3634 } else if (rval && (rval != DDI_DMA_MAPPED)) { 3635 switch (rval) { 3636 case DDI_DMA_NORESOURCES: 3637 bioerror(bp, 0); 3638 break; 3639 case DDI_DMA_BADATTR: 3640 case DDI_DMA_NOMAPPING: 3641 bioerror(bp, EFAULT); 3642 break; 3643 case DDI_DMA_TOOBIG: 3644 default: 3645 bioerror(bp, EINVAL); 3646 break; 3647 } 3648 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3649 if (new_cmd) { 3650 mptsas_scsi_destroy_pkt(ap, pkt); 3651 } 3652 return ((struct scsi_pkt *)NULL); 3653 } 3654 3655 get_dma_cookies: 3656 cmd->cmd_flags |= CFLAG_DMAVALID; 3657 ASSERT(cmd->cmd_cookiec > 0); 3658 3659 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) { 3660 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n", 3661 cmd->cmd_cookiec); 3662 bioerror(bp, EINVAL); 3663 if (new_cmd) { 3664 mptsas_scsi_destroy_pkt(ap, pkt); 3665 } 3666 return ((struct scsi_pkt *)NULL); 3667 } 3668 3669 /* 3670 * Allocate extra SGL buffer if needed. 3671 */ 3672 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) && 3673 (cmd->cmd_extra_frames == NULL)) { 3674 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) == 3675 DDI_FAILURE) { 3676 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc " 3677 "failed"); 3678 bioerror(bp, ENOMEM); 3679 if (new_cmd) { 3680 mptsas_scsi_destroy_pkt(ap, pkt); 3681 } 3682 return ((struct scsi_pkt *)NULL); 3683 } 3684 } 3685 3686 /* 3687 * Always use scatter-gather transfer 3688 * Use the loop below to store physical addresses of 3689 * DMA segments, from the DMA cookies, into your HBA's 3690 * scatter-gather list. 3691 * We need to ensure we have enough kmem alloc'd 3692 * for the sg entries since we are no longer using an 3693 * array inside mptsas_cmd_t. 3694 * 3695 * We check cmd->cmd_cookiec against oldcookiec so 3696 * the scatter-gather list is correctly allocated 3697 */ 3698 3699 if (oldcookiec != cmd->cmd_cookiec) { 3700 if (cmd->cmd_sg != (mptti_t *)NULL) { 3701 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * 3702 oldcookiec); 3703 cmd->cmd_sg = NULL; 3704 } 3705 } 3706 3707 if (cmd->cmd_sg == (mptti_t *)NULL) { 3708 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3709 cmd->cmd_cookiec), kf); 3710 3711 if (cmd->cmd_sg == (mptti_t *)NULL) { 3712 mptsas_log(mpt, CE_WARN, 3713 "unable to kmem_alloc enough memory " 3714 "for scatter/gather list"); 3715 /* 3716 * if we have an ENOMEM condition we need to behave 3717 * the same way as the rest of this routine 3718 */ 3719 3720 bioerror(bp, ENOMEM); 3721 if (new_cmd) { 3722 mptsas_scsi_destroy_pkt(ap, pkt); 3723 } 3724 return ((struct scsi_pkt *)NULL); 3725 } 3726 } 3727 3728 dmap = cmd->cmd_sg; 3729 3730 ASSERT(cmd->cmd_cookie.dmac_size != 0); 3731 3732 /* 3733 * store the first segment into the S/G list 3734 */ 3735 dmap->count = cmd->cmd_cookie.dmac_size; 3736 dmap->addr.address64.Low = (uint32_t) 3737 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3738 dmap->addr.address64.High = (uint32_t) 3739 (cmd->cmd_cookie.dmac_laddress >> 32); 3740 3741 /* 3742 * dmacount counts the size of the dma for this window 3743 * (if partial dma is being used). totaldmacount 3744 * keeps track of the total amount of dma we have 3745 * transferred for all the windows (needed to calculate 3746 * the resid value below). 3747 */ 3748 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size; 3749 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3750 3751 /* 3752 * We already stored the first DMA scatter gather segment, 3753 * start at 1 if we need to store more. 3754 */ 3755 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) { 3756 /* 3757 * Get next DMA cookie 3758 */ 3759 ddi_dma_nextcookie(cmd->cmd_dmahandle, 3760 &cmd->cmd_cookie); 3761 dmap++; 3762 3763 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size; 3764 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3765 3766 /* 3767 * store the segment parms into the S/G list 3768 */ 3769 dmap->count = cmd->cmd_cookie.dmac_size; 3770 dmap->addr.address64.Low = (uint32_t) 3771 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3772 dmap->addr.address64.High = (uint32_t) 3773 (cmd->cmd_cookie.dmac_laddress >> 32); 3774 } 3775 3776 /* 3777 * If this was partially allocated we set the resid 3778 * the amount of data NOT transferred in this window 3779 * If there is only one window, the resid will be 0 3780 */ 3781 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount); 3782 NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount)); 3783 } 3784 return (pkt); 3785 } 3786 3787 /* 3788 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation 3789 * 3790 * Notes: 3791 * - also frees DMA resources if allocated 3792 * - implicit DMA synchonization 3793 */ 3794 static void 3795 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 3796 { 3797 mptsas_cmd_t *cmd = PKT2CMD(pkt); 3798 mptsas_t *mpt = ADDR2MPT(ap); 3799 3800 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p", 3801 ap->a_target, (void *)pkt)); 3802 3803 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3804 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 3805 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3806 } 3807 3808 if (cmd->cmd_sg) { 3809 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec); 3810 cmd->cmd_sg = NULL; 3811 } 3812 3813 mptsas_free_extra_sgl_frame(mpt, cmd); 3814 3815 if ((cmd->cmd_flags & 3816 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN | 3817 CFLAG_SCBEXTERN)) == 0) { 3818 cmd->cmd_flags = CFLAG_FREE; 3819 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 3820 } else { 3821 mptsas_pkt_destroy_extern(mpt, cmd); 3822 } 3823 } 3824 3825 /* 3826 * kmem cache constructor and destructor: 3827 * When constructing, we bzero the cmd and allocate the dma handle 3828 * When destructing, just free the dma handle 3829 */ 3830 static int 3831 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags) 3832 { 3833 mptsas_cmd_t *cmd = buf; 3834 mptsas_t *mpt = cdrarg; 3835 struct scsi_address ap; 3836 uint_t cookiec; 3837 ddi_dma_attr_t arq_dma_attr; 3838 int (*callback)(caddr_t); 3839 3840 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 3841 3842 NDBG4(("mptsas_kmem_cache_constructor")); 3843 3844 ap.a_hba_tran = mpt->m_tran; 3845 ap.a_target = 0; 3846 ap.a_lun = 0; 3847 3848 /* 3849 * allocate a dma handle 3850 */ 3851 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback, 3852 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) { 3853 cmd->cmd_dmahandle = NULL; 3854 return (-1); 3855 } 3856 3857 cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL, 3858 SENSE_LENGTH, B_READ, callback, NULL); 3859 if (cmd->cmd_arq_buf == NULL) { 3860 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3861 cmd->cmd_dmahandle = NULL; 3862 return (-1); 3863 } 3864 3865 /* 3866 * allocate a arq handle 3867 */ 3868 arq_dma_attr = mpt->m_msg_dma_attr; 3869 arq_dma_attr.dma_attr_sgllen = 1; 3870 if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback, 3871 NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) { 3872 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3873 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3874 cmd->cmd_dmahandle = NULL; 3875 cmd->cmd_arqhandle = NULL; 3876 return (-1); 3877 } 3878 3879 if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle, 3880 cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT), 3881 callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) { 3882 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3883 ddi_dma_free_handle(&cmd->cmd_arqhandle); 3884 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3885 cmd->cmd_dmahandle = NULL; 3886 cmd->cmd_arqhandle = NULL; 3887 cmd->cmd_arq_buf = NULL; 3888 return (-1); 3889 } 3890 3891 return (0); 3892 } 3893 3894 static void 3895 mptsas_kmem_cache_destructor(void *buf, void *cdrarg) 3896 { 3897 #ifndef __lock_lint 3898 _NOTE(ARGUNUSED(cdrarg)) 3899 #endif 3900 mptsas_cmd_t *cmd = buf; 3901 3902 NDBG4(("mptsas_kmem_cache_destructor")); 3903 3904 if (cmd->cmd_arqhandle) { 3905 (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle); 3906 ddi_dma_free_handle(&cmd->cmd_arqhandle); 3907 cmd->cmd_arqhandle = NULL; 3908 } 3909 if (cmd->cmd_arq_buf) { 3910 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3911 cmd->cmd_arq_buf = NULL; 3912 } 3913 if (cmd->cmd_dmahandle) { 3914 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3915 cmd->cmd_dmahandle = NULL; 3916 } 3917 } 3918 3919 static int 3920 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags) 3921 { 3922 mptsas_cache_frames_t *p = buf; 3923 mptsas_t *mpt = cdrarg; 3924 ddi_dma_attr_t frame_dma_attr; 3925 size_t mem_size, alloc_len; 3926 ddi_dma_cookie_t cookie; 3927 uint_t ncookie; 3928 int (*callback)(caddr_t) = (kmflags == KM_SLEEP) 3929 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 3930 3931 frame_dma_attr = mpt->m_msg_dma_attr; 3932 frame_dma_attr.dma_attr_align = 0x10; 3933 frame_dma_attr.dma_attr_sgllen = 1; 3934 3935 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL, 3936 &p->m_dma_hdl) != DDI_SUCCESS) { 3937 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for" 3938 " extra SGL."); 3939 return (DDI_FAILURE); 3940 } 3941 3942 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size; 3943 3944 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr, 3945 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr, 3946 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) { 3947 ddi_dma_free_handle(&p->m_dma_hdl); 3948 p->m_dma_hdl = NULL; 3949 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for" 3950 " extra SGL."); 3951 return (DDI_FAILURE); 3952 } 3953 3954 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr, 3955 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL, 3956 &cookie, &ncookie) != DDI_DMA_MAPPED) { 3957 (void) ddi_dma_mem_free(&p->m_acc_hdl); 3958 ddi_dma_free_handle(&p->m_dma_hdl); 3959 p->m_dma_hdl = NULL; 3960 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for" 3961 " extra SGL"); 3962 return (DDI_FAILURE); 3963 } 3964 3965 /* 3966 * Store the SGL memory address. This chip uses this 3967 * address to dma to and from the driver. The second 3968 * address is the address mpt uses to fill in the SGL. 3969 */ 3970 p->m_phys_addr = cookie.dmac_address; 3971 3972 return (DDI_SUCCESS); 3973 } 3974 3975 static void 3976 mptsas_cache_frames_destructor(void *buf, void *cdrarg) 3977 { 3978 #ifndef __lock_lint 3979 _NOTE(ARGUNUSED(cdrarg)) 3980 #endif 3981 mptsas_cache_frames_t *p = buf; 3982 if (p->m_dma_hdl != NULL) { 3983 (void) ddi_dma_unbind_handle(p->m_dma_hdl); 3984 (void) ddi_dma_mem_free(&p->m_acc_hdl); 3985 ddi_dma_free_handle(&p->m_dma_hdl); 3986 p->m_phys_addr = NULL; 3987 p->m_frames_addr = NULL; 3988 p->m_dma_hdl = NULL; 3989 p->m_acc_hdl = NULL; 3990 } 3991 3992 } 3993 3994 /* 3995 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd) 3996 * for non-standard length cdb, pkt_private, status areas 3997 * if allocation fails, then deallocate all external space and the pkt 3998 */ 3999 /* ARGSUSED */ 4000 static int 4001 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 4002 int cmdlen, int tgtlen, int statuslen, int kf) 4003 { 4004 caddr_t cdbp, scbp, tgt; 4005 int (*callback)(caddr_t) = (kf == KM_SLEEP) ? 4006 DDI_DMA_SLEEP : DDI_DMA_DONTWAIT; 4007 struct scsi_address ap; 4008 size_t senselength; 4009 ddi_dma_attr_t ext_arq_dma_attr; 4010 uint_t cookiec; 4011 4012 NDBG3(("mptsas_pkt_alloc_extern: " 4013 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x", 4014 (void *)cmd, cmdlen, tgtlen, statuslen, kf)); 4015 4016 tgt = cdbp = scbp = NULL; 4017 cmd->cmd_scblen = statuslen; 4018 cmd->cmd_privlen = (uchar_t)tgtlen; 4019 4020 if (cmdlen > sizeof (cmd->cmd_cdb)) { 4021 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) { 4022 goto fail; 4023 } 4024 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp; 4025 cmd->cmd_flags |= CFLAG_CDBEXTERN; 4026 } 4027 if (tgtlen > PKT_PRIV_LEN) { 4028 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) { 4029 goto fail; 4030 } 4031 cmd->cmd_flags |= CFLAG_PRIVEXTERN; 4032 cmd->cmd_pkt->pkt_private = tgt; 4033 } 4034 if (statuslen > EXTCMDS_STATUS_SIZE) { 4035 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) { 4036 goto fail; 4037 } 4038 cmd->cmd_flags |= CFLAG_SCBEXTERN; 4039 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp; 4040 4041 /* allocate sense data buf for DMA */ 4042 4043 senselength = statuslen - MPTSAS_GET_ITEM_OFF( 4044 struct scsi_arq_status, sts_sensedata); 4045 cmd->cmd_rqslen = (uchar_t)senselength; 4046 4047 ap.a_hba_tran = mpt->m_tran; 4048 ap.a_target = 0; 4049 ap.a_lun = 0; 4050 4051 cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap, 4052 (struct buf *)NULL, senselength, B_READ, 4053 callback, NULL); 4054 4055 if (cmd->cmd_ext_arq_buf == NULL) { 4056 goto fail; 4057 } 4058 /* 4059 * allocate a extern arq handle and bind the buf 4060 */ 4061 ext_arq_dma_attr = mpt->m_msg_dma_attr; 4062 ext_arq_dma_attr.dma_attr_sgllen = 1; 4063 if ((ddi_dma_alloc_handle(mpt->m_dip, 4064 &ext_arq_dma_attr, callback, 4065 NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) { 4066 goto fail; 4067 } 4068 4069 if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle, 4070 cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT), 4071 callback, NULL, &cmd->cmd_ext_arqcookie, 4072 &cookiec) 4073 != DDI_SUCCESS) { 4074 goto fail; 4075 } 4076 cmd->cmd_flags |= CFLAG_EXTARQBUFVALID; 4077 } 4078 return (0); 4079 fail: 4080 mptsas_pkt_destroy_extern(mpt, cmd); 4081 return (1); 4082 } 4083 4084 /* 4085 * deallocate external pkt space and deallocate the pkt 4086 */ 4087 static void 4088 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd) 4089 { 4090 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd)); 4091 4092 if (cmd->cmd_flags & CFLAG_FREE) { 4093 mptsas_log(mpt, CE_PANIC, 4094 "mptsas_pkt_destroy_extern: freeing free packet"); 4095 _NOTE(NOT_REACHED) 4096 /* NOTREACHED */ 4097 } 4098 if (cmd->cmd_flags & CFLAG_CDBEXTERN) { 4099 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen); 4100 } 4101 if (cmd->cmd_flags & CFLAG_SCBEXTERN) { 4102 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen); 4103 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) { 4104 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle); 4105 } 4106 if (cmd->cmd_ext_arqhandle) { 4107 ddi_dma_free_handle(&cmd->cmd_ext_arqhandle); 4108 cmd->cmd_ext_arqhandle = NULL; 4109 } 4110 if (cmd->cmd_ext_arq_buf) 4111 scsi_free_consistent_buf(cmd->cmd_ext_arq_buf); 4112 } 4113 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) { 4114 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen); 4115 } 4116 cmd->cmd_flags = CFLAG_FREE; 4117 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4118 } 4119 4120 /* 4121 * tran_sync_pkt(9E) - explicit DMA synchronization 4122 */ 4123 /*ARGSUSED*/ 4124 static void 4125 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4126 { 4127 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4128 4129 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p", 4130 ap->a_target, (void *)pkt)); 4131 4132 if (cmd->cmd_dmahandle) { 4133 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4134 (cmd->cmd_flags & CFLAG_DMASEND) ? 4135 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 4136 } 4137 } 4138 4139 /* 4140 * tran_dmafree(9E) - deallocate DMA resources allocated for command 4141 */ 4142 /*ARGSUSED*/ 4143 static void 4144 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 4145 { 4146 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4147 mptsas_t *mpt = ADDR2MPT(ap); 4148 4149 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p", 4150 ap->a_target, (void *)pkt)); 4151 4152 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4153 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4154 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4155 } 4156 4157 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) { 4158 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle); 4159 cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID; 4160 } 4161 4162 mptsas_free_extra_sgl_frame(mpt, cmd); 4163 } 4164 4165 static void 4166 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd) 4167 { 4168 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 4169 (!(cmd->cmd_flags & CFLAG_DMASEND))) { 4170 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4171 DDI_DMA_SYNC_FORCPU); 4172 } 4173 (*pkt->pkt_comp)(pkt); 4174 } 4175 4176 static void 4177 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control, 4178 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4179 { 4180 uint_t cookiec; 4181 mptti_t *dmap; 4182 uint32_t flags; 4183 pMpi2SGESimple64_t sge; 4184 pMpi2SGEChain64_t sgechain; 4185 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID); 4186 4187 /* 4188 * Save the number of entries in the DMA 4189 * Scatter/Gather list 4190 */ 4191 cookiec = cmd->cmd_cookiec; 4192 4193 NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec)); 4194 4195 /* 4196 * Set read/write bit in control. 4197 */ 4198 if (cmd->cmd_flags & CFLAG_DMASEND) { 4199 *control |= MPI2_SCSIIO_CONTROL_WRITE; 4200 } else { 4201 *control |= MPI2_SCSIIO_CONTROL_READ; 4202 } 4203 4204 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount); 4205 4206 /* 4207 * We have 2 cases here. First where we can fit all the 4208 * SG elements into the main frame, and the case 4209 * where we can't. 4210 * If we have more cookies than we can attach to a frame 4211 * we will need to use a chain element to point 4212 * a location of memory where the rest of the S/G 4213 * elements reside. 4214 */ 4215 if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) { 4216 dmap = cmd->cmd_sg; 4217 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4218 while (cookiec--) { 4219 ddi_put32(acc_hdl, 4220 &sge->Address.Low, dmap->addr.address64.Low); 4221 ddi_put32(acc_hdl, 4222 &sge->Address.High, dmap->addr.address64.High); 4223 ddi_put32(acc_hdl, &sge->FlagsLength, 4224 dmap->count); 4225 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4226 flags |= ((uint32_t) 4227 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4228 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4229 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4230 MPI2_SGE_FLAGS_SHIFT); 4231 4232 /* 4233 * If this is the last cookie, we set the flags 4234 * to indicate so 4235 */ 4236 if (cookiec == 0) { 4237 flags |= 4238 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT 4239 | MPI2_SGE_FLAGS_END_OF_BUFFER 4240 | MPI2_SGE_FLAGS_END_OF_LIST) << 4241 MPI2_SGE_FLAGS_SHIFT); 4242 } 4243 if (cmd->cmd_flags & CFLAG_DMASEND) { 4244 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC << 4245 MPI2_SGE_FLAGS_SHIFT); 4246 } else { 4247 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST << 4248 MPI2_SGE_FLAGS_SHIFT); 4249 } 4250 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4251 dmap++; 4252 sge++; 4253 } 4254 } else { 4255 /* 4256 * Hereby we start to deal with multiple frames. 4257 * The process is as follows: 4258 * 1. Determine how many frames are needed for SGL element 4259 * storage; Note that all frames are stored in contiguous 4260 * memory space and in 64-bit DMA mode each element is 4261 * 3 double-words (12 bytes) long. 4262 * 2. Fill up the main frame. We need to do this separately 4263 * since it contains the SCSI IO request header and needs 4264 * dedicated processing. Note that the last 4 double-words 4265 * of the SCSI IO header is for SGL element storage 4266 * (MPI2_SGE_IO_UNION). 4267 * 3. Fill the chain element in the main frame, so the DMA 4268 * engine can use the following frames. 4269 * 4. Enter a loop to fill the remaining frames. Note that the 4270 * last frame contains no chain element. The remaining 4271 * frames go into the mpt SGL buffer allocated on the fly, 4272 * not immediately following the main message frame, as in 4273 * Gen1. 4274 * Some restrictions: 4275 * 1. For 64-bit DMA, the simple element and chain element 4276 * are both of 3 double-words (12 bytes) in size, even 4277 * though all frames are stored in the first 4G of mem 4278 * range and the higher 32-bits of the address are always 0. 4279 * 2. On some controllers (like the 1064/1068), a frame can 4280 * hold SGL elements with the last 1 or 2 double-words 4281 * (4 or 8 bytes) un-used. On these controllers, we should 4282 * recognize that there's not enough room for another SGL 4283 * element and move the sge pointer to the next frame. 4284 */ 4285 int i, j, k, l, frames, sgemax; 4286 int temp; 4287 uint8_t chainflags; 4288 uint16_t chainlength; 4289 mptsas_cache_frames_t *p; 4290 4291 /* 4292 * Sgemax is the number of SGE's that will fit 4293 * each extra frame and frames is total 4294 * number of frames we'll need. 1 sge entry per 4295 * frame is reseverd for the chain element thus the -1 below. 4296 */ 4297 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) 4298 - 1); 4299 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4300 4301 /* 4302 * A little check to see if we need to round up the number 4303 * of frames we need 4304 */ 4305 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4306 sgemax) > 1) { 4307 frames = (temp + 1); 4308 } else { 4309 frames = temp; 4310 } 4311 dmap = cmd->cmd_sg; 4312 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4313 4314 /* 4315 * First fill in the main frame 4316 */ 4317 for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) { 4318 ddi_put32(acc_hdl, &sge->Address.Low, 4319 dmap->addr.address64.Low); 4320 ddi_put32(acc_hdl, &sge->Address.High, 4321 dmap->addr.address64.High); 4322 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count); 4323 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4324 flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4325 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4326 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4327 MPI2_SGE_FLAGS_SHIFT); 4328 4329 /* 4330 * If this is the last SGE of this frame 4331 * we set the end of list flag 4332 */ 4333 if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) { 4334 flags |= ((uint32_t) 4335 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4336 MPI2_SGE_FLAGS_SHIFT); 4337 } 4338 if (cmd->cmd_flags & CFLAG_DMASEND) { 4339 flags |= 4340 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4341 MPI2_SGE_FLAGS_SHIFT); 4342 } else { 4343 flags |= 4344 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4345 MPI2_SGE_FLAGS_SHIFT); 4346 } 4347 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4348 dmap++; 4349 sge++; 4350 } 4351 4352 /* 4353 * Fill in the chain element in the main frame. 4354 * About calculation on ChainOffset: 4355 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4356 * in the end reserved for SGL element storage 4357 * (MPI2_SGE_IO_UNION); we should count it in our 4358 * calculation. See its definition in the header file. 4359 * 2. Constant j is the counter of the current SGL element 4360 * that will be processed, and (j - 1) is the number of 4361 * SGL elements that have been processed (stored in the 4362 * main frame). 4363 * 3. ChainOffset value should be in units of double-words (4 4364 * bytes) so the last value should be divided by 4. 4365 */ 4366 ddi_put8(acc_hdl, &frame->ChainOffset, 4367 (sizeof (MPI2_SCSI_IO_REQUEST) - 4368 sizeof (MPI2_SGE_IO_UNION) + 4369 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4370 sgechain = (pMpi2SGEChain64_t)sge; 4371 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4372 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4373 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4374 ddi_put8(acc_hdl, &sgechain->Flags, chainflags); 4375 4376 /* 4377 * The size of the next frame is the accurate size of space 4378 * (in bytes) used to store the SGL elements. j is the counter 4379 * of SGL elements. (j - 1) is the number of SGL elements that 4380 * have been processed (stored in frames). 4381 */ 4382 if (frames >= 2) { 4383 chainlength = mpt->m_req_frame_size / 4384 sizeof (MPI2_SGE_SIMPLE64) * 4385 sizeof (MPI2_SGE_SIMPLE64); 4386 } else { 4387 chainlength = ((cookiec - (j - 1)) * 4388 sizeof (MPI2_SGE_SIMPLE64)); 4389 } 4390 4391 p = cmd->cmd_extra_frames; 4392 4393 ddi_put16(acc_hdl, &sgechain->Length, chainlength); 4394 ddi_put32(acc_hdl, &sgechain->Address.Low, 4395 p->m_phys_addr); 4396 /* SGL is allocated in the first 4G mem range */ 4397 ddi_put32(acc_hdl, &sgechain->Address.High, 0); 4398 4399 /* 4400 * If there are more than 2 frames left we have to 4401 * fill in the next chain offset to the location of 4402 * the chain element in the next frame. 4403 * sgemax is the number of simple elements in an extra 4404 * frame. Note that the value NextChainOffset should be 4405 * in double-words (4 bytes). 4406 */ 4407 if (frames >= 2) { 4408 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 4409 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4410 } else { 4411 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0); 4412 } 4413 4414 /* 4415 * Jump to next frame; 4416 * Starting here, chain buffers go into the per command SGL. 4417 * This buffer is allocated when chain buffers are needed. 4418 */ 4419 sge = (pMpi2SGESimple64_t)p->m_frames_addr; 4420 i = cookiec; 4421 4422 /* 4423 * Start filling in frames with SGE's. If we 4424 * reach the end of frame and still have SGE's 4425 * to fill we need to add a chain element and 4426 * use another frame. j will be our counter 4427 * for what cookie we are at and i will be 4428 * the total cookiec. k is the current frame 4429 */ 4430 for (k = 1; k <= frames; k++) { 4431 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4432 4433 /* 4434 * If we have reached the end of frame 4435 * and we have more SGE's to fill in 4436 * we have to fill the final entry 4437 * with a chain element and then 4438 * continue to the next frame 4439 */ 4440 if ((l == (sgemax + 1)) && (k != frames)) { 4441 sgechain = (pMpi2SGEChain64_t)sge; 4442 j--; 4443 chainflags = ( 4444 MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4445 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4446 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4447 ddi_put8(p->m_acc_hdl, 4448 &sgechain->Flags, chainflags); 4449 /* 4450 * k is the frame counter and (k + 1) 4451 * is the number of the next frame. 4452 * Note that frames are in contiguous 4453 * memory space. 4454 */ 4455 ddi_put32(p->m_acc_hdl, 4456 &sgechain->Address.Low, 4457 (p->m_phys_addr + 4458 (mpt->m_req_frame_size * k))); 4459 ddi_put32(p->m_acc_hdl, 4460 &sgechain->Address.High, 0); 4461 4462 /* 4463 * If there are more than 2 frames left 4464 * we have to next chain offset to 4465 * the location of the chain element 4466 * in the next frame and fill in the 4467 * length of the next chain 4468 */ 4469 if ((frames - k) >= 2) { 4470 ddi_put8(p->m_acc_hdl, 4471 &sgechain->NextChainOffset, 4472 (sgemax * 4473 sizeof (MPI2_SGE_SIMPLE64)) 4474 >> 2); 4475 ddi_put16(p->m_acc_hdl, 4476 &sgechain->Length, 4477 mpt->m_req_frame_size / 4478 sizeof (MPI2_SGE_SIMPLE64) * 4479 sizeof (MPI2_SGE_SIMPLE64)); 4480 } else { 4481 /* 4482 * This is the last frame. Set 4483 * the NextChainOffset to 0 and 4484 * Length is the total size of 4485 * all remaining simple elements 4486 */ 4487 ddi_put8(p->m_acc_hdl, 4488 &sgechain->NextChainOffset, 4489 0); 4490 ddi_put16(p->m_acc_hdl, 4491 &sgechain->Length, 4492 (cookiec - j) * 4493 sizeof (MPI2_SGE_SIMPLE64)); 4494 } 4495 4496 /* Jump to the next frame */ 4497 sge = (pMpi2SGESimple64_t) 4498 ((char *)p->m_frames_addr + 4499 (int)mpt->m_req_frame_size * k); 4500 4501 continue; 4502 } 4503 4504 ddi_put32(p->m_acc_hdl, 4505 &sge->Address.Low, 4506 dmap->addr.address64.Low); 4507 ddi_put32(p->m_acc_hdl, 4508 &sge->Address.High, 4509 dmap->addr.address64.High); 4510 ddi_put32(p->m_acc_hdl, 4511 &sge->FlagsLength, dmap->count); 4512 flags = ddi_get32(p->m_acc_hdl, 4513 &sge->FlagsLength); 4514 flags |= ((uint32_t)( 4515 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4516 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4517 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4518 MPI2_SGE_FLAGS_SHIFT); 4519 4520 /* 4521 * If we are at the end of the frame and 4522 * there is another frame to fill in 4523 * we set the last simple element as last 4524 * element 4525 */ 4526 if ((l == sgemax) && (k != frames)) { 4527 flags |= ((uint32_t) 4528 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4529 MPI2_SGE_FLAGS_SHIFT); 4530 } 4531 4532 /* 4533 * If this is the final cookie we 4534 * indicate it by setting the flags 4535 */ 4536 if (j == i) { 4537 flags |= ((uint32_t) 4538 (MPI2_SGE_FLAGS_LAST_ELEMENT | 4539 MPI2_SGE_FLAGS_END_OF_BUFFER | 4540 MPI2_SGE_FLAGS_END_OF_LIST) << 4541 MPI2_SGE_FLAGS_SHIFT); 4542 } 4543 if (cmd->cmd_flags & CFLAG_DMASEND) { 4544 flags |= 4545 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4546 MPI2_SGE_FLAGS_SHIFT); 4547 } else { 4548 flags |= 4549 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4550 MPI2_SGE_FLAGS_SHIFT); 4551 } 4552 ddi_put32(p->m_acc_hdl, 4553 &sge->FlagsLength, flags); 4554 dmap++; 4555 sge++; 4556 } 4557 } 4558 4559 /* 4560 * Sync DMA with the chain buffers that were just created 4561 */ 4562 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 4563 } 4564 } 4565 4566 /* 4567 * Interrupt handling 4568 * Utility routine. Poll for status of a command sent to HBA 4569 * without interrupts (a FLAG_NOINTR command). 4570 */ 4571 int 4572 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime) 4573 { 4574 int rval = TRUE; 4575 4576 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd)); 4577 4578 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 4579 mptsas_restart_hba(mpt); 4580 } 4581 4582 /* 4583 * Wait, using drv_usecwait(), long enough for the command to 4584 * reasonably return from the target if the target isn't 4585 * "dead". A polled command may well be sent from scsi_poll, and 4586 * there are retries built in to scsi_poll if the transport 4587 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second 4588 * and retries the transport up to scsi_poll_busycnt times 4589 * (currently 60) if 4590 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or 4591 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY 4592 * 4593 * limit the waiting to avoid a hang in the event that the 4594 * cmd never gets started but we are still receiving interrupts 4595 */ 4596 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) { 4597 if (mptsas_wait_intr(mpt, polltime) == FALSE) { 4598 NDBG5(("mptsas_poll: command incomplete")); 4599 rval = FALSE; 4600 break; 4601 } 4602 } 4603 4604 if (rval == FALSE) { 4605 4606 /* 4607 * this isn't supposed to happen, the hba must be wedged 4608 * Mark this cmd as a timeout. 4609 */ 4610 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT, 4611 (STAT_TIMEOUT|STAT_ABORTED)); 4612 4613 if (poll_cmd->cmd_queued == FALSE) { 4614 4615 NDBG5(("mptsas_poll: not on waitq")); 4616 4617 poll_cmd->cmd_pkt->pkt_state |= 4618 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD); 4619 } else { 4620 4621 /* find and remove it from the waitq */ 4622 NDBG5(("mptsas_poll: delete from waitq")); 4623 mptsas_waitq_delete(mpt, poll_cmd); 4624 } 4625 4626 } 4627 mptsas_fma_check(mpt, poll_cmd); 4628 NDBG5(("mptsas_poll: done")); 4629 return (rval); 4630 } 4631 4632 /* 4633 * Used for polling cmds and TM function 4634 */ 4635 static int 4636 mptsas_wait_intr(mptsas_t *mpt, int polltime) 4637 { 4638 int cnt; 4639 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 4640 uint32_t int_mask; 4641 4642 NDBG5(("mptsas_wait_intr")); 4643 4644 mpt->m_polled_intr = 1; 4645 4646 /* 4647 * Get the current interrupt mask and disable interrupts. When 4648 * re-enabling ints, set mask to saved value. 4649 */ 4650 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask); 4651 MPTSAS_DISABLE_INTR(mpt); 4652 4653 /* 4654 * Keep polling for at least (polltime * 1000) seconds 4655 */ 4656 for (cnt = 0; cnt < polltime; cnt++) { 4657 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 4658 DDI_DMA_SYNC_FORCPU); 4659 4660 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 4661 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 4662 4663 if (ddi_get32(mpt->m_acc_post_queue_hdl, 4664 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 4665 ddi_get32(mpt->m_acc_post_queue_hdl, 4666 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 4667 drv_usecwait(1000); 4668 continue; 4669 } 4670 4671 /* 4672 * The reply is valid, process it according to its 4673 * type. 4674 */ 4675 mptsas_process_intr(mpt, reply_desc_union); 4676 4677 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 4678 mpt->m_post_index = 0; 4679 } 4680 4681 /* 4682 * Update the global reply index 4683 */ 4684 ddi_put32(mpt->m_datap, 4685 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 4686 mpt->m_polled_intr = 0; 4687 4688 /* 4689 * Re-enable interrupts and quit. 4690 */ 4691 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, 4692 int_mask); 4693 return (TRUE); 4694 4695 } 4696 4697 /* 4698 * Clear polling flag, re-enable interrupts and quit. 4699 */ 4700 mpt->m_polled_intr = 0; 4701 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask); 4702 return (FALSE); 4703 } 4704 4705 static void 4706 mptsas_handle_scsi_io_success(mptsas_t *mpt, 4707 pMpi2ReplyDescriptorsUnion_t reply_desc) 4708 { 4709 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success; 4710 uint16_t SMID; 4711 mptsas_slots_t *slots = mpt->m_active; 4712 mptsas_cmd_t *cmd = NULL; 4713 struct scsi_pkt *pkt; 4714 4715 ASSERT(mutex_owned(&mpt->m_mutex)); 4716 4717 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc; 4718 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID); 4719 4720 /* 4721 * This is a success reply so just complete the IO. First, do a sanity 4722 * check on the SMID. The final slot is used for TM requests, which 4723 * would not come into this reply handler. 4724 */ 4725 if ((SMID == 0) || (SMID > slots->m_n_normal)) { 4726 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 4727 SMID); 4728 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4729 return; 4730 } 4731 4732 cmd = slots->m_slot[SMID]; 4733 4734 /* 4735 * print warning and return if the slot is empty 4736 */ 4737 if (cmd == NULL) { 4738 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 4739 "in slot %d", SMID); 4740 return; 4741 } 4742 4743 pkt = CMD2PKT(cmd); 4744 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 4745 STATE_GOT_STATUS); 4746 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4747 pkt->pkt_state |= STATE_XFERRED_DATA; 4748 } 4749 pkt->pkt_resid = 0; 4750 4751 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 4752 cmd->cmd_flags |= CFLAG_FINISHED; 4753 cv_broadcast(&mpt->m_passthru_cv); 4754 return; 4755 } else { 4756 mptsas_remove_cmd(mpt, cmd); 4757 } 4758 4759 if (cmd->cmd_flags & CFLAG_RETRY) { 4760 /* 4761 * The target returned QFULL or busy, do not add tihs 4762 * pkt to the doneq since the hba will retry 4763 * this cmd. 4764 * 4765 * The pkt has already been resubmitted in 4766 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 4767 * Remove this cmd_flag here. 4768 */ 4769 cmd->cmd_flags &= ~CFLAG_RETRY; 4770 } else { 4771 mptsas_doneq_add(mpt, cmd); 4772 } 4773 } 4774 4775 static void 4776 mptsas_handle_address_reply(mptsas_t *mpt, 4777 pMpi2ReplyDescriptorsUnion_t reply_desc) 4778 { 4779 pMpi2AddressReplyDescriptor_t address_reply; 4780 pMPI2DefaultReply_t reply; 4781 mptsas_fw_diagnostic_buffer_t *pBuffer; 4782 uint32_t reply_addr; 4783 uint16_t SMID, iocstatus; 4784 mptsas_slots_t *slots = mpt->m_active; 4785 mptsas_cmd_t *cmd = NULL; 4786 uint8_t function, buffer_type; 4787 m_replyh_arg_t *args; 4788 int reply_frame_no; 4789 4790 ASSERT(mutex_owned(&mpt->m_mutex)); 4791 4792 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc; 4793 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl, 4794 &address_reply->ReplyFrameAddress); 4795 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID); 4796 4797 /* 4798 * If reply frame is not in the proper range we should ignore this 4799 * message and exit the interrupt handler. 4800 */ 4801 if ((reply_addr < mpt->m_reply_frame_dma_addr) || 4802 (reply_addr >= (mpt->m_reply_frame_dma_addr + 4803 (mpt->m_reply_frame_size * mpt->m_max_replies))) || 4804 ((reply_addr - mpt->m_reply_frame_dma_addr) % 4805 mpt->m_reply_frame_size != 0)) { 4806 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame " 4807 "address 0x%x\n", reply_addr); 4808 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4809 return; 4810 } 4811 4812 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 4813 DDI_DMA_SYNC_FORCPU); 4814 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr - 4815 mpt->m_reply_frame_dma_addr)); 4816 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function); 4817 4818 /* 4819 * don't get slot information and command for events since these values 4820 * don't exist 4821 */ 4822 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) && 4823 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) { 4824 /* 4825 * This could be a TM reply, which use the last allocated SMID, 4826 * so allow for that. 4827 */ 4828 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) { 4829 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of " 4830 "%d\n", SMID); 4831 ddi_fm_service_impact(mpt->m_dip, 4832 DDI_SERVICE_UNAFFECTED); 4833 return; 4834 } 4835 4836 cmd = slots->m_slot[SMID]; 4837 4838 /* 4839 * print warning and return if the slot is empty 4840 */ 4841 if (cmd == NULL) { 4842 mptsas_log(mpt, CE_WARN, "?NULL command for address " 4843 "reply in slot %d", SMID); 4844 return; 4845 } 4846 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 4847 (cmd->cmd_flags & CFLAG_CONFIG) || 4848 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 4849 cmd->cmd_rfm = reply_addr; 4850 cmd->cmd_flags |= CFLAG_FINISHED; 4851 cv_broadcast(&mpt->m_passthru_cv); 4852 cv_broadcast(&mpt->m_config_cv); 4853 cv_broadcast(&mpt->m_fw_diag_cv); 4854 return; 4855 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) { 4856 mptsas_remove_cmd(mpt, cmd); 4857 } 4858 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID)); 4859 } 4860 /* 4861 * Depending on the function, we need to handle 4862 * the reply frame (and cmd) differently. 4863 */ 4864 switch (function) { 4865 case MPI2_FUNCTION_SCSI_IO_REQUEST: 4866 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd); 4867 break; 4868 case MPI2_FUNCTION_SCSI_TASK_MGMT: 4869 cmd->cmd_rfm = reply_addr; 4870 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply, 4871 cmd); 4872 break; 4873 case MPI2_FUNCTION_FW_DOWNLOAD: 4874 cmd->cmd_flags |= CFLAG_FINISHED; 4875 cv_signal(&mpt->m_fw_cv); 4876 break; 4877 case MPI2_FUNCTION_EVENT_NOTIFICATION: 4878 reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) / 4879 mpt->m_reply_frame_size; 4880 args = &mpt->m_replyh_args[reply_frame_no]; 4881 args->mpt = (void *)mpt; 4882 args->rfm = reply_addr; 4883 4884 /* 4885 * Record the event if its type is enabled in 4886 * this mpt instance by ioctl. 4887 */ 4888 mptsas_record_event(args); 4889 4890 /* 4891 * Handle time critical events 4892 * NOT_RESPONDING/ADDED only now 4893 */ 4894 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) { 4895 /* 4896 * Would not return main process, 4897 * just let taskq resolve ack action 4898 * and ack would be sent in taskq thread 4899 */ 4900 NDBG20(("send mptsas_handle_event_sync success")); 4901 } 4902 4903 if (mpt->m_in_reset) { 4904 NDBG20(("dropping event received during reset")); 4905 return; 4906 } 4907 4908 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event, 4909 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 4910 mptsas_log(mpt, CE_WARN, "No memory available" 4911 "for dispatch taskq"); 4912 /* 4913 * Return the reply frame to the free queue. 4914 */ 4915 ddi_put32(mpt->m_acc_free_queue_hdl, 4916 &((uint32_t *)(void *) 4917 mpt->m_free_queue)[mpt->m_free_index], reply_addr); 4918 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 4919 DDI_DMA_SYNC_FORDEV); 4920 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 4921 mpt->m_free_index = 0; 4922 } 4923 4924 ddi_put32(mpt->m_datap, 4925 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index); 4926 } 4927 return; 4928 case MPI2_FUNCTION_DIAG_BUFFER_POST: 4929 /* 4930 * If SMID is 0, this implies that the reply is due to a 4931 * release function with a status that the buffer has been 4932 * released. Set the buffer flags accordingly. 4933 */ 4934 if (SMID == 0) { 4935 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 4936 &reply->IOCStatus); 4937 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl, 4938 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType)); 4939 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) { 4940 pBuffer = 4941 &mpt->m_fw_diag_buffer_list[buffer_type]; 4942 pBuffer->valid_data = TRUE; 4943 pBuffer->owned_by_firmware = FALSE; 4944 pBuffer->immediate = FALSE; 4945 } 4946 } else { 4947 /* 4948 * Normal handling of diag post reply with SMID. 4949 */ 4950 cmd = slots->m_slot[SMID]; 4951 4952 /* 4953 * print warning and return if the slot is empty 4954 */ 4955 if (cmd == NULL) { 4956 mptsas_log(mpt, CE_WARN, "?NULL command for " 4957 "address reply in slot %d", SMID); 4958 return; 4959 } 4960 cmd->cmd_rfm = reply_addr; 4961 cmd->cmd_flags |= CFLAG_FINISHED; 4962 cv_broadcast(&mpt->m_fw_diag_cv); 4963 } 4964 return; 4965 default: 4966 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function); 4967 break; 4968 } 4969 4970 /* 4971 * Return the reply frame to the free queue. 4972 */ 4973 ddi_put32(mpt->m_acc_free_queue_hdl, 4974 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 4975 reply_addr); 4976 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 4977 DDI_DMA_SYNC_FORDEV); 4978 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 4979 mpt->m_free_index = 0; 4980 } 4981 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 4982 mpt->m_free_index); 4983 4984 if (cmd->cmd_flags & CFLAG_FW_CMD) 4985 return; 4986 4987 if (cmd->cmd_flags & CFLAG_RETRY) { 4988 /* 4989 * The target returned QFULL or busy, do not add tihs 4990 * pkt to the doneq since the hba will retry 4991 * this cmd. 4992 * 4993 * The pkt has already been resubmitted in 4994 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 4995 * Remove this cmd_flag here. 4996 */ 4997 cmd->cmd_flags &= ~CFLAG_RETRY; 4998 } else { 4999 mptsas_doneq_add(mpt, cmd); 5000 } 5001 } 5002 5003 static void 5004 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 5005 mptsas_cmd_t *cmd) 5006 { 5007 uint8_t scsi_status, scsi_state; 5008 uint16_t ioc_status; 5009 uint32_t xferred, sensecount, responsedata, loginfo = 0; 5010 struct scsi_pkt *pkt; 5011 struct scsi_arq_status *arqstat; 5012 struct buf *bp; 5013 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5014 uint8_t *sensedata = NULL; 5015 5016 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) == 5017 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) { 5018 bp = cmd->cmd_ext_arq_buf; 5019 } else { 5020 bp = cmd->cmd_arq_buf; 5021 } 5022 5023 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus); 5024 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5025 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState); 5026 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount); 5027 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount); 5028 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl, 5029 &reply->ResponseInfo); 5030 5031 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 5032 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 5033 &reply->IOCLogInfo); 5034 mptsas_log(mpt, CE_NOTE, 5035 "?Log info 0x%x received for target %d.\n" 5036 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5037 loginfo, Tgt(cmd), scsi_status, ioc_status, 5038 scsi_state); 5039 } 5040 5041 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5042 scsi_status, ioc_status, scsi_state)); 5043 5044 pkt = CMD2PKT(cmd); 5045 *(pkt->pkt_scbp) = scsi_status; 5046 5047 if (loginfo == 0x31170000) { 5048 /* 5049 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY 5050 * 0x31170000 comes, that means the device missing delay 5051 * is in progressing, the command need retry later. 5052 */ 5053 *(pkt->pkt_scbp) = STATUS_BUSY; 5054 return; 5055 } 5056 5057 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) && 5058 ((ioc_status & MPI2_IOCSTATUS_MASK) == 5059 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) { 5060 pkt->pkt_reason = CMD_INCOMPLETE; 5061 pkt->pkt_state |= STATE_GOT_BUS; 5062 if (ptgt->m_reset_delay == 0) { 5063 mptsas_set_throttle(mpt, ptgt, 5064 DRAIN_THROTTLE); 5065 } 5066 return; 5067 } 5068 5069 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) { 5070 responsedata &= 0x000000FF; 5071 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) { 5072 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n"); 5073 pkt->pkt_reason = CMD_TLR_OFF; 5074 return; 5075 } 5076 } 5077 5078 5079 switch (scsi_status) { 5080 case MPI2_SCSI_STATUS_CHECK_CONDITION: 5081 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5082 arqstat = (void*)(pkt->pkt_scbp); 5083 arqstat->sts_rqpkt_status = *((struct scsi_status *) 5084 (pkt->pkt_scbp)); 5085 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 5086 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE); 5087 if (cmd->cmd_flags & CFLAG_XARQ) { 5088 pkt->pkt_state |= STATE_XARQ_DONE; 5089 } 5090 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5091 pkt->pkt_state |= STATE_XFERRED_DATA; 5092 } 5093 arqstat->sts_rqpkt_reason = pkt->pkt_reason; 5094 arqstat->sts_rqpkt_state = pkt->pkt_state; 5095 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA; 5096 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics; 5097 sensedata = (uint8_t *)&arqstat->sts_sensedata; 5098 5099 bcopy((uchar_t *)bp->b_un.b_addr, sensedata, 5100 ((cmd->cmd_rqslen >= sensecount) ? sensecount : 5101 cmd->cmd_rqslen)); 5102 arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount); 5103 cmd->cmd_flags |= CFLAG_CMDARQ; 5104 /* 5105 * Set proper status for pkt if autosense was valid 5106 */ 5107 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { 5108 struct scsi_status zero_status = { 0 }; 5109 arqstat->sts_rqpkt_status = zero_status; 5110 } 5111 5112 /* 5113 * ASC=0x47 is parity error 5114 * ASC=0x48 is initiator detected error received 5115 */ 5116 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) && 5117 ((scsi_sense_asc(sensedata) == 0x47) || 5118 (scsi_sense_asc(sensedata) == 0x48))) { 5119 mptsas_log(mpt, CE_NOTE, "Aborted_command!"); 5120 } 5121 5122 /* 5123 * ASC/ASCQ=0x3F/0x0E means report_luns data changed 5124 * ASC/ASCQ=0x25/0x00 means invalid lun 5125 */ 5126 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) && 5127 (scsi_sense_asc(sensedata) == 0x3F) && 5128 (scsi_sense_ascq(sensedata) == 0x0E)) || 5129 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) && 5130 (scsi_sense_asc(sensedata) == 0x25) && 5131 (scsi_sense_ascq(sensedata) == 0x00))) { 5132 mptsas_topo_change_list_t *topo_node = NULL; 5133 5134 topo_node = kmem_zalloc( 5135 sizeof (mptsas_topo_change_list_t), 5136 KM_NOSLEEP); 5137 if (topo_node == NULL) { 5138 mptsas_log(mpt, CE_NOTE, "No memory" 5139 "resource for handle SAS dynamic" 5140 "reconfigure.\n"); 5141 break; 5142 } 5143 topo_node->mpt = mpt; 5144 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET; 5145 topo_node->un.phymask = ptgt->m_addr.mta_phymask; 5146 topo_node->devhdl = ptgt->m_devhdl; 5147 topo_node->object = (void *)ptgt; 5148 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED; 5149 5150 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 5151 mptsas_handle_dr, 5152 (void *)topo_node, 5153 DDI_NOSLEEP)) != DDI_SUCCESS) { 5154 mptsas_log(mpt, CE_NOTE, "mptsas start taskq" 5155 "for handle SAS dynamic reconfigure" 5156 "failed. \n"); 5157 } 5158 } 5159 break; 5160 case MPI2_SCSI_STATUS_GOOD: 5161 switch (ioc_status & MPI2_IOCSTATUS_MASK) { 5162 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 5163 pkt->pkt_reason = CMD_DEV_GONE; 5164 pkt->pkt_state |= STATE_GOT_BUS; 5165 if (ptgt->m_reset_delay == 0) { 5166 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5167 } 5168 NDBG31(("lost disk for target%d, command:%x", 5169 Tgt(cmd), pkt->pkt_cdbp[0])); 5170 break; 5171 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 5172 NDBG31(("data overrun: xferred=%d", xferred)); 5173 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5174 pkt->pkt_reason = CMD_DATA_OVR; 5175 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5176 | STATE_SENT_CMD | STATE_GOT_STATUS 5177 | STATE_XFERRED_DATA); 5178 pkt->pkt_resid = 0; 5179 break; 5180 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 5181 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 5182 NDBG31(("data underrun: xferred=%d", xferred)); 5183 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5184 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5185 | STATE_SENT_CMD | STATE_GOT_STATUS); 5186 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5187 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5188 pkt->pkt_state |= STATE_XFERRED_DATA; 5189 } 5190 break; 5191 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 5192 mptsas_set_pkt_reason(mpt, 5193 cmd, CMD_RESET, STAT_BUS_RESET); 5194 break; 5195 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 5196 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 5197 mptsas_set_pkt_reason(mpt, 5198 cmd, CMD_RESET, STAT_DEV_RESET); 5199 break; 5200 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 5201 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 5202 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET); 5203 mptsas_set_pkt_reason(mpt, 5204 cmd, CMD_TERMINATED, STAT_TERMINATED); 5205 break; 5206 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 5207 case MPI2_IOCSTATUS_BUSY: 5208 /* 5209 * set throttles to drain 5210 */ 5211 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 5212 ptgt = refhash_next(mpt->m_targets, ptgt)) { 5213 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5214 } 5215 5216 /* 5217 * retry command 5218 */ 5219 cmd->cmd_flags |= CFLAG_RETRY; 5220 cmd->cmd_pkt_flags |= FLAG_HEAD; 5221 5222 (void) mptsas_accept_pkt(mpt, cmd); 5223 break; 5224 default: 5225 mptsas_log(mpt, CE_WARN, 5226 "unknown ioc_status = %x\n", ioc_status); 5227 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer " 5228 "count = %x, scsi_status = %x", scsi_state, 5229 xferred, scsi_status); 5230 break; 5231 } 5232 break; 5233 case MPI2_SCSI_STATUS_TASK_SET_FULL: 5234 mptsas_handle_qfull(mpt, cmd); 5235 break; 5236 case MPI2_SCSI_STATUS_BUSY: 5237 NDBG31(("scsi_status busy received")); 5238 break; 5239 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT: 5240 NDBG31(("scsi_status reservation conflict received")); 5241 break; 5242 default: 5243 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n", 5244 scsi_status, ioc_status); 5245 mptsas_log(mpt, CE_WARN, 5246 "mptsas_process_intr: invalid scsi status\n"); 5247 break; 5248 } 5249 } 5250 5251 static void 5252 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply, 5253 mptsas_cmd_t *cmd) 5254 { 5255 uint8_t task_type; 5256 uint16_t ioc_status; 5257 uint32_t log_info; 5258 uint16_t dev_handle; 5259 struct scsi_pkt *pkt = CMD2PKT(cmd); 5260 5261 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType); 5262 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5263 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo); 5264 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle); 5265 5266 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5267 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x " 5268 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n", 5269 task_type, ioc_status, log_info, dev_handle); 5270 pkt->pkt_reason = CMD_INCOMPLETE; 5271 return; 5272 } 5273 5274 switch (task_type) { 5275 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 5276 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 5277 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 5278 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA: 5279 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET: 5280 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION: 5281 break; 5282 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 5283 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 5284 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 5285 /* 5286 * Check for invalid DevHandle of 0 in case application 5287 * sends bad command. DevHandle of 0 could cause problems. 5288 */ 5289 if (dev_handle == 0) { 5290 mptsas_log(mpt, CE_WARN, "!Can't flush target with" 5291 " DevHandle of 0."); 5292 } else { 5293 mptsas_flush_target(mpt, dev_handle, Lun(cmd), 5294 task_type); 5295 } 5296 break; 5297 default: 5298 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 5299 task_type); 5300 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status); 5301 break; 5302 } 5303 } 5304 5305 static void 5306 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg) 5307 { 5308 mptsas_t *mpt = arg->mpt; 5309 uint64_t t = arg->t; 5310 mptsas_cmd_t *cmd; 5311 struct scsi_pkt *pkt; 5312 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 5313 5314 mutex_enter(&item->mutex); 5315 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) { 5316 if (!item->doneq) { 5317 cv_wait(&item->cv, &item->mutex); 5318 } 5319 pkt = NULL; 5320 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) { 5321 cmd->cmd_flags |= CFLAG_COMPLETED; 5322 pkt = CMD2PKT(cmd); 5323 } 5324 mutex_exit(&item->mutex); 5325 if (pkt) { 5326 mptsas_pkt_comp(pkt, cmd); 5327 } 5328 mutex_enter(&item->mutex); 5329 } 5330 mutex_exit(&item->mutex); 5331 mutex_enter(&mpt->m_doneq_mutex); 5332 mpt->m_doneq_thread_n--; 5333 cv_broadcast(&mpt->m_doneq_thread_cv); 5334 mutex_exit(&mpt->m_doneq_mutex); 5335 } 5336 5337 5338 /* 5339 * mpt interrupt handler. 5340 */ 5341 static uint_t 5342 mptsas_intr(caddr_t arg1, caddr_t arg2) 5343 { 5344 mptsas_t *mpt = (void *)arg1; 5345 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5346 uchar_t did_reply = FALSE; 5347 5348 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2)); 5349 5350 mutex_enter(&mpt->m_mutex); 5351 5352 /* 5353 * If interrupts are shared by two channels then check whether this 5354 * interrupt is genuinely for this channel by making sure first the 5355 * chip is in high power state. 5356 */ 5357 if ((mpt->m_options & MPTSAS_OPT_PM) && 5358 (mpt->m_power_level != PM_LEVEL_D0)) { 5359 mutex_exit(&mpt->m_mutex); 5360 return (DDI_INTR_UNCLAIMED); 5361 } 5362 5363 /* 5364 * If polling, interrupt was triggered by some shared interrupt because 5365 * IOC interrupts are disabled during polling, so polling routine will 5366 * handle any replies. Considering this, if polling is happening, 5367 * return with interrupt unclaimed. 5368 */ 5369 if (mpt->m_polled_intr) { 5370 mutex_exit(&mpt->m_mutex); 5371 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt"); 5372 return (DDI_INTR_UNCLAIMED); 5373 } 5374 5375 /* 5376 * Read the istat register. 5377 */ 5378 if ((INTPENDING(mpt)) != 0) { 5379 /* 5380 * read fifo until empty. 5381 */ 5382 #ifndef __lock_lint 5383 _NOTE(CONSTCOND) 5384 #endif 5385 while (TRUE) { 5386 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5387 DDI_DMA_SYNC_FORCPU); 5388 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5389 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5390 5391 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5392 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5393 ddi_get32(mpt->m_acc_post_queue_hdl, 5394 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5395 break; 5396 } 5397 5398 /* 5399 * The reply is valid, process it according to its 5400 * type. Also, set a flag for updating the reply index 5401 * after they've all been processed. 5402 */ 5403 did_reply = TRUE; 5404 5405 mptsas_process_intr(mpt, reply_desc_union); 5406 5407 /* 5408 * Increment post index and roll over if needed. 5409 */ 5410 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5411 mpt->m_post_index = 0; 5412 } 5413 } 5414 5415 /* 5416 * Update the global reply index if at least one reply was 5417 * processed. 5418 */ 5419 if (did_reply) { 5420 ddi_put32(mpt->m_datap, 5421 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5422 } 5423 } else { 5424 mutex_exit(&mpt->m_mutex); 5425 return (DDI_INTR_UNCLAIMED); 5426 } 5427 NDBG1(("mptsas_intr complete")); 5428 5429 /* 5430 * If no helper threads are created, process the doneq in ISR. If 5431 * helpers are created, use the doneq length as a metric to measure the 5432 * load on the interrupt CPU. If it is long enough, which indicates the 5433 * load is heavy, then we deliver the IO completions to the helpers. 5434 * This measurement has some limitations, although it is simple and 5435 * straightforward and works well for most of the cases at present. 5436 */ 5437 if (!mpt->m_doneq_thread_n || 5438 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) { 5439 mptsas_doneq_empty(mpt); 5440 } else { 5441 mptsas_deliver_doneq_thread(mpt); 5442 } 5443 5444 /* 5445 * If there are queued cmd, start them now. 5446 */ 5447 if (mpt->m_waitq != NULL) { 5448 mptsas_restart_waitq(mpt); 5449 } 5450 5451 mutex_exit(&mpt->m_mutex); 5452 return (DDI_INTR_CLAIMED); 5453 } 5454 5455 static void 5456 mptsas_process_intr(mptsas_t *mpt, 5457 pMpi2ReplyDescriptorsUnion_t reply_desc_union) 5458 { 5459 uint8_t reply_type; 5460 5461 ASSERT(mutex_owned(&mpt->m_mutex)); 5462 5463 /* 5464 * The reply is valid, process it according to its 5465 * type. Also, set a flag for updated the reply index 5466 * after they've all been processed. 5467 */ 5468 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 5469 &reply_desc_union->Default.ReplyFlags); 5470 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 5471 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 5472 mptsas_handle_scsi_io_success(mpt, reply_desc_union); 5473 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 5474 mptsas_handle_address_reply(mpt, reply_desc_union); 5475 } else { 5476 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type); 5477 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5478 } 5479 5480 /* 5481 * Clear the reply descriptor for re-use and increment 5482 * index. 5483 */ 5484 ddi_put64(mpt->m_acc_post_queue_hdl, 5485 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index], 5486 0xFFFFFFFFFFFFFFFF); 5487 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5488 DDI_DMA_SYNC_FORDEV); 5489 } 5490 5491 /* 5492 * handle qfull condition 5493 */ 5494 static void 5495 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd) 5496 { 5497 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5498 5499 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) || 5500 (ptgt->m_qfull_retries == 0)) { 5501 /* 5502 * We have exhausted the retries on QFULL, or, 5503 * the target driver has indicated that it 5504 * wants to handle QFULL itself by setting 5505 * qfull-retries capability to 0. In either case 5506 * we want the target driver's QFULL handling 5507 * to kick in. We do this by having pkt_reason 5508 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL. 5509 */ 5510 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5511 } else { 5512 if (ptgt->m_reset_delay == 0) { 5513 ptgt->m_t_throttle = 5514 max((ptgt->m_t_ncmds - 2), 0); 5515 } 5516 5517 cmd->cmd_pkt_flags |= FLAG_HEAD; 5518 cmd->cmd_flags &= ~(CFLAG_TRANFLAG); 5519 cmd->cmd_flags |= CFLAG_RETRY; 5520 5521 (void) mptsas_accept_pkt(mpt, cmd); 5522 5523 /* 5524 * when target gives queue full status with no commands 5525 * outstanding (m_t_ncmds == 0), throttle is set to 0 5526 * (HOLD_THROTTLE), and the queue full handling start 5527 * (see psarc/1994/313); if there are commands outstanding, 5528 * throttle is set to (m_t_ncmds - 2) 5529 */ 5530 if (ptgt->m_t_throttle == HOLD_THROTTLE) { 5531 /* 5532 * By setting throttle to QFULL_THROTTLE, we 5533 * avoid submitting new commands and in 5534 * mptsas_restart_cmd find out slots which need 5535 * their throttles to be cleared. 5536 */ 5537 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE); 5538 if (mpt->m_restart_cmd_timeid == 0) { 5539 mpt->m_restart_cmd_timeid = 5540 timeout(mptsas_restart_cmd, mpt, 5541 ptgt->m_qfull_retry_interval); 5542 } 5543 } 5544 } 5545 } 5546 5547 mptsas_phymask_t 5548 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport) 5549 { 5550 mptsas_phymask_t phy_mask = 0; 5551 uint8_t i = 0; 5552 5553 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance)); 5554 5555 ASSERT(mutex_owned(&mpt->m_mutex)); 5556 5557 /* 5558 * If physport is 0xFF, this is a RAID volume. Use phymask of 0. 5559 */ 5560 if (physport == 0xFF) { 5561 return (0); 5562 } 5563 5564 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 5565 if (mpt->m_phy_info[i].attached_devhdl && 5566 (mpt->m_phy_info[i].phy_mask != 0) && 5567 (mpt->m_phy_info[i].port_num == physport)) { 5568 phy_mask = mpt->m_phy_info[i].phy_mask; 5569 break; 5570 } 5571 } 5572 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ", 5573 mpt->m_instance, physport, phy_mask)); 5574 return (phy_mask); 5575 } 5576 5577 /* 5578 * mpt free device handle after device gone, by use of passthrough 5579 */ 5580 static int 5581 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl) 5582 { 5583 Mpi2SasIoUnitControlRequest_t req; 5584 Mpi2SasIoUnitControlReply_t rep; 5585 int ret; 5586 5587 ASSERT(mutex_owned(&mpt->m_mutex)); 5588 5589 /* 5590 * Need to compose a SAS IO Unit Control request message 5591 * and call mptsas_do_passthru() function 5592 */ 5593 bzero(&req, sizeof (req)); 5594 bzero(&rep, sizeof (rep)); 5595 5596 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; 5597 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE; 5598 req.DevHandle = LE_16(devhdl); 5599 5600 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 5601 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 5602 if (ret != 0) { 5603 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 5604 "Control error %d", ret); 5605 return (DDI_FAILURE); 5606 } 5607 5608 /* do passthrough success, check the ioc status */ 5609 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 5610 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 5611 "Control IOCStatus %d", LE_16(rep.IOCStatus)); 5612 return (DDI_FAILURE); 5613 } 5614 5615 return (DDI_SUCCESS); 5616 } 5617 5618 static void 5619 mptsas_update_phymask(mptsas_t *mpt) 5620 { 5621 mptsas_phymask_t mask = 0, phy_mask; 5622 char *phy_mask_name; 5623 uint8_t current_port; 5624 int i, j; 5625 5626 NDBG20(("mptsas%d update phymask ", mpt->m_instance)); 5627 5628 ASSERT(mutex_owned(&mpt->m_mutex)); 5629 5630 (void) mptsas_get_sas_io_unit_page(mpt); 5631 5632 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 5633 5634 for (i = 0; i < mpt->m_num_phys; i++) { 5635 phy_mask = 0x00; 5636 5637 if (mpt->m_phy_info[i].attached_devhdl == 0) 5638 continue; 5639 5640 bzero(phy_mask_name, sizeof (phy_mask_name)); 5641 5642 current_port = mpt->m_phy_info[i].port_num; 5643 5644 if ((mask & (1 << i)) != 0) 5645 continue; 5646 5647 for (j = 0; j < mpt->m_num_phys; j++) { 5648 if (mpt->m_phy_info[j].attached_devhdl && 5649 (mpt->m_phy_info[j].port_num == current_port)) { 5650 phy_mask |= (1 << j); 5651 } 5652 } 5653 mask = mask | phy_mask; 5654 5655 for (j = 0; j < mpt->m_num_phys; j++) { 5656 if ((phy_mask >> j) & 0x01) { 5657 mpt->m_phy_info[j].phy_mask = phy_mask; 5658 } 5659 } 5660 5661 (void) sprintf(phy_mask_name, "%x", phy_mask); 5662 5663 mutex_exit(&mpt->m_mutex); 5664 /* 5665 * register a iport, if the port has already been existed 5666 * SCSA will do nothing and just return. 5667 */ 5668 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 5669 mutex_enter(&mpt->m_mutex); 5670 } 5671 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 5672 NDBG20(("mptsas%d update phymask return", mpt->m_instance)); 5673 } 5674 5675 /* 5676 * mptsas_handle_dr is a task handler for DR, the DR action includes: 5677 * 1. Directly attched Device Added/Removed. 5678 * 2. Expander Device Added/Removed. 5679 * 3. Indirectly Attached Device Added/Expander. 5680 * 4. LUNs of a existing device status change. 5681 * 5. RAID volume created/deleted. 5682 * 6. Member of RAID volume is released because of RAID deletion. 5683 * 7. Physical disks are removed because of RAID creation. 5684 */ 5685 static void 5686 mptsas_handle_dr(void *args) { 5687 mptsas_topo_change_list_t *topo_node = NULL; 5688 mptsas_topo_change_list_t *save_node = NULL; 5689 mptsas_t *mpt; 5690 dev_info_t *parent = NULL; 5691 mptsas_phymask_t phymask = 0; 5692 char *phy_mask_name; 5693 uint8_t flags = 0, physport = 0xff; 5694 uint8_t port_update = 0; 5695 uint_t event; 5696 5697 topo_node = (mptsas_topo_change_list_t *)args; 5698 5699 mpt = topo_node->mpt; 5700 event = topo_node->event; 5701 flags = topo_node->flags; 5702 5703 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 5704 5705 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance)); 5706 5707 switch (event) { 5708 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 5709 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 5710 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) || 5711 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 5712 /* 5713 * Direct attached or expander attached device added 5714 * into system or a Phys Disk that is being unhidden. 5715 */ 5716 port_update = 1; 5717 } 5718 break; 5719 case MPTSAS_DR_EVENT_RECONFIG_SMP: 5720 /* 5721 * New expander added into system, it must be the head 5722 * of topo_change_list_t 5723 */ 5724 port_update = 1; 5725 break; 5726 default: 5727 port_update = 0; 5728 break; 5729 } 5730 /* 5731 * All cases port_update == 1 may cause initiator port form change 5732 */ 5733 mutex_enter(&mpt->m_mutex); 5734 if (mpt->m_port_chng && port_update) { 5735 /* 5736 * mpt->m_port_chng flag indicates some PHYs of initiator 5737 * port have changed to online. So when expander added or 5738 * directly attached device online event come, we force to 5739 * update port information by issueing SAS IO Unit Page and 5740 * update PHYMASKs. 5741 */ 5742 (void) mptsas_update_phymask(mpt); 5743 mpt->m_port_chng = 0; 5744 5745 } 5746 mutex_exit(&mpt->m_mutex); 5747 while (topo_node) { 5748 phymask = 0; 5749 if (parent == NULL) { 5750 physport = topo_node->un.physport; 5751 event = topo_node->event; 5752 flags = topo_node->flags; 5753 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET | 5754 MPTSAS_DR_EVENT_OFFLINE_SMP)) { 5755 /* 5756 * For all offline events, phymask is known 5757 */ 5758 phymask = topo_node->un.phymask; 5759 goto find_parent; 5760 } 5761 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 5762 goto handle_topo_change; 5763 } 5764 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) { 5765 phymask = topo_node->un.phymask; 5766 goto find_parent; 5767 } 5768 5769 if ((flags == 5770 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) && 5771 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) { 5772 /* 5773 * There is no any field in IR_CONFIG_CHANGE 5774 * event indicate physport/phynum, let's get 5775 * parent after SAS Device Page0 request. 5776 */ 5777 goto handle_topo_change; 5778 } 5779 5780 mutex_enter(&mpt->m_mutex); 5781 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 5782 /* 5783 * If the direct attached device added or a 5784 * phys disk is being unhidden, argument 5785 * physport actually is PHY#, so we have to get 5786 * phymask according PHY#. 5787 */ 5788 physport = mpt->m_phy_info[physport].port_num; 5789 } 5790 5791 /* 5792 * Translate physport to phymask so that we can search 5793 * parent dip. 5794 */ 5795 phymask = mptsas_physport_to_phymask(mpt, 5796 physport); 5797 mutex_exit(&mpt->m_mutex); 5798 5799 find_parent: 5800 bzero(phy_mask_name, MPTSAS_MAX_PHYS); 5801 /* 5802 * For RAID topology change node, write the iport name 5803 * as v0. 5804 */ 5805 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 5806 (void) sprintf(phy_mask_name, "v0"); 5807 } else { 5808 /* 5809 * phymask can bo 0 if the drive has been 5810 * pulled by the time an add event is 5811 * processed. If phymask is 0, just skip this 5812 * event and continue. 5813 */ 5814 if (phymask == 0) { 5815 mutex_enter(&mpt->m_mutex); 5816 save_node = topo_node; 5817 topo_node = topo_node->next; 5818 ASSERT(save_node); 5819 kmem_free(save_node, 5820 sizeof (mptsas_topo_change_list_t)); 5821 mutex_exit(&mpt->m_mutex); 5822 5823 parent = NULL; 5824 continue; 5825 } 5826 (void) sprintf(phy_mask_name, "%x", phymask); 5827 } 5828 parent = scsi_hba_iport_find(mpt->m_dip, 5829 phy_mask_name); 5830 if (parent == NULL) { 5831 mptsas_log(mpt, CE_WARN, "Failed to find an " 5832 "iport, should not happen!"); 5833 goto out; 5834 } 5835 5836 } 5837 ASSERT(parent); 5838 handle_topo_change: 5839 5840 mutex_enter(&mpt->m_mutex); 5841 /* 5842 * If HBA is being reset, don't perform operations depending 5843 * on the IOC. We must free the topo list, however. 5844 */ 5845 if (!mpt->m_in_reset) 5846 mptsas_handle_topo_change(topo_node, parent); 5847 else 5848 NDBG20(("skipping topo change received during reset")); 5849 save_node = topo_node; 5850 topo_node = topo_node->next; 5851 ASSERT(save_node); 5852 kmem_free(save_node, sizeof (mptsas_topo_change_list_t)); 5853 mutex_exit(&mpt->m_mutex); 5854 5855 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 5856 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) || 5857 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) { 5858 /* 5859 * If direct attached device associated, make sure 5860 * reset the parent before start the next one. But 5861 * all devices associated with expander shares the 5862 * parent. Also, reset parent if this is for RAID. 5863 */ 5864 parent = NULL; 5865 } 5866 } 5867 out: 5868 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 5869 } 5870 5871 static void 5872 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 5873 dev_info_t *parent) 5874 { 5875 mptsas_target_t *ptgt = NULL; 5876 mptsas_smp_t *psmp = NULL; 5877 mptsas_t *mpt = (void *)topo_node->mpt; 5878 uint16_t devhdl; 5879 uint16_t attached_devhdl; 5880 uint64_t sas_wwn = 0; 5881 int rval = 0; 5882 uint32_t page_address; 5883 uint8_t phy, flags; 5884 char *addr = NULL; 5885 dev_info_t *lundip; 5886 int circ = 0, circ1 = 0; 5887 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 5888 5889 NDBG20(("mptsas%d handle_topo_change enter", mpt->m_instance)); 5890 5891 ASSERT(mutex_owned(&mpt->m_mutex)); 5892 5893 switch (topo_node->event) { 5894 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 5895 { 5896 char *phy_mask_name; 5897 mptsas_phymask_t phymask = 0; 5898 5899 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 5900 /* 5901 * Get latest RAID info. 5902 */ 5903 (void) mptsas_get_raid_info(mpt); 5904 ptgt = refhash_linear_search(mpt->m_targets, 5905 mptsas_target_eval_devhdl, &topo_node->devhdl); 5906 if (ptgt == NULL) 5907 break; 5908 } else { 5909 ptgt = (void *)topo_node->object; 5910 } 5911 5912 if (ptgt == NULL) { 5913 /* 5914 * If a Phys Disk was deleted, RAID info needs to be 5915 * updated to reflect the new topology. 5916 */ 5917 (void) mptsas_get_raid_info(mpt); 5918 5919 /* 5920 * Get sas device page 0 by DevHandle to make sure if 5921 * SSP/SATA end device exist. 5922 */ 5923 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 5924 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 5925 topo_node->devhdl; 5926 5927 rval = mptsas_get_target_device_info(mpt, page_address, 5928 &devhdl, &ptgt); 5929 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) { 5930 mptsas_log(mpt, CE_NOTE, 5931 "mptsas_handle_topo_change: target %d is " 5932 "not a SAS/SATA device. \n", 5933 topo_node->devhdl); 5934 } else if (rval == DEV_INFO_FAIL_ALLOC) { 5935 mptsas_log(mpt, CE_NOTE, 5936 "mptsas_handle_topo_change: could not " 5937 "allocate memory. \n"); 5938 } 5939 /* 5940 * If rval is DEV_INFO_PHYS_DISK than there is nothing 5941 * else to do, just leave. 5942 */ 5943 if (rval != DEV_INFO_SUCCESS) { 5944 return; 5945 } 5946 } 5947 5948 ASSERT(ptgt->m_devhdl == topo_node->devhdl); 5949 5950 mutex_exit(&mpt->m_mutex); 5951 flags = topo_node->flags; 5952 5953 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) { 5954 phymask = ptgt->m_addr.mta_phymask; 5955 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 5956 (void) sprintf(phy_mask_name, "%x", phymask); 5957 parent = scsi_hba_iport_find(mpt->m_dip, 5958 phy_mask_name); 5959 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 5960 if (parent == NULL) { 5961 mptsas_log(mpt, CE_WARN, "Failed to find a " 5962 "iport for PD, should not happen!"); 5963 mutex_enter(&mpt->m_mutex); 5964 break; 5965 } 5966 } 5967 5968 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 5969 ndi_devi_enter(parent, &circ1); 5970 (void) mptsas_config_raid(parent, topo_node->devhdl, 5971 &lundip); 5972 ndi_devi_exit(parent, circ1); 5973 } else { 5974 /* 5975 * hold nexus for bus configure 5976 */ 5977 ndi_devi_enter(scsi_vhci_dip, &circ); 5978 ndi_devi_enter(parent, &circ1); 5979 rval = mptsas_config_target(parent, ptgt); 5980 /* 5981 * release nexus for bus configure 5982 */ 5983 ndi_devi_exit(parent, circ1); 5984 ndi_devi_exit(scsi_vhci_dip, circ); 5985 5986 /* 5987 * Add parent's props for SMHBA support 5988 */ 5989 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 5990 bzero(attached_wwnstr, 5991 sizeof (attached_wwnstr)); 5992 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 5993 ptgt->m_addr.mta_wwn); 5994 if (ddi_prop_update_string(DDI_DEV_T_NONE, 5995 parent, 5996 SCSI_ADDR_PROP_ATTACHED_PORT, 5997 attached_wwnstr) 5998 != DDI_PROP_SUCCESS) { 5999 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6000 parent, 6001 SCSI_ADDR_PROP_ATTACHED_PORT); 6002 mptsas_log(mpt, CE_WARN, "Failed to" 6003 "attached-port props"); 6004 return; 6005 } 6006 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6007 MPTSAS_NUM_PHYS, 1) != 6008 DDI_PROP_SUCCESS) { 6009 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6010 parent, MPTSAS_NUM_PHYS); 6011 mptsas_log(mpt, CE_WARN, "Failed to" 6012 " create num-phys props"); 6013 return; 6014 } 6015 6016 /* 6017 * Update PHY info for smhba 6018 */ 6019 mutex_enter(&mpt->m_mutex); 6020 if (mptsas_smhba_phy_init(mpt)) { 6021 mutex_exit(&mpt->m_mutex); 6022 mptsas_log(mpt, CE_WARN, "mptsas phy" 6023 " update failed"); 6024 return; 6025 } 6026 mutex_exit(&mpt->m_mutex); 6027 6028 /* 6029 * topo_node->un.physport is really the PHY# 6030 * for direct attached devices 6031 */ 6032 mptsas_smhba_set_one_phy_props(mpt, parent, 6033 topo_node->un.physport, &attached_devhdl); 6034 6035 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6036 MPTSAS_VIRTUAL_PORT, 0) != 6037 DDI_PROP_SUCCESS) { 6038 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6039 parent, MPTSAS_VIRTUAL_PORT); 6040 mptsas_log(mpt, CE_WARN, 6041 "mptsas virtual-port" 6042 "port prop update failed"); 6043 return; 6044 } 6045 } 6046 } 6047 mutex_enter(&mpt->m_mutex); 6048 6049 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, " 6050 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl, 6051 ptgt->m_addr.mta_phymask)); 6052 break; 6053 } 6054 case MPTSAS_DR_EVENT_OFFLINE_TARGET: 6055 { 6056 devhdl = topo_node->devhdl; 6057 ptgt = refhash_linear_search(mpt->m_targets, 6058 mptsas_target_eval_devhdl, &devhdl); 6059 if (ptgt == NULL) 6060 break; 6061 6062 sas_wwn = ptgt->m_addr.mta_wwn; 6063 phy = ptgt->m_phynum; 6064 6065 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 6066 6067 if (sas_wwn) { 6068 (void) sprintf(addr, "w%016"PRIx64, sas_wwn); 6069 } else { 6070 (void) sprintf(addr, "p%x", phy); 6071 } 6072 ASSERT(ptgt->m_devhdl == devhdl); 6073 6074 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) || 6075 (topo_node->flags == 6076 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6077 /* 6078 * Get latest RAID info if RAID volume status changes 6079 * or Phys Disk status changes 6080 */ 6081 (void) mptsas_get_raid_info(mpt); 6082 } 6083 /* 6084 * Abort all outstanding command on the device 6085 */ 6086 rval = mptsas_do_scsi_reset(mpt, devhdl); 6087 if (rval) { 6088 NDBG20(("mptsas%d handle_topo_change to reset target " 6089 "before offline devhdl:%x, phymask:%x, rval:%x", 6090 mpt->m_instance, ptgt->m_devhdl, 6091 ptgt->m_addr.mta_phymask, rval)); 6092 } 6093 6094 mutex_exit(&mpt->m_mutex); 6095 6096 ndi_devi_enter(scsi_vhci_dip, &circ); 6097 ndi_devi_enter(parent, &circ1); 6098 rval = mptsas_offline_target(parent, addr); 6099 ndi_devi_exit(parent, circ1); 6100 ndi_devi_exit(scsi_vhci_dip, circ); 6101 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, " 6102 "phymask:%x, rval:%x", mpt->m_instance, 6103 ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval)); 6104 6105 kmem_free(addr, SCSI_MAXNAMELEN); 6106 6107 /* 6108 * Clear parent's props for SMHBA support 6109 */ 6110 flags = topo_node->flags; 6111 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6112 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6113 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6114 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6115 DDI_PROP_SUCCESS) { 6116 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6117 SCSI_ADDR_PROP_ATTACHED_PORT); 6118 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6119 "prop update failed"); 6120 break; 6121 } 6122 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6123 MPTSAS_NUM_PHYS, 0) != 6124 DDI_PROP_SUCCESS) { 6125 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6126 MPTSAS_NUM_PHYS); 6127 mptsas_log(mpt, CE_WARN, "mptsas num phys " 6128 "prop update failed"); 6129 break; 6130 } 6131 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6132 MPTSAS_VIRTUAL_PORT, 1) != 6133 DDI_PROP_SUCCESS) { 6134 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6135 MPTSAS_VIRTUAL_PORT); 6136 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6137 "prop update failed"); 6138 break; 6139 } 6140 } 6141 6142 mutex_enter(&mpt->m_mutex); 6143 ptgt->m_led_status = 0; 6144 (void) mptsas_flush_led_status(mpt, ptgt); 6145 if (rval == DDI_SUCCESS) { 6146 refhash_remove(mpt->m_targets, ptgt); 6147 ptgt = NULL; 6148 } else { 6149 /* 6150 * clean DR_INTRANSITION flag to allow I/O down to 6151 * PHCI driver since failover finished. 6152 * Invalidate the devhdl 6153 */ 6154 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL; 6155 ptgt->m_tgt_unconfigured = 0; 6156 mutex_enter(&mpt->m_tx_waitq_mutex); 6157 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE; 6158 mutex_exit(&mpt->m_tx_waitq_mutex); 6159 } 6160 6161 /* 6162 * Send SAS IO Unit Control to free the dev handle 6163 */ 6164 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6165 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) { 6166 rval = mptsas_free_devhdl(mpt, devhdl); 6167 6168 NDBG20(("mptsas%d handle_topo_change to remove " 6169 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6170 rval)); 6171 } 6172 6173 break; 6174 } 6175 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE: 6176 { 6177 devhdl = topo_node->devhdl; 6178 /* 6179 * If this is the remove handle event, do a reset first. 6180 */ 6181 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6182 rval = mptsas_do_scsi_reset(mpt, devhdl); 6183 if (rval) { 6184 NDBG20(("mpt%d reset target before remove " 6185 "devhdl:%x, rval:%x", mpt->m_instance, 6186 devhdl, rval)); 6187 } 6188 } 6189 6190 /* 6191 * Send SAS IO Unit Control to free the dev handle 6192 */ 6193 rval = mptsas_free_devhdl(mpt, devhdl); 6194 NDBG20(("mptsas%d handle_topo_change to remove " 6195 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6196 rval)); 6197 break; 6198 } 6199 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6200 { 6201 mptsas_smp_t smp; 6202 dev_info_t *smpdip; 6203 6204 devhdl = topo_node->devhdl; 6205 6206 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 6207 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl; 6208 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp); 6209 if (rval != DDI_SUCCESS) { 6210 mptsas_log(mpt, CE_WARN, "failed to online smp, " 6211 "handle %x", devhdl); 6212 return; 6213 } 6214 6215 psmp = mptsas_smp_alloc(mpt, &smp); 6216 if (psmp == NULL) { 6217 return; 6218 } 6219 6220 mutex_exit(&mpt->m_mutex); 6221 ndi_devi_enter(parent, &circ1); 6222 (void) mptsas_online_smp(parent, psmp, &smpdip); 6223 ndi_devi_exit(parent, circ1); 6224 6225 mutex_enter(&mpt->m_mutex); 6226 break; 6227 } 6228 case MPTSAS_DR_EVENT_OFFLINE_SMP: 6229 { 6230 devhdl = topo_node->devhdl; 6231 uint32_t dev_info; 6232 6233 psmp = refhash_linear_search(mpt->m_smp_targets, 6234 mptsas_smp_eval_devhdl, &devhdl); 6235 if (psmp == NULL) 6236 break; 6237 /* 6238 * The mptsas_smp_t data is released only if the dip is offlined 6239 * successfully. 6240 */ 6241 mutex_exit(&mpt->m_mutex); 6242 6243 ndi_devi_enter(parent, &circ1); 6244 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE); 6245 ndi_devi_exit(parent, circ1); 6246 6247 dev_info = psmp->m_deviceinfo; 6248 if ((dev_info & DEVINFO_DIRECT_ATTACHED) == 6249 DEVINFO_DIRECT_ATTACHED) { 6250 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6251 MPTSAS_VIRTUAL_PORT, 1) != 6252 DDI_PROP_SUCCESS) { 6253 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6254 MPTSAS_VIRTUAL_PORT); 6255 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6256 "prop update failed"); 6257 return; 6258 } 6259 /* 6260 * Check whether the smp connected to the iport, 6261 */ 6262 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6263 MPTSAS_NUM_PHYS, 0) != 6264 DDI_PROP_SUCCESS) { 6265 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6266 MPTSAS_NUM_PHYS); 6267 mptsas_log(mpt, CE_WARN, "mptsas num phys" 6268 "prop update failed"); 6269 return; 6270 } 6271 /* 6272 * Clear parent's attached-port props 6273 */ 6274 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6275 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6276 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6277 DDI_PROP_SUCCESS) { 6278 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6279 SCSI_ADDR_PROP_ATTACHED_PORT); 6280 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6281 "prop update failed"); 6282 return; 6283 } 6284 } 6285 6286 mutex_enter(&mpt->m_mutex); 6287 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, " 6288 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval)); 6289 if (rval == DDI_SUCCESS) { 6290 refhash_remove(mpt->m_smp_targets, psmp); 6291 } else { 6292 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL; 6293 } 6294 6295 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6296 6297 break; 6298 } 6299 default: 6300 return; 6301 } 6302 } 6303 6304 /* 6305 * Record the event if its type is enabled in mpt instance by ioctl. 6306 */ 6307 static void 6308 mptsas_record_event(void *args) 6309 { 6310 m_replyh_arg_t *replyh_arg; 6311 pMpi2EventNotificationReply_t eventreply; 6312 uint32_t event, rfm; 6313 mptsas_t *mpt; 6314 int i, j; 6315 uint16_t event_data_len; 6316 boolean_t sendAEN = FALSE; 6317 6318 replyh_arg = (m_replyh_arg_t *)args; 6319 rfm = replyh_arg->rfm; 6320 mpt = replyh_arg->mpt; 6321 6322 eventreply = (pMpi2EventNotificationReply_t) 6323 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr)); 6324 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6325 6326 6327 /* 6328 * Generate a system event to let anyone who cares know that a 6329 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the 6330 * event mask is set to. 6331 */ 6332 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) { 6333 sendAEN = TRUE; 6334 } 6335 6336 /* 6337 * Record the event only if it is not masked. Determine which dword 6338 * and bit of event mask to test. 6339 */ 6340 i = (uint8_t)(event / 32); 6341 j = (uint8_t)(event % 32); 6342 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) { 6343 i = mpt->m_event_index; 6344 mpt->m_events[i].Type = event; 6345 mpt->m_events[i].Number = ++mpt->m_event_number; 6346 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4); 6347 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl, 6348 &eventreply->EventDataLength); 6349 6350 if (event_data_len > 0) { 6351 /* 6352 * Limit data to size in m_event entry 6353 */ 6354 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) { 6355 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH; 6356 } 6357 for (j = 0; j < event_data_len; j++) { 6358 mpt->m_events[i].Data[j] = 6359 ddi_get32(mpt->m_acc_reply_frame_hdl, 6360 &(eventreply->EventData[j])); 6361 } 6362 6363 /* 6364 * check for index wrap-around 6365 */ 6366 if (++i == MPTSAS_EVENT_QUEUE_SIZE) { 6367 i = 0; 6368 } 6369 mpt->m_event_index = (uint8_t)i; 6370 6371 /* 6372 * Set flag to send the event. 6373 */ 6374 sendAEN = TRUE; 6375 } 6376 } 6377 6378 /* 6379 * Generate a system event if flag is set to let anyone who cares know 6380 * that an event has occurred. 6381 */ 6382 if (sendAEN) { 6383 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS", 6384 "SAS", NULL, NULL, DDI_NOSLEEP); 6385 } 6386 } 6387 6388 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS 6389 /* 6390 * handle sync events from ioc in interrupt 6391 * return value: 6392 * DDI_SUCCESS: The event is handled by this func 6393 * DDI_FAILURE: Event is not handled 6394 */ 6395 static int 6396 mptsas_handle_event_sync(void *args) 6397 { 6398 m_replyh_arg_t *replyh_arg; 6399 pMpi2EventNotificationReply_t eventreply; 6400 uint32_t event, rfm; 6401 mptsas_t *mpt; 6402 uint_t iocstatus; 6403 6404 replyh_arg = (m_replyh_arg_t *)args; 6405 rfm = replyh_arg->rfm; 6406 mpt = replyh_arg->mpt; 6407 6408 ASSERT(mutex_owned(&mpt->m_mutex)); 6409 6410 eventreply = (pMpi2EventNotificationReply_t) 6411 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr)); 6412 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6413 6414 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 6415 &eventreply->IOCStatus)) { 6416 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 6417 mptsas_log(mpt, CE_WARN, 6418 "!mptsas_handle_event_sync: IOCStatus=0x%x, " 6419 "IOCLogInfo=0x%x", iocstatus, 6420 ddi_get32(mpt->m_acc_reply_frame_hdl, 6421 &eventreply->IOCLogInfo)); 6422 } else { 6423 mptsas_log(mpt, CE_WARN, 6424 "mptsas_handle_event_sync: IOCStatus=0x%x, " 6425 "IOCLogInfo=0x%x", iocstatus, 6426 ddi_get32(mpt->m_acc_reply_frame_hdl, 6427 &eventreply->IOCLogInfo)); 6428 } 6429 } 6430 6431 /* 6432 * figure out what kind of event we got and handle accordingly 6433 */ 6434 switch (event) { 6435 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 6436 { 6437 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list; 6438 uint8_t num_entries, expstatus, phy; 6439 uint8_t phystatus, physport, state, i; 6440 uint8_t start_phy_num, link_rate; 6441 uint16_t dev_handle, reason_code; 6442 uint16_t enc_handle, expd_handle; 6443 char string[80], curr[80], prev[80]; 6444 mptsas_topo_change_list_t *topo_head = NULL; 6445 mptsas_topo_change_list_t *topo_tail = NULL; 6446 mptsas_topo_change_list_t *topo_node = NULL; 6447 mptsas_target_t *ptgt; 6448 mptsas_smp_t *psmp; 6449 uint8_t flags = 0, exp_flag; 6450 smhba_info_t *pSmhba = NULL; 6451 6452 NDBG20(("mptsas_handle_event_sync: SAS topology change")); 6453 6454 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t) 6455 eventreply->EventData; 6456 6457 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6458 &sas_topo_change_list->EnclosureHandle); 6459 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6460 &sas_topo_change_list->ExpanderDevHandle); 6461 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 6462 &sas_topo_change_list->NumEntries); 6463 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 6464 &sas_topo_change_list->StartPhyNum); 6465 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 6466 &sas_topo_change_list->ExpStatus); 6467 physport = ddi_get8(mpt->m_acc_reply_frame_hdl, 6468 &sas_topo_change_list->PhysicalPort); 6469 6470 string[0] = 0; 6471 if (expd_handle) { 6472 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED; 6473 switch (expstatus) { 6474 case MPI2_EVENT_SAS_TOPO_ES_ADDED: 6475 (void) sprintf(string, " added"); 6476 /* 6477 * New expander device added 6478 */ 6479 mpt->m_port_chng = 1; 6480 topo_node = kmem_zalloc( 6481 sizeof (mptsas_topo_change_list_t), 6482 KM_SLEEP); 6483 topo_node->mpt = mpt; 6484 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP; 6485 topo_node->un.physport = physport; 6486 topo_node->devhdl = expd_handle; 6487 topo_node->flags = flags; 6488 topo_node->object = NULL; 6489 if (topo_head == NULL) { 6490 topo_head = topo_tail = topo_node; 6491 } else { 6492 topo_tail->next = topo_node; 6493 topo_tail = topo_node; 6494 } 6495 break; 6496 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING: 6497 (void) sprintf(string, " not responding, " 6498 "removed"); 6499 psmp = refhash_linear_search(mpt->m_smp_targets, 6500 mptsas_smp_eval_devhdl, &expd_handle); 6501 if (psmp == NULL) 6502 break; 6503 6504 topo_node = kmem_zalloc( 6505 sizeof (mptsas_topo_change_list_t), 6506 KM_SLEEP); 6507 topo_node->mpt = mpt; 6508 topo_node->un.phymask = 6509 psmp->m_addr.mta_phymask; 6510 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP; 6511 topo_node->devhdl = expd_handle; 6512 topo_node->flags = flags; 6513 topo_node->object = NULL; 6514 if (topo_head == NULL) { 6515 topo_head = topo_tail = topo_node; 6516 } else { 6517 topo_tail->next = topo_node; 6518 topo_tail = topo_node; 6519 } 6520 break; 6521 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING: 6522 break; 6523 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING: 6524 (void) sprintf(string, " not responding, " 6525 "delaying removal"); 6526 break; 6527 default: 6528 break; 6529 } 6530 } else { 6531 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE; 6532 } 6533 6534 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n", 6535 enc_handle, expd_handle, string)); 6536 for (i = 0; i < num_entries; i++) { 6537 phy = i + start_phy_num; 6538 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 6539 &sas_topo_change_list->PHY[i].PhyStatus); 6540 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6541 &sas_topo_change_list->PHY[i].AttachedDevHandle); 6542 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK; 6543 /* 6544 * Filter out processing of Phy Vacant Status unless 6545 * the reason code is "Not Responding". Process all 6546 * other combinations of Phy Status and Reason Codes. 6547 */ 6548 if ((phystatus & 6549 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) && 6550 (reason_code != 6551 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) { 6552 continue; 6553 } 6554 curr[0] = 0; 6555 prev[0] = 0; 6556 string[0] = 0; 6557 switch (reason_code) { 6558 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED: 6559 { 6560 NDBG20(("mptsas%d phy %d physical_port %d " 6561 "dev_handle %d added", mpt->m_instance, phy, 6562 physport, dev_handle)); 6563 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 6564 &sas_topo_change_list->PHY[i].LinkRate); 6565 state = (link_rate & 6566 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 6567 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 6568 switch (state) { 6569 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 6570 (void) sprintf(curr, "is disabled"); 6571 break; 6572 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 6573 (void) sprintf(curr, "is offline, " 6574 "failed speed negotiation"); 6575 break; 6576 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 6577 (void) sprintf(curr, "SATA OOB " 6578 "complete"); 6579 break; 6580 case SMP_RESET_IN_PROGRESS: 6581 (void) sprintf(curr, "SMP reset in " 6582 "progress"); 6583 break; 6584 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 6585 (void) sprintf(curr, "is online at " 6586 "1.5 Gbps"); 6587 break; 6588 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 6589 (void) sprintf(curr, "is online at 3.0 " 6590 "Gbps"); 6591 break; 6592 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 6593 (void) sprintf(curr, "is online at 6.0 " 6594 "Gbps"); 6595 break; 6596 default: 6597 (void) sprintf(curr, "state is " 6598 "unknown"); 6599 break; 6600 } 6601 /* 6602 * New target device added into the system. 6603 * Set association flag according to if an 6604 * expander is used or not. 6605 */ 6606 exp_flag = 6607 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 6608 if (flags == 6609 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 6610 flags = exp_flag; 6611 } 6612 topo_node = kmem_zalloc( 6613 sizeof (mptsas_topo_change_list_t), 6614 KM_SLEEP); 6615 topo_node->mpt = mpt; 6616 topo_node->event = 6617 MPTSAS_DR_EVENT_RECONFIG_TARGET; 6618 if (expd_handle == 0) { 6619 /* 6620 * Per MPI 2, if expander dev handle 6621 * is 0, it's a directly attached 6622 * device. So driver use PHY to decide 6623 * which iport is associated 6624 */ 6625 physport = phy; 6626 mpt->m_port_chng = 1; 6627 } 6628 topo_node->un.physport = physport; 6629 topo_node->devhdl = dev_handle; 6630 topo_node->flags = flags; 6631 topo_node->object = NULL; 6632 if (topo_head == NULL) { 6633 topo_head = topo_tail = topo_node; 6634 } else { 6635 topo_tail->next = topo_node; 6636 topo_tail = topo_node; 6637 } 6638 break; 6639 } 6640 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING: 6641 { 6642 NDBG20(("mptsas%d phy %d physical_port %d " 6643 "dev_handle %d removed", mpt->m_instance, 6644 phy, physport, dev_handle)); 6645 /* 6646 * Set association flag according to if an 6647 * expander is used or not. 6648 */ 6649 exp_flag = 6650 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 6651 if (flags == 6652 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 6653 flags = exp_flag; 6654 } 6655 /* 6656 * Target device is removed from the system 6657 * Before the device is really offline from 6658 * from system. 6659 */ 6660 ptgt = refhash_linear_search(mpt->m_targets, 6661 mptsas_target_eval_devhdl, &dev_handle); 6662 /* 6663 * If ptgt is NULL here, it means that the 6664 * DevHandle is not in the hash table. This is 6665 * reasonable sometimes. For example, if a 6666 * disk was pulled, then added, then pulled 6667 * again, the disk will not have been put into 6668 * the hash table because the add event will 6669 * have an invalid phymask. BUT, this does not 6670 * mean that the DevHandle is invalid. The 6671 * controller will still have a valid DevHandle 6672 * that must be removed. To do this, use the 6673 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event. 6674 */ 6675 if (ptgt == NULL) { 6676 topo_node = kmem_zalloc( 6677 sizeof (mptsas_topo_change_list_t), 6678 KM_SLEEP); 6679 topo_node->mpt = mpt; 6680 topo_node->un.phymask = 0; 6681 topo_node->event = 6682 MPTSAS_TOPO_FLAG_REMOVE_HANDLE; 6683 topo_node->devhdl = dev_handle; 6684 topo_node->flags = flags; 6685 topo_node->object = NULL; 6686 if (topo_head == NULL) { 6687 topo_head = topo_tail = 6688 topo_node; 6689 } else { 6690 topo_tail->next = topo_node; 6691 topo_tail = topo_node; 6692 } 6693 break; 6694 } 6695 6696 /* 6697 * Update DR flag immediately avoid I/O failure 6698 * before failover finish. Pay attention to the 6699 * mutex protect, we need grab m_tx_waitq_mutex 6700 * during set m_dr_flag because we won't add 6701 * the following command into waitq, instead, 6702 * we need return TRAN_BUSY in the tran_start 6703 * context. 6704 */ 6705 mutex_enter(&mpt->m_tx_waitq_mutex); 6706 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 6707 mutex_exit(&mpt->m_tx_waitq_mutex); 6708 6709 topo_node = kmem_zalloc( 6710 sizeof (mptsas_topo_change_list_t), 6711 KM_SLEEP); 6712 topo_node->mpt = mpt; 6713 topo_node->un.phymask = 6714 ptgt->m_addr.mta_phymask; 6715 topo_node->event = 6716 MPTSAS_DR_EVENT_OFFLINE_TARGET; 6717 topo_node->devhdl = dev_handle; 6718 topo_node->flags = flags; 6719 topo_node->object = NULL; 6720 if (topo_head == NULL) { 6721 topo_head = topo_tail = topo_node; 6722 } else { 6723 topo_tail->next = topo_node; 6724 topo_tail = topo_node; 6725 } 6726 break; 6727 } 6728 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED: 6729 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 6730 &sas_topo_change_list->PHY[i].LinkRate); 6731 state = (link_rate & 6732 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 6733 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 6734 pSmhba = &mpt->m_phy_info[i].smhba_info; 6735 pSmhba->negotiated_link_rate = state; 6736 switch (state) { 6737 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 6738 (void) sprintf(curr, "is disabled"); 6739 mptsas_smhba_log_sysevent(mpt, 6740 ESC_SAS_PHY_EVENT, 6741 SAS_PHY_REMOVE, 6742 &mpt->m_phy_info[i].smhba_info); 6743 mpt->m_phy_info[i].smhba_info. 6744 negotiated_link_rate 6745 = 0x1; 6746 break; 6747 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 6748 (void) sprintf(curr, "is offline, " 6749 "failed speed negotiation"); 6750 mptsas_smhba_log_sysevent(mpt, 6751 ESC_SAS_PHY_EVENT, 6752 SAS_PHY_OFFLINE, 6753 &mpt->m_phy_info[i].smhba_info); 6754 break; 6755 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 6756 (void) sprintf(curr, "SATA OOB " 6757 "complete"); 6758 break; 6759 case SMP_RESET_IN_PROGRESS: 6760 (void) sprintf(curr, "SMP reset in " 6761 "progress"); 6762 break; 6763 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 6764 (void) sprintf(curr, "is online at " 6765 "1.5 Gbps"); 6766 if ((expd_handle == 0) && 6767 (enc_handle == 1)) { 6768 mpt->m_port_chng = 1; 6769 } 6770 mptsas_smhba_log_sysevent(mpt, 6771 ESC_SAS_PHY_EVENT, 6772 SAS_PHY_ONLINE, 6773 &mpt->m_phy_info[i].smhba_info); 6774 break; 6775 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 6776 (void) sprintf(curr, "is online at 3.0 " 6777 "Gbps"); 6778 if ((expd_handle == 0) && 6779 (enc_handle == 1)) { 6780 mpt->m_port_chng = 1; 6781 } 6782 mptsas_smhba_log_sysevent(mpt, 6783 ESC_SAS_PHY_EVENT, 6784 SAS_PHY_ONLINE, 6785 &mpt->m_phy_info[i].smhba_info); 6786 break; 6787 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 6788 (void) sprintf(curr, "is online at " 6789 "6.0 Gbps"); 6790 if ((expd_handle == 0) && 6791 (enc_handle == 1)) { 6792 mpt->m_port_chng = 1; 6793 } 6794 mptsas_smhba_log_sysevent(mpt, 6795 ESC_SAS_PHY_EVENT, 6796 SAS_PHY_ONLINE, 6797 &mpt->m_phy_info[i].smhba_info); 6798 break; 6799 default: 6800 (void) sprintf(curr, "state is " 6801 "unknown"); 6802 break; 6803 } 6804 6805 state = (link_rate & 6806 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >> 6807 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT; 6808 switch (state) { 6809 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 6810 (void) sprintf(prev, ", was disabled"); 6811 break; 6812 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 6813 (void) sprintf(prev, ", was offline, " 6814 "failed speed negotiation"); 6815 break; 6816 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 6817 (void) sprintf(prev, ", was SATA OOB " 6818 "complete"); 6819 break; 6820 case SMP_RESET_IN_PROGRESS: 6821 (void) sprintf(prev, ", was SMP reset " 6822 "in progress"); 6823 break; 6824 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 6825 (void) sprintf(prev, ", was online at " 6826 "1.5 Gbps"); 6827 break; 6828 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 6829 (void) sprintf(prev, ", was online at " 6830 "3.0 Gbps"); 6831 break; 6832 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 6833 (void) sprintf(prev, ", was online at " 6834 "6.0 Gbps"); 6835 break; 6836 default: 6837 break; 6838 } 6839 (void) sprintf(&string[strlen(string)], "link " 6840 "changed, "); 6841 break; 6842 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE: 6843 continue; 6844 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING: 6845 (void) sprintf(&string[strlen(string)], 6846 "target not responding, delaying " 6847 "removal"); 6848 break; 6849 } 6850 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n", 6851 mpt->m_instance, phy, dev_handle, string, curr, 6852 prev)); 6853 } 6854 if (topo_head != NULL) { 6855 /* 6856 * Launch DR taskq to handle topology change 6857 */ 6858 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 6859 mptsas_handle_dr, (void *)topo_head, 6860 DDI_NOSLEEP)) != DDI_SUCCESS) { 6861 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 6862 "for handle SAS DR event failed. \n"); 6863 } 6864 } 6865 break; 6866 } 6867 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 6868 { 6869 Mpi2EventDataIrConfigChangeList_t *irChangeList; 6870 mptsas_topo_change_list_t *topo_head = NULL; 6871 mptsas_topo_change_list_t *topo_tail = NULL; 6872 mptsas_topo_change_list_t *topo_node = NULL; 6873 mptsas_target_t *ptgt; 6874 uint8_t num_entries, i, reason; 6875 uint16_t volhandle, diskhandle; 6876 6877 irChangeList = (pMpi2EventDataIrConfigChangeList_t) 6878 eventreply->EventData; 6879 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 6880 &irChangeList->NumElements); 6881 6882 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received", 6883 mpt->m_instance)); 6884 6885 for (i = 0; i < num_entries; i++) { 6886 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 6887 &irChangeList->ConfigElement[i].ReasonCode); 6888 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6889 &irChangeList->ConfigElement[i].VolDevHandle); 6890 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6891 &irChangeList->ConfigElement[i].PhysDiskDevHandle); 6892 6893 switch (reason) { 6894 case MPI2_EVENT_IR_CHANGE_RC_ADDED: 6895 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED: 6896 { 6897 NDBG20(("mptsas %d volume added\n", 6898 mpt->m_instance)); 6899 6900 topo_node = kmem_zalloc( 6901 sizeof (mptsas_topo_change_list_t), 6902 KM_SLEEP); 6903 6904 topo_node->mpt = mpt; 6905 topo_node->event = 6906 MPTSAS_DR_EVENT_RECONFIG_TARGET; 6907 topo_node->un.physport = 0xff; 6908 topo_node->devhdl = volhandle; 6909 topo_node->flags = 6910 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 6911 topo_node->object = NULL; 6912 if (topo_head == NULL) { 6913 topo_head = topo_tail = topo_node; 6914 } else { 6915 topo_tail->next = topo_node; 6916 topo_tail = topo_node; 6917 } 6918 break; 6919 } 6920 case MPI2_EVENT_IR_CHANGE_RC_REMOVED: 6921 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED: 6922 { 6923 NDBG20(("mptsas %d volume deleted\n", 6924 mpt->m_instance)); 6925 ptgt = refhash_linear_search(mpt->m_targets, 6926 mptsas_target_eval_devhdl, &volhandle); 6927 if (ptgt == NULL) 6928 break; 6929 6930 /* 6931 * Clear any flags related to volume 6932 */ 6933 (void) mptsas_delete_volume(mpt, volhandle); 6934 6935 /* 6936 * Update DR flag immediately avoid I/O failure 6937 */ 6938 mutex_enter(&mpt->m_tx_waitq_mutex); 6939 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 6940 mutex_exit(&mpt->m_tx_waitq_mutex); 6941 6942 topo_node = kmem_zalloc( 6943 sizeof (mptsas_topo_change_list_t), 6944 KM_SLEEP); 6945 topo_node->mpt = mpt; 6946 topo_node->un.phymask = 6947 ptgt->m_addr.mta_phymask; 6948 topo_node->event = 6949 MPTSAS_DR_EVENT_OFFLINE_TARGET; 6950 topo_node->devhdl = volhandle; 6951 topo_node->flags = 6952 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 6953 topo_node->object = (void *)ptgt; 6954 if (topo_head == NULL) { 6955 topo_head = topo_tail = topo_node; 6956 } else { 6957 topo_tail->next = topo_node; 6958 topo_tail = topo_node; 6959 } 6960 break; 6961 } 6962 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED: 6963 case MPI2_EVENT_IR_CHANGE_RC_HIDE: 6964 { 6965 ptgt = refhash_linear_search(mpt->m_targets, 6966 mptsas_target_eval_devhdl, &diskhandle); 6967 if (ptgt == NULL) 6968 break; 6969 6970 /* 6971 * Update DR flag immediately avoid I/O failure 6972 */ 6973 mutex_enter(&mpt->m_tx_waitq_mutex); 6974 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 6975 mutex_exit(&mpt->m_tx_waitq_mutex); 6976 6977 topo_node = kmem_zalloc( 6978 sizeof (mptsas_topo_change_list_t), 6979 KM_SLEEP); 6980 topo_node->mpt = mpt; 6981 topo_node->un.phymask = 6982 ptgt->m_addr.mta_phymask; 6983 topo_node->event = 6984 MPTSAS_DR_EVENT_OFFLINE_TARGET; 6985 topo_node->devhdl = diskhandle; 6986 topo_node->flags = 6987 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 6988 topo_node->object = (void *)ptgt; 6989 if (topo_head == NULL) { 6990 topo_head = topo_tail = topo_node; 6991 } else { 6992 topo_tail->next = topo_node; 6993 topo_tail = topo_node; 6994 } 6995 break; 6996 } 6997 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE: 6998 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED: 6999 { 7000 /* 7001 * The physical drive is released by a IR 7002 * volume. But we cannot get the the physport 7003 * or phynum from the event data, so we only 7004 * can get the physport/phynum after SAS 7005 * Device Page0 request for the devhdl. 7006 */ 7007 topo_node = kmem_zalloc( 7008 sizeof (mptsas_topo_change_list_t), 7009 KM_SLEEP); 7010 topo_node->mpt = mpt; 7011 topo_node->un.phymask = 0; 7012 topo_node->event = 7013 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7014 topo_node->devhdl = diskhandle; 7015 topo_node->flags = 7016 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7017 topo_node->object = NULL; 7018 mpt->m_port_chng = 1; 7019 if (topo_head == NULL) { 7020 topo_head = topo_tail = topo_node; 7021 } else { 7022 topo_tail->next = topo_node; 7023 topo_tail = topo_node; 7024 } 7025 break; 7026 } 7027 default: 7028 break; 7029 } 7030 } 7031 7032 if (topo_head != NULL) { 7033 /* 7034 * Launch DR taskq to handle topology change 7035 */ 7036 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7037 mptsas_handle_dr, (void *)topo_head, 7038 DDI_NOSLEEP)) != DDI_SUCCESS) { 7039 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7040 "for handle SAS DR event failed. \n"); 7041 } 7042 } 7043 break; 7044 } 7045 default: 7046 return (DDI_FAILURE); 7047 } 7048 7049 return (DDI_SUCCESS); 7050 } 7051 7052 /* 7053 * handle events from ioc 7054 */ 7055 static void 7056 mptsas_handle_event(void *args) 7057 { 7058 m_replyh_arg_t *replyh_arg; 7059 pMpi2EventNotificationReply_t eventreply; 7060 uint32_t event, iocloginfo, rfm; 7061 uint32_t status; 7062 uint8_t port; 7063 mptsas_t *mpt; 7064 uint_t iocstatus; 7065 7066 replyh_arg = (m_replyh_arg_t *)args; 7067 rfm = replyh_arg->rfm; 7068 mpt = replyh_arg->mpt; 7069 7070 mutex_enter(&mpt->m_mutex); 7071 /* 7072 * If HBA is being reset, drop incoming event. 7073 */ 7074 if (mpt->m_in_reset) { 7075 NDBG20(("dropping event received prior to reset")); 7076 mutex_exit(&mpt->m_mutex); 7077 return; 7078 } 7079 7080 eventreply = (pMpi2EventNotificationReply_t) 7081 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr)); 7082 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7083 7084 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 7085 &eventreply->IOCStatus)) { 7086 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 7087 mptsas_log(mpt, CE_WARN, 7088 "!mptsas_handle_event: IOCStatus=0x%x, " 7089 "IOCLogInfo=0x%x", iocstatus, 7090 ddi_get32(mpt->m_acc_reply_frame_hdl, 7091 &eventreply->IOCLogInfo)); 7092 } else { 7093 mptsas_log(mpt, CE_WARN, 7094 "mptsas_handle_event: IOCStatus=0x%x, " 7095 "IOCLogInfo=0x%x", iocstatus, 7096 ddi_get32(mpt->m_acc_reply_frame_hdl, 7097 &eventreply->IOCLogInfo)); 7098 } 7099 } 7100 7101 /* 7102 * figure out what kind of event we got and handle accordingly 7103 */ 7104 switch (event) { 7105 case MPI2_EVENT_LOG_ENTRY_ADDED: 7106 break; 7107 case MPI2_EVENT_LOG_DATA: 7108 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7109 &eventreply->IOCLogInfo); 7110 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance, 7111 iocloginfo)); 7112 break; 7113 case MPI2_EVENT_STATE_CHANGE: 7114 NDBG20(("mptsas%d state change.", mpt->m_instance)); 7115 break; 7116 case MPI2_EVENT_HARD_RESET_RECEIVED: 7117 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7118 break; 7119 case MPI2_EVENT_SAS_DISCOVERY: 7120 { 7121 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery; 7122 char string[80]; 7123 uint8_t rc; 7124 7125 sasdiscovery = 7126 (pMpi2EventDataSasDiscovery_t)eventreply->EventData; 7127 7128 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7129 &sasdiscovery->ReasonCode); 7130 port = ddi_get8(mpt->m_acc_reply_frame_hdl, 7131 &sasdiscovery->PhysicalPort); 7132 status = ddi_get32(mpt->m_acc_reply_frame_hdl, 7133 &sasdiscovery->DiscoveryStatus); 7134 7135 string[0] = 0; 7136 switch (rc) { 7137 case MPI2_EVENT_SAS_DISC_RC_STARTED: 7138 (void) sprintf(string, "STARTING"); 7139 break; 7140 case MPI2_EVENT_SAS_DISC_RC_COMPLETED: 7141 (void) sprintf(string, "COMPLETED"); 7142 break; 7143 default: 7144 (void) sprintf(string, "UNKNOWN"); 7145 break; 7146 } 7147 7148 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string, 7149 port, status)); 7150 7151 break; 7152 } 7153 case MPI2_EVENT_EVENT_CHANGE: 7154 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7155 break; 7156 case MPI2_EVENT_TASK_SET_FULL: 7157 { 7158 pMpi2EventDataTaskSetFull_t taskfull; 7159 7160 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData; 7161 7162 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n", 7163 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 7164 &taskfull->CurrentDepth))); 7165 break; 7166 } 7167 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 7168 { 7169 /* 7170 * SAS TOPOLOGY CHANGE LIST Event has already been handled 7171 * in mptsas_handle_event_sync() of interrupt context 7172 */ 7173 break; 7174 } 7175 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 7176 { 7177 pMpi2EventDataSasEnclDevStatusChange_t encstatus; 7178 uint8_t rc; 7179 char string[80]; 7180 7181 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t) 7182 eventreply->EventData; 7183 7184 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7185 &encstatus->ReasonCode); 7186 switch (rc) { 7187 case MPI2_EVENT_SAS_ENCL_RC_ADDED: 7188 (void) sprintf(string, "added"); 7189 break; 7190 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING: 7191 (void) sprintf(string, ", not responding"); 7192 break; 7193 default: 7194 break; 7195 } 7196 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure %x%s\n", 7197 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 7198 &encstatus->EnclosureHandle), string)); 7199 break; 7200 } 7201 7202 /* 7203 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by 7204 * mptsas_handle_event_sync,in here just send ack message. 7205 */ 7206 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 7207 { 7208 pMpi2EventDataSasDeviceStatusChange_t statuschange; 7209 uint8_t rc; 7210 uint16_t devhdl; 7211 uint64_t wwn = 0; 7212 uint32_t wwn_lo, wwn_hi; 7213 7214 statuschange = (pMpi2EventDataSasDeviceStatusChange_t) 7215 eventreply->EventData; 7216 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7217 &statuschange->ReasonCode); 7218 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7219 (uint32_t *)(void *)&statuschange->SASAddress); 7220 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl, 7221 (uint32_t *)(void *)&statuschange->SASAddress + 1); 7222 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo; 7223 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7224 &statuschange->DevHandle); 7225 7226 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64, 7227 wwn)); 7228 7229 switch (rc) { 7230 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7231 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x", 7232 ddi_get8(mpt->m_acc_reply_frame_hdl, 7233 &statuschange->ASC), 7234 ddi_get8(mpt->m_acc_reply_frame_hdl, 7235 &statuschange->ASCQ))); 7236 break; 7237 7238 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7239 NDBG20(("Device not supported")); 7240 break; 7241 7242 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7243 NDBG20(("IOC internally generated the Target Reset " 7244 "for devhdl:%x", devhdl)); 7245 break; 7246 7247 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET: 7248 NDBG20(("IOC's internally generated Target Reset " 7249 "completed for devhdl:%x", devhdl)); 7250 break; 7251 7252 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7253 NDBG20(("IOC internally generated Abort Task")); 7254 break; 7255 7256 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL: 7257 NDBG20(("IOC's internally generated Abort Task " 7258 "completed")); 7259 break; 7260 7261 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 7262 NDBG20(("IOC internally generated Abort Task Set")); 7263 break; 7264 7265 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 7266 NDBG20(("IOC internally generated Clear Task Set")); 7267 break; 7268 7269 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 7270 NDBG20(("IOC internally generated Query Task")); 7271 break; 7272 7273 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION: 7274 NDBG20(("Device sent an Asynchronous Notification")); 7275 break; 7276 7277 default: 7278 break; 7279 } 7280 break; 7281 } 7282 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7283 { 7284 /* 7285 * IR TOPOLOGY CHANGE LIST Event has already been handled 7286 * in mpt_handle_event_sync() of interrupt context 7287 */ 7288 break; 7289 } 7290 case MPI2_EVENT_IR_OPERATION_STATUS: 7291 { 7292 Mpi2EventDataIrOperationStatus_t *irOpStatus; 7293 char reason_str[80]; 7294 uint8_t rc, percent; 7295 uint16_t handle; 7296 7297 irOpStatus = (pMpi2EventDataIrOperationStatus_t) 7298 eventreply->EventData; 7299 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7300 &irOpStatus->RAIDOperation); 7301 percent = ddi_get8(mpt->m_acc_reply_frame_hdl, 7302 &irOpStatus->PercentComplete); 7303 handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7304 &irOpStatus->VolDevHandle); 7305 7306 switch (rc) { 7307 case MPI2_EVENT_IR_RAIDOP_RESYNC: 7308 (void) sprintf(reason_str, "resync"); 7309 break; 7310 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION: 7311 (void) sprintf(reason_str, "online capacity " 7312 "expansion"); 7313 break; 7314 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK: 7315 (void) sprintf(reason_str, "consistency check"); 7316 break; 7317 default: 7318 (void) sprintf(reason_str, "unknown reason %x", 7319 rc); 7320 } 7321 7322 NDBG20(("mptsas%d raid operational status: (%s)" 7323 "\thandle(0x%04x), percent complete(%d)\n", 7324 mpt->m_instance, reason_str, handle, percent)); 7325 break; 7326 } 7327 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 7328 { 7329 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast; 7330 uint8_t phy_num; 7331 uint8_t primitive; 7332 7333 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t) 7334 eventreply->EventData; 7335 7336 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 7337 &sas_broadcast->PhyNum); 7338 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl, 7339 &sas_broadcast->Primitive); 7340 7341 switch (primitive) { 7342 case MPI2_EVENT_PRIMITIVE_CHANGE: 7343 mptsas_smhba_log_sysevent(mpt, 7344 ESC_SAS_HBA_PORT_BROADCAST, 7345 SAS_PORT_BROADCAST_CHANGE, 7346 &mpt->m_phy_info[phy_num].smhba_info); 7347 break; 7348 case MPI2_EVENT_PRIMITIVE_SES: 7349 mptsas_smhba_log_sysevent(mpt, 7350 ESC_SAS_HBA_PORT_BROADCAST, 7351 SAS_PORT_BROADCAST_SES, 7352 &mpt->m_phy_info[phy_num].smhba_info); 7353 break; 7354 case MPI2_EVENT_PRIMITIVE_EXPANDER: 7355 mptsas_smhba_log_sysevent(mpt, 7356 ESC_SAS_HBA_PORT_BROADCAST, 7357 SAS_PORT_BROADCAST_D01_4, 7358 &mpt->m_phy_info[phy_num].smhba_info); 7359 break; 7360 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT: 7361 mptsas_smhba_log_sysevent(mpt, 7362 ESC_SAS_HBA_PORT_BROADCAST, 7363 SAS_PORT_BROADCAST_D04_7, 7364 &mpt->m_phy_info[phy_num].smhba_info); 7365 break; 7366 case MPI2_EVENT_PRIMITIVE_RESERVED3: 7367 mptsas_smhba_log_sysevent(mpt, 7368 ESC_SAS_HBA_PORT_BROADCAST, 7369 SAS_PORT_BROADCAST_D16_7, 7370 &mpt->m_phy_info[phy_num].smhba_info); 7371 break; 7372 case MPI2_EVENT_PRIMITIVE_RESERVED4: 7373 mptsas_smhba_log_sysevent(mpt, 7374 ESC_SAS_HBA_PORT_BROADCAST, 7375 SAS_PORT_BROADCAST_D29_7, 7376 &mpt->m_phy_info[phy_num].smhba_info); 7377 break; 7378 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED: 7379 mptsas_smhba_log_sysevent(mpt, 7380 ESC_SAS_HBA_PORT_BROADCAST, 7381 SAS_PORT_BROADCAST_D24_0, 7382 &mpt->m_phy_info[phy_num].smhba_info); 7383 break; 7384 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED: 7385 mptsas_smhba_log_sysevent(mpt, 7386 ESC_SAS_HBA_PORT_BROADCAST, 7387 SAS_PORT_BROADCAST_D27_4, 7388 &mpt->m_phy_info[phy_num].smhba_info); 7389 break; 7390 default: 7391 NDBG20(("mptsas%d: unknown BROADCAST PRIMITIVE" 7392 " %x received", 7393 mpt->m_instance, primitive)); 7394 break; 7395 } 7396 NDBG20(("mptsas%d sas broadcast primitive: " 7397 "\tprimitive(0x%04x), phy(%d) complete\n", 7398 mpt->m_instance, primitive, phy_num)); 7399 break; 7400 } 7401 case MPI2_EVENT_IR_VOLUME: 7402 { 7403 Mpi2EventDataIrVolume_t *irVolume; 7404 uint16_t devhandle; 7405 uint32_t state; 7406 int config, vol; 7407 uint8_t found = FALSE; 7408 7409 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData; 7410 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 7411 &irVolume->NewValue); 7412 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7413 &irVolume->VolDevHandle); 7414 7415 NDBG20(("EVENT_IR_VOLUME event is received")); 7416 7417 /* 7418 * Get latest RAID info and then find the DevHandle for this 7419 * event in the configuration. If the DevHandle is not found 7420 * just exit the event. 7421 */ 7422 (void) mptsas_get_raid_info(mpt); 7423 for (config = 0; (config < mpt->m_num_raid_configs) && 7424 (!found); config++) { 7425 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 7426 if (mpt->m_raidconfig[config].m_raidvol[vol]. 7427 m_raidhandle == devhandle) { 7428 found = TRUE; 7429 break; 7430 } 7431 } 7432 } 7433 if (!found) { 7434 break; 7435 } 7436 7437 switch (irVolume->ReasonCode) { 7438 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED: 7439 { 7440 uint32_t i; 7441 mpt->m_raidconfig[config].m_raidvol[vol].m_settings = 7442 state; 7443 7444 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING; 7445 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed" 7446 ", auto-config of hot-swap drives is %s" 7447 ", write caching is %s" 7448 ", hot-spare pool mask is %02x\n", 7449 vol, state & 7450 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE 7451 ? "disabled" : "enabled", 7452 i == MPI2_RAIDVOL0_SETTING_UNCHANGED 7453 ? "controlled by member disks" : 7454 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING 7455 ? "disabled" : 7456 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING 7457 ? "enabled" : 7458 "incorrectly set", 7459 (state >> 16) & 0xff); 7460 break; 7461 } 7462 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED: 7463 { 7464 mpt->m_raidconfig[config].m_raidvol[vol].m_state = 7465 (uint8_t)state; 7466 7467 mptsas_log(mpt, CE_NOTE, 7468 "Volume %d is now %s\n", vol, 7469 state == MPI2_RAID_VOL_STATE_OPTIMAL 7470 ? "optimal" : 7471 state == MPI2_RAID_VOL_STATE_DEGRADED 7472 ? "degraded" : 7473 state == MPI2_RAID_VOL_STATE_ONLINE 7474 ? "online" : 7475 state == MPI2_RAID_VOL_STATE_INITIALIZING 7476 ? "initializing" : 7477 state == MPI2_RAID_VOL_STATE_FAILED 7478 ? "failed" : 7479 state == MPI2_RAID_VOL_STATE_MISSING 7480 ? "missing" : 7481 "state unknown"); 7482 break; 7483 } 7484 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED: 7485 { 7486 mpt->m_raidconfig[config].m_raidvol[vol]. 7487 m_statusflags = state; 7488 7489 mptsas_log(mpt, CE_NOTE, 7490 " Volume %d is now %s%s%s%s%s%s%s%s%s\n", 7491 vol, 7492 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED 7493 ? ", enabled" : ", disabled", 7494 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED 7495 ? ", quiesced" : "", 7496 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE 7497 ? ", inactive" : ", active", 7498 state & 7499 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL 7500 ? ", bad block table is full" : "", 7501 state & 7502 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 7503 ? ", resync in progress" : "", 7504 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT 7505 ? ", background initialization in progress" : "", 7506 state & 7507 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION 7508 ? ", capacity expansion in progress" : "", 7509 state & 7510 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK 7511 ? ", consistency check in progress" : "", 7512 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB 7513 ? ", data scrub in progress" : ""); 7514 break; 7515 } 7516 default: 7517 break; 7518 } 7519 break; 7520 } 7521 case MPI2_EVENT_IR_PHYSICAL_DISK: 7522 { 7523 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk; 7524 uint16_t devhandle, enchandle, slot; 7525 uint32_t status, state; 7526 uint8_t physdisknum, reason; 7527 7528 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *) 7529 eventreply->EventData; 7530 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl, 7531 &irPhysDisk->PhysDiskNum); 7532 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7533 &irPhysDisk->PhysDiskDevHandle); 7534 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7535 &irPhysDisk->EnclosureHandle); 7536 slot = ddi_get16(mpt->m_acc_reply_frame_hdl, 7537 &irPhysDisk->Slot); 7538 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 7539 &irPhysDisk->NewValue); 7540 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 7541 &irPhysDisk->ReasonCode); 7542 7543 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received")); 7544 7545 switch (reason) { 7546 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED: 7547 mptsas_log(mpt, CE_NOTE, 7548 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 7549 "for enclosure with handle 0x%x is now in hot " 7550 "spare pool %d", 7551 physdisknum, devhandle, slot, enchandle, 7552 (state >> 16) & 0xff); 7553 break; 7554 7555 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED: 7556 status = state; 7557 mptsas_log(mpt, CE_NOTE, 7558 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 7559 "for enclosure with handle 0x%x is now " 7560 "%s%s%s%s%s\n", physdisknum, devhandle, slot, 7561 enchandle, 7562 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME 7563 ? ", inactive" : ", active", 7564 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 7565 ? ", out of sync" : "", 7566 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED 7567 ? ", quiesced" : "", 7568 status & 7569 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED 7570 ? ", write cache enabled" : "", 7571 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET 7572 ? ", capacity expansion target" : ""); 7573 break; 7574 7575 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED: 7576 mptsas_log(mpt, CE_NOTE, 7577 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 7578 "for enclosure with handle 0x%x is now %s\n", 7579 physdisknum, devhandle, slot, enchandle, 7580 state == MPI2_RAID_PD_STATE_OPTIMAL 7581 ? "optimal" : 7582 state == MPI2_RAID_PD_STATE_REBUILDING 7583 ? "rebuilding" : 7584 state == MPI2_RAID_PD_STATE_DEGRADED 7585 ? "degraded" : 7586 state == MPI2_RAID_PD_STATE_HOT_SPARE 7587 ? "a hot spare" : 7588 state == MPI2_RAID_PD_STATE_ONLINE 7589 ? "online" : 7590 state == MPI2_RAID_PD_STATE_OFFLINE 7591 ? "offline" : 7592 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE 7593 ? "not compatible" : 7594 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED 7595 ? "not configured" : 7596 "state unknown"); 7597 break; 7598 } 7599 break; 7600 } 7601 default: 7602 NDBG20(("mptsas%d: unknown event %x received", 7603 mpt->m_instance, event)); 7604 break; 7605 } 7606 7607 /* 7608 * Return the reply frame to the free queue. 7609 */ 7610 ddi_put32(mpt->m_acc_free_queue_hdl, 7611 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm); 7612 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 7613 DDI_DMA_SYNC_FORDEV); 7614 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 7615 mpt->m_free_index = 0; 7616 } 7617 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 7618 mpt->m_free_index); 7619 mutex_exit(&mpt->m_mutex); 7620 } 7621 7622 /* 7623 * invoked from timeout() to restart qfull cmds with throttle == 0 7624 */ 7625 static void 7626 mptsas_restart_cmd(void *arg) 7627 { 7628 mptsas_t *mpt = arg; 7629 mptsas_target_t *ptgt = NULL; 7630 7631 mutex_enter(&mpt->m_mutex); 7632 7633 mpt->m_restart_cmd_timeid = 0; 7634 7635 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 7636 ptgt = refhash_next(mpt->m_targets, ptgt)) { 7637 if (ptgt->m_reset_delay == 0) { 7638 if (ptgt->m_t_throttle == QFULL_THROTTLE) { 7639 mptsas_set_throttle(mpt, ptgt, 7640 MAX_THROTTLE); 7641 } 7642 } 7643 } 7644 mptsas_restart_hba(mpt); 7645 mutex_exit(&mpt->m_mutex); 7646 } 7647 7648 void 7649 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 7650 { 7651 int slot; 7652 mptsas_slots_t *slots = mpt->m_active; 7653 int t; 7654 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 7655 7656 ASSERT(cmd != NULL); 7657 ASSERT(cmd->cmd_queued == FALSE); 7658 7659 /* 7660 * Task Management cmds are removed in their own routines. Also, 7661 * we don't want to modify timeout based on TM cmds. 7662 */ 7663 if (cmd->cmd_flags & CFLAG_TM_CMD) { 7664 return; 7665 } 7666 7667 t = Tgt(cmd); 7668 slot = cmd->cmd_slot; 7669 7670 /* 7671 * remove the cmd. 7672 */ 7673 if (cmd == slots->m_slot[slot]) { 7674 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p", (void *)cmd)); 7675 slots->m_slot[slot] = NULL; 7676 mpt->m_ncmds--; 7677 7678 /* 7679 * only decrement per target ncmds if command 7680 * has a target associated with it. 7681 */ 7682 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 7683 ptgt->m_t_ncmds--; 7684 /* 7685 * reset throttle if we just ran an untagged command 7686 * to a tagged target 7687 */ 7688 if ((ptgt->m_t_ncmds == 0) && 7689 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) { 7690 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 7691 } 7692 } 7693 7694 } 7695 7696 /* 7697 * This is all we need to do for ioc commands. 7698 */ 7699 if (cmd->cmd_flags & CFLAG_CMDIOC) { 7700 mptsas_return_to_pool(mpt, cmd); 7701 return; 7702 } 7703 7704 /* 7705 * Figure out what to set tag Q timeout for... 7706 * 7707 * Optimize: If we have duplicate's of same timeout 7708 * we're using, then we'll use it again until we run 7709 * out of duplicates. This should be the normal case 7710 * for block and raw I/O. 7711 * If no duplicates, we have to scan through tag que and 7712 * find the longest timeout value and use it. This is 7713 * going to take a while... 7714 * Add 1 to m_n_normal to account for TM request. 7715 */ 7716 if (cmd->cmd_pkt->pkt_time == ptgt->m_timebase) { 7717 if (--(ptgt->m_dups) == 0) { 7718 if (ptgt->m_t_ncmds) { 7719 mptsas_cmd_t *ssp; 7720 uint_t n = 0; 7721 ushort_t nslots = (slots->m_n_normal + 1); 7722 ushort_t i; 7723 /* 7724 * This crude check assumes we don't do 7725 * this too often which seems reasonable 7726 * for block and raw I/O. 7727 */ 7728 for (i = 0; i < nslots; i++) { 7729 ssp = slots->m_slot[i]; 7730 if (ssp && (Tgt(ssp) == t) && 7731 (ssp->cmd_pkt->pkt_time > n)) { 7732 n = ssp->cmd_pkt->pkt_time; 7733 ptgt->m_dups = 1; 7734 } else if (ssp && (Tgt(ssp) == t) && 7735 (ssp->cmd_pkt->pkt_time == n)) { 7736 ptgt->m_dups++; 7737 } 7738 } 7739 ptgt->m_timebase = n; 7740 } else { 7741 ptgt->m_dups = 0; 7742 ptgt->m_timebase = 0; 7743 } 7744 } 7745 } 7746 ptgt->m_timeout = ptgt->m_timebase; 7747 7748 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]); 7749 } 7750 7751 /* 7752 * accept all cmds on the tx_waitq if any and then 7753 * start a fresh request from the top of the device queue. 7754 * 7755 * since there are always cmds queued on the tx_waitq, and rare cmds on 7756 * the instance waitq, so this function should not be invoked in the ISR, 7757 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the 7758 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU. 7759 */ 7760 static void 7761 mptsas_restart_hba(mptsas_t *mpt) 7762 { 7763 ASSERT(mutex_owned(&mpt->m_mutex)); 7764 7765 mutex_enter(&mpt->m_tx_waitq_mutex); 7766 if (mpt->m_tx_waitq) { 7767 mptsas_accept_tx_waitq(mpt); 7768 } 7769 mutex_exit(&mpt->m_tx_waitq_mutex); 7770 mptsas_restart_waitq(mpt); 7771 } 7772 7773 /* 7774 * start a fresh request from the top of the device queue 7775 */ 7776 static void 7777 mptsas_restart_waitq(mptsas_t *mpt) 7778 { 7779 mptsas_cmd_t *cmd, *next_cmd; 7780 mptsas_target_t *ptgt = NULL; 7781 7782 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt)); 7783 7784 ASSERT(mutex_owned(&mpt->m_mutex)); 7785 7786 /* 7787 * If there is a reset delay, don't start any cmds. Otherwise, start 7788 * as many cmds as possible. 7789 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 7790 * commands is m_max_requests - 2. 7791 */ 7792 cmd = mpt->m_waitq; 7793 7794 while (cmd != NULL) { 7795 next_cmd = cmd->cmd_linkp; 7796 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 7797 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 7798 /* 7799 * passthru command get slot need 7800 * set CFLAG_PREPARED. 7801 */ 7802 cmd->cmd_flags |= CFLAG_PREPARED; 7803 mptsas_waitq_delete(mpt, cmd); 7804 mptsas_start_passthru(mpt, cmd); 7805 } 7806 cmd = next_cmd; 7807 continue; 7808 } 7809 if (cmd->cmd_flags & CFLAG_CONFIG) { 7810 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 7811 /* 7812 * Send the config page request and delete it 7813 * from the waitq. 7814 */ 7815 cmd->cmd_flags |= CFLAG_PREPARED; 7816 mptsas_waitq_delete(mpt, cmd); 7817 mptsas_start_config_page_access(mpt, cmd); 7818 } 7819 cmd = next_cmd; 7820 continue; 7821 } 7822 if (cmd->cmd_flags & CFLAG_FW_DIAG) { 7823 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 7824 /* 7825 * Send the FW Diag request and delete if from 7826 * the waitq. 7827 */ 7828 cmd->cmd_flags |= CFLAG_PREPARED; 7829 mptsas_waitq_delete(mpt, cmd); 7830 mptsas_start_diag(mpt, cmd); 7831 } 7832 cmd = next_cmd; 7833 continue; 7834 } 7835 7836 ptgt = cmd->cmd_tgt_addr; 7837 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) && 7838 (ptgt->m_t_ncmds == 0)) { 7839 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 7840 } 7841 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 7842 (ptgt && (ptgt->m_reset_delay == 0)) && 7843 (ptgt && (ptgt->m_t_ncmds < 7844 ptgt->m_t_throttle))) { 7845 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 7846 mptsas_waitq_delete(mpt, cmd); 7847 (void) mptsas_start_cmd(mpt, cmd); 7848 } 7849 } 7850 cmd = next_cmd; 7851 } 7852 } 7853 /* 7854 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait). 7855 * Accept all those queued cmds before new cmd is accept so that the 7856 * cmds are sent in order. 7857 */ 7858 static void 7859 mptsas_accept_tx_waitq(mptsas_t *mpt) 7860 { 7861 mptsas_cmd_t *cmd; 7862 7863 ASSERT(mutex_owned(&mpt->m_mutex)); 7864 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex)); 7865 7866 /* 7867 * A Bus Reset could occur at any time and flush the tx_waitq, 7868 * so we cannot count on the tx_waitq to contain even one cmd. 7869 * And when the m_tx_waitq_mutex is released and run 7870 * mptsas_accept_pkt(), the tx_waitq may be flushed. 7871 */ 7872 cmd = mpt->m_tx_waitq; 7873 for (;;) { 7874 if ((cmd = mpt->m_tx_waitq) == NULL) { 7875 mpt->m_tx_draining = 0; 7876 break; 7877 } 7878 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) { 7879 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 7880 } 7881 cmd->cmd_linkp = NULL; 7882 mutex_exit(&mpt->m_tx_waitq_mutex); 7883 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT) 7884 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed " 7885 "to accept cmd on queue\n"); 7886 mutex_enter(&mpt->m_tx_waitq_mutex); 7887 } 7888 } 7889 7890 7891 /* 7892 * mpt tag type lookup 7893 */ 7894 static char mptsas_tag_lookup[] = 7895 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG}; 7896 7897 static int 7898 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 7899 { 7900 struct scsi_pkt *pkt = CMD2PKT(cmd); 7901 uint32_t control = 0; 7902 int n; 7903 caddr_t mem; 7904 pMpi2SCSIIORequest_t io_request; 7905 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 7906 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 7907 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 7908 uint16_t SMID, io_flags = 0; 7909 uint32_t request_desc_low, request_desc_high; 7910 7911 NDBG1(("mptsas_start_cmd: cmd=0x%p", (void *)cmd)); 7912 7913 /* 7914 * Set SMID and increment index. Rollover to 1 instead of 0 if index 7915 * is at the max. 0 is an invalid SMID, so we call the first index 1. 7916 */ 7917 SMID = cmd->cmd_slot; 7918 7919 /* 7920 * It is possible for back to back device reset to 7921 * happen before the reset delay has expired. That's 7922 * ok, just let the device reset go out on the bus. 7923 */ 7924 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 7925 ASSERT(ptgt->m_reset_delay == 0); 7926 } 7927 7928 /* 7929 * if a non-tagged cmd is submitted to an active tagged target 7930 * then drain before submitting this cmd; SCSI-2 allows RQSENSE 7931 * to be untagged 7932 */ 7933 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) && 7934 (ptgt->m_t_ncmds > 1) && 7935 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) && 7936 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) { 7937 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 7938 NDBG23(("target=%d, untagged cmd, start draining\n", 7939 ptgt->m_devhdl)); 7940 7941 if (ptgt->m_reset_delay == 0) { 7942 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 7943 } 7944 7945 mptsas_remove_cmd(mpt, cmd); 7946 cmd->cmd_pkt_flags |= FLAG_HEAD; 7947 mptsas_waitq_add(mpt, cmd); 7948 } 7949 return (DDI_FAILURE); 7950 } 7951 7952 /* 7953 * Set correct tag bits. 7954 */ 7955 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) { 7956 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags & 7957 FLAG_TAGMASK) >> 12)]) { 7958 case MSG_SIMPLE_QTAG: 7959 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 7960 break; 7961 case MSG_HEAD_QTAG: 7962 control |= MPI2_SCSIIO_CONTROL_HEADOFQ; 7963 break; 7964 case MSG_ORDERED_QTAG: 7965 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ; 7966 break; 7967 default: 7968 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n"); 7969 break; 7970 } 7971 } else { 7972 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) { 7973 ptgt->m_t_throttle = 1; 7974 } 7975 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 7976 } 7977 7978 if (cmd->cmd_pkt_flags & FLAG_TLR) { 7979 control |= MPI2_SCSIIO_CONTROL_TLR_ON; 7980 } 7981 7982 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 7983 io_request = (pMpi2SCSIIORequest_t)mem; 7984 7985 bzero(io_request, sizeof (Mpi2SCSIIORequest_t)); 7986 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof 7987 (MPI2_SCSI_IO_REQUEST, SGL) / 4); 7988 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0, 7989 MPI2_FUNCTION_SCSI_IO_REQUEST); 7990 7991 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp, 7992 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR); 7993 7994 io_flags = cmd->cmd_cdblen; 7995 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags); 7996 /* 7997 * setup the Scatter/Gather DMA list for this request 7998 */ 7999 if (cmd->cmd_cookiec > 0) { 8000 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl); 8001 } else { 8002 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength, 8003 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT | 8004 MPI2_SGE_FLAGS_END_OF_BUFFER | 8005 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 8006 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT); 8007 } 8008 8009 /* 8010 * save ARQ information 8011 */ 8012 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen); 8013 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) == 8014 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) { 8015 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, 8016 cmd->cmd_ext_arqcookie.dmac_address); 8017 } else { 8018 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, 8019 cmd->cmd_arqcookie.dmac_address); 8020 } 8021 8022 ddi_put32(acc_hdl, &io_request->Control, control); 8023 8024 NDBG31(("starting message=0x%p, with cmd=0x%p", 8025 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd)); 8026 8027 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 8028 8029 /* 8030 * Build request descriptor and write it to the request desc post reg. 8031 */ 8032 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 8033 request_desc_high = ptgt->m_devhdl << 16; 8034 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high); 8035 8036 /* 8037 * Start timeout. 8038 */ 8039 #ifdef MPTSAS_TEST 8040 /* 8041 * Temporarily set timebase = 0; needed for 8042 * timeout torture test. 8043 */ 8044 if (mptsas_test_timeouts) { 8045 ptgt->m_timebase = 0; 8046 } 8047 #endif 8048 n = pkt->pkt_time - ptgt->m_timebase; 8049 8050 if (n == 0) { 8051 (ptgt->m_dups)++; 8052 ptgt->m_timeout = ptgt->m_timebase; 8053 } else if (n > 0) { 8054 ptgt->m_timeout = 8055 ptgt->m_timebase = pkt->pkt_time; 8056 ptgt->m_dups = 1; 8057 } else if (n < 0) { 8058 ptgt->m_timeout = ptgt->m_timebase; 8059 } 8060 #ifdef MPTSAS_TEST 8061 /* 8062 * Set back to a number higher than 8063 * mptsas_scsi_watchdog_tick 8064 * so timeouts will happen in mptsas_watchsubr 8065 */ 8066 if (mptsas_test_timeouts) { 8067 ptgt->m_timebase = 60; 8068 } 8069 #endif 8070 8071 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 8072 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 8073 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8074 return (DDI_FAILURE); 8075 } 8076 return (DDI_SUCCESS); 8077 } 8078 8079 /* 8080 * Select a helper thread to handle current doneq 8081 */ 8082 static void 8083 mptsas_deliver_doneq_thread(mptsas_t *mpt) 8084 { 8085 uint64_t t, i; 8086 uint32_t min = 0xffffffff; 8087 mptsas_doneq_thread_list_t *item; 8088 8089 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 8090 item = &mpt->m_doneq_thread_id[i]; 8091 /* 8092 * If the completed command on help thread[i] less than 8093 * doneq_thread_threshold, then pick the thread[i]. Otherwise 8094 * pick a thread which has least completed command. 8095 */ 8096 8097 mutex_enter(&item->mutex); 8098 if (item->len < mpt->m_doneq_thread_threshold) { 8099 t = i; 8100 mutex_exit(&item->mutex); 8101 break; 8102 } 8103 if (item->len < min) { 8104 min = item->len; 8105 t = i; 8106 } 8107 mutex_exit(&item->mutex); 8108 } 8109 mutex_enter(&mpt->m_doneq_thread_id[t].mutex); 8110 mptsas_doneq_mv(mpt, t); 8111 cv_signal(&mpt->m_doneq_thread_id[t].cv); 8112 mutex_exit(&mpt->m_doneq_thread_id[t].mutex); 8113 } 8114 8115 /* 8116 * move the current global doneq to the doneq of thead[t] 8117 */ 8118 static void 8119 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t) 8120 { 8121 mptsas_cmd_t *cmd; 8122 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8123 8124 ASSERT(mutex_owned(&item->mutex)); 8125 while ((cmd = mpt->m_doneq) != NULL) { 8126 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) { 8127 mpt->m_donetail = &mpt->m_doneq; 8128 } 8129 cmd->cmd_linkp = NULL; 8130 *item->donetail = cmd; 8131 item->donetail = &cmd->cmd_linkp; 8132 mpt->m_doneq_len--; 8133 item->len++; 8134 } 8135 } 8136 8137 void 8138 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd) 8139 { 8140 struct scsi_pkt *pkt = CMD2PKT(cmd); 8141 8142 /* Check all acc and dma handles */ 8143 if ((mptsas_check_acc_handle(mpt->m_datap) != 8144 DDI_SUCCESS) || 8145 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 8146 DDI_SUCCESS) || 8147 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 8148 DDI_SUCCESS) || 8149 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 8150 DDI_SUCCESS) || 8151 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 8152 DDI_SUCCESS) || 8153 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 8154 DDI_SUCCESS) || 8155 (mptsas_check_acc_handle(mpt->m_config_handle) != 8156 DDI_SUCCESS)) { 8157 ddi_fm_service_impact(mpt->m_dip, 8158 DDI_SERVICE_UNAFFECTED); 8159 ddi_fm_acc_err_clear(mpt->m_config_handle, 8160 DDI_FME_VER0); 8161 pkt->pkt_reason = CMD_TRAN_ERR; 8162 pkt->pkt_statistics = 0; 8163 } 8164 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 8165 DDI_SUCCESS) || 8166 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 8167 DDI_SUCCESS) || 8168 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 8169 DDI_SUCCESS) || 8170 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 8171 DDI_SUCCESS) || 8172 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 8173 DDI_SUCCESS)) { 8174 ddi_fm_service_impact(mpt->m_dip, 8175 DDI_SERVICE_UNAFFECTED); 8176 pkt->pkt_reason = CMD_TRAN_ERR; 8177 pkt->pkt_statistics = 0; 8178 } 8179 if (cmd->cmd_dmahandle && 8180 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) { 8181 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8182 pkt->pkt_reason = CMD_TRAN_ERR; 8183 pkt->pkt_statistics = 0; 8184 } 8185 if ((cmd->cmd_extra_frames && 8186 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) != 8187 DDI_SUCCESS) || 8188 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) != 8189 DDI_SUCCESS)))) { 8190 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8191 pkt->pkt_reason = CMD_TRAN_ERR; 8192 pkt->pkt_statistics = 0; 8193 } 8194 if (cmd->cmd_arqhandle && 8195 (mptsas_check_dma_handle(cmd->cmd_arqhandle) != DDI_SUCCESS)) { 8196 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8197 pkt->pkt_reason = CMD_TRAN_ERR; 8198 pkt->pkt_statistics = 0; 8199 } 8200 if (cmd->cmd_ext_arqhandle && 8201 (mptsas_check_dma_handle(cmd->cmd_ext_arqhandle) != DDI_SUCCESS)) { 8202 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8203 pkt->pkt_reason = CMD_TRAN_ERR; 8204 pkt->pkt_statistics = 0; 8205 } 8206 } 8207 8208 /* 8209 * These routines manipulate the queue of commands that 8210 * are waiting for their completion routines to be called. 8211 * The queue is usually in FIFO order but on an MP system 8212 * it's possible for the completion routines to get out 8213 * of order. If that's a problem you need to add a global 8214 * mutex around the code that calls the completion routine 8215 * in the interrupt handler. 8216 */ 8217 static void 8218 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 8219 { 8220 struct scsi_pkt *pkt = CMD2PKT(cmd); 8221 8222 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd)); 8223 8224 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0); 8225 cmd->cmd_linkp = NULL; 8226 cmd->cmd_flags |= CFLAG_FINISHED; 8227 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT; 8228 8229 mptsas_fma_check(mpt, cmd); 8230 8231 /* 8232 * only add scsi pkts that have completion routines to 8233 * the doneq. no intr cmds do not have callbacks. 8234 */ 8235 if (pkt && (pkt->pkt_comp)) { 8236 *mpt->m_donetail = cmd; 8237 mpt->m_donetail = &cmd->cmd_linkp; 8238 mpt->m_doneq_len++; 8239 } 8240 } 8241 8242 static mptsas_cmd_t * 8243 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t) 8244 { 8245 mptsas_cmd_t *cmd; 8246 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8247 8248 /* pop one off the done queue */ 8249 if ((cmd = item->doneq) != NULL) { 8250 /* if the queue is now empty fix the tail pointer */ 8251 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd)); 8252 if ((item->doneq = cmd->cmd_linkp) == NULL) { 8253 item->donetail = &item->doneq; 8254 } 8255 cmd->cmd_linkp = NULL; 8256 item->len--; 8257 } 8258 return (cmd); 8259 } 8260 8261 static void 8262 mptsas_doneq_empty(mptsas_t *mpt) 8263 { 8264 if (mpt->m_doneq && !mpt->m_in_callback) { 8265 mptsas_cmd_t *cmd, *next; 8266 struct scsi_pkt *pkt; 8267 8268 mpt->m_in_callback = 1; 8269 cmd = mpt->m_doneq; 8270 mpt->m_doneq = NULL; 8271 mpt->m_donetail = &mpt->m_doneq; 8272 mpt->m_doneq_len = 0; 8273 8274 mutex_exit(&mpt->m_mutex); 8275 /* 8276 * run the completion routines of all the 8277 * completed commands 8278 */ 8279 while (cmd != NULL) { 8280 next = cmd->cmd_linkp; 8281 cmd->cmd_linkp = NULL; 8282 /* run this command's completion routine */ 8283 cmd->cmd_flags |= CFLAG_COMPLETED; 8284 pkt = CMD2PKT(cmd); 8285 mptsas_pkt_comp(pkt, cmd); 8286 cmd = next; 8287 } 8288 mutex_enter(&mpt->m_mutex); 8289 mpt->m_in_callback = 0; 8290 } 8291 } 8292 8293 /* 8294 * These routines manipulate the target's queue of pending requests 8295 */ 8296 void 8297 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 8298 { 8299 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd)); 8300 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8301 cmd->cmd_queued = TRUE; 8302 if (ptgt) 8303 ptgt->m_t_nwait++; 8304 if (cmd->cmd_pkt_flags & FLAG_HEAD) { 8305 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) { 8306 mpt->m_waitqtail = &cmd->cmd_linkp; 8307 } 8308 mpt->m_waitq = cmd; 8309 } else { 8310 cmd->cmd_linkp = NULL; 8311 *(mpt->m_waitqtail) = cmd; 8312 mpt->m_waitqtail = &cmd->cmd_linkp; 8313 } 8314 } 8315 8316 static mptsas_cmd_t * 8317 mptsas_waitq_rm(mptsas_t *mpt) 8318 { 8319 mptsas_cmd_t *cmd; 8320 mptsas_target_t *ptgt; 8321 NDBG7(("mptsas_waitq_rm")); 8322 8323 MPTSAS_WAITQ_RM(mpt, cmd); 8324 8325 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd)); 8326 if (cmd) { 8327 ptgt = cmd->cmd_tgt_addr; 8328 if (ptgt) { 8329 ptgt->m_t_nwait--; 8330 ASSERT(ptgt->m_t_nwait >= 0); 8331 } 8332 } 8333 return (cmd); 8334 } 8335 8336 /* 8337 * remove specified cmd from the middle of the wait queue. 8338 */ 8339 static void 8340 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 8341 { 8342 mptsas_cmd_t *prevp = mpt->m_waitq; 8343 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8344 8345 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8346 (void *)mpt, (void *)cmd)); 8347 if (ptgt) { 8348 ptgt->m_t_nwait--; 8349 ASSERT(ptgt->m_t_nwait >= 0); 8350 } 8351 8352 if (prevp == cmd) { 8353 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL) 8354 mpt->m_waitqtail = &mpt->m_waitq; 8355 8356 cmd->cmd_linkp = NULL; 8357 cmd->cmd_queued = FALSE; 8358 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8359 (void *)mpt, (void *)cmd)); 8360 return; 8361 } 8362 8363 while (prevp != NULL) { 8364 if (prevp->cmd_linkp == cmd) { 8365 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 8366 mpt->m_waitqtail = &prevp->cmd_linkp; 8367 8368 cmd->cmd_linkp = NULL; 8369 cmd->cmd_queued = FALSE; 8370 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8371 (void *)mpt, (void *)cmd)); 8372 return; 8373 } 8374 prevp = prevp->cmd_linkp; 8375 } 8376 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch"); 8377 } 8378 8379 static mptsas_cmd_t * 8380 mptsas_tx_waitq_rm(mptsas_t *mpt) 8381 { 8382 mptsas_cmd_t *cmd; 8383 NDBG7(("mptsas_tx_waitq_rm")); 8384 8385 MPTSAS_TX_WAITQ_RM(mpt, cmd); 8386 8387 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd)); 8388 8389 return (cmd); 8390 } 8391 8392 /* 8393 * remove specified cmd from the middle of the tx_waitq. 8394 */ 8395 static void 8396 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 8397 { 8398 mptsas_cmd_t *prevp = mpt->m_tx_waitq; 8399 8400 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 8401 (void *)mpt, (void *)cmd)); 8402 8403 if (prevp == cmd) { 8404 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) 8405 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 8406 8407 cmd->cmd_linkp = NULL; 8408 cmd->cmd_queued = FALSE; 8409 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 8410 (void *)mpt, (void *)cmd)); 8411 return; 8412 } 8413 8414 while (prevp != NULL) { 8415 if (prevp->cmd_linkp == cmd) { 8416 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 8417 mpt->m_tx_waitqtail = &prevp->cmd_linkp; 8418 8419 cmd->cmd_linkp = NULL; 8420 cmd->cmd_queued = FALSE; 8421 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 8422 (void *)mpt, (void *)cmd)); 8423 return; 8424 } 8425 prevp = prevp->cmd_linkp; 8426 } 8427 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch"); 8428 } 8429 8430 /* 8431 * device and bus reset handling 8432 * 8433 * Notes: 8434 * - RESET_ALL: reset the controller 8435 * - RESET_TARGET: reset the target specified in scsi_address 8436 */ 8437 static int 8438 mptsas_scsi_reset(struct scsi_address *ap, int level) 8439 { 8440 mptsas_t *mpt = ADDR2MPT(ap); 8441 int rval; 8442 mptsas_tgt_private_t *tgt_private; 8443 mptsas_target_t *ptgt = NULL; 8444 8445 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private; 8446 ptgt = tgt_private->t_private; 8447 if (ptgt == NULL) { 8448 return (FALSE); 8449 } 8450 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl, 8451 level)); 8452 8453 mutex_enter(&mpt->m_mutex); 8454 /* 8455 * if we are not in panic set up a reset delay for this target 8456 */ 8457 if (!ddi_in_panic()) { 8458 mptsas_setup_bus_reset_delay(mpt); 8459 } else { 8460 drv_usecwait(mpt->m_scsi_reset_delay * 1000); 8461 } 8462 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl); 8463 mutex_exit(&mpt->m_mutex); 8464 8465 /* 8466 * The transport layer expect to only see TRUE and 8467 * FALSE. Therefore, we will adjust the return value 8468 * if mptsas_do_scsi_reset returns FAILED. 8469 */ 8470 if (rval == FAILED) 8471 rval = FALSE; 8472 return (rval); 8473 } 8474 8475 static int 8476 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl) 8477 { 8478 int rval = FALSE; 8479 uint8_t config, disk; 8480 8481 ASSERT(mutex_owned(&mpt->m_mutex)); 8482 8483 if (mptsas_debug_resets) { 8484 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d", 8485 devhdl); 8486 } 8487 8488 /* 8489 * Issue a Target Reset message to the target specified but not to a 8490 * disk making up a raid volume. Just look through the RAID config 8491 * Phys Disk list of DevHandles. If the target's DevHandle is in this 8492 * list, then don't reset this target. 8493 */ 8494 for (config = 0; config < mpt->m_num_raid_configs; config++) { 8495 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 8496 if (devhdl == mpt->m_raidconfig[config]. 8497 m_physdisk_devhdl[disk]) { 8498 return (TRUE); 8499 } 8500 } 8501 } 8502 8503 rval = mptsas_ioc_task_management(mpt, 8504 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0); 8505 8506 mptsas_doneq_empty(mpt); 8507 return (rval); 8508 } 8509 8510 static int 8511 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 8512 void (*callback)(caddr_t), caddr_t arg) 8513 { 8514 mptsas_t *mpt = ADDR2MPT(ap); 8515 8516 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target)); 8517 8518 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg, 8519 &mpt->m_mutex, &mpt->m_reset_notify_listf)); 8520 } 8521 8522 static int 8523 mptsas_get_name(struct scsi_device *sd, char *name, int len) 8524 { 8525 dev_info_t *lun_dip = NULL; 8526 8527 ASSERT(sd != NULL); 8528 ASSERT(name != NULL); 8529 lun_dip = sd->sd_dev; 8530 ASSERT(lun_dip != NULL); 8531 8532 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) { 8533 return (1); 8534 } else { 8535 return (0); 8536 } 8537 } 8538 8539 static int 8540 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len) 8541 { 8542 return (mptsas_get_name(sd, name, len)); 8543 } 8544 8545 void 8546 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what) 8547 { 8548 8549 NDBG25(("mptsas_set_throttle: throttle=%x", what)); 8550 8551 /* 8552 * if the bus is draining/quiesced, no changes to the throttles 8553 * are allowed. Not allowing change of throttles during draining 8554 * limits error recovery but will reduce draining time 8555 * 8556 * all throttles should have been set to HOLD_THROTTLE 8557 */ 8558 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) { 8559 return; 8560 } 8561 8562 if (what == HOLD_THROTTLE) { 8563 ptgt->m_t_throttle = HOLD_THROTTLE; 8564 } else if (ptgt->m_reset_delay == 0) { 8565 ptgt->m_t_throttle = what; 8566 } 8567 } 8568 8569 /* 8570 * Clean up from a device reset. 8571 * For the case of target reset, this function clears the waitq of all 8572 * commands for a particular target. For the case of abort task set, this 8573 * function clears the waitq of all commonds for a particular target/lun. 8574 */ 8575 static void 8576 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype) 8577 { 8578 mptsas_slots_t *slots = mpt->m_active; 8579 mptsas_cmd_t *cmd, *next_cmd; 8580 int slot; 8581 uchar_t reason; 8582 uint_t stat; 8583 8584 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun)); 8585 8586 /* 8587 * Make sure the I/O Controller has flushed all cmds 8588 * that are associated with this target for a target reset 8589 * and target/lun for abort task set. 8590 * Account for TM requests, which use the last SMID. 8591 */ 8592 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 8593 if ((cmd = slots->m_slot[slot]) == NULL) 8594 continue; 8595 reason = CMD_RESET; 8596 stat = STAT_DEV_RESET; 8597 switch (tasktype) { 8598 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 8599 if (Tgt(cmd) == target) { 8600 NDBG25(("mptsas_flush_target discovered non-" 8601 "NULL cmd in slot %d, tasktype 0x%x", slot, 8602 tasktype)); 8603 mptsas_dump_cmd(mpt, cmd); 8604 mptsas_remove_cmd(mpt, cmd); 8605 mptsas_set_pkt_reason(mpt, cmd, reason, stat); 8606 mptsas_doneq_add(mpt, cmd); 8607 } 8608 break; 8609 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 8610 reason = CMD_ABORTED; 8611 stat = STAT_ABORTED; 8612 /*FALLTHROUGH*/ 8613 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 8614 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 8615 8616 NDBG25(("mptsas_flush_target discovered non-" 8617 "NULL cmd in slot %d, tasktype 0x%x", slot, 8618 tasktype)); 8619 mptsas_dump_cmd(mpt, cmd); 8620 mptsas_remove_cmd(mpt, cmd); 8621 mptsas_set_pkt_reason(mpt, cmd, reason, 8622 stat); 8623 mptsas_doneq_add(mpt, cmd); 8624 } 8625 break; 8626 default: 8627 break; 8628 } 8629 } 8630 8631 /* 8632 * Flush the waitq and tx_waitq of this target's cmds 8633 */ 8634 cmd = mpt->m_waitq; 8635 8636 reason = CMD_RESET; 8637 stat = STAT_DEV_RESET; 8638 8639 switch (tasktype) { 8640 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 8641 while (cmd != NULL) { 8642 next_cmd = cmd->cmd_linkp; 8643 if (Tgt(cmd) == target) { 8644 mptsas_waitq_delete(mpt, cmd); 8645 mptsas_set_pkt_reason(mpt, cmd, 8646 reason, stat); 8647 mptsas_doneq_add(mpt, cmd); 8648 } 8649 cmd = next_cmd; 8650 } 8651 mutex_enter(&mpt->m_tx_waitq_mutex); 8652 cmd = mpt->m_tx_waitq; 8653 while (cmd != NULL) { 8654 next_cmd = cmd->cmd_linkp; 8655 if (Tgt(cmd) == target) { 8656 mptsas_tx_waitq_delete(mpt, cmd); 8657 mutex_exit(&mpt->m_tx_waitq_mutex); 8658 mptsas_set_pkt_reason(mpt, cmd, 8659 reason, stat); 8660 mptsas_doneq_add(mpt, cmd); 8661 mutex_enter(&mpt->m_tx_waitq_mutex); 8662 } 8663 cmd = next_cmd; 8664 } 8665 mutex_exit(&mpt->m_tx_waitq_mutex); 8666 break; 8667 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 8668 reason = CMD_ABORTED; 8669 stat = STAT_ABORTED; 8670 /*FALLTHROUGH*/ 8671 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 8672 while (cmd != NULL) { 8673 next_cmd = cmd->cmd_linkp; 8674 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 8675 mptsas_waitq_delete(mpt, cmd); 8676 mptsas_set_pkt_reason(mpt, cmd, 8677 reason, stat); 8678 mptsas_doneq_add(mpt, cmd); 8679 } 8680 cmd = next_cmd; 8681 } 8682 mutex_enter(&mpt->m_tx_waitq_mutex); 8683 cmd = mpt->m_tx_waitq; 8684 while (cmd != NULL) { 8685 next_cmd = cmd->cmd_linkp; 8686 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 8687 mptsas_tx_waitq_delete(mpt, cmd); 8688 mutex_exit(&mpt->m_tx_waitq_mutex); 8689 mptsas_set_pkt_reason(mpt, cmd, 8690 reason, stat); 8691 mptsas_doneq_add(mpt, cmd); 8692 mutex_enter(&mpt->m_tx_waitq_mutex); 8693 } 8694 cmd = next_cmd; 8695 } 8696 mutex_exit(&mpt->m_tx_waitq_mutex); 8697 break; 8698 default: 8699 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 8700 tasktype); 8701 break; 8702 } 8703 } 8704 8705 /* 8706 * Clean up hba state, abort all outstanding command and commands in waitq 8707 * reset timeout of all targets. 8708 */ 8709 static void 8710 mptsas_flush_hba(mptsas_t *mpt) 8711 { 8712 mptsas_slots_t *slots = mpt->m_active; 8713 mptsas_cmd_t *cmd; 8714 int slot; 8715 8716 NDBG25(("mptsas_flush_hba")); 8717 8718 /* 8719 * The I/O Controller should have already sent back 8720 * all commands via the scsi I/O reply frame. Make 8721 * sure all commands have been flushed. 8722 * Account for TM request, which use the last SMID. 8723 */ 8724 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 8725 if ((cmd = slots->m_slot[slot]) == NULL) 8726 continue; 8727 8728 if (cmd->cmd_flags & CFLAG_CMDIOC) { 8729 /* 8730 * Need to make sure to tell everyone that might be 8731 * waiting on this command that it's going to fail. If 8732 * we get here, this command will never timeout because 8733 * the active command table is going to be re-allocated, 8734 * so there will be nothing to check against a time out. 8735 * Instead, mark the command as failed due to reset. 8736 */ 8737 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 8738 STAT_BUS_RESET); 8739 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 8740 (cmd->cmd_flags & CFLAG_CONFIG) || 8741 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 8742 cmd->cmd_flags |= CFLAG_FINISHED; 8743 cv_broadcast(&mpt->m_passthru_cv); 8744 cv_broadcast(&mpt->m_config_cv); 8745 cv_broadcast(&mpt->m_fw_diag_cv); 8746 } 8747 continue; 8748 } 8749 8750 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d", 8751 slot)); 8752 mptsas_dump_cmd(mpt, cmd); 8753 8754 mptsas_remove_cmd(mpt, cmd); 8755 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 8756 mptsas_doneq_add(mpt, cmd); 8757 } 8758 8759 /* 8760 * Flush the waitq. 8761 */ 8762 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) { 8763 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 8764 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 8765 (cmd->cmd_flags & CFLAG_CONFIG) || 8766 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 8767 cmd->cmd_flags |= CFLAG_FINISHED; 8768 cv_broadcast(&mpt->m_passthru_cv); 8769 cv_broadcast(&mpt->m_config_cv); 8770 cv_broadcast(&mpt->m_fw_diag_cv); 8771 } else { 8772 mptsas_doneq_add(mpt, cmd); 8773 } 8774 } 8775 8776 /* 8777 * Flush the tx_waitq 8778 */ 8779 mutex_enter(&mpt->m_tx_waitq_mutex); 8780 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) { 8781 mutex_exit(&mpt->m_tx_waitq_mutex); 8782 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 8783 mptsas_doneq_add(mpt, cmd); 8784 mutex_enter(&mpt->m_tx_waitq_mutex); 8785 } 8786 mutex_exit(&mpt->m_tx_waitq_mutex); 8787 8788 /* 8789 * Drain the taskqs prior to reallocating resources. 8790 */ 8791 mutex_exit(&mpt->m_mutex); 8792 ddi_taskq_wait(mpt->m_event_taskq); 8793 ddi_taskq_wait(mpt->m_dr_taskq); 8794 mutex_enter(&mpt->m_mutex); 8795 } 8796 8797 /* 8798 * set pkt_reason and OR in pkt_statistics flag 8799 */ 8800 static void 8801 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason, 8802 uint_t stat) 8803 { 8804 #ifndef __lock_lint 8805 _NOTE(ARGUNUSED(mpt)) 8806 #endif 8807 8808 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x", 8809 (void *)cmd, reason, stat)); 8810 8811 if (cmd) { 8812 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) { 8813 cmd->cmd_pkt->pkt_reason = reason; 8814 } 8815 cmd->cmd_pkt->pkt_statistics |= stat; 8816 } 8817 } 8818 8819 static void 8820 mptsas_start_watch_reset_delay() 8821 { 8822 NDBG22(("mptsas_start_watch_reset_delay")); 8823 8824 mutex_enter(&mptsas_global_mutex); 8825 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) { 8826 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL, 8827 drv_usectohz((clock_t) 8828 MPTSAS_WATCH_RESET_DELAY_TICK * 1000)); 8829 ASSERT(mptsas_reset_watch != NULL); 8830 } 8831 mutex_exit(&mptsas_global_mutex); 8832 } 8833 8834 static void 8835 mptsas_setup_bus_reset_delay(mptsas_t *mpt) 8836 { 8837 mptsas_target_t *ptgt = NULL; 8838 8839 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 8840 8841 NDBG22(("mptsas_setup_bus_reset_delay")); 8842 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 8843 ptgt = refhash_next(mpt->m_targets, ptgt)) { 8844 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 8845 ptgt->m_reset_delay = mpt->m_scsi_reset_delay; 8846 } 8847 8848 mptsas_start_watch_reset_delay(); 8849 } 8850 8851 /* 8852 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every 8853 * mpt instance for active reset delays 8854 */ 8855 static void 8856 mptsas_watch_reset_delay(void *arg) 8857 { 8858 #ifndef __lock_lint 8859 _NOTE(ARGUNUSED(arg)) 8860 #endif 8861 8862 mptsas_t *mpt; 8863 int not_done = 0; 8864 8865 NDBG22(("mptsas_watch_reset_delay")); 8866 8867 mutex_enter(&mptsas_global_mutex); 8868 mptsas_reset_watch = 0; 8869 mutex_exit(&mptsas_global_mutex); 8870 rw_enter(&mptsas_global_rwlock, RW_READER); 8871 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) { 8872 if (mpt->m_tran == 0) { 8873 continue; 8874 } 8875 mutex_enter(&mpt->m_mutex); 8876 not_done += mptsas_watch_reset_delay_subr(mpt); 8877 mutex_exit(&mpt->m_mutex); 8878 } 8879 rw_exit(&mptsas_global_rwlock); 8880 8881 if (not_done) { 8882 mptsas_start_watch_reset_delay(); 8883 } 8884 } 8885 8886 static int 8887 mptsas_watch_reset_delay_subr(mptsas_t *mpt) 8888 { 8889 int done = 0; 8890 int restart = 0; 8891 mptsas_target_t *ptgt = NULL; 8892 8893 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt)); 8894 8895 ASSERT(mutex_owned(&mpt->m_mutex)); 8896 8897 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 8898 ptgt = refhash_next(mpt->m_targets, ptgt)) { 8899 if (ptgt->m_reset_delay != 0) { 8900 ptgt->m_reset_delay -= 8901 MPTSAS_WATCH_RESET_DELAY_TICK; 8902 if (ptgt->m_reset_delay <= 0) { 8903 ptgt->m_reset_delay = 0; 8904 mptsas_set_throttle(mpt, ptgt, 8905 MAX_THROTTLE); 8906 restart++; 8907 } else { 8908 done = -1; 8909 } 8910 } 8911 } 8912 8913 if (restart > 0) { 8914 mptsas_restart_hba(mpt); 8915 } 8916 return (done); 8917 } 8918 8919 #ifdef MPTSAS_TEST 8920 static void 8921 mptsas_test_reset(mptsas_t *mpt, int target) 8922 { 8923 mptsas_target_t *ptgt = NULL; 8924 8925 if (mptsas_rtest == target) { 8926 if (mptsas_do_scsi_reset(mpt, target) == TRUE) { 8927 mptsas_rtest = -1; 8928 } 8929 if (mptsas_rtest == -1) { 8930 NDBG22(("mptsas_test_reset success")); 8931 } 8932 } 8933 } 8934 #endif 8935 8936 /* 8937 * abort handling: 8938 * 8939 * Notes: 8940 * - if pkt is not NULL, abort just that command 8941 * - if pkt is NULL, abort all outstanding commands for target 8942 */ 8943 static int 8944 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 8945 { 8946 mptsas_t *mpt = ADDR2MPT(ap); 8947 int rval; 8948 mptsas_tgt_private_t *tgt_private; 8949 int target, lun; 8950 8951 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 8952 tran_tgt_private; 8953 ASSERT(tgt_private != NULL); 8954 target = tgt_private->t_private->m_devhdl; 8955 lun = tgt_private->t_lun; 8956 8957 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun)); 8958 8959 mutex_enter(&mpt->m_mutex); 8960 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt); 8961 mutex_exit(&mpt->m_mutex); 8962 return (rval); 8963 } 8964 8965 static int 8966 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt) 8967 { 8968 mptsas_cmd_t *sp = NULL; 8969 mptsas_slots_t *slots = mpt->m_active; 8970 int rval = FALSE; 8971 8972 ASSERT(mutex_owned(&mpt->m_mutex)); 8973 8974 /* 8975 * Abort the command pkt on the target/lun in ap. If pkt is 8976 * NULL, abort all outstanding commands on that target/lun. 8977 * If you can abort them, return 1, else return 0. 8978 * Each packet that's aborted should be sent back to the target 8979 * driver through the callback routine, with pkt_reason set to 8980 * CMD_ABORTED. 8981 * 8982 * abort cmd pkt on HBA hardware; clean out of outstanding 8983 * command lists, etc. 8984 */ 8985 if (pkt != NULL) { 8986 /* abort the specified packet */ 8987 sp = PKT2CMD(pkt); 8988 8989 if (sp->cmd_queued) { 8990 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted", 8991 (void *)sp)); 8992 mptsas_waitq_delete(mpt, sp); 8993 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED, 8994 STAT_ABORTED); 8995 mptsas_doneq_add(mpt, sp); 8996 rval = TRUE; 8997 goto done; 8998 } 8999 9000 /* 9001 * Have mpt firmware abort this command 9002 */ 9003 9004 if (slots->m_slot[sp->cmd_slot] != NULL) { 9005 rval = mptsas_ioc_task_management(mpt, 9006 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target, 9007 lun, NULL, 0, 0); 9008 9009 /* 9010 * The transport layer expects only TRUE and FALSE. 9011 * Therefore, if mptsas_ioc_task_management returns 9012 * FAILED we will return FALSE. 9013 */ 9014 if (rval == FAILED) 9015 rval = FALSE; 9016 goto done; 9017 } 9018 } 9019 9020 /* 9021 * If pkt is NULL then abort task set 9022 */ 9023 rval = mptsas_ioc_task_management(mpt, 9024 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0); 9025 9026 /* 9027 * The transport layer expects only TRUE and FALSE. 9028 * Therefore, if mptsas_ioc_task_management returns 9029 * FAILED we will return FALSE. 9030 */ 9031 if (rval == FAILED) 9032 rval = FALSE; 9033 9034 #ifdef MPTSAS_TEST 9035 if (rval && mptsas_test_stop) { 9036 debug_enter("mptsas_do_scsi_abort"); 9037 } 9038 #endif 9039 9040 done: 9041 mptsas_doneq_empty(mpt); 9042 return (rval); 9043 } 9044 9045 /* 9046 * capability handling: 9047 * (*tran_getcap). Get the capability named, and return its value. 9048 */ 9049 static int 9050 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly) 9051 { 9052 mptsas_t *mpt = ADDR2MPT(ap); 9053 int ckey; 9054 int rval = FALSE; 9055 9056 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x", 9057 ap->a_target, cap, tgtonly)); 9058 9059 mutex_enter(&mpt->m_mutex); 9060 9061 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9062 mutex_exit(&mpt->m_mutex); 9063 return (UNDEFINED); 9064 } 9065 9066 switch (ckey) { 9067 case SCSI_CAP_DMA_MAX: 9068 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer; 9069 break; 9070 case SCSI_CAP_ARQ: 9071 rval = TRUE; 9072 break; 9073 case SCSI_CAP_MSG_OUT: 9074 case SCSI_CAP_PARITY: 9075 case SCSI_CAP_UNTAGGED_QING: 9076 rval = TRUE; 9077 break; 9078 case SCSI_CAP_TAGGED_QING: 9079 rval = TRUE; 9080 break; 9081 case SCSI_CAP_RESET_NOTIFICATION: 9082 rval = TRUE; 9083 break; 9084 case SCSI_CAP_LINKED_CMDS: 9085 rval = FALSE; 9086 break; 9087 case SCSI_CAP_QFULL_RETRIES: 9088 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran-> 9089 tran_tgt_private))->t_private->m_qfull_retries; 9090 break; 9091 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9092 rval = drv_hztousec(((mptsas_tgt_private_t *) 9093 (ap->a_hba_tran->tran_tgt_private))-> 9094 t_private->m_qfull_retry_interval) / 1000; 9095 break; 9096 case SCSI_CAP_CDB_LEN: 9097 rval = CDB_GROUP4; 9098 break; 9099 case SCSI_CAP_INTERCONNECT_TYPE: 9100 rval = INTERCONNECT_SAS; 9101 break; 9102 case SCSI_CAP_TRAN_LAYER_RETRIES: 9103 if (mpt->m_ioc_capabilities & 9104 MPI2_IOCFACTS_CAPABILITY_TLR) 9105 rval = TRUE; 9106 else 9107 rval = FALSE; 9108 break; 9109 default: 9110 rval = UNDEFINED; 9111 break; 9112 } 9113 9114 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval)); 9115 9116 mutex_exit(&mpt->m_mutex); 9117 return (rval); 9118 } 9119 9120 /* 9121 * (*tran_setcap). Set the capability named to the value given. 9122 */ 9123 static int 9124 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly) 9125 { 9126 mptsas_t *mpt = ADDR2MPT(ap); 9127 int ckey; 9128 int rval = FALSE; 9129 9130 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x", 9131 ap->a_target, cap, value, tgtonly)); 9132 9133 if (!tgtonly) { 9134 return (rval); 9135 } 9136 9137 mutex_enter(&mpt->m_mutex); 9138 9139 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9140 mutex_exit(&mpt->m_mutex); 9141 return (UNDEFINED); 9142 } 9143 9144 switch (ckey) { 9145 case SCSI_CAP_DMA_MAX: 9146 case SCSI_CAP_MSG_OUT: 9147 case SCSI_CAP_PARITY: 9148 case SCSI_CAP_INITIATOR_ID: 9149 case SCSI_CAP_LINKED_CMDS: 9150 case SCSI_CAP_UNTAGGED_QING: 9151 case SCSI_CAP_RESET_NOTIFICATION: 9152 /* 9153 * None of these are settable via 9154 * the capability interface. 9155 */ 9156 break; 9157 case SCSI_CAP_ARQ: 9158 /* 9159 * We cannot turn off arq so return false if asked to 9160 */ 9161 if (value) { 9162 rval = TRUE; 9163 } else { 9164 rval = FALSE; 9165 } 9166 break; 9167 case SCSI_CAP_TAGGED_QING: 9168 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *) 9169 (ap->a_hba_tran->tran_tgt_private))->t_private, 9170 MAX_THROTTLE); 9171 rval = TRUE; 9172 break; 9173 case SCSI_CAP_QFULL_RETRIES: 9174 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9175 t_private->m_qfull_retries = (uchar_t)value; 9176 rval = TRUE; 9177 break; 9178 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9179 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9180 t_private->m_qfull_retry_interval = 9181 drv_usectohz(value * 1000); 9182 rval = TRUE; 9183 break; 9184 default: 9185 rval = UNDEFINED; 9186 break; 9187 } 9188 mutex_exit(&mpt->m_mutex); 9189 return (rval); 9190 } 9191 9192 /* 9193 * Utility routine for mptsas_ifsetcap/ifgetcap 9194 */ 9195 /*ARGSUSED*/ 9196 static int 9197 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp) 9198 { 9199 NDBG24(("mptsas_scsi_capchk: cap=%s", cap)); 9200 9201 if (!cap) 9202 return (FALSE); 9203 9204 *cidxp = scsi_hba_lookup_capstr(cap); 9205 return (TRUE); 9206 } 9207 9208 static int 9209 mptsas_alloc_active_slots(mptsas_t *mpt, int flag) 9210 { 9211 mptsas_slots_t *old_active = mpt->m_active; 9212 mptsas_slots_t *new_active; 9213 size_t size; 9214 9215 /* 9216 * if there are active commands, then we cannot 9217 * change size of active slots array. 9218 */ 9219 ASSERT(mpt->m_ncmds == 0); 9220 9221 size = MPTSAS_SLOTS_SIZE(mpt); 9222 new_active = kmem_zalloc(size, flag); 9223 if (new_active == NULL) { 9224 NDBG1(("new active alloc failed")); 9225 return (-1); 9226 } 9227 /* 9228 * Since SMID 0 is reserved and the TM slot is reserved, the 9229 * number of slots that can be used at any one time is 9230 * m_max_requests - 2. 9231 */ 9232 new_active->m_n_normal = (mpt->m_max_requests - 2); 9233 new_active->m_size = size; 9234 new_active->m_rotor = 1; 9235 if (old_active) 9236 mptsas_free_active_slots(mpt); 9237 mpt->m_active = new_active; 9238 9239 return (0); 9240 } 9241 9242 static void 9243 mptsas_free_active_slots(mptsas_t *mpt) 9244 { 9245 mptsas_slots_t *active = mpt->m_active; 9246 size_t size; 9247 9248 if (active == NULL) 9249 return; 9250 size = active->m_size; 9251 kmem_free(active, size); 9252 mpt->m_active = NULL; 9253 } 9254 9255 /* 9256 * Error logging, printing, and debug print routines. 9257 */ 9258 static char *mptsas_label = "mpt_sas"; 9259 9260 /*PRINTFLIKE3*/ 9261 void 9262 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...) 9263 { 9264 dev_info_t *dev; 9265 va_list ap; 9266 9267 if (mpt) { 9268 dev = mpt->m_dip; 9269 } else { 9270 dev = 0; 9271 } 9272 9273 mutex_enter(&mptsas_log_mutex); 9274 9275 va_start(ap, fmt); 9276 (void) vsprintf(mptsas_log_buf, fmt, ap); 9277 va_end(ap); 9278 9279 if (level == CE_CONT) { 9280 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf); 9281 } else { 9282 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf); 9283 } 9284 9285 mutex_exit(&mptsas_log_mutex); 9286 } 9287 9288 #ifdef MPTSAS_DEBUG 9289 /*PRINTFLIKE1*/ 9290 void 9291 mptsas_printf(char *fmt, ...) 9292 { 9293 dev_info_t *dev = 0; 9294 va_list ap; 9295 9296 mutex_enter(&mptsas_log_mutex); 9297 9298 va_start(ap, fmt); 9299 (void) vsprintf(mptsas_log_buf, fmt, ap); 9300 va_end(ap); 9301 9302 #ifdef PROM_PRINTF 9303 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf); 9304 #else 9305 scsi_log(dev, mptsas_label, SCSI_DEBUG, "%s\n", mptsas_log_buf); 9306 #endif 9307 mutex_exit(&mptsas_log_mutex); 9308 } 9309 #endif 9310 9311 /* 9312 * timeout handling 9313 */ 9314 static void 9315 mptsas_watch(void *arg) 9316 { 9317 #ifndef __lock_lint 9318 _NOTE(ARGUNUSED(arg)) 9319 #endif 9320 9321 mptsas_t *mpt; 9322 uint32_t doorbell; 9323 9324 NDBG30(("mptsas_watch")); 9325 9326 rw_enter(&mptsas_global_rwlock, RW_READER); 9327 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) { 9328 9329 mutex_enter(&mpt->m_mutex); 9330 9331 /* Skip device if not powered on */ 9332 if (mpt->m_options & MPTSAS_OPT_PM) { 9333 if (mpt->m_power_level == PM_LEVEL_D0) { 9334 (void) pm_busy_component(mpt->m_dip, 0); 9335 mpt->m_busy = 1; 9336 } else { 9337 mutex_exit(&mpt->m_mutex); 9338 continue; 9339 } 9340 } 9341 9342 /* 9343 * Check if controller is in a FAULT state. If so, reset it. 9344 */ 9345 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell); 9346 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 9347 doorbell &= MPI2_DOORBELL_DATA_MASK; 9348 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, " 9349 "code: %04x", doorbell); 9350 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 9351 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 9352 mptsas_log(mpt, CE_WARN, "Reset failed" 9353 "after fault was detected"); 9354 } 9355 } 9356 9357 /* 9358 * For now, always call mptsas_watchsubr. 9359 */ 9360 mptsas_watchsubr(mpt); 9361 9362 if (mpt->m_options & MPTSAS_OPT_PM) { 9363 mpt->m_busy = 0; 9364 (void) pm_idle_component(mpt->m_dip, 0); 9365 } 9366 9367 mutex_exit(&mpt->m_mutex); 9368 } 9369 rw_exit(&mptsas_global_rwlock); 9370 9371 mutex_enter(&mptsas_global_mutex); 9372 if (mptsas_timeouts_enabled) 9373 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 9374 mutex_exit(&mptsas_global_mutex); 9375 } 9376 9377 static void 9378 mptsas_watchsubr(mptsas_t *mpt) 9379 { 9380 int i; 9381 mptsas_cmd_t *cmd; 9382 mptsas_target_t *ptgt = NULL; 9383 9384 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 9385 9386 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt)); 9387 9388 #ifdef MPTSAS_TEST 9389 if (mptsas_enable_untagged) { 9390 mptsas_test_untagged++; 9391 } 9392 #endif 9393 9394 /* 9395 * Check for commands stuck in active slot 9396 * Account for TM requests, which use the last SMID. 9397 */ 9398 for (i = 0; i <= mpt->m_active->m_n_normal; i++) { 9399 if ((cmd = mpt->m_active->m_slot[i]) != NULL) { 9400 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 9401 cmd->cmd_active_timeout -= 9402 mptsas_scsi_watchdog_tick; 9403 if (cmd->cmd_active_timeout <= 0) { 9404 /* 9405 * There seems to be a command stuck 9406 * in the active slot. Drain throttle. 9407 */ 9408 mptsas_set_throttle(mpt, 9409 cmd->cmd_tgt_addr, 9410 DRAIN_THROTTLE); 9411 } 9412 } 9413 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 9414 (cmd->cmd_flags & CFLAG_CONFIG) || 9415 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 9416 cmd->cmd_active_timeout -= 9417 mptsas_scsi_watchdog_tick; 9418 if (cmd->cmd_active_timeout <= 0) { 9419 /* 9420 * passthrough command timeout 9421 */ 9422 cmd->cmd_flags |= (CFLAG_FINISHED | 9423 CFLAG_TIMEOUT); 9424 cv_broadcast(&mpt->m_passthru_cv); 9425 cv_broadcast(&mpt->m_config_cv); 9426 cv_broadcast(&mpt->m_fw_diag_cv); 9427 } 9428 } 9429 } 9430 } 9431 9432 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9433 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9434 /* 9435 * If we were draining due to a qfull condition, 9436 * go back to full throttle. 9437 */ 9438 if ((ptgt->m_t_throttle < MAX_THROTTLE) && 9439 (ptgt->m_t_throttle > HOLD_THROTTLE) && 9440 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) { 9441 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 9442 mptsas_restart_hba(mpt); 9443 } 9444 9445 if ((ptgt->m_t_ncmds > 0) && 9446 (ptgt->m_timebase)) { 9447 9448 if (ptgt->m_timebase <= 9449 mptsas_scsi_watchdog_tick) { 9450 ptgt->m_timebase += 9451 mptsas_scsi_watchdog_tick; 9452 continue; 9453 } 9454 9455 ptgt->m_timeout -= mptsas_scsi_watchdog_tick; 9456 9457 if (ptgt->m_timeout < 0) { 9458 mptsas_cmd_timeout(mpt, ptgt->m_devhdl); 9459 continue; 9460 } 9461 9462 if ((ptgt->m_timeout) <= 9463 mptsas_scsi_watchdog_tick) { 9464 NDBG23(("pending timeout")); 9465 mptsas_set_throttle(mpt, ptgt, 9466 DRAIN_THROTTLE); 9467 } 9468 } 9469 } 9470 } 9471 9472 /* 9473 * timeout recovery 9474 */ 9475 static void 9476 mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl) 9477 { 9478 9479 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl)); 9480 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for " 9481 "Target %d", devhdl); 9482 9483 /* 9484 * If the current target is not the target passed in, 9485 * try to reset that target. 9486 */ 9487 NDBG29(("mptsas_cmd_timeout: device reset")); 9488 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) { 9489 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout " 9490 "recovery failed!", devhdl); 9491 } 9492 } 9493 9494 /* 9495 * Device / Hotplug control 9496 */ 9497 static int 9498 mptsas_scsi_quiesce(dev_info_t *dip) 9499 { 9500 mptsas_t *mpt; 9501 scsi_hba_tran_t *tran; 9502 9503 tran = ddi_get_driver_private(dip); 9504 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 9505 return (-1); 9506 9507 return (mptsas_quiesce_bus(mpt)); 9508 } 9509 9510 static int 9511 mptsas_scsi_unquiesce(dev_info_t *dip) 9512 { 9513 mptsas_t *mpt; 9514 scsi_hba_tran_t *tran; 9515 9516 tran = ddi_get_driver_private(dip); 9517 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 9518 return (-1); 9519 9520 return (mptsas_unquiesce_bus(mpt)); 9521 } 9522 9523 static int 9524 mptsas_quiesce_bus(mptsas_t *mpt) 9525 { 9526 mptsas_target_t *ptgt = NULL; 9527 9528 NDBG28(("mptsas_quiesce_bus")); 9529 mutex_enter(&mpt->m_mutex); 9530 9531 /* Set all the throttles to zero */ 9532 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9533 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9534 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 9535 } 9536 9537 /* If there are any outstanding commands in the queue */ 9538 if (mpt->m_ncmds) { 9539 mpt->m_softstate |= MPTSAS_SS_DRAINING; 9540 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 9541 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000))); 9542 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) { 9543 /* 9544 * Quiesce has been interrupted 9545 */ 9546 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 9547 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9548 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9549 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 9550 } 9551 mptsas_restart_hba(mpt); 9552 if (mpt->m_quiesce_timeid != 0) { 9553 timeout_id_t tid = mpt->m_quiesce_timeid; 9554 mpt->m_quiesce_timeid = 0; 9555 mutex_exit(&mpt->m_mutex); 9556 (void) untimeout(tid); 9557 return (-1); 9558 } 9559 mutex_exit(&mpt->m_mutex); 9560 return (-1); 9561 } else { 9562 /* Bus has been quiesced */ 9563 ASSERT(mpt->m_quiesce_timeid == 0); 9564 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 9565 mpt->m_softstate |= MPTSAS_SS_QUIESCED; 9566 mutex_exit(&mpt->m_mutex); 9567 return (0); 9568 } 9569 } 9570 /* Bus was not busy - QUIESCED */ 9571 mutex_exit(&mpt->m_mutex); 9572 9573 return (0); 9574 } 9575 9576 static int 9577 mptsas_unquiesce_bus(mptsas_t *mpt) 9578 { 9579 mptsas_target_t *ptgt = NULL; 9580 9581 NDBG28(("mptsas_unquiesce_bus")); 9582 mutex_enter(&mpt->m_mutex); 9583 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED; 9584 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9585 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9586 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 9587 } 9588 mptsas_restart_hba(mpt); 9589 mutex_exit(&mpt->m_mutex); 9590 return (0); 9591 } 9592 9593 static void 9594 mptsas_ncmds_checkdrain(void *arg) 9595 { 9596 mptsas_t *mpt = arg; 9597 mptsas_target_t *ptgt = NULL; 9598 9599 mutex_enter(&mpt->m_mutex); 9600 if (mpt->m_softstate & MPTSAS_SS_DRAINING) { 9601 mpt->m_quiesce_timeid = 0; 9602 if (mpt->m_ncmds == 0) { 9603 /* Command queue has been drained */ 9604 cv_signal(&mpt->m_cv); 9605 } else { 9606 /* 9607 * The throttle may have been reset because 9608 * of a SCSI bus reset 9609 */ 9610 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9611 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9612 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 9613 } 9614 9615 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 9616 mpt, (MPTSAS_QUIESCE_TIMEOUT * 9617 drv_usectohz(1000000))); 9618 } 9619 } 9620 mutex_exit(&mpt->m_mutex); 9621 } 9622 9623 /*ARGSUSED*/ 9624 static void 9625 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 9626 { 9627 int i; 9628 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp; 9629 char buf[128]; 9630 9631 buf[0] = '\0'; 9632 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd, 9633 Tgt(cmd), Lun(cmd))); 9634 (void) sprintf(&buf[0], "\tcdb=["); 9635 for (i = 0; i < (int)cmd->cmd_cdblen; i++) { 9636 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++); 9637 } 9638 (void) sprintf(&buf[strlen(buf)], " ]"); 9639 NDBG25(("?%s\n", buf)); 9640 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n", 9641 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics, 9642 cmd->cmd_pkt->pkt_state)); 9643 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ? 9644 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags)); 9645 } 9646 9647 static void 9648 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd) 9649 { 9650 caddr_t memp; 9651 pMPI2RequestHeader_t request_hdrp; 9652 struct scsi_pkt *pkt = cmd->cmd_pkt; 9653 mptsas_pt_request_t *pt = pkt->pkt_ha_private; 9654 uint32_t request_size, data_size, dataout_size; 9655 uint32_t direction; 9656 ddi_dma_cookie_t data_cookie; 9657 ddi_dma_cookie_t dataout_cookie; 9658 uint32_t request_desc_low, request_desc_high = 0; 9659 uint32_t i, sense_bufp; 9660 uint8_t desc_type; 9661 uint8_t *request, function; 9662 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 9663 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 9664 9665 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 9666 9667 request = pt->request; 9668 direction = pt->direction; 9669 request_size = pt->request_size; 9670 data_size = pt->data_size; 9671 dataout_size = pt->dataout_size; 9672 data_cookie = pt->data_cookie; 9673 dataout_cookie = pt->dataout_cookie; 9674 9675 /* 9676 * Store the passthrough message in memory location 9677 * corresponding to our slot number 9678 */ 9679 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot); 9680 request_hdrp = (pMPI2RequestHeader_t)memp; 9681 bzero(memp, mpt->m_req_frame_size); 9682 9683 for (i = 0; i < request_size; i++) { 9684 bcopy(request + i, memp + i, 1); 9685 } 9686 9687 if (data_size || dataout_size) { 9688 pMpi2SGESimple64_t sgep; 9689 uint32_t sge_flags; 9690 9691 sgep = (pMpi2SGESimple64_t)((uint8_t *)request_hdrp + 9692 request_size); 9693 if (dataout_size) { 9694 9695 sge_flags = dataout_size | 9696 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 9697 MPI2_SGE_FLAGS_END_OF_BUFFER | 9698 MPI2_SGE_FLAGS_HOST_TO_IOC | 9699 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 9700 MPI2_SGE_FLAGS_SHIFT); 9701 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags); 9702 ddi_put32(acc_hdl, &sgep->Address.Low, 9703 (uint32_t)(dataout_cookie.dmac_laddress & 9704 0xffffffffull)); 9705 ddi_put32(acc_hdl, &sgep->Address.High, 9706 (uint32_t)(dataout_cookie.dmac_laddress 9707 >> 32)); 9708 sgep++; 9709 } 9710 sge_flags = data_size; 9711 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 9712 MPI2_SGE_FLAGS_LAST_ELEMENT | 9713 MPI2_SGE_FLAGS_END_OF_BUFFER | 9714 MPI2_SGE_FLAGS_END_OF_LIST | 9715 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 9716 MPI2_SGE_FLAGS_SHIFT); 9717 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 9718 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 9719 MPI2_SGE_FLAGS_SHIFT); 9720 } else { 9721 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 9722 MPI2_SGE_FLAGS_SHIFT); 9723 } 9724 ddi_put32(acc_hdl, &sgep->FlagsLength, 9725 sge_flags); 9726 ddi_put32(acc_hdl, &sgep->Address.Low, 9727 (uint32_t)(data_cookie.dmac_laddress & 9728 0xffffffffull)); 9729 ddi_put32(acc_hdl, &sgep->Address.High, 9730 (uint32_t)(data_cookie.dmac_laddress >> 32)); 9731 } 9732 9733 function = request_hdrp->Function; 9734 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 9735 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 9736 pMpi2SCSIIORequest_t scsi_io_req; 9737 9738 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp; 9739 /* 9740 * Put SGE for data and data_out buffer at the end of 9741 * scsi_io_request message header.(64 bytes in total) 9742 * Following above SGEs, the residual space will be 9743 * used by sense data. 9744 */ 9745 ddi_put8(acc_hdl, 9746 &scsi_io_req->SenseBufferLength, 9747 (uint8_t)(request_size - 64)); 9748 9749 sense_bufp = mpt->m_req_frame_dma_addr + 9750 (mpt->m_req_frame_size * cmd->cmd_slot); 9751 sense_bufp += 64; 9752 ddi_put32(acc_hdl, 9753 &scsi_io_req->SenseBufferLowAddress, sense_bufp); 9754 9755 /* 9756 * Set SGLOffset0 value 9757 */ 9758 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0, 9759 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4); 9760 9761 /* 9762 * Setup descriptor info. RAID passthrough must use the 9763 * default request descriptor which is already set, so if this 9764 * is a SCSI IO request, change the descriptor to SCSI IO. 9765 */ 9766 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 9767 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 9768 request_desc_high = (ddi_get16(acc_hdl, 9769 &scsi_io_req->DevHandle) << 16); 9770 } 9771 } 9772 9773 /* 9774 * We must wait till the message has been completed before 9775 * beginning the next message so we wait for this one to 9776 * finish. 9777 */ 9778 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 9779 request_desc_low = (cmd->cmd_slot << 16) + desc_type; 9780 cmd->cmd_rfm = NULL; 9781 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high); 9782 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 9783 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 9784 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 9785 } 9786 } 9787 9788 9789 9790 static int 9791 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 9792 uint8_t *data, uint32_t request_size, uint32_t reply_size, 9793 uint32_t data_size, uint32_t direction, uint8_t *dataout, 9794 uint32_t dataout_size, short timeout, int mode) 9795 { 9796 mptsas_pt_request_t pt; 9797 mptsas_dma_alloc_state_t data_dma_state; 9798 mptsas_dma_alloc_state_t dataout_dma_state; 9799 caddr_t memp; 9800 mptsas_cmd_t *cmd = NULL; 9801 struct scsi_pkt *pkt; 9802 uint32_t reply_len = 0, sense_len = 0; 9803 pMPI2RequestHeader_t request_hdrp; 9804 pMPI2RequestHeader_t request_msg; 9805 pMPI2DefaultReply_t reply_msg; 9806 Mpi2SCSIIOReply_t rep_msg; 9807 int i, status = 0, pt_flags = 0, rv = 0; 9808 int rvalue; 9809 uint8_t function; 9810 9811 ASSERT(mutex_owned(&mpt->m_mutex)); 9812 9813 reply_msg = (pMPI2DefaultReply_t)(&rep_msg); 9814 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY)); 9815 request_msg = kmem_zalloc(request_size, KM_SLEEP); 9816 9817 mutex_exit(&mpt->m_mutex); 9818 /* 9819 * copy in the request buffer since it could be used by 9820 * another thread when the pt request into waitq 9821 */ 9822 if (ddi_copyin(request, request_msg, request_size, mode)) { 9823 mutex_enter(&mpt->m_mutex); 9824 status = EFAULT; 9825 mptsas_log(mpt, CE_WARN, "failed to copy request data"); 9826 goto out; 9827 } 9828 mutex_enter(&mpt->m_mutex); 9829 9830 function = request_msg->Function; 9831 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) { 9832 pMpi2SCSITaskManagementRequest_t task; 9833 task = (pMpi2SCSITaskManagementRequest_t)request_msg; 9834 mptsas_setup_bus_reset_delay(mpt); 9835 rv = mptsas_ioc_task_management(mpt, task->TaskType, 9836 task->DevHandle, (int)task->LUN[1], reply, reply_size, 9837 mode); 9838 9839 if (rv != TRUE) { 9840 status = EIO; 9841 mptsas_log(mpt, CE_WARN, "task management failed"); 9842 } 9843 goto out; 9844 } 9845 9846 if (data_size != 0) { 9847 data_dma_state.size = data_size; 9848 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) { 9849 status = ENOMEM; 9850 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 9851 "resource"); 9852 goto out; 9853 } 9854 pt_flags |= MPTSAS_DATA_ALLOCATED; 9855 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 9856 mutex_exit(&mpt->m_mutex); 9857 for (i = 0; i < data_size; i++) { 9858 if (ddi_copyin(data + i, (uint8_t *) 9859 data_dma_state.memp + i, 1, mode)) { 9860 mutex_enter(&mpt->m_mutex); 9861 status = EFAULT; 9862 mptsas_log(mpt, CE_WARN, "failed to " 9863 "copy read data"); 9864 goto out; 9865 } 9866 } 9867 mutex_enter(&mpt->m_mutex); 9868 } 9869 } 9870 9871 if (dataout_size != 0) { 9872 dataout_dma_state.size = dataout_size; 9873 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) { 9874 status = ENOMEM; 9875 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 9876 "resource"); 9877 goto out; 9878 } 9879 pt_flags |= MPTSAS_DATAOUT_ALLOCATED; 9880 mutex_exit(&mpt->m_mutex); 9881 for (i = 0; i < dataout_size; i++) { 9882 if (ddi_copyin(dataout + i, (uint8_t *) 9883 dataout_dma_state.memp + i, 1, mode)) { 9884 mutex_enter(&mpt->m_mutex); 9885 mptsas_log(mpt, CE_WARN, "failed to copy out" 9886 " data"); 9887 status = EFAULT; 9888 goto out; 9889 } 9890 } 9891 mutex_enter(&mpt->m_mutex); 9892 } 9893 9894 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 9895 status = EAGAIN; 9896 mptsas_log(mpt, CE_NOTE, "event ack command pool is full"); 9897 goto out; 9898 } 9899 pt_flags |= MPTSAS_REQUEST_POOL_CMD; 9900 9901 bzero((caddr_t)cmd, sizeof (*cmd)); 9902 bzero((caddr_t)pkt, scsi_pkt_size()); 9903 bzero((caddr_t)&pt, sizeof (pt)); 9904 9905 cmd->ioc_cmd_slot = (uint32_t)(rvalue); 9906 9907 pt.request = (uint8_t *)request_msg; 9908 pt.direction = direction; 9909 pt.request_size = request_size; 9910 pt.data_size = data_size; 9911 pt.dataout_size = dataout_size; 9912 pt.data_cookie = data_dma_state.cookie; 9913 pt.dataout_cookie = dataout_dma_state.cookie; 9914 9915 /* 9916 * Form a blank cmd/pkt to store the acknowledgement message 9917 */ 9918 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0]; 9919 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 9920 pkt->pkt_ha_private = (opaque_t)&pt; 9921 pkt->pkt_flags = FLAG_HEAD; 9922 pkt->pkt_time = timeout; 9923 cmd->cmd_pkt = pkt; 9924 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU; 9925 9926 /* 9927 * Save the command in a slot 9928 */ 9929 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 9930 /* 9931 * Once passthru command get slot, set cmd_flags 9932 * CFLAG_PREPARED. 9933 */ 9934 cmd->cmd_flags |= CFLAG_PREPARED; 9935 mptsas_start_passthru(mpt, cmd); 9936 } else { 9937 mptsas_waitq_add(mpt, cmd); 9938 } 9939 9940 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 9941 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex); 9942 } 9943 9944 if (cmd->cmd_flags & CFLAG_PREPARED) { 9945 memp = mpt->m_req_frame + (mpt->m_req_frame_size * 9946 cmd->cmd_slot); 9947 request_hdrp = (pMPI2RequestHeader_t)memp; 9948 } 9949 9950 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 9951 status = ETIMEDOUT; 9952 mptsas_log(mpt, CE_WARN, "passthrough command timeout"); 9953 pt_flags |= MPTSAS_CMD_TIMEOUT; 9954 goto out; 9955 } 9956 9957 if (cmd->cmd_rfm) { 9958 /* 9959 * cmd_rfm is zero means the command reply is a CONTEXT 9960 * reply and no PCI Write to post the free reply SMFA 9961 * because no reply message frame is used. 9962 * cmd_rfm is non-zero means the reply is a ADDRESS 9963 * reply and reply message frame is used. 9964 */ 9965 pt_flags |= MPTSAS_ADDRESS_REPLY; 9966 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 9967 DDI_DMA_SYNC_FORCPU); 9968 reply_msg = (pMPI2DefaultReply_t) 9969 (mpt->m_reply_frame + (cmd->cmd_rfm - 9970 mpt->m_reply_frame_dma_addr)); 9971 } 9972 9973 mptsas_fma_check(mpt, cmd); 9974 if (pkt->pkt_reason == CMD_TRAN_ERR) { 9975 status = EAGAIN; 9976 mptsas_log(mpt, CE_WARN, "passthru fma error"); 9977 goto out; 9978 } 9979 if (pkt->pkt_reason == CMD_RESET) { 9980 status = EAGAIN; 9981 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru"); 9982 goto out; 9983 } 9984 9985 if (pkt->pkt_reason == CMD_INCOMPLETE) { 9986 status = EIO; 9987 mptsas_log(mpt, CE_WARN, "passthrough command incomplete"); 9988 goto out; 9989 } 9990 9991 mutex_exit(&mpt->m_mutex); 9992 if (cmd->cmd_flags & CFLAG_PREPARED) { 9993 function = request_hdrp->Function; 9994 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 9995 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 9996 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 9997 sense_len = reply_size - reply_len; 9998 } else { 9999 reply_len = reply_size; 10000 sense_len = 0; 10001 } 10002 10003 for (i = 0; i < reply_len; i++) { 10004 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1, 10005 mode)) { 10006 mutex_enter(&mpt->m_mutex); 10007 status = EFAULT; 10008 mptsas_log(mpt, CE_WARN, "failed to copy out " 10009 "reply data"); 10010 goto out; 10011 } 10012 } 10013 for (i = 0; i < sense_len; i++) { 10014 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i, 10015 reply + reply_len + i, 1, mode)) { 10016 mutex_enter(&mpt->m_mutex); 10017 status = EFAULT; 10018 mptsas_log(mpt, CE_WARN, "failed to copy out " 10019 "sense data"); 10020 goto out; 10021 } 10022 } 10023 } 10024 10025 if (data_size) { 10026 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) { 10027 (void) ddi_dma_sync(data_dma_state.handle, 0, 0, 10028 DDI_DMA_SYNC_FORCPU); 10029 for (i = 0; i < data_size; i++) { 10030 if (ddi_copyout((uint8_t *)( 10031 data_dma_state.memp + i), data + i, 1, 10032 mode)) { 10033 mutex_enter(&mpt->m_mutex); 10034 status = EFAULT; 10035 mptsas_log(mpt, CE_WARN, "failed to " 10036 "copy out the reply data"); 10037 goto out; 10038 } 10039 } 10040 } 10041 } 10042 mutex_enter(&mpt->m_mutex); 10043 out: 10044 /* 10045 * Put the reply frame back on the free queue, increment the free 10046 * index, and write the new index to the free index register. But only 10047 * if this reply is an ADDRESS reply. 10048 */ 10049 if (pt_flags & MPTSAS_ADDRESS_REPLY) { 10050 ddi_put32(mpt->m_acc_free_queue_hdl, 10051 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 10052 cmd->cmd_rfm); 10053 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 10054 DDI_DMA_SYNC_FORDEV); 10055 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 10056 mpt->m_free_index = 0; 10057 } 10058 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 10059 mpt->m_free_index); 10060 } 10061 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 10062 mptsas_remove_cmd(mpt, cmd); 10063 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD); 10064 } 10065 if (pt_flags & MPTSAS_REQUEST_POOL_CMD) 10066 mptsas_return_to_pool(mpt, cmd); 10067 if (pt_flags & MPTSAS_DATA_ALLOCATED) { 10068 if (mptsas_check_dma_handle(data_dma_state.handle) != 10069 DDI_SUCCESS) { 10070 ddi_fm_service_impact(mpt->m_dip, 10071 DDI_SERVICE_UNAFFECTED); 10072 status = EFAULT; 10073 } 10074 mptsas_dma_free(&data_dma_state); 10075 } 10076 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) { 10077 if (mptsas_check_dma_handle(dataout_dma_state.handle) != 10078 DDI_SUCCESS) { 10079 ddi_fm_service_impact(mpt->m_dip, 10080 DDI_SERVICE_UNAFFECTED); 10081 status = EFAULT; 10082 } 10083 mptsas_dma_free(&dataout_dma_state); 10084 } 10085 if (pt_flags & MPTSAS_CMD_TIMEOUT) { 10086 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 10087 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed"); 10088 } 10089 } 10090 if (request_msg) 10091 kmem_free(request_msg, request_size); 10092 10093 return (status); 10094 } 10095 10096 static int 10097 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode) 10098 { 10099 /* 10100 * If timeout is 0, set timeout to default of 60 seconds. 10101 */ 10102 if (data->Timeout == 0) { 10103 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT; 10104 } 10105 10106 if (((data->DataSize == 0) && 10107 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) || 10108 ((data->DataSize != 0) && 10109 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) || 10110 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) || 10111 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) && 10112 (data->DataOutSize != 0))))) { 10113 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) { 10114 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ; 10115 } else { 10116 data->DataOutSize = 0; 10117 } 10118 /* 10119 * Send passthru request messages 10120 */ 10121 return (mptsas_do_passthru(mpt, 10122 (uint8_t *)((uintptr_t)data->PtrRequest), 10123 (uint8_t *)((uintptr_t)data->PtrReply), 10124 (uint8_t *)((uintptr_t)data->PtrData), 10125 data->RequestSize, data->ReplySize, 10126 data->DataSize, data->DataDirection, 10127 (uint8_t *)((uintptr_t)data->PtrDataOut), 10128 data->DataOutSize, data->Timeout, mode)); 10129 } else { 10130 return (EINVAL); 10131 } 10132 } 10133 10134 static uint8_t 10135 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id) 10136 { 10137 uint8_t index; 10138 10139 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) { 10140 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) { 10141 return (index); 10142 } 10143 } 10144 10145 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND); 10146 } 10147 10148 static void 10149 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd) 10150 { 10151 pMpi2DiagBufferPostRequest_t pDiag_post_msg; 10152 pMpi2DiagReleaseRequest_t pDiag_release_msg; 10153 struct scsi_pkt *pkt = cmd->cmd_pkt; 10154 mptsas_diag_request_t *diag = pkt->pkt_ha_private; 10155 uint32_t request_desc_low, i; 10156 10157 ASSERT(mutex_owned(&mpt->m_mutex)); 10158 10159 /* 10160 * Form the diag message depending on the post or release function. 10161 */ 10162 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) { 10163 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t) 10164 (mpt->m_req_frame + (mpt->m_req_frame_size * 10165 cmd->cmd_slot)); 10166 bzero(pDiag_post_msg, mpt->m_req_frame_size); 10167 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function, 10168 diag->function); 10169 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType, 10170 diag->pBuffer->buffer_type); 10171 ddi_put8(mpt->m_acc_req_frame_hdl, 10172 &pDiag_post_msg->ExtendedType, 10173 diag->pBuffer->extended_type); 10174 ddi_put32(mpt->m_acc_req_frame_hdl, 10175 &pDiag_post_msg->BufferLength, 10176 diag->pBuffer->buffer_data.size); 10177 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4); 10178 i++) { 10179 ddi_put32(mpt->m_acc_req_frame_hdl, 10180 &pDiag_post_msg->ProductSpecific[i], 10181 diag->pBuffer->product_specific[i]); 10182 } 10183 ddi_put32(mpt->m_acc_req_frame_hdl, 10184 &pDiag_post_msg->BufferAddress.Low, 10185 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 10186 & 0xffffffffull)); 10187 ddi_put32(mpt->m_acc_req_frame_hdl, 10188 &pDiag_post_msg->BufferAddress.High, 10189 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 10190 >> 32)); 10191 } else { 10192 pDiag_release_msg = (pMpi2DiagReleaseRequest_t) 10193 (mpt->m_req_frame + (mpt->m_req_frame_size * 10194 cmd->cmd_slot)); 10195 bzero(pDiag_release_msg, mpt->m_req_frame_size); 10196 ddi_put8(mpt->m_acc_req_frame_hdl, 10197 &pDiag_release_msg->Function, diag->function); 10198 ddi_put8(mpt->m_acc_req_frame_hdl, 10199 &pDiag_release_msg->BufferType, 10200 diag->pBuffer->buffer_type); 10201 } 10202 10203 /* 10204 * Send the message 10205 */ 10206 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0, 10207 DDI_DMA_SYNC_FORDEV); 10208 request_desc_low = (cmd->cmd_slot << 16) + 10209 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 10210 cmd->cmd_rfm = NULL; 10211 MPTSAS_START_CMD(mpt, request_desc_low, 0); 10212 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 10213 DDI_SUCCESS) || 10214 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 10215 DDI_SUCCESS)) { 10216 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 10217 } 10218 } 10219 10220 static int 10221 mptsas_post_fw_diag_buffer(mptsas_t *mpt, 10222 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code) 10223 { 10224 mptsas_diag_request_t diag; 10225 int status, slot_num, post_flags = 0; 10226 mptsas_cmd_t *cmd = NULL; 10227 struct scsi_pkt *pkt; 10228 pMpi2DiagBufferPostReply_t reply; 10229 uint16_t iocstatus; 10230 uint32_t iocloginfo, transfer_length; 10231 10232 /* 10233 * If buffer is not enabled, just leave. 10234 */ 10235 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED; 10236 if (!pBuffer->enabled) { 10237 status = DDI_FAILURE; 10238 goto out; 10239 } 10240 10241 /* 10242 * Clear some flags initially. 10243 */ 10244 pBuffer->force_release = FALSE; 10245 pBuffer->valid_data = FALSE; 10246 pBuffer->owned_by_firmware = FALSE; 10247 10248 /* 10249 * Get a cmd buffer from the cmd buffer pool 10250 */ 10251 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 10252 status = DDI_FAILURE; 10253 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag"); 10254 goto out; 10255 } 10256 post_flags |= MPTSAS_REQUEST_POOL_CMD; 10257 10258 bzero((caddr_t)cmd, sizeof (*cmd)); 10259 bzero((caddr_t)pkt, scsi_pkt_size()); 10260 10261 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 10262 10263 diag.pBuffer = pBuffer; 10264 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST; 10265 10266 /* 10267 * Form a blank cmd/pkt to store the acknowledgement message 10268 */ 10269 pkt->pkt_ha_private = (opaque_t)&diag; 10270 pkt->pkt_flags = FLAG_HEAD; 10271 pkt->pkt_time = 60; 10272 cmd->cmd_pkt = pkt; 10273 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 10274 10275 /* 10276 * Save the command in a slot 10277 */ 10278 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 10279 /* 10280 * Once passthru command get slot, set cmd_flags 10281 * CFLAG_PREPARED. 10282 */ 10283 cmd->cmd_flags |= CFLAG_PREPARED; 10284 mptsas_start_diag(mpt, cmd); 10285 } else { 10286 mptsas_waitq_add(mpt, cmd); 10287 } 10288 10289 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 10290 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 10291 } 10292 10293 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 10294 status = DDI_FAILURE; 10295 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout"); 10296 goto out; 10297 } 10298 10299 /* 10300 * cmd_rfm points to the reply message if a reply was given. Check the 10301 * IOCStatus to make sure everything went OK with the FW diag request 10302 * and set buffer flags. 10303 */ 10304 if (cmd->cmd_rfm) { 10305 post_flags |= MPTSAS_ADDRESS_REPLY; 10306 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 10307 DDI_DMA_SYNC_FORCPU); 10308 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame + 10309 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr)); 10310 10311 /* 10312 * Get the reply message data 10313 */ 10314 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 10315 &reply->IOCStatus); 10316 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 10317 &reply->IOCLogInfo); 10318 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl, 10319 &reply->TransferLength); 10320 10321 /* 10322 * If post failed quit. 10323 */ 10324 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) { 10325 status = DDI_FAILURE; 10326 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, " 10327 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus, 10328 iocloginfo, transfer_length)); 10329 goto out; 10330 } 10331 10332 /* 10333 * Post was successful. 10334 */ 10335 pBuffer->valid_data = TRUE; 10336 pBuffer->owned_by_firmware = TRUE; 10337 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 10338 status = DDI_SUCCESS; 10339 } 10340 10341 out: 10342 /* 10343 * Put the reply frame back on the free queue, increment the free 10344 * index, and write the new index to the free index register. But only 10345 * if this reply is an ADDRESS reply. 10346 */ 10347 if (post_flags & MPTSAS_ADDRESS_REPLY) { 10348 ddi_put32(mpt->m_acc_free_queue_hdl, 10349 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 10350 cmd->cmd_rfm); 10351 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 10352 DDI_DMA_SYNC_FORDEV); 10353 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 10354 mpt->m_free_index = 0; 10355 } 10356 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 10357 mpt->m_free_index); 10358 } 10359 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 10360 mptsas_remove_cmd(mpt, cmd); 10361 post_flags &= (~MPTSAS_REQUEST_POOL_CMD); 10362 } 10363 if (post_flags & MPTSAS_REQUEST_POOL_CMD) { 10364 mptsas_return_to_pool(mpt, cmd); 10365 } 10366 10367 return (status); 10368 } 10369 10370 static int 10371 mptsas_release_fw_diag_buffer(mptsas_t *mpt, 10372 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 10373 uint32_t diag_type) 10374 { 10375 mptsas_diag_request_t diag; 10376 int status, slot_num, rel_flags = 0; 10377 mptsas_cmd_t *cmd = NULL; 10378 struct scsi_pkt *pkt; 10379 pMpi2DiagReleaseReply_t reply; 10380 uint16_t iocstatus; 10381 uint32_t iocloginfo; 10382 10383 /* 10384 * If buffer is not enabled, just leave. 10385 */ 10386 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED; 10387 if (!pBuffer->enabled) { 10388 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported " 10389 "by the IOC"); 10390 status = DDI_FAILURE; 10391 goto out; 10392 } 10393 10394 /* 10395 * Clear some flags initially. 10396 */ 10397 pBuffer->force_release = FALSE; 10398 pBuffer->valid_data = FALSE; 10399 pBuffer->owned_by_firmware = FALSE; 10400 10401 /* 10402 * Get a cmd buffer from the cmd buffer pool 10403 */ 10404 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 10405 status = DDI_FAILURE; 10406 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW " 10407 "Diag"); 10408 goto out; 10409 } 10410 rel_flags |= MPTSAS_REQUEST_POOL_CMD; 10411 10412 bzero((caddr_t)cmd, sizeof (*cmd)); 10413 bzero((caddr_t)pkt, scsi_pkt_size()); 10414 10415 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 10416 10417 diag.pBuffer = pBuffer; 10418 diag.function = MPI2_FUNCTION_DIAG_RELEASE; 10419 10420 /* 10421 * Form a blank cmd/pkt to store the acknowledgement message 10422 */ 10423 pkt->pkt_ha_private = (opaque_t)&diag; 10424 pkt->pkt_flags = FLAG_HEAD; 10425 pkt->pkt_time = 60; 10426 cmd->cmd_pkt = pkt; 10427 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 10428 10429 /* 10430 * Save the command in a slot 10431 */ 10432 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 10433 /* 10434 * Once passthru command get slot, set cmd_flags 10435 * CFLAG_PREPARED. 10436 */ 10437 cmd->cmd_flags |= CFLAG_PREPARED; 10438 mptsas_start_diag(mpt, cmd); 10439 } else { 10440 mptsas_waitq_add(mpt, cmd); 10441 } 10442 10443 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 10444 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 10445 } 10446 10447 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 10448 status = DDI_FAILURE; 10449 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout"); 10450 goto out; 10451 } 10452 10453 /* 10454 * cmd_rfm points to the reply message if a reply was given. Check the 10455 * IOCStatus to make sure everything went OK with the FW diag request 10456 * and set buffer flags. 10457 */ 10458 if (cmd->cmd_rfm) { 10459 rel_flags |= MPTSAS_ADDRESS_REPLY; 10460 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 10461 DDI_DMA_SYNC_FORCPU); 10462 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame + 10463 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr)); 10464 10465 /* 10466 * Get the reply message data 10467 */ 10468 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 10469 &reply->IOCStatus); 10470 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 10471 &reply->IOCLogInfo); 10472 10473 /* 10474 * If release failed quit. 10475 */ 10476 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) || 10477 pBuffer->owned_by_firmware) { 10478 status = DDI_FAILURE; 10479 NDBG13(("release FW Diag Buffer failed: " 10480 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, 10481 iocloginfo)); 10482 goto out; 10483 } 10484 10485 /* 10486 * Release was successful. 10487 */ 10488 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 10489 status = DDI_SUCCESS; 10490 10491 /* 10492 * If this was for an UNREGISTER diag type command, clear the 10493 * unique ID. 10494 */ 10495 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) { 10496 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 10497 } 10498 } 10499 10500 out: 10501 /* 10502 * Put the reply frame back on the free queue, increment the free 10503 * index, and write the new index to the free index register. But only 10504 * if this reply is an ADDRESS reply. 10505 */ 10506 if (rel_flags & MPTSAS_ADDRESS_REPLY) { 10507 ddi_put32(mpt->m_acc_free_queue_hdl, 10508 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 10509 cmd->cmd_rfm); 10510 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 10511 DDI_DMA_SYNC_FORDEV); 10512 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 10513 mpt->m_free_index = 0; 10514 } 10515 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 10516 mpt->m_free_index); 10517 } 10518 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 10519 mptsas_remove_cmd(mpt, cmd); 10520 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD); 10521 } 10522 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) { 10523 mptsas_return_to_pool(mpt, cmd); 10524 } 10525 10526 return (status); 10527 } 10528 10529 static int 10530 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register, 10531 uint32_t *return_code) 10532 { 10533 mptsas_fw_diagnostic_buffer_t *pBuffer; 10534 uint8_t extended_type, buffer_type, i; 10535 uint32_t buffer_size; 10536 uint32_t unique_id; 10537 int status; 10538 10539 ASSERT(mutex_owned(&mpt->m_mutex)); 10540 10541 extended_type = diag_register->ExtendedType; 10542 buffer_type = diag_register->BufferType; 10543 buffer_size = diag_register->RequestedBufferSize; 10544 unique_id = diag_register->UniqueId; 10545 10546 /* 10547 * Check for valid buffer type 10548 */ 10549 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) { 10550 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10551 return (DDI_FAILURE); 10552 } 10553 10554 /* 10555 * Get the current buffer and look up the unique ID. The unique ID 10556 * should not be found. If it is, the ID is already in use. 10557 */ 10558 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10559 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type]; 10560 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10561 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10562 return (DDI_FAILURE); 10563 } 10564 10565 /* 10566 * The buffer's unique ID should not be registered yet, and the given 10567 * unique ID cannot be 0. 10568 */ 10569 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) || 10570 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 10571 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10572 return (DDI_FAILURE); 10573 } 10574 10575 /* 10576 * If this buffer is already posted as immediate, just change owner. 10577 */ 10578 if (pBuffer->immediate && pBuffer->owned_by_firmware && 10579 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 10580 pBuffer->immediate = FALSE; 10581 pBuffer->unique_id = unique_id; 10582 return (DDI_SUCCESS); 10583 } 10584 10585 /* 10586 * Post a new buffer after checking if it's enabled. The DMA buffer 10587 * that is allocated will be contiguous (sgl_len = 1). 10588 */ 10589 if (!pBuffer->enabled) { 10590 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 10591 return (DDI_FAILURE); 10592 } 10593 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t)); 10594 pBuffer->buffer_data.size = buffer_size; 10595 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) { 10596 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for " 10597 "diag buffer: size = %d bytes", buffer_size); 10598 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 10599 return (DDI_FAILURE); 10600 } 10601 10602 /* 10603 * Copy the given info to the diag buffer and post the buffer. 10604 */ 10605 pBuffer->buffer_type = buffer_type; 10606 pBuffer->immediate = FALSE; 10607 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) { 10608 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4); 10609 i++) { 10610 pBuffer->product_specific[i] = 10611 diag_register->ProductSpecific[i]; 10612 } 10613 } 10614 pBuffer->extended_type = extended_type; 10615 pBuffer->unique_id = unique_id; 10616 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code); 10617 10618 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 10619 DDI_SUCCESS) { 10620 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in " 10621 "mptsas_diag_register."); 10622 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 10623 status = DDI_FAILURE; 10624 } 10625 10626 /* 10627 * In case there was a failure, free the DMA buffer. 10628 */ 10629 if (status == DDI_FAILURE) { 10630 mptsas_dma_free(&pBuffer->buffer_data); 10631 } 10632 10633 return (status); 10634 } 10635 10636 static int 10637 mptsas_diag_unregister(mptsas_t *mpt, 10638 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code) 10639 { 10640 mptsas_fw_diagnostic_buffer_t *pBuffer; 10641 uint8_t i; 10642 uint32_t unique_id; 10643 int status; 10644 10645 ASSERT(mutex_owned(&mpt->m_mutex)); 10646 10647 unique_id = diag_unregister->UniqueId; 10648 10649 /* 10650 * Get the current buffer and look up the unique ID. The unique ID 10651 * should be there. 10652 */ 10653 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10654 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10655 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10656 return (DDI_FAILURE); 10657 } 10658 10659 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 10660 10661 /* 10662 * Try to release the buffer from FW before freeing it. If release 10663 * fails, don't free the DMA buffer in case FW tries to access it 10664 * later. If buffer is not owned by firmware, can't release it. 10665 */ 10666 if (!pBuffer->owned_by_firmware) { 10667 status = DDI_SUCCESS; 10668 } else { 10669 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, 10670 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER); 10671 } 10672 10673 /* 10674 * At this point, return the current status no matter what happens with 10675 * the DMA buffer. 10676 */ 10677 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 10678 if (status == DDI_SUCCESS) { 10679 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 10680 DDI_SUCCESS) { 10681 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed " 10682 "in mptsas_diag_unregister."); 10683 ddi_fm_service_impact(mpt->m_dip, 10684 DDI_SERVICE_UNAFFECTED); 10685 } 10686 mptsas_dma_free(&pBuffer->buffer_data); 10687 } 10688 10689 return (status); 10690 } 10691 10692 static int 10693 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 10694 uint32_t *return_code) 10695 { 10696 mptsas_fw_diagnostic_buffer_t *pBuffer; 10697 uint8_t i; 10698 uint32_t unique_id; 10699 10700 ASSERT(mutex_owned(&mpt->m_mutex)); 10701 10702 unique_id = diag_query->UniqueId; 10703 10704 /* 10705 * If ID is valid, query on ID. 10706 * If ID is invalid, query on buffer type. 10707 */ 10708 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) { 10709 i = diag_query->BufferType; 10710 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) { 10711 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10712 return (DDI_FAILURE); 10713 } 10714 } else { 10715 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10716 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10717 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10718 return (DDI_FAILURE); 10719 } 10720 } 10721 10722 /* 10723 * Fill query structure with the diag buffer info. 10724 */ 10725 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 10726 diag_query->BufferType = pBuffer->buffer_type; 10727 diag_query->ExtendedType = pBuffer->extended_type; 10728 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) { 10729 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4); 10730 i++) { 10731 diag_query->ProductSpecific[i] = 10732 pBuffer->product_specific[i]; 10733 } 10734 } 10735 diag_query->TotalBufferSize = pBuffer->buffer_data.size; 10736 diag_query->DriverAddedBufferSize = 0; 10737 diag_query->UniqueId = pBuffer->unique_id; 10738 diag_query->ApplicationFlags = 0; 10739 diag_query->DiagnosticFlags = 0; 10740 10741 /* 10742 * Set/Clear application flags 10743 */ 10744 if (pBuffer->immediate) { 10745 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED; 10746 } else { 10747 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED; 10748 } 10749 if (pBuffer->valid_data || pBuffer->owned_by_firmware) { 10750 diag_query->ApplicationFlags |= 10751 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 10752 } else { 10753 diag_query->ApplicationFlags &= 10754 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 10755 } 10756 if (pBuffer->owned_by_firmware) { 10757 diag_query->ApplicationFlags |= 10758 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 10759 } else { 10760 diag_query->ApplicationFlags &= 10761 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 10762 } 10763 10764 return (DDI_SUCCESS); 10765 } 10766 10767 static int 10768 mptsas_diag_read_buffer(mptsas_t *mpt, 10769 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 10770 uint32_t *return_code, int ioctl_mode) 10771 { 10772 mptsas_fw_diagnostic_buffer_t *pBuffer; 10773 uint8_t i, *pData; 10774 uint32_t unique_id, byte; 10775 int status; 10776 10777 ASSERT(mutex_owned(&mpt->m_mutex)); 10778 10779 unique_id = diag_read_buffer->UniqueId; 10780 10781 /* 10782 * Get the current buffer and look up the unique ID. The unique ID 10783 * should be there. 10784 */ 10785 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10786 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10787 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10788 return (DDI_FAILURE); 10789 } 10790 10791 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 10792 10793 /* 10794 * Make sure requested read is within limits 10795 */ 10796 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead > 10797 pBuffer->buffer_data.size) { 10798 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10799 return (DDI_FAILURE); 10800 } 10801 10802 /* 10803 * Copy the requested data from DMA to the diag_read_buffer. The DMA 10804 * buffer that was allocated is one contiguous buffer. 10805 */ 10806 pData = (uint8_t *)(pBuffer->buffer_data.memp + 10807 diag_read_buffer->StartingOffset); 10808 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0, 10809 DDI_DMA_SYNC_FORCPU); 10810 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) { 10811 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode) 10812 != 0) { 10813 return (DDI_FAILURE); 10814 } 10815 } 10816 diag_read_buffer->Status = 0; 10817 10818 /* 10819 * Set or clear the Force Release flag. 10820 */ 10821 if (pBuffer->force_release) { 10822 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 10823 } else { 10824 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 10825 } 10826 10827 /* 10828 * If buffer is to be reregistered, make sure it's not already owned by 10829 * firmware first. 10830 */ 10831 status = DDI_SUCCESS; 10832 if (!pBuffer->owned_by_firmware) { 10833 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) { 10834 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, 10835 return_code); 10836 } 10837 } 10838 10839 return (status); 10840 } 10841 10842 static int 10843 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release, 10844 uint32_t *return_code) 10845 { 10846 mptsas_fw_diagnostic_buffer_t *pBuffer; 10847 uint8_t i; 10848 uint32_t unique_id; 10849 int status; 10850 10851 ASSERT(mutex_owned(&mpt->m_mutex)); 10852 10853 unique_id = diag_release->UniqueId; 10854 10855 /* 10856 * Get the current buffer and look up the unique ID. The unique ID 10857 * should be there. 10858 */ 10859 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10860 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10861 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10862 return (DDI_FAILURE); 10863 } 10864 10865 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 10866 10867 /* 10868 * If buffer is not owned by firmware, it's already been released. 10869 */ 10870 if (!pBuffer->owned_by_firmware) { 10871 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED; 10872 return (DDI_FAILURE); 10873 } 10874 10875 /* 10876 * Release the buffer. 10877 */ 10878 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code, 10879 MPTSAS_FW_DIAG_TYPE_RELEASE); 10880 return (status); 10881 } 10882 10883 static int 10884 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action, 10885 uint32_t length, uint32_t *return_code, int ioctl_mode) 10886 { 10887 mptsas_fw_diag_register_t diag_register; 10888 mptsas_fw_diag_unregister_t diag_unregister; 10889 mptsas_fw_diag_query_t diag_query; 10890 mptsas_diag_read_buffer_t diag_read_buffer; 10891 mptsas_fw_diag_release_t diag_release; 10892 int status = DDI_SUCCESS; 10893 uint32_t original_return_code, read_buf_len; 10894 10895 ASSERT(mutex_owned(&mpt->m_mutex)); 10896 10897 original_return_code = *return_code; 10898 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 10899 10900 switch (action) { 10901 case MPTSAS_FW_DIAG_TYPE_REGISTER: 10902 if (!length) { 10903 *return_code = 10904 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10905 status = DDI_FAILURE; 10906 break; 10907 } 10908 if (ddi_copyin(diag_action, &diag_register, 10909 sizeof (diag_register), ioctl_mode) != 0) { 10910 return (DDI_FAILURE); 10911 } 10912 status = mptsas_diag_register(mpt, &diag_register, 10913 return_code); 10914 break; 10915 10916 case MPTSAS_FW_DIAG_TYPE_UNREGISTER: 10917 if (length < sizeof (diag_unregister)) { 10918 *return_code = 10919 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10920 status = DDI_FAILURE; 10921 break; 10922 } 10923 if (ddi_copyin(diag_action, &diag_unregister, 10924 sizeof (diag_unregister), ioctl_mode) != 0) { 10925 return (DDI_FAILURE); 10926 } 10927 status = mptsas_diag_unregister(mpt, &diag_unregister, 10928 return_code); 10929 break; 10930 10931 case MPTSAS_FW_DIAG_TYPE_QUERY: 10932 if (length < sizeof (diag_query)) { 10933 *return_code = 10934 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10935 status = DDI_FAILURE; 10936 break; 10937 } 10938 if (ddi_copyin(diag_action, &diag_query, 10939 sizeof (diag_query), ioctl_mode) != 0) { 10940 return (DDI_FAILURE); 10941 } 10942 status = mptsas_diag_query(mpt, &diag_query, 10943 return_code); 10944 if (status == DDI_SUCCESS) { 10945 if (ddi_copyout(&diag_query, diag_action, 10946 sizeof (diag_query), ioctl_mode) != 0) { 10947 return (DDI_FAILURE); 10948 } 10949 } 10950 break; 10951 10952 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER: 10953 if (ddi_copyin(diag_action, &diag_read_buffer, 10954 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) { 10955 return (DDI_FAILURE); 10956 } 10957 read_buf_len = sizeof (diag_read_buffer) - 10958 sizeof (diag_read_buffer.DataBuffer) + 10959 diag_read_buffer.BytesToRead; 10960 if (length < read_buf_len) { 10961 *return_code = 10962 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10963 status = DDI_FAILURE; 10964 break; 10965 } 10966 status = mptsas_diag_read_buffer(mpt, 10967 &diag_read_buffer, diag_action + 10968 sizeof (diag_read_buffer) - 4, return_code, 10969 ioctl_mode); 10970 if (status == DDI_SUCCESS) { 10971 if (ddi_copyout(&diag_read_buffer, diag_action, 10972 sizeof (diag_read_buffer) - 4, ioctl_mode) 10973 != 0) { 10974 return (DDI_FAILURE); 10975 } 10976 } 10977 break; 10978 10979 case MPTSAS_FW_DIAG_TYPE_RELEASE: 10980 if (length < sizeof (diag_release)) { 10981 *return_code = 10982 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10983 status = DDI_FAILURE; 10984 break; 10985 } 10986 if (ddi_copyin(diag_action, &diag_release, 10987 sizeof (diag_release), ioctl_mode) != 0) { 10988 return (DDI_FAILURE); 10989 } 10990 status = mptsas_diag_release(mpt, &diag_release, 10991 return_code); 10992 break; 10993 10994 default: 10995 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10996 status = DDI_FAILURE; 10997 break; 10998 } 10999 11000 if ((status == DDI_FAILURE) && 11001 (original_return_code == MPTSAS_FW_DIAG_NEW) && 11002 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) { 11003 status = DDI_SUCCESS; 11004 } 11005 11006 return (status); 11007 } 11008 11009 static int 11010 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode) 11011 { 11012 int status; 11013 mptsas_diag_action_t driver_data; 11014 11015 ASSERT(mutex_owned(&mpt->m_mutex)); 11016 11017 /* 11018 * Copy the user data to a driver data buffer. 11019 */ 11020 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t), 11021 mode) == 0) { 11022 /* 11023 * Send diag action request if Action is valid 11024 */ 11025 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER || 11026 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER || 11027 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY || 11028 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER || 11029 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) { 11030 status = mptsas_do_diag_action(mpt, driver_data.Action, 11031 (void *)(uintptr_t)driver_data.PtrDiagAction, 11032 driver_data.Length, &driver_data.ReturnCode, 11033 mode); 11034 if (status == DDI_SUCCESS) { 11035 if (ddi_copyout(&driver_data.ReturnCode, 11036 &user_data->ReturnCode, 11037 sizeof (user_data->ReturnCode), mode) 11038 != 0) { 11039 status = EFAULT; 11040 } else { 11041 status = 0; 11042 } 11043 } else { 11044 status = EIO; 11045 } 11046 } else { 11047 status = EINVAL; 11048 } 11049 } else { 11050 status = EFAULT; 11051 } 11052 11053 return (status); 11054 } 11055 11056 /* 11057 * This routine handles the "event query" ioctl. 11058 */ 11059 static int 11060 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode, 11061 int *rval) 11062 { 11063 int status; 11064 mptsas_event_query_t driverdata; 11065 uint8_t i; 11066 11067 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE; 11068 11069 mutex_enter(&mpt->m_mutex); 11070 for (i = 0; i < 4; i++) { 11071 driverdata.Types[i] = mpt->m_event_mask[i]; 11072 } 11073 mutex_exit(&mpt->m_mutex); 11074 11075 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) { 11076 status = EFAULT; 11077 } else { 11078 *rval = MPTIOCTL_STATUS_GOOD; 11079 status = 0; 11080 } 11081 11082 return (status); 11083 } 11084 11085 /* 11086 * This routine handles the "event enable" ioctl. 11087 */ 11088 static int 11089 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode, 11090 int *rval) 11091 { 11092 int status; 11093 mptsas_event_enable_t driverdata; 11094 uint8_t i; 11095 11096 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 11097 mutex_enter(&mpt->m_mutex); 11098 for (i = 0; i < 4; i++) { 11099 mpt->m_event_mask[i] = driverdata.Types[i]; 11100 } 11101 mutex_exit(&mpt->m_mutex); 11102 11103 *rval = MPTIOCTL_STATUS_GOOD; 11104 status = 0; 11105 } else { 11106 status = EFAULT; 11107 } 11108 return (status); 11109 } 11110 11111 /* 11112 * This routine handles the "event report" ioctl. 11113 */ 11114 static int 11115 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode, 11116 int *rval) 11117 { 11118 int status; 11119 mptsas_event_report_t driverdata; 11120 11121 mutex_enter(&mpt->m_mutex); 11122 11123 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size), 11124 mode) == 0) { 11125 if (driverdata.Size >= sizeof (mpt->m_events)) { 11126 if (ddi_copyout(mpt->m_events, data->Events, 11127 sizeof (mpt->m_events), mode) != 0) { 11128 status = EFAULT; 11129 } else { 11130 if (driverdata.Size > sizeof (mpt->m_events)) { 11131 driverdata.Size = 11132 sizeof (mpt->m_events); 11133 if (ddi_copyout(&driverdata.Size, 11134 &data->Size, 11135 sizeof (driverdata.Size), 11136 mode) != 0) { 11137 status = EFAULT; 11138 } else { 11139 *rval = MPTIOCTL_STATUS_GOOD; 11140 status = 0; 11141 } 11142 } else { 11143 *rval = MPTIOCTL_STATUS_GOOD; 11144 status = 0; 11145 } 11146 } 11147 } else { 11148 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 11149 status = 0; 11150 } 11151 } else { 11152 status = EFAULT; 11153 } 11154 11155 mutex_exit(&mpt->m_mutex); 11156 return (status); 11157 } 11158 11159 static void 11160 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 11161 { 11162 int *reg_data; 11163 uint_t reglen; 11164 11165 /* 11166 * Lookup the 'reg' property and extract the other data 11167 */ 11168 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 11169 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 11170 DDI_PROP_SUCCESS) { 11171 /* 11172 * Extract the PCI data from the 'reg' property first DWORD. 11173 * The entry looks like the following: 11174 * First DWORD: 11175 * Bits 0 - 7 8-bit Register number 11176 * Bits 8 - 10 3-bit Function number 11177 * Bits 11 - 15 5-bit Device number 11178 * Bits 16 - 23 8-bit Bus number 11179 * Bits 24 - 25 2-bit Address Space type identifier 11180 * 11181 */ 11182 adapter_data->PciInformation.u.bits.BusNumber = 11183 (reg_data[0] & 0x00FF0000) >> 16; 11184 adapter_data->PciInformation.u.bits.DeviceNumber = 11185 (reg_data[0] & 0x0000F800) >> 11; 11186 adapter_data->PciInformation.u.bits.FunctionNumber = 11187 (reg_data[0] & 0x00000700) >> 8; 11188 ddi_prop_free((void *)reg_data); 11189 } else { 11190 /* 11191 * If we can't determine the PCI data then we fill in FF's for 11192 * the data to indicate this. 11193 */ 11194 adapter_data->PCIDeviceHwId = 0xFFFFFFFF; 11195 adapter_data->MpiPortNumber = 0xFFFFFFFF; 11196 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF; 11197 } 11198 11199 /* 11200 * Saved in the mpt->m_fwversion 11201 */ 11202 adapter_data->MpiFirmwareVersion = mpt->m_fwversion; 11203 } 11204 11205 static void 11206 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 11207 { 11208 char *driver_verstr = MPTSAS_MOD_STRING; 11209 11210 mptsas_lookup_pci_data(mpt, adapter_data); 11211 adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS2; 11212 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid; 11213 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid; 11214 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid; 11215 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid; 11216 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr); 11217 adapter_data->BiosVersion = 0; 11218 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion); 11219 } 11220 11221 static void 11222 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info) 11223 { 11224 int *reg_data, i; 11225 uint_t reglen; 11226 11227 /* 11228 * Lookup the 'reg' property and extract the other data 11229 */ 11230 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 11231 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 11232 DDI_PROP_SUCCESS) { 11233 /* 11234 * Extract the PCI data from the 'reg' property first DWORD. 11235 * The entry looks like the following: 11236 * First DWORD: 11237 * Bits 8 - 10 3-bit Function number 11238 * Bits 11 - 15 5-bit Device number 11239 * Bits 16 - 23 8-bit Bus number 11240 */ 11241 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16; 11242 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11; 11243 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8; 11244 ddi_prop_free((void *)reg_data); 11245 } else { 11246 /* 11247 * If we can't determine the PCI info then we fill in FF's for 11248 * the data to indicate this. 11249 */ 11250 pci_info->BusNumber = 0xFFFFFFFF; 11251 pci_info->DeviceNumber = 0xFF; 11252 pci_info->FunctionNumber = 0xFF; 11253 } 11254 11255 /* 11256 * Now get the interrupt vector and the pci header. The vector can 11257 * only be 0 right now. The header is the first 256 bytes of config 11258 * space. 11259 */ 11260 pci_info->InterruptVector = 0; 11261 for (i = 0; i < sizeof (pci_info->PciHeader); i++) { 11262 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle, 11263 i); 11264 } 11265 } 11266 11267 static int 11268 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode) 11269 { 11270 int status = 0; 11271 mptsas_reg_access_t driverdata; 11272 11273 mutex_enter(&mpt->m_mutex); 11274 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 11275 switch (driverdata.Command) { 11276 /* 11277 * IO access is not supported. 11278 */ 11279 case REG_IO_READ: 11280 case REG_IO_WRITE: 11281 mptsas_log(mpt, CE_WARN, "IO access is not " 11282 "supported. Use memory access."); 11283 status = EINVAL; 11284 break; 11285 11286 case REG_MEM_READ: 11287 driverdata.RegData = ddi_get32(mpt->m_datap, 11288 (uint32_t *)(void *)mpt->m_reg + 11289 driverdata.RegOffset); 11290 if (ddi_copyout(&driverdata.RegData, 11291 &data->RegData, 11292 sizeof (driverdata.RegData), mode) != 0) { 11293 mptsas_log(mpt, CE_WARN, "Register " 11294 "Read Failed"); 11295 status = EFAULT; 11296 } 11297 break; 11298 11299 case REG_MEM_WRITE: 11300 ddi_put32(mpt->m_datap, 11301 (uint32_t *)(void *)mpt->m_reg + 11302 driverdata.RegOffset, 11303 driverdata.RegData); 11304 break; 11305 11306 default: 11307 status = EINVAL; 11308 break; 11309 } 11310 } else { 11311 status = EFAULT; 11312 } 11313 11314 mutex_exit(&mpt->m_mutex); 11315 return (status); 11316 } 11317 11318 static int 11319 led_control(mptsas_t *mpt, intptr_t data, int mode) 11320 { 11321 int ret = 0; 11322 mptsas_led_control_t lc; 11323 mptsas_target_t *ptgt; 11324 11325 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) { 11326 return (EFAULT); 11327 } 11328 11329 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET && 11330 lc.Command != MPTSAS_LEDCTL_FLAG_GET) || 11331 lc.Led < MPTSAS_LEDCTL_LED_MIN || 11332 lc.Led > MPTSAS_LEDCTL_LED_MAX || 11333 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 && 11334 lc.LedStatus != 1)) { 11335 return (EINVAL); 11336 } 11337 11338 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) || 11339 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0)) 11340 return (EACCES); 11341 11342 /* Locate the target we're interrogating... */ 11343 mutex_enter(&mpt->m_mutex); 11344 ptgt = refhash_linear_search(mpt->m_targets, 11345 mptsas_target_eval_slot, &lc); 11346 if (ptgt == NULL) { 11347 /* We could not find a target for that enclosure/slot. */ 11348 mutex_exit(&mpt->m_mutex); 11349 return (ENOENT); 11350 } 11351 11352 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) { 11353 /* Update our internal LED state. */ 11354 ptgt->m_led_status &= ~(1 << (lc.Led - 1)); 11355 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1); 11356 11357 /* Flush it to the controller. */ 11358 ret = mptsas_flush_led_status(mpt, ptgt); 11359 mutex_exit(&mpt->m_mutex); 11360 return (ret); 11361 } 11362 11363 /* Return our internal LED state. */ 11364 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1; 11365 mutex_exit(&mpt->m_mutex); 11366 11367 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) { 11368 return (EFAULT); 11369 } 11370 11371 return (0); 11372 } 11373 11374 static int 11375 get_disk_info(mptsas_t *mpt, intptr_t data, int mode) 11376 { 11377 uint16_t i = 0; 11378 uint16_t count = 0; 11379 int ret = 0; 11380 mptsas_target_t *ptgt; 11381 mptsas_disk_info_t *di; 11382 STRUCT_DECL(mptsas_get_disk_info, gdi); 11383 11384 if ((mode & FREAD) == 0) 11385 return (EACCES); 11386 11387 STRUCT_INIT(gdi, get_udatamodel()); 11388 11389 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi), 11390 mode) != 0) { 11391 return (EFAULT); 11392 } 11393 11394 /* Find out how many targets there are. */ 11395 mutex_enter(&mpt->m_mutex); 11396 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 11397 ptgt = refhash_next(mpt->m_targets, ptgt)) { 11398 count++; 11399 } 11400 mutex_exit(&mpt->m_mutex); 11401 11402 /* 11403 * If we haven't been asked to copy out information on each target, 11404 * then just return the count. 11405 */ 11406 STRUCT_FSET(gdi, DiskCount, count); 11407 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL) 11408 goto copy_out; 11409 11410 /* 11411 * If we haven't been given a large enough buffer to copy out into, 11412 * let the caller know. 11413 */ 11414 if (STRUCT_FGET(gdi, DiskInfoArraySize) < 11415 count * sizeof (mptsas_disk_info_t)) { 11416 ret = ENOSPC; 11417 goto copy_out; 11418 } 11419 11420 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP); 11421 11422 mutex_enter(&mpt->m_mutex); 11423 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 11424 ptgt = refhash_next(mpt->m_targets, ptgt)) { 11425 if (i >= count) { 11426 /* 11427 * The number of targets changed while we weren't 11428 * looking, so give up. 11429 */ 11430 refhash_rele(mpt->m_targets, ptgt); 11431 mutex_exit(&mpt->m_mutex); 11432 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 11433 return (EAGAIN); 11434 } 11435 di[i].Instance = mpt->m_instance; 11436 di[i].Enclosure = ptgt->m_enclosure; 11437 di[i].Slot = ptgt->m_slot_num; 11438 di[i].SasAddress = ptgt->m_addr.mta_wwn; 11439 i++; 11440 } 11441 mutex_exit(&mpt->m_mutex); 11442 STRUCT_FSET(gdi, DiskCount, i); 11443 11444 /* Copy out the disk information to the caller. */ 11445 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray), 11446 i * sizeof (mptsas_disk_info_t), mode) != 0) { 11447 ret = EFAULT; 11448 } 11449 11450 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 11451 11452 copy_out: 11453 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi), 11454 mode) != 0) { 11455 ret = EFAULT; 11456 } 11457 11458 return (ret); 11459 } 11460 11461 static int 11462 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp, 11463 int *rval) 11464 { 11465 int status = 0; 11466 mptsas_t *mpt; 11467 mptsas_update_flash_t flashdata; 11468 mptsas_pass_thru_t passthru_data; 11469 mptsas_adapter_data_t adapter_data; 11470 mptsas_pci_info_t pci_info; 11471 int copylen; 11472 11473 int iport_flag = 0; 11474 dev_info_t *dip = NULL; 11475 mptsas_phymask_t phymask = 0; 11476 struct devctl_iocdata *dcp = NULL; 11477 char *addr = NULL; 11478 mptsas_target_t *ptgt = NULL; 11479 11480 *rval = MPTIOCTL_STATUS_GOOD; 11481 if (secpolicy_sys_config(credp, B_FALSE) != 0) { 11482 return (EPERM); 11483 } 11484 11485 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev))); 11486 if (mpt == NULL) { 11487 /* 11488 * Called from iport node, get the states 11489 */ 11490 iport_flag = 1; 11491 dip = mptsas_get_dip_from_dev(dev, &phymask); 11492 if (dip == NULL) { 11493 return (ENXIO); 11494 } 11495 mpt = DIP2MPT(dip); 11496 } 11497 /* Make sure power level is D0 before accessing registers */ 11498 mutex_enter(&mpt->m_mutex); 11499 if (mpt->m_options & MPTSAS_OPT_PM) { 11500 (void) pm_busy_component(mpt->m_dip, 0); 11501 if (mpt->m_power_level != PM_LEVEL_D0) { 11502 mutex_exit(&mpt->m_mutex); 11503 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) != 11504 DDI_SUCCESS) { 11505 mptsas_log(mpt, CE_WARN, 11506 "mptsas%d: mptsas_ioctl: Raise power " 11507 "request failed.", mpt->m_instance); 11508 (void) pm_idle_component(mpt->m_dip, 0); 11509 return (ENXIO); 11510 } 11511 } else { 11512 mutex_exit(&mpt->m_mutex); 11513 } 11514 } else { 11515 mutex_exit(&mpt->m_mutex); 11516 } 11517 11518 if (iport_flag) { 11519 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval); 11520 if (status != 0) { 11521 goto out; 11522 } 11523 /* 11524 * The following code control the OK2RM LED, it doesn't affect 11525 * the ioctl return status. 11526 */ 11527 if ((cmd == DEVCTL_DEVICE_ONLINE) || 11528 (cmd == DEVCTL_DEVICE_OFFLINE)) { 11529 if (ndi_dc_allochdl((void *)data, &dcp) != 11530 NDI_SUCCESS) { 11531 goto out; 11532 } 11533 addr = ndi_dc_getaddr(dcp); 11534 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask); 11535 if (ptgt == NULL) { 11536 NDBG14(("mptsas_ioctl led control: tgt %s not " 11537 "found", addr)); 11538 ndi_dc_freehdl(dcp); 11539 goto out; 11540 } 11541 mutex_enter(&mpt->m_mutex); 11542 if (cmd == DEVCTL_DEVICE_ONLINE) { 11543 ptgt->m_tgt_unconfigured = 0; 11544 } else if (cmd == DEVCTL_DEVICE_OFFLINE) { 11545 ptgt->m_tgt_unconfigured = 1; 11546 } 11547 if (cmd == DEVCTL_DEVICE_OFFLINE) { 11548 ptgt->m_led_status |= 11549 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)); 11550 } else { 11551 ptgt->m_led_status &= 11552 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)); 11553 } 11554 (void) mptsas_flush_led_status(mpt, ptgt); 11555 mutex_exit(&mpt->m_mutex); 11556 ndi_dc_freehdl(dcp); 11557 } 11558 goto out; 11559 } 11560 switch (cmd) { 11561 case MPTIOCTL_GET_DISK_INFO: 11562 status = get_disk_info(mpt, data, mode); 11563 break; 11564 case MPTIOCTL_LED_CONTROL: 11565 status = led_control(mpt, data, mode); 11566 break; 11567 case MPTIOCTL_UPDATE_FLASH: 11568 if (ddi_copyin((void *)data, &flashdata, 11569 sizeof (struct mptsas_update_flash), mode)) { 11570 status = EFAULT; 11571 break; 11572 } 11573 11574 mutex_enter(&mpt->m_mutex); 11575 if (mptsas_update_flash(mpt, 11576 (caddr_t)(long)flashdata.PtrBuffer, 11577 flashdata.ImageSize, flashdata.ImageType, mode)) { 11578 status = EFAULT; 11579 } 11580 11581 /* 11582 * Reset the chip to start using the new 11583 * firmware. Reset if failed also. 11584 */ 11585 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 11586 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 11587 status = EFAULT; 11588 } 11589 mutex_exit(&mpt->m_mutex); 11590 break; 11591 case MPTIOCTL_PASS_THRU: 11592 /* 11593 * The user has requested to pass through a command to 11594 * be executed by the MPT firmware. Call our routine 11595 * which does this. Only allow one passthru IOCTL at 11596 * one time. Other threads will block on 11597 * m_passthru_mutex, which is of adaptive variant. 11598 */ 11599 if (ddi_copyin((void *)data, &passthru_data, 11600 sizeof (mptsas_pass_thru_t), mode)) { 11601 status = EFAULT; 11602 break; 11603 } 11604 mutex_enter(&mpt->m_passthru_mutex); 11605 mutex_enter(&mpt->m_mutex); 11606 status = mptsas_pass_thru(mpt, &passthru_data, mode); 11607 mutex_exit(&mpt->m_mutex); 11608 mutex_exit(&mpt->m_passthru_mutex); 11609 11610 break; 11611 case MPTIOCTL_GET_ADAPTER_DATA: 11612 /* 11613 * The user has requested to read adapter data. Call 11614 * our routine which does this. 11615 */ 11616 bzero(&adapter_data, sizeof (mptsas_adapter_data_t)); 11617 if (ddi_copyin((void *)data, (void *)&adapter_data, 11618 sizeof (mptsas_adapter_data_t), mode)) { 11619 status = EFAULT; 11620 break; 11621 } 11622 if (adapter_data.StructureLength >= 11623 sizeof (mptsas_adapter_data_t)) { 11624 adapter_data.StructureLength = (uint32_t) 11625 sizeof (mptsas_adapter_data_t); 11626 copylen = sizeof (mptsas_adapter_data_t); 11627 mutex_enter(&mpt->m_mutex); 11628 mptsas_read_adapter_data(mpt, &adapter_data); 11629 mutex_exit(&mpt->m_mutex); 11630 } else { 11631 adapter_data.StructureLength = (uint32_t) 11632 sizeof (mptsas_adapter_data_t); 11633 copylen = sizeof (adapter_data.StructureLength); 11634 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 11635 } 11636 if (ddi_copyout((void *)(&adapter_data), (void *)data, 11637 copylen, mode) != 0) { 11638 status = EFAULT; 11639 } 11640 break; 11641 case MPTIOCTL_GET_PCI_INFO: 11642 /* 11643 * The user has requested to read pci info. Call 11644 * our routine which does this. 11645 */ 11646 bzero(&pci_info, sizeof (mptsas_pci_info_t)); 11647 mutex_enter(&mpt->m_mutex); 11648 mptsas_read_pci_info(mpt, &pci_info); 11649 mutex_exit(&mpt->m_mutex); 11650 if (ddi_copyout((void *)(&pci_info), (void *)data, 11651 sizeof (mptsas_pci_info_t), mode) != 0) { 11652 status = EFAULT; 11653 } 11654 break; 11655 case MPTIOCTL_RESET_ADAPTER: 11656 mutex_enter(&mpt->m_mutex); 11657 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 11658 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 11659 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL " 11660 "failed"); 11661 status = EFAULT; 11662 } 11663 mutex_exit(&mpt->m_mutex); 11664 break; 11665 case MPTIOCTL_DIAG_ACTION: 11666 /* 11667 * The user has done a diag buffer action. Call our 11668 * routine which does this. Only allow one diag action 11669 * at one time. 11670 */ 11671 mutex_enter(&mpt->m_mutex); 11672 if (mpt->m_diag_action_in_progress) { 11673 mutex_exit(&mpt->m_mutex); 11674 return (EBUSY); 11675 } 11676 mpt->m_diag_action_in_progress = 1; 11677 status = mptsas_diag_action(mpt, 11678 (mptsas_diag_action_t *)data, mode); 11679 mpt->m_diag_action_in_progress = 0; 11680 mutex_exit(&mpt->m_mutex); 11681 break; 11682 case MPTIOCTL_EVENT_QUERY: 11683 /* 11684 * The user has done an event query. Call our routine 11685 * which does this. 11686 */ 11687 status = mptsas_event_query(mpt, 11688 (mptsas_event_query_t *)data, mode, rval); 11689 break; 11690 case MPTIOCTL_EVENT_ENABLE: 11691 /* 11692 * The user has done an event enable. Call our routine 11693 * which does this. 11694 */ 11695 status = mptsas_event_enable(mpt, 11696 (mptsas_event_enable_t *)data, mode, rval); 11697 break; 11698 case MPTIOCTL_EVENT_REPORT: 11699 /* 11700 * The user has done an event report. Call our routine 11701 * which does this. 11702 */ 11703 status = mptsas_event_report(mpt, 11704 (mptsas_event_report_t *)data, mode, rval); 11705 break; 11706 case MPTIOCTL_REG_ACCESS: 11707 /* 11708 * The user has requested register access. Call our 11709 * routine which does this. 11710 */ 11711 status = mptsas_reg_access(mpt, 11712 (mptsas_reg_access_t *)data, mode); 11713 break; 11714 default: 11715 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, 11716 rval); 11717 break; 11718 } 11719 11720 out: 11721 return (status); 11722 } 11723 11724 int 11725 mptsas_restart_ioc(mptsas_t *mpt) 11726 { 11727 int rval = DDI_SUCCESS; 11728 mptsas_target_t *ptgt = NULL; 11729 11730 ASSERT(mutex_owned(&mpt->m_mutex)); 11731 11732 /* 11733 * Set a flag telling I/O path that we're processing a reset. This is 11734 * needed because after the reset is complete, the hash table still 11735 * needs to be rebuilt. If I/Os are started before the hash table is 11736 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked 11737 * so that they can be retried. 11738 */ 11739 mpt->m_in_reset = TRUE; 11740 11741 /* 11742 * Set all throttles to HOLD 11743 */ 11744 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 11745 ptgt = refhash_next(mpt->m_targets, ptgt)) { 11746 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 11747 } 11748 11749 /* 11750 * Disable interrupts 11751 */ 11752 MPTSAS_DISABLE_INTR(mpt); 11753 11754 /* 11755 * Abort all commands: outstanding commands, commands in waitq and 11756 * tx_waitq. 11757 */ 11758 mptsas_flush_hba(mpt); 11759 11760 /* 11761 * Reinitialize the chip. 11762 */ 11763 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 11764 rval = DDI_FAILURE; 11765 } 11766 11767 /* 11768 * Enable interrupts again 11769 */ 11770 MPTSAS_ENABLE_INTR(mpt); 11771 11772 /* 11773 * If mptsas_init_chip was successful, update the driver data. 11774 */ 11775 if (rval == DDI_SUCCESS) { 11776 mptsas_update_driver_data(mpt); 11777 } 11778 11779 /* 11780 * Reset the throttles 11781 */ 11782 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 11783 ptgt = refhash_next(mpt->m_targets, ptgt)) { 11784 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 11785 } 11786 11787 mptsas_doneq_empty(mpt); 11788 mptsas_restart_hba(mpt); 11789 11790 if (rval != DDI_SUCCESS) { 11791 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 11792 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 11793 } 11794 11795 /* 11796 * Clear the reset flag so that I/Os can continue. 11797 */ 11798 mpt->m_in_reset = FALSE; 11799 11800 return (rval); 11801 } 11802 11803 static int 11804 mptsas_init_chip(mptsas_t *mpt, int first_time) 11805 { 11806 ddi_dma_cookie_t cookie; 11807 uint32_t i; 11808 int rval; 11809 11810 /* 11811 * Check to see if the firmware image is valid 11812 */ 11813 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) & 11814 MPI2_DIAG_FLASH_BAD_SIG) { 11815 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!"); 11816 goto fail; 11817 } 11818 11819 /* 11820 * Reset the chip 11821 */ 11822 rval = mptsas_ioc_reset(mpt, first_time); 11823 if (rval == MPTSAS_RESET_FAIL) { 11824 mptsas_log(mpt, CE_WARN, "hard reset failed!"); 11825 goto fail; 11826 } 11827 11828 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) { 11829 goto mur; 11830 } 11831 /* 11832 * Setup configuration space 11833 */ 11834 if (mptsas_config_space_init(mpt) == FALSE) { 11835 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init " 11836 "failed!"); 11837 goto fail; 11838 } 11839 11840 /* 11841 * IOC facts can change after a diag reset so all buffers that are 11842 * based on these numbers must be de-allocated and re-allocated. Get 11843 * new IOC facts each time chip is initialized. 11844 */ 11845 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) { 11846 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed"); 11847 goto fail; 11848 } 11849 11850 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT, 11851 mptsas_target_addr_hash, mptsas_target_addr_cmp, 11852 mptsas_target_free, sizeof (mptsas_target_t), 11853 offsetof(mptsas_target_t, m_link), 11854 offsetof(mptsas_target_t, m_addr), KM_SLEEP); 11855 11856 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) { 11857 goto fail; 11858 } 11859 /* 11860 * Allocate request message frames, reply free queue, reply descriptor 11861 * post queue, and reply message frames using latest IOC facts. 11862 */ 11863 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) { 11864 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed"); 11865 goto fail; 11866 } 11867 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) { 11868 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!"); 11869 goto fail; 11870 } 11871 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) { 11872 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!"); 11873 goto fail; 11874 } 11875 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) { 11876 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!"); 11877 goto fail; 11878 } 11879 11880 mur: 11881 /* 11882 * Re-Initialize ioc to operational state 11883 */ 11884 if (mptsas_ioc_init(mpt) == DDI_FAILURE) { 11885 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed"); 11886 goto fail; 11887 } 11888 11889 mptsas_alloc_reply_args(mpt); 11890 11891 /* 11892 * Initialize reply post index. Reply free index is initialized after 11893 * the next loop. 11894 */ 11895 mpt->m_post_index = 0; 11896 11897 /* 11898 * Initialize the Reply Free Queue with the physical addresses of our 11899 * reply frames. 11900 */ 11901 cookie.dmac_address = mpt->m_reply_frame_dma_addr; 11902 for (i = 0; i < mpt->m_max_replies; i++) { 11903 ddi_put32(mpt->m_acc_free_queue_hdl, 11904 &((uint32_t *)(void *)mpt->m_free_queue)[i], 11905 cookie.dmac_address); 11906 cookie.dmac_address += mpt->m_reply_frame_size; 11907 } 11908 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11909 DDI_DMA_SYNC_FORDEV); 11910 11911 /* 11912 * Initialize the reply free index to one past the last frame on the 11913 * queue. This will signify that the queue is empty to start with. 11914 */ 11915 mpt->m_free_index = i; 11916 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i); 11917 11918 /* 11919 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's. 11920 */ 11921 for (i = 0; i < mpt->m_post_queue_depth; i++) { 11922 ddi_put64(mpt->m_acc_post_queue_hdl, 11923 &((uint64_t *)(void *)mpt->m_post_queue)[i], 11924 0xFFFFFFFFFFFFFFFF); 11925 } 11926 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 11927 DDI_DMA_SYNC_FORDEV); 11928 11929 /* 11930 * Enable ports 11931 */ 11932 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) { 11933 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed"); 11934 goto fail; 11935 } 11936 11937 /* 11938 * enable events 11939 */ 11940 if (mptsas_ioc_enable_event_notification(mpt)) { 11941 goto fail; 11942 } 11943 11944 /* 11945 * We need checks in attach and these. 11946 * chip_init is called in mult. places 11947 */ 11948 11949 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 11950 DDI_SUCCESS) || 11951 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 11952 DDI_SUCCESS) || 11953 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 11954 DDI_SUCCESS) || 11955 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 11956 DDI_SUCCESS) || 11957 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 11958 DDI_SUCCESS)) { 11959 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11960 goto fail; 11961 } 11962 11963 /* Check all acc handles */ 11964 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 11965 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 11966 DDI_SUCCESS) || 11967 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 11968 DDI_SUCCESS) || 11969 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 11970 DDI_SUCCESS) || 11971 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 11972 DDI_SUCCESS) || 11973 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 11974 DDI_SUCCESS) || 11975 (mptsas_check_acc_handle(mpt->m_config_handle) != 11976 DDI_SUCCESS)) { 11977 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11978 goto fail; 11979 } 11980 11981 return (DDI_SUCCESS); 11982 11983 fail: 11984 return (DDI_FAILURE); 11985 } 11986 11987 static int 11988 mptsas_get_pci_cap(mptsas_t *mpt) 11989 { 11990 ushort_t caps_ptr, cap, cap_count; 11991 11992 if (mpt->m_config_handle == NULL) 11993 return (FALSE); 11994 /* 11995 * Check if capabilities list is supported and if so, 11996 * get initial capabilities pointer and clear bits 0,1. 11997 */ 11998 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) 11999 & PCI_STAT_CAP) { 12000 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 12001 PCI_CONF_CAP_PTR), 4); 12002 } else { 12003 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 12004 } 12005 12006 /* 12007 * Walk capabilities if supported. 12008 */ 12009 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 12010 12011 /* 12012 * Check that we haven't exceeded the maximum number of 12013 * capabilities and that the pointer is in a valid range. 12014 */ 12015 if (++cap_count > 48) { 12016 mptsas_log(mpt, CE_WARN, 12017 "too many device capabilities.\n"); 12018 break; 12019 } 12020 if (caps_ptr < 64) { 12021 mptsas_log(mpt, CE_WARN, 12022 "capabilities pointer 0x%x out of range.\n", 12023 caps_ptr); 12024 break; 12025 } 12026 12027 /* 12028 * Get next capability and check that it is valid. 12029 * For now, we only support power management. 12030 */ 12031 cap = pci_config_get8(mpt->m_config_handle, caps_ptr); 12032 switch (cap) { 12033 case PCI_CAP_ID_PM: 12034 mptsas_log(mpt, CE_NOTE, 12035 "?mptsas%d supports power management.\n", 12036 mpt->m_instance); 12037 mpt->m_options |= MPTSAS_OPT_PM; 12038 12039 /* Save PMCSR offset */ 12040 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR; 12041 break; 12042 /* 12043 * The following capabilities are valid. Any others 12044 * will cause a message to be logged. 12045 */ 12046 case PCI_CAP_ID_VPD: 12047 case PCI_CAP_ID_MSI: 12048 case PCI_CAP_ID_PCIX: 12049 case PCI_CAP_ID_PCI_E: 12050 case PCI_CAP_ID_MSI_X: 12051 break; 12052 default: 12053 mptsas_log(mpt, CE_NOTE, 12054 "?mptsas%d unrecognized capability " 12055 "0x%x.\n", mpt->m_instance, cap); 12056 break; 12057 } 12058 12059 /* 12060 * Get next capabilities pointer and clear bits 0,1. 12061 */ 12062 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 12063 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 12064 } 12065 return (TRUE); 12066 } 12067 12068 static int 12069 mptsas_init_pm(mptsas_t *mpt) 12070 { 12071 char pmc_name[16]; 12072 char *pmc[] = { 12073 NULL, 12074 "0=Off (PCI D3 State)", 12075 "3=On (PCI D0 State)", 12076 NULL 12077 }; 12078 uint16_t pmcsr_stat; 12079 12080 if (mptsas_get_pci_cap(mpt) == FALSE) { 12081 return (DDI_FAILURE); 12082 } 12083 /* 12084 * If PCI's capability does not support PM, then don't need 12085 * to registe the pm-components 12086 */ 12087 if (!(mpt->m_options & MPTSAS_OPT_PM)) 12088 return (DDI_SUCCESS); 12089 /* 12090 * If power management is supported by this chip, create 12091 * pm-components property for the power management framework 12092 */ 12093 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance); 12094 pmc[0] = pmc_name; 12095 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip, 12096 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 12097 mpt->m_options &= ~MPTSAS_OPT_PM; 12098 mptsas_log(mpt, CE_WARN, 12099 "mptsas%d: pm-component property creation failed.", 12100 mpt->m_instance); 12101 return (DDI_FAILURE); 12102 } 12103 12104 /* 12105 * Power on device. 12106 */ 12107 (void) pm_busy_component(mpt->m_dip, 0); 12108 pmcsr_stat = pci_config_get16(mpt->m_config_handle, 12109 mpt->m_pmcsr_offset); 12110 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) { 12111 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device", 12112 mpt->m_instance); 12113 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, 12114 PCI_PMCSR_D0); 12115 } 12116 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 12117 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed"); 12118 return (DDI_FAILURE); 12119 } 12120 mpt->m_power_level = PM_LEVEL_D0; 12121 /* 12122 * Set pm idle delay. 12123 */ 12124 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 12125 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT); 12126 12127 return (DDI_SUCCESS); 12128 } 12129 12130 static int 12131 mptsas_register_intrs(mptsas_t *mpt) 12132 { 12133 dev_info_t *dip; 12134 int intr_types; 12135 12136 dip = mpt->m_dip; 12137 12138 /* Get supported interrupt types */ 12139 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 12140 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types " 12141 "failed\n"); 12142 return (FALSE); 12143 } 12144 12145 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types)); 12146 12147 /* 12148 * Try MSI, but fall back to FIXED 12149 */ 12150 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) { 12151 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) { 12152 NDBG0(("Using MSI interrupt type")); 12153 mpt->m_intr_type = DDI_INTR_TYPE_MSI; 12154 return (TRUE); 12155 } 12156 } 12157 if (intr_types & DDI_INTR_TYPE_FIXED) { 12158 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) { 12159 NDBG0(("Using FIXED interrupt type")); 12160 mpt->m_intr_type = DDI_INTR_TYPE_FIXED; 12161 return (TRUE); 12162 } else { 12163 NDBG0(("FIXED interrupt registration failed")); 12164 return (FALSE); 12165 } 12166 } 12167 12168 return (FALSE); 12169 } 12170 12171 static void 12172 mptsas_unregister_intrs(mptsas_t *mpt) 12173 { 12174 mptsas_rem_intrs(mpt); 12175 } 12176 12177 /* 12178 * mptsas_add_intrs: 12179 * 12180 * Register FIXED or MSI interrupts. 12181 */ 12182 static int 12183 mptsas_add_intrs(mptsas_t *mpt, int intr_type) 12184 { 12185 dev_info_t *dip = mpt->m_dip; 12186 int avail, actual, count = 0; 12187 int i, flag, ret; 12188 12189 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type)); 12190 12191 /* Get number of interrupts */ 12192 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 12193 if ((ret != DDI_SUCCESS) || (count <= 0)) { 12194 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, " 12195 "ret %d count %d\n", ret, count); 12196 12197 return (DDI_FAILURE); 12198 } 12199 12200 /* Get number of available interrupts */ 12201 ret = ddi_intr_get_navail(dip, intr_type, &avail); 12202 if ((ret != DDI_SUCCESS) || (avail == 0)) { 12203 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, " 12204 "ret %d avail %d\n", ret, avail); 12205 12206 return (DDI_FAILURE); 12207 } 12208 12209 if (avail < count) { 12210 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, " 12211 "navail() returned %d", count, avail); 12212 } 12213 12214 /* Mpt only have one interrupt routine */ 12215 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 12216 count = 1; 12217 } 12218 12219 /* Allocate an array of interrupt handles */ 12220 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t); 12221 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP); 12222 12223 flag = DDI_INTR_ALLOC_NORMAL; 12224 12225 /* call ddi_intr_alloc() */ 12226 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0, 12227 count, &actual, flag); 12228 12229 if ((ret != DDI_SUCCESS) || (actual == 0)) { 12230 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n", 12231 ret); 12232 kmem_free(mpt->m_htable, mpt->m_intr_size); 12233 return (DDI_FAILURE); 12234 } 12235 12236 /* use interrupt count returned or abort? */ 12237 if (actual < count) { 12238 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n", 12239 count, actual); 12240 } 12241 12242 mpt->m_intr_cnt = actual; 12243 12244 /* 12245 * Get priority for first msi, assume remaining are all the same 12246 */ 12247 if ((ret = ddi_intr_get_pri(mpt->m_htable[0], 12248 &mpt->m_intr_pri)) != DDI_SUCCESS) { 12249 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret); 12250 12251 /* Free already allocated intr */ 12252 for (i = 0; i < actual; i++) { 12253 (void) ddi_intr_free(mpt->m_htable[i]); 12254 } 12255 12256 kmem_free(mpt->m_htable, mpt->m_intr_size); 12257 return (DDI_FAILURE); 12258 } 12259 12260 /* Test for high level mutex */ 12261 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) { 12262 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: " 12263 "Hi level interrupt not supported\n"); 12264 12265 /* Free already allocated intr */ 12266 for (i = 0; i < actual; i++) { 12267 (void) ddi_intr_free(mpt->m_htable[i]); 12268 } 12269 12270 kmem_free(mpt->m_htable, mpt->m_intr_size); 12271 return (DDI_FAILURE); 12272 } 12273 12274 /* Call ddi_intr_add_handler() */ 12275 for (i = 0; i < actual; i++) { 12276 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr, 12277 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 12278 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() " 12279 "failed %d\n", ret); 12280 12281 /* Free already allocated intr */ 12282 for (i = 0; i < actual; i++) { 12283 (void) ddi_intr_free(mpt->m_htable[i]); 12284 } 12285 12286 kmem_free(mpt->m_htable, mpt->m_intr_size); 12287 return (DDI_FAILURE); 12288 } 12289 } 12290 12291 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap)) 12292 != DDI_SUCCESS) { 12293 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret); 12294 12295 /* Free already allocated intr */ 12296 for (i = 0; i < actual; i++) { 12297 (void) ddi_intr_free(mpt->m_htable[i]); 12298 } 12299 12300 kmem_free(mpt->m_htable, mpt->m_intr_size); 12301 return (DDI_FAILURE); 12302 } 12303 12304 /* 12305 * Enable interrupts 12306 */ 12307 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 12308 /* Call ddi_intr_block_enable() for MSI interrupts */ 12309 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt); 12310 } else { 12311 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 12312 for (i = 0; i < mpt->m_intr_cnt; i++) { 12313 (void) ddi_intr_enable(mpt->m_htable[i]); 12314 } 12315 } 12316 return (DDI_SUCCESS); 12317 } 12318 12319 /* 12320 * mptsas_rem_intrs: 12321 * 12322 * Unregister FIXED or MSI interrupts 12323 */ 12324 static void 12325 mptsas_rem_intrs(mptsas_t *mpt) 12326 { 12327 int i; 12328 12329 NDBG6(("mptsas_rem_intrs")); 12330 12331 /* Disable all interrupts */ 12332 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 12333 /* Call ddi_intr_block_disable() */ 12334 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt); 12335 } else { 12336 for (i = 0; i < mpt->m_intr_cnt; i++) { 12337 (void) ddi_intr_disable(mpt->m_htable[i]); 12338 } 12339 } 12340 12341 /* Call ddi_intr_remove_handler() */ 12342 for (i = 0; i < mpt->m_intr_cnt; i++) { 12343 (void) ddi_intr_remove_handler(mpt->m_htable[i]); 12344 (void) ddi_intr_free(mpt->m_htable[i]); 12345 } 12346 12347 kmem_free(mpt->m_htable, mpt->m_intr_size); 12348 } 12349 12350 /* 12351 * The IO fault service error handling callback function 12352 */ 12353 /*ARGSUSED*/ 12354 static int 12355 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 12356 { 12357 /* 12358 * as the driver can always deal with an error in any dma or 12359 * access handle, we can just return the fme_status value. 12360 */ 12361 pci_ereport_post(dip, err, NULL); 12362 return (err->fme_status); 12363 } 12364 12365 /* 12366 * mptsas_fm_init - initialize fma capabilities and register with IO 12367 * fault services. 12368 */ 12369 static void 12370 mptsas_fm_init(mptsas_t *mpt) 12371 { 12372 /* 12373 * Need to change iblock to priority for new MSI intr 12374 */ 12375 ddi_iblock_cookie_t fm_ibc; 12376 12377 /* Only register with IO Fault Services if we have some capability */ 12378 if (mpt->m_fm_capabilities) { 12379 /* Adjust access and dma attributes for FMA */ 12380 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 12381 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 12382 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 12383 12384 /* 12385 * Register capabilities with IO Fault Services. 12386 * mpt->m_fm_capabilities will be updated to indicate 12387 * capabilities actually supported (not requested.) 12388 */ 12389 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc); 12390 12391 /* 12392 * Initialize pci ereport capabilities if ereport 12393 * capable (should always be.) 12394 */ 12395 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 12396 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 12397 pci_ereport_setup(mpt->m_dip); 12398 } 12399 12400 /* 12401 * Register error callback if error callback capable. 12402 */ 12403 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 12404 ddi_fm_handler_register(mpt->m_dip, 12405 mptsas_fm_error_cb, (void *) mpt); 12406 } 12407 } 12408 } 12409 12410 /* 12411 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO 12412 * fault services. 12413 * 12414 */ 12415 static void 12416 mptsas_fm_fini(mptsas_t *mpt) 12417 { 12418 /* Only unregister FMA capabilities if registered */ 12419 if (mpt->m_fm_capabilities) { 12420 12421 /* 12422 * Un-register error callback if error callback capable. 12423 */ 12424 12425 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 12426 ddi_fm_handler_unregister(mpt->m_dip); 12427 } 12428 12429 /* 12430 * Release any resources allocated by pci_ereport_setup() 12431 */ 12432 12433 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 12434 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 12435 pci_ereport_teardown(mpt->m_dip); 12436 } 12437 12438 /* Unregister from IO Fault Services */ 12439 ddi_fm_fini(mpt->m_dip); 12440 12441 /* Adjust access and dma attributes for FMA */ 12442 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 12443 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 12444 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 12445 12446 } 12447 } 12448 12449 int 12450 mptsas_check_acc_handle(ddi_acc_handle_t handle) 12451 { 12452 ddi_fm_error_t de; 12453 12454 if (handle == NULL) 12455 return (DDI_FAILURE); 12456 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0); 12457 return (de.fme_status); 12458 } 12459 12460 int 12461 mptsas_check_dma_handle(ddi_dma_handle_t handle) 12462 { 12463 ddi_fm_error_t de; 12464 12465 if (handle == NULL) 12466 return (DDI_FAILURE); 12467 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0); 12468 return (de.fme_status); 12469 } 12470 12471 void 12472 mptsas_fm_ereport(mptsas_t *mpt, char *detail) 12473 { 12474 uint64_t ena; 12475 char buf[FM_MAX_CLASS]; 12476 12477 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 12478 ena = fm_ena_generate(0, FM_ENA_FMT1); 12479 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) { 12480 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP, 12481 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 12482 } 12483 } 12484 12485 static int 12486 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 12487 uint16_t *dev_handle, mptsas_target_t **pptgt) 12488 { 12489 int rval; 12490 uint32_t dev_info; 12491 uint64_t sas_wwn; 12492 mptsas_phymask_t phymask; 12493 uint8_t physport, phynum, config, disk; 12494 uint64_t devicename; 12495 uint16_t pdev_hdl; 12496 mptsas_target_t *tmp_tgt = NULL; 12497 uint16_t bay_num, enclosure; 12498 12499 ASSERT(*pptgt == NULL); 12500 12501 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle, 12502 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl, 12503 &bay_num, &enclosure); 12504 if (rval != DDI_SUCCESS) { 12505 rval = DEV_INFO_FAIL_PAGE0; 12506 return (rval); 12507 } 12508 12509 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET | 12510 MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 12511 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) { 12512 rval = DEV_INFO_WRONG_DEVICE_TYPE; 12513 return (rval); 12514 } 12515 12516 /* 12517 * Check if the dev handle is for a Phys Disk. If so, set return value 12518 * and exit. Don't add Phys Disks to hash. 12519 */ 12520 for (config = 0; config < mpt->m_num_raid_configs; config++) { 12521 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 12522 if (*dev_handle == mpt->m_raidconfig[config]. 12523 m_physdisk_devhdl[disk]) { 12524 rval = DEV_INFO_PHYS_DISK; 12525 return (rval); 12526 } 12527 } 12528 } 12529 12530 /* 12531 * Get SATA Device Name from SAS device page0 for 12532 * sata device, if device name doesn't exist, set mta_wwn to 12533 * 0 for direct attached SATA. For the device behind the expander 12534 * we still can use STP address assigned by expander. 12535 */ 12536 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 12537 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 12538 mutex_exit(&mpt->m_mutex); 12539 /* alloc a tmp_tgt to send the cmd */ 12540 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), 12541 KM_SLEEP); 12542 tmp_tgt->m_devhdl = *dev_handle; 12543 tmp_tgt->m_deviceinfo = dev_info; 12544 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 12545 tmp_tgt->m_qfull_retry_interval = 12546 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 12547 tmp_tgt->m_t_throttle = MAX_THROTTLE; 12548 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0); 12549 kmem_free(tmp_tgt, sizeof (struct mptsas_target)); 12550 mutex_enter(&mpt->m_mutex); 12551 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) { 12552 sas_wwn = devicename; 12553 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) { 12554 sas_wwn = 0; 12555 } 12556 } 12557 12558 phymask = mptsas_physport_to_phymask(mpt, physport); 12559 *pptgt = mptsas_tgt_alloc(mpt, *dev_handle, sas_wwn, 12560 dev_info, phymask, phynum); 12561 if (*pptgt == NULL) { 12562 mptsas_log(mpt, CE_WARN, "Failed to allocated target" 12563 "structure!"); 12564 rval = DEV_INFO_FAIL_ALLOC; 12565 return (rval); 12566 } 12567 (*pptgt)->m_enclosure = enclosure; 12568 (*pptgt)->m_slot_num = bay_num; 12569 return (DEV_INFO_SUCCESS); 12570 } 12571 12572 uint64_t 12573 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun) 12574 { 12575 uint64_t sata_guid = 0, *pwwn = NULL; 12576 int target = ptgt->m_devhdl; 12577 uchar_t *inq83 = NULL; 12578 int inq83_len = 0xFF; 12579 uchar_t *dblk = NULL; 12580 int inq83_retry = 3; 12581 int rval = DDI_FAILURE; 12582 12583 inq83 = kmem_zalloc(inq83_len, KM_SLEEP); 12584 12585 inq83_retry: 12586 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 12587 inq83_len, NULL, 1); 12588 if (rval != DDI_SUCCESS) { 12589 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 12590 "0x83 for target:%x, lun:%x failed!", target, lun); 12591 goto out; 12592 } 12593 /* According to SAT2, the first descriptor is logic unit name */ 12594 dblk = &inq83[4]; 12595 if ((dblk[1] & 0x30) != 0) { 12596 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated."); 12597 goto out; 12598 } 12599 pwwn = (uint64_t *)(void *)(&dblk[4]); 12600 if ((dblk[4] & 0xf0) == 0x50) { 12601 sata_guid = BE_64(*pwwn); 12602 goto out; 12603 } else if (dblk[4] == 'A') { 12604 NDBG20(("SATA drive has no NAA format GUID.")); 12605 goto out; 12606 } else { 12607 /* The data is not ready, wait and retry */ 12608 inq83_retry--; 12609 if (inq83_retry <= 0) { 12610 goto out; 12611 } 12612 NDBG20(("The GUID is not ready, retry...")); 12613 delay(1 * drv_usectohz(1000000)); 12614 goto inq83_retry; 12615 } 12616 out: 12617 kmem_free(inq83, inq83_len); 12618 return (sata_guid); 12619 } 12620 12621 static int 12622 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page, 12623 unsigned char *buf, int len, int *reallen, uchar_t evpd) 12624 { 12625 uchar_t cdb[CDB_GROUP0]; 12626 struct scsi_address ap; 12627 struct buf *data_bp = NULL; 12628 int resid = 0; 12629 int ret = DDI_FAILURE; 12630 12631 ASSERT(len <= 0xffff); 12632 12633 ap.a_target = MPTSAS_INVALID_DEVHDL; 12634 ap.a_lun = (uchar_t)(lun); 12635 ap.a_hba_tran = mpt->m_tran; 12636 12637 data_bp = scsi_alloc_consistent_buf(&ap, 12638 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL); 12639 if (data_bp == NULL) { 12640 return (ret); 12641 } 12642 bzero(cdb, CDB_GROUP0); 12643 cdb[0] = SCMD_INQUIRY; 12644 cdb[1] = evpd; 12645 cdb[2] = page; 12646 cdb[3] = (len & 0xff00) >> 8; 12647 cdb[4] = (len & 0x00ff); 12648 cdb[5] = 0; 12649 12650 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp, 12651 &resid); 12652 if (ret == DDI_SUCCESS) { 12653 if (reallen) { 12654 *reallen = len - resid; 12655 } 12656 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len); 12657 } 12658 if (data_bp) { 12659 scsi_free_consistent_buf(data_bp); 12660 } 12661 return (ret); 12662 } 12663 12664 static int 12665 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 12666 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 12667 int *resid) 12668 { 12669 struct scsi_pkt *pktp = NULL; 12670 scsi_hba_tran_t *tran_clone = NULL; 12671 mptsas_tgt_private_t *tgt_private = NULL; 12672 int ret = DDI_FAILURE; 12673 12674 /* 12675 * scsi_hba_tran_t->tran_tgt_private is used to pass the address 12676 * information to scsi_init_pkt, allocate a scsi_hba_tran structure 12677 * to simulate the cmds from sd 12678 */ 12679 tran_clone = kmem_alloc( 12680 sizeof (scsi_hba_tran_t), KM_SLEEP); 12681 if (tran_clone == NULL) { 12682 goto out; 12683 } 12684 bcopy((caddr_t)mpt->m_tran, 12685 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t)); 12686 tgt_private = kmem_alloc( 12687 sizeof (mptsas_tgt_private_t), KM_SLEEP); 12688 if (tgt_private == NULL) { 12689 goto out; 12690 } 12691 tgt_private->t_lun = ap->a_lun; 12692 tgt_private->t_private = ptgt; 12693 tran_clone->tran_tgt_private = tgt_private; 12694 ap->a_hba_tran = tran_clone; 12695 12696 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL, 12697 data_bp, cdblen, sizeof (struct scsi_arq_status), 12698 0, PKT_CONSISTENT, NULL, NULL); 12699 if (pktp == NULL) { 12700 goto out; 12701 } 12702 bcopy(cdb, pktp->pkt_cdbp, cdblen); 12703 pktp->pkt_flags = FLAG_NOPARITY; 12704 if (scsi_poll(pktp) < 0) { 12705 goto out; 12706 } 12707 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) { 12708 goto out; 12709 } 12710 if (resid != NULL) { 12711 *resid = pktp->pkt_resid; 12712 } 12713 12714 ret = DDI_SUCCESS; 12715 out: 12716 if (pktp) { 12717 scsi_destroy_pkt(pktp); 12718 } 12719 if (tran_clone) { 12720 kmem_free(tran_clone, sizeof (scsi_hba_tran_t)); 12721 } 12722 if (tgt_private) { 12723 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 12724 } 12725 return (ret); 12726 } 12727 static int 12728 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun) 12729 { 12730 char *cp = NULL; 12731 char *ptr = NULL; 12732 size_t s = 0; 12733 char *wwid_str = NULL; 12734 char *lun_str = NULL; 12735 long lunnum; 12736 long phyid = -1; 12737 int rc = DDI_FAILURE; 12738 12739 ptr = name; 12740 ASSERT(ptr[0] == 'w' || ptr[0] == 'p'); 12741 ptr++; 12742 if ((cp = strchr(ptr, ',')) == NULL) { 12743 return (DDI_FAILURE); 12744 } 12745 12746 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 12747 s = (uintptr_t)cp - (uintptr_t)ptr; 12748 12749 bcopy(ptr, wwid_str, s); 12750 wwid_str[s] = '\0'; 12751 12752 ptr = ++cp; 12753 12754 if ((cp = strchr(ptr, '\0')) == NULL) { 12755 goto out; 12756 } 12757 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 12758 s = (uintptr_t)cp - (uintptr_t)ptr; 12759 12760 bcopy(ptr, lun_str, s); 12761 lun_str[s] = '\0'; 12762 12763 if (name[0] == 'p') { 12764 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid); 12765 } else { 12766 rc = scsi_wwnstr_to_wwn(wwid_str, wwid); 12767 } 12768 if (rc != DDI_SUCCESS) 12769 goto out; 12770 12771 if (phyid != -1) { 12772 ASSERT(phyid < MPTSAS_MAX_PHYS); 12773 *phy = (uint8_t)phyid; 12774 } 12775 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum); 12776 if (rc != 0) 12777 goto out; 12778 12779 *lun = (int)lunnum; 12780 rc = DDI_SUCCESS; 12781 out: 12782 if (wwid_str) 12783 kmem_free(wwid_str, SCSI_MAXNAMELEN); 12784 if (lun_str) 12785 kmem_free(lun_str, SCSI_MAXNAMELEN); 12786 12787 return (rc); 12788 } 12789 12790 /* 12791 * mptsas_parse_smp_name() is to parse sas wwn string 12792 * which format is "wWWN" 12793 */ 12794 static int 12795 mptsas_parse_smp_name(char *name, uint64_t *wwn) 12796 { 12797 char *ptr = name; 12798 12799 if (*ptr != 'w') { 12800 return (DDI_FAILURE); 12801 } 12802 12803 ptr++; 12804 if (scsi_wwnstr_to_wwn(ptr, wwn)) { 12805 return (DDI_FAILURE); 12806 } 12807 return (DDI_SUCCESS); 12808 } 12809 12810 static int 12811 mptsas_bus_config(dev_info_t *pdip, uint_t flag, 12812 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 12813 { 12814 int ret = NDI_FAILURE; 12815 int circ = 0; 12816 int circ1 = 0; 12817 mptsas_t *mpt; 12818 char *ptr = NULL; 12819 char *devnm = NULL; 12820 uint64_t wwid = 0; 12821 uint8_t phy = 0xFF; 12822 int lun = 0; 12823 uint_t mflags = flag; 12824 int bconfig = TRUE; 12825 12826 if (scsi_hba_iport_unit_address(pdip) == 0) { 12827 return (DDI_FAILURE); 12828 } 12829 12830 mpt = DIP2MPT(pdip); 12831 if (!mpt) { 12832 return (DDI_FAILURE); 12833 } 12834 /* 12835 * Hold the nexus across the bus_config 12836 */ 12837 ndi_devi_enter(scsi_vhci_dip, &circ); 12838 ndi_devi_enter(pdip, &circ1); 12839 switch (op) { 12840 case BUS_CONFIG_ONE: 12841 /* parse wwid/target name out of name given */ 12842 if ((ptr = strchr((char *)arg, '@')) == NULL) { 12843 ret = NDI_FAILURE; 12844 break; 12845 } 12846 ptr++; 12847 if (strncmp((char *)arg, "smp", 3) == 0) { 12848 /* 12849 * This is a SMP target device 12850 */ 12851 ret = mptsas_parse_smp_name(ptr, &wwid); 12852 if (ret != DDI_SUCCESS) { 12853 ret = NDI_FAILURE; 12854 break; 12855 } 12856 ret = mptsas_config_smp(pdip, wwid, childp); 12857 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) { 12858 /* 12859 * OBP could pass down a non-canonical form 12860 * bootpath without LUN part when LUN is 0. 12861 * So driver need adjust the string. 12862 */ 12863 if (strchr(ptr, ',') == NULL) { 12864 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 12865 (void) sprintf(devnm, "%s,0", (char *)arg); 12866 ptr = strchr(devnm, '@'); 12867 ptr++; 12868 } 12869 12870 /* 12871 * The device path is wWWID format and the device 12872 * is not SMP target device. 12873 */ 12874 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun); 12875 if (ret != DDI_SUCCESS) { 12876 ret = NDI_FAILURE; 12877 break; 12878 } 12879 *childp = NULL; 12880 if (ptr[0] == 'w') { 12881 ret = mptsas_config_one_addr(pdip, wwid, 12882 lun, childp); 12883 } else if (ptr[0] == 'p') { 12884 ret = mptsas_config_one_phy(pdip, phy, lun, 12885 childp); 12886 } 12887 12888 /* 12889 * If this is CD/DVD device in OBP path, the 12890 * ndi_busop_bus_config can be skipped as config one 12891 * operation is done above. 12892 */ 12893 if ((ret == NDI_SUCCESS) && (*childp != NULL) && 12894 (strcmp(ddi_node_name(*childp), "cdrom") == 0) && 12895 (strncmp((char *)arg, "disk", 4) == 0)) { 12896 bconfig = FALSE; 12897 ndi_hold_devi(*childp); 12898 } 12899 } else { 12900 ret = NDI_FAILURE; 12901 break; 12902 } 12903 12904 /* 12905 * DDI group instructed us to use this flag. 12906 */ 12907 mflags |= NDI_MDI_FALLBACK; 12908 break; 12909 case BUS_CONFIG_DRIVER: 12910 case BUS_CONFIG_ALL: 12911 mptsas_config_all(pdip); 12912 ret = NDI_SUCCESS; 12913 break; 12914 } 12915 12916 if ((ret == NDI_SUCCESS) && bconfig) { 12917 ret = ndi_busop_bus_config(pdip, mflags, op, 12918 (devnm == NULL) ? arg : devnm, childp, 0); 12919 } 12920 12921 ndi_devi_exit(pdip, circ1); 12922 ndi_devi_exit(scsi_vhci_dip, circ); 12923 if (devnm != NULL) 12924 kmem_free(devnm, SCSI_MAXNAMELEN); 12925 return (ret); 12926 } 12927 12928 static int 12929 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip, 12930 mptsas_target_t *ptgt) 12931 { 12932 int rval = DDI_FAILURE; 12933 struct scsi_inquiry *sd_inq = NULL; 12934 mptsas_t *mpt = DIP2MPT(pdip); 12935 12936 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 12937 12938 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq, 12939 SUN_INQSIZE, 0, (uchar_t)0); 12940 12941 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 12942 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun); 12943 } else { 12944 rval = DDI_FAILURE; 12945 } 12946 12947 kmem_free(sd_inq, SUN_INQSIZE); 12948 return (rval); 12949 } 12950 12951 static int 12952 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 12953 dev_info_t **lundip) 12954 { 12955 int rval; 12956 mptsas_t *mpt = DIP2MPT(pdip); 12957 int phymask; 12958 mptsas_target_t *ptgt = NULL; 12959 12960 /* 12961 * Get the physical port associated to the iport 12962 */ 12963 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 12964 "phymask", 0); 12965 12966 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr); 12967 if (ptgt == NULL) { 12968 /* 12969 * didn't match any device by searching 12970 */ 12971 return (DDI_FAILURE); 12972 } 12973 /* 12974 * If the LUN already exists and the status is online, 12975 * we just return the pointer to dev_info_t directly. 12976 * For the mdi_pathinfo node, we'll handle it in 12977 * mptsas_create_virt_lun() 12978 * TODO should be also in mptsas_handle_dr 12979 */ 12980 12981 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun); 12982 if (*lundip != NULL) { 12983 /* 12984 * TODO Another senario is, we hotplug the same disk 12985 * on the same slot, the devhdl changed, is this 12986 * possible? 12987 * tgt_private->t_private != ptgt 12988 */ 12989 if (sasaddr != ptgt->m_addr.mta_wwn) { 12990 /* 12991 * The device has changed although the devhdl is the 12992 * same (Enclosure mapping mode, change drive on the 12993 * same slot) 12994 */ 12995 return (DDI_FAILURE); 12996 } 12997 return (DDI_SUCCESS); 12998 } 12999 13000 if (phymask == 0) { 13001 /* 13002 * Configure IR volume 13003 */ 13004 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip); 13005 return (rval); 13006 } 13007 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 13008 13009 return (rval); 13010 } 13011 13012 static int 13013 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 13014 dev_info_t **lundip) 13015 { 13016 int rval; 13017 mptsas_t *mpt = DIP2MPT(pdip); 13018 mptsas_phymask_t phymask; 13019 mptsas_target_t *ptgt = NULL; 13020 13021 /* 13022 * Get the physical port associated to the iport 13023 */ 13024 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 13025 "phymask", 0); 13026 13027 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy); 13028 if (ptgt == NULL) { 13029 /* 13030 * didn't match any device by searching 13031 */ 13032 return (DDI_FAILURE); 13033 } 13034 13035 /* 13036 * If the LUN already exists and the status is online, 13037 * we just return the pointer to dev_info_t directly. 13038 * For the mdi_pathinfo node, we'll handle it in 13039 * mptsas_create_virt_lun(). 13040 */ 13041 13042 *lundip = mptsas_find_child_phy(pdip, phy); 13043 if (*lundip != NULL) { 13044 return (DDI_SUCCESS); 13045 } 13046 13047 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 13048 13049 return (rval); 13050 } 13051 13052 static int 13053 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num, 13054 uint8_t *lun_addr_type) 13055 { 13056 uint32_t lun_idx = 0; 13057 13058 ASSERT(lun_num != NULL); 13059 ASSERT(lun_addr_type != NULL); 13060 13061 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 13062 /* determine report luns addressing type */ 13063 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) { 13064 /* 13065 * Vendors in the field have been found to be concatenating 13066 * bus/target/lun to equal the complete lun value instead 13067 * of switching to flat space addressing 13068 */ 13069 /* 00b - peripheral device addressing method */ 13070 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL: 13071 /* FALLTHRU */ 13072 /* 10b - logical unit addressing method */ 13073 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT: 13074 /* FALLTHRU */ 13075 /* 01b - flat space addressing method */ 13076 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE: 13077 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */ 13078 *lun_addr_type = (buf[lun_idx] & 13079 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6; 13080 *lun_num = (buf[lun_idx] & 0x3F) << 8; 13081 *lun_num |= buf[lun_idx + 1]; 13082 return (DDI_SUCCESS); 13083 default: 13084 return (DDI_FAILURE); 13085 } 13086 } 13087 13088 static int 13089 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt) 13090 { 13091 struct buf *repluns_bp = NULL; 13092 struct scsi_address ap; 13093 uchar_t cdb[CDB_GROUP5]; 13094 int ret = DDI_FAILURE; 13095 int retry = 0; 13096 int lun_list_len = 0; 13097 uint16_t lun_num = 0; 13098 uint8_t lun_addr_type = 0; 13099 uint32_t lun_cnt = 0; 13100 uint32_t lun_total = 0; 13101 dev_info_t *cdip = NULL; 13102 uint16_t *saved_repluns = NULL; 13103 char *buffer = NULL; 13104 int buf_len = 128; 13105 mptsas_t *mpt = DIP2MPT(pdip); 13106 uint64_t sas_wwn = 0; 13107 uint8_t phy = 0xFF; 13108 uint32_t dev_info = 0; 13109 13110 mutex_enter(&mpt->m_mutex); 13111 sas_wwn = ptgt->m_addr.mta_wwn; 13112 phy = ptgt->m_phynum; 13113 dev_info = ptgt->m_deviceinfo; 13114 mutex_exit(&mpt->m_mutex); 13115 13116 if (sas_wwn == 0) { 13117 /* 13118 * It's a SATA without Device Name 13119 * So don't try multi-LUNs 13120 */ 13121 if (mptsas_find_child_phy(pdip, phy)) { 13122 return (DDI_SUCCESS); 13123 } else { 13124 /* 13125 * need configure and create node 13126 */ 13127 return (DDI_FAILURE); 13128 } 13129 } 13130 13131 /* 13132 * WWN (SAS address or Device Name exist) 13133 */ 13134 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13135 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 13136 /* 13137 * SATA device with Device Name 13138 * So don't try multi-LUNs 13139 */ 13140 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) { 13141 return (DDI_SUCCESS); 13142 } else { 13143 return (DDI_FAILURE); 13144 } 13145 } 13146 13147 do { 13148 ap.a_target = MPTSAS_INVALID_DEVHDL; 13149 ap.a_lun = 0; 13150 ap.a_hba_tran = mpt->m_tran; 13151 repluns_bp = scsi_alloc_consistent_buf(&ap, 13152 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL); 13153 if (repluns_bp == NULL) { 13154 retry++; 13155 continue; 13156 } 13157 bzero(cdb, CDB_GROUP5); 13158 cdb[0] = SCMD_REPORT_LUNS; 13159 cdb[6] = (buf_len & 0xff000000) >> 24; 13160 cdb[7] = (buf_len & 0x00ff0000) >> 16; 13161 cdb[8] = (buf_len & 0x0000ff00) >> 8; 13162 cdb[9] = (buf_len & 0x000000ff); 13163 13164 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5, 13165 repluns_bp, NULL); 13166 if (ret != DDI_SUCCESS) { 13167 scsi_free_consistent_buf(repluns_bp); 13168 retry++; 13169 continue; 13170 } 13171 lun_list_len = BE_32(*(int *)((void *)( 13172 repluns_bp->b_un.b_addr))); 13173 if (buf_len >= lun_list_len + 8) { 13174 ret = DDI_SUCCESS; 13175 break; 13176 } 13177 scsi_free_consistent_buf(repluns_bp); 13178 buf_len = lun_list_len + 8; 13179 13180 } while (retry < 3); 13181 13182 if (ret != DDI_SUCCESS) 13183 return (ret); 13184 buffer = (char *)repluns_bp->b_un.b_addr; 13185 /* 13186 * find out the number of luns returned by the SCSI ReportLun call 13187 * and allocate buffer space 13188 */ 13189 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 13190 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP); 13191 if (saved_repluns == NULL) { 13192 scsi_free_consistent_buf(repluns_bp); 13193 return (DDI_FAILURE); 13194 } 13195 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) { 13196 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer), 13197 &lun_num, &lun_addr_type) != DDI_SUCCESS) { 13198 continue; 13199 } 13200 saved_repluns[lun_cnt] = lun_num; 13201 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) 13202 ret = DDI_SUCCESS; 13203 else 13204 ret = mptsas_probe_lun(pdip, lun_num, &cdip, 13205 ptgt); 13206 if ((ret == DDI_SUCCESS) && (cdip != NULL)) { 13207 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip, 13208 MPTSAS_DEV_GONE); 13209 } 13210 } 13211 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt); 13212 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total); 13213 scsi_free_consistent_buf(repluns_bp); 13214 return (DDI_SUCCESS); 13215 } 13216 13217 static int 13218 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip) 13219 { 13220 int rval = DDI_FAILURE; 13221 struct scsi_inquiry *sd_inq = NULL; 13222 mptsas_t *mpt = DIP2MPT(pdip); 13223 mptsas_target_t *ptgt = NULL; 13224 13225 mutex_enter(&mpt->m_mutex); 13226 ptgt = refhash_linear_search(mpt->m_targets, 13227 mptsas_target_eval_devhdl, &target); 13228 mutex_exit(&mpt->m_mutex); 13229 if (ptgt == NULL) { 13230 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x " 13231 "not found.", target); 13232 return (rval); 13233 } 13234 13235 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 13236 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq, 13237 SUN_INQSIZE, 0, (uchar_t)0); 13238 13239 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 13240 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt, 13241 0); 13242 } else { 13243 rval = DDI_FAILURE; 13244 } 13245 13246 kmem_free(sd_inq, SUN_INQSIZE); 13247 return (rval); 13248 } 13249 13250 /* 13251 * configure all RAID volumes for virtual iport 13252 */ 13253 static void 13254 mptsas_config_all_viport(dev_info_t *pdip) 13255 { 13256 mptsas_t *mpt = DIP2MPT(pdip); 13257 int config, vol; 13258 int target; 13259 dev_info_t *lundip = NULL; 13260 13261 /* 13262 * Get latest RAID info and search for any Volume DevHandles. If any 13263 * are found, configure the volume. 13264 */ 13265 mutex_enter(&mpt->m_mutex); 13266 for (config = 0; config < mpt->m_num_raid_configs; config++) { 13267 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 13268 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid 13269 == 1) { 13270 target = mpt->m_raidconfig[config]. 13271 m_raidvol[vol].m_raidhandle; 13272 mutex_exit(&mpt->m_mutex); 13273 (void) mptsas_config_raid(pdip, target, 13274 &lundip); 13275 mutex_enter(&mpt->m_mutex); 13276 } 13277 } 13278 } 13279 mutex_exit(&mpt->m_mutex); 13280 } 13281 13282 static void 13283 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns, 13284 int lun_cnt, mptsas_target_t *ptgt) 13285 { 13286 dev_info_t *child = NULL, *savechild = NULL; 13287 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 13288 uint64_t sas_wwn, wwid; 13289 uint8_t phy; 13290 int lun; 13291 int i; 13292 int find; 13293 char *addr; 13294 char *nodename; 13295 mptsas_t *mpt = DIP2MPT(pdip); 13296 13297 mutex_enter(&mpt->m_mutex); 13298 wwid = ptgt->m_addr.mta_wwn; 13299 mutex_exit(&mpt->m_mutex); 13300 13301 child = ddi_get_child(pdip); 13302 while (child) { 13303 find = 0; 13304 savechild = child; 13305 child = ddi_get_next_sibling(child); 13306 13307 nodename = ddi_node_name(savechild); 13308 if (strcmp(nodename, "smp") == 0) { 13309 continue; 13310 } 13311 13312 addr = ddi_get_name_addr(savechild); 13313 if (addr == NULL) { 13314 continue; 13315 } 13316 13317 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) != 13318 DDI_SUCCESS) { 13319 continue; 13320 } 13321 13322 if (wwid == sas_wwn) { 13323 for (i = 0; i < lun_cnt; i++) { 13324 if (repluns[i] == lun) { 13325 find = 1; 13326 break; 13327 } 13328 } 13329 } else { 13330 continue; 13331 } 13332 if (find == 0) { 13333 /* 13334 * The lun has not been there already 13335 */ 13336 (void) mptsas_offline_lun(pdip, savechild, NULL, 13337 NDI_DEVI_REMOVE); 13338 } 13339 } 13340 13341 pip = mdi_get_next_client_path(pdip, NULL); 13342 while (pip) { 13343 find = 0; 13344 savepip = pip; 13345 addr = MDI_PI(pip)->pi_addr; 13346 13347 pip = mdi_get_next_client_path(pdip, pip); 13348 13349 if (addr == NULL) { 13350 continue; 13351 } 13352 13353 if (mptsas_parse_address(addr, &sas_wwn, &phy, 13354 &lun) != DDI_SUCCESS) { 13355 continue; 13356 } 13357 13358 if (sas_wwn == wwid) { 13359 for (i = 0; i < lun_cnt; i++) { 13360 if (repluns[i] == lun) { 13361 find = 1; 13362 break; 13363 } 13364 } 13365 } else { 13366 continue; 13367 } 13368 13369 if (find == 0) { 13370 /* 13371 * The lun has not been there already 13372 */ 13373 (void) mptsas_offline_lun(pdip, NULL, savepip, 13374 NDI_DEVI_REMOVE); 13375 } 13376 } 13377 } 13378 13379 void 13380 mptsas_update_hashtab(struct mptsas *mpt) 13381 { 13382 uint32_t page_address; 13383 int rval = 0; 13384 uint16_t dev_handle; 13385 mptsas_target_t *ptgt = NULL; 13386 mptsas_smp_t smp_node; 13387 13388 /* 13389 * Get latest RAID info. 13390 */ 13391 (void) mptsas_get_raid_info(mpt); 13392 13393 dev_handle = mpt->m_smp_devhdl; 13394 for (; mpt->m_done_traverse_smp == 0; ) { 13395 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 13396 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle; 13397 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node) 13398 != DDI_SUCCESS) { 13399 break; 13400 } 13401 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl; 13402 (void) mptsas_smp_alloc(mpt, &smp_node); 13403 } 13404 13405 /* 13406 * Config target devices 13407 */ 13408 dev_handle = mpt->m_dev_handle; 13409 13410 /* 13411 * Do loop to get sas device page 0 by GetNextHandle till the 13412 * the last handle. If the sas device is a SATA/SSP target, 13413 * we try to config it. 13414 */ 13415 for (; mpt->m_done_traverse_dev == 0; ) { 13416 ptgt = NULL; 13417 page_address = 13418 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 13419 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 13420 (uint32_t)dev_handle; 13421 rval = mptsas_get_target_device_info(mpt, page_address, 13422 &dev_handle, &ptgt); 13423 if ((rval == DEV_INFO_FAIL_PAGE0) || 13424 (rval == DEV_INFO_FAIL_ALLOC)) { 13425 break; 13426 } 13427 13428 mpt->m_dev_handle = dev_handle; 13429 } 13430 13431 } 13432 13433 void 13434 mptsas_update_driver_data(struct mptsas *mpt) 13435 { 13436 mptsas_target_t *tp; 13437 mptsas_smp_t *sp; 13438 13439 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 13440 13441 /* 13442 * TODO after hard reset, update the driver data structures 13443 * 1. update port/phymask mapping table mpt->m_phy_info 13444 * 2. invalid all the entries in hash table 13445 * m_devhdl = 0xffff and m_deviceinfo = 0 13446 * 3. call sas_device_page/expander_page to update hash table 13447 */ 13448 mptsas_update_phymask(mpt); 13449 /* 13450 * Invalid the existing entries 13451 * 13452 * XXX - It seems like we should just delete everything here. We are 13453 * holding the lock and are about to refresh all the targets in both 13454 * hashes anyway. Given the path we're in, what outstanding async 13455 * event could possibly be trying to reference one of these things 13456 * without taking the lock, and how would that be useful anyway? 13457 */ 13458 for (tp = refhash_first(mpt->m_targets); tp != NULL; 13459 tp = refhash_next(mpt->m_targets, tp)) { 13460 tp->m_devhdl = MPTSAS_INVALID_DEVHDL; 13461 tp->m_deviceinfo = 0; 13462 tp->m_dr_flag = MPTSAS_DR_INACTIVE; 13463 } 13464 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 13465 sp = refhash_next(mpt->m_smp_targets, sp)) { 13466 sp->m_devhdl = MPTSAS_INVALID_DEVHDL; 13467 sp->m_deviceinfo = 0; 13468 } 13469 mpt->m_done_traverse_dev = 0; 13470 mpt->m_done_traverse_smp = 0; 13471 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL; 13472 mptsas_update_hashtab(mpt); 13473 } 13474 13475 static void 13476 mptsas_config_all(dev_info_t *pdip) 13477 { 13478 dev_info_t *smpdip = NULL; 13479 mptsas_t *mpt = DIP2MPT(pdip); 13480 int phymask = 0; 13481 mptsas_phymask_t phy_mask; 13482 mptsas_target_t *ptgt = NULL; 13483 mptsas_smp_t *psmp; 13484 13485 /* 13486 * Get the phymask associated to the iport 13487 */ 13488 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 13489 "phymask", 0); 13490 13491 /* 13492 * Enumerate RAID volumes here (phymask == 0). 13493 */ 13494 if (phymask == 0) { 13495 mptsas_config_all_viport(pdip); 13496 return; 13497 } 13498 13499 mutex_enter(&mpt->m_mutex); 13500 13501 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) { 13502 mptsas_update_hashtab(mpt); 13503 } 13504 13505 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL; 13506 psmp = refhash_next(mpt->m_smp_targets, psmp)) { 13507 phy_mask = psmp->m_addr.mta_phymask; 13508 if (phy_mask == phymask) { 13509 smpdip = NULL; 13510 mutex_exit(&mpt->m_mutex); 13511 (void) mptsas_online_smp(pdip, psmp, &smpdip); 13512 mutex_enter(&mpt->m_mutex); 13513 } 13514 } 13515 13516 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 13517 ptgt = refhash_next(mpt->m_targets, ptgt)) { 13518 phy_mask = ptgt->m_addr.mta_phymask; 13519 if (phy_mask == phymask) { 13520 mutex_exit(&mpt->m_mutex); 13521 (void) mptsas_config_target(pdip, ptgt); 13522 mutex_enter(&mpt->m_mutex); 13523 } 13524 } 13525 mutex_exit(&mpt->m_mutex); 13526 } 13527 13528 static int 13529 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt) 13530 { 13531 int rval = DDI_FAILURE; 13532 dev_info_t *tdip; 13533 13534 rval = mptsas_config_luns(pdip, ptgt); 13535 if (rval != DDI_SUCCESS) { 13536 /* 13537 * The return value means the SCMD_REPORT_LUNS 13538 * did not execute successfully. The target maybe 13539 * doesn't support such command. 13540 */ 13541 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt); 13542 } 13543 return (rval); 13544 } 13545 13546 /* 13547 * Return fail if not all the childs/paths are freed. 13548 * if there is any path under the HBA, the return value will be always fail 13549 * because we didn't call mdi_pi_free for path 13550 */ 13551 static int 13552 mptsas_offline_target(dev_info_t *pdip, char *name) 13553 { 13554 dev_info_t *child = NULL, *prechild = NULL; 13555 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 13556 int tmp_rval, rval = DDI_SUCCESS; 13557 char *addr, *cp; 13558 size_t s; 13559 mptsas_t *mpt = DIP2MPT(pdip); 13560 13561 child = ddi_get_child(pdip); 13562 while (child) { 13563 addr = ddi_get_name_addr(child); 13564 prechild = child; 13565 child = ddi_get_next_sibling(child); 13566 13567 if (addr == NULL) { 13568 continue; 13569 } 13570 if ((cp = strchr(addr, ',')) == NULL) { 13571 continue; 13572 } 13573 13574 s = (uintptr_t)cp - (uintptr_t)addr; 13575 13576 if (strncmp(addr, name, s) != 0) { 13577 continue; 13578 } 13579 13580 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL, 13581 NDI_DEVI_REMOVE); 13582 if (tmp_rval != DDI_SUCCESS) { 13583 rval = DDI_FAILURE; 13584 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 13585 prechild, MPTSAS_DEV_GONE) != 13586 DDI_PROP_SUCCESS) { 13587 mptsas_log(mpt, CE_WARN, "mptsas driver " 13588 "unable to create property for " 13589 "SAS %s (MPTSAS_DEV_GONE)", addr); 13590 } 13591 } 13592 } 13593 13594 pip = mdi_get_next_client_path(pdip, NULL); 13595 while (pip) { 13596 addr = MDI_PI(pip)->pi_addr; 13597 savepip = pip; 13598 pip = mdi_get_next_client_path(pdip, pip); 13599 if (addr == NULL) { 13600 continue; 13601 } 13602 13603 if ((cp = strchr(addr, ',')) == NULL) { 13604 continue; 13605 } 13606 13607 s = (uintptr_t)cp - (uintptr_t)addr; 13608 13609 if (strncmp(addr, name, s) != 0) { 13610 continue; 13611 } 13612 13613 (void) mptsas_offline_lun(pdip, NULL, savepip, 13614 NDI_DEVI_REMOVE); 13615 /* 13616 * driver will not invoke mdi_pi_free, so path will not 13617 * be freed forever, return DDI_FAILURE. 13618 */ 13619 rval = DDI_FAILURE; 13620 } 13621 return (rval); 13622 } 13623 13624 static int 13625 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 13626 mdi_pathinfo_t *rpip, uint_t flags) 13627 { 13628 int rval = DDI_FAILURE; 13629 char *devname; 13630 dev_info_t *cdip, *parent; 13631 13632 if (rpip != NULL) { 13633 parent = scsi_vhci_dip; 13634 cdip = mdi_pi_get_client(rpip); 13635 } else if (rdip != NULL) { 13636 parent = pdip; 13637 cdip = rdip; 13638 } else { 13639 return (DDI_FAILURE); 13640 } 13641 13642 /* 13643 * Make sure node is attached otherwise 13644 * it won't have related cache nodes to 13645 * clean up. i_ddi_devi_attached is 13646 * similiar to i_ddi_node_state(cdip) >= 13647 * DS_ATTACHED. 13648 */ 13649 if (i_ddi_devi_attached(cdip)) { 13650 13651 /* Get full devname */ 13652 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 13653 (void) ddi_deviname(cdip, devname); 13654 /* Clean cache */ 13655 (void) devfs_clean(parent, devname + 1, 13656 DV_CLEAN_FORCE); 13657 kmem_free(devname, MAXNAMELEN + 1); 13658 } 13659 if (rpip != NULL) { 13660 if (MDI_PI_IS_OFFLINE(rpip)) { 13661 rval = DDI_SUCCESS; 13662 } else { 13663 rval = mdi_pi_offline(rpip, 0); 13664 } 13665 } else { 13666 rval = ndi_devi_offline(cdip, flags); 13667 } 13668 13669 return (rval); 13670 } 13671 13672 static dev_info_t * 13673 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn) 13674 { 13675 dev_info_t *child = NULL; 13676 char *smp_wwn = NULL; 13677 13678 child = ddi_get_child(parent); 13679 while (child) { 13680 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child, 13681 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn) 13682 != DDI_SUCCESS) { 13683 child = ddi_get_next_sibling(child); 13684 continue; 13685 } 13686 13687 if (strcmp(smp_wwn, str_wwn) == 0) { 13688 ddi_prop_free(smp_wwn); 13689 break; 13690 } 13691 child = ddi_get_next_sibling(child); 13692 ddi_prop_free(smp_wwn); 13693 } 13694 return (child); 13695 } 13696 13697 static int 13698 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags) 13699 { 13700 int rval = DDI_FAILURE; 13701 char *devname; 13702 char wwn_str[MPTSAS_WWN_STRLEN]; 13703 dev_info_t *cdip; 13704 13705 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 13706 13707 cdip = mptsas_find_smp_child(pdip, wwn_str); 13708 13709 if (cdip == NULL) 13710 return (DDI_SUCCESS); 13711 13712 /* 13713 * Make sure node is attached otherwise 13714 * it won't have related cache nodes to 13715 * clean up. i_ddi_devi_attached is 13716 * similiar to i_ddi_node_state(cdip) >= 13717 * DS_ATTACHED. 13718 */ 13719 if (i_ddi_devi_attached(cdip)) { 13720 13721 /* Get full devname */ 13722 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 13723 (void) ddi_deviname(cdip, devname); 13724 /* Clean cache */ 13725 (void) devfs_clean(pdip, devname + 1, 13726 DV_CLEAN_FORCE); 13727 kmem_free(devname, MAXNAMELEN + 1); 13728 } 13729 13730 rval = ndi_devi_offline(cdip, flags); 13731 13732 return (rval); 13733 } 13734 13735 static dev_info_t * 13736 mptsas_find_child(dev_info_t *pdip, char *name) 13737 { 13738 dev_info_t *child = NULL; 13739 char *rname = NULL; 13740 int rval = DDI_FAILURE; 13741 13742 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13743 13744 child = ddi_get_child(pdip); 13745 while (child) { 13746 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN); 13747 if (rval != DDI_SUCCESS) { 13748 child = ddi_get_next_sibling(child); 13749 bzero(rname, SCSI_MAXNAMELEN); 13750 continue; 13751 } 13752 13753 if (strcmp(rname, name) == 0) { 13754 break; 13755 } 13756 child = ddi_get_next_sibling(child); 13757 bzero(rname, SCSI_MAXNAMELEN); 13758 } 13759 13760 kmem_free(rname, SCSI_MAXNAMELEN); 13761 13762 return (child); 13763 } 13764 13765 13766 static dev_info_t * 13767 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun) 13768 { 13769 dev_info_t *child = NULL; 13770 char *name = NULL; 13771 char *addr = NULL; 13772 13773 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13774 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13775 (void) sprintf(name, "%016"PRIx64, sasaddr); 13776 (void) sprintf(addr, "w%s,%x", name, lun); 13777 child = mptsas_find_child(pdip, addr); 13778 kmem_free(name, SCSI_MAXNAMELEN); 13779 kmem_free(addr, SCSI_MAXNAMELEN); 13780 return (child); 13781 } 13782 13783 static dev_info_t * 13784 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy) 13785 { 13786 dev_info_t *child; 13787 char *addr; 13788 13789 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13790 (void) sprintf(addr, "p%x,0", phy); 13791 child = mptsas_find_child(pdip, addr); 13792 kmem_free(addr, SCSI_MAXNAMELEN); 13793 return (child); 13794 } 13795 13796 static mdi_pathinfo_t * 13797 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy) 13798 { 13799 mdi_pathinfo_t *path; 13800 char *addr = NULL; 13801 13802 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13803 (void) sprintf(addr, "p%x,0", phy); 13804 path = mdi_pi_find(pdip, NULL, addr); 13805 kmem_free(addr, SCSI_MAXNAMELEN); 13806 return (path); 13807 } 13808 13809 static mdi_pathinfo_t * 13810 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun) 13811 { 13812 mdi_pathinfo_t *path; 13813 char *name = NULL; 13814 char *addr = NULL; 13815 13816 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13817 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13818 (void) sprintf(name, "%016"PRIx64, sasaddr); 13819 (void) sprintf(addr, "w%s,%x", name, lun); 13820 path = mdi_pi_find(parent, NULL, addr); 13821 kmem_free(name, SCSI_MAXNAMELEN); 13822 kmem_free(addr, SCSI_MAXNAMELEN); 13823 13824 return (path); 13825 } 13826 13827 static int 13828 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 13829 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 13830 { 13831 int i = 0; 13832 uchar_t *inq83 = NULL; 13833 int inq83_len1 = 0xFF; 13834 int inq83_len = 0; 13835 int rval = DDI_FAILURE; 13836 ddi_devid_t devid; 13837 char *guid = NULL; 13838 int target = ptgt->m_devhdl; 13839 mdi_pathinfo_t *pip = NULL; 13840 mptsas_t *mpt = DIP2MPT(pdip); 13841 13842 /* 13843 * For DVD/CD ROM and tape devices and optical 13844 * devices, we won't try to enumerate them under 13845 * scsi_vhci, so no need to try page83 13846 */ 13847 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT || 13848 sd_inq->inq_dtype == DTYPE_OPTICAL || 13849 sd_inq->inq_dtype == DTYPE_ESI)) 13850 goto create_lun; 13851 13852 /* 13853 * The LCA returns good SCSI status, but corrupt page 83 data the first 13854 * time it is queried. The solution is to keep trying to request page83 13855 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in 13856 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver 13857 * give up to get VPD page at this stage and fail the enumeration. 13858 */ 13859 13860 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP); 13861 13862 for (i = 0; i < mptsas_inq83_retry_timeout; i++) { 13863 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 13864 inq83_len1, &inq83_len, 1); 13865 if (rval != 0) { 13866 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 13867 "0x83 for target:%x, lun:%x failed!", target, lun); 13868 if (mptsas_physical_bind_failed_page_83 != B_FALSE) 13869 goto create_lun; 13870 goto out; 13871 } 13872 /* 13873 * create DEVID from inquiry data 13874 */ 13875 if ((rval = ddi_devid_scsi_encode( 13876 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq, 13877 sizeof (struct scsi_inquiry), NULL, 0, inq83, 13878 (size_t)inq83_len, &devid)) == DDI_SUCCESS) { 13879 /* 13880 * extract GUID from DEVID 13881 */ 13882 guid = ddi_devid_to_guid(devid); 13883 13884 /* 13885 * Do not enable MPXIO if the strlen(guid) is greater 13886 * than MPTSAS_MAX_GUID_LEN, this constrain would be 13887 * handled by framework later. 13888 */ 13889 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) { 13890 ddi_devid_free_guid(guid); 13891 guid = NULL; 13892 if (mpt->m_mpxio_enable == TRUE) { 13893 mptsas_log(mpt, CE_NOTE, "!Target:%x, " 13894 "lun:%x doesn't have a valid GUID, " 13895 "multipathing for this drive is " 13896 "not enabled", target, lun); 13897 } 13898 } 13899 13900 /* 13901 * devid no longer needed 13902 */ 13903 ddi_devid_free(devid); 13904 break; 13905 } else if (rval == DDI_NOT_WELL_FORMED) { 13906 /* 13907 * return value of ddi_devid_scsi_encode equal to 13908 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth 13909 * to retry inquiry page 0x83 and get GUID. 13910 */ 13911 NDBG20(("Not well formed devid, retry...")); 13912 delay(1 * drv_usectohz(1000000)); 13913 continue; 13914 } else { 13915 mptsas_log(mpt, CE_WARN, "!Encode devid failed for " 13916 "path target:%x, lun:%x", target, lun); 13917 rval = DDI_FAILURE; 13918 goto create_lun; 13919 } 13920 } 13921 13922 if (i == mptsas_inq83_retry_timeout) { 13923 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout " 13924 "for path target:%x, lun:%x", target, lun); 13925 } 13926 13927 rval = DDI_FAILURE; 13928 13929 create_lun: 13930 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) { 13931 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip, 13932 ptgt, lun); 13933 } 13934 if (rval != DDI_SUCCESS) { 13935 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip, 13936 ptgt, lun); 13937 13938 } 13939 out: 13940 if (guid != NULL) { 13941 /* 13942 * guid no longer needed 13943 */ 13944 ddi_devid_free_guid(guid); 13945 } 13946 if (inq83 != NULL) 13947 kmem_free(inq83, inq83_len1); 13948 return (rval); 13949 } 13950 13951 static int 13952 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid, 13953 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun) 13954 { 13955 int target; 13956 char *nodename = NULL; 13957 char **compatible = NULL; 13958 int ncompatible = 0; 13959 int mdi_rtn = MDI_FAILURE; 13960 int rval = DDI_FAILURE; 13961 char *old_guid = NULL; 13962 mptsas_t *mpt = DIP2MPT(pdip); 13963 char *lun_addr = NULL; 13964 char *wwn_str = NULL; 13965 char *attached_wwn_str = NULL; 13966 char *component = NULL; 13967 uint8_t phy = 0xFF; 13968 uint64_t sas_wwn; 13969 int64_t lun64 = 0; 13970 uint32_t devinfo; 13971 uint16_t dev_hdl; 13972 uint16_t pdev_hdl; 13973 uint64_t dev_sas_wwn; 13974 uint64_t pdev_sas_wwn; 13975 uint32_t pdev_info; 13976 uint8_t physport; 13977 uint8_t phy_id; 13978 uint32_t page_address; 13979 uint16_t bay_num, enclosure; 13980 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 13981 uint32_t dev_info; 13982 13983 mutex_enter(&mpt->m_mutex); 13984 target = ptgt->m_devhdl; 13985 sas_wwn = ptgt->m_addr.mta_wwn; 13986 devinfo = ptgt->m_deviceinfo; 13987 phy = ptgt->m_phynum; 13988 mutex_exit(&mpt->m_mutex); 13989 13990 if (sas_wwn) { 13991 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun); 13992 } else { 13993 *pip = mptsas_find_path_phy(pdip, phy); 13994 } 13995 13996 if (*pip != NULL) { 13997 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 13998 ASSERT(*lun_dip != NULL); 13999 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip, 14000 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM), 14001 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) { 14002 if (strncmp(guid, old_guid, strlen(guid)) == 0) { 14003 /* 14004 * Same path back online again. 14005 */ 14006 (void) ddi_prop_free(old_guid); 14007 if ((!MDI_PI_IS_ONLINE(*pip)) && 14008 (!MDI_PI_IS_STANDBY(*pip)) && 14009 (ptgt->m_tgt_unconfigured == 0)) { 14010 rval = mdi_pi_online(*pip, 0); 14011 mutex_enter(&mpt->m_mutex); 14012 ptgt->m_led_status = 0; 14013 (void) mptsas_flush_led_status(mpt, 14014 ptgt); 14015 mutex_exit(&mpt->m_mutex); 14016 } else { 14017 rval = DDI_SUCCESS; 14018 } 14019 if (rval != DDI_SUCCESS) { 14020 mptsas_log(mpt, CE_WARN, "path:target: " 14021 "%x, lun:%x online failed!", target, 14022 lun); 14023 *pip = NULL; 14024 *lun_dip = NULL; 14025 } 14026 return (rval); 14027 } else { 14028 /* 14029 * The GUID of the LUN has changed which maybe 14030 * because customer mapped another volume to the 14031 * same LUN. 14032 */ 14033 mptsas_log(mpt, CE_WARN, "The GUID of the " 14034 "target:%x, lun:%x was changed, maybe " 14035 "because someone mapped another volume " 14036 "to the same LUN", target, lun); 14037 (void) ddi_prop_free(old_guid); 14038 if (!MDI_PI_IS_OFFLINE(*pip)) { 14039 rval = mdi_pi_offline(*pip, 0); 14040 if (rval != MDI_SUCCESS) { 14041 mptsas_log(mpt, CE_WARN, "path:" 14042 "target:%x, lun:%x offline " 14043 "failed!", target, lun); 14044 *pip = NULL; 14045 *lun_dip = NULL; 14046 return (DDI_FAILURE); 14047 } 14048 } 14049 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) { 14050 mptsas_log(mpt, CE_WARN, "path:target:" 14051 "%x, lun:%x free failed!", target, 14052 lun); 14053 *pip = NULL; 14054 *lun_dip = NULL; 14055 return (DDI_FAILURE); 14056 } 14057 } 14058 } else { 14059 mptsas_log(mpt, CE_WARN, "Can't get client-guid " 14060 "property for path:target:%x, lun:%x", target, lun); 14061 *pip = NULL; 14062 *lun_dip = NULL; 14063 return (DDI_FAILURE); 14064 } 14065 } 14066 scsi_hba_nodename_compatible_get(inq, NULL, 14067 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible); 14068 14069 /* 14070 * if nodename can't be determined then print a message and skip it 14071 */ 14072 if (nodename == NULL) { 14073 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible " 14074 "driver for target%d lun %d dtype:0x%02x", target, lun, 14075 inq->inq_dtype); 14076 return (DDI_FAILURE); 14077 } 14078 14079 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 14080 /* The property is needed by MPAPI */ 14081 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 14082 14083 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14084 if (guid) { 14085 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun); 14086 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 14087 } else { 14088 (void) sprintf(lun_addr, "p%x,%x", phy, lun); 14089 (void) sprintf(wwn_str, "p%x", phy); 14090 } 14091 14092 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename, 14093 guid, lun_addr, compatible, ncompatible, 14094 0, pip); 14095 if (mdi_rtn == MDI_SUCCESS) { 14096 14097 if (mdi_prop_update_string(*pip, MDI_GUID, 14098 guid) != DDI_SUCCESS) { 14099 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14100 "create prop for target %d lun %d (MDI_GUID)", 14101 target, lun); 14102 mdi_rtn = MDI_FAILURE; 14103 goto virt_create_done; 14104 } 14105 14106 if (mdi_prop_update_int(*pip, LUN_PROP, 14107 lun) != DDI_SUCCESS) { 14108 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14109 "create prop for target %d lun %d (LUN_PROP)", 14110 target, lun); 14111 mdi_rtn = MDI_FAILURE; 14112 goto virt_create_done; 14113 } 14114 lun64 = (int64_t)lun; 14115 if (mdi_prop_update_int64(*pip, LUN64_PROP, 14116 lun64) != DDI_SUCCESS) { 14117 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14118 "create prop for target %d (LUN64_PROP)", 14119 target); 14120 mdi_rtn = MDI_FAILURE; 14121 goto virt_create_done; 14122 } 14123 if (mdi_prop_update_string_array(*pip, "compatible", 14124 compatible, ncompatible) != 14125 DDI_PROP_SUCCESS) { 14126 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14127 "create prop for target %d lun %d (COMPATIBLE)", 14128 target, lun); 14129 mdi_rtn = MDI_FAILURE; 14130 goto virt_create_done; 14131 } 14132 if (sas_wwn && (mdi_prop_update_string(*pip, 14133 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) { 14134 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14135 "create prop for target %d lun %d " 14136 "(target-port)", target, lun); 14137 mdi_rtn = MDI_FAILURE; 14138 goto virt_create_done; 14139 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip, 14140 "sata-phy", phy) != DDI_PROP_SUCCESS)) { 14141 /* 14142 * Direct attached SATA device without DeviceName 14143 */ 14144 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14145 "create prop for SAS target %d lun %d " 14146 "(sata-phy)", target, lun); 14147 mdi_rtn = MDI_FAILURE; 14148 goto virt_create_done; 14149 } 14150 mutex_enter(&mpt->m_mutex); 14151 14152 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14153 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14154 (uint32_t)ptgt->m_devhdl; 14155 rval = mptsas_get_sas_device_page0(mpt, page_address, 14156 &dev_hdl, &dev_sas_wwn, &dev_info, &physport, 14157 &phy_id, &pdev_hdl, &bay_num, &enclosure); 14158 if (rval != DDI_SUCCESS) { 14159 mutex_exit(&mpt->m_mutex); 14160 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 14161 "parent device for handle %d", page_address); 14162 mdi_rtn = MDI_FAILURE; 14163 goto virt_create_done; 14164 } 14165 14166 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14167 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 14168 rval = mptsas_get_sas_device_page0(mpt, page_address, 14169 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 14170 &phy_id, &pdev_hdl, &bay_num, &enclosure); 14171 if (rval != DDI_SUCCESS) { 14172 mutex_exit(&mpt->m_mutex); 14173 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 14174 "device info for handle %d", page_address); 14175 mdi_rtn = MDI_FAILURE; 14176 goto virt_create_done; 14177 } 14178 14179 mutex_exit(&mpt->m_mutex); 14180 14181 /* 14182 * If this device direct attached to the controller 14183 * set the attached-port to the base wwid 14184 */ 14185 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 14186 != DEVINFO_DIRECT_ATTACHED) { 14187 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 14188 pdev_sas_wwn); 14189 } else { 14190 /* 14191 * Update the iport's attached-port to guid 14192 */ 14193 if (sas_wwn == 0) { 14194 (void) sprintf(wwn_str, "p%x", phy); 14195 } else { 14196 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 14197 } 14198 if (ddi_prop_update_string(DDI_DEV_T_NONE, 14199 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 14200 DDI_PROP_SUCCESS) { 14201 mptsas_log(mpt, CE_WARN, 14202 "mptsas unable to create " 14203 "property for iport target-port" 14204 " %s (sas_wwn)", 14205 wwn_str); 14206 mdi_rtn = MDI_FAILURE; 14207 goto virt_create_done; 14208 } 14209 14210 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 14211 mpt->un.m_base_wwid); 14212 } 14213 14214 if (mdi_prop_update_string(*pip, 14215 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 14216 DDI_PROP_SUCCESS) { 14217 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14218 "property for iport attached-port %s (sas_wwn)", 14219 attached_wwn_str); 14220 mdi_rtn = MDI_FAILURE; 14221 goto virt_create_done; 14222 } 14223 14224 14225 if (inq->inq_dtype == 0) { 14226 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 14227 /* 14228 * set obp path for pathinfo 14229 */ 14230 (void) snprintf(component, MAXPATHLEN, 14231 "disk@%s", lun_addr); 14232 14233 if (mdi_pi_pathname_obp_set(*pip, component) != 14234 DDI_SUCCESS) { 14235 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 14236 "unable to set obp-path for object %s", 14237 component); 14238 mdi_rtn = MDI_FAILURE; 14239 goto virt_create_done; 14240 } 14241 } 14242 14243 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 14244 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 14245 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 14246 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip, 14247 "pm-capable", 1)) != 14248 DDI_PROP_SUCCESS) { 14249 mptsas_log(mpt, CE_WARN, "mptsas driver" 14250 "failed to create pm-capable " 14251 "property, target %d", target); 14252 mdi_rtn = MDI_FAILURE; 14253 goto virt_create_done; 14254 } 14255 } 14256 /* 14257 * Create the phy-num property 14258 */ 14259 if (mdi_prop_update_int(*pip, "phy-num", 14260 ptgt->m_phynum) != DDI_SUCCESS) { 14261 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14262 "create phy-num property for target %d lun %d", 14263 target, lun); 14264 mdi_rtn = MDI_FAILURE; 14265 goto virt_create_done; 14266 } 14267 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr)); 14268 mdi_rtn = mdi_pi_online(*pip, 0); 14269 if (mdi_rtn == MDI_SUCCESS) { 14270 mutex_enter(&mpt->m_mutex); 14271 ptgt->m_led_status = 0; 14272 (void) mptsas_flush_led_status(mpt, ptgt); 14273 mutex_exit(&mpt->m_mutex); 14274 } 14275 if (mdi_rtn == MDI_NOT_SUPPORTED) { 14276 mdi_rtn = MDI_FAILURE; 14277 } 14278 virt_create_done: 14279 if (*pip && mdi_rtn != MDI_SUCCESS) { 14280 (void) mdi_pi_free(*pip, 0); 14281 *pip = NULL; 14282 *lun_dip = NULL; 14283 } 14284 } 14285 14286 scsi_hba_nodename_compatible_free(nodename, compatible); 14287 if (lun_addr != NULL) { 14288 kmem_free(lun_addr, SCSI_MAXNAMELEN); 14289 } 14290 if (wwn_str != NULL) { 14291 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 14292 } 14293 if (component != NULL) { 14294 kmem_free(component, MAXPATHLEN); 14295 } 14296 14297 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 14298 } 14299 14300 static int 14301 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq, 14302 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 14303 { 14304 int target; 14305 int rval; 14306 int ndi_rtn = NDI_FAILURE; 14307 uint64_t be_sas_wwn; 14308 char *nodename = NULL; 14309 char **compatible = NULL; 14310 int ncompatible = 0; 14311 int instance = 0; 14312 mptsas_t *mpt = DIP2MPT(pdip); 14313 char *wwn_str = NULL; 14314 char *component = NULL; 14315 char *attached_wwn_str = NULL; 14316 uint8_t phy = 0xFF; 14317 uint64_t sas_wwn; 14318 uint32_t devinfo; 14319 uint16_t dev_hdl; 14320 uint16_t pdev_hdl; 14321 uint64_t pdev_sas_wwn; 14322 uint64_t dev_sas_wwn; 14323 uint32_t pdev_info; 14324 uint8_t physport; 14325 uint8_t phy_id; 14326 uint32_t page_address; 14327 uint16_t bay_num, enclosure; 14328 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 14329 uint32_t dev_info; 14330 int64_t lun64 = 0; 14331 14332 mutex_enter(&mpt->m_mutex); 14333 target = ptgt->m_devhdl; 14334 sas_wwn = ptgt->m_addr.mta_wwn; 14335 devinfo = ptgt->m_deviceinfo; 14336 phy = ptgt->m_phynum; 14337 mutex_exit(&mpt->m_mutex); 14338 14339 /* 14340 * generate compatible property with binding-set "mpt" 14341 */ 14342 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL, 14343 &nodename, &compatible, &ncompatible); 14344 14345 /* 14346 * if nodename can't be determined then print a message and skip it 14347 */ 14348 if (nodename == NULL) { 14349 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver " 14350 "for target %d lun %d", target, lun); 14351 return (DDI_FAILURE); 14352 } 14353 14354 ndi_rtn = ndi_devi_alloc(pdip, nodename, 14355 DEVI_SID_NODEID, lun_dip); 14356 14357 /* 14358 * if lun alloc success, set props 14359 */ 14360 if (ndi_rtn == NDI_SUCCESS) { 14361 14362 if (ndi_prop_update_int(DDI_DEV_T_NONE, 14363 *lun_dip, LUN_PROP, lun) != 14364 DDI_PROP_SUCCESS) { 14365 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14366 "property for target %d lun %d (LUN_PROP)", 14367 target, lun); 14368 ndi_rtn = NDI_FAILURE; 14369 goto phys_create_done; 14370 } 14371 14372 lun64 = (int64_t)lun; 14373 if (ndi_prop_update_int64(DDI_DEV_T_NONE, 14374 *lun_dip, LUN64_PROP, lun64) != 14375 DDI_PROP_SUCCESS) { 14376 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14377 "property for target %d lun64 %d (LUN64_PROP)", 14378 target, lun); 14379 ndi_rtn = NDI_FAILURE; 14380 goto phys_create_done; 14381 } 14382 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, 14383 *lun_dip, "compatible", compatible, ncompatible) 14384 != DDI_PROP_SUCCESS) { 14385 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14386 "property for target %d lun %d (COMPATIBLE)", 14387 target, lun); 14388 ndi_rtn = NDI_FAILURE; 14389 goto phys_create_done; 14390 } 14391 14392 /* 14393 * We need the SAS WWN for non-multipath devices, so 14394 * we'll use the same property as that multipathing 14395 * devices need to present for MPAPI. If we don't have 14396 * a WWN (e.g. parallel SCSI), don't create the prop. 14397 */ 14398 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 14399 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 14400 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE, 14401 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) 14402 != DDI_PROP_SUCCESS) { 14403 mptsas_log(mpt, CE_WARN, "mptsas unable to " 14404 "create property for SAS target %d lun %d " 14405 "(target-port)", target, lun); 14406 ndi_rtn = NDI_FAILURE; 14407 goto phys_create_done; 14408 } 14409 14410 be_sas_wwn = BE_64(sas_wwn); 14411 if (sas_wwn && ndi_prop_update_byte_array( 14412 DDI_DEV_T_NONE, *lun_dip, "port-wwn", 14413 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) { 14414 mptsas_log(mpt, CE_WARN, "mptsas unable to " 14415 "create property for SAS target %d lun %d " 14416 "(port-wwn)", target, lun); 14417 ndi_rtn = NDI_FAILURE; 14418 goto phys_create_done; 14419 } else if ((sas_wwn == 0) && (ndi_prop_update_int( 14420 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) != 14421 DDI_PROP_SUCCESS)) { 14422 /* 14423 * Direct attached SATA device without DeviceName 14424 */ 14425 mptsas_log(mpt, CE_WARN, "mptsas unable to " 14426 "create property for SAS target %d lun %d " 14427 "(sata-phy)", target, lun); 14428 ndi_rtn = NDI_FAILURE; 14429 goto phys_create_done; 14430 } 14431 14432 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 14433 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) { 14434 mptsas_log(mpt, CE_WARN, "mptsas unable to" 14435 "create property for SAS target %d lun %d" 14436 " (SAS_PROP)", target, lun); 14437 ndi_rtn = NDI_FAILURE; 14438 goto phys_create_done; 14439 } 14440 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE, 14441 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) { 14442 mptsas_log(mpt, CE_WARN, "mptsas unable " 14443 "to create guid property for target %d " 14444 "lun %d", target, lun); 14445 ndi_rtn = NDI_FAILURE; 14446 goto phys_create_done; 14447 } 14448 14449 /* 14450 * The following code is to set properties for SM-HBA support, 14451 * it doesn't apply to RAID volumes 14452 */ 14453 if (ptgt->m_addr.mta_phymask == 0) 14454 goto phys_raid_lun; 14455 14456 mutex_enter(&mpt->m_mutex); 14457 14458 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14459 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14460 (uint32_t)ptgt->m_devhdl; 14461 rval = mptsas_get_sas_device_page0(mpt, page_address, 14462 &dev_hdl, &dev_sas_wwn, &dev_info, 14463 &physport, &phy_id, &pdev_hdl, 14464 &bay_num, &enclosure); 14465 if (rval != DDI_SUCCESS) { 14466 mutex_exit(&mpt->m_mutex); 14467 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 14468 "parent device for handle %d.", page_address); 14469 ndi_rtn = NDI_FAILURE; 14470 goto phys_create_done; 14471 } 14472 14473 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14474 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 14475 rval = mptsas_get_sas_device_page0(mpt, page_address, 14476 &dev_hdl, &pdev_sas_wwn, &pdev_info, 14477 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure); 14478 if (rval != DDI_SUCCESS) { 14479 mutex_exit(&mpt->m_mutex); 14480 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14481 "device for handle %d.", page_address); 14482 ndi_rtn = NDI_FAILURE; 14483 goto phys_create_done; 14484 } 14485 14486 mutex_exit(&mpt->m_mutex); 14487 14488 /* 14489 * If this device direct attached to the controller 14490 * set the attached-port to the base wwid 14491 */ 14492 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 14493 != DEVINFO_DIRECT_ATTACHED) { 14494 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 14495 pdev_sas_wwn); 14496 } else { 14497 /* 14498 * Update the iport's attached-port to guid 14499 */ 14500 if (sas_wwn == 0) { 14501 (void) sprintf(wwn_str, "p%x", phy); 14502 } else { 14503 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 14504 } 14505 if (ddi_prop_update_string(DDI_DEV_T_NONE, 14506 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 14507 DDI_PROP_SUCCESS) { 14508 mptsas_log(mpt, CE_WARN, 14509 "mptsas unable to create " 14510 "property for iport target-port" 14511 " %s (sas_wwn)", 14512 wwn_str); 14513 ndi_rtn = NDI_FAILURE; 14514 goto phys_create_done; 14515 } 14516 14517 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 14518 mpt->un.m_base_wwid); 14519 } 14520 14521 if (ndi_prop_update_string(DDI_DEV_T_NONE, 14522 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 14523 DDI_PROP_SUCCESS) { 14524 mptsas_log(mpt, CE_WARN, 14525 "mptsas unable to create " 14526 "property for iport attached-port %s (sas_wwn)", 14527 attached_wwn_str); 14528 ndi_rtn = NDI_FAILURE; 14529 goto phys_create_done; 14530 } 14531 14532 if (IS_SATA_DEVICE(dev_info)) { 14533 if (ndi_prop_update_string(DDI_DEV_T_NONE, 14534 *lun_dip, MPTSAS_VARIANT, "sata") != 14535 DDI_PROP_SUCCESS) { 14536 mptsas_log(mpt, CE_WARN, 14537 "mptsas unable to create " 14538 "property for device variant "); 14539 ndi_rtn = NDI_FAILURE; 14540 goto phys_create_done; 14541 } 14542 } 14543 14544 if (IS_ATAPI_DEVICE(dev_info)) { 14545 if (ndi_prop_update_string(DDI_DEV_T_NONE, 14546 *lun_dip, MPTSAS_VARIANT, "atapi") != 14547 DDI_PROP_SUCCESS) { 14548 mptsas_log(mpt, CE_WARN, 14549 "mptsas unable to create " 14550 "property for device variant "); 14551 ndi_rtn = NDI_FAILURE; 14552 goto phys_create_done; 14553 } 14554 } 14555 14556 phys_raid_lun: 14557 /* 14558 * if this is a SAS controller, and the target is a SATA 14559 * drive, set the 'pm-capable' property for sd and if on 14560 * an OPL platform, also check if this is an ATAPI 14561 * device. 14562 */ 14563 instance = ddi_get_instance(mpt->m_dip); 14564 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 14565 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 14566 NDBG2(("mptsas%d: creating pm-capable property, " 14567 "target %d", instance, target)); 14568 14569 if ((ndi_prop_update_int(DDI_DEV_T_NONE, 14570 *lun_dip, "pm-capable", 1)) != 14571 DDI_PROP_SUCCESS) { 14572 mptsas_log(mpt, CE_WARN, "mptsas " 14573 "failed to create pm-capable " 14574 "property, target %d", target); 14575 ndi_rtn = NDI_FAILURE; 14576 goto phys_create_done; 14577 } 14578 14579 } 14580 14581 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) { 14582 /* 14583 * add 'obp-path' properties for devinfo 14584 */ 14585 bzero(wwn_str, sizeof (wwn_str)); 14586 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 14587 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 14588 if (guid) { 14589 (void) snprintf(component, MAXPATHLEN, 14590 "disk@w%s,%x", wwn_str, lun); 14591 } else { 14592 (void) snprintf(component, MAXPATHLEN, 14593 "disk@p%x,%x", phy, lun); 14594 } 14595 if (ddi_pathname_obp_set(*lun_dip, component) 14596 != DDI_SUCCESS) { 14597 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 14598 "unable to set obp-path for SAS " 14599 "object %s", component); 14600 ndi_rtn = NDI_FAILURE; 14601 goto phys_create_done; 14602 } 14603 } 14604 /* 14605 * Create the phy-num property for non-raid disk 14606 */ 14607 if (ptgt->m_addr.mta_phymask != 0) { 14608 if (ndi_prop_update_int(DDI_DEV_T_NONE, 14609 *lun_dip, "phy-num", ptgt->m_phynum) != 14610 DDI_PROP_SUCCESS) { 14611 mptsas_log(mpt, CE_WARN, "mptsas driver " 14612 "failed to create phy-num property for " 14613 "target %d", target); 14614 ndi_rtn = NDI_FAILURE; 14615 goto phys_create_done; 14616 } 14617 } 14618 phys_create_done: 14619 /* 14620 * If props were setup ok, online the lun 14621 */ 14622 if (ndi_rtn == NDI_SUCCESS) { 14623 /* 14624 * Try to online the new node 14625 */ 14626 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH); 14627 } 14628 if (ndi_rtn == NDI_SUCCESS) { 14629 mutex_enter(&mpt->m_mutex); 14630 ptgt->m_led_status = 0; 14631 (void) mptsas_flush_led_status(mpt, ptgt); 14632 mutex_exit(&mpt->m_mutex); 14633 } 14634 14635 /* 14636 * If success set rtn flag, else unwire alloc'd lun 14637 */ 14638 if (ndi_rtn != NDI_SUCCESS) { 14639 NDBG12(("mptsas driver unable to online " 14640 "target %d lun %d", target, lun)); 14641 ndi_prop_remove_all(*lun_dip); 14642 (void) ndi_devi_free(*lun_dip); 14643 *lun_dip = NULL; 14644 } 14645 } 14646 14647 scsi_hba_nodename_compatible_free(nodename, compatible); 14648 14649 if (wwn_str != NULL) { 14650 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 14651 } 14652 if (component != NULL) { 14653 kmem_free(component, MAXPATHLEN); 14654 } 14655 14656 14657 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 14658 } 14659 14660 static int 14661 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn) 14662 { 14663 mptsas_t *mpt = DIP2MPT(pdip); 14664 struct smp_device smp_sd; 14665 14666 /* XXX An HBA driver should not be allocating an smp_device. */ 14667 bzero(&smp_sd, sizeof (struct smp_device)); 14668 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran; 14669 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE); 14670 14671 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS) 14672 return (NDI_FAILURE); 14673 return (NDI_SUCCESS); 14674 } 14675 14676 static int 14677 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip) 14678 { 14679 mptsas_t *mpt = DIP2MPT(pdip); 14680 mptsas_smp_t *psmp = NULL; 14681 int rval; 14682 int phymask; 14683 14684 /* 14685 * Get the physical port associated to the iport 14686 * PHYMASK TODO 14687 */ 14688 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14689 "phymask", 0); 14690 /* 14691 * Find the smp node in hash table with specified sas address and 14692 * physical port 14693 */ 14694 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn); 14695 if (psmp == NULL) { 14696 return (DDI_FAILURE); 14697 } 14698 14699 rval = mptsas_online_smp(pdip, psmp, smp_dip); 14700 14701 return (rval); 14702 } 14703 14704 static int 14705 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 14706 dev_info_t **smp_dip) 14707 { 14708 char wwn_str[MPTSAS_WWN_STRLEN]; 14709 char attached_wwn_str[MPTSAS_WWN_STRLEN]; 14710 int ndi_rtn = NDI_FAILURE; 14711 int rval = 0; 14712 mptsas_smp_t dev_info; 14713 uint32_t page_address; 14714 mptsas_t *mpt = DIP2MPT(pdip); 14715 uint16_t dev_hdl; 14716 uint64_t sas_wwn; 14717 uint64_t smp_sas_wwn; 14718 uint8_t physport; 14719 uint8_t phy_id; 14720 uint16_t pdev_hdl; 14721 uint8_t numphys = 0; 14722 uint16_t i = 0; 14723 char phymask[MPTSAS_MAX_PHYS]; 14724 char *iport = NULL; 14725 mptsas_phymask_t phy_mask = 0; 14726 uint16_t attached_devhdl; 14727 uint16_t bay_num, enclosure; 14728 14729 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 14730 14731 /* 14732 * Probe smp device, prevent the node of removed device from being 14733 * configured succesfully 14734 */ 14735 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) { 14736 return (DDI_FAILURE); 14737 } 14738 14739 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) { 14740 return (DDI_SUCCESS); 14741 } 14742 14743 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip); 14744 14745 /* 14746 * if lun alloc success, set props 14747 */ 14748 if (ndi_rtn == NDI_SUCCESS) { 14749 /* 14750 * Set the flavor of the child to be SMP flavored 14751 */ 14752 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP); 14753 14754 if (ndi_prop_update_string(DDI_DEV_T_NONE, 14755 *smp_dip, SMP_WWN, wwn_str) != 14756 DDI_PROP_SUCCESS) { 14757 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14758 "property for smp device %s (sas_wwn)", 14759 wwn_str); 14760 ndi_rtn = NDI_FAILURE; 14761 goto smp_create_done; 14762 } 14763 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn); 14764 if (ndi_prop_update_string(DDI_DEV_T_NONE, 14765 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != 14766 DDI_PROP_SUCCESS) { 14767 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14768 "property for iport target-port %s (sas_wwn)", 14769 wwn_str); 14770 ndi_rtn = NDI_FAILURE; 14771 goto smp_create_done; 14772 } 14773 14774 mutex_enter(&mpt->m_mutex); 14775 14776 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 14777 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl; 14778 rval = mptsas_get_sas_expander_page0(mpt, page_address, 14779 &dev_info); 14780 if (rval != DDI_SUCCESS) { 14781 mutex_exit(&mpt->m_mutex); 14782 mptsas_log(mpt, CE_WARN, 14783 "mptsas unable to get expander " 14784 "parent device info for %x", page_address); 14785 ndi_rtn = NDI_FAILURE; 14786 goto smp_create_done; 14787 } 14788 14789 smp_node->m_pdevhdl = dev_info.m_pdevhdl; 14790 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14791 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14792 (uint32_t)dev_info.m_pdevhdl; 14793 rval = mptsas_get_sas_device_page0(mpt, page_address, 14794 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, 14795 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure); 14796 if (rval != DDI_SUCCESS) { 14797 mutex_exit(&mpt->m_mutex); 14798 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 14799 "device info for %x", page_address); 14800 ndi_rtn = NDI_FAILURE; 14801 goto smp_create_done; 14802 } 14803 14804 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14805 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14806 (uint32_t)dev_info.m_devhdl; 14807 rval = mptsas_get_sas_device_page0(mpt, page_address, 14808 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo, 14809 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure); 14810 if (rval != DDI_SUCCESS) { 14811 mutex_exit(&mpt->m_mutex); 14812 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 14813 "device info for %x", page_address); 14814 ndi_rtn = NDI_FAILURE; 14815 goto smp_create_done; 14816 } 14817 mutex_exit(&mpt->m_mutex); 14818 14819 /* 14820 * If this smp direct attached to the controller 14821 * set the attached-port to the base wwid 14822 */ 14823 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 14824 != DEVINFO_DIRECT_ATTACHED) { 14825 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 14826 sas_wwn); 14827 } else { 14828 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 14829 mpt->un.m_base_wwid); 14830 } 14831 14832 if (ndi_prop_update_string(DDI_DEV_T_NONE, 14833 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) != 14834 DDI_PROP_SUCCESS) { 14835 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14836 "property for smp attached-port %s (sas_wwn)", 14837 attached_wwn_str); 14838 ndi_rtn = NDI_FAILURE; 14839 goto smp_create_done; 14840 } 14841 14842 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 14843 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) { 14844 mptsas_log(mpt, CE_WARN, "mptsas unable to " 14845 "create property for SMP %s (SMP_PROP) ", 14846 wwn_str); 14847 ndi_rtn = NDI_FAILURE; 14848 goto smp_create_done; 14849 } 14850 14851 /* 14852 * check the smp to see whether it direct 14853 * attached to the controller 14854 */ 14855 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 14856 != DEVINFO_DIRECT_ATTACHED) { 14857 goto smp_create_done; 14858 } 14859 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 14860 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1); 14861 if (numphys > 0) { 14862 goto smp_create_done; 14863 } 14864 /* 14865 * this iport is an old iport, we need to 14866 * reconfig the props for it. 14867 */ 14868 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 14869 MPTSAS_VIRTUAL_PORT, 0) != 14870 DDI_PROP_SUCCESS) { 14871 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 14872 MPTSAS_VIRTUAL_PORT); 14873 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 14874 "prop update failed"); 14875 goto smp_create_done; 14876 } 14877 14878 mutex_enter(&mpt->m_mutex); 14879 numphys = 0; 14880 iport = ddi_get_name_addr(pdip); 14881 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 14882 bzero(phymask, sizeof (phymask)); 14883 (void) sprintf(phymask, 14884 "%x", mpt->m_phy_info[i].phy_mask); 14885 if (strcmp(phymask, iport) == 0) { 14886 phy_mask = mpt->m_phy_info[i].phy_mask; 14887 break; 14888 } 14889 } 14890 14891 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 14892 if ((phy_mask >> i) & 0x01) { 14893 numphys++; 14894 } 14895 } 14896 /* 14897 * Update PHY info for smhba 14898 */ 14899 if (mptsas_smhba_phy_init(mpt)) { 14900 mutex_exit(&mpt->m_mutex); 14901 mptsas_log(mpt, CE_WARN, "mptsas phy update " 14902 "failed"); 14903 goto smp_create_done; 14904 } 14905 mutex_exit(&mpt->m_mutex); 14906 14907 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask, 14908 &attached_devhdl); 14909 14910 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 14911 MPTSAS_NUM_PHYS, numphys) != 14912 DDI_PROP_SUCCESS) { 14913 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 14914 MPTSAS_NUM_PHYS); 14915 mptsas_log(mpt, CE_WARN, "mptsas update " 14916 "num phys props failed"); 14917 goto smp_create_done; 14918 } 14919 /* 14920 * Add parent's props for SMHBA support 14921 */ 14922 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip, 14923 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 14924 DDI_PROP_SUCCESS) { 14925 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 14926 SCSI_ADDR_PROP_ATTACHED_PORT); 14927 mptsas_log(mpt, CE_WARN, "mptsas update iport" 14928 "attached-port failed"); 14929 goto smp_create_done; 14930 } 14931 14932 smp_create_done: 14933 /* 14934 * If props were setup ok, online the lun 14935 */ 14936 if (ndi_rtn == NDI_SUCCESS) { 14937 /* 14938 * Try to online the new node 14939 */ 14940 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH); 14941 } 14942 14943 /* 14944 * If success set rtn flag, else unwire alloc'd lun 14945 */ 14946 if (ndi_rtn != NDI_SUCCESS) { 14947 NDBG12(("mptsas unable to online " 14948 "SMP target %s", wwn_str)); 14949 ndi_prop_remove_all(*smp_dip); 14950 (void) ndi_devi_free(*smp_dip); 14951 } 14952 } 14953 14954 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 14955 } 14956 14957 /* smp transport routine */ 14958 static int mptsas_smp_start(struct smp_pkt *smp_pkt) 14959 { 14960 uint64_t wwn; 14961 Mpi2SmpPassthroughRequest_t req; 14962 Mpi2SmpPassthroughReply_t rep; 14963 uint32_t direction = 0; 14964 mptsas_t *mpt; 14965 int ret; 14966 uint64_t tmp64; 14967 14968 mpt = (mptsas_t *)smp_pkt->smp_pkt_address-> 14969 smp_a_hba_tran->smp_tran_hba_private; 14970 14971 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE); 14972 /* 14973 * Need to compose a SMP request message 14974 * and call mptsas_do_passthru() function 14975 */ 14976 bzero(&req, sizeof (req)); 14977 bzero(&rep, sizeof (rep)); 14978 req.PassthroughFlags = 0; 14979 req.PhysicalPort = 0xff; 14980 req.ChainOffset = 0; 14981 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH; 14982 14983 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) { 14984 smp_pkt->smp_pkt_reason = ERANGE; 14985 return (DDI_FAILURE); 14986 } 14987 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4)); 14988 14989 req.MsgFlags = 0; 14990 tmp64 = LE_64(wwn); 14991 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE); 14992 if (smp_pkt->smp_pkt_rspsize > 0) { 14993 direction |= MPTSAS_PASS_THRU_DIRECTION_READ; 14994 } 14995 if (smp_pkt->smp_pkt_reqsize > 0) { 14996 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE; 14997 } 14998 14999 mutex_enter(&mpt->m_mutex); 15000 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, 15001 (uint8_t *)smp_pkt->smp_pkt_rsp, 15002 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep), 15003 smp_pkt->smp_pkt_rspsize - 4, direction, 15004 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4, 15005 smp_pkt->smp_pkt_timeout, FKIOCTL); 15006 mutex_exit(&mpt->m_mutex); 15007 if (ret != 0) { 15008 cmn_err(CE_WARN, "smp_start do passthru error %d", ret); 15009 smp_pkt->smp_pkt_reason = (uchar_t)(ret); 15010 return (DDI_FAILURE); 15011 } 15012 /* do passthrough success, check the smp status */ 15013 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 15014 switch (LE_16(rep.IOCStatus)) { 15015 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 15016 smp_pkt->smp_pkt_reason = ENODEV; 15017 break; 15018 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 15019 smp_pkt->smp_pkt_reason = EOVERFLOW; 15020 break; 15021 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 15022 smp_pkt->smp_pkt_reason = EIO; 15023 break; 15024 default: 15025 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc" 15026 "status:%x", LE_16(rep.IOCStatus)); 15027 smp_pkt->smp_pkt_reason = EIO; 15028 break; 15029 } 15030 return (DDI_FAILURE); 15031 } 15032 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) { 15033 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x", 15034 rep.SASStatus); 15035 smp_pkt->smp_pkt_reason = EIO; 15036 return (DDI_FAILURE); 15037 } 15038 15039 return (DDI_SUCCESS); 15040 } 15041 15042 /* 15043 * If we didn't get a match, we need to get sas page0 for each device, and 15044 * untill we get a match. If failed, return NULL 15045 */ 15046 static mptsas_target_t * 15047 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy) 15048 { 15049 int i, j = 0; 15050 int rval = 0; 15051 uint16_t cur_handle; 15052 uint32_t page_address; 15053 mptsas_target_t *ptgt = NULL; 15054 15055 /* 15056 * PHY named device must be direct attached and attaches to 15057 * narrow port, if the iport is not parent of the device which 15058 * we are looking for. 15059 */ 15060 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 15061 if ((1 << i) & phymask) 15062 j++; 15063 } 15064 15065 if (j > 1) 15066 return (NULL); 15067 15068 /* 15069 * Must be a narrow port and single device attached to the narrow port 15070 * So the physical port num of device which is equal to the iport's 15071 * port num is the device what we are looking for. 15072 */ 15073 15074 if (mpt->m_phy_info[phy].phy_mask != phymask) 15075 return (NULL); 15076 15077 mutex_enter(&mpt->m_mutex); 15078 15079 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn, 15080 &phy); 15081 if (ptgt != NULL) { 15082 mutex_exit(&mpt->m_mutex); 15083 return (ptgt); 15084 } 15085 15086 if (mpt->m_done_traverse_dev) { 15087 mutex_exit(&mpt->m_mutex); 15088 return (NULL); 15089 } 15090 15091 /* If didn't get a match, come here */ 15092 cur_handle = mpt->m_dev_handle; 15093 for (; ; ) { 15094 ptgt = NULL; 15095 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 15096 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle; 15097 rval = mptsas_get_target_device_info(mpt, page_address, 15098 &cur_handle, &ptgt); 15099 if ((rval == DEV_INFO_FAIL_PAGE0) || 15100 (rval == DEV_INFO_FAIL_ALLOC)) { 15101 break; 15102 } 15103 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 15104 (rval == DEV_INFO_PHYS_DISK)) { 15105 continue; 15106 } 15107 mpt->m_dev_handle = cur_handle; 15108 15109 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) { 15110 break; 15111 } 15112 } 15113 15114 mutex_exit(&mpt->m_mutex); 15115 return (ptgt); 15116 } 15117 15118 /* 15119 * The ptgt->m_addr.mta_wwn contains the wwid for each disk. 15120 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid 15121 * If we didn't get a match, we need to get sas page0 for each device, and 15122 * untill we get a match 15123 * If failed, return NULL 15124 */ 15125 static mptsas_target_t * 15126 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 15127 { 15128 int rval = 0; 15129 uint16_t cur_handle; 15130 uint32_t page_address; 15131 mptsas_target_t *tmp_tgt = NULL; 15132 mptsas_target_addr_t addr; 15133 15134 addr.mta_wwn = wwid; 15135 addr.mta_phymask = phymask; 15136 mutex_enter(&mpt->m_mutex); 15137 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 15138 if (tmp_tgt != NULL) { 15139 mutex_exit(&mpt->m_mutex); 15140 return (tmp_tgt); 15141 } 15142 15143 if (phymask == 0) { 15144 /* 15145 * It's IR volume 15146 */ 15147 rval = mptsas_get_raid_info(mpt); 15148 if (rval) { 15149 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 15150 } 15151 mutex_exit(&mpt->m_mutex); 15152 return (tmp_tgt); 15153 } 15154 15155 if (mpt->m_done_traverse_dev) { 15156 mutex_exit(&mpt->m_mutex); 15157 return (NULL); 15158 } 15159 15160 /* If didn't get a match, come here */ 15161 cur_handle = mpt->m_dev_handle; 15162 for (;;) { 15163 tmp_tgt = NULL; 15164 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 15165 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle; 15166 rval = mptsas_get_target_device_info(mpt, page_address, 15167 &cur_handle, &tmp_tgt); 15168 if ((rval == DEV_INFO_FAIL_PAGE0) || 15169 (rval == DEV_INFO_FAIL_ALLOC)) { 15170 tmp_tgt = NULL; 15171 break; 15172 } 15173 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 15174 (rval == DEV_INFO_PHYS_DISK)) { 15175 continue; 15176 } 15177 mpt->m_dev_handle = cur_handle; 15178 if ((tmp_tgt->m_addr.mta_wwn) && 15179 (tmp_tgt->m_addr.mta_wwn == wwid) && 15180 (tmp_tgt->m_addr.mta_phymask == phymask)) { 15181 break; 15182 } 15183 } 15184 15185 mutex_exit(&mpt->m_mutex); 15186 return (tmp_tgt); 15187 } 15188 15189 static mptsas_smp_t * 15190 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 15191 { 15192 int rval = 0; 15193 uint16_t cur_handle; 15194 uint32_t page_address; 15195 mptsas_smp_t smp_node, *psmp = NULL; 15196 mptsas_target_addr_t addr; 15197 15198 addr.mta_wwn = wwid; 15199 addr.mta_phymask = phymask; 15200 mutex_enter(&mpt->m_mutex); 15201 psmp = refhash_lookup(mpt->m_smp_targets, &addr); 15202 if (psmp != NULL) { 15203 mutex_exit(&mpt->m_mutex); 15204 return (psmp); 15205 } 15206 15207 if (mpt->m_done_traverse_smp) { 15208 mutex_exit(&mpt->m_mutex); 15209 return (NULL); 15210 } 15211 15212 /* If didn't get a match, come here */ 15213 cur_handle = mpt->m_smp_devhdl; 15214 for (;;) { 15215 psmp = NULL; 15216 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 15217 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle; 15218 rval = mptsas_get_sas_expander_page0(mpt, page_address, 15219 &smp_node); 15220 if (rval != DDI_SUCCESS) { 15221 break; 15222 } 15223 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl; 15224 psmp = mptsas_smp_alloc(mpt, &smp_node); 15225 ASSERT(psmp); 15226 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) && 15227 (psmp->m_addr.mta_phymask == phymask)) { 15228 break; 15229 } 15230 } 15231 15232 mutex_exit(&mpt->m_mutex); 15233 return (psmp); 15234 } 15235 15236 mptsas_target_t * 15237 mptsas_tgt_alloc(mptsas_t *mpt, uint16_t devhdl, uint64_t wwid, 15238 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum) 15239 { 15240 mptsas_target_t *tmp_tgt = NULL; 15241 mptsas_target_addr_t addr; 15242 15243 addr.mta_wwn = wwid; 15244 addr.mta_phymask = phymask; 15245 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 15246 if (tmp_tgt != NULL) { 15247 NDBG20(("Hash item already exist")); 15248 tmp_tgt->m_deviceinfo = devinfo; 15249 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */ 15250 return (tmp_tgt); 15251 } 15252 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP); 15253 if (tmp_tgt == NULL) { 15254 cmn_err(CE_WARN, "Fatal, allocated tgt failed"); 15255 return (NULL); 15256 } 15257 tmp_tgt->m_devhdl = devhdl; 15258 tmp_tgt->m_addr.mta_wwn = wwid; 15259 tmp_tgt->m_deviceinfo = devinfo; 15260 tmp_tgt->m_addr.mta_phymask = phymask; 15261 tmp_tgt->m_phynum = phynum; 15262 /* Initialized the tgt structure */ 15263 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 15264 tmp_tgt->m_qfull_retry_interval = 15265 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 15266 tmp_tgt->m_t_throttle = MAX_THROTTLE; 15267 15268 refhash_insert(mpt->m_targets, tmp_tgt); 15269 15270 return (tmp_tgt); 15271 } 15272 15273 static mptsas_smp_t * 15274 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data) 15275 { 15276 mptsas_target_addr_t addr; 15277 mptsas_smp_t *ret_data; 15278 15279 addr.mta_wwn = data->m_addr.mta_wwn; 15280 addr.mta_phymask = data->m_addr.mta_phymask; 15281 ret_data = refhash_lookup(mpt->m_smp_targets, &addr); 15282 if (ret_data != NULL) { 15283 bcopy(data, ret_data, sizeof (mptsas_smp_t)); /* XXX - dupl */ 15284 return (ret_data); 15285 } 15286 15287 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP); 15288 bcopy(data, ret_data, sizeof (mptsas_smp_t)); 15289 refhash_insert(mpt->m_smp_targets, ret_data); 15290 return (ret_data); 15291 } 15292 15293 /* 15294 * Functions for SGPIO LED support 15295 */ 15296 static dev_info_t * 15297 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask) 15298 { 15299 dev_info_t *dip; 15300 int prop; 15301 dip = e_ddi_hold_devi_by_dev(dev, 0); 15302 if (dip == NULL) 15303 return (dip); 15304 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 15305 "phymask", 0); 15306 *phymask = (mptsas_phymask_t)prop; 15307 ddi_release_devi(dip); 15308 return (dip); 15309 } 15310 static mptsas_target_t * 15311 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask) 15312 { 15313 uint8_t phynum; 15314 uint64_t wwn; 15315 int lun; 15316 mptsas_target_t *ptgt = NULL; 15317 15318 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) { 15319 return (NULL); 15320 } 15321 if (addr[0] == 'w') { 15322 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn); 15323 } else { 15324 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum); 15325 } 15326 return (ptgt); 15327 } 15328 15329 static int 15330 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt) 15331 { 15332 uint32_t slotstatus = 0; 15333 15334 /* Build an MPI2 Slot Status based on our view of the world */ 15335 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1))) 15336 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST; 15337 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1))) 15338 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT; 15339 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1))) 15340 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE; 15341 15342 /* Write it to the controller */ 15343 NDBG14(("mptsas_ioctl: set LED status %x for slot %x", 15344 slotstatus, ptgt->m_slot_num)); 15345 return (mptsas_send_sep(mpt, ptgt, &slotstatus, 15346 MPI2_SEP_REQ_ACTION_WRITE_STATUS)); 15347 } 15348 15349 /* 15350 * send sep request, use enclosure/slot addressing 15351 */ 15352 static int 15353 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt, 15354 uint32_t *status, uint8_t act) 15355 { 15356 Mpi2SepRequest_t req; 15357 Mpi2SepReply_t rep; 15358 int ret; 15359 15360 ASSERT(mutex_owned(&mpt->m_mutex)); 15361 15362 /* 15363 * We only support SEP control of directly-attached targets, in which 15364 * case the "SEP" we're talking to is a virtual one contained within 15365 * the HBA itself. This is necessary because DA targets typically have 15366 * no other mechanism for LED control. Targets for which a separate 15367 * enclosure service processor exists should be controlled via ses(7d) 15368 * or sgen(7d). Furthermore, since such requests can time out, they 15369 * should be made in user context rather than in response to 15370 * asynchronous fabric changes. 15371 * 15372 * In addition, we do not support this operation for RAID volumes, 15373 * since there is no slot associated with them. 15374 */ 15375 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) || 15376 ptgt->m_addr.mta_phymask == 0) { 15377 return (ENOTTY); 15378 } 15379 15380 bzero(&req, sizeof (req)); 15381 bzero(&rep, sizeof (rep)); 15382 15383 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR; 15384 req.Action = act; 15385 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS; 15386 req.EnclosureHandle = LE_16(ptgt->m_enclosure); 15387 req.Slot = LE_16(ptgt->m_slot_num); 15388 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 15389 req.SlotStatus = LE_32(*status); 15390 } 15391 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 15392 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 15393 if (ret != 0) { 15394 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP " 15395 "Processor Request message error %d", ret); 15396 return (ret); 15397 } 15398 /* do passthrough success, check the ioc status */ 15399 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 15400 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc " 15401 "status:%x loginfo %x", act, LE_16(rep.IOCStatus), 15402 LE_32(rep.IOCLogInfo)); 15403 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) { 15404 case MPI2_IOCSTATUS_INVALID_FUNCTION: 15405 case MPI2_IOCSTATUS_INVALID_VPID: 15406 case MPI2_IOCSTATUS_INVALID_FIELD: 15407 case MPI2_IOCSTATUS_INVALID_STATE: 15408 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 15409 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 15410 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 15411 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 15412 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 15413 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 15414 return (EINVAL); 15415 case MPI2_IOCSTATUS_BUSY: 15416 return (EBUSY); 15417 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 15418 return (EAGAIN); 15419 case MPI2_IOCSTATUS_INVALID_SGL: 15420 case MPI2_IOCSTATUS_INTERNAL_ERROR: 15421 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 15422 default: 15423 return (EIO); 15424 } 15425 } 15426 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 15427 *status = LE_32(rep.SlotStatus); 15428 } 15429 15430 return (0); 15431 } 15432 15433 int 15434 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 15435 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 15436 uint32_t alloc_size, ddi_dma_cookie_t *cookiep) 15437 { 15438 ddi_dma_cookie_t new_cookie; 15439 size_t alloc_len; 15440 uint_t ncookie; 15441 15442 if (cookiep == NULL) 15443 cookiep = &new_cookie; 15444 15445 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP, 15446 NULL, dma_hdp) != DDI_SUCCESS) { 15447 dma_hdp = NULL; 15448 return (FALSE); 15449 } 15450 15451 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr, 15452 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len, 15453 acc_hdp) != DDI_SUCCESS) { 15454 ddi_dma_free_handle(dma_hdp); 15455 dma_hdp = NULL; 15456 return (FALSE); 15457 } 15458 15459 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len, 15460 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL, 15461 cookiep, &ncookie) != DDI_DMA_MAPPED) { 15462 (void) ddi_dma_mem_free(acc_hdp); 15463 ddi_dma_free_handle(dma_hdp); 15464 dma_hdp = NULL; 15465 return (FALSE); 15466 } 15467 15468 return (TRUE); 15469 } 15470 15471 void 15472 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp) 15473 { 15474 if (*dma_hdp == NULL) 15475 return; 15476 15477 (void) ddi_dma_unbind_handle(*dma_hdp); 15478 (void) ddi_dma_mem_free(acc_hdp); 15479 ddi_dma_free_handle(dma_hdp); 15480 dma_hdp = NULL; 15481 }