1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2000-2012 LSI Corporation.
24 *
25 * Redistribution and use in source and binary forms of all code within
26 * this file that is exclusively owned by LSI, with or without
27 * modification, is permitted provided that, in addition to the CDDL 1.0
28 * License requirements, the following conditions are met:
29 *
30 * Neither the name of the author nor the names of its contributors may be
31 * used to endorse or promote products derived from this software without
32 * specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
37 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
38 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
40 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
41 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
42 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
44 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
45 * DAMAGE.
46 */
47
48 /*
49 * Name: mpi2_cnfg.h
50 * Title: MPI Configuration messages and pages
51 * Creation Date: November 10, 2006
52 *
53 * mpi2_cnfg.h Version: 02.00.xx
54 *
55 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
56 * prefix are for use only on MPI v2.5 products, and must not be used
57 * with MPI v2.0 products. Unless otherwise noted, names beginning with
58 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
59 *
60 * Version History
61 * ---------------
62 *
63 * Date Version Description
64 * -------- -------- ------------------------------------------------------
65 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
66 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
67 * Added Manufacturing Page 11.
68 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
69 * define.
70 * 06-26-07 02.00.02 Adding generic structure for product-specific
71 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
72 * Rework of BIOS Page 2 configuration page.
73 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
74 * forms.
75 * Added configuration pages IOC Page 8 and Driver
76 * Persistent Mapping Page 0.
77 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
78 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
79 * RAID Physical Disk Pages 0 and 1, RAID Configuration
80 * Page 0).
81 * Added new value for AccessStatus field of SAS Device
82 * Page 0 (_SATA_NEEDS_INITIALIZATION).
83 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
84 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
85 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
86 * NVDATA.
87 * Modified IOC Page 7 to use masks and added field for
88 * SASBroadcastPrimitiveMasks.
89 * Added MPI2_CONFIG_PAGE_BIOS_4.
90 * Added MPI2_CONFIG_PAGE_LOG_0.
91 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
92 * Added SAS Device IDs.
93 * Updated Integrated RAID configuration pages including
94 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
95 * Page 0.
96 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
97 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
98 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
99 * Added missing MaxNumRoutedSasAddresses field to
100 * MPI2_CONFIG_PAGE_EXPANDER_0.
101 * Added SAS Port Page 0.
102 * Modified structure layout for
103 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
104 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
105 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
106 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
107 * to 0x000000FF.
108 * Added two new values for the Physical Disk Coercion Size
109 * bits in the Flags field of Manufacturing Page 4.
110 * Added product-specific Manufacturing pages 16 to 31.
111 * Modified Flags bits for controlling write cache on SATA
112 * drives in IO Unit Page 1.
113 * Added new bit to AdditionalControlFlags of SAS IO Unit
114 * Page 1 to control Invalid Topology Correction.
115 * Added additional defines for RAID Volume Page 0
116 * VolumeStatusFlags field.
117 * Modified meaning of RAID Volume Page 0 VolumeSettings
118 * define for auto-configure of hot-swap drives.
119 * Added SupportedPhysDisks field to RAID Volume Page 1 and
120 * added related defines.
121 * Added PhysDiskAttributes field (and related defines) to
122 * RAID Physical Disk Page 0.
123 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
124 * Added three new DiscoveryStatus bits for SAS IO Unit
125 * Page 0 and SAS Expander Page 0.
126 * Removed multiplexing information from SAS IO Unit pages.
127 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
128 * Removed Zone Address Resolved bit from PhyInfo and from
129 * Expander Page 0 Flags field.
130 * Added two new AccessStatus values to SAS Device Page 0
131 * for indicating routing problems. Added 3 reserved words
132 * to this page.
133 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
134 * Inserted missing reserved field into structure for IOC
135 * Page 6.
136 * Added more pending task bits to RAID Volume Page 0
137 * VolumeStatusFlags defines.
138 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
139 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
140 * and SAS Expander Page 0 to flag a downstream initiator
141 * when in simplified routing mode.
142 * Removed SATA Init Failure defines for DiscoveryStatus
143 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
144 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
145 * Added PortGroups, DmaGroup, and ControlGroup fields to
146 * SAS Device Page 0.
147 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
148 * Unit Page 6.
149 * Added expander reduced functionality data to SAS
150 * Expander Page 0.
151 * Added SAS PHY Page 2 and SAS PHY Page 3.
152 * 07-30-09 02.00.12 Added IO Unit Page 7.
153 * Added new device ids.
154 * Added SAS IO Unit Page 5.
155 * Added partial and slumber power management capable flags
156 * to SAS Device Page 0 Flags field.
157 * Added PhyInfo defines for power condition.
158 * Added Ethernet configuration pages.
159 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
160 * Added SAS PHY Page 4 structure and defines.
161 * 02-10-10 02.00.14 Modified the comments for the configuration page
162 * structures that contain an array of data. The host
163 * should use the "count" field in the page data (e.g. the
164 * NumPhys field) to determine the number of valid elements
165 * in the array.
166 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
167 * Added PowerManagementCapabilities to IO Unit Page 7.
168 * Added PortWidthModGroup field to
169 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
170 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
171 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
172 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
173 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
174 * define.
175 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
176 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
177 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
178 * defines.
179 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
180 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
181 * the Pinout field.
182 * Added BoardTemperature and BoardTemperatureUnits fields
183 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
184 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
185 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
186 * --------------------------------------------------------------------------
187 */
188
189 #ifndef MPI2_CNFG_H
190 #define MPI2_CNFG_H
191
192 /*****************************************************************************
193 * Configuration Page Header and defines
194 *****************************************************************************/
195
196 /* Config Page Header */
197 typedef struct _MPI2_CONFIG_PAGE_HEADER
198 {
199 U8 PageVersion; /* 0x00 */
200 U8 PageLength; /* 0x01 */
201 U8 PageNumber; /* 0x02 */
202 U8 PageType; /* 0x03 */
203 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
204 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
205
206 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
207 {
208 MPI2_CONFIG_PAGE_HEADER Struct;
209 U8 Bytes[4];
210 U16 Word16[2];
211 U32 Word32;
212 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
213 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
214
215 /* Extended Config Page Header */
216 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
217 {
218 U8 PageVersion; /* 0x00 */
219 U8 Reserved1; /* 0x01 */
220 U8 PageNumber; /* 0x02 */
221 U8 PageType; /* 0x03 */
222 U16 ExtPageLength; /* 0x04 */
223 U8 ExtPageType; /* 0x06 */
224 U8 Reserved2; /* 0x07 */
225 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
226 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
227 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
228
229 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
230 {
231 MPI2_CONFIG_PAGE_HEADER Struct;
232 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
233 U8 Bytes[8];
234 U16 Word16[4];
235 U32 Word32[2];
236 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
237 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
238
239
240 /* PageType field values */
241 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
242 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
243 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
244 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
245
246 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
247 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
248 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
249 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
250 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
251 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
252 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
253 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
254
255 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
256
257
258 /* ExtPageType field values */
259 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
260 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
261 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
262 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
263 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
264 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
265 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
266 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
267 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
268 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
269 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
270
271
272 /*****************************************************************************
273 * PageAddress defines
274 *****************************************************************************/
275
276 /* RAID Volume PageAddress format */
277 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
278 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
279 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
280
281 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
282
283
284 /* RAID Physical Disk PageAddress format */
285 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
286 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
287 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
288 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
289
290 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
291 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
292
293
294 /* SAS Expander PageAddress format */
295 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
296 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
297 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
298 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
299
300 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
301 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
302 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
303
304
305 /* SAS Device PageAddress format */
306 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
307 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
308 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
309
310 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
311
312
313 /* SAS PHY PageAddress format */
314 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
315 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
316 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
317
318 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
319 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
320
321
322 /* SAS Port PageAddress format */
323 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
324 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
325 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
326
327 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
328
329
330 /* SAS Enclosure PageAddress format */
331 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
332 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
333 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
334
335 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
336
337
338 /* RAID Configuration PageAddress format */
339 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
340 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
341 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
342 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
343
344 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
345
346
347 /* Driver Persistent Mapping PageAddress format */
348 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
349 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
350
351 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
352 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
353 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
354
355
356 /* Ethernet PageAddress format */
357 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
358 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
359
360 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
361
362
363
364 /****************************************************************************
365 * Configuration messages
366 ****************************************************************************/
367
368 /* Configuration Request Message */
369 typedef struct _MPI2_CONFIG_REQUEST
370 {
371 U8 Action; /* 0x00 */
372 U8 SGLFlags; /* 0x01 */
373 U8 ChainOffset; /* 0x02 */
374 U8 Function; /* 0x03 */
375 U16 ExtPageLength; /* 0x04 */
376 U8 ExtPageType; /* 0x06 */
377 U8 MsgFlags; /* 0x07 */
378 U8 VP_ID; /* 0x08 */
379 U8 VF_ID; /* 0x09 */
380 U16 Reserved1; /* 0x0A */
381 U32 Reserved2; /* 0x0C */
382 U32 Reserved3; /* 0x10 */
383 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
384 U32 PageAddress; /* 0x18 */
385 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
386 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
387 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
388
389 /* values for the Action field */
390 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
391 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
392 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
393 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
394 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
395 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
396 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
397 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
398
399 /* values for SGLFlags field are in the SGL section of mpi2.h */
400
401
402 /* Config Reply Message */
403 typedef struct _MPI2_CONFIG_REPLY
404 {
405 U8 Action; /* 0x00 */
406 U8 SGLFlags; /* 0x01 */
407 U8 MsgLength; /* 0x02 */
408 U8 Function; /* 0x03 */
409 U16 ExtPageLength; /* 0x04 */
410 U8 ExtPageType; /* 0x06 */
411 U8 MsgFlags; /* 0x07 */
412 U8 VP_ID; /* 0x08 */
413 U8 VF_ID; /* 0x09 */
414 U16 Reserved1; /* 0x0A */
415 U16 Reserved2; /* 0x0C */
416 U16 IOCStatus; /* 0x0E */
417 U32 IOCLogInfo; /* 0x10 */
418 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
419 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
420 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
421
422
423
424 /*****************************************************************************
425 *
426 * C o n f i g u r a t i o n P a g e s
427 *
428 *****************************************************************************/
429
430 /****************************************************************************
431 * Manufacturing Config pages
432 ****************************************************************************/
433
434 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
435
436 /* MPI v2.0 SAS products */
437 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
438 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
439 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
440 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
441 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
442 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
443 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
444
445 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
446
447 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
448 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
449 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
450 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
451 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
452 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
453 #define MPI2_MFGPAGE_DEVID_SAS2208_7 (0x0086)
454 #define MPI2_MFGPAGE_DEVID_SAS2208_8 (0x0087)
455 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
456 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
457 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
458
459 /* MPI v2.5 SAS products */
460 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
461 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
462 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
463 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
464 #define MPI25_MFGPAGE_DEVID_SAS3108_3 (0x0092)
465 #define MPI25_MFGPAGE_DEVID_SAS3108_4 (0x0093)
466 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
467 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
468
469 /* Manufacturing Page 0 */
470
471 typedef struct _MPI2_CONFIG_PAGE_MAN_0
472 {
473 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
474 U8 ChipName[16]; /* 0x04 */
475 U8 ChipRevision[8]; /* 0x14 */
476 U8 BoardName[16]; /* 0x1C */
477 U8 BoardAssembly[16]; /* 0x2C */
478 U8 BoardTracerNumber[16]; /* 0x3C */
479 } MPI2_CONFIG_PAGE_MAN_0,
480 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
481 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
482
483 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
484
485
486 /* Manufacturing Page 1 */
487
488 typedef struct _MPI2_CONFIG_PAGE_MAN_1
489 {
490 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
491 U8 VPD[256]; /* 0x04 */
492 } MPI2_CONFIG_PAGE_MAN_1,
493 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
494 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
495
496 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
497
498
499 typedef struct _MPI2_CHIP_REVISION_ID
500 {
501 U16 DeviceID; /* 0x00 */
502 U8 PCIRevisionID; /* 0x02 */
503 U8 Reserved; /* 0x03 */
504 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
505 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
506
507
508 /* Manufacturing Page 2 */
509
510 /*
511 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
512 * one and check Header.PageLength at runtime.
513 */
514 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
515 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
516 #endif
517
518 typedef struct _MPI2_CONFIG_PAGE_MAN_2
519 {
520 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
521 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
522 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
523 } MPI2_CONFIG_PAGE_MAN_2,
524 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
525 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
526
527 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
528
529
530 /* Manufacturing Page 3 */
531
532 /*
533 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
534 * one and check Header.PageLength at runtime.
535 */
536 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
537 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
538 #endif
539
540 typedef struct _MPI2_CONFIG_PAGE_MAN_3
541 {
542 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
543 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
544 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
545 } MPI2_CONFIG_PAGE_MAN_3,
546 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
547 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
548
549 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
550
551
552 /* Manufacturing Page 4 */
553
554 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
555 {
556 U8 PowerSaveFlags; /* 0x00 */
557 U8 InternalOperationsSleepTime; /* 0x01 */
558 U8 InternalOperationsRunTime; /* 0x02 */
559 U8 HostIdleTime; /* 0x03 */
560 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
561 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
562 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
563
564 /* defines for the PowerSaveFlags field */
565 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
566 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
567 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
568 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
569
570 typedef struct _MPI2_CONFIG_PAGE_MAN_4
571 {
572 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
573 U32 Reserved1; /* 0x04 */
574 U32 Flags; /* 0x08 */
575 U8 InquirySize; /* 0x0C */
576 U8 Reserved2; /* 0x0D */
577 U16 Reserved3; /* 0x0E */
578 U8 InquiryData[56]; /* 0x10 */
579 U32 RAID0VolumeSettings; /* 0x48 */
580 U32 RAID1EVolumeSettings; /* 0x4C */
581 U32 RAID1VolumeSettings; /* 0x50 */
582 U32 RAID10VolumeSettings; /* 0x54 */
583 U32 Reserved4; /* 0x58 */
584 U32 Reserved5; /* 0x5C */
585 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
586 U8 MaxOCEDisks; /* 0x64 */
587 U8 ResyncRate; /* 0x65 */
588 U16 DataScrubDuration; /* 0x66 */
589 U8 MaxHotSpares; /* 0x68 */
590 U8 MaxPhysDisksPerVol; /* 0x69 */
591 U8 MaxPhysDisks; /* 0x6A */
592 U8 MaxVolumes; /* 0x6B */
593 } MPI2_CONFIG_PAGE_MAN_4,
594 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
595 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
596
597 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
598
599 /* Manufacturing Page 4 Flags field */
600 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
601 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
602
603 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
604 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
605 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
606
607 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
608 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
609 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
610 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
611 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
612
613 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
614 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
615 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
616 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
617
618 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
619 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
620 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
621 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
622 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
623 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
624 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
625 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
626
627
628 /* Manufacturing Page 5 */
629
630 /*
631 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
632 * one and check Header.PageLength or NumPhys at runtime.
633 */
634 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
635 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
636 #endif
637
638 typedef struct _MPI2_MANUFACTURING5_ENTRY
639 {
640 U64 WWID; /* 0x00 */
641 U64 DeviceName; /* 0x08 */
642 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
643 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
644
645 typedef struct _MPI2_CONFIG_PAGE_MAN_5
646 {
647 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
648 U8 NumPhys; /* 0x04 */
649 U8 Reserved1; /* 0x05 */
650 U16 Reserved2; /* 0x06 */
651 U32 Reserved3; /* 0x08 */
652 U32 Reserved4; /* 0x0C */
653 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
654 } MPI2_CONFIG_PAGE_MAN_5,
655 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
656 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
657
658 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
659
660
661 /* Manufacturing Page 6 */
662
663 typedef struct _MPI2_CONFIG_PAGE_MAN_6
664 {
665 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
666 U32 ProductSpecificInfo;/* 0x04 */
667 } MPI2_CONFIG_PAGE_MAN_6,
668 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
669 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
670
671 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
672
673
674 /* Manufacturing Page 7 */
675
676 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
677 {
678 U32 Pinout; /* 0x00 */
679 U8 Connector[16]; /* 0x04 */
680 U8 Location; /* 0x14 */
681 U8 ReceptacleID; /* 0x15 */
682 U16 Slot; /* 0x16 */
683 U32 Reserved2; /* 0x18 */
684 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
685 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
686
687 /* defines for the Pinout field */
688 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
689 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
690 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
691 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
692 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
693 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
694 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
695 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
696 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
697 #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
698
699 /* defines for the Location field */
700 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
701 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
702 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
703 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
704 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
705 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
706 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
707
708 /*
709 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
710 * one and check NumPhys at runtime.
711 */
712 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
713 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
714 #endif
715
716 typedef struct _MPI2_CONFIG_PAGE_MAN_7
717 {
718 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
719 U32 Reserved1; /* 0x04 */
720 U32 Reserved2; /* 0x08 */
721 U32 Flags; /* 0x0C */
722 U8 EnclosureName[16]; /* 0x10 */
723 U8 NumPhys; /* 0x20 */
724 U8 Reserved3; /* 0x21 */
725 U16 Reserved4; /* 0x22 */
726 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
727 } MPI2_CONFIG_PAGE_MAN_7,
728 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
729 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
730
731 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
732
733 /* defines for the Flags field */
734 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
735
736
737 /*
738 * Generic structure to use for product-specific manufacturing pages
739 * (currently Manufacturing Page 8 through Manufacturing Page 31).
740 */
741
742 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
743 {
744 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
745 U32 ProductSpecificInfo;/* 0x04 */
746 } MPI2_CONFIG_PAGE_MAN_PS,
747 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
748 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
749
750 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
751 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
752 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
753 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
754 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
755 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
756 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
757 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
758 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
759 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
760 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
761 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
762 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
763 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
764 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
765 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
766 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
767 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
768 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
769 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
770 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
771 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
772 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
773 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
774
775
776 /****************************************************************************
777 * IO Unit Config Pages
778 ****************************************************************************/
779
780 /* IO Unit Page 0 */
781
782 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
783 {
784 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
785 U64 UniqueValue; /* 0x04 */
786 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
787 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
788 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
789 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
790
791 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
792
793
794 /* IO Unit Page 1 */
795
796 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
797 {
798 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
799 U32 Flags; /* 0x04 */
800 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
801 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
802
803 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
804
805 /* IO Unit Page 1 Flags defines */
806 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
807 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
808 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
809 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
810 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
811 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
812 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
813 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
814 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
815 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
816 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
817 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
818 #define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
819 #define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
820
821
822 /* IO Unit Page 3 */
823
824 /*
825 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
826 * one and check Header.PageLength at runtime.
827 */
828 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
829 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
830 #endif
831
832 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
833 {
834 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
835 U8 GPIOCount; /* 0x04 */
836 U8 Reserved1; /* 0x05 */
837 U16 Reserved2; /* 0x06 */
838 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
839 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
840 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
841
842 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
843
844 /* defines for IO Unit Page 3 GPIOVal field */
845 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
846 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
847 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
848 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
849
850
851 /* IO Unit Page 5 */
852
853 /*
854 * Upper layer code (drivers, utilities, etc.) should leave this define set to
855 * one and check Header.PageLength or NumDmaEngines at runtime.
856 */
857 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
858 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
859 #endif
860
861 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5
862 {
863 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
864 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
865 U64 RaidAcceleratorBufferSize; /* 0x0C */
866 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
867 U8 RAControlSize; /* 0x1C */
868 U8 NumDmaEngines; /* 0x1D */
869 U8 RAMinControlSize; /* 0x1E */
870 U8 RAMaxControlSize; /* 0x1F */
871 U32 Reserved1; /* 0x20 */
872 U32 Reserved2; /* 0x24 */
873 U32 Reserved3; /* 0x28 */
874 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
875 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
876 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
877
878 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
879
880 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
881 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
882 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
883
884 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
885 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
886 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
887 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
888
889
890 /* IO Unit Page 6 */
891
892 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6
893 {
894 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
895 U16 Flags; /* 0x04 */
896 U8 RAHostControlSize; /* 0x06 */
897 U8 Reserved0; /* 0x07 */
898 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
899 U32 Reserved1; /* 0x10 */
900 U32 Reserved2; /* 0x14 */
901 U32 Reserved3; /* 0x18 */
902 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
903 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
904
905 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
906
907 /* defines for IO Unit Page 6 Flags field */
908 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
909
910
911 /* IO Unit Page 7 */
912
913 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
914 {
915 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
916 U16 Reserved1; /* 0x04 */
917 U8 PCIeWidth; /* 0x06 */
918 U8 PCIeSpeed; /* 0x07 */
919 U32 ProcessorState; /* 0x08 */
920 U32 PowerManagementCapabilities; /* 0x0C */
921 U16 IOCTemperature; /* 0x10 */
922 U8 IOCTemperatureUnits; /* 0x12 */
923 U8 IOCSpeed; /* 0x13 */
924 U16 BoardTemperature; /* 0x14 */
925 U8 BoardTemperatureUnits; /* 0x16 */
926 U8 Reserved3; /* 0x17 */
927 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
928 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
929
930 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
931
932 /* defines for IO Unit Page 7 PCIeWidth field */
933 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
934 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
935 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
936 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
937
938 /* defines for IO Unit Page 7 PCIeSpeed field */
939 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
940 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
941 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
942
943 /* defines for IO Unit Page 7 ProcessorState field */
944 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
945 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
946
947 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
948 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
949 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
950
951 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
952 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
953 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
954 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
955 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008)
956 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004)
957
958 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
959 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
960 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
961 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
962
963 /* defines for IO Unit Page 7 IOCSpeed field */
964 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
965 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
966 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
967 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
968
969 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
970 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
971 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
972 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
973
974
975 /****************************************************************************
976 * IOC Config Pages
977 ****************************************************************************/
978
979 /* IOC Page 0 */
980
981 typedef struct _MPI2_CONFIG_PAGE_IOC_0
982 {
983 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
984 U32 Reserved1; /* 0x04 */
985 U32 Reserved2; /* 0x08 */
986 U16 VendorID; /* 0x0C */
987 U16 DeviceID; /* 0x0E */
988 U8 RevisionID; /* 0x10 */
989 U8 Reserved3; /* 0x11 */
990 U16 Reserved4; /* 0x12 */
991 U32 ClassCode; /* 0x14 */
992 U16 SubsystemVendorID; /* 0x18 */
993 U16 SubsystemID; /* 0x1A */
994 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
995 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
996
997 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
998
999
1000 /* IOC Page 1 */
1001
1002 typedef struct _MPI2_CONFIG_PAGE_IOC_1
1003 {
1004 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1005 U32 Flags; /* 0x04 */
1006 U32 CoalescingTimeout; /* 0x08 */
1007 U8 CoalescingDepth; /* 0x0C */
1008 U8 PCISlotNum; /* 0x0D */
1009 U8 PCIBusNum; /* 0x0E */
1010 U8 PCIDomainSegment; /* 0x0F */
1011 U32 Reserved1; /* 0x10 */
1012 U32 Reserved2; /* 0x14 */
1013 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1014 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1015
1016 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1017
1018 /* defines for IOC Page 1 Flags field */
1019 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1020
1021 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1022 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1023 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1024
1025 /* IOC Page 6 */
1026
1027 typedef struct _MPI2_CONFIG_PAGE_IOC_6
1028 {
1029 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1030 U32 CapabilitiesFlags; /* 0x04 */
1031 U8 MaxDrivesRAID0; /* 0x08 */
1032 U8 MaxDrivesRAID1; /* 0x09 */
1033 U8 MaxDrivesRAID1E; /* 0x0A */
1034 U8 MaxDrivesRAID10; /* 0x0B */
1035 U8 MinDrivesRAID0; /* 0x0C */
1036 U8 MinDrivesRAID1; /* 0x0D */
1037 U8 MinDrivesRAID1E; /* 0x0E */
1038 U8 MinDrivesRAID10; /* 0x0F */
1039 U32 Reserved1; /* 0x10 */
1040 U8 MaxGlobalHotSpares; /* 0x14 */
1041 U8 MaxPhysDisks; /* 0x15 */
1042 U8 MaxVolumes; /* 0x16 */
1043 U8 MaxConfigs; /* 0x17 */
1044 U8 MaxOCEDisks; /* 0x18 */
1045 U8 Reserved2; /* 0x19 */
1046 U16 Reserved3; /* 0x1A */
1047 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1048 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1049 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1050 U32 Reserved4; /* 0x28 */
1051 U32 Reserved5; /* 0x2C */
1052 U16 DefaultMetadataSize; /* 0x30 */
1053 U16 Reserved6; /* 0x32 */
1054 U16 MaxBadBlockTableEntries; /* 0x34 */
1055 U16 Reserved7; /* 0x36 */
1056 U32 IRNvsramVersion; /* 0x38 */
1057 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1058 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1059
1060 #define MPI2_IOCPAGE6_PAGEVERSION (0x04)
1061
1062 /* defines for IOC Page 6 CapabilitiesFlags */
1063 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1064 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1065 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1066 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1067 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1068
1069
1070 /* IOC Page 7 */
1071
1072 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1073
1074 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1075 {
1076 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1077 U32 Reserved1; /* 0x04 */
1078 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1079 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1080 U16 Reserved2; /* 0x1A */
1081 U32 Reserved3; /* 0x1C */
1082 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1083 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1084
1085 #define MPI2_IOCPAGE7_PAGEVERSION (0x01)
1086
1087
1088 /* IOC Page 8 */
1089
1090 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1091 {
1092 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1093 U8 NumDevsPerEnclosure; /* 0x04 */
1094 U8 Reserved1; /* 0x05 */
1095 U16 Reserved2; /* 0x06 */
1096 U16 MaxPersistentEntries; /* 0x08 */
1097 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1098 U16 Flags; /* 0x0C */
1099 U16 Reserved3; /* 0x0E */
1100 U16 IRVolumeMappingFlags; /* 0x10 */
1101 U16 Reserved4; /* 0x12 */
1102 U32 Reserved5; /* 0x14 */
1103 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1104 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1105
1106 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1107
1108 /* defines for IOC Page 8 Flags field */
1109 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1110 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1111
1112 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1113 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1114 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1115
1116 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1117 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1118
1119 /* defines for IOC Page 8 IRVolumeMappingFlags */
1120 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1121 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1122 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1123
1124
1125 /****************************************************************************
1126 * BIOS Config Pages
1127 ****************************************************************************/
1128
1129 /* BIOS Page 1 */
1130
1131 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1132 {
1133 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1134 U32 BiosOptions; /* 0x04 */
1135 U32 IOCSettings; /* 0x08 */
1136 U32 Reserved1; /* 0x0C */
1137 U32 DeviceSettings; /* 0x10 */
1138 U16 NumberOfDevices; /* 0x14 */
1139 U16 Reserved2; /* 0x16 */
1140 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1141 U16 IOTimeoutSequential; /* 0x1A */
1142 U16 IOTimeoutOther; /* 0x1C */
1143 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1144 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1145 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1146
1147 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
1148
1149 /* values for BIOS Page 1 BiosOptions field */
1150 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1151
1152 /* values for BIOS Page 1 IOCSettings field */
1153 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1154 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1155 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1156
1157 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1158 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1159 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1160 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1161
1162 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1163 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1164 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1165 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1166 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1167
1168 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1169
1170 /* values for BIOS Page 1 DeviceSettings field */
1171 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1172 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1173 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1174 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1175 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1176
1177
1178 /* BIOS Page 2 */
1179
1180 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1181 {
1182 U32 Reserved1; /* 0x00 */
1183 U32 Reserved2; /* 0x04 */
1184 U32 Reserved3; /* 0x08 */
1185 U32 Reserved4; /* 0x0C */
1186 U32 Reserved5; /* 0x10 */
1187 U32 Reserved6; /* 0x14 */
1188 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1189 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1190 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1191
1192 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1193 {
1194 U64 SASAddress; /* 0x00 */
1195 U8 LUN[8]; /* 0x08 */
1196 U32 Reserved1; /* 0x10 */
1197 U32 Reserved2; /* 0x14 */
1198 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1199 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1200
1201 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1202 {
1203 U64 EnclosureLogicalID; /* 0x00 */
1204 U32 Reserved1; /* 0x08 */
1205 U32 Reserved2; /* 0x0C */
1206 U16 SlotNumber; /* 0x10 */
1207 U16 Reserved3; /* 0x12 */
1208 U32 Reserved4; /* 0x14 */
1209 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1210 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1211 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1212
1213 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1214 {
1215 U64 DeviceName; /* 0x00 */
1216 U8 LUN[8]; /* 0x08 */
1217 U32 Reserved1; /* 0x10 */
1218 U32 Reserved2; /* 0x14 */
1219 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1220 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1221
1222 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1223 {
1224 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1225 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1226 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1227 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1228 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1229 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1230
1231 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1232 {
1233 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1234 U32 Reserved1; /* 0x04 */
1235 U32 Reserved2; /* 0x08 */
1236 U32 Reserved3; /* 0x0C */
1237 U32 Reserved4; /* 0x10 */
1238 U32 Reserved5; /* 0x14 */
1239 U32 Reserved6; /* 0x18 */
1240 U8 ReqBootDeviceForm; /* 0x1C */
1241 U8 Reserved7; /* 0x1D */
1242 U16 Reserved8; /* 0x1E */
1243 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1244 U8 ReqAltBootDeviceForm; /* 0x38 */
1245 U8 Reserved9; /* 0x39 */
1246 U16 Reserved10; /* 0x3A */
1247 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1248 U8 CurrentBootDeviceForm; /* 0x58 */
1249 U8 Reserved11; /* 0x59 */
1250 U16 Reserved12; /* 0x5A */
1251 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1252 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1253 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1254
1255 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1256
1257 /* values for BIOS Page 2 BootDeviceForm fields */
1258 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1259 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1260 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1261 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1262 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1263
1264
1265 /* BIOS Page 3 */
1266
1267 typedef struct _MPI2_ADAPTER_INFO
1268 {
1269 U8 PciBusNumber; /* 0x00 */
1270 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1271 U16 AdapterFlags; /* 0x02 */
1272 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1273 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1274
1275 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1276 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1277
1278 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1279 {
1280 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1281 U32 GlobalFlags; /* 0x04 */
1282 U32 BiosVersion; /* 0x08 */
1283 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1284 U32 Reserved1; /* 0x1C */
1285 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1286 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1287
1288 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1289
1290 /* values for BIOS Page 3 GlobalFlags */
1291 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1292 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1293 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1294
1295 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1296 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1297 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1298 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1299
1300
1301 /* BIOS Page 4 */
1302
1303 /*
1304 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1305 * one and check Header.PageLength or NumPhys at runtime.
1306 */
1307 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1308 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1309 #endif
1310
1311 typedef struct _MPI2_BIOS4_ENTRY
1312 {
1313 U64 ReassignmentWWID; /* 0x00 */
1314 U64 ReassignmentDeviceName; /* 0x08 */
1315 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1316 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1317
1318 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1319 {
1320 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1321 U8 NumPhys; /* 0x04 */
1322 U8 Reserved1; /* 0x05 */
1323 U16 Reserved2; /* 0x06 */
1324 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1325 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1326 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1327
1328 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1329
1330
1331 /****************************************************************************
1332 * RAID Volume Config Pages
1333 ****************************************************************************/
1334
1335 /* RAID Volume Page 0 */
1336
1337 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1338 {
1339 U8 RAIDSetNum; /* 0x00 */
1340 U8 PhysDiskMap; /* 0x01 */
1341 U8 PhysDiskNum; /* 0x02 */
1342 U8 Reserved; /* 0x03 */
1343 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1344 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1345
1346 /* defines for the PhysDiskMap field */
1347 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1348 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1349
1350 typedef struct _MPI2_RAIDVOL0_SETTINGS
1351 {
1352 U16 Settings; /* 0x00 */
1353 U8 HotSparePool; /* 0x01 */
1354 U8 Reserved; /* 0x02 */
1355 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1356 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1357
1358 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1359 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1360 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1361 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1362 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1363 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1364 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1365 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1366 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1367
1368 /* RAID Volume Page 0 VolumeSettings defines */
1369 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1370 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1371
1372 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1373 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1374 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1375 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1376
1377 /*
1378 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1379 * one and check Header.PageLength at runtime.
1380 */
1381 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1382 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1383 #endif
1384
1385 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1386 {
1387 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1388 U16 DevHandle; /* 0x04 */
1389 U8 VolumeState; /* 0x06 */
1390 U8 VolumeType; /* 0x07 */
1391 U32 VolumeStatusFlags; /* 0x08 */
1392 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1393 U64 MaxLBA; /* 0x10 */
1394 U32 StripeSize; /* 0x18 */
1395 U16 BlockSize; /* 0x1C */
1396 U16 Reserved1; /* 0x1E */
1397 U8 SupportedPhysDisks; /* 0x20 */
1398 U8 ResyncRate; /* 0x21 */
1399 U16 DataScrubDuration; /* 0x22 */
1400 U8 NumPhysDisks; /* 0x24 */
1401 U8 Reserved2; /* 0x25 */
1402 U8 Reserved3; /* 0x26 */
1403 U8 InactiveStatus; /* 0x27 */
1404 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1405 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1406 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1407
1408 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1409
1410 /* values for RAID VolumeState */
1411 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1412 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1413 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1414 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1415 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1416 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1417
1418 /* values for RAID VolumeType */
1419 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1420 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1421 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1422 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1423 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1424
1425 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1426 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1427 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1428 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1429 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1430 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1431 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1432 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1433 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1434 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1435 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1436 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1437 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1438 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1439 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1440 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1441 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1442 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1443 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1444 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1445
1446 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1447 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1448 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1449 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1450 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1451
1452 /* values for RAID Volume Page 0 InactiveStatus field */
1453 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1454 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1455 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1456 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1457 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1458 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1459 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1460
1461
1462 /* RAID Volume Page 1 */
1463
1464 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1465 {
1466 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1467 U16 DevHandle; /* 0x04 */
1468 U16 Reserved0; /* 0x06 */
1469 U8 GUID[24]; /* 0x08 */
1470 U8 Name[16]; /* 0x20 */
1471 U64 WWID; /* 0x30 */
1472 U32 Reserved1; /* 0x38 */
1473 U32 Reserved2; /* 0x3C */
1474 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1475 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1476
1477 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1478
1479
1480 /****************************************************************************
1481 * RAID Physical Disk Config Pages
1482 ****************************************************************************/
1483
1484 /* RAID Physical Disk Page 0 */
1485
1486 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1487 {
1488 U16 Reserved1; /* 0x00 */
1489 U8 HotSparePool; /* 0x02 */
1490 U8 Reserved2; /* 0x03 */
1491 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1492 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1493
1494 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1495
1496 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1497 {
1498 U8 VendorID[8]; /* 0x00 */
1499 U8 ProductID[16]; /* 0x08 */
1500 U8 ProductRevLevel[4]; /* 0x18 */
1501 U8 SerialNum[32]; /* 0x1C */
1502 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1503 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1504 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1505
1506 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1507 {
1508 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1509 U16 DevHandle; /* 0x04 */
1510 U8 Reserved1; /* 0x06 */
1511 U8 PhysDiskNum; /* 0x07 */
1512 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1513 U32 Reserved2; /* 0x0C */
1514 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1515 U32 Reserved3; /* 0x4C */
1516 U8 PhysDiskState; /* 0x50 */
1517 U8 OfflineReason; /* 0x51 */
1518 U8 IncompatibleReason; /* 0x52 */
1519 U8 PhysDiskAttributes; /* 0x53 */
1520 U32 PhysDiskStatusFlags; /* 0x54 */
1521 U64 DeviceMaxLBA; /* 0x58 */
1522 U64 HostMaxLBA; /* 0x60 */
1523 U64 CoercedMaxLBA; /* 0x68 */
1524 U16 BlockSize; /* 0x70 */
1525 U16 Reserved5; /* 0x72 */
1526 U32 Reserved6; /* 0x74 */
1527 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1528 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1529 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1530
1531 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1532
1533 /* PhysDiskState defines */
1534 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1535 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1536 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1537 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1538 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1539 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1540 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1541 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1542
1543 /* OfflineReason defines */
1544 #define MPI2_PHYSDISK0_ONLINE (0x00)
1545 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1546 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1547 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1548 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1549 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1550 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1551
1552 /* IncompatibleReason defines */
1553 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1554 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1555 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1556 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1557 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1558 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1559 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1560 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1561
1562 /* PhysDiskAttributes defines */
1563 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1564 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1565
1566 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1567 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1568 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1569
1570 /* PhysDiskStatusFlags defines */
1571 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1572 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1573 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1574 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1575 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1576 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1577 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1578 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1579
1580
1581 /* RAID Physical Disk Page 1 */
1582
1583 /*
1584 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1585 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1586 */
1587 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1588 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1589 #endif
1590
1591 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1592 {
1593 U16 DevHandle; /* 0x00 */
1594 U16 Reserved1; /* 0x02 */
1595 U64 WWID; /* 0x04 */
1596 U64 OwnerWWID; /* 0x0C */
1597 U8 OwnerIdentifier; /* 0x14 */
1598 U8 Reserved2; /* 0x15 */
1599 U16 Flags; /* 0x16 */
1600 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1601 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1602
1603 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1604 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1605 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1606 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1607
1608 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1609 {
1610 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1611 U8 NumPhysDiskPaths; /* 0x04 */
1612 U8 PhysDiskNum; /* 0x05 */
1613 U16 Reserved1; /* 0x06 */
1614 U32 Reserved2; /* 0x08 */
1615 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1616 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1617 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1618 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1619
1620 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1621
1622
1623 /****************************************************************************
1624 * values for fields used by several types of SAS Config Pages
1625 ****************************************************************************/
1626
1627 /* values for NegotiatedLinkRates fields */
1628 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1629 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1630 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1631 /* link rates used for Negotiated Physical and Logical Link Rate */
1632 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1633 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1634 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1635 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1636 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1637 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1638 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1639 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1640 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1641 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1642 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
1643
1644
1645 /* values for AttachedPhyInfo fields */
1646 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1647 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1648 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1649
1650 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1651 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1652 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1653 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1654 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1655 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1656 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1657 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1658 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1659 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1660
1661
1662 /* values for PhyInfo fields */
1663 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1664
1665 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1666 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1667 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1668 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1669 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1670
1671 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1672 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1673 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1674 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1675 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1676 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1677
1678 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1679 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1680 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1681 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1682 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1683 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1684 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1685 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1686 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1687 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1688
1689 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1690 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1691 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1692 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1693
1694 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1695 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1696
1697 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1698 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1699 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1700 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1701
1702
1703 /* values for SAS ProgrammedLinkRate fields */
1704 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1705 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1706 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1707 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1708 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1709 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1710 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1711 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1712 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1713 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1714 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
1715
1716
1717 /* values for SAS HwLinkRate fields */
1718 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1719 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1720 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1721 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1722 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1723 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1724 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1725 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1726 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
1727
1728
1729
1730 /****************************************************************************
1731 * SAS IO Unit Config Pages
1732 ****************************************************************************/
1733
1734 /* SAS IO Unit Page 0 */
1735
1736 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1737 {
1738 U8 Port; /* 0x00 */
1739 U8 PortFlags; /* 0x01 */
1740 U8 PhyFlags; /* 0x02 */
1741 U8 NegotiatedLinkRate; /* 0x03 */
1742 U32 ControllerPhyDeviceInfo;/* 0x04 */
1743 U16 AttachedDevHandle; /* 0x08 */
1744 U16 ControllerDevHandle; /* 0x0A */
1745 U32 DiscoveryStatus; /* 0x0C */
1746 U32 Reserved; /* 0x10 */
1747 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1748 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1749
1750 /*
1751 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1752 * one and check Header.ExtPageLength or NumPhys at runtime.
1753 */
1754 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1755 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1756 #endif
1757
1758 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1759 {
1760 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1761 U32 Reserved1; /* 0x08 */
1762 U8 NumPhys; /* 0x0C */
1763 U8 Reserved2; /* 0x0D */
1764 U16 Reserved3; /* 0x0E */
1765 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1766 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1767 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1768 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1769
1770 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1771
1772 /* values for SAS IO Unit Page 0 PortFlags */
1773 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1774 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1775
1776 /* values for SAS IO Unit Page 0 PhyFlags */
1777 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1778 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1779
1780 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1781
1782 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1783
1784 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1785 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1786 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1787 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1788 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1789 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1790 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1791 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1792 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1793 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1794 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1795 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1796 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1797 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1798 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1799 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1800 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1801 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1802 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1803 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1804 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1805
1806
1807 /* SAS IO Unit Page 1 */
1808
1809 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1810 {
1811 U8 Port; /* 0x00 */
1812 U8 PortFlags; /* 0x01 */
1813 U8 PhyFlags; /* 0x02 */
1814 U8 MaxMinLinkRate; /* 0x03 */
1815 U32 ControllerPhyDeviceInfo; /* 0x04 */
1816 U16 MaxTargetPortConnectTime; /* 0x08 */
1817 U16 Reserved1; /* 0x0A */
1818 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1819 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1820
1821 /*
1822 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1823 * one and check Header.ExtPageLength or NumPhys at runtime.
1824 */
1825 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1826 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1827 #endif
1828
1829 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1830 {
1831 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1832 U16 ControlFlags; /* 0x08 */
1833 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1834 U16 AdditionalControlFlags; /* 0x0C */
1835 U16 SASWideMaxQueueDepth; /* 0x0E */
1836 U8 NumPhys; /* 0x10 */
1837 U8 SATAMaxQDepth; /* 0x11 */
1838 U8 ReportDeviceMissingDelay; /* 0x12 */
1839 U8 IODeviceMissingDelay; /* 0x13 */
1840 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1841 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1842 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1843 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1844
1845 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1846
1847 /* values for SAS IO Unit Page 1 ControlFlags */
1848 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1849 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1850 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1851 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1852
1853 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1854 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1855 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1856 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1857 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1858
1859 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1860 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1861 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1862 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1863 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1864 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1865 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1866 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1867
1868 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1869 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1870 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1871 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1872 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1873 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1874 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1875 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1876 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1877
1878 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1879 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1880 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1881
1882 /* values for SAS IO Unit Page 1 PortFlags */
1883 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1884
1885 /* values for SAS IO Unit Page 1 PhyFlags */
1886 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1887 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1888
1889 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1890 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1891 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1892 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1893 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1894 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
1895 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1896 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1897 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1898 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1899 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
1900
1901 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1902
1903
1904 /* SAS IO Unit Page 4 */
1905
1906 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1907 {
1908 U8 MaxTargetSpinup; /* 0x00 */
1909 U8 SpinupDelay; /* 0x01 */
1910 U16 Reserved1; /* 0x02 */
1911 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1912 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1913
1914 /*
1915 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1916 * four and check Header.ExtPageLength or NumPhys at runtime.
1917 */
1918 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1919 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1920 #endif
1921
1922 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1923 {
1924 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1925 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1926 U32 Reserved1; /* 0x18 */
1927 U32 Reserved2; /* 0x1C */
1928 U32 Reserved3; /* 0x20 */
1929 U8 BootDeviceWaitTime; /* 0x24 */
1930 U8 Reserved4; /* 0x25 */
1931 U16 Reserved5; /* 0x26 */
1932 U8 NumPhys; /* 0x28 */
1933 U8 PEInitialSpinupDelay; /* 0x29 */
1934 U8 PEReplyDelay; /* 0x2A */
1935 U8 Flags; /* 0x2B */
1936 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1937 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1938 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1939 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1940
1941 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1942
1943 /* defines for Flags field */
1944 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1945
1946 /* defines for PHY field */
1947 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1948
1949
1950 /* SAS IO Unit Page 5 */
1951
1952 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
1953 {
1954 U8 ControlFlags; /* 0x00 */
1955 U8 PortWidthModGroup; /* 0x01 */
1956 U16 InactivityTimerExponent; /* 0x02 */
1957 U8 SATAPartialTimeout; /* 0x04 */
1958 U8 Reserved2; /* 0x05 */
1959 U8 SATASlumberTimeout; /* 0x06 */
1960 U8 Reserved3; /* 0x07 */
1961 U8 SASPartialTimeout; /* 0x08 */
1962 U8 Reserved4; /* 0x09 */
1963 U8 SASSlumberTimeout; /* 0x0A */
1964 U8 Reserved5; /* 0x0B */
1965 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1966 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1967 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1968
1969 /* defines for ControlFlags field */
1970 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1971 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1972 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1973 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1974
1975 /* defines for PortWidthModeGroup field */
1976 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
1977
1978 /* defines for InactivityTimerExponent field */
1979 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
1980 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
1981 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
1982 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
1983 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
1984 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
1985 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
1986 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
1987
1988 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
1989 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
1990 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
1991 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
1992 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
1993 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
1994 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
1995 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
1996
1997 /*
1998 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1999 * one and check Header.ExtPageLength or NumPhys at runtime.
2000 */
2001 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2002 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2003 #endif
2004
2005 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
2006 {
2007 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2008 U8 NumPhys; /* 0x08 */
2009 U8 Reserved1; /* 0x09 */
2010 U16 Reserved2; /* 0x0A */
2011 U32 Reserved3; /* 0x0C */
2012 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2013 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2014 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2015 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2016
2017 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2018
2019
2020 /* SAS IO Unit Page 6 */
2021
2022 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2023 {
2024 U8 CurrentStatus; /* 0x00 */
2025 U8 CurrentModulation; /* 0x01 */
2026 U8 CurrentUtilization; /* 0x02 */
2027 U8 Reserved1; /* 0x03 */
2028 U32 Reserved2; /* 0x04 */
2029 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2030 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2031 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2032 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2033
2034 /* defines for CurrentStatus field */
2035 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2036 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2037 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2038 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2039 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2040 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2041 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2042 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2043
2044 /* defines for CurrentModulation field */
2045 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2046 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2047 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2048 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2049
2050 /*
2051 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2052 * one and check the value returned for NumGroups at runtime.
2053 */
2054 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2055 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2056 #endif
2057
2058 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6
2059 {
2060 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2061 U32 Reserved1; /* 0x08 */
2062 U32 Reserved2; /* 0x0C */
2063 U8 NumGroups; /* 0x10 */
2064 U8 Reserved3; /* 0x11 */
2065 U16 Reserved4; /* 0x12 */
2066 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2067 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2068 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2069 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2070 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2071
2072 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2073
2074
2075 /* SAS IO Unit Page 7 */
2076
2077 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2078 {
2079 U8 Flags; /* 0x00 */
2080 U8 Reserved1; /* 0x01 */
2081 U16 Reserved2; /* 0x02 */
2082 U8 Threshold75Pct; /* 0x04 */
2083 U8 Threshold50Pct; /* 0x05 */
2084 U8 Threshold25Pct; /* 0x06 */
2085 U8 Reserved3; /* 0x07 */
2086 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2087 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2088 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2089 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2090
2091 /* defines for Flags field */
2092 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2093
2094
2095 /*
2096 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2097 * one and check the value returned for NumGroups at runtime.
2098 */
2099 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2100 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2101 #endif
2102
2103 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7
2104 {
2105 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2106 U8 SamplingInterval; /* 0x08 */
2107 U8 WindowLength; /* 0x09 */
2108 U16 Reserved1; /* 0x0A */
2109 U32 Reserved2; /* 0x0C */
2110 U32 Reserved3; /* 0x10 */
2111 U8 NumGroups; /* 0x14 */
2112 U8 Reserved4; /* 0x15 */
2113 U16 Reserved5; /* 0x16 */
2114 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2115 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2116 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2117 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2118 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2119
2120 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2121
2122
2123 /* SAS IO Unit Page 8 */
2124
2125 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8
2126 {
2127 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2128 U32 Reserved1; /* 0x08 */
2129 U32 PowerManagementCapabilities; /* 0x0C */
2130 U32 Reserved2; /* 0x10 */
2131 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2132 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2133 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2134
2135 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2136
2137 /* defines for PowerManagementCapabilities field */
2138 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000)
2139 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800)
2140 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400)
2141 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200)
2142 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100)
2143 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010)
2144 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008)
2145 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004)
2146 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002)
2147 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001)
2148
2149
2150
2151
2152 /****************************************************************************
2153 * SAS Expander Config Pages
2154 ****************************************************************************/
2155
2156 /* SAS Expander Page 0 */
2157
2158 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2159 {
2160 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2161 U8 PhysicalPort; /* 0x08 */
2162 U8 ReportGenLength; /* 0x09 */
2163 U16 EnclosureHandle; /* 0x0A */
2164 U64 SASAddress; /* 0x0C */
2165 U32 DiscoveryStatus; /* 0x14 */
2166 U16 DevHandle; /* 0x18 */
2167 U16 ParentDevHandle; /* 0x1A */
2168 U16 ExpanderChangeCount; /* 0x1C */
2169 U16 ExpanderRouteIndexes; /* 0x1E */
2170 U8 NumPhys; /* 0x20 */
2171 U8 SASLevel; /* 0x21 */
2172 U16 Flags; /* 0x22 */
2173 U16 STPBusInactivityTimeLimit; /* 0x24 */
2174 U16 STPMaxConnectTimeLimit; /* 0x26 */
2175 U16 STP_SMP_NexusLossTime; /* 0x28 */
2176 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2177 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2178 U16 ZoneLockInactivityLimit; /* 0x34 */
2179 U16 Reserved1; /* 0x36 */
2180 U8 TimeToReducedFunc; /* 0x38 */
2181 U8 InitialTimeToReducedFunc; /* 0x39 */
2182 U8 MaxReducedFuncTime; /* 0x3A */
2183 U8 Reserved2; /* 0x3B */
2184 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2185 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2186
2187 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2188
2189 /* values for SAS Expander Page 0 DiscoveryStatus field */
2190 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2191 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2192 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2193 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2194 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2195 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2196 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2197 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2198 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2199 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2200 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2201 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2202 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2203 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2204 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2205 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2206 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2207 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2208 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2209 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2210
2211 /* values for SAS Expander Page 0 Flags field */
2212 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2213 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2214 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2215 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2216 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2217 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2218 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2219 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2220 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2221 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2222 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2223
2224
2225 /* SAS Expander Page 1 */
2226
2227 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2228 {
2229 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2230 U8 PhysicalPort; /* 0x08 */
2231 U8 Reserved1; /* 0x09 */
2232 U16 Reserved2; /* 0x0A */
2233 U8 NumPhys; /* 0x0C */
2234 U8 Phy; /* 0x0D */
2235 U16 NumTableEntriesProgrammed; /* 0x0E */
2236 U8 ProgrammedLinkRate; /* 0x10 */
2237 U8 HwLinkRate; /* 0x11 */
2238 U16 AttachedDevHandle; /* 0x12 */
2239 U32 PhyInfo; /* 0x14 */
2240 U32 AttachedDeviceInfo; /* 0x18 */
2241 U16 ExpanderDevHandle; /* 0x1C */
2242 U8 ChangeCount; /* 0x1E */
2243 U8 NegotiatedLinkRate; /* 0x1F */
2244 U8 PhyIdentifier; /* 0x20 */
2245 U8 AttachedPhyIdentifier; /* 0x21 */
2246 U8 Reserved3; /* 0x22 */
2247 U8 DiscoveryInfo; /* 0x23 */
2248 U32 AttachedPhyInfo; /* 0x24 */
2249 U8 ZoneGroup; /* 0x28 */
2250 U8 SelfConfigStatus; /* 0x29 */
2251 U16 Reserved4; /* 0x2A */
2252 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2253 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2254
2255 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2256
2257 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2258
2259 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2260
2261 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2262
2263 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2264
2265 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2266
2267 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2268
2269 /* values for SAS Expander Page 1 DiscoveryInfo field */
2270 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2271 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2272 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2273
2274
2275 /****************************************************************************
2276 * SAS Device Config Pages
2277 ****************************************************************************/
2278
2279 /* SAS Device Page 0 */
2280
2281 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2282 {
2283 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2284 U16 Slot; /* 0x08 */
2285 U16 EnclosureHandle; /* 0x0A */
2286 U64 SASAddress; /* 0x0C */
2287 U16 ParentDevHandle; /* 0x14 */
2288 U8 PhyNum; /* 0x16 */
2289 U8 AccessStatus; /* 0x17 */
2290 U16 DevHandle; /* 0x18 */
2291 U8 AttachedPhyIdentifier; /* 0x1A */
2292 U8 ZoneGroup; /* 0x1B */
2293 U32 DeviceInfo; /* 0x1C */
2294 U16 Flags; /* 0x20 */
2295 U8 PhysicalPort; /* 0x22 */
2296 U8 MaxPortConnections; /* 0x23 */
2297 U64 DeviceName; /* 0x24 */
2298 U8 PortGroups; /* 0x2C */
2299 U8 DmaGroup; /* 0x2D */
2300 U8 ControlGroup; /* 0x2E */
2301 U8 Reserved1; /* 0x2F */
2302 U32 Reserved2; /* 0x30 */
2303 U32 Reserved3; /* 0x34 */
2304 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2305 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2306
2307 #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2308
2309 /* values for SAS Device Page 0 AccessStatus field */
2310 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2311 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2312 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2313 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2314 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2315 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2316 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2317 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2318 /* specific values for SATA Init failures */
2319 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2320 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2321 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2322 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2323 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2324 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2325 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2326 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2327 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2328 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2329 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2330
2331 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2332
2333 /* values for SAS Device Page 0 Flags field */
2334 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2335 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2336 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2337 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2338 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2339 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2340 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2341 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2342 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2343 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2344 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2345 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2346 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2347
2348
2349 /* SAS Device Page 1 */
2350
2351 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2352 {
2353 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2354 U32 Reserved1; /* 0x08 */
2355 U64 SASAddress; /* 0x0C */
2356 U32 Reserved2; /* 0x14 */
2357 U16 DevHandle; /* 0x18 */
2358 U16 Reserved3; /* 0x1A */
2359 U8 InitialRegDeviceFIS[20];/* 0x1C */
2360 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2361 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2362
2363 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2364
2365
2366 /****************************************************************************
2367 * SAS PHY Config Pages
2368 ****************************************************************************/
2369
2370 /* SAS PHY Page 0 */
2371
2372 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2373 {
2374 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2375 U16 OwnerDevHandle; /* 0x08 */
2376 U16 Reserved1; /* 0x0A */
2377 U16 AttachedDevHandle; /* 0x0C */
2378 U8 AttachedPhyIdentifier; /* 0x0E */
2379 U8 Reserved2; /* 0x0F */
2380 U32 AttachedPhyInfo; /* 0x10 */
2381 U8 ProgrammedLinkRate; /* 0x14 */
2382 U8 HwLinkRate; /* 0x15 */
2383 U8 ChangeCount; /* 0x16 */
2384 U8 Flags; /* 0x17 */
2385 U32 PhyInfo; /* 0x18 */
2386 U8 NegotiatedLinkRate; /* 0x1C */
2387 U8 Reserved3; /* 0x1D */
2388 U16 Reserved4; /* 0x1E */
2389 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2390 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2391
2392 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2393
2394 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2395
2396 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2397
2398 /* values for SAS PHY Page 0 Flags field */
2399 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2400
2401 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2402
2403 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2404
2405 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2406
2407
2408 /* SAS PHY Page 1 */
2409
2410 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2411 {
2412 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2413 U32 Reserved1; /* 0x08 */
2414 U32 InvalidDwordCount; /* 0x0C */
2415 U32 RunningDisparityErrorCount; /* 0x10 */
2416 U32 LossDwordSynchCount; /* 0x14 */
2417 U32 PhyResetProblemCount; /* 0x18 */
2418 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2419 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2420
2421 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2422
2423
2424 /* SAS PHY Page 2 */
2425
2426 typedef struct _MPI2_SASPHY2_PHY_EVENT
2427 {
2428 U8 PhyEventCode; /* 0x00 */
2429 U8 Reserved1; /* 0x01 */
2430 U16 Reserved2; /* 0x02 */
2431 U32 PhyEventInfo; /* 0x04 */
2432 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2433 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2434
2435 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2436
2437
2438 /*
2439 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2440 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2441 */
2442 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2443 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2444 #endif
2445
2446 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2
2447 {
2448 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2449 U32 Reserved1; /* 0x08 */
2450 U8 NumPhyEvents; /* 0x0C */
2451 U8 Reserved2; /* 0x0D */
2452 U16 Reserved3; /* 0x0E */
2453 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
2454 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2455 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2456
2457 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2458
2459
2460 /* SAS PHY Page 3 */
2461
2462 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG
2463 {
2464 U8 PhyEventCode; /* 0x00 */
2465 U8 Reserved1; /* 0x01 */
2466 U16 Reserved2; /* 0x02 */
2467 U8 CounterType; /* 0x04 */
2468 U8 ThresholdWindow; /* 0x05 */
2469 U8 TimeUnits; /* 0x06 */
2470 U8 Reserved3; /* 0x07 */
2471 U32 EventThreshold; /* 0x08 */
2472 U16 ThresholdFlags; /* 0x0C */
2473 U16 Reserved4; /* 0x0E */
2474 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2475 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2476
2477 /* values for PhyEventCode field */
2478 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2479 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2480 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2481 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2482 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2483 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2484 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2485 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2486 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2487 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2488 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2489 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2490 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2491 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2492 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2493 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2494 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2495 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2496 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2497 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2498 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2499 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2500 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2501 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2502 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2503 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2504 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2505 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2506 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2507 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2508 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2509 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2510 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2511 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2512 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2513 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2514 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2515
2516 /* values for the CounterType field */
2517 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2518 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2519 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2520
2521 /* values for the TimeUnits field */
2522 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2523 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2524 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2525 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2526
2527 /* values for the ThresholdFlags field */
2528 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2529 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2530
2531 /*
2532 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2533 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2534 */
2535 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2536 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2537 #endif
2538
2539 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
2540 {
2541 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2542 U32 Reserved1; /* 0x08 */
2543 U8 NumPhyEvents; /* 0x0C */
2544 U8 Reserved2; /* 0x0D */
2545 U16 Reserved3; /* 0x0E */
2546 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2547 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2548 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2549
2550 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2551
2552
2553 /* SAS PHY Page 4 */
2554
2555 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4
2556 {
2557 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2558 U16 Reserved1; /* 0x08 */
2559 U8 Reserved2; /* 0x0A */
2560 U8 Flags; /* 0x0B */
2561 U8 InitialFrame[28]; /* 0x0C */
2562 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2563 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2564
2565 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2566
2567 /* values for the Flags field */
2568 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2569 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2570
2571
2572
2573
2574 /****************************************************************************
2575 * SAS Port Config Pages
2576 ****************************************************************************/
2577
2578 /* SAS Port Page 0 */
2579
2580 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2581 {
2582 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2583 U8 PortNumber; /* 0x08 */
2584 U8 PhysicalPort; /* 0x09 */
2585 U8 PortWidth; /* 0x0A */
2586 U8 PhysicalPortWidth; /* 0x0B */
2587 U8 ZoneGroup; /* 0x0C */
2588 U8 Reserved1; /* 0x0D */
2589 U16 Reserved2; /* 0x0E */
2590 U64 SASAddress; /* 0x10 */
2591 U32 DeviceInfo; /* 0x18 */
2592 U32 Reserved3; /* 0x1C */
2593 U32 Reserved4; /* 0x20 */
2594 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2595 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2596
2597 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2598
2599 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2600
2601
2602 /****************************************************************************
2603 * SAS Enclosure Config Pages
2604 ****************************************************************************/
2605
2606 /* SAS Enclosure Page 0 */
2607
2608 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2609 {
2610 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2611 U32 Reserved1; /* 0x08 */
2612 U64 EnclosureLogicalID; /* 0x0C */
2613 U16 Flags; /* 0x14 */
2614 U16 EnclosureHandle; /* 0x16 */
2615 U16 NumSlots; /* 0x18 */
2616 U16 StartSlot; /* 0x1A */
2617 U16 Reserved2; /* 0x1C */
2618 U16 SEPDevHandle; /* 0x1E */
2619 U32 Reserved3; /* 0x20 */
2620 U32 Reserved4; /* 0x24 */
2621 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2622 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2623 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2624
2625 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2626
2627 /* values for SAS Enclosure Page 0 Flags field */
2628 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2629 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2630 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2631 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2632 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2633 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2634 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2635
2636
2637 /****************************************************************************
2638 * Log Config Page
2639 ****************************************************************************/
2640
2641 /* Log Page 0 */
2642
2643 /*
2644 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2645 * one and check Header.ExtPageLength or NumPhys at runtime.
2646 */
2647 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2648 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2649 #endif
2650
2651 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2652
2653 typedef struct _MPI2_LOG_0_ENTRY
2654 {
2655 U64 TimeStamp; /* 0x00 */
2656 U32 Reserved1; /* 0x08 */
2657 U16 LogSequence; /* 0x0C */
2658 U16 LogEntryQualifier; /* 0x0E */
2659 U8 VP_ID; /* 0x10 */
2660 U8 VF_ID; /* 0x11 */
2661 U16 Reserved2; /* 0x12 */
2662 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2663 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2664 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2665
2666 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2667 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2668 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2669 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2670 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2671 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2672
2673 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2674 {
2675 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2676 U32 Reserved1; /* 0x08 */
2677 U32 Reserved2; /* 0x0C */
2678 U16 NumLogEntries; /* 0x10 */
2679 U16 Reserved3; /* 0x12 */
2680 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2681 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2682 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2683
2684 #define MPI2_LOG_0_PAGEVERSION (0x02)
2685
2686
2687 /****************************************************************************
2688 * RAID Config Page
2689 ****************************************************************************/
2690
2691 /* RAID Page 0 */
2692
2693 /*
2694 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2695 * one and check Header.ExtPageLength or NumPhys at runtime.
2696 */
2697 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2698 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2699 #endif
2700
2701 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2702 {
2703 U16 ElementFlags; /* 0x00 */
2704 U16 VolDevHandle; /* 0x02 */
2705 U8 HotSparePool; /* 0x04 */
2706 U8 PhysDiskNum; /* 0x05 */
2707 U16 PhysDiskDevHandle; /* 0x06 */
2708 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2709 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2710 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2711
2712 /* values for the ElementFlags field */
2713 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2714 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2715 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2716 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2717 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2718
2719
2720 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2721 {
2722 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2723 U8 NumHotSpares; /* 0x08 */
2724 U8 NumPhysDisks; /* 0x09 */
2725 U8 NumVolumes; /* 0x0A */
2726 U8 ConfigNum; /* 0x0B */
2727 U32 Flags; /* 0x0C */
2728 U8 ConfigGUID[24]; /* 0x10 */
2729 U32 Reserved1; /* 0x28 */
2730 U8 NumElements; /* 0x2C */
2731 U8 Reserved2; /* 0x2D */
2732 U16 Reserved3; /* 0x2E */
2733 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2734 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2735 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2736 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2737
2738 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2739
2740 /* values for RAID Configuration Page 0 Flags field */
2741 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2742
2743
2744 /****************************************************************************
2745 * Driver Persistent Mapping Config Pages
2746 ****************************************************************************/
2747
2748 /* Driver Persistent Mapping Page 0 */
2749
2750 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2751 {
2752 U64 PhysicalIdentifier; /* 0x00 */
2753 U16 MappingInformation; /* 0x08 */
2754 U16 DeviceIndex; /* 0x0A */
2755 U32 PhysicalBitsMapping; /* 0x0C */
2756 U32 Reserved1; /* 0x10 */
2757 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2758 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2759 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2760
2761 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2762 {
2763 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2764 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2765 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2766 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2767 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2768
2769 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2770
2771 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2772 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2773 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2774 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2775
2776
2777 /****************************************************************************
2778 * Ethernet Config Pages
2779 ****************************************************************************/
2780
2781 /* Ethernet Page 0 */
2782
2783 /* IP address (union of IPv4 and IPv6) */
2784 typedef union _MPI2_ETHERNET_IP_ADDR
2785 {
2786 U32 IPv4Addr;
2787 U32 IPv6Addr[4];
2788 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2789 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2790
2791 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2792
2793 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0
2794 {
2795 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2796 U8 NumInterfaces; /* 0x08 */
2797 U8 Reserved0; /* 0x09 */
2798 U16 Reserved1; /* 0x0A */
2799 U32 Status; /* 0x0C */
2800 U8 MediaState; /* 0x10 */
2801 U8 Reserved2; /* 0x11 */
2802 U16 Reserved3; /* 0x12 */
2803 U8 MacAddress[6]; /* 0x14 */
2804 U8 Reserved4; /* 0x1A */
2805 U8 Reserved5; /* 0x1B */
2806 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2807 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2808 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2809 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2810 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2811 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2812 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2813 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2814 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2815
2816 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2817
2818 /* values for Ethernet Page 0 Status field */
2819 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2820 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2821 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2822 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2823 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2824 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2825 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2826 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2827 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2828 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2829 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2830 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2831
2832 /* values for Ethernet Page 0 MediaState field */
2833 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2834 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2835 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2836
2837 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2838 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2839 #define MPI2_ETHPG0_MS_10MBIT (0x01)
2840 #define MPI2_ETHPG0_MS_100MBIT (0x02)
2841 #define MPI2_ETHPG0_MS_1GBIT (0x03)
2842
2843
2844 /* Ethernet Page 1 */
2845
2846 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1
2847 {
2848 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2849 U32 Reserved0; /* 0x08 */
2850 U32 Flags; /* 0x0C */
2851 U8 MediaState; /* 0x10 */
2852 U8 Reserved1; /* 0x11 */
2853 U16 Reserved2; /* 0x12 */
2854 U8 MacAddress[6]; /* 0x14 */
2855 U8 Reserved3; /* 0x1A */
2856 U8 Reserved4; /* 0x1B */
2857 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2858 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2859 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2860 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2861 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2862 U32 Reserved5; /* 0x6C */
2863 U32 Reserved6; /* 0x70 */
2864 U32 Reserved7; /* 0x74 */
2865 U32 Reserved8; /* 0x78 */
2866 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2867 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2868 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2869
2870 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2871
2872 /* values for Ethernet Page 1 Flags field */
2873 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2874 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2875 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2876 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2877 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2878 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2879 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2880 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2881 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2882
2883 /* values for Ethernet Page 1 MediaState field */
2884 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2885 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2886 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2887
2888 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2889 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2890 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2891 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2892 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2893
2894
2895 /****************************************************************************
2896 * Extended Manufacturing Config Pages
2897 ****************************************************************************/
2898
2899 /*
2900 * Generic structure to use for product-specific extended manufacturing pages
2901 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
2902 * Page 60).
2903 */
2904
2905 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS
2906 {
2907 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2908 U32 ProductSpecificInfo; /* 0x08 */
2909 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
2910 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
2911 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
2912
2913 /* PageVersion should be provided by product-specific code */
2914
2915 #endif
2916